The LatticeMico32 direct memory access controller (DMA) provides a master read port, a master write port, and a slave port to control data transmission.
*If the data sheet fails to open, see the note at the bottom of this page.
|
Version |
Description |
|
3.1 (8.0) |
DMA Engine upgraded to comply with Rule 3.100 of Wishbone Specifications, which deal with byte alignment for transfers that are less than the width of Wishbone data bus. |
|
3.0 (7.0 SP2) |
Because the read and write channel worked in parallel, the write channel started writing data to the slave as soon as the FIFO is not empty. Increased burst size to support bigger bursts from a current value of 4 and 8 to 16 and 32, respectively. DMA now supports four burst sizes: 4, 8, 16, and 32. The Burst Size field of the control register was increased to 2 bits. A glitch was removed on the S_ACK_O signal. |
|
1.0 |
Initial release. |
|
Parameter |
Description |
|
Instance Name |
Specifies the name of the DMA controller instance. Alphanumeric values and underscores are supported. The default is dma. |
|
Base Address |
Specifies the base address for accessing the internal registers. The minimum boundary alignment is 0X80. Supported values are 0X80000000 to 0XFFFFFFFF. The default is 0X80000000. |
|
FIFO Implementation |
Determines whether the FIFO is implemented as an EBR or a LUT. The default is EBR. |
|
Length Width |
Specifies the number of bits in the length register. The length register holds a count value that determines the number of DMA transactions to be performed. Supported values are 1 to 32. The default is 16. The default value permits up to 65535 (0XFFFF) memory transactions to be performed. |
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