Fri, 13 Aug 2010 10:43:05 +0100
Initial commit, DMAC version 3.1
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114 <h1>LatticeMico32 DMA Controller <a title="View Data Sheet" href="dma.pdf" target="_blank" onmouseover="if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) ehlp_showtip(this,event,'View Data Sheet');" onmouseout="if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) ehlp_hidetip();"><img src="ds_icon_ast.jpg" x-maintain-ratio="TRUE" width="29px" height="31px" border="0" class="img_whs1"></a></h1>
116 <p>The LatticeMico32 direct memory access controller (DMA) provides a master
117 read port, a master write port, and a slave port to control data transmission.
118 </p>
120 <p class="whs2"><span style="font-style: italic;"><I>*If the
121 data sheet fails to open, see the note at the bottom of this page.</I></span></p>
123 <h2>Revision History </h2>
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129 <col class="whs4">
130 <col class="whs5">
132 <tr valign="top" class="whs6">
133 <td bgcolor="#DEE8F4" width="86px" class="whs7">
134 <p class=Table
135 style="font-weight: bold;">Version</td>
136 <td bgcolor="#DEE8F4" width="504px" class="whs8">
137 <p class=Table
138 style="font-weight: bold;">Description</td></tr>
140 <tr valign="top" class="whs6">
141 <td colspan="1" rowspan="1" width="86px" class="whs9">
142 <p class=Table
143 style="font-weight: normal;">3.1 (8.0)</td>
144 <td colspan="1" rowspan="1" width="504px" class="whs10">
145 <p class=Table>DMA Engine upgraded to comply with Rule 3.100 of Wishbone
146 Specifications, which deal with byte alignment for transfers that are
147 less than the width of Wishbone data bus.</td></tr>
149 <tr valign="top" class="whs6">
150 <td colspan="1" rowspan="1" width="86px" class="whs9">
151 <p class=Table
152 style="font-weight: normal;"><span style="font-weight: normal;">3.0
153 (7.0 SP2)</span></td>
154 <td colspan="1" rowspan="1" width="504px" class="whs10">
155 <p class=Table>Because the read and write channel worked in parallel, the
156 write channel started writing data to the slave as soon as the FIFO is
157 not empty.</p>
158 <p class=Table>Increased burst size to support bigger bursts from a current
159 value of 4 and 8 to 16 and 32, respectively. DMA now supports four burst
160 sizes: 4, 8, 16, and 32. The Burst Size field of the control register
161 was increased to 2 bits.</p>
162 <p class=Table>A glitch was removed on the S_ACK_O signal.</td></tr>
164 <tr valign="top" class="whs6">
165 <td colspan="1" rowspan="1" width="86px" class="whs9">
166 <p class="whs11">1.0</td>
167 <td colspan="1" rowspan="1" width="504px" class="whs10">
168 <p class=Table>Initial release.</td></tr>
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172 </table>
174
176 <h2>Dialog Box Parameters</h2>
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182 <col>
183 <col>
185 <tr valign="top" class="whs13">
186 <td bgcolor="#DEE8F4" class="whs14">
187 <p class=Table
188 style="font-weight: bold; margin-right: 2px;">Parameter</td>
189 <td bgcolor="#DEE8F4" class="whs15">
190 <p class=Table
191 style="font-weight: bold;">Description</td></tr>
193 <tr valign="top" class="whs13">
194 <td colspan="1" rowspan="1" class="whs16">
195 <p class=Table
196 style="margin-right: 2px;">Instance Name</td>
197 <td colspan="1" rowspan="1" class="whs17">
198 <p class=Table>Specifies the name of the DMA controller instance. Alphanumeric
199 values and underscores are supported. The default is dma.</td></tr>
201 <tr valign="top" class="whs13">
202 <td colspan="1" rowspan="1" class="whs16">
203 <p class=Table
204 style="margin-right: 2px;">Base Address</td>
205 <td colspan="1" rowspan="1" class="whs17">
206 <p class=Table>Specifies the base address for accessing the internal registers.
207 The minimum boundary alignment is 0X80. Supported values are 0X80000000
208 to 0XFFFFFFFF. The default is 0X80000000.</td></tr>
210 <tr valign="top" class="whs13">
211 <td colspan="1" rowspan="1" class="whs18">
212 <p class=Table
213 style="margin-right: 2px;">FIFO Implementation</td>
214 <td colspan="1" rowspan="1" class="whs19">
215 <p class=Table>Determines whether the FIFO is implemented as an EBR or
216 a LUT. The default is EBR.</td></tr>
218 <tr valign="top" class="whs13">
219 <td colspan="1" rowspan="1" class="whs18">
220 <p class=Table
221 style="margin-right: 2px;">Length Width</td>
222 <td colspan="1" rowspan="1" class="whs19">
223 <p class=Table>Specifies the number of bits in the length register. The
224 length register holds a count value that determines the number of DMA
225 transactions to be performed. Supported values are 1 to 32. The default
226 is 16. The default value permits up to 65535 (0XFFFF) memory transactions
227 to be performed.</td></tr>
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233
235 <p><span style="font-weight: bold;"><B>Note</B></span>: If the data sheet fails
236 to open, click <img src="qm_icon.jpg" x-maintain-ratio="TRUE" width="14px" height="16px" border="0" class="img_whs20"> on the Available Components toolbar, and
237 then click the note button.</p>
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