Sat, 06 Aug 2011 01:48:48 +0100
Update to LM32 DMA v3.3
+// Version : 3.2
+// : 1. Support for 8/32-bit WISHBONE Data Bus. The Control and
+// : Read/Write Ports can be independently configured.
+// : 2. Support for "retry" on receipt of a WISHBONE RTY. This
+// : retry results in the current burst or classic cycle
+// : being issued again after a retry timeout.
+// : 3. Support for "error" on receipt of a WISHBONE ERR. This
+// : results in the current dma transfer being terminated
+// : and the error is updated within the STATUS CSR.
+// : 4. Support for burst size of 64.
+// :
+// Version : 3.3
+// : Support for MachXO2 added. The MachXO2 only has a FIFO
+// : with separate read/write clocks.
1.1 --- a/dma.xml Fri Aug 13 10:43:05 2010 +0100 1.2 +++ b/dma.xml Sat Aug 06 01:48:48 2011 +0100 1.3 @@ -1,9 +1,9 @@ 1.4 <?xml version="1.0" encoding="UTF-8"?> 1.5 -<Component Name="wb_dma_ctrl" Text="DMA" Type="IO" Ver="3.1" Help="wb_dma_ctrl\document\dma.htm"> 1.6 +<Component Name="wb_dma_ctrl" Text="DMA" Type="IO" Ver="3.3" Help="wb_dma_ctrl\document\dma.htm" Processor="LM32,LM8" LatticeFamily="All" Device="All"> 1.7 <MasterSlavePorts> 1.8 - <MasterPort Prefix="MA" Name="Read Master Port" Type="DMAR" Priority="2" /> 1.9 - <MasterPort Prefix="MB" Name="Write Master Port" Type="DMAW" Priority="3"/> 1.10 - <SlavePort Prefix="S" Name="Control Port" Type="DATA"/> 1.11 + <MasterPort Prefix="MA" Port="MA" Name="Read Master Port" Type="DMAR" Priority="2"/> 1.12 + <MasterPort Prefix="MB" Port="MB" Name="Write Master Port" Type="DMAW" Priority="3"/> 1.13 + <SlavePort Prefix="S" Port="S" Name="Control Port" Type="DATA"/> 1.14 </MasterSlavePorts> 1.15 <ClockPort Name="CLK_I " Description="Clock one"/> 1.16 <ResetPort Name="RST_I " Description="Reset"/> 1.17 @@ -14,18 +14,24 @@ 1.18 <File Name="../components/wb_dma_ctrl/rtl/verilog/wb_dma_ctrl.v" /> 1.19 </Files> 1.20 <DeviceDriver InitRoutine="MicoDMAInit" StructName="MicoDMACtx_t"> 1.21 - <DDInclude Include="LookupServices.h"/> 1.22 + <DDInclude Include="LookupServices.h" Processor="LM32"/> 1.23 + <DDInclude Include="stddef.h" Processor="LM8"/> 1.24 + <DDIRQ IRQAPI="MicoDMAISR" Parameter="InstanceName" Include="MicoDMA.h" Processor="LM8"/> 1.25 + <DDPreProcessor Name="__MICODMA_USER_IRQ_HANDLER__" Processor="LM8"/> 1.26 <DDstruct> 1.27 - <DDSElem MemberName = "name" MemberType = "const char*" Type = "Parm" Value = "InstanceName" Format="string"/> 1.28 - <DDSElem MemberName = "base" MemberType = "unsigned int" Type = "Parm" Value = "BASE_ADDRESS" /> 1.29 - <DDSElem MemberName = "lookupReg" MemberType = "DeviceReg_t" Type = "uninitialized" Value=""/> 1.30 - <DDSElem MemberName = "irq" MemberType = "unsigned int" Type = "Interrupt" Value = "IRQ_LEVEL" /> 1.31 - <DDSElem MemberName = "maxLength" MemberType = "unsigned int" Type = "Parm" Value = "LENGTH_WIDTH" /> 1.32 - <DDSElem MemberName = "flags" MemberType = "unsigned int" Type = "uninitialized" Value = "" /> 1.33 - <DDSElem MemberName = "pCurr" MemberType = "void *" Type = "uninitialized" Value = "" /> 1.34 - <DDSElem MemberName = "pHead" MemberType = "void *" Type = "uninitialized" Value = "" /> 1.35 - <DDSElem MemberName = "prev" MemberType = "void *" Type = "uninitialized" Value = "" /> 1.36 - <DDSElem MemberName = "next" MemberType = "void *" Type = "uninitialized" Value = "" /> 1.37 + <DDSElem MemberName="name" MemberType="const char*" Type = "Parm" Value="InstanceName" Format="string" Processor="LM32,LM8"/> 1.38 + <DDSElem MemberName="base" MemberType="unsigned int" Type="Parm" Value="BASE_ADDRESS" Port="S" Processor="LM32"/> 1.39 + <DDSElem MemberName="base" MemberType="size_t" Type="Parm" Value="BASE_ADDRESS" Port="S" Processor="LM8"/> 1.40 + <DDSElem MemberName="wb" MemberType="unsigned char" Type="Parm" Value="WB_DAT_WIDTH" Port="S"/> 1.41 + <DDSElem MemberName="lookupReg" MemberType="DeviceReg_t" Type="uninitialized" Value="" Processor="LM32"/> 1.42 + <DDSElem MemberName="irq" MemberType="unsigned int" Type="Interrupt" Value="IRQ_LEVEL" Processor="LM32"/> 1.43 + <DDSElem MemberName="irq" MemberType="unsigned char" Type="Interrupt" Value="IRQ_LEVEL" Processor="LM8"/> 1.44 + <DDSElem MemberName="maxLength" MemberType="unsigned int" Type="Parm" Value="LENGTH_WIDTH" Processor="LM32"/> 1.45 + <DDSElem MemberName="flags" MemberType="unsigned int" Type="uninitialized" Value="" Processor="LM32"/> 1.46 + <DDSElem MemberName="pCurr" MemberType="void *" Type="uninitialized" Value="" Processor="LM32"/> 1.47 + <DDSElem MemberName="pHead" MemberType="void *" Type="uninitialized" Value="" Processor="LM32"/> 1.48 + <DDSElem MemberName="prev" MemberType="void *" Type="uninitialized" Value="" Processor="LM32"/> 1.49 + <DDSElem MemberName="next" MemberType="void *" Type="uninitialized" Value="" Processor="LM32"/> 1.50 </DDstruct> 1.51 </DeviceDriver> 1.52 <PMIDef> 1.53 @@ -33,20 +39,30 @@ 1.54 <Module Name="pmi_fifo_dc" /> 1.55 </PMIDef> 1.56 <Parms> 1.57 - <Parm Name="InstanceName" Value="dma" Type="string" isiname="true" Text="Instance Name"/> 1.58 - <Parm Name="BASE_ADDRESS" Value="0x80000000" Type="Integer" isba="true" Text="Base Address"/> 1.59 - <Parm Name="FIFO_IMPLEMENTATION" Value="EBR" Type="String" ListValues="EBR,LUT" Text="FIFO Implementation" isparm="true"/> 1.60 - <Parm Name="SIZE" Value="128" Type="Integer" issize="true" Text="Size" Enable="false"/> 1.61 - <Parm Name="DISABLE" Type="define" Value="undef" isdisable="true" Text="Disable Component"/> 1.62 - <Parm Name="ADDRESS_LOCK" Type="Define" Value="undef" Text="Lock Address "/> 1.63 - <Parm Name="LENGTH_WIDTH" Value="16" Type="Integer" ValueRange="1-32" Text="Length Width" isparm="true"/> 1.64 + <Parm Name="InstanceName" Value="dma" Type="string" isiname="true" Text="Instance Name"/> 1.65 + <Parm Name="BASE_ADDRESS" Port="S" Value="0x80000000" Type="Integer" isba="true" Text="Base Address"/> 1.66 + <Parm Name="FIFO_IMPLEMENTATION" Value="EBR" Type="String" ListValues="EBR,LUT" Text="FIFO Implementation" isparm="true"/> 1.67 + <Parm Name="SIZE" Port="S" Value="128" Type="Integer" issize="true" Text="Size" Enable="false"/> 1.68 + <Parm Name="DISABLE" Value="undef" Type="define" isdisable="true" Text="Disable Component"/> 1.69 + <Parm Name="ADDRESS_LOCK" Value="undef" Type="Define" Text="Lock Address "/> 1.70 + <Parm Name="RETRY_TIMEOUT" Value="16" Type="Integer" ValueRange="1-255" Text="Retry Timeout" isparm="true"/> 1.71 + <Parm Name="LENGTH_WIDTH" Value="32" Type="Integer" ValueRange="1-32" Text="Length Width" isparm="false"/> 1.72 + <Parm Name="WB_DAT_WIDTH" Port="S" Value="32" Type="List" ListValues="8,32" OType="Integer" Text="Control Port Data Bus Width" isparm="true"/> 1.73 + <Parm Name="WB_ADR_WIDTH" Port="S" Value="32" Type="Integer" OType="Integer" Text="WISHBONE Address Bus Width" isparm="true"/> 1.74 + <Parm Name="WB_DAT_WIDTH" Port="MA" Value="32" Type="List" ListValues="8,32" OType="Integer" Text="Read/Write Ports Data Bus Width" isparm="true" SetValTo="MB"/> 1.75 + <Parm Name="WB_ADR_WIDTH" Port="MA" Value="32" Type="Integer" OType="Integer" Text="WISHBONE Address Bus Width" isparm="true"/> 1.76 + <Parm Name="WB_DAT_WIDTH" Port="MB" Value="32" Type="List" ListValues="8,32" OType="Integer" Text="WISHBONE Data Bus Width" isparm="true"/> 1.77 + <Parm Name="WB_ADR_WIDTH" Port="MB" Value="32" Type="Integer" OType="Integer" Text="WISHBONE Address Bus Width" isparm="true"/> 1.78 </Parms> 1.79 <GUIS Columns="2" Help="document\dma.htm" Name="WB_DMA_CTRL"> 1.80 <GUI Widget="Text" Span="1" Name="InstanceName" Width="40"/> 1.81 - <GUI Widget="Text" Span="1" Name="BASE_ADDRESS"/> 1.82 + <GUI Widget="Text" Span="1" Name="BASE_ADDRESS" Port="S"/> 1.83 <GUI Widget="Combo" Span="1" Name="FIFO_IMPLEMENTATION"/> 1.84 <GUI Widget="Group" Span="2" Name="SETTINGS" Text="Settings" Columns="3"/> 1.85 <GUI Widget="Label" Span="1" Name=""/> 1.86 - <GUI Widget="Spinner" Span="1" Name="LENGTH_WIDTH"/> 1.87 + <GUI Widget="Spinner" Span="1" Name="RETRY_TIMEOUT"/> 1.88 + <GUI Widget="Group" Span="2" Text="WISHBONE Configuration" Columns="2"/> 1.89 + <GUI Widget="Combo" Span="1" Name="WB_DAT_WIDTH" Port="S"/> 1.90 + <GUI Widget="Combo" Span="1" Name="WB_DAT_WIDTH" Port="MA"/> 1.91 </GUIS> 1.92 </Component>
2.1 --- a/document/dma.htm Fri Aug 13 10:43:05 2010 +0100 2.2 +++ b/document/dma.htm Sat Aug 06 01:48:48 2011 +0100 2.3 @@ -111,9 +111,9 @@ 2.4 writeIntopicBar(4); 2.5 //--> 2.6 </script> 2.7 -<h1>LatticeMico32 DMA Controller <a title="View Data Sheet" href="dma.pdf" target="_blank" onmouseover="if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) ehlp_showtip(this,event,'View Data Sheet');" onmouseout="if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) ehlp_hidetip();"><img src="ds_icon_ast.jpg" x-maintain-ratio="TRUE" width="29px" height="31px" border="0" class="img_whs1"></a></h1> 2.8 +<h1>LatticeMico DMA Controller <a title="View Data Sheet" href="dma.pdf" target="_blank" onmouseover="if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) ehlp_showtip(this,event,'View Data Sheet');" onmouseout="if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) ehlp_hidetip();"><img src="ds_icon_ast.jpg" x-maintain-ratio="TRUE" width="29px" height="31px" border="0" class="img_whs1"></a></h1> 2.9 2.10 -<p>The LatticeMico32 direct memory access controller (DMA) provides a master 2.11 +<p>The LatticeMico direct memory access controller (DMA) provides a master 2.12 read port, a master write port, and a slave port to control data transmission. 2.13 </p> 2.14 2.15 @@ -140,6 +140,23 @@ 2.16 <tr valign="top" class="whs6"> 2.17 <td colspan="1" rowspan="1" width="86px" class="whs9"> 2.18 <p class=Table 2.19 + style="font-weight: normal;">3.3</td> 2.20 +<td colspan="1" rowspan="1" width="504px" class="whs10"> 2.21 +<p class=Table>Added software support for LatticeMico8.</td></tr> 2.22 + 2.23 +<tr valign="top" class="whs6"> 2.24 +<td colspan="1" rowspan="1" width="86px" class="whs9"> 2.25 +<p class=Table 2.26 + style="font-weight: normal;">3.2 (8.1 SP1)</td> 2.27 +<td colspan="1" rowspan="1" width="504px" class="whs10"> 2.28 +<p class=Table>The data busses on the three WISHBONE interfaces can be 2.29 + configured to be 8 or 32 bits. Support added for handling WISHBONE RTY 2.30 + (retry) for burst transfers. Support added for handling WISHBONE ERR (error). 2.31 + Register map updated to support 8-bit and 32-bit WISHBONE data bus.</td></tr> 2.32 + 2.33 +<tr valign="top" class="whs6"> 2.34 +<td colspan="1" rowspan="1" width="86px" class="whs9"> 2.35 +<p class=Table 2.36 style="font-weight: normal;">3.1 (8.0)</td> 2.37 <td colspan="1" rowspan="1" width="504px" class="whs10"> 2.38 <p class=Table>DMA Engine upgraded to comply with Rule 3.100 of Wishbone 2.39 @@ -176,9 +193,6 @@ 2.40 <h2>Dialog Box Parameters</h2> 2.41 2.42 <table x-use-null-cells cellspacing="0" class="whs12"> 2.43 -<script language='JavaScript'><!-- 2.44 -if ((navigator.appName == "Netscape") && (parseInt(navigator.appVersion) == 4)) document.write("</table><table x-use-null-cells cellspacing='0' border='1' bordercolor='silver' bordercolorlight='silver' bordercolordark='silver'>"); 2.45 -//--></script> 2.46 <col> 2.47 <col> 2.48 2.49 @@ -218,16 +232,34 @@ 2.50 <tr valign="top" class="whs13"> 2.51 <td colspan="1" rowspan="1" class="whs18"> 2.52 <p class=Table 2.53 - style="margin-right: 2px;">Length Width</td> 2.54 + style="margin-right: 2px;">Retry Timeout</p> 2.55 +<p class=table> </td> 2.56 <td colspan="1" rowspan="1" class="whs19"> 2.57 -<p class=Table>Specifies the number of bits in the length register. The 2.58 - length register holds a count value that determines the number of DMA 2.59 - transactions to be performed. Supported values are 1 to 32. The default 2.60 - is 16. The default value permits up to 65535 (0XFFFF) memory transactions 2.61 - to be performed.</td></tr> 2.62 -<script language='JavaScript'><!-- 2.63 -if ((navigator.appName == "Netscape") && (parseInt(navigator.appVersion) == 4)) document.write("</table></table><table>"); 2.64 -//--></script> 2.65 +<p class=Table>Specifies the number of WISHBONE clock cycles that the DMA 2.66 + controller must wait after the source or destination asserts the WISHBONE 2.67 + RTY before retrying the same WISHBONE cycle. Supported 2.68 + values are 1 to 255. The default is 16. </p> 2.69 +<p class=table> </td></tr> 2.70 + 2.71 +<tr valign="top" class="whs13"> 2.72 +<td colspan="2" rowspan="1" class="whs18"> 2.73 +<p class=Table 2.74 + style="font-weight: bold;">WISHBONE Configuration</td> 2.75 +</tr> 2.76 + 2.77 +<tr valign="top" class="whs13"> 2.78 +<td colspan="1" rowspan="1" class="whs18"> 2.79 +<p class=Table>Control Port Data Bus Width</td> 2.80 +<td colspan="1" rowspan="1" class="whs19"> 2.81 +<p class=Table>Configures the control port's WISHBONE data bus to be 8 2.82 + or 32 bits wide.</td></tr> 2.83 + 2.84 +<tr valign="top" class="whs13"> 2.85 +<td colspan="1" rowspan="1" class="whs18"> 2.86 +<p class=Table>Read/Write Port Data Bus Width</td> 2.87 +<td colspan="1" rowspan="1" class="whs19"> 2.88 +<p class=Table>Configures the read and write WISHBONE master port data 2.89 + buses to be 8 or 32 bits wide.</td></tr> 2.90 </table> 2.91 2.92
3.1 Binary file document/dma.pdf has changed
4.1 --- a/drivers/peripheral.mk Fri Aug 13 10:43:05 2010 +0100 4.2 +++ b/drivers/peripheral.mk Sat Aug 06 01:48:48 2011 +0100 4.3 @@ -2,8 +2,7 @@ 4.4 # Identify source-paths for this device's driver-sources, 4.5 # compiled when building the library 4.6 #--------------------------------------------------------- 4.7 -LIBRARY_C_SRCS += MicoDMA.c \ 4.8 - MicoDMAService.c 4.9 +LIBRARY_C_SRCS += 4.10 LIBRARY_ASM_SRCS += 4.11 4.12
5.1 --- a/rtl/verilog/master_ctrl.v Fri Aug 13 10:43:05 2010 +0100 5.2 +++ b/rtl/verilog/master_ctrl.v Sat Aug 06 01:48:48 2011 +0100 5.3 @@ -1,1188 +1,902 @@ 5.4 -// ============================================================================= 5.5 -// COPYRIGHT NOTICE 5.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation 5.7 -// ALL RIGHTS RESERVED 5.8 -// This confidential and proprietary software may be used only as authorised by 5.9 -// a licensing agreement from Lattice Semiconductor Corporation. 5.10 -// The entire notice above must be reproduced on all authorized copies and 5.11 -// copies may only be made to the extent permitted by a licensing agreement from 5.12 -// Lattice Semiconductor Corporation. 5.13 +// ================================================================== 5.14 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 5.15 +// ------------------------------------------------------------------ 5.16 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 5.17 +// ALL RIGHTS RESERVED 5.18 +// ------------------------------------------------------------------ 5.19 +// 5.20 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 5.21 +// 5.22 +// Permission: 5.23 +// 5.24 +// Lattice Semiconductor grants permission to use this code 5.25 +// pursuant to the terms of the Lattice Semiconductor Corporation 5.26 +// Open Source License Agreement. 5.27 +// 5.28 +// Disclaimer: 5.29 // 5.30 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 5.31 -// 5555 NE Moore Court 408-826-6000 (other locations) 5.32 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 5.33 -// U.S.A email: techsupport@latticesemi.com 5.34 -// =============================================================================/ 5.35 +// Lattice Semiconductor provides no warranty regarding the use or 5.36 +// functionality of this code. It is the user's responsibility to 5.37 +// verify the user’s design for consistency and functionality through 5.38 +// the use of formal verification methods. 5.39 +// 5.40 +// -------------------------------------------------------------------- 5.41 +// 5.42 +// Lattice Semiconductor Corporation 5.43 +// 5555 NE Moore Court 5.44 +// Hillsboro, OR 97214 5.45 +// U.S.A 5.46 +// 5.47 +// TEL: 1-800-Lattice (USA and Canada) 5.48 +// 503-286-8001 (other locations) 5.49 +// 5.50 +// web: http://www.latticesemi.com/ 5.51 +// email: techsupport@latticesemi.com 5.52 +// 5.53 +// -------------------------------------------------------------------- 5.54 // FILE DETAILS 5.55 // Project : LM32 DMA Component 5.56 -// File : master_ctrl.v 5.57 -// Title : DMA Master controller 5.58 +// File : wb_dma_ctrl.v 5.59 +// Title : DMA controller top file 5.60 // Dependencies : None 5.61 -// 5.62 -// Version 3.1 5.63 -// 1. Make DMA Engine compliant to Rule 3.100 of Wishbone Spec which defines 5.64 -// alignement of bytes in sub-word transfers. 5.65 -// 2. Removed glitch that did not pause the burst write when the read burst 5.66 -// was paused by the "read slave". 5.67 -// 5.68 -// Version 7.0SP2, 3.0 5.69 -// 1. Read and Write channel of DMA controller are working in parallel, 5.70 -// due to that now as soon as FIFO is not empty write channel of the DMA 5.71 -// controller start writing data to the slave. 5.72 -// 2. Burst Size supported by DMA controller is increased to support bigger 5.73 -// burst (from current value of 4 and 8 to 16 and 32). Now 4 different type 5.74 -// of burst sizes are supported by the DMA controller 4, 8, 16 and 32. 5.75 -// For this Burst Size field of the control register is increased to 2 bits. 5.76 -// 3. Glitch is removed on the S_ACK_O signal. 5.77 -// 5.78 -// Version 7.0 5.79 -// 1. Initial Release 5.80 -// 5.81 +// : 5.82 +// Version : 7.0 5.83 +// : Initial Release 5.84 +// : 5.85 +// Version : 7.0SP2, 3.0 5.86 +// : 1. Read and Write channel of DMA controller are working in 5.87 +// : parallel, due to that now as soon as FIFO is not empty 5.88 +// : write channel of the DMA controller start writing data 5.89 +// : to the slave. 5.90 +// : 2. Burst Size supported by DMA controller is increased to 5.91 +// : support bigger burst (from current value of 4 and 8 to 5.92 +// : 16 and 32). Now 4 different type of burst sizes are 5.93 +// : supported by the DMA controller 4, 8, 16 and 32. For 5.94 +// : this Burst Size field of the control register is 5.95 +// : increased to 2 bits. 5.96 +// : 3. Glitch is removed on the S_ACK_O signal. 5.97 +// : 5.98 +// Version : 3.1 5.99 +// : Make DMA Engine compliant to Rule 3.100 of Wishbone Spec 5.100 +// : which defines alignement of bytes in sub-word transfers. 5.101 +// : 5.102 +// Version : 3.2 5.103 +// : 1. Support for 8/32-bit WISHBONE Data Bus. The Control and 5.104 +// : Read/Write Ports can be independently configured. 5.105 +// : 2. Support for "retry" on receipt of a WISHBONE RTY. This 5.106 +// : retry results in the current burst or classic cycle 5.107 +// : being issued again after a retry timeout. 5.108 +// : 3. Support for "error" on receipt of a WISHBONE ERR. This 5.109 +// : results in the current dma transfer being terminated 5.110 +// : and the error is updated within the STATUS CSR. 5.111 +// : 4. Support for burst size of 64. 5.112 +// : 5.113 +// Version : 3.3 5.114 +// : Support for MachXO2 added. The MachXO2 only has a FIFO 5.115 +// : with separate read/write clocks. 5.116 // ============================================================================= 5.117 5.118 `ifndef MASTER_CTRL_FILE 5.119 `define MASTER_CTRL_FILE 5.120 `include "system_conf.v" 5.121 module MASTER_CTRL 5.122 - #(parameter LENGTH_WIDTH = 16, 5.123 + #(parameter MA_WB_DAT_WIDTH = 32, 5.124 + parameter MA_WB_ADR_WIDTH = 32, 5.125 + parameter MB_WB_DAT_WIDTH = 32, 5.126 + parameter MB_WB_ADR_WIDTH = 32, 5.127 + parameter S_WB_DAT_WIDTH = 32, 5.128 parameter FIFO_IMPLEMENTATION = "EBR") 5.129 - ( 5.130 - //master read port 5.131 - MA_ADR_O, 5.132 - MA_SEL_O, 5.133 - MA_WE_O, 5.134 - MA_STB_O, 5.135 - MA_CYC_O, 5.136 - MA_CTI_O, 5.137 - MA_LOCK_O, 5.138 - MA_DAT_I, //32bits 5.139 - MA_ACK_I, 5.140 - MA_ERR_I, 5.141 - MA_RTY_I, 5.142 - //master write port 5.143 - MB_ADR_O, 5.144 - MB_SEL_O, 5.145 - MB_DAT_O, //32bits 5.146 - MB_WE_O, 5.147 - MB_STB_O, 5.148 - MB_CYC_O, 5.149 - MB_CTI_O, 5.150 - MB_LOCK_O, 5.151 - MB_ACK_I, 5.152 - MB_ERR_I, 5.153 - MB_RTY_I, 5.154 - //register interface 5.155 - M_SEL_O, 5.156 - reg_start, 5.157 - reg_status, 5.158 - reg_interrupt, 5.159 - reg_busy, 5.160 - data_length, 5.161 - reg_cntlg, 5.162 - reg_bt2,reg_bt1,reg_bt0, 5.163 - incr_unit, 5.164 - reg_s_con, 5.165 - reg_d_con, 5.166 - reg_00_data, 5.167 - reg_04_data, 5.168 - //system clock and reset 5.169 - CLK_I, 5.170 - RST_I 5.171 - ); 5.172 - //master read port 5.173 - output [31:0] MA_ADR_O; 5.174 - output [3:0] MA_SEL_O; 5.175 - output MA_WE_O; 5.176 - output MA_STB_O; 5.177 - output MA_CYC_O; 5.178 - output [2:0] MA_CTI_O; 5.179 - output MA_LOCK_O; 5.180 - input [31:0] MA_DAT_I; //32bits 5.181 - input MA_ACK_I; 5.182 - input MA_ERR_I; 5.183 - input MA_RTY_I; 5.184 - //master write port 5.185 - output [31:0] MB_ADR_O; 5.186 - output [3:0] MB_SEL_O; 5.187 - output [31:0] MB_DAT_O; //32bits 5.188 - output MB_WE_O; 5.189 - output MB_STB_O; 5.190 - output MB_CYC_O; 5.191 - output [2:0] MB_CTI_O; 5.192 - output MB_LOCK_O; 5.193 - input MB_ACK_I; 5.194 - input MB_ERR_I; 5.195 - input MB_RTY_I; 5.196 - 5.197 - //register interface 5.198 - input [3:0] M_SEL_O; 5.199 - input reg_start; 5.200 - output reg_status; 5.201 - output reg_interrupt; 5.202 - output reg_busy; 5.203 - input [LENGTH_WIDTH-1:0] data_length; 5.204 - output reg_cntlg; 5.205 - input reg_bt2,reg_bt1,reg_bt0; 5.206 - input [2:0] incr_unit; 5.207 - input reg_s_con; 5.208 - input reg_d_con; 5.209 - input [31:0] reg_00_data; 5.210 - input [31:0] reg_04_data; 5.211 - //system clock and reset 5.212 - input CLK_I; 5.213 - input RST_I; 5.214 + ( 5.215 + // System clock and reset 5.216 + input CLK_I, 5.217 + input RST_I, 5.218 + // Master read port 5.219 + output reg [MA_WB_ADR_WIDTH-1:0] MA_ADR_O, 5.220 + output reg [MA_WB_DAT_WIDTH/8-1:0] MA_SEL_O, 5.221 + output reg [MA_WB_DAT_WIDTH-1:0] MA_DAT_O, 5.222 + output reg MA_WE_O, 5.223 + output reg MA_STB_O, 5.224 + output reg MA_CYC_O, 5.225 + output reg [2:0] MA_CTI_O, 5.226 + output reg MA_LOCK_O, 5.227 + input [MA_WB_DAT_WIDTH-1:0] MA_DAT_I, 5.228 + input MA_ACK_I, 5.229 + input MA_ERR_I, 5.230 + input MA_RTY_I, 5.231 + // Master write port 5.232 + output reg [MB_WB_ADR_WIDTH-1:0] MB_ADR_O, 5.233 + output reg [MB_WB_DAT_WIDTH/8-1:0] MB_SEL_O, 5.234 + output reg [MB_WB_DAT_WIDTH-1:0] MB_DAT_O, 5.235 + output reg MB_WE_O, 5.236 + output reg MB_STB_O, 5.237 + output reg MB_CYC_O, 5.238 + output reg [2:0] MB_CTI_O, 5.239 + output reg MB_LOCK_O, 5.240 + input MB_ACK_I, 5.241 + input MB_ERR_I, 5.242 + input MB_RTY_I, 5.243 + // Register interface 5.244 + input reg_start, 5.245 + output reg reg_busy, 5.246 + output reg reg_status, 5.247 + output reg reg_interrupt, 5.248 + input reg_bt3, reg_bt2, reg_bt1, reg_bt0, 5.249 + input reg_s_con, reg_d_con, 5.250 + input reg_incw, reg_inchw, 5.251 + input [7:0] reg_rdelay, 5.252 + input [31:0] reg_00_data, 5.253 + input [31:0] reg_04_data, 5.254 + input [31:0] reg_08_data 5.255 + ); 5.256 + 5.257 + parameter lat_family = `LATTICE_FAMILY; 5.258 + parameter UDLY = 1; 5.259 + 5.260 + wire [MB_WB_DAT_WIDTH-1:0] fifo_dout; 5.261 + wire fifo_empty, fifo_aempty; 5.262 + reg [MA_WB_DAT_WIDTH-1:0] fifo_din; 5.263 + 5.264 + reg [31:0] xfer_length, xfer_length_nxt; 5.265 + reg [5:0] rburst_count, rburst_count_nxt; 5.266 + reg [5:0] wburst_count, wburst_count_nxt; 5.267 + reg [5:0] save_wburst_count, save_wburst_count_nxt; 5.268 + reg [31:0] raddr_checkpoint, raddr_checkpoint_nxt, waddr_checkpoint, waddr_checkpoint_nxt; 5.269 + reg [7:0] retry_delay, retry_delay_nxt; 5.270 + reg MA_CYC_O_nxt, MA_STB_O_nxt, MA_CYC_O_d; 5.271 + reg [2:0] MA_CTI_O_nxt; 5.272 + reg [MA_WB_ADR_WIDTH-1:0] MA_ADR_O_nxt; 5.273 + reg [MA_WB_DAT_WIDTH/8-1:0] MA_SEL_O_nxt; 5.274 + reg MB_CYC_O_nxt, MB_STB_O_nxt, MB_CYC_O_d; 5.275 + reg [2:0] MB_CTI_O_nxt; 5.276 + reg [MB_WB_ADR_WIDTH-1:0] MB_ADR_O_nxt; 5.277 + reg [MB_WB_DAT_WIDTH/8-1:0] MB_SEL_O_nxt; 5.278 + reg reg_status_nxt; 5.279 + reg burst_start, xfer_done; 5.280 + wire [2:0] iCount; 5.281 + wire [5:0] bCount; 5.282 + wire [8:0] biCount; 5.283 + 5.284 + /*---------------------------------------------------------------------- 5.285 + 5.286 + READ State Machine 5.287 + 5.288 + ----------------------------------------------------------------------*/ 5.289 + reg [2:0] rstate, rstate_nxt; 5.290 + parameter RD_IDLE = 3'b000; 5.291 + parameter RD_SINGLEA = 3'b001; 5.292 + parameter RD_SINGLEB = 3'b010; 5.293 + parameter RD_SINGLE_RETRY = 3'b011; 5.294 + parameter RD_BURST = 3'b100; 5.295 + 5.296 + always @(/*AUTOSENSE*/MA_ACK_I or MA_ERR_I or MA_RTY_I or MB_ERR_I 5.297 + or MB_RTY_I or burst_start or rburst_count or reg_bt3 5.298 + or reg_start or retry_delay or rstate or xfer_done) 5.299 + casez (rstate) 5.300 + RD_IDLE: 5.301 + if (reg_start && (reg_bt3 == 1'b0)) 5.302 + rstate_nxt = RD_SINGLEA; 5.303 + else if (burst_start && reg_bt3) 5.304 + rstate_nxt = RD_BURST; 5.305 + else 5.306 + rstate_nxt = rstate; 5.307 + 5.308 + RD_SINGLEA: 5.309 + if (MA_ACK_I) 5.310 + rstate_nxt = RD_SINGLEB; 5.311 + else if (MA_ERR_I) 5.312 + rstate_nxt = RD_IDLE; 5.313 + else if (MA_RTY_I) 5.314 + rstate_nxt = RD_SINGLE_RETRY; 5.315 + else 5.316 + rstate_nxt = rstate; 5.317 + 5.318 + RD_SINGLEB: 5.319 + if (burst_start) 5.320 + rstate_nxt = RD_SINGLEA; 5.321 + else if (MB_ERR_I || xfer_done) 5.322 + rstate_nxt = RD_IDLE; 5.323 + else if (MB_RTY_I) 5.324 + rstate_nxt = RD_SINGLE_RETRY; 5.325 + else 5.326 + rstate_nxt = rstate; 5.327 + 5.328 + RD_BURST: 5.329 + if (MB_ERR_I || MB_RTY_I || MA_ERR_I || MB_RTY_I || (MA_ACK_I && (rburst_count == 0))) 5.330 + rstate_nxt = RD_IDLE; 5.331 + else 5.332 + rstate_nxt = rstate; 5.333 + 5.334 + RD_SINGLE_RETRY: 5.335 + if (retry_delay == 8'h0) 5.336 + rstate_nxt = RD_SINGLEA; 5.337 + else 5.338 + rstate_nxt = rstate; 5.339 + 5.340 + default: 5.341 + rstate_nxt = RD_IDLE; 5.342 + endcase 5.343 + 5.344 + /*---------------------------------------------------------------------- 5.345 + 5.346 + WRITE State Machine 5.347 + 5.348 + ----------------------------------------------------------------------*/ 5.349 + reg [3:0] wstate, wstate_nxt; 5.350 + parameter WR_IDLE = 4'b0000; 5.351 + parameter WR_SINGLEA = 4'b0001; 5.352 + parameter WR_SINGLEB = 4'b0010; 5.353 + parameter WR_FIFO_CHECK = 4'b0011; 5.354 + parameter WR_SHORT = 4'b0100; 5.355 + parameter WR_BURST = 4'b0101; 5.356 + parameter WR_SBURST = 4'b0110; 5.357 + parameter WR_SETUPA = 4'b0111; 5.358 + parameter WR_SETUPB = 4'b1000; 5.359 + parameter WR_ERROR = 4'b1001; 5.360 + parameter WR_RETRY = 4'b1010; 5.361 + 5.362 + always @(/*AUTOSENSE*/MA_ERR_I or MA_RTY_I or MB_ACK_I or MB_ERR_I 5.363 + or MB_RTY_I or fifo_aempty or fifo_empty or iCount 5.364 + or reg_bt3 or reg_start or retry_delay or wburst_count 5.365 + or wstate or xfer_length) 5.366 + casez (wstate) 5.367 + WR_IDLE: 5.368 + if (reg_start) 5.369 + wstate_nxt = reg_bt3 ? WR_SETUPA : WR_SINGLEA; 5.370 + else 5.371 + wstate_nxt = wstate; 5.372 + 5.373 + WR_SINGLEA: 5.374 + if (MA_ERR_I) 5.375 + wstate_nxt = WR_IDLE; 5.376 + else if (fifo_empty == 1'b0) 5.377 + wstate_nxt = WR_SINGLEB; 5.378 + else 5.379 + wstate_nxt = wstate; 5.380 + 5.381 + WR_SINGLEB: 5.382 + if (MB_ACK_I) 5.383 + wstate_nxt = (xfer_length == iCount) ? WR_IDLE : WR_SINGLEA; 5.384 + else if (MB_ERR_I) 5.385 + wstate_nxt = WR_IDLE; 5.386 + else if (MB_RTY_I) 5.387 + wstate_nxt = WR_SINGLEA; 5.388 + else 5.389 + wstate_nxt = wstate; 5.390 + 5.391 + WR_FIFO_CHECK: 5.392 + if (MA_ERR_I) 5.393 + wstate_nxt = WR_ERROR; 5.394 + else if (MA_RTY_I) 5.395 + wstate_nxt = WR_RETRY; 5.396 + else 5.397 + if ((fifo_empty == 1'b0) && (wburst_count == 6'h0)) 5.398 + wstate_nxt = WR_SHORT; 5.399 + else if ((fifo_aempty == 1'b0) && (wburst_count >= 6'h1)) 5.400 + wstate_nxt = WR_BURST; 5.401 + else 5.402 + wstate_nxt = wstate; 5.403 + 5.404 + WR_SHORT: 5.405 + if (MA_ERR_I) 5.406 + wstate_nxt = WR_ERROR; 5.407 + else if (MA_RTY_I) 5.408 + wstate_nxt = WR_RETRY; 5.409 + else 5.410 + if (MB_ACK_I) 5.411 + wstate_nxt = WR_FIFO_CHECK; 5.412 + else if (MB_ERR_I) 5.413 + wstate_nxt = WR_ERROR; 5.414 + else if (MB_RTY_I) 5.415 + wstate_nxt = WR_RETRY; 5.416 + else 5.417 + wstate_nxt = wstate; 5.418 + 5.419 + WR_BURST: 5.420 + if (MA_ERR_I) 5.421 + wstate_nxt = WR_ERROR; 5.422 + else if (MA_RTY_I) 5.423 + wstate_nxt = WR_RETRY; 5.424 + else 5.425 + if (MB_ACK_I) 5.426 + if (fifo_aempty && (wburst_count >= 6'h2)) 5.427 + wstate_nxt = WR_SBURST; 5.428 + else if (wburst_count == 6'h0) 5.429 + wstate_nxt = WR_SETUPA; 5.430 + else 5.431 + wstate_nxt = wstate; 5.432 + else if (MB_ERR_I) 5.433 + wstate_nxt = WR_ERROR; 5.434 + else if (MB_RTY_I) 5.435 + wstate_nxt = WR_RETRY; 5.436 + else 5.437 + wstate_nxt = wstate; 5.438 + 5.439 + WR_SBURST: 5.440 + if (MA_ERR_I) 5.441 + wstate_nxt = WR_ERROR; 5.442 + else if (MA_RTY_I) 5.443 + wstate_nxt = WR_RETRY; 5.444 + else 5.445 + if (MB_ACK_I) 5.446 + wstate_nxt = WR_FIFO_CHECK; 5.447 + else if (MB_RTY_I) 5.448 + wstate_nxt = WR_RETRY; 5.449 + else 5.450 + wstate_nxt = wstate; 5.451 + 5.452 + WR_SETUPA: 5.453 + wstate_nxt = WR_SETUPB; 5.454 + 5.455 + WR_SETUPB: 5.456 + wstate_nxt = (wburst_count == 6'h0) ? WR_IDLE : WR_FIFO_CHECK; 5.457 + 5.458 + WR_ERROR: 5.459 + wstate_nxt = fifo_empty ? WR_IDLE : wstate; 5.460 + 5.461 + WR_RETRY: 5.462 + if (fifo_empty && (retry_delay == 8'h0)) 5.463 + wstate_nxt = WR_FIFO_CHECK; 5.464 + else 5.465 + wstate_nxt = wstate; 5.466 + 5.467 + default: 5.468 + wstate_nxt = WR_IDLE; 5.469 + endcase 5.470 + 5.471 + /*---------------------------------------------------------------------- 5.472 + Status Signals 5.473 + ----------------------------------------------------------------------*/ 5.474 + always @(/*AUTOSENSE*/MA_ERR_I or MB_ERR_I or reg_status or wstate 5.475 + or wstate_nxt) 5.476 + begin 5.477 + // Raise and hold busy signal until current DMA transfer is complete 5.478 + reg_busy = (wstate_nxt != WR_IDLE); 5.479 + 5.480 + // Raise and hold error signal until a new DMA transfer is initiated. 5.481 + // Error signal is raised when the WISHBONE cycle results in _ERR_I 5.482 + if ((wstate == WR_IDLE) && (wstate_nxt != WR_IDLE)) 5.483 + reg_status_nxt = 1'b0; 5.484 + else if (MA_ERR_I || MB_ERR_I) 5.485 + reg_status_nxt = 1'b1; 5.486 + else 5.487 + reg_status_nxt = reg_status; 5.488 + 5.489 + // Raise interrupt on completion of DMA transfer 5.490 + reg_interrupt = (wstate != WR_IDLE) & (wstate_nxt == WR_IDLE); 5.491 + end 5.492 + 5.493 + /*---------------------------------------------------------------------- 5.494 + WISHBONE Read Port 5.495 + ----------------------------------------------------------------------*/ 5.496 + always @(/*AUTOSENSE*/MA_ACK_I or MA_ADR_O or MA_CTI_O or MA_CYC_O 5.497 + or MA_CYC_O_d or MA_ERR_I or MA_RTY_I or MA_STB_O 5.498 + or MB_ERR_I or MB_RTY_I or burst_start or iCount 5.499 + or raddr_checkpoint or rburst_count or reg_00_data 5.500 + or reg_bt3 or reg_s_con or reg_start or rstate 5.501 + or rstate_nxt) 5.502 + begin 5.503 + // MA_CYC_O and MA_STB_O 5.504 + 5.505 + // handle all conditions that cause MA_CYC_O to go 0 5.506 + if (((rstate == RD_SINGLEA) 5.507 + && (MA_ACK_I || MA_ERR_I || MA_RTY_I)) 5.508 + || ((rstate == RD_BURST) 5.509 + && (MB_ERR_I || MB_RTY_I || (MA_ACK_I && (rburst_count == 6'h0))))) 5.510 + begin 5.511 + MA_CYC_O_nxt = 1'b0; 5.512 + MA_STB_O_nxt = 1'b0; 5.513 + end 5.514 + // handle all conditions that cause MA_CYC_O to go 1 5.515 + else if (((rstate_nxt == RD_SINGLEA) 5.516 + && ((rstate == RD_IDLE) || (rstate == RD_SINGLEB) || (rstate == RD_SINGLE_RETRY))) 5.517 + || ((rstate == RD_BURST) && (MA_CYC_O_d == 1'b0))) 5.518 + begin 5.519 + MA_CYC_O_nxt = 1'b1; 5.520 + MA_STB_O_nxt = 1'b1; 5.521 + end 5.522 + // default: maintain state 5.523 + else 5.524 + begin 5.525 + MA_CYC_O_nxt = MA_CYC_O; 5.526 + MA_STB_O_nxt = MA_STB_O; 5.527 + end 5.528 + 5.529 + 5.530 + // MA_ADR_O 5.531 + 5.532 + // set up first address of the dma transfer 5.533 + if (reg_start) 5.534 + MA_ADR_O_nxt = reg_00_data; 5.535 + else if (reg_s_con == 1'b0) 5.536 + begin 5.537 + // roll back to first address in a burst transfer on a retry 5.538 + if (/*(rstate == RD_BURST) && */MB_RTY_I) 5.539 + MA_ADR_O_nxt = raddr_checkpoint; 5.540 + // increment for every regular transfer 5.541 + else if ((MB_RTY_I == 1'b0) 5.542 + && (((rstate == RD_SINGLEB) && burst_start) 5.543 + || ((rstate == RD_BURST) && MA_ACK_I))) 5.544 + MA_ADR_O_nxt = MA_ADR_O + iCount; 5.545 + else 5.546 + MA_ADR_O_nxt = MA_ADR_O; 5.547 + end 5.548 + else 5.549 + MA_ADR_O_nxt = MA_ADR_O; 5.550 + 5.551 + 5.552 + // MA_CTI_O 5.553 + 5.554 + if (reg_start || burst_start) 5.555 + MA_CTI_O_nxt = reg_bt3 ? (reg_s_con ? 3'b001 : 3'b010) : 3'b000; 5.556 + else if ((rstate == RD_BURST) && (rburst_count == 6'h1) && MA_ACK_I) 5.557 + MA_CTI_O_nxt = 3'b111; 5.558 + else 5.559 + MA_CTI_O_nxt = MA_CTI_O; 5.560 + 5.561 + 5.562 + // Other signals 5.563 + MA_WE_O = 1'b0; 5.564 + MA_DAT_O = 0; 5.565 + MA_LOCK_O = 1'b0; 5.566 + end 5.567 + 5.568 + generate 5.569 + if (MA_WB_DAT_WIDTH == 8) begin 5.570 + 5.571 + always @(*) 5.572 + MA_SEL_O_nxt = 1'b1; 5.573 + 5.574 + end 5.575 + else begin 5.576 + 5.577 + always @(/*AUTOSENSE*/MA_ADR_O_nxt or iCount) 5.578 + begin 5.579 + if (iCount == 1) 5.580 + casez (MA_ADR_O_nxt[1:0]) 5.581 + 2'b00: MA_SEL_O_nxt = 4'b1000; 5.582 + 2'b01: MA_SEL_O_nxt = 4'b0100; 5.583 + 2'b10: MA_SEL_O_nxt = 4'b0010; 5.584 + 2'b11: MA_SEL_O_nxt = 4'b0001; 5.585 + default: 5.586 + MA_SEL_O_nxt = 4'b1111; 5.587 + endcase 5.588 + else if (iCount == 2) 5.589 + MA_SEL_O_nxt = MA_ADR_O_nxt[1] ? 4'b0011 : 4'b1100; 5.590 + else 5.591 + MA_SEL_O_nxt = 4'b1111; 5.592 + end 5.593 + 5.594 + end 5.595 + endgenerate 5.596 + 5.597 + 5.598 + /*---------------------------------------------------------------------- 5.599 + WISHBONE Write Port 5.600 + ----------------------------------------------------------------------*/ 5.601 + always @(/*AUTOSENSE*/MA_ERR_I or MA_RTY_I or MB_ACK_I or MB_ADR_O 5.602 + or MB_CTI_O or MB_CYC_O or MB_ERR_I or MB_RTY_I 5.603 + or MB_STB_O or fifo_aempty or fifo_dout or fifo_empty 5.604 + or iCount or reg_04_data or reg_d_con or reg_s_con 5.605 + or reg_start or waddr_checkpoint or wburst_count or wstate 5.606 + or wstate_nxt) 5.607 + begin 5.608 + // MB_CYC_O and MB_STB_O 5.609 + 5.610 + // handle all conditions that cause MB_CYC_O to go 0 5.611 + if (((wstate == WR_SINGLEB) 5.612 + && (MB_ACK_I || MB_ERR_I || MB_RTY_I)) 5.613 + || ((MA_ERR_I || MA_RTY_I) 5.614 + && ((wstate == WR_SHORT) || (wstate == WR_FIFO_CHECK) || (wstate == WR_BURST) || (wstate == WR_SBURST))) 5.615 + || ((wstate == WR_BURST) 5.616 + && ((MB_ACK_I && (wburst_count == 6'h0)) || MB_ERR_I || MB_RTY_I)) 5.617 + || ((wstate == WR_SBURST) 5.618 + && (MB_ACK_I || MB_ERR_I || MB_RTY_I))) 5.619 + begin 5.620 + MB_CYC_O_nxt = 1'b0; 5.621 + MB_STB_O_nxt = 1'b0; 5.622 + end 5.623 + // handle all conditions that cause MB_CYC_O to go 1 5.624 + else if (((wstate == WR_SINGLEA) && (fifo_empty == 1'b0)) 5.625 + || ((wstate == WR_FIFO_CHECK) 5.626 + && (((fifo_empty == 1'b0) && (wburst_count == 6'h0)) 5.627 + || ((fifo_aempty == 1'b0) && (wburst_count >= 6'h1))))) 5.628 + begin 5.629 + MB_CYC_O_nxt = 1'b1; 5.630 + MB_STB_O_nxt = 1'b1; 5.631 + end 5.632 + // default: maintain state 5.633 + else 5.634 + begin 5.635 + MB_CYC_O_nxt = MB_CYC_O; 5.636 + MB_STB_O_nxt = MB_STB_O; 5.637 + end 5.638 + 5.639 + 5.640 + // MB_ADR_O 5.641 + 5.642 + // set up first address of the dma transfer 5.643 + if (reg_start) 5.644 + MB_ADR_O_nxt = reg_04_data; 5.645 + else if (reg_d_con == 1'b0) 5.646 + begin 5.647 + // roll back to first address in a burst transfer on a retry 5.648 + if (wstate == WR_RETRY) 5.649 + MB_ADR_O_nxt = waddr_checkpoint; 5.650 + // increment for every regular transfer 5.651 + else if (((wstate == WR_SINGLEB) && MB_ACK_I) 5.652 + || (MB_ACK_I && (MA_RTY_I == 1'b0) && (MA_ERR_I == 1'b0) 5.653 + && ((wstate == WR_SHORT) || (wstate == WR_BURST) || (wstate == WR_SBURST)))) 5.654 + MB_ADR_O_nxt = MB_ADR_O + iCount; 5.655 + else 5.656 + MB_ADR_O_nxt = MB_ADR_O; 5.657 + end 5.658 + else 5.659 + MB_ADR_O_nxt = MB_ADR_O; 5.660 + 5.661 + 5.662 + // MB_CTI_O 5.663 + 5.664 + // set up classic wishbone cycle 5.665 + if ((wstate == WR_SINGLEA) 5.666 + || ((wstate == WR_FIFO_CHECK) && (wstate_nxt == WR_SHORT))) 5.667 + MB_CTI_O_nxt = 3'b000; 5.668 + // set up termination of a wishbone burst cycle 5.669 + else if ((wstate == WR_BURST) 5.670 + && ((MB_ACK_I && (wburst_count == 6'h1)) || (wstate_nxt == WR_SBURST))) 5.671 + MB_CTI_O_nxt = 3'b111; 5.672 + // set up wishbone burst (incrementing or constant address) 5.673 + else if (((wstate == WR_FIFO_CHECK) && (wstate_nxt == WR_BURST)) 5.674 + || ((wstate == WR_BURST) && MB_ACK_I)) 5.675 + MB_CTI_O_nxt = reg_s_con ? 3'b001 : 3'b010; 5.676 + // hold 5.677 + else 5.678 + MB_CTI_O_nxt = MB_CTI_O; 5.679 + 5.680 + // MB_DAT_O 5.681 + MB_DAT_O = fifo_dout; 5.682 + 5.683 + 5.684 + // Other signals 5.685 + MB_WE_O = 1'b1; 5.686 + MB_LOCK_O = 1'b0; 5.687 + end 5.688 + 5.689 + generate 5.690 + if (MB_WB_DAT_WIDTH == 8) begin 5.691 + 5.692 + always @(*) 5.693 + MB_SEL_O_nxt = 1'b1; 5.694 + 5.695 + end 5.696 + else begin 5.697 + 5.698 + always @(/*AUTOSENSE*/MB_ADR_O_nxt or iCount) 5.699 + begin 5.700 + if (iCount == 1) 5.701 + casez (MB_ADR_O_nxt[1:0]) 5.702 + 2'b00: MB_SEL_O_nxt = 4'b1000; 5.703 + 2'b01: MB_SEL_O_nxt = 4'b0100; 5.704 + 2'b10: MB_SEL_O_nxt = 4'b0010; 5.705 + 2'b11: MB_SEL_O_nxt = 4'b0001; 5.706 + default: 5.707 + MB_SEL_O_nxt = 4'b1111; 5.708 + endcase 5.709 + else if (iCount == 2) 5.710 + MB_SEL_O_nxt = MB_ADR_O_nxt[1] ? 4'b0011 : 4'b1100; 5.711 + else 5.712 + MB_SEL_O_nxt = 4'b1111; 5.713 + end 5.714 + 5.715 + end 5.716 + endgenerate 5.717 + 5.718 + /*---------------------------------------------------------------------- 5.719 + Logic to keep track of where we are in the transfer process 5.720 + ----------------------------------------------------------------------*/ 5.721 + // Increment Count 5.722 + generate 5.723 + if (S_WB_DAT_WIDTH == 8) begin 5.724 + assign iCount = 3'h1; 5.725 + end 5.726 + else begin 5.727 + assign iCount = reg_incw ? 3'h4 : (reg_inchw ? 3'h2 : 3'h1); 5.728 + end 5.729 + endgenerate 5.730 + 5.731 + // Burst Count 5.732 + assign bCount = (reg_bt3 5.733 + ? (reg_bt2 5.734 + ? 6'h3f 5.735 + : (reg_bt1 5.736 + ? (reg_bt0 ? 6'h1f : 6'h0f) 5.737 + : (reg_bt0 ? 6'h07 : 6'h03))) 5.738 + : 6'h01 5.739 + ); 5.740 + 5.741 + // Burst Increment Count 5.742 + assign biCount = (reg_bt3 5.743 + ? (reg_bt2 5.744 + ? iCount<<6 5.745 + : (reg_bt1 5.746 + ? (reg_bt0 ? iCount<<5 : iCount<<4) 5.747 + : (reg_bt0 ? iCount<<3 : iCount<<2) 5.748 + ) 5.749 + ) 5.750 + : iCount 5.751 + ); 5.752 + 5.753 + always @(/*AUTOSENSE*/MA_ACK_I or MB_ACK_I or bCount or biCount 5.754 + or fifo_empty or iCount or rburst_count or reg_08_data 5.755 + or reg_inchw or reg_incw or reg_start or rstate 5.756 + or save_wburst_count or wburst_count or wstate 5.757 + or xfer_length) 5.758 + begin 5.759 + // Transfer Length 5.760 + if (reg_start && (wstate == WR_IDLE)) 5.761 + xfer_length_nxt = reg_08_data; 5.762 + else if (MB_ACK_I && (wstate == WR_SINGLEB)) 5.763 + xfer_length_nxt = xfer_length - iCount; 5.764 + else if (wstate == WR_SETUPA) 5.765 + xfer_length_nxt = (xfer_length >= biCount) ? (xfer_length - biCount) : 0; 5.766 + else 5.767 + xfer_length_nxt = xfer_length; 5.768 + 5.769 + // Read-side Burst Count 5.770 + if (rstate == RD_IDLE) 5.771 + rburst_count_nxt = wburst_count; 5.772 + else if ((rstate == RD_BURST) && MA_ACK_I) 5.773 + rburst_count_nxt = rburst_count - 1'b1; 5.774 + else 5.775 + rburst_count_nxt = rburst_count; 5.776 + 5.777 + // Write-side Burst Count 5.778 + if (wstate == WR_SETUPA) 5.779 + wburst_count_nxt = ((xfer_length == 0) 5.780 + ? 0 5.781 + : ((xfer_length >= biCount) 5.782 + ? bCount 5.783 + : (xfer_length-1)>>(reg_incw ? 2 : (reg_inchw ? 1 : 0)))); 5.784 + else if ((wstate == WR_RETRY) && fifo_empty) 5.785 + wburst_count_nxt = save_wburst_count; 5.786 + else if (MB_ACK_I 5.787 + && ((wstate == WR_SHORT) || (wstate == WR_BURST) || (wstate == WR_SBURST))) 5.788 + wburst_count_nxt = wburst_count - 1'b1; 5.789 + else 5.790 + wburst_count_nxt = wburst_count; 5.791 + end 5.792 + 5.793 + /*---------------------------------------------------------------------- 5.794 + Logic to support a burst retry 5.795 + ----------------------------------------------------------------------*/ 5.796 + always @(/*AUTOSENSE*/MA_ADR_O or MB_ADR_O or raddr_checkpoint 5.797 + or reg_rdelay or retry_delay or rstate or rstate_nxt 5.798 + or save_wburst_count or waddr_checkpoint 5.799 + or wburst_count_nxt or wstate or wstate_nxt) 5.800 + begin 5.801 + // Write-side Saved Burst Count 5.802 + if (wstate == WR_SETUPA) 5.803 + save_wburst_count_nxt = wburst_count_nxt; 5.804 + else 5.805 + save_wburst_count_nxt = save_wburst_count; 5.806 + 5.807 + // Retry Delay 5.808 + if (((wstate != WR_RETRY) && (wstate_nxt == WR_RETRY)) 5.809 + || ((rstate == RD_SINGLEA) && (rstate_nxt == RD_SINGLE_RETRY))) 5.810 + retry_delay_nxt = reg_rdelay; 5.811 + else if ((wstate == WR_RETRY) || (rstate == RD_SINGLE_RETRY)) 5.812 + retry_delay_nxt = retry_delay - 1'b1; 5.813 + else 5.814 + retry_delay_nxt = retry_delay; 5.815 + 5.816 + // Read Address Checkpoint 5.817 + if ((rstate == RD_IDLE) && (rstate_nxt == RD_BURST)) 5.818 + raddr_checkpoint_nxt = MA_ADR_O; 5.819 + else 5.820 + raddr_checkpoint_nxt = raddr_checkpoint; 5.821 + 5.822 + // Write Address Checkpoint 5.823 + if (wstate == WR_SETUPA) 5.824 + waddr_checkpoint_nxt = MB_ADR_O; 5.825 + else 5.826 + waddr_checkpoint_nxt = waddr_checkpoint; 5.827 + end 5.828 + 5.829 + /*---------------------------------------------------------------------- 5.830 + Logic to indicate start/end of transfer and bursts 5.831 + ----------------------------------------------------------------------*/ 5.832 + always @(/*AUTOSENSE*/MA_ERR_I or MB_ACK_I or MB_ERR_I or iCount 5.833 + or retry_delay or wburst_count or wstate or xfer_length) 5.834 + begin 5.835 + if (((wstate == WR_SINGLEB) && (xfer_length > iCount) && MB_ACK_I) 5.836 + || ((wstate == WR_SETUPB) && (wburst_count > 0)) 5.837 + || ((wstate == WR_RETRY) && (retry_delay == 8'b0))) 5.838 + burst_start = 1'b1; 5.839 + else 5.840 + burst_start = 1'b0; 5.841 + 5.842 + if (MB_ERR_I 5.843 + || MA_ERR_I 5.844 + || ((wstate == WR_SINGLEB) && (xfer_length == iCount) && MB_ACK_I) 5.845 + || ((wstate == WR_SETUPB) && (wburst_count == 0))) 5.846 + xfer_done = 1'b1; 5.847 + else 5.848 + xfer_done = 1'b0; 5.849 + end 5.850 5.851 - parameter lat_family = `LATTICE_FAMILY; 5.852 - parameter UDLY = 1; 5.853 - //Read FSM States encoding 5.854 - parameter ST_IDLE = 3'b000; 5.855 - parameter ST_READ = 3'b001; 5.856 - parameter ST_RDADDR = 3'b010; 5.857 - parameter ST_RDFIFO = 3'b011; 5.858 - parameter ST_WAIT_WRITE_FINISH = 3'b100; 5.859 - 5.860 - //Write FSM States encoding 5.861 - parameter ST_WRITE_IDLE = 4'b0000; 5.862 - parameter ST_WRITE = 4'b0001; 5.863 - parameter ST_WRADDR = 4'b0010; 5.864 - parameter ST_CNTLNGTH = 4'b0011; 5.865 - parameter ST_JUSTICE = 4'b0100; 5.866 - parameter ST_FIFO_EMPTY = 4'b0101; 5.867 - parameter ST_WRITE_WAIT = 4'b0110; 5.868 - parameter ST_FIFO_AEMPTY = 4'b1010; 5.869 - parameter ST_FIFO_RESUME = 4'b1000; 5.870 - 5.871 - // FSM for normal data transfer 5.872 - parameter ST_IDLE1 = 3'b000; 5.873 - parameter ST_READ1 = 3'b001; 5.874 - parameter ST_WRITE1 = 3'b010; 5.875 - parameter ST_RDADDR1 = 3'b011; 5.876 - parameter ST_WRADDR1 = 3'b100; 5.877 - parameter ST_CNTLNGTH1 = 3'b101; 5.878 - parameter ST_JUSTICE1 = 3'b110; 5.879 - parameter ST_RDFIFO1 = 3'b111; 5.880 - reg [2:0] status; 5.881 - reg var_length; 5.882 - 5.883 - 5.884 - //fifo status 5.885 - 5.886 - reg [2:0] status1; 5.887 - reg [3:0] status2; 5.888 - reg var_length2; 5.889 - reg var_length1; 5.890 - reg MA_STB_O; 5.891 - reg MB_STB_O; 5.892 - reg MA_CYC_O; 5.893 - reg MB_CYC_O; 5.894 - reg [2:0] MA_CTI_O; 5.895 - reg [2:0] MB_CTI_O; 5.896 - wire MA_WE_O = 1'b0; 5.897 - wire MB_WE_O = 1'b1; 5.898 - reg [31:0] MA_ADR_O; 5.899 - reg [31:0] MB_ADR_O; 5.900 - reg [3:0] MA_SEL_O; 5.901 - reg [3:0] MB_SEL_O; 5.902 - wire MA_LOCK_O = 0; //reg_bt2 ? (status1 == ST_READ) && (!(MA_CTI_O == 3'h7)) : 1'b0; 5.903 - wire MB_LOCK_O = 0; //reg_bt2 ? (status2 == ST_WRITE) && (!(MB_CTI_O == 3'h7)) : 1'b0; 5.904 - 5.905 - wire reg_busy = reg_bt2 ? !(status1 == ST_IDLE) : !(status == ST_IDLE1); 5.906 - wire reg_interrupt; 5.907 - wire reg_status; 5.908 - 5.909 - wire reg_cntlg; 5.910 - reg start_flag; 5.911 - reg [5:0] burst_size; 5.912 - reg [5:0] burst_cnt; 5.913 - reg fifo_wr; 5.914 - reg fifo_rd; 5.915 - reg [31:0] fifo_din; 5.916 - wire [31:0] fifo_dout; 5.917 - wire fifo_empty; 5.918 - wire fifo_aempty; 5.919 - reg fifo_clear; 5.920 - reg [31:0] first_data; 5.921 - reg first_data_flag; 5.922 - wire [31:0] MB_DAT_O = first_data_flag ? first_data : fifo_dout; 5.923 - reg latch_start; 5.924 - 5.925 - reg reg_status1, reg_status2; 5.926 - reg reg_interrupt1, reg_interrupt2; 5.927 - reg end_of_transfer; 5.928 - reg burst_completed; 5.929 - reg donot_start_again; 5.930 - reg [5:0] burst_size2; 5.931 - reg [5:0] burst_cnt2; 5.932 - 5.933 - reg reg_cntlg_burst, reg_cntlg_normal; 5.934 - reg reg_status_normal, reg_interrupt_normal; 5.935 - reg direct_data; 5.936 - 5.937 + /*---------------------------------------------------------------------- 5.938 + Sequential Logic 5.939 + ----------------------------------------------------------------------*/ 5.940 always @(posedge CLK_I or posedge RST_I) 5.941 - if(RST_I) 5.942 - begin 5.943 - first_data <= #UDLY 'h0; 5.944 - first_data_flag <= #UDLY 1'b0; 5.945 - end 5.946 - else if((start_flag || direct_data) & !reg_bt2 & MA_ACK_I) 5.947 + if (RST_I) 5.948 begin 5.949 - first_data <= #UDLY MA_DAT_I; 5.950 - first_data_flag <= #UDLY 1'b1; 5.951 + rstate <= #UDLY RD_IDLE; 5.952 + wstate <= #UDLY WR_IDLE; 5.953 + xfer_length <= #UDLY 32'b0; 5.954 + rburst_count <= #UDLY 6'b0; 5.955 + wburst_count <= #UDLY 6'b0; 5.956 + retry_delay <= #UDLY 8'b0; 5.957 + reg_status <= #UDLY 1'b0; 5.958 + MA_CYC_O <= #UDLY 1'b0; 5.959 + MA_CYC_O_d <= #UDLY 1'b0; 5.960 + MA_STB_O <= #UDLY 1'b0; 5.961 + MA_CTI_O <= #UDLY 3'b0; 5.962 + MA_ADR_O <= #UDLY 'b0; 5.963 + MA_SEL_O <= #UDLY 'b0; 5.964 + MB_CYC_O <= #UDLY 1'b0; 5.965 + MB_CYC_O_d <= #UDLY 1'b0; 5.966 + MB_STB_O <= #UDLY 1'b0; 5.967 + MB_CTI_O <= #UDLY 3'b0; 5.968 + MB_ADR_O <= #UDLY 'b0; 5.969 + MB_SEL_O <= #UDLY 'b0; 5.970 + raddr_checkpoint <= #UDLY 32'b0; 5.971 + waddr_checkpoint <= #UDLY 32'b0; 5.972 + save_wburst_count <= #UDLY 6'b0; 5.973 end 5.974 - else if(first_data_flag & MB_ACK_I) 5.975 + else 5.976 begin 5.977 - first_data_flag <= #UDLY 1'b0; 5.978 + rstate <= #UDLY rstate_nxt; 5.979 + wstate <= #UDLY wstate_nxt; 5.980 + xfer_length <= #UDLY xfer_length_nxt; 5.981 + rburst_count <= #UDLY rburst_count_nxt; 5.982 + wburst_count <= #UDLY wburst_count_nxt; 5.983 + retry_delay <= #UDLY retry_delay_nxt; 5.984 + reg_status <= #UDLY reg_status_nxt; 5.985 + MA_CYC_O <= #UDLY MA_CYC_O_nxt; 5.986 + MA_CYC_O_d <= #UDLY MA_CYC_O; 5.987 + MA_STB_O <= #UDLY MA_STB_O_nxt; 5.988 + MA_CTI_O <= #UDLY MA_CTI_O_nxt; 5.989 + MA_ADR_O <= #UDLY MA_ADR_O_nxt; 5.990 + MA_SEL_O <= #UDLY MA_SEL_O_nxt; 5.991 + MB_CYC_O <= #UDLY MB_CYC_O_nxt; 5.992 + MB_CYC_O_d <= #UDLY MB_CYC_O; 5.993 + MB_STB_O <= #UDLY MB_STB_O_nxt; 5.994 + MB_CTI_O <= #UDLY MB_CTI_O_nxt; 5.995 + MB_ADR_O <= #UDLY MB_ADR_O_nxt; 5.996 + MB_SEL_O <= #UDLY MB_SEL_O_nxt; 5.997 + raddr_checkpoint <= #UDLY raddr_checkpoint_nxt; 5.998 + waddr_checkpoint <= #UDLY waddr_checkpoint_nxt; 5.999 + save_wburst_count <= #UDLY save_wburst_count_nxt; 5.1000 end 5.1001 5.1002 - assign reg_status = reg_bt2 ? (reg_status1 | reg_status2) : reg_status_normal; 5.1003 - assign reg_interrupt = reg_bt2 ? (reg_interrupt1 | reg_interrupt2) : reg_interrupt_normal; 5.1004 - assign reg_cntlg = reg_bt2 ? reg_cntlg_burst : reg_cntlg_normal; 5.1005 - 5.1006 - 5.1007 - //FSM 5.1008 - always @(posedge CLK_I or posedge RST_I) 5.1009 - if(RST_I) 5.1010 - begin 5.1011 - status1 <= #UDLY ST_IDLE; 5.1012 - var_length1 <= #UDLY 1'b0; 5.1013 - MA_ADR_O <= #UDLY 32'h0; 5.1014 - MA_SEL_O <= #UDLY 4'b1111; 5.1015 - MA_CYC_O <= #UDLY 1'b0; 5.1016 - MA_CTI_O <= #UDLY 3'h0; 5.1017 - MA_STB_O <= #UDLY 1'b0; 5.1018 - reg_status1 <= #UDLY 1'b0; 5.1019 - reg_interrupt1 <= #UDLY 1'b0; 5.1020 - start_flag <= #UDLY 1'b0; 5.1021 - burst_size <= #UDLY 5'h0; 5.1022 - burst_cnt <= #UDLY 5'h0; 5.1023 - fifo_clear <= #UDLY 1'b0; 5.1024 - latch_start <= #UDLY 1'b0; 5.1025 - fifo_wr <= #UDLY 1'b0; 5.1026 - 5.1027 - status2 <= #UDLY ST_WRITE_IDLE; 5.1028 - MB_ADR_O <= #UDLY 32'h0; 5.1029 - MB_SEL_O <= #UDLY 4'b1111; 5.1030 - MB_CYC_O <= #UDLY 1'b0; 5.1031 - MB_CTI_O <= #UDLY 3'h0; 5.1032 - MB_STB_O <= #UDLY 1'b0; 5.1033 - reg_status2 <= #UDLY 1'b0; 5.1034 - reg_interrupt2 <= #UDLY 1'b0; 5.1035 - reg_cntlg_burst <= #UDLY 1'b0; 5.1036 - burst_size2 <= #UDLY 5'h0; 5.1037 - burst_cnt2 <= #UDLY 5'h0; 5.1038 - fifo_rd <= #UDLY 1'b0; 5.1039 - end_of_transfer <= #UDLY 1'b0; 5.1040 - var_length2 <= #UDLY 1'b0; 5.1041 - burst_completed <= #UDLY 1'b0; 5.1042 - donot_start_again <= #UDLY 1'b0; 5.1043 - 5.1044 - status <= #UDLY ST_IDLE1; 5.1045 - var_length <= #UDLY 1'b0; 5.1046 - reg_status_normal <= #UDLY 1'b0; 5.1047 - reg_interrupt_normal <= #UDLY 1'b0; 5.1048 - reg_cntlg_normal <= #UDLY 1'b0; 5.1049 - direct_data <= #UDLY 1'b0; 5.1050 - end 5.1051 - else 5.1052 - begin 5.1053 - if (reg_bt2) begin 5.1054 - // Read Burst 5.1055 - if ((MB_RTY_I && (!(|data_length))) || (MB_ERR_I && (status2 == ST_WRITE))) 5.1056 - begin 5.1057 - status1 <= #UDLY ST_IDLE; 5.1058 - end 5.1059 - else 5.1060 - begin 5.1061 - case(status1) 5.1062 - ST_IDLE: 5.1063 - begin 5.1064 - if(fifo_wr) 5.1065 - fifo_wr <= #UDLY 1'b0; 5.1066 - if(MA_ACK_I) 5.1067 - begin 5.1068 - MA_CYC_O <= #UDLY 1'b0; 5.1069 - MA_STB_O <= #UDLY 1'b0; 5.1070 - MA_CTI_O <= #UDLY 3'h0; 5.1071 - end 5.1072 - if(reg_start | latch_start) 5.1073 - begin 5.1074 - if(fifo_empty) 5.1075 - begin 5.1076 - if(latch_start) 5.1077 - latch_start <= #UDLY 1'b0; 5.1078 - status1 <= #UDLY ST_READ; 5.1079 - MA_CYC_O <= #UDLY 1'b1; 5.1080 - MA_STB_O <= #UDLY 1'b1; 5.1081 - MA_ADR_O <= #UDLY reg_00_data; 5.1082 - case (reg_00_data[1:0]) 5.1083 - 2'b01: MA_SEL_O <= #UDLY {1'b0,M_SEL_O[3:1]}; 5.1084 - 2'b10: MA_SEL_O <= #UDLY {2'b00,M_SEL_O[3:2]}; 5.1085 - 2'b11: MA_SEL_O <= #UDLY {3'b00,M_SEL_O[3:3]}; 5.1086 - default: 5.1087 - MA_SEL_O <= #UDLY M_SEL_O; 5.1088 - endcase 5.1089 - set_cti_a; 5.1090 - start_flag <= #UDLY 1'b1; 5.1091 - if(!(|data_length)) 5.1092 - var_length1 <= #UDLY 1'b1; 5.1093 - else 5.1094 - var_length1 <= #UDLY 1'b0; 5.1095 - burst_size <= #UDLY reg_bt1 ? (reg_bt0 ? 5'h1f : 5'hf) : (reg_bt0 ? 5'h7 : 5'h3); 5.1096 - burst_cnt <= #UDLY reg_bt1 ? (reg_bt0 ? 5'h1f : 5'hf) : (reg_bt0 ? 5'h7 : 5'h3); 5.1097 - end 5.1098 - else 5.1099 - status1 <= #UDLY ST_RDFIFO; 5.1100 - end 5.1101 - else 5.1102 - status1 <= #UDLY ST_IDLE; 5.1103 - reg_interrupt1 <= #UDLY 1'b0; 5.1104 - end 5.1105 - 5.1106 - ST_WAIT_WRITE_FINISH: 5.1107 - begin 5.1108 - fifo_wr <= #UDLY 1'b0; 5.1109 - if (status2 == ST_WRITE) 5.1110 - start_flag <= #UDLY 1'b0; 5.1111 - if(end_of_transfer) 5.1112 - begin 5.1113 - if(!reg_s_con) 5.1114 - MA_ADR_O <= #UDLY MA_ADR_O + incr_unit; 5.1115 - if (incr_unit == 3'b001) 5.1116 - MA_SEL_O <= #UDLY {MA_SEL_O[0], MA_SEL_O[3:1]}; 5.1117 - else 5.1118 - if (incr_unit == 3'b010) 5.1119 - MA_SEL_O <= #UDLY {MA_SEL_O[1:0], MA_SEL_O[3:2]}; 5.1120 - 5.1121 - status1 <= #UDLY ST_RDADDR; 5.1122 - burst_cnt <= #UDLY burst_size; 5.1123 - end 5.1124 - else 5.1125 - begin 5.1126 - if(burst_completed) 5.1127 - status1 <= #UDLY ST_IDLE; 5.1128 - end 5.1129 - end 5.1130 - 5.1131 - ST_RDFIFO: 5.1132 - begin 5.1133 - if(fifo_empty) 5.1134 - begin 5.1135 - status1 <= #UDLY ST_IDLE; 5.1136 - fifo_clear <= #UDLY 1'b0; 5.1137 - latch_start <= #UDLY 1'b1; 5.1138 - end 5.1139 - else 5.1140 - fifo_clear <= #UDLY !fifo_clear; 5.1141 - end 5.1142 - 5.1143 - ST_RDADDR: 5.1144 - begin 5.1145 - MA_CYC_O <= #UDLY 1'b1; 5.1146 - MA_STB_O <= #UDLY 1'b1; 5.1147 - set_cti_a; 5.1148 - status1 <= #UDLY ST_READ; 5.1149 - end 5.1150 - 5.1151 - ST_READ: 5.1152 - begin 5.1153 - write_fifo; 5.1154 - if(MA_ACK_I) 5.1155 - begin 5.1156 - if(start_flag) 5.1157 - begin 5.1158 - if(burst_cnt == 0) 5.1159 - begin 5.1160 - MA_CYC_O <= #UDLY 1'b0; 5.1161 - MA_STB_O <= #UDLY 1'b0; 5.1162 - MA_CTI_O <= #UDLY 3'h0; 5.1163 - status1 <= #UDLY ST_WAIT_WRITE_FINISH; 5.1164 - end 5.1165 - else 5.1166 - begin 5.1167 - if(burst_cnt == 1) 5.1168 - MA_CTI_O <= #UDLY 3'h7; 5.1169 - burst_cnt <= #UDLY burst_cnt - 1; 5.1170 - if(!reg_s_con) 5.1171 - MA_ADR_O <= #UDLY MA_ADR_O + incr_unit; 5.1172 - if (incr_unit == 3'b001) 5.1173 - MA_SEL_O <= #UDLY {MA_SEL_O[0], MA_SEL_O[3:1]}; 5.1174 - else 5.1175 - if (incr_unit == 3'b010) 5.1176 - MA_SEL_O <= #UDLY {MA_SEL_O[1:0], MA_SEL_O[3:2]}; 5.1177 - end 5.1178 - end 5.1179 - else 5.1180 - begin 5.1181 - if(burst_cnt == 0) 5.1182 - begin 5.1183 - MA_CYC_O <= #UDLY 1'b0; 5.1184 - MA_STB_O <= #UDLY 1'b0; 5.1185 - MA_CTI_O <= #UDLY 3'h0; 5.1186 - status1 <= #UDLY ST_WAIT_WRITE_FINISH; 5.1187 - end 5.1188 - else 5.1189 - begin 5.1190 - if(burst_cnt == 1) 5.1191 - MA_CTI_O <= #UDLY 3'h7; 5.1192 - if(!reg_s_con) 5.1193 - MA_ADR_O <= #UDLY MA_ADR_O + incr_unit; 5.1194 - if (incr_unit == 3'b001) 5.1195 - MA_SEL_O <= #UDLY {MA_SEL_O[0], MA_SEL_O[3:1]}; 5.1196 - else 5.1197 - if (incr_unit == 3'b010) 5.1198 - MA_SEL_O <= #UDLY {MA_SEL_O[1:0], MA_SEL_O[3:2]}; 5.1199 - burst_cnt <= #UDLY burst_cnt - 1; 5.1200 - end 5.1201 - end 5.1202 - end 5.1203 - else if(MA_RTY_I) 5.1204 - begin 5.1205 - if(var_length1) 5.1206 - begin 5.1207 - MA_CYC_O <= #UDLY 1'b0; 5.1208 - MA_STB_O <= #UDLY 1'b0; 5.1209 - MA_CTI_O <= #UDLY 3'h0; 5.1210 - status1 <= #UDLY ST_IDLE; 5.1211 - reg_status1 <= #UDLY 1'b0; 5.1212 - reg_interrupt1 <= #UDLY 1'b1; 5.1213 - start_flag <= #UDLY 1'b0; 5.1214 - end 5.1215 - end 5.1216 - else if(MA_ERR_I) 5.1217 - begin 5.1218 - MA_CYC_O <= #UDLY 1'b0; 5.1219 - MA_STB_O <= #UDLY 1'b0; 5.1220 - MA_CTI_O <= #UDLY 3'h0; 5.1221 - status1 <= #UDLY ST_IDLE; 5.1222 - reg_status1 <= #UDLY 1'b1; 5.1223 - reg_interrupt1 <= #UDLY 1'b1; 5.1224 - start_flag <= #UDLY 1'b0; 5.1225 - end 5.1226 - end 5.1227 - 5.1228 - default: 5.1229 - begin 5.1230 - status1 <= #UDLY ST_IDLE; 5.1231 - var_length1 <= #UDLY 1'b0; 5.1232 - MA_ADR_O <= #UDLY 32'h0; 5.1233 - MA_SEL_O <= #UDLY 4'b1111; 5.1234 - MA_CYC_O <= #UDLY 1'b0; 5.1235 - MA_CTI_O <= #UDLY 3'h0; 5.1236 - MA_STB_O <= #UDLY 1'b0; 5.1237 - reg_status1 <= #UDLY 1'b0; 5.1238 - reg_interrupt1 <= #UDLY 1'b0; 5.1239 - start_flag <= #UDLY 1'b0; 5.1240 - burst_size <= #UDLY 5'h0; 5.1241 - burst_cnt <= #UDLY 5'h0; 5.1242 - fifo_clear <= #UDLY 1'b0; 5.1243 - latch_start <= #UDLY 1'b0; 5.1244 - fifo_wr <= #UDLY 1'b0; 5.1245 - end 5.1246 - endcase 5.1247 - end 5.1248 - // Write Burst 5.1249 - if ((MA_RTY_I && (!(|data_length))) || (MA_ERR_I && (status1 == ST_READ))) 5.1250 - begin 5.1251 - status2 <= #UDLY ST_WRITE_IDLE; 5.1252 - donot_start_again <= #UDLY 1'b1; 5.1253 - end 5.1254 - else 5.1255 - begin 5.1256 - case(status2) 5.1257 - ST_WRITE_IDLE: 5.1258 - begin 5.1259 - if(reg_start) 5.1260 - begin 5.1261 - MB_ADR_O <= #UDLY reg_04_data; 5.1262 - case (reg_04_data[1:0]) 5.1263 - 2'b01: MB_SEL_O <= #UDLY {1'b0,M_SEL_O[3:1]}; 5.1264 - 2'b10: MB_SEL_O <= #UDLY {2'b00,M_SEL_O[3:2]}; 5.1265 - 2'b11: MB_SEL_O <= #UDLY {3'b00,M_SEL_O[3:3]}; 5.1266 - default: 5.1267 - MB_SEL_O <= #UDLY M_SEL_O; 5.1268 - endcase 5.1269 - if(!(|data_length)) 5.1270 - var_length2 <= #UDLY 1'b1; 5.1271 - else 5.1272 - var_length2 <= #UDLY 1'b0; 5.1273 - burst_size2 <= #UDLY reg_bt1 ? (reg_bt0 ? 5'h1f : 5'hf) : (reg_bt0 ? 5'h7 : 5'h3); 5.1274 - burst_cnt2 <= #UDLY reg_bt1 ? (reg_bt0 ? 5'h1f : 5'hf) : (reg_bt0 ? 5'h7 : 5'h3); 5.1275 - if(!fifo_empty) 5.1276 - status2 <= #UDLY ST_FIFO_EMPTY; 5.1277 - else 5.1278 - donot_start_again <= #UDLY 1'b0; 5.1279 - end 5.1280 - if(fifo_empty) 5.1281 - begin 5.1282 - if(MB_ACK_I) 5.1283 - begin 5.1284 - MB_CYC_O <= #UDLY 1'b0; 5.1285 - MB_STB_O <= #UDLY 1'b0; 5.1286 - MB_CTI_O <= #UDLY 3'h0; 5.1287 - fifo_rd <= #UDLY 1'b0; 5.1288 - end 5.1289 - burst_cnt2 <= #UDLY 5'h0; 5.1290 - end 5.1291 - else 5.1292 - begin 5.1293 - if(donot_start_again) 5.1294 - begin 5.1295 - if(MB_ACK_I) 5.1296 - begin 5.1297 - if(!reg_d_con) 5.1298 - MB_ADR_O <= #UDLY MB_ADR_O + incr_unit; 5.1299 - if (incr_unit == 3'b001) 5.1300 - MB_SEL_O <= #UDLY {MB_SEL_O[0], MB_SEL_O[3:1]}; 5.1301 - else 5.1302 - if (incr_unit == 3'b010) 5.1303 - MB_SEL_O <= #UDLY {MB_SEL_O[1:0], MB_SEL_O[3:2]}; 5.1304 - end 5.1305 - end 5.1306 - end 5.1307 - 5.1308 - if(!fifo_empty && !donot_start_again) 5.1309 - begin 5.1310 - if(start_flag) 5.1311 - begin 5.1312 - set_cti_b; 5.1313 - status2 <= #UDLY ST_WRITE_WAIT; 5.1314 - read_fifo; 5.1315 - burst_cnt2 <= #UDLY reg_bt1 ? (reg_bt0 ? 5'h1f : 5'hf) : (reg_bt0 ? 5'h7 : 5'h3); 5.1316 - end 5.1317 - else 5.1318 - begin 5.1319 - if(!reg_d_con) 5.1320 - MB_ADR_O <= #UDLY MB_ADR_O + incr_unit; 5.1321 - if (incr_unit == 3'b001) 5.1322 - MB_SEL_O <= #UDLY {MB_SEL_O[0], MB_SEL_O[3:1]}; 5.1323 - else 5.1324 - if (incr_unit == 3'b010) 5.1325 - MB_SEL_O <= #UDLY {MB_SEL_O[1:0], MB_SEL_O[3:2]}; 5.1326 - status2 <= #UDLY ST_WRADDR; 5.1327 - read_fifo; 5.1328 - burst_cnt2 <= #UDLY reg_bt1 ? (reg_bt0 ? 5'h1f : 5'hf) : (reg_bt0 ? 5'h7 : 5'h3); 5.1329 - end 5.1330 - end 5.1331 - end_of_transfer <= #UDLY 1'b0; 5.1332 - burst_completed <= #UDLY 1'b0; 5.1333 - reg_interrupt2 <= #UDLY 1'b0; 5.1334 - end 5.1335 - 5.1336 - ST_FIFO_EMPTY: 5.1337 - begin 5.1338 - if(fifo_empty) 5.1339 - begin 5.1340 - status2 <= #UDLY ST_WRITE_IDLE; 5.1341 - donot_start_again <= #UDLY 1'b0; 5.1342 - end 5.1343 - end 5.1344 - 5.1345 - ST_WRADDR: 5.1346 - begin 5.1347 - burst_cnt2 <= #UDLY burst_size2; 5.1348 - MB_CYC_O <= #UDLY 1'b1; 5.1349 - MB_STB_O <= #UDLY 1'b1; 5.1350 - 5.1351 - if (fifo_aempty && (burst_size2 > 5'h2)) 5.1352 - begin 5.1353 - MB_CTI_O <= #UDLY 3'b000; 5.1354 - status2 <= #UDLY ST_FIFO_AEMPTY; 5.1355 - fifo_rd <= #UDLY 1'b0; 5.1356 - end 5.1357 - else 5.1358 - begin 5.1359 - set_cti_b; 5.1360 - status2 <= #UDLY ST_WRITE; 5.1361 - end 5.1362 - end 5.1363 - 5.1364 - ST_WRITE_WAIT: 5.1365 - begin 5.1366 - MB_CYC_O <= #UDLY 1'b1; 5.1367 - MB_STB_O <= #UDLY 1'b1; 5.1368 - 5.1369 - if (fifo_aempty && (burst_size2 > 5'h2)) 5.1370 - begin 5.1371 - MB_CTI_O <= #UDLY 3'b000; 5.1372 - status2 <= #UDLY ST_FIFO_AEMPTY; 5.1373 - fifo_rd <= #UDLY 1'b0; 5.1374 - end 5.1375 - else 5.1376 - begin 5.1377 - set_cti_b; 5.1378 - status2 <= #UDLY ST_WRITE; 5.1379 - end 5.1380 - end 5.1381 - 5.1382 - ST_FIFO_AEMPTY: 5.1383 - begin 5.1384 - if (MB_ACK_I) 5.1385 - begin 5.1386 - MB_CYC_O <= #UDLY 1'b0; 5.1387 - MB_STB_O <= #UDLY 1'b0; 5.1388 - 5.1389 - burst_cnt2 <= #UDLY burst_cnt2 - 1; 5.1390 - 5.1391 - if (!reg_d_con) 5.1392 - MB_ADR_O <= #UDLY MB_ADR_O + incr_unit; 5.1393 - 5.1394 - if (incr_unit == 3'b001) 5.1395 - MB_SEL_O <= #UDLY {MB_SEL_O[0], MB_SEL_O[3:1]}; 5.1396 - else 5.1397 - if (incr_unit == 3'b010) 5.1398 - MB_SEL_O <= #UDLY {MB_SEL_O[1:0], MB_SEL_O[3:2]}; 5.1399 - end 5.1400 - 5.1401 - if (!MB_CYC_O && !fifo_aempty) 5.1402 - begin 5.1403 - status2 <= #UDLY ST_FIFO_RESUME; 5.1404 - read_fifo; 5.1405 - end 5.1406 - end 5.1407 - 5.1408 - ST_FIFO_RESUME: 5.1409 - begin 5.1410 - MB_CYC_O <= #UDLY 1'b1; 5.1411 - MB_STB_O <= #UDLY 1'b1; 5.1412 - 5.1413 - if (fifo_aempty && (burst_cnt2 > 5'h2)) 5.1414 - begin 5.1415 - MB_CTI_O <= #UDLY 3'b000; 5.1416 - status2 <= #UDLY ST_FIFO_AEMPTY; 5.1417 - fifo_rd <= #UDLY 1'b0; 5.1418 - end 5.1419 - else 5.1420 - begin 5.1421 - set_cti_b; 5.1422 - status2 <= #UDLY ST_WRITE; 5.1423 - end 5.1424 - end 5.1425 - 5.1426 - ST_WRITE: 5.1427 - begin 5.1428 - if (MB_ACK_I) 5.1429 - begin 5.1430 - if(var_length2) 5.1431 - begin 5.1432 - if(burst_cnt2 == 0) 5.1433 - begin 5.1434 - MB_CYC_O <= #UDLY 1'b0; 5.1435 - MB_STB_O <= #UDLY 1'b0; 5.1436 - MB_CTI_O <= #UDLY 3'h0; 5.1437 - end_of_transfer <= #UDLY 1'b1; 5.1438 - status2 <= #UDLY ST_WRITE_IDLE; 5.1439 - fifo_rd <= #UDLY 1'b0; 5.1440 - burst_cnt2 <= #UDLY burst_size2; 5.1441 - end 5.1442 - else 5.1443 - begin 5.1444 - if(burst_cnt2 == 1) 5.1445 - MB_CTI_O <= #UDLY 3'h7; 5.1446 - else 5.1447 - set_cti_b; 5.1448 - if(!reg_d_con) 5.1449 - MB_ADR_O <= #UDLY MB_ADR_O + incr_unit; 5.1450 - if (incr_unit == 3'b001) 5.1451 - MB_SEL_O <= #UDLY {MB_SEL_O[0], MB_SEL_O[3:1]}; 5.1452 - else 5.1453 - if (incr_unit == 3'b010) 5.1454 - MB_SEL_O <= #UDLY {MB_SEL_O[1:0], MB_SEL_O[3:2]}; 5.1455 - read_fifo; 5.1456 - burst_cnt2 <= #UDLY burst_cnt2 - 1; 5.1457 - end 5.1458 - end 5.1459 - else 5.1460 - begin 5.1461 - if(burst_cnt2 == 0) 5.1462 - begin 5.1463 - MB_CYC_O <= #UDLY 1'b0; 5.1464 - MB_STB_O <= #UDLY 1'b0; 5.1465 - MB_CTI_O <= #UDLY 3'h0; 5.1466 - reg_cntlg_burst <= #UDLY 1'b1; 5.1467 - status2 <= #UDLY ST_CNTLNGTH; 5.1468 - fifo_rd <= #UDLY 1'b0; 5.1469 - burst_cnt2 <= #UDLY burst_size2; 5.1470 - end 5.1471 - else 5.1472 - begin 5.1473 - if ((fifo_aempty && (burst_cnt2 > 5'h2)) || (burst_cnt2 == 5'h1)) 5.1474 - MB_CTI_O <= #UDLY 3'h7; 5.1475 - else 5.1476 - set_cti_b; 5.1477 - 5.1478 - burst_cnt2 <= #UDLY burst_cnt2 - 1; 5.1479 - 5.1480 - if(!reg_d_con) 5.1481 - MB_ADR_O <= #UDLY MB_ADR_O + incr_unit; 5.1482 - 5.1483 - if (incr_unit == 3'b001) 5.1484 - MB_SEL_O <= #UDLY {MB_SEL_O[0], MB_SEL_O[3:1]}; 5.1485 - else 5.1486 - if (incr_unit == 3'b010) 5.1487 - MB_SEL_O <= #UDLY {MB_SEL_O[1:0], MB_SEL_O[3:2]}; 5.1488 - 5.1489 - if (fifo_aempty && (burst_cnt2 > 5'h2)) 5.1490 - begin 5.1491 - status2 <= #UDLY ST_FIFO_AEMPTY; 5.1492 - fifo_rd <= 1'b0; 5.1493 - end 5.1494 - else 5.1495 - read_fifo; 5.1496 - end 5.1497 - end 5.1498 - end 5.1499 - 5.1500 - else if(MB_RTY_I) 5.1501 - begin 5.1502 - if(var_length2) 5.1503 - begin 5.1504 - MB_CYC_O <= #UDLY 1'b0; 5.1505 - MB_STB_O <= #UDLY 1'b0; 5.1506 - MB_CTI_O <= #UDLY 3'h0; 5.1507 - status2 <= #UDLY ST_WRITE_IDLE; 5.1508 - reg_status2 <= #UDLY 1'b0; 5.1509 - reg_interrupt2 <= #UDLY 1'b1; 5.1510 - var_length2 <= #UDLY 1'b0; 5.1511 - donot_start_again <= #UDLY 1'b1; 5.1512 - fifo_rd <= #UDLY 1'b0; 5.1513 - end 5.1514 - end // if (MB_RTY_I) 5.1515 - 5.1516 - else if(MB_ERR_I) 5.1517 - begin 5.1518 - MB_CYC_O <= #UDLY 1'b0; 5.1519 - MB_STB_O <= #UDLY 1'b0; 5.1520 - MB_CTI_O <= #UDLY 3'h0; 5.1521 - status2 <= #UDLY ST_WRITE_IDLE; 5.1522 - reg_status2 <= #UDLY 1'b1; 5.1523 - reg_interrupt2 <= #UDLY 1'b1; 5.1524 - donot_start_again <= #UDLY 1'b1; 5.1525 - fifo_rd <= #UDLY 1'b0; 5.1526 - end // if (MB_ERR_I) 5.1527 - 5.1528 - end 5.1529 - 5.1530 - ST_CNTLNGTH: 5.1531 - begin 5.1532 - reg_cntlg_burst <= #UDLY 1'b0; 5.1533 - status2 <= #UDLY ST_JUSTICE; 5.1534 - end 5.1535 - 5.1536 - ST_JUSTICE: 5.1537 - begin 5.1538 - if(!(|data_length)) 5.1539 - begin 5.1540 - status2 <= #UDLY ST_WRITE_IDLE; 5.1541 - reg_status2 <= #UDLY 1'b0; 5.1542 - reg_interrupt2 <= #UDLY 1'b1; 5.1543 - burst_completed <= #UDLY 1'b1; 5.1544 - end 5.1545 - else 5.1546 - begin 5.1547 - end_of_transfer <= #UDLY 1'b1; 5.1548 - status2 <= ST_WRITE_IDLE; 5.1549 - end 5.1550 - end 5.1551 - 5.1552 - default: 5.1553 - begin 5.1554 - status2 <= #UDLY ST_WRITE_IDLE; 5.1555 - MB_ADR_O <= #UDLY 32'h0; 5.1556 - MB_SEL_O <= #UDLY 4'b1111; 5.1557 - MB_CYC_O <= #UDLY 1'b0; 5.1558 - MB_CTI_O <= #UDLY 3'h0; 5.1559 - MB_STB_O <= #UDLY 1'b0; 5.1560 - reg_status2 <= #UDLY 1'b0; 5.1561 - reg_interrupt2 <= #UDLY 1'b0; 5.1562 - reg_cntlg_burst <= #UDLY 1'b0; 5.1563 - burst_size2 <= #UDLY 5'h0; 5.1564 - burst_cnt2 <= #UDLY 5'h0; 5.1565 - fifo_rd <= #UDLY 1'b0; 5.1566 - end_of_transfer <= #UDLY 1'b0; 5.1567 - var_length2 <= #UDLY 1'b0; 5.1568 - burst_completed <= #UDLY 1'b0; 5.1569 - donot_start_again <= #UDLY 1'b0; 5.1570 - end 5.1571 - endcase 5.1572 - end 5.1573 - end 5.1574 - else begin 5.1575 - // Read/Write Normal 5.1576 - case(status) 5.1577 - 5.1578 - ST_IDLE1: 5.1579 - begin 5.1580 - if(reg_start | latch_start) 5.1581 - begin 5.1582 - if(fifo_empty) 5.1583 - begin 5.1584 - if(latch_start) 5.1585 - latch_start <= #UDLY 1'b0; 5.1586 - status <= #UDLY ST_READ1; 5.1587 - MA_CYC_O <= #UDLY 1'b1; 5.1588 - MA_STB_O <= #UDLY 1'b1; 5.1589 - MA_ADR_O <= #UDLY reg_00_data; 5.1590 - case (reg_00_data[1:0]) 5.1591 - 2'b01: MA_SEL_O <= #UDLY {1'b0,M_SEL_O[3:1]}; 5.1592 - 2'b10: MA_SEL_O <= #UDLY {2'b00,M_SEL_O[3:2]}; 5.1593 - 2'b11: MA_SEL_O <= #UDLY {3'b00,M_SEL_O[3:3]}; 5.1594 - default: 5.1595 - MA_SEL_O <= #UDLY M_SEL_O; 5.1596 - endcase 5.1597 - MB_ADR_O <= #UDLY reg_04_data; 5.1598 - case (reg_04_data[1:0]) 5.1599 - 2'b01: MB_SEL_O <= #UDLY {1'b0,M_SEL_O[3:1]}; 5.1600 - 2'b10: MB_SEL_O <= #UDLY {2'b00,M_SEL_O[3:2]}; 5.1601 - 2'b11: MB_SEL_O <= #UDLY {3'b00,M_SEL_O[3:3]}; 5.1602 - default: 5.1603 - MB_SEL_O <= #UDLY M_SEL_O; 5.1604 - endcase 5.1605 - set_cti_a; 5.1606 - start_flag <= #UDLY 1'b1; 5.1607 - if(!(|data_length)) 5.1608 - var_length <= #UDLY 1'b1; 5.1609 - else 5.1610 - var_length <= #UDLY 1'b0; 5.1611 - burst_size <= #UDLY 5'h0; 5.1612 - burst_cnt <= #UDLY 5'h0; 5.1613 - end 5.1614 - else 5.1615 - begin 5.1616 - status <= #UDLY ST_RDFIFO1; 5.1617 - end 5.1618 - end 5.1619 - else 5.1620 - begin 5.1621 - status <= #UDLY ST_IDLE1; 5.1622 - end 5.1623 - reg_interrupt_normal <= #UDLY 1'b0; 5.1624 - end 5.1625 - ST_RDFIFO1: 5.1626 - begin 5.1627 - if(fifo_empty) 5.1628 - begin 5.1629 - status <= #UDLY ST_IDLE1; 5.1630 - fifo_clear <= #UDLY 1'b0; 5.1631 - latch_start <= #UDLY 1'b1; 5.1632 - end 5.1633 - else 5.1634 - fifo_clear <= #UDLY !fifo_clear; 5.1635 - end 5.1636 - 5.1637 - ST_RDADDR1: 5.1638 - begin 5.1639 - MA_CYC_O <= #UDLY 1'b1; 5.1640 - MA_STB_O <= #UDLY 1'b1; 5.1641 - set_cti_a; 5.1642 - status <= #UDLY ST_READ1; 5.1643 - direct_data <= #UDLY 1'b1; 5.1644 - end 5.1645 - 5.1646 - ST_READ1: 5.1647 - begin 5.1648 - if(!start_flag) 5.1649 - write_fifo; 5.1650 - if(MA_ACK_I) 5.1651 - begin 5.1652 - if(start_flag) 5.1653 - begin 5.1654 - MA_CYC_O <= #UDLY 1'b0; 5.1655 - MA_STB_O <= #UDLY 1'b0; 5.1656 - MA_CTI_O <= #UDLY 3'h0; 5.1657 - MB_CYC_O <= #UDLY 1'b1; 5.1658 - MB_STB_O <= #UDLY 1'b1; 5.1659 - set_cti_b; 5.1660 - status <= #UDLY ST_WRITE1; 5.1661 - start_flag <= #UDLY 1'b0; 5.1662 - burst_cnt <= #UDLY burst_size; 5.1663 - end 5.1664 - else 5.1665 - begin 5.1666 - MA_CYC_O <= #UDLY 1'b0; 5.1667 - MA_STB_O <= #UDLY 1'b0; 5.1668 - MA_CTI_O <= #UDLY 3'h0; 5.1669 - if(!reg_d_con) 5.1670 - begin 5.1671 - MB_ADR_O <= #UDLY MB_ADR_O + incr_unit; 5.1672 - if (incr_unit == 3'b001) 5.1673 - MB_SEL_O <= #UDLY {MB_SEL_O[0], MB_SEL_O[3:1]}; 5.1674 - else 5.1675 - if (incr_unit == 3'b010) 5.1676 - MB_SEL_O <= #UDLY {MB_SEL_O[1:0], MB_SEL_O[3:2]}; 5.1677 - end 5.1678 - status <= #UDLY ST_WRADDR1; 5.1679 - burst_cnt <= #UDLY burst_size; 5.1680 - end 5.1681 - end 5.1682 - else if(MA_RTY_I) 5.1683 - begin 5.1684 - if(var_length) 5.1685 - begin 5.1686 - MA_CYC_O <= #UDLY 1'b0; 5.1687 - MA_STB_O <= #UDLY 1'b0; 5.1688 - MA_CTI_O <= #UDLY 3'h0; 5.1689 - status <= #UDLY ST_IDLE1; 5.1690 - reg_status_normal <= #UDLY 1'b0; 5.1691 - reg_interrupt_normal <= #UDLY 1'b1; 5.1692 - end 5.1693 - end 5.1694 - else if(MA_ERR_I) 5.1695 - begin 5.1696 - MA_CYC_O <= #UDLY 1'b0; 5.1697 - MA_STB_O <= #UDLY 1'b0; 5.1698 - MA_CTI_O <= #UDLY 3'h0; 5.1699 - status <= #UDLY ST_IDLE1; 5.1700 - reg_status_normal <= #UDLY 1'b1; 5.1701 - reg_interrupt_normal <= #UDLY 1'b1; 5.1702 - end 5.1703 - end 5.1704 - 5.1705 - ST_WRADDR1: 5.1706 - begin 5.1707 - fifo_wr <= #UDLY 1'b0; 5.1708 - MB_CYC_O <= #UDLY 1'b1; 5.1709 - MB_STB_O <= #UDLY 1'b1; 5.1710 - burst_cnt <= #UDLY burst_size; 5.1711 - set_cti_b; 5.1712 - status <= #UDLY ST_WRITE1; 5.1713 - read_fifo; 5.1714 - end 5.1715 - 5.1716 - ST_WRITE1: 5.1717 - begin 5.1718 - if(fifo_wr) 5.1719 - fifo_wr <= #UDLY 1'b0; 5.1720 - if(MB_ACK_I) 5.1721 - begin 5.1722 - direct_data <= #UDLY 1'b0; 5.1723 - if(var_length) 5.1724 - begin 5.1725 - MB_CYC_O <= #UDLY 1'b0; 5.1726 - MB_STB_O <= #UDLY 1'b0; 5.1727 - MB_CTI_O <= #UDLY 3'h0; 5.1728 - if(!reg_s_con) 5.1729 - begin 5.1730 - MA_ADR_O <= #UDLY MA_ADR_O + incr_unit; 5.1731 - if (incr_unit == 3'b001) 5.1732 - MA_SEL_O <= #UDLY {MA_SEL_O[0], MA_SEL_O[3:1]}; 5.1733 - else 5.1734 - if (incr_unit == 3'b010) 5.1735 - MA_SEL_O <= #UDLY {MA_SEL_O[1:0], MA_SEL_O[3:2]}; 5.1736 - end 5.1737 - status <= #UDLY ST_RDADDR1; 5.1738 - fifo_rd <= #UDLY 1'b0; 5.1739 - burst_cnt <= #UDLY burst_size; 5.1740 - end 5.1741 - else 5.1742 - begin 5.1743 - MB_CYC_O <= #UDLY 1'b0; 5.1744 - MB_STB_O <= #UDLY 1'b0; 5.1745 - MB_CTI_O <= #UDLY 3'h0; 5.1746 - reg_cntlg_normal <= #UDLY 1'b1; 5.1747 - status <= #UDLY ST_CNTLNGTH1; 5.1748 - fifo_rd <= #UDLY 1'b0; 5.1749 - burst_cnt <= #UDLY burst_size; 5.1750 - end 5.1751 - end 5.1752 - else if(MB_RTY_I) 5.1753 - begin 5.1754 - if(var_length) 5.1755 - begin 5.1756 - MB_CYC_O <= #UDLY 1'b0; 5.1757 - MB_STB_O <= #UDLY 1'b0; 5.1758 - MB_CTI_O <= #UDLY 3'h0; 5.1759 - status <= #UDLY ST_IDLE1; 5.1760 - reg_status_normal <= #UDLY 1'b0; 5.1761 - reg_interrupt_normal <= #UDLY 1'b1; 5.1762 - var_length <= #UDLY 1'b0; 5.1763 - fifo_rd <= #UDLY 1'b0; 5.1764 - end 5.1765 - end 5.1766 - else if(MB_ERR_I) 5.1767 - begin 5.1768 - MB_CYC_O <= #UDLY 1'b0; 5.1769 - MB_STB_O <= #UDLY 1'b0; 5.1770 - MB_CTI_O <= #UDLY 3'h0; 5.1771 - status <= #UDLY ST_IDLE1; 5.1772 - reg_status_normal <= #UDLY 1'b1; 5.1773 - reg_interrupt_normal <= #UDLY 1'b1; 5.1774 - fifo_rd <= #UDLY 1'b0; 5.1775 - end 5.1776 - end 5.1777 - 5.1778 - ST_CNTLNGTH1: 5.1779 - begin 5.1780 - reg_cntlg_normal <= #UDLY 1'b0; 5.1781 - status <= #UDLY ST_JUSTICE1; 5.1782 - end 5.1783 - 5.1784 - ST_JUSTICE1: 5.1785 - begin 5.1786 - if(!(|data_length)) 5.1787 - begin 5.1788 - status <= #UDLY ST_IDLE1; 5.1789 - reg_status_normal <= #UDLY 1'b0; 5.1790 - reg_interrupt_normal <= #UDLY 1'b1; 5.1791 - end 5.1792 - else 5.1793 - begin 5.1794 - if(!reg_s_con) 5.1795 - begin 5.1796 - MA_ADR_O <= #UDLY MA_ADR_O + incr_unit; 5.1797 - if (incr_unit == 3'b001) 5.1798 - MA_SEL_O <= #UDLY {MA_SEL_O[0], MA_SEL_O[3:1]}; 5.1799 - else 5.1800 - if (incr_unit == 3'b010) 5.1801 - MA_SEL_O <= #UDLY {MA_SEL_O[1:0], MA_SEL_O[3:2]}; 5.1802 - end 5.1803 - status <= #UDLY ST_RDADDR1; 5.1804 - end 5.1805 - end 5.1806 - 5.1807 - default: 5.1808 - begin 5.1809 - status <= #UDLY ST_IDLE1; 5.1810 - var_length <= #UDLY 1'b0; 5.1811 - MA_CYC_O <= #UDLY 1'b0; 5.1812 - MA_CTI_O <= #UDLY 3'h0; 5.1813 - MB_CYC_O <= #UDLY 1'b0; 5.1814 - MB_CTI_O <= #UDLY 3'h0; 5.1815 - MA_STB_O <= #UDLY 1'b0; 5.1816 - MB_STB_O <= #UDLY 1'b0; 5.1817 - reg_status_normal <= #UDLY 1'b0; 5.1818 - reg_interrupt_normal <= #UDLY 1'b0; 5.1819 - reg_cntlg_normal <= #UDLY 1'b0; 5.1820 - burst_size <= #UDLY 3'h0; 5.1821 - burst_cnt <= #UDLY 3'h0; 5.1822 - fifo_wr <= #UDLY 1'b0; 5.1823 - fifo_rd <= #UDLY 1'b0; 5.1824 - fifo_clear <= #UDLY 1'b0; 5.1825 - latch_start <= #UDLY 1'b0; 5.1826 - direct_data <= #UDLY 1'b0; 5.1827 - end 5.1828 - endcase 5.1829 - end 5.1830 - end 5.1831 - 5.1832 - //Task for generating write enable to the FIFO 5.1833 - task write_fifo; 5.1834 - begin 5.1835 - if(MA_ACK_I) 5.1836 - begin 5.1837 - fifo_wr <= #UDLY 1'b1; 5.1838 - fifo_din <= #UDLY MA_DAT_I; 5.1839 - end 5.1840 - else 5.1841 - begin 5.1842 - fifo_wr <= #UDLY 1'b0; 5.1843 - end 5.1844 - end 5.1845 - endtask 5.1846 - 5.1847 - //Task for generating read enable signal to the FIFO 5.1848 - task read_fifo; 5.1849 - begin 5.1850 - fifo_rd <= #UDLY 1'b1; 5.1851 - end 5.1852 - endtask 5.1853 - 5.1854 - //Task for setting wishbone CTI signal for read 5.1855 - //master port depending upon whether request is for burst 5.1856 - //transfer or classic cycle. 5.1857 - task set_cti_a; 5.1858 - begin 5.1859 - if(reg_bt2) 5.1860 - begin 5.1861 - if(reg_s_con) 5.1862 - MA_CTI_O <= #UDLY 3'b001; 5.1863 - else 5.1864 - MA_CTI_O <= #UDLY 3'b010; 5.1865 - end 5.1866 - else 5.1867 - MA_CTI_O <= #UDLY 3'b000; 5.1868 - end 5.1869 - endtask 5.1870 - 5.1871 - //Task for setting wishbone CTI signal for write 5.1872 - //master port depending upon whether request is for burst 5.1873 - //transfer or classic cycle. 5.1874 - task set_cti_b; 5.1875 - begin 5.1876 - if(reg_bt2) begin 5.1877 - if(reg_d_con) 5.1878 - MB_CTI_O <= #UDLY 3'b001; 5.1879 - else 5.1880 - MB_CTI_O <= #UDLY 3'b010; 5.1881 - end else 5.1882 - MB_CTI_O <= #UDLY 3'b000; 5.1883 - end 5.1884 - endtask 5.1885 - 5.1886 - //RdEn 5.1887 - reg fifo_rd_dly; 5.1888 - always @(posedge CLK_I or posedge RST_I) 5.1889 - if(RST_I) 5.1890 - fifo_rd_dly <= #UDLY 1'b0; 5.1891 - else 5.1892 - fifo_rd_dly <= #UDLY fifo_rd; 5.1893 - 5.1894 - wire RdEn = fifo_rd & (!fifo_rd_dly | (reg_bt2 ? (burst_cnt2[5:0] != 5'b00000) : (burst_cnt[5:0] != 5'b00000)) & MB_ACK_I) | fifo_clear; 5.1895 - 5.1896 + /*---------------------------------------------------------------------- 5.1897 + FIFO Logic 5.1898 + ----------------------------------------------------------------------*/ 5.1899 + reg fifo_rd_en, fifo_wr_en; 5.1900 + always @(/*AUTOSENSE*/MA_ACK_I or MA_DAT_I or MB_ACK_I 5.1901 + or fifo_aempty or fifo_empty or rstate or wburst_count 5.1902 + or wstate) 5.1903 + begin 5.1904 + if (((wstate == WR_SINGLEA) && (fifo_empty == 1'b0)) 5.1905 + || ((wstate == WR_FIFO_CHECK) 5.1906 + && (((fifo_empty == 1'b0) && (wburst_count == 6'h0)) 5.1907 + || ((fifo_aempty == 1'b0) && (wburst_count >= 6'h1)))) 5.1908 + || ((wstate == WR_BURST) 5.1909 + && (/*(MB_CYC_O_d == 1'b0) 5.1910 + ||*/ (MB_ACK_I && (wburst_count >= 6'h1)))) 5.1911 + || ((wstate == WR_ERROR) && (fifo_empty == 1'b0)) 5.1912 + || ((wstate == WR_RETRY) && (fifo_empty == 1'b0))) 5.1913 + fifo_rd_en = 1'b1; 5.1914 + else 5.1915 + fifo_rd_en = 1'b0; 5.1916 + 5.1917 + if (MA_ACK_I 5.1918 + && ((rstate == RD_SINGLEA) || (rstate == RD_BURST))) 5.1919 + fifo_wr_en = 1'b1; 5.1920 + else 5.1921 + fifo_wr_en = 1'b0; 5.1922 + 5.1923 + fifo_din = MA_DAT_I; 5.1924 + end 5.1925 + 5.1926 generate 5.1927 if (lat_family == "SC" || lat_family == "SCM") begin 5.1928 + 5.1929 + pmi_fifo_dc 5.1930 + #(.pmi_data_width_w(MA_WB_DAT_WIDTH), 5.1931 + .pmi_data_width_r(MA_WB_DAT_WIDTH), 5.1932 + .pmi_data_depth_w(64), 5.1933 + .pmi_data_depth_r(64), 5.1934 + .pmi_full_flag(64), 5.1935 + .pmi_empty_flag(0), 5.1936 + .pmi_almost_full_flag(60), 5.1937 + .pmi_almost_empty_flag(4), 5.1938 + .pmi_regmode("noreg"), 5.1939 + .pmi_family(`LATTICE_FAMILY), 5.1940 + .module_type("pmi_fifo_dc"), 5.1941 + .pmi_implementation(FIFO_IMPLEMENTATION)) 5.1942 + dma_fifo_dc 5.1943 + ( 5.1944 + .Data(fifo_din), 5.1945 + .WrClock (CLK_I), 5.1946 + .RdClock (CLK_I), 5.1947 + .WrEn (fifo_wr_en), 5.1948 + .RdEn (fifo_rd_en), 5.1949 + .Reset (RST_I), 5.1950 + .RPReset (RST_I), 5.1951 + .Q (fifo_dout), 5.1952 + .Empty (fifo_empty), 5.1953 + .Full (), 5.1954 + .AlmostEmpty(), 5.1955 + .AlmostFull ()); 5.1956 + 5.1957 + end else if (lat_family == "MachXO2") begin 5.1958 + 5.1959 + pmi_fifo_dc 5.1960 + #(.pmi_data_width_w (MA_WB_DAT_WIDTH), 5.1961 + .pmi_data_width_r (MA_WB_DAT_WIDTH), 5.1962 + .pmi_data_depth_w (64), 5.1963 + .pmi_data_depth_r (64), 5.1964 + .pmi_full_flag (64), 5.1965 + .pmi_empty_flag (0), 5.1966 + .pmi_almost_full_flag (60), 5.1967 + .pmi_almost_empty_flag (1), 5.1968 + .pmi_regmode ("noreg"), 5.1969 + .pmi_family ("XO2"), 5.1970 + .module_type ("pmi_fifo_dc"), 5.1971 + .pmi_implementation (FIFO_IMPLEMENTATION)) 5.1972 + dma_fifo 5.1973 + (.Data (fifo_din), 5.1974 + .WrClock (CLK_I), 5.1975 + .RdClock (CLK_I), 5.1976 + .WrEn (fifo_wr_en), 5.1977 + .RdEn (fifo_rd_en), 5.1978 + .Reset (RST_I), 5.1979 + .RPReset (RST_I), 5.1980 + .Q (fifo_dout), 5.1981 + .Empty (fifo_empty), 5.1982 + .Full (), 5.1983 + .AlmostEmpty(fifo_aempty), 5.1984 + .AlmostFull ()); 5.1985 5.1986 - pmi_fifo_dc #(.pmi_data_width_w(32), 5.1987 - .pmi_data_width_r(32), 5.1988 - .pmi_data_depth_w(32), 5.1989 - .pmi_data_depth_r(32), 5.1990 - .pmi_full_flag(32), 5.1991 - .pmi_empty_flag(0), 5.1992 - .pmi_almost_full_flag(28), 5.1993 - .pmi_almost_empty_flag(4), 5.1994 - .pmi_regmode("noreg"), 5.1995 - .pmi_family(`LATTICE_FAMILY), 5.1996 - .module_type("pmi_fifo_dc"), 5.1997 - .pmi_implementation(FIFO_IMPLEMENTATION)) 5.1998 - dma_fifo_dc ( 5.1999 - .Data(fifo_din), 5.2000 - .WrClock(CLK_I), 5.2001 - .RdClock(CLK_I), 5.2002 - .WrEn (fifo_wr), 5.2003 - .RdEn (RdEn), 5.2004 - .Reset (RST_I), 5.2005 - .RPReset(RST_I), 5.2006 - .Q (fifo_dout), 5.2007 - .Empty (fifo_empty), 5.2008 - .Full (), 5.2009 - .AlmostEmpty (), 5.2010 - .AlmostFull ()); 5.2011 - 5.2012 - 5.2013 - 5.2014 end else begin 5.2015 - pmi_fifo #(.pmi_data_width(32), 5.2016 - .pmi_data_depth(32), 5.2017 - .pmi_full_flag(32), 5.2018 - .pmi_empty_flag(0), 5.2019 - .pmi_almost_full_flag(28), 5.2020 - .pmi_almost_empty_flag(1), 5.2021 - .pmi_regmode("noreg"), 5.2022 - .pmi_family(`LATTICE_FAMILY), 5.2023 - .module_type("pmi_fifo"), 5.2024 - .pmi_implementation(FIFO_IMPLEMENTATION)) 5.2025 - dma_fifo (.Data (fifo_din), 5.2026 - .Clock (CLK_I), 5.2027 - .WrEn (fifo_wr), 5.2028 - .RdEn (RdEn), 5.2029 - .Reset (RST_I), 5.2030 - .Q (fifo_dout), 5.2031 - .Empty (fifo_empty), 5.2032 - .Full (), 5.2033 - .AlmostEmpty (fifo_aempty), 5.2034 - .AlmostFull ()); 5.2035 - end 5.2036 + 5.2037 + pmi_fifo 5.2038 + #(.pmi_data_width(MA_WB_DAT_WIDTH), 5.2039 + .pmi_data_depth(64), 5.2040 + .pmi_full_flag(64), 5.2041 + .pmi_empty_flag(0), 5.2042 + .pmi_almost_full_flag(60), 5.2043 + .pmi_almost_empty_flag(1), 5.2044 + .pmi_regmode("noreg"), 5.2045 + .pmi_family(`LATTICE_FAMILY), 5.2046 + .module_type("pmi_fifo"), 5.2047 + .pmi_implementation(FIFO_IMPLEMENTATION)) 5.2048 + dma_fifo 5.2049 + (.Data (fifo_din), 5.2050 + .Clock (CLK_I), 5.2051 + .WrEn (fifo_wr_en), 5.2052 + .RdEn (fifo_rd_en), 5.2053 + .Reset (RST_I), 5.2054 + .Q (fifo_dout), 5.2055 + .Empty (fifo_empty), 5.2056 + .Full (), 5.2057 + .AlmostEmpty(fifo_aempty), 5.2058 + .AlmostFull ()); 5.2059 + 5.2060 + end 5.2061 + 5.2062 endgenerate 5.2063 5.2064 -endmodule // MASTER_CTRL 5.2065 +endmodule 5.2066 5.2067 -`endif // MASTER_CTRL_FILE 5.2068 +`endif // `ifndef MASTER_CTRL_FILE
6.1 --- a/rtl/verilog/slave_reg.v Fri Aug 13 10:43:05 2010 +0100 6.2 +++ b/rtl/verilog/slave_reg.v Sat Aug 06 01:48:48 2011 +0100 6.3 @@ -1,234 +1,475 @@ 6.4 -// ============================================================================= 6.5 -// COPYRIGHT NOTICE 6.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation 6.7 -// ALL RIGHTS RESERVED 6.8 -// This confidential and proprietary software may be used only as authorised by 6.9 -// a licensing agreement from Lattice Semiconductor Corporation. 6.10 -// The entire notice above must be reproduced on all authorized copies and 6.11 -// copies may only be made to the extent permitted by a licensing agreement from 6.12 -// Lattice Semiconductor Corporation. 6.13 +// ================================================================== 6.14 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 6.15 +// ------------------------------------------------------------------ 6.16 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 6.17 +// ALL RIGHTS RESERVED 6.18 +// ------------------------------------------------------------------ 6.19 +// 6.20 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 6.21 +// 6.22 +// Permission: 6.23 +// 6.24 +// Lattice Semiconductor grants permission to use this code 6.25 +// pursuant to the terms of the Lattice Semiconductor Corporation 6.26 +// Open Source License Agreement. 6.27 +// 6.28 +// Disclaimer: 6.29 // 6.30 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 6.31 -// 5555 NE Moore Court 408-826-6000 (other locations) 6.32 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 6.33 -// U.S.A email: techsupport@latticesemi.com 6.34 -// =============================================================================/ 6.35 +// Lattice Semiconductor provides no warranty regarding the use or 6.36 +// functionality of this code. It is the user's responsibility to 6.37 +// verify the user’s design for consistency and functionality through 6.38 +// the use of formal verification methods. 6.39 +// 6.40 +// -------------------------------------------------------------------- 6.41 +// 6.42 +// Lattice Semiconductor Corporation 6.43 +// 5555 NE Moore Court 6.44 +// Hillsboro, OR 97214 6.45 +// U.S.A 6.46 +// 6.47 +// TEL: 1-800-Lattice (USA and Canada) 6.48 +// 503-286-8001 (other locations) 6.49 +// 6.50 +// web: http://www.latticesemi.com/ 6.51 +// email: techsupport@latticesemi.com 6.52 +// 6.53 +// -------------------------------------------------------------------- 6.54 // FILE DETAILS 6.55 // Project : LM32 DMA Component 6.56 // File : slave_reg.v 6.57 // Title : DMA Slave controller 6.58 // Dependencies : None 6.59 +// : 6.60 // Version : 7.0 6.61 // : Initial Release 6.62 +// : 6.63 // Version : 7.0SP2, 3.0 6.64 -// 1. Read and Write channel of DMA controller are working in parallel, 6.65 -// due to that now as soon as FIFO is not empty write channel of the DMA 6.66 -// controller start writing data to the slave. 6.67 -// 2. Burst Size supported by DMA controller is increased to support bigger 6.68 -// burst (from current value of 4 and 8 to 16 and 32). Now 4 different type 6.69 -// of burst sizes are supported by the DMA controller 4, 8, 16 and 32. 6.70 -// For this Burst Size field of the control register is increased to 2 bits. 6.71 -// 3. Glitch is removed on the S_ACK_O signal. 6.72 +// : 1. Read and Write channel of DMA controller are working in 6.73 +// : parallel, due to that now as soon as FIFO is not empty 6.74 +// : write channel of the DMA controller start writing data 6.75 +// : to the slave. 6.76 +// : 2. Burst Size supported by DMA controller is increased to 6.77 +// : support bigger burst (from current value of 4 and 8 to 6.78 +// : 16 and 32). Now 4 different type of burst sizes are 6.79 +// : supported by the DMA controller 4, 8, 16 and 32. For 6.80 +// : this Burst Size field of the control register is 6.81 +// : increased to 2 bits. 6.82 +// : 3. Glitch is removed on the S_ACK_O signal. 6.83 +// : 6.84 // Version : 3.1 6.85 -// : Make DMA Engine compliant to Rule 3.100 of Wishbone Spec 6.86 -// : which defines alignement of bytes in sub-word transfers. 6.87 +// : 1. Make DMA Engine compliant to Rule 3.100 of Wishbone Spec 6.88 +// : which defines alignement of bytes in sub-word transfers. 6.89 +// : 2. Removed glitch that did not pause the burst write when 6.90 +// : the read burst was paused by the "read slave". 6.91 +// : 6.92 +// Version : 3.2 6.93 +// : 1. Support for 8/32-bit WISHBONE Data Bus. The Control and 6.94 +// : Read/Write Ports can be independently configured. 6.95 +// : 2. Support for burst size of 64. 6.96 +// : 6.97 +// Version : 3.3 6.98 +// : 1. Interrupt can be release by writing 0 to IE bit in the 6.99 +// : status register. 6.100 // ============================================================================= 6.101 6.102 `ifndef SLAVE_REG_FILE 6.103 `define SLAVE_REG_FILE 6.104 `include "system_conf.v" 6.105 module SLAVE_REG 6.106 - #(parameter LENGTH_WIDTH = 16, 6.107 + #(parameter S_WB_DAT_WIDTH = 32, 6.108 + parameter S_WB_ADR_WIDTH = 32, 6.109 + parameter MA_WB_DAT_WIDTH = 32, 6.110 + parameter MA_WB_ADR_WIDTH = 32, 6.111 + parameter RETRY_TIMEOUT = 16, 6.112 parameter FIFO_IMPLEMENTATION = "EBR") 6.113 - ( 6.114 - //slave port 6.115 - S_ADR_I, //32bits 6.116 - S_DAT_I, //32bits 6.117 - S_WE_I, 6.118 - S_STB_I, 6.119 - S_CYC_I, 6.120 - S_CTI_I, 6.121 - S_DAT_O, //32bits 6.122 - S_ACK_O, 6.123 - S_INT_O, 6.124 - //Master Address 6.125 -// MA_SEL_O, 6.126 -// MB_SEL_O, 6.127 - M_SEL_O, 6.128 - //internal signals 6.129 - reg_start, 6.130 - reg_status, 6.131 - reg_interrupt, 6.132 - reg_busy, 6.133 - data_length, 6.134 - reg_cntlg, 6.135 - reg_bt2,reg_bt1,reg_bt0, 6.136 - incr_unit, 6.137 - reg_s_con, 6.138 - reg_d_con, 6.139 - reg_00_data, 6.140 - reg_04_data, 6.141 - //system clock and reset 6.142 - CLK_I, 6.143 - RST_I 6.144 - ); 6.145 - 6.146 - input [31:0] S_ADR_I; 6.147 - input [31:0] S_DAT_I; //32bits 6.148 - input S_WE_I; 6.149 - input S_STB_I; 6.150 - input S_CYC_I; 6.151 - input [2:0] S_CTI_I; 6.152 - output [31:0] S_DAT_O; //32bits 6.153 - output S_ACK_O; 6.154 - output S_INT_O; //interrupt signal 6.155 - //Master Address 6.156 - output [3:0] M_SEL_O; 6.157 -// output [3:0] MA_SEL_O; 6.158 -// output [3:0] MB_SEL_O; 6.159 - //internal signals 6.160 - output reg_start; 6.161 - input reg_status; 6.162 - input reg_interrupt; 6.163 - input reg_busy; 6.164 - output [LENGTH_WIDTH-1:0] data_length; 6.165 - input reg_cntlg; 6.166 - output reg_bt2,reg_bt1,reg_bt0; 6.167 - output [2:0] incr_unit; 6.168 - output reg_s_con; 6.169 - output reg_d_con; 6.170 - output [31:0] reg_00_data; 6.171 - output [31:0] reg_04_data; 6.172 - 6.173 - //system clock and reset 6.174 - input CLK_I; 6.175 - input RST_I; 6.176 - 6.177 - parameter UDLY = 1; 6.178 - 6.179 - reg [31:0] reg_00_data; 6.180 - reg [31:0] reg_04_data; 6.181 - reg [LENGTH_WIDTH-1:0] reg_08_data; 6.182 - reg [6:0] reg_0c_data; 6.183 - 6.184 - reg [3:0] M_SEL_O; 6.185 -// wire [3:0] MA_SEL_O = M_SEL_O; 6.186 -// wire [3:0] MB_SEL_O = M_SEL_O; 6.187 - wire [LENGTH_WIDTH-1:0] data_length = reg_08_data; 6.188 - 6.189 - wire reg_bt2, reg_bt1, reg_bt0, reg_incw, reg_inchw, reg_d_con, reg_s_con; 6.190 - assign {reg_bt2,reg_bt1,reg_bt0,reg_incw,reg_inchw,reg_d_con,reg_s_con} = reg_0c_data; 6.191 - wire [2:0] incr_unit = reg_incw ? 4 : reg_inchw ? 2 : 1; 6.192 - 6.193 - wire [8:0] burst_incr_unit = reg_bt2 ? (reg_bt1 ? (reg_bt0 ? incr_unit<<5 : incr_unit<<4) : (reg_bt0 ? incr_unit<<3 : incr_unit<<2)) : incr_unit; 6.194 - reg reg_ie; 6.195 - wire [2:0] read_10_data = {reg_status,reg_ie,reg_busy}; 6.196 - 6.197 - wire reg_wr_rd = S_CYC_I && S_STB_I; 6.198 - 6.199 - wire master_idle = !reg_busy; 6.200 - reg s_ack_o_pre; 6.201 - wire S_ACK_O = s_ack_o_pre && S_CYC_I && S_STB_I; 6.202 + ( 6.203 + input CLK_I, 6.204 + input RST_I, 6.205 + 6.206 + // Slave port 6.207 + input [S_WB_ADR_WIDTH-1:0] S_ADR_I, 6.208 + input [S_WB_DAT_WIDTH-1:0] S_DAT_I, 6.209 + input [S_WB_DAT_WIDTH/8-1:0] S_SEL_I, 6.210 + input S_WE_I, 6.211 + input S_STB_I, 6.212 + input S_CYC_I, 6.213 + input [2:0] S_CTI_I, 6.214 + output [S_WB_DAT_WIDTH-1:0] S_DAT_O, 6.215 + output reg S_ACK_O, 6.216 + output reg S_INT_O, 6.217 + 6.218 + output reg reg_start, 6.219 + input reg_status, 6.220 + input reg_interrupt, 6.221 + input reg_busy, 6.222 + output reg reg_bt3, reg_bt2, reg_bt1, reg_bt0, 6.223 + output reg reg_s_con, reg_d_con, 6.224 + output reg reg_incw, reg_inchw, 6.225 + output reg [7:0] reg_rdelay, 6.226 + output reg [31:0] reg_00_data, 6.227 + output reg [31:0] reg_04_data, 6.228 + output reg [31:0] reg_08_data 6.229 + ); 6.230 + 6.231 + parameter UDLY = 1; 6.232 + 6.233 + reg [31:0] reg_00_data_nxt, reg_04_data_nxt, reg_08_data_nxt; 6.234 + reg [7:0] reg_0c_data, reg_0c_data_nxt; 6.235 + 6.236 + always @(/*AUTOSENSE*/reg_0c_data) 6.237 + begin 6.238 + //reg_rdelay = reg_0c_data[23:16]; 6.239 + reg_rdelay = RETRY_TIMEOUT; 6.240 + reg_bt3 = reg_0c_data[7]; 6.241 + reg_bt2 = reg_0c_data[6]; 6.242 + reg_bt1 = reg_0c_data[5]; 6.243 + reg_bt0 = reg_0c_data[4]; 6.244 + reg_incw = reg_0c_data[3]; 6.245 + reg_inchw = reg_0c_data[2]; 6.246 + reg_d_con = reg_0c_data[1]; 6.247 + reg_s_con = reg_0c_data[0]; 6.248 + end 6.249 + 6.250 + reg [2:0] read_10_data; 6.251 + reg reg_ie; 6.252 + always @(/*AUTOSENSE*/reg_busy or reg_ie or reg_status) 6.253 + begin 6.254 + read_10_data[2] = reg_status; 6.255 + read_10_data[1] = reg_ie; 6.256 + read_10_data[0] = reg_busy; 6.257 + end 6.258 + 6.259 + wire master_idle, reg_wr_rd, reg_wr, reg_rd; 6.260 + assign master_idle = ~reg_busy; 6.261 + assign reg_wr_rd = S_CYC_I & S_STB_I; 6.262 + assign reg_wr = reg_wr_rd & master_idle & S_WE_I & S_ACK_O; 6.263 + assign reg_rd = reg_wr_rd & ~S_WE_I & S_ACK_O; 6.264 + 6.265 + reg s_ack_o_pre, s_ack_o_pre_nxt; 6.266 + always @(/*AUTOSENSE*/S_CYC_I or S_STB_I or S_WE_I or master_idle 6.267 + or reg_wr_rd or s_ack_o_pre) 6.268 + begin 6.269 + if ((s_ack_o_pre == 1'b0) 6.270 + && ((master_idle && reg_wr_rd) 6.271 + || ((master_idle == 1'b0) && reg_wr_rd && (S_WE_I == 1'b0)))) 6.272 + s_ack_o_pre_nxt = 1'b1; 6.273 + else 6.274 + s_ack_o_pre_nxt = 1'b0; 6.275 + 6.276 + S_ACK_O = s_ack_o_pre && S_CYC_I && S_STB_I; 6.277 + end 6.278 6.279 always @(posedge CLK_I or posedge RST_I) 6.280 - if(RST_I) 6.281 - s_ack_o_pre <= #UDLY 1'b0; 6.282 - else if(((master_idle && reg_wr_rd) || (!master_idle && reg_wr_rd && !S_WE_I)) && (!s_ack_o_pre)) 6.283 - s_ack_o_pre <= #UDLY 1'b1; 6.284 - else 6.285 - s_ack_o_pre <= #UDLY 1'b0; 6.286 - 6.287 - 6.288 - //register write and read 6.289 - wire reg_wr = reg_wr_rd && S_WE_I && master_idle && S_ACK_O; 6.290 - wire reg_rd = reg_wr_rd && !S_WE_I && S_ACK_O; 6.291 - 6.292 - wire dw00_cs = (!(|S_ADR_I[5:2])); 6.293 - wire dw04_cs = (S_ADR_I[5:2] == 4'h1); 6.294 - wire dw08_cs = (S_ADR_I[5:2] == 4'h2); 6.295 - wire dw0c_cs = (S_ADR_I[5:2] == 4'h3); 6.296 - wire dw10_cs = (S_ADR_I[5:2] == 4'h4); 6.297 + if (RST_I) 6.298 + s_ack_o_pre <= #UDLY 1'b0; 6.299 + else 6.300 + s_ack_o_pre <= #UDLY s_ack_o_pre_nxt; 6.301 + 6.302 + wire dw00_cs, dw04_cs, dw08_cs, dw0c_cs, dw10_cs; 6.303 + assign dw00_cs = (S_ADR_I[5:2] == 4'h0); 6.304 + assign dw04_cs = (S_ADR_I[5:2] == 4'h1); 6.305 + assign dw08_cs = (S_ADR_I[5:2] == 4'h2); 6.306 + assign dw0c_cs = (S_ADR_I[5:2] == 4'h3); 6.307 + assign dw10_cs = (S_ADR_I[5:2] == 4'h4); 6.308 + 6.309 + wire [31:0] S_DAT_O_int = (dw00_cs 6.310 + ? reg_00_data 6.311 + : (dw04_cs 6.312 + ? reg_04_data 6.313 + : (dw08_cs 6.314 + ? reg_08_data 6.315 + : (dw0c_cs 6.316 + ? {4{reg_0c_data}} 6.317 + : (dw10_cs 6.318 + ? {4{5'h0,read_10_data}} 6.319 + : 32'h0))))); 6.320 + generate 6.321 + if (S_WB_DAT_WIDTH == 8) begin 6.322 + 6.323 + assign S_DAT_O = ((S_ADR_I[1:0] == 2'b00) 6.324 + ? S_DAT_O_int[31:24] 6.325 + : ((S_ADR_I[1:0] == 2'b01) 6.326 + ? S_DAT_O_int[23:16] 6.327 + : ((S_ADR_I[1:0] == 2'b10) 6.328 + ? S_DAT_O_int[15:8] 6.329 + : S_DAT_O_int[7:0]))); 6.330 + 6.331 + end 6.332 + else begin 6.333 + 6.334 + assign S_DAT_O = S_DAT_O_int; 6.335 + 6.336 + end 6.337 + endgenerate 6.338 + 6.339 + 6.340 + 6.341 + // Interrupt 6.342 + generate 6.343 + if (S_WB_DAT_WIDTH == 8) begin 6.344 + 6.345 + always @(posedge CLK_I or posedge RST_I) 6.346 + begin 6.347 + if(RST_I) 6.348 + S_INT_O <= #UDLY 1'b0; 6.349 + else if(reg_interrupt && reg_ie) 6.350 + S_INT_O <= #UDLY 1'b1; 6.351 + else if(dw10_cs && (reg_rd || (reg_wr && (S_DAT_I[1] == 1'b0)))) 6.352 + S_INT_O <= #UDLY 1'b0; 6.353 + end 6.354 + 6.355 + end 6.356 + else begin 6.357 + 6.358 + always @(posedge CLK_I or posedge RST_I) 6.359 + begin 6.360 + if(RST_I) 6.361 + S_INT_O <= #UDLY 1'b0; 6.362 + else if(reg_interrupt && reg_ie) 6.363 + S_INT_O <= #UDLY 1'b1; 6.364 + else if(dw10_cs && (reg_rd || (reg_wr && (S_DAT_I[25] == 1'b0)))) 6.365 + S_INT_O <= #UDLY 1'b0; 6.366 + end 6.367 + 6.368 + end 6.369 + endgenerate 6.370 + 6.371 + // reg_00 6.372 + generate 6.373 + if (S_WB_DAT_WIDTH == 8) begin 6.374 6.375 - //S_DAT_O 6.376 - wire [31:0] S_DAT_O = dw00_cs ? reg_00_data : 6.377 - dw04_cs ? reg_04_data : 6.378 - dw08_cs ? reg_08_data : 6.379 - dw0c_cs ? {24'h0,1'h0,reg_0c_data} : 6.380 - dw10_cs ? {24'h0,5'h0,read_10_data} : 32'h0; 6.381 + always @(/*AUTOSENSE*/S_ADR_I or S_DAT_I or dw00_cs 6.382 + or reg_00_data or reg_wr) 6.383 + begin 6.384 + if (dw00_cs && reg_wr) begin 6.385 + casez (S_ADR_I[1:0]) 6.386 + 2'b00: reg_00_data_nxt = { S_DAT_I[7:0], reg_00_data[23: 0]}; 6.387 + 2'b01: reg_00_data_nxt = {reg_00_data[31:24], S_DAT_I[7:0], reg_00_data[15: 0]}; 6.388 + 2'b10: reg_00_data_nxt = {reg_00_data[31:16], S_DAT_I[7:0], reg_00_data[ 7: 0]}; 6.389 + 2'b11: reg_00_data_nxt = {reg_00_data[31: 8], S_DAT_I[7:0] }; 6.390 + 6.391 + default: 6.392 + reg_00_data_nxt = reg_00_data; 6.393 + endcase 6.394 + end 6.395 + else 6.396 + reg_00_data_nxt = reg_00_data; 6.397 + end 6.398 + 6.399 + end 6.400 + else begin 6.401 + 6.402 + always @(/*AUTOSENSE*/S_DAT_I or S_SEL_I or dw00_cs 6.403 + or reg_00_data or reg_wr) 6.404 + begin 6.405 + if (dw00_cs && reg_wr) begin 6.406 + casez (S_SEL_I) 6.407 + 4'b1000: reg_00_data_nxt = { S_DAT_I[31:24], reg_00_data[23:0]}; 6.408 + 4'b0100: reg_00_data_nxt = {reg_00_data[31:24], S_DAT_I[23:16], reg_00_data[15:0]}; 6.409 + 4'b0010: reg_00_data_nxt = {reg_00_data[31:16], S_DAT_I[15: 8], reg_00_data[ 7:0]}; 6.410 + 4'b0001: reg_00_data_nxt = {reg_00_data[31: 8], S_DAT_I[ 7: 0] }; 6.411 + 4'b1111: reg_00_data_nxt = S_DAT_I[31: 0] ; 6.412 + 6.413 + default: 6.414 + reg_00_data_nxt = reg_00_data; 6.415 + endcase 6.416 + end 6.417 + else 6.418 + reg_00_data_nxt = reg_00_data; 6.419 + end 6.420 + 6.421 + end 6.422 + endgenerate 6.423 + 6.424 + always @(posedge CLK_I or posedge RST_I) 6.425 + if (RST_I) 6.426 + reg_00_data <= #UDLY 32'b0; 6.427 + else 6.428 + reg_00_data <= #UDLY reg_00_data_nxt; 6.429 + 6.430 + 6.431 + 6.432 + // reg_04 6.433 + generate 6.434 + if (S_WB_DAT_WIDTH == 8) begin 6.435 6.436 - always @(posedge CLK_I or posedge RST_I) 6.437 - if(RST_I) 6.438 - M_SEL_O <= #UDLY 4'h0; 6.439 - else if(data_length < incr_unit) 6.440 - case(data_length[2:0]) 6.441 - 1: M_SEL_O <= #UDLY 4'h8; 6.442 - 2: M_SEL_O <= #UDLY 4'hc; 6.443 - 3: M_SEL_O <= #UDLY 4'he; 6.444 - default:M_SEL_O <= #UDLY 4'hf; 6.445 - endcase 6.446 - else 6.447 - case(incr_unit) 6.448 - 1: M_SEL_O <= #UDLY 4'h8; 6.449 - 2: M_SEL_O <= #UDLY 4'hc; 6.450 - 4: M_SEL_O <= #UDLY 4'hf; 6.451 - default:M_SEL_O <= #UDLY 4'hf; 6.452 - endcase 6.453 - //interrupt 6.454 - reg S_INT_O; 6.455 + always @(/*AUTOSENSE*/S_ADR_I or S_DAT_I or dw04_cs 6.456 + or reg_04_data or reg_wr) 6.457 + begin 6.458 + if (dw04_cs && reg_wr) begin 6.459 + casez (S_ADR_I[1:0]) 6.460 + 2'b00: reg_04_data_nxt = { S_DAT_I[7:0], reg_04_data[23: 0]}; 6.461 + 2'b01: reg_04_data_nxt = {reg_04_data[31:24], S_DAT_I[7:0], reg_04_data[15: 0]}; 6.462 + 2'b10: reg_04_data_nxt = {reg_04_data[31:16], S_DAT_I[7:0], reg_04_data[ 7: 0]}; 6.463 + 2'b11: reg_04_data_nxt = {reg_04_data[31: 8], S_DAT_I[7:0] }; 6.464 + 6.465 + default: 6.466 + reg_04_data_nxt = reg_04_data; 6.467 + endcase 6.468 + end 6.469 + else 6.470 + reg_04_data_nxt = reg_04_data; 6.471 + end 6.472 + 6.473 + end 6.474 + else begin 6.475 + 6.476 + always @(/*AUTOSENSE*/S_DAT_I or S_SEL_I or dw04_cs 6.477 + or reg_04_data or reg_wr) 6.478 + begin 6.479 + if (dw04_cs && reg_wr) begin 6.480 + casez (S_SEL_I) 6.481 + 4'b1000: reg_04_data_nxt = { S_DAT_I[31:24], reg_04_data[23:0]}; 6.482 + 4'b0100: reg_04_data_nxt = {reg_04_data[31:24], S_DAT_I[23:16], reg_04_data[15:0]}; 6.483 + 4'b0010: reg_04_data_nxt = {reg_04_data[31:16], S_DAT_I[15: 8], reg_04_data[ 7:0]}; 6.484 + 4'b0001: reg_04_data_nxt = {reg_04_data[31: 8], S_DAT_I[ 7: 0] }; 6.485 + 4'b1111: reg_04_data_nxt = { S_DAT_I[31: 0] }; 6.486 + 6.487 + default: 6.488 + reg_04_data_nxt = reg_04_data; 6.489 + endcase 6.490 + end 6.491 + else 6.492 + reg_04_data_nxt = reg_04_data; 6.493 + end 6.494 + 6.495 + end 6.496 + endgenerate 6.497 + 6.498 always @(posedge CLK_I or posedge RST_I) 6.499 - if(RST_I) 6.500 - S_INT_O <= #UDLY 1'b0; 6.501 - else if(reg_interrupt && reg_ie) 6.502 - S_INT_O <= #UDLY 1'b1; 6.503 - else if(dw10_cs && reg_rd) 6.504 - S_INT_O <= #UDLY 1'b0; 6.505 + if (RST_I) 6.506 + reg_04_data <= #UDLY 32'b0; 6.507 + else 6.508 + reg_04_data <= #UDLY reg_04_data_nxt; 6.509 + 6.510 + 6.511 + 6.512 + // reg_08 6.513 + generate 6.514 + if (S_WB_DAT_WIDTH == 8) begin 6.515 6.516 - //reg_00 6.517 - always @(posedge CLK_I or posedge RST_I) 6.518 - if(RST_I) 6.519 - reg_00_data <= #UDLY 32'h0; 6.520 - else if(dw00_cs && reg_wr) 6.521 - reg_00_data <= #UDLY S_DAT_I; 6.522 - 6.523 - //reg_04 6.524 - always @(posedge CLK_I or posedge RST_I) 6.525 - if(RST_I) 6.526 - reg_04_data <= #UDLY 32'h0; 6.527 - else if(dw04_cs && reg_wr) 6.528 - reg_04_data <= #UDLY S_DAT_I; 6.529 - 6.530 - //reg_08 6.531 + always @(/*AUTOSENSE*/S_ADR_I or S_DAT_I or dw08_cs 6.532 + or reg_08_data or reg_wr) 6.533 + if (dw08_cs && reg_wr) begin 6.534 + casez (S_ADR_I[1:0]) 6.535 + 2'b00: reg_08_data_nxt = { S_DAT_I[7:0], reg_08_data[23: 0]}; 6.536 + 2'b01: reg_08_data_nxt = {reg_08_data[31:24], S_DAT_I[7:0], reg_08_data[15: 0]}; 6.537 + 2'b10: reg_08_data_nxt = {reg_08_data[31:16], S_DAT_I[7:0], reg_08_data[ 7: 0]}; 6.538 + 2'b11: reg_08_data_nxt = {reg_08_data[31: 8], S_DAT_I[7:0] }; 6.539 + 6.540 + default: 6.541 + reg_08_data_nxt = reg_08_data; 6.542 + endcase 6.543 + end 6.544 + 6.545 + end 6.546 + else begin 6.547 + 6.548 + always @(/*AUTOSENSE*/S_DAT_I or S_SEL_I or dw08_cs 6.549 + or reg_08_data or reg_wr) 6.550 + if (dw08_cs && reg_wr) begin 6.551 + casez (S_SEL_I) 6.552 + 4'b1000: reg_08_data_nxt = { S_DAT_I[31:24], reg_08_data[23:0]}; 6.553 + 4'b0100: reg_08_data_nxt = {reg_08_data[31:24], S_DAT_I[23:16], reg_08_data[15:0]}; 6.554 + 4'b0010: reg_08_data_nxt = {reg_08_data[31:16], S_DAT_I[15: 8], reg_08_data[ 7:0]}; 6.555 + 4'b0001: reg_08_data_nxt = {reg_08_data[31: 8], S_DAT_I[ 7: 0] }; 6.556 + 4'b1111: reg_08_data_nxt = { S_DAT_I[31: 0] }; 6.557 + 6.558 + default: 6.559 + reg_08_data_nxt = reg_08_data; 6.560 + endcase 6.561 + end 6.562 + 6.563 + end 6.564 + endgenerate 6.565 + 6.566 always @(posedge CLK_I or posedge RST_I) 6.567 - if(RST_I) 6.568 - reg_08_data <= #UDLY 32'h0; 6.569 - else if(reg_cntlg) 6.570 - reg_08_data <= #UDLY (reg_08_data < burst_incr_unit) ? 'h0 : (reg_08_data - burst_incr_unit); 6.571 - else if(dw08_cs && reg_wr) 6.572 - reg_08_data <= #UDLY S_DAT_I; 6.573 - 6.574 - //reg_0c 6.575 + if (RST_I) 6.576 + reg_08_data <= #UDLY 0; 6.577 + else 6.578 + reg_08_data <= #UDLY reg_08_data_nxt[31:0]; 6.579 + 6.580 + 6.581 + 6.582 + // reg_0c 6.583 + generate 6.584 + if (S_WB_DAT_WIDTH == 8) begin 6.585 + 6.586 + always @(/*AUTOSENSE*/S_DAT_I or dw0c_cs or reg_0c_data 6.587 + or reg_wr) 6.588 + if (dw0c_cs && reg_wr) 6.589 + reg_0c_data_nxt = S_DAT_I[7:0]; 6.590 + else 6.591 + reg_0c_data_nxt = reg_0c_data; 6.592 + 6.593 + end 6.594 + else begin 6.595 + 6.596 + always @(/*AUTOSENSE*/S_DAT_I or S_SEL_I or dw0c_cs 6.597 + or reg_0c_data or reg_wr) 6.598 + if (dw0c_cs && reg_wr) 6.599 + reg_0c_data_nxt = S_DAT_I[31:24]; 6.600 + else 6.601 + reg_0c_data_nxt = reg_0c_data; 6.602 + 6.603 + end 6.604 + endgenerate 6.605 + 6.606 always @(posedge CLK_I or posedge RST_I) 6.607 - if(RST_I) 6.608 - reg_0c_data <= #UDLY 7'h0; 6.609 - else if(dw0c_cs && reg_wr) 6.610 - reg_0c_data <= #UDLY S_DAT_I[6:0]; 6.611 - 6.612 - //reg_10 6.613 - reg reg_start; 6.614 + if (RST_I) 6.615 + reg_0c_data <= #UDLY 8'b0; 6.616 + else 6.617 + reg_0c_data <= #UDLY reg_0c_data_nxt; 6.618 + 6.619 + 6.620 + 6.621 + // reg_10 6.622 + reg reg_ie_nxt, reg_start_nxt; 6.623 + generate 6.624 + if (S_WB_DAT_WIDTH == 8) begin 6.625 + 6.626 + always @(/*AUTOSENSE*/S_DAT_I or dw10_cs or reg_ie or reg_wr) 6.627 + if (dw10_cs && reg_wr) 6.628 + begin 6.629 + reg_ie_nxt = S_DAT_I[1]; 6.630 + reg_start_nxt = S_DAT_I[3]; 6.631 + end 6.632 + else 6.633 + begin 6.634 + reg_ie_nxt = reg_ie; 6.635 + reg_start_nxt = 1'b0; 6.636 + end 6.637 + 6.638 + end 6.639 + else begin 6.640 + 6.641 + always @(/*AUTOSENSE*/S_DAT_I or S_SEL_I or dw10_cs or reg_ie 6.642 + or reg_wr) 6.643 + if (dw10_cs && reg_wr) 6.644 + begin 6.645 + reg_ie_nxt = S_DAT_I[25]; 6.646 + reg_start_nxt = S_DAT_I[27]; 6.647 + end 6.648 + else 6.649 + begin 6.650 + reg_ie_nxt = reg_ie; 6.651 + reg_start_nxt = 1'b0; 6.652 + end 6.653 + 6.654 + end 6.655 + endgenerate 6.656 + 6.657 always @(posedge CLK_I or posedge RST_I) 6.658 - if(RST_I) 6.659 + if (RST_I) 6.660 begin 6.661 - reg_ie <= #UDLY 1'b0; 6.662 - reg_start <= #UDLY 1'b0; 6.663 - end 6.664 - else if(dw10_cs && reg_wr) 6.665 + reg_ie <= #UDLY 1'b0; 6.666 + reg_start <= #UDLY 1'b0; 6.667 + end 6.668 + else 6.669 begin 6.670 - reg_ie <= #UDLY S_DAT_I[1]; 6.671 - reg_start <= #UDLY S_DAT_I[3]; 6.672 + reg_ie <= #UDLY reg_ie_nxt; 6.673 + reg_start <= #UDLY reg_start_nxt; 6.674 end 6.675 - else 6.676 - begin 6.677 - reg_start <= #UDLY 1'b0; 6.678 - end 6.679 + 6.680 endmodule // SLAVE_REG 6.681 `endif // SLAVE_REG_FILE
7.1 --- a/rtl/verilog/wb_dma_ctrl.v Fri Aug 13 10:43:05 2010 +0100 7.2 +++ b/rtl/verilog/wb_dma_ctrl.v Sat Aug 06 01:48:48 2011 +0100 7.3 @@ -1,237 +1,245 @@ 7.4 -// ============================================================================= 7.5 -// COPYRIGHT NOTICE 7.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation 7.7 -// ALL RIGHTS RESERVED 7.8 -// This confidential and proprietary software may be used only as authorised by 7.9 -// a licensing agreement from Lattice Semiconductor Corporation. 7.10 -// The entire notice above must be reproduced on all authorized copies and 7.11 -// copies may only be made to the extent permitted by a licensing agreement from 7.12 -// Lattice Semiconductor Corporation. 7.13 +// ================================================================== 7.14 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 7.15 +// ------------------------------------------------------------------ 7.16 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 7.17 +// ALL RIGHTS RESERVED 7.18 +// ------------------------------------------------------------------ 7.19 +// 7.20 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 7.21 +// 7.22 +// Permission: 7.23 +// 7.24 +// Lattice Semiconductor grants permission to use this code 7.25 +// pursuant to the terms of the Lattice Semiconductor Corporation 7.26 +// Open Source License Agreement. 7.27 +// 7.28 +// Disclaimer: 7.29 // 7.30 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 7.31 -// 5555 NE Moore Court 408-826-6000 (other locations) 7.32 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 7.33 -// U.S.A email: techsupport@latticesemi.com 7.34 -// =============================================================================/ 7.35 +// Lattice Semiconductor provides no warranty regarding the use or 7.36 +// functionality of this code. It is the user's responsibility to 7.37 +// verify the user’s design for consistency and functionality through 7.38 +// the use of formal verification methods. 7.39 +// 7.40 +// -------------------------------------------------------------------- 7.41 +// 7.42 +// Lattice Semiconductor Corporation 7.43 +// 5555 NE Moore Court 7.44 +// Hillsboro, OR 97214 7.45 +// U.S.A 7.46 +// 7.47 +// TEL: 1-800-Lattice (USA and Canada) 7.48 +// 503-286-8001 (other locations) 7.49 +// 7.50 +// web: http://www.latticesemi.com/ 7.51 +// email: techsupport@latticesemi.com 7.52 +// 7.53 +// -------------------------------------------------------------------- 7.54 // FILE DETAILS 7.55 // Project : LM32 DMA Component 7.56 // File : wb_dma_ctrl.v 7.57 // Title : DMA controller top file 7.58 // Dependencies : None 7.59 +// : 7.60 // Version : 7.0 7.61 // : Initial Release 7.62 +// : 7.63 // Version : 7.0SP2, 3.0 7.64 -// 1. Read and Write channel of DMA controller are working in parallel, 7.65 -// due to that now as soon as FIFO is not empty write channel of the DMA 7.66 -// controller start writing data to the slave. 7.67 -// 2. Burst Size supported by DMA controller is increased to support bigger 7.68 -// burst (from current value of 4 and 8 to 16 and 32). Now 4 different type 7.69 -// of burst sizes are supported by the DMA controller 4, 8, 16 and 32. 7.70 -// For this Burst Size field of the control register is increased to 2 bits. 7.71 -// 3. Glitch is removed on the S_ACK_O signal. 7.72 +// : 1. Read and Write channel of DMA controller are working in 7.73 +// : parallel, due to that now as soon as FIFO is not empty 7.74 +// : write channel of the DMA controller start writing data 7.75 +// : to the slave. 7.76 +// : 2. Burst Size supported by DMA controller is increased to 7.77 +// : support bigger burst (from current value of 4 and 8 to 7.78 +// : 16 and 32). Now 4 different type of burst sizes are 7.79 +// : supported by the DMA controller 4, 8, 16 and 32. For 7.80 +// : this Burst Size field of the control register is 7.81 +// : increased to 2 bits. 7.82 +// : 3. Glitch is removed on the S_ACK_O signal. 7.83 +// : 7.84 // Version : 3.1 7.85 // : Make DMA Engine compliant to Rule 3.100 of Wishbone Spec 7.86 // : which defines alignement of bytes in sub-word transfers. 7.87 +// : 7.88 +// Version : 3.2 7.89 +// : 1. Support for 8/32-bit WISHBONE Data Bus. The Control and 7.90 +// : Read/Write Ports can be independently configured. 7.91 +// : 2. Support for "retry" on receipt of a WISHBONE RTY. This 7.92 +// : retry results in the current burst or classic cycle 7.93 +// : being issued again after a retry timeout. 7.94 +// : 3. Support for "error" on receipt of a WISHBONE ERR. This 7.95 +// : results in the current dma transfer being terminated 7.96 +// : and the error is updated within the STATUS CSR. 7.97 +// : 4. Support for burst size of 64. 7.98 // ============================================================================= 7.99 7.100 `ifndef WB_DMA_CTRL_FILE 7.101 `define WB_DMA_CTRL_FILE 7.102 `include "system_conf.v" 7.103 -module wb_dma_ctrl #(parameter LENGTH_WIDTH = 16, 7.104 - parameter FIFO_IMPLEMENTATION = "EBR") 7.105 -( 7.106 - //master read port 7.107 - MA_ADR_O, //32bits 7.108 - MA_WE_O, 7.109 - MA_SEL_O, //4bits 7.110 - MA_STB_O, 7.111 - MA_CYC_O, 7.112 - MA_LOCK_O, 7.113 - MA_CTI_O, 7.114 - MA_BTE_O, 7.115 - MA_DAT_I, //32bits 7.116 - MA_DAT_O, //32bits 7.117 - MA_ACK_I, 7.118 - MA_ERR_I, 7.119 - MA_RTY_I, 7.120 - //master write port 7.121 - MB_ADR_O, //32bits 7.122 - MB_DAT_O, //32bits 7.123 - MB_WE_O, 7.124 - MB_SEL_O, //4bits 7.125 - MB_STB_O, 7.126 - MB_CYC_O, 7.127 - MB_LOCK_O, 7.128 - MB_CTI_O, 7.129 - MB_BTE_O, 7.130 - MB_DAT_I, //32bits 7.131 - MB_ACK_I, 7.132 - MB_ERR_I, 7.133 - MB_RTY_I, 7.134 - //slave port 7.135 - S_ADR_I, //32bits 7.136 - S_DAT_I, //32bits 7.137 - S_WE_I, 7.138 - S_STB_I, 7.139 - S_CYC_I, 7.140 - S_SEL_I, 7.141 - S_LOCK_I, 7.142 - S_CTI_I, 7.143 - S_BTE_I, 7.144 - S_DAT_O, //32bits 7.145 - S_ACK_O, 7.146 - S_ERR_O, 7.147 - S_RTY_O, 7.148 - S_INT_O, 7.149 - //system clock and reset 7.150 - CLK_I, 7.151 - RST_I 7.152 - ); 7.153 - //master read port 7.154 - output [31:0] MA_ADR_O; //32bits 7.155 - output MA_WE_O; 7.156 - output [3:0] MA_SEL_O; //4bits 7.157 - output MA_STB_O; 7.158 - output MA_CYC_O; 7.159 - output MA_LOCK_O; 7.160 - output [2:0] MA_CTI_O; 7.161 - output [1:0] MA_BTE_O; 7.162 - output [31:0] MA_DAT_O; //32bits 7.163 - input [31:0] MA_DAT_I; //32bits 7.164 - input MA_ACK_I; 7.165 - input MA_ERR_I; 7.166 - input MA_RTY_I; 7.167 - //master write port 7.168 - output [31:0] MB_ADR_O; //32bits 7.169 - output [31:0] MB_DAT_O; //32bits 7.170 - output MB_WE_O; 7.171 - output [3:0] MB_SEL_O; //4bits 7.172 - output MB_STB_O; 7.173 - output MB_CYC_O; 7.174 - output [2:0] MB_CTI_O; 7.175 - output MB_LOCK_O; 7.176 - output [1:0] MB_BTE_O; 7.177 - input [31:0] MB_DAT_I; //32bits 7.178 - input MB_ACK_I; 7.179 - input MB_ERR_I; 7.180 - input MB_RTY_I; 7.181 - //slave port 7.182 - input [31:0] S_ADR_I; //32bits 7.183 - input [31:0] S_DAT_I; //32bits 7.184 - input S_WE_I; 7.185 - input S_STB_I; 7.186 - input S_CYC_I; 7.187 - input [2:0] S_CTI_I; 7.188 - input [1:0] S_BTE_I; 7.189 - input [3:0] S_SEL_I; 7.190 - input S_LOCK_I; 7.191 - output [31:0] S_DAT_O; //32bits 7.192 - output S_ACK_O; 7.193 - output S_ERR_O; 7.194 - output S_RTY_O; 7.195 - output S_INT_O; 7.196 - //system clock and reset 7.197 - input CLK_I; 7.198 - input RST_I; 7.199 - 7.200 - wire [31:0] MA_DAT_O = 0; 7.201 - wire [1:0] MA_BTE_O = 0; 7.202 - wire MA_LOCK_O; 7.203 +module wb_dma_ctrl 7.204 + #(parameter S_WB_DAT_WIDTH = 32, 7.205 + parameter S_WB_ADR_WIDTH = 32, 7.206 + parameter MA_WB_DAT_WIDTH = 32, 7.207 + parameter MA_WB_ADR_WIDTH = 32, 7.208 + parameter MB_WB_DAT_WIDTH = 32, 7.209 + parameter MB_WB_ADR_WIDTH = 32, 7.210 + parameter RETRY_TIMEOUT = 16, 7.211 + parameter FIFO_IMPLEMENTATION = "EBR") 7.212 + ( 7.213 + // master read port 7.214 + output [MA_WB_ADR_WIDTH-1:0] MA_ADR_O, 7.215 + output MA_WE_O, 7.216 + output [MA_WB_DAT_WIDTH/8-1:0] MA_SEL_O, 7.217 + output MA_STB_O, 7.218 + output MA_CYC_O, 7.219 + output MA_LOCK_O, 7.220 + output [2:0] MA_CTI_O, 7.221 + output [1:0] MA_BTE_O, 7.222 + output [MA_WB_DAT_WIDTH-1:0] MA_DAT_O, 7.223 + input [MA_WB_DAT_WIDTH-1:0] MA_DAT_I, 7.224 + input MA_ACK_I, 7.225 + input MA_ERR_I, 7.226 + input MA_RTY_I, 7.227 + // master write port 7.228 + output [MB_WB_ADR_WIDTH-1:0] MB_ADR_O, 7.229 + output [MB_WB_DAT_WIDTH-1:0] MB_DAT_O, 7.230 + output MB_WE_O, 7.231 + output [MB_WB_DAT_WIDTH/8-1:0] MB_SEL_O, 7.232 + output MB_STB_O, 7.233 + output MB_CYC_O, 7.234 + output MB_LOCK_O, 7.235 + output [2:0] MB_CTI_O, 7.236 + output [1:0] MB_BTE_O, 7.237 + input [MB_WB_DAT_WIDTH-1:0] MB_DAT_I, 7.238 + input MB_ACK_I, 7.239 + input MB_ERR_I, 7.240 + input MB_RTY_I, 7.241 + // slave port 7.242 + input [S_WB_ADR_WIDTH-1:0] S_ADR_I, 7.243 + input [S_WB_DAT_WIDTH-1:0] S_DAT_I, 7.244 + input S_WE_I, 7.245 + input S_STB_I, 7.246 + input S_CYC_I, 7.247 + input [S_WB_DAT_WIDTH/8-1:0] S_SEL_I, 7.248 + input S_LOCK_I, 7.249 + input [2:0] S_CTI_I, 7.250 + input [1:0] S_BTE_I, 7.251 + output [S_WB_DAT_WIDTH-1:0] S_DAT_O, 7.252 + output S_ACK_O, 7.253 + output S_ERR_O, 7.254 + output S_RTY_O, 7.255 + output S_INT_O, 7.256 + // system clock and reset 7.257 + input CLK_I, 7.258 + input RST_I 7.259 + ); 7.260 + 7.261 + assign MA_BTE_O = 0; 7.262 + assign MB_BTE_O = 0; 7.263 + assign S_ERR_O = 0; 7.264 + assign S_RTY_O = 0; 7.265 + 7.266 + wire [31:0] reg_00_data; 7.267 + wire [31:0] reg_04_data; 7.268 + wire [31:0] reg_08_data; 7.269 + wire [7:0] reg_rdelay; 7.270 7.271 - wire [1:0] MB_BTE_O = 0; 7.272 - wire MB_LOCK_O; 7.273 - 7.274 - wire S_ERR_O = 0; 7.275 - wire S_RTY_O = 0; 7.276 - 7.277 - wire [LENGTH_WIDTH-1:0] data_length;//read back data 7.278 - wire [2:0] incr_unit; 7.279 - wire [31:0] reg_00_data; 7.280 - wire [31:0] reg_04_data; 7.281 - wire [3:0] M_SEL_O; 7.282 - 7.283 - //slave port:master write/read data to/from register file. 7.284 - SLAVE_REG #(.LENGTH_WIDTH(LENGTH_WIDTH), 7.285 - .FIFO_IMPLEMENTATION(FIFO_IMPLEMENTATION)) SLAVE_REG( 7.286 - .S_ADR_I (S_ADR_I ), 7.287 - .S_DAT_I (S_DAT_I ), 7.288 - .S_WE_I (S_WE_I ), 7.289 - .S_STB_I (S_STB_I ), 7.290 - .S_CYC_I (S_CYC_I ), 7.291 - .S_CTI_I (S_CTI_I ), 7.292 - .S_DAT_O (S_DAT_O ), 7.293 - .S_ACK_O (S_ACK_O ), 7.294 - .S_INT_O (S_INT_O ), 7.295 - //Master Addr 7.296 - .M_SEL_O (M_SEL_O ), 7.297 -// .MA_SEL_O (MA_SEL_O ), 7.298 -// .MB_SEL_O (MB_SEL_O ), 7.299 - //internal signals 7.300 - .reg_start (reg_start ), 7.301 - .reg_status (reg_status ), 7.302 - .reg_interrupt (reg_interrupt ), 7.303 - .reg_busy (reg_busy ), 7.304 - .data_length (data_length ), 7.305 - .reg_cntlg (reg_cntlg ), 7.306 - .reg_bt2 (reg_bt2 ), 7.307 - .reg_bt1 (reg_bt1 ), 7.308 - .reg_bt0 (reg_bt0 ), 7.309 - .reg_s_con (reg_s_con ), 7.310 - .reg_d_con (reg_d_con ), 7.311 - .incr_unit (incr_unit ), 7.312 - .reg_00_data (reg_00_data ), 7.313 - .reg_04_data (reg_04_data ), 7.314 - //system clock and reset 7.315 - .CLK_I (CLK_I ), 7.316 - .RST_I (RST_I ) 7.317 - ); 7.318 + // slave port:master write/read data to/from register file. 7.319 + SLAVE_REG 7.320 + #(.S_WB_DAT_WIDTH (S_WB_DAT_WIDTH), 7.321 + .S_WB_ADR_WIDTH (S_WB_ADR_WIDTH), 7.322 + .FIFO_IMPLEMENTATION (FIFO_IMPLEMENTATION) 7.323 + ) 7.324 + SLAVE_REG 7.325 + ( 7.326 + .S_ADR_I (S_ADR_I ), 7.327 + .S_DAT_I (S_DAT_I ), 7.328 + .S_SEL_I (S_SEL_I ), 7.329 + .S_WE_I (S_WE_I ), 7.330 + .S_STB_I (S_STB_I ), 7.331 + .S_CYC_I (S_CYC_I ), 7.332 + .S_CTI_I (S_CTI_I ), 7.333 + .S_DAT_O (S_DAT_O ), 7.334 + .S_ACK_O (S_ACK_O ), 7.335 + .S_INT_O (S_INT_O ), 7.336 + // internal signals 7.337 + .reg_start (reg_start ), 7.338 + .reg_status (reg_status ), 7.339 + .reg_interrupt (reg_interrupt ), 7.340 + .reg_busy (reg_busy ), 7.341 + .reg_bt3 (reg_bt3 ), 7.342 + .reg_bt2 (reg_bt2 ), 7.343 + .reg_bt1 (reg_bt1 ), 7.344 + .reg_bt0 (reg_bt0 ), 7.345 + .reg_s_con (reg_s_con ), 7.346 + .reg_d_con (reg_d_con ), 7.347 + .reg_incw (reg_incw ), 7.348 + .reg_inchw (reg_inchw ), 7.349 + .reg_rdelay (reg_rdelay ), 7.350 + .reg_00_data (reg_00_data ), 7.351 + .reg_04_data (reg_04_data ), 7.352 + .reg_08_data (reg_08_data ), 7.353 + // system clock and reset 7.354 + .CLK_I (CLK_I ), 7.355 + .RST_I (RST_I ) 7.356 + ); 7.357 7.358 - //Master control 7.359 - MASTER_CTRL #(.LENGTH_WIDTH(LENGTH_WIDTH), 7.360 - .FIFO_IMPLEMENTATION(FIFO_IMPLEMENTATION)) MASTER_CTRL( 7.361 - //master read port 7.362 - .MA_ADR_O (MA_ADR_O ), 7.363 - .MA_SEL_O (MA_SEL_O ), 7.364 - .MA_WE_O (MA_WE_O ), 7.365 - .MA_STB_O (MA_STB_O ), 7.366 - .MA_CYC_O (MA_CYC_O ), 7.367 - .MA_CTI_O (MA_CTI_O ), 7.368 - .MA_LOCK_O (MA_LOCK_O ), 7.369 - .MA_DAT_I (MA_DAT_I ), //32bits 7.370 - .MA_ACK_I (MA_ACK_I ), 7.371 - .MA_ERR_I (MA_ERR_I ), 7.372 - .MA_RTY_I (MA_RTY_I ), 7.373 - //master write port 7.374 - .MB_ADR_O (MB_ADR_O ), 7.375 - .MB_SEL_O (MB_SEL_O ), 7.376 - .MB_DAT_O (MB_DAT_O ), //32bits 7.377 - .MB_WE_O (MB_WE_O ), 7.378 - .MB_STB_O (MB_STB_O ), 7.379 - .MB_CYC_O (MB_CYC_O ), 7.380 - .MB_CTI_O (MB_CTI_O ), 7.381 - .MB_LOCK_O (MB_LOCK_O ), 7.382 - .MB_ACK_I (MB_ACK_I ), 7.383 - .MB_ERR_I (MB_ERR_I ), 7.384 - .MB_RTY_I (MB_RTY_I ), 7.385 - //register interface 7.386 - .M_SEL_O (M_SEL_O ), 7.387 - .reg_start (reg_start ), 7.388 - .reg_status (reg_status ), 7.389 - .reg_interrupt (reg_interrupt ), 7.390 - .reg_busy (reg_busy ), 7.391 - .data_length (data_length ), 7.392 - .reg_cntlg (reg_cntlg ), 7.393 - .reg_bt2 (reg_bt2 ), 7.394 - .reg_bt1 (reg_bt1 ), 7.395 - .reg_bt0 (reg_bt0 ), 7.396 - .reg_s_con (reg_s_con ), 7.397 - .reg_d_con (reg_d_con ), 7.398 - .incr_unit (incr_unit ), 7.399 - .reg_00_data (reg_00_data ), 7.400 - .reg_04_data (reg_04_data ), 7.401 - //system clock and reset 7.402 - .CLK_I (CLK_I ), 7.403 - .RST_I (RST_I ) 7.404 - ); 7.405 + // Master control 7.406 + MASTER_CTRL 7.407 + #(.MA_WB_DAT_WIDTH (MA_WB_DAT_WIDTH), 7.408 + .MA_WB_ADR_WIDTH (MA_WB_ADR_WIDTH), 7.409 + .MB_WB_DAT_WIDTH (MB_WB_DAT_WIDTH), 7.410 + .MB_WB_ADR_WIDTH (MB_WB_ADR_WIDTH), 7.411 + .S_WB_DAT_WIDTH (S_WB_DAT_WIDTH), 7.412 + .FIFO_IMPLEMENTATION (FIFO_IMPLEMENTATION) 7.413 + ) 7.414 + MASTER_CTRL 7.415 + ( 7.416 + // master read port 7.417 + .MA_ADR_O (MA_ADR_O ), 7.418 + .MA_SEL_O (MA_SEL_O ), 7.419 + .MA_DAT_O (MA_DAT_O ), 7.420 + .MA_WE_O (MA_WE_O ), 7.421 + .MA_STB_O (MA_STB_O ), 7.422 + .MA_CYC_O (MA_CYC_O ), 7.423 + .MA_CTI_O (MA_CTI_O ), 7.424 + .MA_LOCK_O (MA_LOCK_O ), 7.425 + .MA_DAT_I (MA_DAT_I ), 7.426 + .MA_ACK_I (MA_ACK_I ), 7.427 + .MA_ERR_I (MA_ERR_I ), 7.428 + .MA_RTY_I (MA_RTY_I ), 7.429 + // master write port 7.430 + .MB_ADR_O (MB_ADR_O ), 7.431 + .MB_SEL_O (MB_SEL_O ), 7.432 + .MB_DAT_O (MB_DAT_O ), 7.433 + .MB_WE_O (MB_WE_O ), 7.434 + .MB_STB_O (MB_STB_O ), 7.435 + .MB_CYC_O (MB_CYC_O ), 7.436 + .MB_CTI_O (MB_CTI_O ), 7.437 + .MB_LOCK_O (MB_LOCK_O ), 7.438 + .MB_ACK_I (MB_ACK_I ), 7.439 + .MB_ERR_I (MB_ERR_I ), 7.440 + .MB_RTY_I (MB_RTY_I ), 7.441 + // register interface 7.442 + .reg_start (reg_start ), 7.443 + .reg_busy (reg_busy ), 7.444 + .reg_status (reg_status ), 7.445 + .reg_interrupt (reg_interrupt ), 7.446 + .reg_bt3 (reg_bt3 ), 7.447 + .reg_bt2 (reg_bt2 ), 7.448 + .reg_bt1 (reg_bt1 ), 7.449 + .reg_bt0 (reg_bt0 ), 7.450 + .reg_s_con (reg_s_con ), 7.451 + .reg_d_con (reg_d_con ), 7.452 + .reg_incw (reg_incw ), 7.453 + .reg_inchw (reg_inchw ), 7.454 + .reg_rdelay (reg_rdelay ), 7.455 + .reg_00_data (reg_00_data ), 7.456 + .reg_04_data (reg_04_data ), 7.457 + .reg_08_data (reg_08_data ), 7.458 + // system clock and reset 7.459 + .CLK_I (CLK_I ), 7.460 + .RST_I (RST_I ) 7.461 + ); 7.462 + 7.463 endmodule // WB_DMA_CTRL 7.464 `endif // WB_DMA_CTRL_FILE