IPCores/lm32_gpio / files

     1.1 --- a/document/gpio.htm	Fri Aug 13 10:41:29 2010 +0100
     1.2 +++ b/document/gpio.htm	Sat Aug 06 01:43:24 2011 +0100
     1.3 @@ -113,10 +113,10 @@
     1.4  	writeIntopicBar(4);
     1.5  //-->
     1.6  </script>
     1.7 -<h1>LatticeMico32 GPIO &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<a title="View Data Sheet" href="gpio.pdf" target="_blank" onmouseover="if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) ehlp_showtip(this,event,'View Data Sheet');" onmouseout="if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) ehlp_hidetip();"><img src="ds_icon_ast.jpg" x-maintain-ratio="TRUE" width="29px" height="31px" border="0" class="img_whs1"></a></h1>
     1.8 +<h1>LatticeMico GPIO &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<a title="View Data Sheet" href="gpio.pdf" target="_blank" onmouseover="if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) ehlp_showtip(this,event,'View Data Sheet');" onmouseout="if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) ehlp_hidetip();"><img src="ds_icon_ast.jpg" x-maintain-ratio="TRUE" width="29px" height="31px" border="0" class="img_whs1"></a></h1>
     1.9  
    1.10 -<p>The LatticeMico32 general-purpose input/output core (GPIO) provides 
    1.11 - a memory-mapped interface between a WISHBONE slave port and general-purpose 
    1.12 +<p>The LatticeMico general-purpose input/output core (GPIO) provides a 
    1.13 + memory-mapped interface between a WISHBONE slave port and general-purpose 
    1.14   I/O ports. The I/O ports can connect to either on-chip or off-chip logic.</p>
    1.15  
    1.16  <p class="whs2">*If the data sheet fails to open, see the 
    1.17 @@ -144,6 +144,22 @@
    1.18  <tr valign="top" class="whs6">
    1.19  <td colspan="1" rowspan="1" width="85px" class="whs9">
    1.20  <p class=Table
    1.21 +	style="font-weight: normal;">3.3</td>
    1.22 +<td colspan="1" rowspan="1" width="505px" class="whs10">
    1.23 +<p class=Table>Added software support for LatticeMico8.
    1.24 +</td></tr>
    1.25 +
    1.26 +<tr valign="top" class="whs6">
    1.27 +<td colspan="1" rowspan="1" width="85px" class="whs9">
    1.28 +<p class=Table
    1.29 +	style="font-weight: normal;">3.2 (8.1 SP1)</td>
    1.30 +<td colspan="1" rowspan="1" width="505px" class="whs10">
    1.31 +<p class=Table>WISHBONE data bus size is configurable to 8 or 32 bits. 
    1.32 + Register map is updated to accommodate 8/32-bit WISHBONE data bus. </td></tr>
    1.33 +
    1.34 +<tr valign="top" class="whs6">
    1.35 +<td colspan="1" rowspan="1" width="85px" class="whs9">
    1.36 +<p class=Table
    1.37  	style="font-weight: normal;">3.1 (7.2)</td>
    1.38  <td colspan="1" rowspan="1" width="505px" class="whs10">
    1.39  <p class=Table>Updated the Edge Capture Register clean method</p>
    1.40 @@ -313,6 +329,19 @@
    1.41  <td colspan="1" rowspan="1" width="503px" class="whs17">
    1.42  <p class=Table>Generates an IRQ on high-to-low transitions. This option 
    1.43   is deselected by default.</td></tr>
    1.44 +
    1.45 +<tr valign="top" class="whs13">
    1.46 +<td colspan="2" rowspan="1" width="85px" class="whs16">
    1.47 +<p class=Table
    1.48 +	style="font-weight: bold;">WISHBONE Configuration</td>
    1.49 +</tr>
    1.50 +
    1.51 +<tr valign="top" class="whs13">
    1.52 +<td colspan="1" rowspan="1" width="85px" class="whs16">
    1.53 +<p class=Table>WISHBONE Data Bus Width</td>
    1.54 +<td colspan="1" rowspan="1" width="503px" class="whs17">
    1.55 +<p class=Table>Specifies the WISHBONE data bus width in bits. Supported 
    1.56 + values are 8 and 32. The default is 32.</td></tr>
    1.57  </table>
    1.58  
    1.59  &nbsp; 

     2.1 Binary file document/gpio.pdf has changed

     3.1 --- a/drivers/peripheral.mk	Fri Aug 13 10:41:29 2010 +0100
     3.2 +++ b/drivers/peripheral.mk	Sat Aug 06 01:43:24 2011 +0100
     3.3 @@ -2,9 +2,7 @@
     3.4  # Identify source-paths for this device's driver-sources,
     3.5  # compiled when building the library
     3.6  #---------------------------------------------------------
     3.7 -LIBRARY_C_SRCS	+=			MicoGPIO.c		\
     3.8 -					MicoGPIOService.c	\
     3.9 -					LCD.c
    3.10 +LIBRARY_C_SRCS	+=		MicoGPIOService.c
    3.11  
    3.12  LIBRARY_ASM_SRCS += 
    3.13  

     4.1 --- a/gpio.xml	Fri Aug 13 10:41:29 2010 +0100
     4.2 +++ b/gpio.xml	Sat Aug 06 01:43:24 2011 +0100
     4.3 @@ -1,5 +1,5 @@
     4.4  <?xml version="1.0" encoding="UTF-8"?>
     4.5 -<Component Name="gpio" Text="GPIO" Type="IO" Ver="3.1" Help="gpio\document\gpio.htm">
     4.6 +<Component Name="gpio" Text="GPIO" Type="IO" Ver="3.3" Help="gpio\document\gpio.htm" Processor="LM32,LM8" LatticeFamily="All" Device="All">
     4.7  	<MasterSlavePorts>
     4.8  		<SlavePort Prefix="GPIO" Name="GP I/O Port" Type="DATA,DMAR,DMAW"/>
     4.9  	</MasterSlavePorts>
    4.10 @@ -14,32 +14,48 @@
    4.11  		<ExternalPort Name="PIO_IO" Type="inout" Width="DATA_WIDTH" Condition="TRISTATE_PORTS" />
    4.12  	</ExternalPorts>
    4.13          <DeviceDriver InitRoutine="MicoGPIOInit" StructName="MicoGPIOCtx_t">
    4.14 -                <DDInclude Include = "LookupServices.h"/>
    4.15 -                <DDstruct>			
    4.16 -			<DDSElem MemberName = "name" MemberType = "const char*" Type = "Parm" Value = "InstanceName" Format="string"/>
    4.17 -			<DDSElem MemberName = "base" MemberType = "unsigned int" Type = "Parm" Value = "BASE_ADDRESS" />
    4.18 -                        <DDSElem MemberName = "lookupReg" MemberType = "DeviceReg_t" Type="uninitialized" Value=""/>
    4.19 -                        <DDSElem MemberName = "intrLevel" MemberType = "unsigned int" Type = "Interrupt" Value = "IRQ_LEVEL" />
    4.20 -                        <DDSElem MemberName = "output_only" MemberType = "unsigned int" Type = "Parm" Value = "OUTPUT_PORTS_ONLY" />
    4.21 -                        <DDSElem MemberName = "input_only" MemberType = "unsigned int" Type = "Parm" Value = "INPUT_PORTS_ONLY" />
    4.22 -                        <DDSElem MemberName = "in_and_out" MemberType = "unsigned int" Type = "Parm" Value = "BOTH_INPUT_AND_OUTPUT" />
    4.23 -                        <DDSElem MemberName = "tristate" MemberType = "unsigned int" Type = "Parm" Value = "TRISTATE_PORTS"	/>
    4.24 -                        <DDSElem MemberName = "data_width" MemberType = "unsigned int" Type = "Parm" Value = "DATA_WIDTH" />
    4.25 -                        <DDSElem MemberName = "input_width" MemberType = "unsigned int" Type = "Parm" Value = "INPUT_WIDTH" />
    4.26 -                        <DDSElem MemberName = "output_width" MemberType = "unsigned int" Type = "Parm" Value = "OUTPUT_WIDTH" />
    4.27 -                        <DDSElem MemberName = "intr_enable" MemberType = "unsigned int" Type = "Parm" Value = "IRQ_MODE" />
    4.28 -                        <DDSElem MemberName = "prev" MemberType = "void *" Type = "uninitialized" Value = "" />
    4.29 -                        <DDSElem MemberName = "next" MemberType = "void *" Type = "uninitialized" Value = "" />
    4.30 +                <DDInclude Include = "LookupServices.h" Processor="LM32"/>
    4.31 +                <DDInclude Include = "stddef.h" Processor="LM8"/>
    4.32 +				<DDIRQ IRQAPI="MicoGPIOISR" Parameter="InstanceName" Include="MicoGPIO.h" Processor="LM8"/>
    4.33 +	            <DDPreProcessor Name="__MICOGPIO_USER_IRQ_HANDLER__" Processor="LM8"/>
    4.34 +                <DDstruct>
    4.35 +			<DDSElem MemberName = "name" MemberType = "const char*" Type = "Parm" Value = "InstanceName" Format="string" Processor="LM32,LM8"/>
    4.36 +			<DDSElem MemberName = "base" MemberType = "unsigned int" Type = "Parm" Value = "BASE_ADDRESS" Processor="LM32"/>
    4.37 +			<DDSElem MemberName = "base" MemberType = "size_t" Type = "Parm" Value = "BASE_ADDRESS" Processor="LM8"/>
    4.38 +                        <DDSElem MemberName = "lookupReg" MemberType = "DeviceReg_t" Type="uninitialized" Value="" Processor="LM32"/>
    4.39 +                        <DDSElem MemberName = "intrLevel" MemberType = "unsigned int" Type = "Interrupt" Value = "IRQ_LEVEL" Processor="LM32"/>
    4.40 +                        <DDSElem MemberName = "intrLevel" MemberType = "unsigned char" Type = "Interrupt" Value = "IRQ_LEVEL" Processor="LM8"/>
    4.41 +                        <DDSElem MemberName = "output_only" MemberType = "unsigned int" Type = "Parm" Value = "OUTPUT_PORTS_ONLY" Processor="LM32"/>
    4.42 +                        <DDSElem MemberName = "output_only" MemberType = "unsigned int" Type = "Parm" Value = "OUTPUT_PORTS_ONLY" Processor="LM8"/>
    4.43 +                        <DDSElem MemberName = "input_only" MemberType = "unsigned int" Type = "Parm" Value = "INPUT_PORTS_ONLY" Processor="LM32"/>
    4.44 +                        <DDSElem MemberName = "input_only" MemberType = "unsigned char" Type = "Parm" Value = "INPUT_PORTS_ONLY" Processor="LM8"/>
    4.45 +                        <DDSElem MemberName = "in_and_out" MemberType = "unsigned int" Type = "Parm" Value = "BOTH_INPUT_AND_OUTPUT" Processor="LM32"/>
    4.46 +                        <DDSElem MemberName = "in_and_out" MemberType = "unsigned char" Type = "Parm" Value = "BOTH_INPUT_AND_OUTPUT" Processor="LM8"/>
    4.47 +			<DDSElem MemberName = "tristate" MemberType = "unsigned int" Type = "Parm" Value = "TRISTATE_PORTS" Processor="LM32"/>
    4.48 +			<DDSElem MemberName = "tristate" MemberType = "unsigned char" Type = "Parm" Value = "TRISTATE_PORTS" Processor="LM8"/>
    4.49 +                        <DDSElem MemberName = "data_width" MemberType = "unsigned int" Type = "Parm" Value = "DATA_WIDTH" Processor="LM32"/>
    4.50 +                        <DDSElem MemberName = "data_width" MemberType = "unsigned char" Type = "Parm" Value = "DATA_WIDTH" Processor="LM8"/>
    4.51 +                        <DDSElem MemberName = "input_width" MemberType = "unsigned int" Type = "Parm" Value = "INPUT_WIDTH" Processor="LM32"/>
    4.52 +                        <DDSElem MemberName = "input_width" MemberType = "unsigned char" Type = "Parm" Value = "INPUT_WIDTH" Processor="LM8"/>
    4.53 +                        <DDSElem MemberName = "output_width" MemberType = "unsigned int" Type = "Parm" Value = "OUTPUT_WIDTH" Processor="LM32"/>
    4.54 +                        <DDSElem MemberName = "output_width" MemberType = "unsigned char" Type = "Parm" Value = "OUTPUT_WIDTH" Processor="LM8"/>
    4.55 +                        <DDSElem MemberName = "intr_enable" MemberType = "unsigned int" Type = "Parm" Value = "IRQ_MODE" Processor="LM32"/>
    4.56 +                        <DDSElem MemberName = "intr_enable" MemberType = "unsigned char" Type = "Parm" Value = "IRQ_MODE" Processor="LM8"/>
    4.57 +                        <DDSElem MemberName = "wb_data_size" MemberType = "unsigned int" Type = "Parm" Value = "WB_DAT_WIDTH" Processor="LM32"/>
    4.58 +                        <DDSElem MemberName = "prev" MemberType = "void *" Type = "uninitialized" Value = "" Processor="LM32"/>
    4.59 +                        <DDSElem MemberName = "next" MemberType = "void *" Type = "uninitialized" Value = "" Processor="LM32"/>
    4.60                  </DDstruct>
    4.61          </DeviceDriver>
    4.62        <Files>
    4.63 -	    <File Name="../components/gpio/rtl/verilog/gpio.v" />
    4.64 -	    <File Name="../components/gpio/rtl/verilog/tpio.v" />
    4.65 +	    <File Name="../components/gpio/rtl/verilog/gpio.v"/>
    4.66 +	    <File Name="../components/gpio/rtl/verilog/tpio.v"/>
    4.67        </Files>
    4.68  	<Parms>
    4.69 -		<Parm Name="InstanceName"    Value="gpio"     Type="string" isiname="true" Text="Instance Name"/>
    4.70 -		<Parm Name="BASE_ADDRESS"    Value="0x80000000" Type="Integer" isba="true" Text="Base Address"/>
    4.71 -		<Parm Name="SIZE"            Value="128"    Type="Integer" issize="true" Text="Size" Enable="false"/>
    4.72 +		<Parm Name="InstanceName" Value="gpio" Type="string" isiname="true" Text="Instance Name"/>
    4.73 +		<Parm Name="BASE_ADDRESS" Value="0x80000000" Type="Integer" isba="true" Text="Base Address"/>
    4.74 +		<Parm Name="SIZE" Value="16" Type="Integer" issize="true" Text="Size" Enable="false"/>
    4.75 +		<Parm Name="WB_DAT_WIDTH" Port="GPIO" Type="List" ListValues="8,32" OType="Integer" Value="32" Text="WISHBONE Data Bus Width" isparm="true"/>
    4.76 +		<Parm Name="WB_ADR_WIDTH" Port="GPIO" Type="Integer" OType="Integer" Value="4" Text="WISHBONE Address Bus Width" isparm="true"/>
    4.77                  <Parm Name="ADDRESS_LOCK" Type="Define" Value="undef" Text="Lock Address"/>
    4.78  		<Parm Name="DISABLE" Type="Define" Value="undef" isuse="true" Text="Disable Component"/>
    4.79  		<Parm Name="OUTPUT_PORTS_ONLY" Type="define" Value="def" GROUP="XFER_MODE" Text="Output Ports Only" isparm="true" />
    4.80 @@ -50,8 +66,8 @@
    4.81  		<Parm Name="INPUT_WIDTH" Type="Integer" ValueRange="1-32" Value="1" Condition="BOTH_INPUT_AND_OUTPUT" Text="Input Width" isparm="true"/>
    4.82  		<Parm Name="OUTPUT_WIDTH" Type="Integer" ValueRange="1-32" Value="1" Condition="BOTH_INPUT_AND_OUTPUT" Text="Output Width" isparm="true"/>
    4.83  		<Parm Name="IRQ_MODE" Type="define" Value="undef" Text="IRQ Mode" isparm="true"/>
    4.84 -		<Parm Name="LEVEL" Type="define" Value="undef" GROUP="IMODE" Condition="IRQ_MODE" Text="Level" isparm="true"/>
    4.85 -		<Parm Name="EDGE" Type="define" Value="def" GROUP="IMODE" Condition="IRQ_MODE" Text="Edge" isparm="true"/>
    4.86 +		<Parm Name="LEVEL" Type="define" Value="undef" GROUP="IMODE" Condition="IRQ_MODE" Text="Level Sensitive" isparm="true"/>
    4.87 +		<Parm Name="EDGE" Type="define" Value="def" GROUP="IMODE" Condition="IRQ_MODE" Text="Edge Sensitive" isparm="true"/>
    4.88  		<Parm Name="EITHER_EDGE_IRQ" Type="define" Value="undef" Group="EMODE" Condition="EDGE" Text="Either Edge" isparm="true"/>
    4.89  		<Parm Name="POSE_EDGE_IRQ" Type="define" Value="def" Group="EMODE" Condition="EDGE" Text="Postive Edge" isparm="true"/>
    4.90  		<Parm Name="NEGE_EDGE_IRQ" Type="define" Value="undef" Group="EMODE" Condition="EDGE" Text="Negative Edge" isparm="true"/>
    4.91 @@ -59,25 +75,29 @@
    4.92        <GUIS Columns="2" Help="component_help\lm32.htm" Name="GPIO">
    4.93              <GUI Widget="Text" Span="1" Name="InstanceName" Width="40"/>
    4.94              <GUI Widget="Text" Span="1" Name="BASE_ADDRESS"/>
    4.95 -            <GUI Widget="Group" Span="1" Name="XFER_MODE" Text="Port Types" Columns="1"/>
    4.96 +	    
    4.97 +	    <GUI Widget="Group" Span="1" Name="XFER_MODE" Text="Port Types" Columns="1"/>
    4.98              <GUI Widget="Radio" Span="1" Name="OUTPUT_PORTS_ONLY"/>
    4.99              <GUI Widget="Radio" Span="1" Name="INPUT_PORTS_ONLY"/>
   4.100              <GUI Widget="Radio" Span="1" Name="TRISTATE_PORTS"/>
   4.101              <GUI Widget="Radio" Span="1" Name="BOTH_INPUT_AND_OUTPUT"/>
   4.102 -
   4.103 -            <GUI Widget="Group" Span="1" Text="Port Width" Columns="2"/>
   4.104 +	    
   4.105 +            <GUI Widget="Group" Span="1" Text="Input/Output Port Widths" Columns="2"/>
   4.106              <GUI Widget="Spinner" Span="1" Name="DATA_WIDTH"/>
   4.107              <GUI Widget="Spinner" Span="1" Name="INPUT_WIDTH"/>
   4.108              <GUI Widget="Spinner" Span="1" Name="OUTPUT_WIDTH"/>
   4.109 -
   4.110 -            <GUI Widget="Group" Span="1" Name="IRQ_MODE" Text="IRQ Mode" Columns="1"/>
   4.111 +	    	    	    
   4.112 +            <GUI Widget="Group" Span="2" Name="IRQ_MODE" Text="IRQ Mode" Columns="3"/>
   4.113              <GUI Widget="Check" Span="1" Name="IRQ_MODE"/>
   4.114              <GUI Widget="Radio" Span="1" Name="LEVEL"/>
   4.115              <GUI Widget="Radio" Span="1" Name="EDGE"/>
   4.116 -
   4.117 -            <GUI Widget="Group" Span="1" Text="Edge Response" Columns="1"/>
   4.118 +	    
   4.119 +            <GUI Widget="Group" Span="2" Text="Edge Response" Columns="3"/>
   4.120              <GUI Widget="Radio" Span="1" Name="EITHER_EDGE_IRQ"/>
   4.121              <GUI Widget="Radio" Span="1" Name="POSE_EDGE_IRQ"/>
   4.122              <GUI Widget="Radio" Span="1" Name="NEGE_EDGE_IRQ"/>
   4.123 +	    
   4.124 +	    <GUI Widget="Group" Span="2" Text="WISHBONE Configuration" Columns="2"/>
   4.125 +	    <GUI Widget="Combo" Span="1" Name="WB_DAT_WIDTH" Port="GPIO"/>
   4.126       </GUIS>
   4.127  </Component>

     5.1 --- a/rtl/verilog/gpio.v	Fri Aug 13 10:41:29 2010 +0100
     5.2 +++ b/rtl/verilog/gpio.v	Sat Aug 06 01:43:24 2011 +0100
     5.3 @@ -1,18 +1,39 @@
     5.4 -// =============================================================================
     5.5 -//                           COPYRIGHT NOTICE
     5.6 -// Copyright 2004 (c) Lattice Semiconductor Corporation
     5.7 -// ALL RIGHTS RESERVED
     5.8 -// This confidential and proprietary software may be used only as authorised by
     5.9 -// a licensing agreement from Lattice Semiconductor Corporation.
    5.10 -// The entire notice above must be reproduced on all authorized copies and
    5.11 -// copies may only be made to the extent permitted by a licensing agreement from
    5.12 -// Lattice Semiconductor Corporation.
    5.13 +//   ==================================================================
    5.14 +//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
    5.15 +//   ------------------------------------------------------------------
    5.16 +//   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
    5.17 +//   ALL RIGHTS RESERVED 
    5.18 +//   ------------------------------------------------------------------
    5.19 +//
    5.20 +//   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
    5.21 +//
    5.22 +//   Permission:
    5.23 +//
    5.24 +//      Lattice Semiconductor grants permission to use this code
    5.25 +//      pursuant to the terms of the Lattice Semiconductor Corporation
    5.26 +//      Open Source License Agreement.  
    5.27 +//
    5.28 +//   Disclaimer:
    5.29  //
    5.30 -// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
    5.31 -// 5555 NE Moore Court                            408-826-6000 (other locations)
    5.32 -// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
    5.33 -// U.S.A                                   email: techsupport@latticesemi.com
    5.34 -// =============================================================================/
    5.35 +//      Lattice Semiconductor provides no warranty regarding the use or
    5.36 +//      functionality of this code. It is the user's responsibility to
    5.37 +//      verify the user’s design for consistency and functionality through
    5.38 +//      the use of formal verification methods.
    5.39 +//
    5.40 +//   --------------------------------------------------------------------
    5.41 +//
    5.42 +//                  Lattice Semiconductor Corporation
    5.43 +//                  5555 NE Moore Court
    5.44 +//                  Hillsboro, OR 97214
    5.45 +//                  U.S.A
    5.46 +//
    5.47 +//                  TEL: 1-800-Lattice (USA and Canada)
    5.48 +//                         503-286-8001 (other locations)
    5.49 +//
    5.50 +//                  web: http://www.latticesemi.com/
    5.51 +//                  email: techsupport@latticesemi.com
    5.52 +//
    5.53 +//   --------------------------------------------------------------------
    5.54  //                         FILE DETAILS
    5.55  // Project          : GPIO for LM32
    5.56  // File             : gpio.v
    5.57 @@ -34,346 +55,1782 @@
    5.58  // Mod. Date        : 11 Oct. 2008
    5.59  // Changes Made     : Update the Edge Capture Register clean method
    5.60  //                    Make IRQ Mask register readable
    5.61 +//
    5.62 +// Version          : 3.2
    5.63 +// Mod. Data        : Jun 6, 2010
    5.64 +// Changes Made     : 1. Provide capability to read/write bytes (when GPIO larger
    5.65 +//                       than 8 bits wide)
    5.66 +//                    2. Provide capability to use a 32-bit or 8-bit data bus on
    5.67 +//                       the WISHBONE slave port
    5.68 +//                    3. Perform a big-endian to little-endian conversion in 
    5.69 +//                       hardware
    5.70  // =============================================================================
    5.71  `ifndef GPIO_V
    5.72  `define GPIO_V
    5.73  `timescale 1ns/100 ps
    5.74  `include "system_conf.v"
    5.75 -module gpio #(parameter DATA_WIDTH = 16,
    5.76 -              parameter INPUT_WIDTH = 16,
    5.77 -              parameter OUTPUT_WIDTH = 16,
    5.78 -              parameter IRQ_MODE = 0,
    5.79 -              parameter LEVEL = 0,
    5.80 -              parameter EDGE = 0,
    5.81 -              parameter POSE_EDGE_IRQ = 0,
    5.82 -              parameter NEGE_EDGE_IRQ = 0,
    5.83 -              parameter EITHER_EDGE_IRQ = 0,
    5.84 -              parameter INPUT_PORTS_ONLY = 1,
    5.85 -              parameter OUTPUT_PORTS_ONLY = 0,
    5.86 -              parameter BOTH_INPUT_AND_OUTPUT = 0,
    5.87 -              parameter TRISTATE_PORTS = 0)
    5.88 -     (
    5.89 -     //system clock and reset
    5.90 -     CLK_I,
    5.91 -     RST_I,
    5.92 -     //wishbone interface signals
    5.93 -     GPIO_ADR_I,
    5.94 -     GPIO_CYC_I,
    5.95 -     GPIO_DAT_I,
    5.96 -     GPIO_SEL_I,
    5.97 -     GPIO_STB_I,
    5.98 -     GPIO_WE_I,
    5.99 -     GPIO_LOCK_I,
   5.100 -     GPIO_CTI_I,
   5.101 -     GPIO_BTE_I,
   5.102 -     GPIO_ACK_O,
   5.103 -     GPIO_RTY_O,
   5.104 -     GPIO_DAT_O,
   5.105 -     GPIO_ERR_O,
   5.106 -     IRQ_O, //bit_or of all IRQs
   5.107 -     //PIO side
   5.108 -     PIO_IN,
   5.109 -     PIO_OUT,
   5.110 -     PIO_IO,
   5.111 -     PIO_BOTH_IN,
   5.112 -     PIO_BOTH_OUT
   5.113 -     );
   5.114 -
   5.115 -//---------------------------------------------------------------------
   5.116 -// inputs
   5.117 -   //
   5.118 -   input                   CLK_I;
   5.119 -   input                   RST_I;
   5.120 -   input [31:0]            GPIO_ADR_I;
   5.121 -   input                   GPIO_CYC_I;
   5.122 -   input [31:0]            GPIO_DAT_I;
   5.123 -   input [3:0]             GPIO_SEL_I;
   5.124 -   input                   GPIO_STB_I;
   5.125 -   input                   GPIO_WE_I;
   5.126 -   input                   GPIO_LOCK_I;
   5.127 -   input [2:0]             GPIO_CTI_I;
   5.128 -   input [1:0]             GPIO_BTE_I;   
   5.129 -   input [DATA_WIDTH-1:0]  PIO_IN;
   5.130 -   input [INPUT_WIDTH-1:0] PIO_BOTH_IN;
   5.131 -//---------------------------------------------------------------------
   5.132 -// outputs
   5.133 -//
   5.134 -   output                    GPIO_ACK_O;
   5.135 -   output                    GPIO_RTY_O;
   5.136 -   output [31:0]             GPIO_DAT_O;
   5.137 -   output                    GPIO_ERR_O;
   5.138 -   output                    IRQ_O;
   5.139 -   output [DATA_WIDTH-1:0]   PIO_OUT;
   5.140 -   output [OUTPUT_WIDTH-1:0] PIO_BOTH_OUT;
   5.141 -//----------------
   5.142 -//inout mode
   5.143 -   inout [DATA_WIDTH-1:0]    PIO_IO;
   5.144 -//----------------
   5.145 -//process
   5.146 +module gpio 
   5.147 +  #(
   5.148 +    parameter GPIO_WB_DAT_WIDTH = 32,
   5.149 +    parameter GPIO_WB_ADR_WIDTH = 4,
   5.150 +    parameter DATA_WIDTH = 16,
   5.151 +    parameter INPUT_WIDTH = 16,
   5.152 +    parameter OUTPUT_WIDTH = 16,
   5.153 +    parameter IRQ_MODE = 0,
   5.154 +    parameter LEVEL = 0,
   5.155 +    parameter EDGE = 0,
   5.156 +    parameter POSE_EDGE_IRQ = 0,
   5.157 +    parameter NEGE_EDGE_IRQ = 0,
   5.158 +    parameter EITHER_EDGE_IRQ = 0,
   5.159 +    parameter INPUT_PORTS_ONLY = 1,
   5.160 +    parameter OUTPUT_PORTS_ONLY = 0,
   5.161 +    parameter BOTH_INPUT_AND_OUTPUT = 0,
   5.162 +    parameter TRISTATE_PORTS = 0
   5.163 +    )
   5.164 +   (
   5.165 +    // system clock and reset
   5.166 +    input CLK_I,
   5.167 +    input RST_I,
   5.168 +    
   5.169 +    // wishbone interface signals
   5.170 +    input GPIO_CYC_I,
   5.171 +    input GPIO_STB_I,
   5.172 +    input GPIO_WE_I,
   5.173 +    input GPIO_LOCK_I,
   5.174 +    input [2:0] GPIO_CTI_I,
   5.175 +    input [1:0] GPIO_BTE_I,
   5.176 +    input [GPIO_WB_ADR_WIDTH-1:0] GPIO_ADR_I,
   5.177 +    input [GPIO_WB_DAT_WIDTH-1:0] GPIO_DAT_I,
   5.178 +    input [GPIO_WB_DAT_WIDTH/8-1:0] GPIO_SEL_I,
   5.179 +    output reg GPIO_ACK_O,
   5.180 +    output GPIO_ERR_O,
   5.181 +    output GPIO_RTY_O,
   5.182 +    output [GPIO_WB_DAT_WIDTH-1:0] GPIO_DAT_O,
   5.183 +    
   5.184 +    output IRQ_O,
   5.185 +    
   5.186 +    // PIO side
   5.187 +    input [DATA_WIDTH-1:0] PIO_IN,
   5.188 +    input [INPUT_WIDTH-1:0] PIO_BOTH_IN,
   5.189 +    output [DATA_WIDTH-1:0] PIO_OUT,
   5.190 +    output [OUTPUT_WIDTH-1:0] PIO_BOTH_OUT,
   5.191 +    inout [DATA_WIDTH-1:0] PIO_IO
   5.192 +    );
   5.193     
   5.194 -   parameter    UDLY     = 1;
   5.195 +   // The incoming data bus is big-endian and the internal memory-mapped registers of GPIO
   5.196 +   // component are little-endian. Performing a big-endian to little-endian conversion!
   5.197 +   wire [GPIO_WB_DAT_WIDTH-1:0] GPIO_DAT_I_switch, GPIO_DAT_O_switch;
   5.198 +   wire [GPIO_WB_DAT_WIDTH/8-1:0] GPIO_SEL_I_switch;
   5.199 +   generate
   5.200 +      if (GPIO_WB_DAT_WIDTH == 8) begin
   5.201 +	 assign GPIO_DAT_I_switch = GPIO_DAT_I;
   5.202 +	 assign GPIO_SEL_I_switch = GPIO_SEL_I;
   5.203 +	 assign GPIO_DAT_O = GPIO_DAT_O_switch;
   5.204 +      end
   5.205 +      else begin
   5.206 +	 assign GPIO_DAT_I_switch = {GPIO_DAT_I[7:0], GPIO_DAT_I[15:8], GPIO_DAT_I[23:16], GPIO_DAT_I[31:24]};
   5.207 +	 assign GPIO_SEL_I_switch = {GPIO_SEL_I[0], GPIO_SEL_I[1], GPIO_SEL_I[2], GPIO_SEL_I[3]};
   5.208 +	 assign GPIO_DAT_O = {GPIO_DAT_O_switch[7:0], GPIO_DAT_O_switch[15:8], GPIO_DAT_O_switch[23:16], GPIO_DAT_O_switch[31:24]};
   5.209 +      end
   5.210 +   endgenerate
   5.211 +      
   5.212 +   reg [OUTPUT_WIDTH-1:0] PIO_DATAO; 
   5.213 +   reg [INPUT_WIDTH-1:0]  PIO_DATAI;
   5.214 +   wire 		  ADR_0, ADR_4, ADR_8, ADR_C;
   5.215 +   wire [DATA_WIDTH-1:0]  tpio_out;
   5.216 +   
   5.217 +   wire 		  PIO_DATA_WR_EN;
   5.218 +   wire 		  PIO_DATA_WR_EN_0, PIO_DATA_WR_EN_1, PIO_DATA_WR_EN_2, PIO_DATA_WR_EN_3;
   5.219     
   5.220 -   wire         ADR_0;
   5.221 -   wire         ADR_4;
   5.222 -   wire         ADR_8;
   5.223 -   wire         ADR_C;
   5.224 -   wire         read_addr_0;   
   5.225 -   wire         read_addr_4;   
   5.226 -   wire         read_addr_8;   
   5.227 -   wire         read_addr_C;   
   5.228 -   wire         GPIO_RTY_O;
   5.229 -   wire         GPIO_ERR_O;
   5.230 -   wire [31:0]  GPIO_DAT_O;
   5.231 -   wire         IRQ_O;
   5.232 -   wire [DATA_WIDTH-1:0]   PIO_OUT;
   5.233 -   wire [OUTPUT_WIDTH-1:0] PIO_BOTH_OUT;
   5.234 -   wire [DATA_WIDTH-1:0]   tpio_out;
   5.235 -   wire                    PIO_DATA_WR_EN;
   5.236 -   wire                    PIO_TRI_WR_EN;
   5.237 -   wire                    IRQ_MASK_WR_EN;
   5.238 -   wire                    EDGE_CAP_WR_EN;
   5.239 -   wire                    PIO_DATA_RE_EN;
   5.240 -   wire                    PIO_TRI_RE_EN;
   5.241 -   wire                    IRQ_MASK_RE_EN;
   5.242 -   wire [DATA_WIDTH-1:0]   IRQ_TRI_TEMP;
   5.243 -   reg [DATA_WIDTH-1:0]    PIO_DATA;
   5.244 -   reg [DATA_WIDTH-1:0]    IRQ_MASK;
   5.245 -   reg [INPUT_WIDTH-1:0]   IRQ_MASK_BOTH;
   5.246 -   reg [DATA_WIDTH-1:0]    IRQ_TEMP;
   5.247 -   reg [INPUT_WIDTH-1:0]   IRQ_TEMP_BOTH;
   5.248 -   reg [DATA_WIDTH-1:0]    EDGE_CAPTURE;
   5.249 -   reg [INPUT_WIDTH-1:0]   EDGE_CAPTURE_BOTH;
   5.250 -   reg [DATA_WIDTH-1:0]    PIO_DATA_DLY;
   5.251 -   reg [INPUT_WIDTH-1:0]   PIO_DATA_DLY_BOTH;
   5.252 -   reg [OUTPUT_WIDTH-1:0]  PIO_DATAO; 
   5.253 -   reg [INPUT_WIDTH-1 :0]  PIO_DATAI;
   5.254 -   reg                     GPIO_ACK_O;
   5.255 -
   5.256 +   wire 		  PIO_TRI_WR_EN;
   5.257 +   wire 		  PIO_TRI_WR_EN_0, PIO_TRI_WR_EN_1, PIO_TRI_WR_EN_2, PIO_TRI_WR_EN_3;
   5.258 +   
   5.259 +   wire 		  IRQ_MASK_WR_EN;
   5.260 +   wire 		  IRQ_MASK_WR_EN_0, IRQ_MASK_WR_EN_1, IRQ_MASK_WR_EN_2, IRQ_MASK_WR_EN_3;
   5.261 +   
   5.262 +   wire 		  EDGE_CAP_WR_EN;
   5.263 +   wire 		  EDGE_CAP_WR_EN_0, EDGE_CAP_WR_EN_1, EDGE_CAP_WR_EN_2, EDGE_CAP_WR_EN_3;
   5.264 +   
   5.265 +   wire 		  PIO_DATA_RE_EN;
   5.266 +   wire 		  PIO_TRI_RE_EN;
   5.267 +   wire 		  IRQ_MASK_RE_EN;
   5.268 +   wire [DATA_WIDTH-1:0]  IRQ_TRI_TEMP;
   5.269 +   reg [DATA_WIDTH-1:0]   PIO_DATA;
   5.270 +   reg [DATA_WIDTH-1:0]   IRQ_MASK;
   5.271 +   reg [INPUT_WIDTH-1:0]  IRQ_MASK_BOTH;
   5.272 +   reg [DATA_WIDTH-1:0]   IRQ_TEMP;
   5.273 +   reg [INPUT_WIDTH-1:0]  IRQ_TEMP_BOTH;
   5.274 +   reg [DATA_WIDTH-1:0]   EDGE_CAPTURE;
   5.275 +   reg [INPUT_WIDTH-1:0]  EDGE_CAPTURE_BOTH;
   5.276 +   reg [DATA_WIDTH-1:0]   PIO_DATA_DLY;
   5.277 +   reg [INPUT_WIDTH-1:0]  PIO_DATA_DLY_BOTH;
   5.278 +   
   5.279 +   parameter UDLY = 1;
   5.280 +   
   5.281     assign GPIO_RTY_O = 1'b0;
   5.282     assign GPIO_ERR_O = 1'b0;
   5.283 -   assign ADR_0 = (GPIO_ADR_I[3:0] == 4'b0000 ? 1'b1 : 0); // IO Data           
   5.284 -   assign ADR_4 = (GPIO_ADR_I[3:0] == 4'b0100 ? 1'b1 : 0); // Tri-state Control 
   5.285 -   assign ADR_8 = (GPIO_ADR_I[3:0] == 4'b1000 ? 1'b1 : 0); // IRQ Mask          
   5.286 -   assign ADR_C = (GPIO_ADR_I[3:0] == 4'b1100 ? 1'b1 : 0); // Edge Capture      
   5.287 +   assign ADR_0 = (GPIO_ADR_I[3:2] == 4'b00 ? 1'b1 : 0); // IO Data           
   5.288 +   assign ADR_4 = (GPIO_ADR_I[3:2] == 4'b01 ? 1'b1 : 0); // Tri-state Control 
   5.289 +   assign ADR_8 = (GPIO_ADR_I[3:2] == 4'b10 ? 1'b1 : 0); // IRQ Mask          
   5.290 +   assign ADR_C = (GPIO_ADR_I[3:2] == 4'b11 ? 1'b1 : 0); // Edge Capture      
   5.291 +   
   5.292 +   always @(posedge CLK_I or posedge RST_I)
   5.293 +     if(RST_I)
   5.294 +       GPIO_ACK_O <= #UDLY 1'b0;
   5.295 +     else if(GPIO_STB_I && (GPIO_ACK_O == 1'b0))
   5.296 +       GPIO_ACK_O <= #UDLY 1'b1;
   5.297 +     else
   5.298 +       GPIO_ACK_O <= #UDLY 1'b0;   
   5.299 +   
   5.300 +   
   5.301 +   generate
   5.302 +      if (INPUT_PORTS_ONLY == 1) begin
   5.303 +         always @(posedge CLK_I or posedge RST_I)
   5.304 +           if (RST_I)
   5.305 +             PIO_DATA <= #UDLY 0;
   5.306 +           else if (GPIO_STB_I && !GPIO_ACK_O && !GPIO_WE_I && GPIO_ADR_I[3:2] == 2'b00)
   5.307 +             PIO_DATA <= #UDLY PIO_IN;
   5.308 +      end
   5.309 +   endgenerate
   5.310 +   
   5.311 +   generate
   5.312 +      if (OUTPUT_PORTS_ONLY == 1) begin
   5.313 +	 if (GPIO_WB_DAT_WIDTH == 8) begin
   5.314 +	    genvar ipd_idx;
   5.315 +	    for (ipd_idx = 0; (ipd_idx < DATA_WIDTH) && (ipd_idx < 8); ipd_idx = ipd_idx + 1)
   5.316 +	      begin
   5.317 +		 always @(posedge CLK_I or posedge RST_I)
   5.318 +		   if (RST_I)
   5.319 +		     PIO_DATA[ipd_idx] <= #UDLY 0;
   5.320 +		   else if (GPIO_STB_I && !GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0000)
   5.321 +		     PIO_DATA[ipd_idx] <= #UDLY GPIO_DAT_I_switch[ipd_idx];
   5.322 +	      end
   5.323 +	    if (DATA_WIDTH > 8) begin
   5.324 +	       genvar jpd_idx;
   5.325 +	       for (jpd_idx = 8; (jpd_idx < DATA_WIDTH) && (jpd_idx < 16); jpd_idx = jpd_idx + 1)
   5.326 +		 begin
   5.327 +		    always @(posedge CLK_I or posedge RST_I)
   5.328 +		      if (RST_I)
   5.329 +			PIO_DATA[jpd_idx] <= #UDLY 0;
   5.330 +		      else if (GPIO_STB_I && !GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0001)
   5.331 +			PIO_DATA[jpd_idx] <= #UDLY GPIO_DAT_I_switch[jpd_idx-8];
   5.332 +		 end
   5.333 +	    end
   5.334 +	    if (DATA_WIDTH > 16) begin
   5.335 +	       genvar kpd_idx;
   5.336 +	       for (kpd_idx = 16; (kpd_idx < DATA_WIDTH) && (kpd_idx < 24); kpd_idx = kpd_idx + 1)
   5.337 +		 begin
   5.338 +		    always @(posedge CLK_I or posedge RST_I)
   5.339 +		      if (RST_I)
   5.340 +			PIO_DATA[kpd_idx] <= #UDLY 0;
   5.341 +		      else if (GPIO_STB_I && !GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0010)
   5.342 +			PIO_DATA[kpd_idx] <= #UDLY GPIO_DAT_I_switch[kpd_idx-16];
   5.343 +		 end
   5.344 +	    end
   5.345 +	    if (DATA_WIDTH > 24) begin
   5.346 +	       genvar lpd_idx;
   5.347 +	       for (lpd_idx = 24; (lpd_idx < DATA_WIDTH) && (lpd_idx < 32); lpd_idx = lpd_idx + 1)
   5.348 +		 begin
   5.349 +		    always @(posedge CLK_I or posedge RST_I)
   5.350 +		      if (RST_I)
   5.351 +			PIO_DATA[lpd_idx] <= #UDLY 0;
   5.352 +		      else if (GPIO_STB_I && !GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0011)
   5.353 +			PIO_DATA[lpd_idx] <= #UDLY GPIO_DAT_I_switch[lpd_idx-24];
   5.354 +		 end
   5.355 +	    end
   5.356 +	 end // if (GPIO_WB_DAT_WIDTH == 8)
   5.357 +	 
   5.358 +	 else if (GPIO_WB_DAT_WIDTH == 32) begin
   5.359 +	    genvar ipd_idx;
   5.360 +	    for (ipd_idx = 0; (ipd_idx < DATA_WIDTH) && (ipd_idx < 8); ipd_idx = ipd_idx + 1)
   5.361 +	      begin
   5.362 +		 always @(posedge CLK_I or posedge RST_I)
   5.363 +		   if (RST_I)
   5.364 +		     PIO_DATA[ipd_idx] <= #UDLY 0;
   5.365 +		   else if (GPIO_STB_I && !GPIO_ACK_O && GPIO_WE_I && ADR_0 == 1'b1 && GPIO_SEL_I_switch[0])
   5.366 +		     PIO_DATA[ipd_idx] <= #UDLY GPIO_DAT_I_switch[ipd_idx];
   5.367 +	      end
   5.368 +	    if (DATA_WIDTH > 8) begin
   5.369 +	       genvar jpd_idx;
   5.370 +	       for (jpd_idx = 8; (jpd_idx < DATA_WIDTH) && (jpd_idx < 16); jpd_idx = jpd_idx + 1)
   5.371 +		 begin
   5.372 +		    always @(posedge CLK_I or posedge RST_I)
   5.373 +		      if (RST_I)
   5.374 +			PIO_DATA[jpd_idx] <= #UDLY 0;
   5.375 +		      else if (GPIO_STB_I && !GPIO_ACK_O && GPIO_WE_I && ADR_0 == 1'b1 && GPIO_SEL_I_switch[1])
   5.376 +			PIO_DATA[jpd_idx] <= #UDLY GPIO_DAT_I_switch[jpd_idx];
   5.377 +		 end
   5.378 +	    end
   5.379 +	    if (DATA_WIDTH > 16) begin
   5.380 +	       genvar kpd_idx;
   5.381 +	       for (kpd_idx = 16; (kpd_idx < DATA_WIDTH) && (kpd_idx < 24); kpd_idx = kpd_idx + 1)
   5.382 +		 begin
   5.383 +		    always @(posedge CLK_I or posedge RST_I)
   5.384 +		      if (RST_I)
   5.385 +			PIO_DATA[kpd_idx] <= #UDLY 0;
   5.386 +		      else if (GPIO_STB_I && !GPIO_ACK_O && GPIO_WE_I && ADR_0 == 1'b1 && GPIO_SEL_I_switch[2])
   5.387 +			PIO_DATA[kpd_idx] <= #UDLY GPIO_DAT_I_switch[kpd_idx];
   5.388 +		 end
   5.389 +	    end
   5.390 +	    if (DATA_WIDTH > 24) begin
   5.391 +	       genvar lpd_idx;
   5.392 +	       for (lpd_idx = 24; (lpd_idx < DATA_WIDTH) && (lpd_idx < 32); lpd_idx = lpd_idx + 1)
   5.393 +		 begin
   5.394 +		    always @(posedge CLK_I or posedge RST_I)
   5.395 +		      if (RST_I)
   5.396 +			PIO_DATA[lpd_idx] <= #UDLY 0;
   5.397 +		      else if (GPIO_STB_I && !GPIO_ACK_O && GPIO_WE_I && ADR_0 == 1'b1 && GPIO_SEL_I_switch[3])
   5.398 +			PIO_DATA[lpd_idx] <= #UDLY GPIO_DAT_I_switch[lpd_idx];
   5.399 +		 end
   5.400 +	    end
   5.401 +         end // if (GPIO_WB_DAT_WIDTH == 32)
   5.402 +	 	 
   5.403 +         assign  PIO_OUT = PIO_DATA;
   5.404 +      end
   5.405 +   endgenerate
   5.406 +   
   5.407 +   generate
   5.408 +      if (BOTH_INPUT_AND_OUTPUT == 1) begin
   5.409 +	 if (GPIO_WB_DAT_WIDTH == 8) begin
   5.410 +	    genvar iopd_idx;
   5.411 +	    for (iopd_idx = 0; (iopd_idx < OUTPUT_WIDTH) && (iopd_idx < 8); iopd_idx = iopd_idx + 1)
   5.412 +	      begin
   5.413 +		 always @(posedge CLK_I or posedge RST_I)
   5.414 +		   if (RST_I) 
   5.415 +		     begin
   5.416 +			PIO_DATAI[iopd_idx] <= #UDLY 0;
   5.417 +			PIO_DATAO[iopd_idx] <= #UDLY 0;
   5.418 +		     end 
   5.419 +		   else if (GPIO_STB_I && !GPIO_ACK_O && !GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0000)
   5.420 +		     PIO_DATAI[iopd_idx] <= #UDLY PIO_BOTH_IN[iopd_idx];
   5.421 +		   else if (GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0000)
   5.422 +		     PIO_DATAO[iopd_idx] <= #UDLY GPIO_DAT_I_switch[iopd_idx];
   5.423 +	      end
   5.424 +	    if (OUTPUT_WIDTH > 8) begin
   5.425 +	       genvar jopd_idx;
   5.426 +	       for (jopd_idx = 8; (jopd_idx < OUTPUT_WIDTH) && (jopd_idx < 16); jopd_idx = jopd_idx + 1)
   5.427 +		 begin
   5.428 +		    always @(posedge CLK_I or posedge RST_I)
   5.429 +		      if (RST_I) 
   5.430 +			begin
   5.431 +			   PIO_DATAI[jopd_idx] <= #UDLY 0;
   5.432 +			   PIO_DATAO[jopd_idx] <= #UDLY 0;
   5.433 +			end 
   5.434 +		      else if (GPIO_STB_I && !GPIO_ACK_O && !GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0001)
   5.435 +			PIO_DATAI[jopd_idx] <= #UDLY PIO_BOTH_IN[jopd_idx];
   5.436 +		      else if (GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0001)
   5.437 +			PIO_DATAO[jopd_idx] <= #UDLY GPIO_DAT_I_switch[jopd_idx-8];
   5.438 +		 end
   5.439 +	    end
   5.440 +	    if (OUTPUT_WIDTH > 16) begin
   5.441 +	       genvar kopd_idx;
   5.442 +	       for (kopd_idx = 16; (kopd_idx < OUTPUT_WIDTH) && (kopd_idx < 24); kopd_idx = kopd_idx + 1)
   5.443 +		 begin
   5.444 +		    always @(posedge CLK_I or posedge RST_I)
   5.445 +		      if (RST_I) 
   5.446 +			begin
   5.447 +			   PIO_DATAI[kopd_idx] <= #UDLY 0;
   5.448 +			   PIO_DATAO[kopd_idx] <= #UDLY 0;
   5.449 +			end 
   5.450 +		      else if (GPIO_STB_I && !GPIO_ACK_O && !GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0010)
   5.451 +			PIO_DATAI[kopd_idx] <= #UDLY PIO_BOTH_IN[kopd_idx];
   5.452 +		      else if (GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0010)
   5.453 +			PIO_DATAO[kopd_idx] <= #UDLY GPIO_DAT_I_switch[kopd_idx-16];
   5.454 +		 end
   5.455 +	    end
   5.456 +	    if (OUTPUT_WIDTH > 24) begin
   5.457 +	       genvar lopd_idx;
   5.458 +	       for (lopd_idx = 24; (lopd_idx < OUTPUT_WIDTH) && (lopd_idx < 32); lopd_idx = lopd_idx + 1)
   5.459 +		 begin
   5.460 +		    always @(posedge CLK_I or posedge RST_I)
   5.461 +		      if (RST_I) 
   5.462 +			begin
   5.463 +			   PIO_DATAI[lopd_idx] <= #UDLY 0;
   5.464 +			   PIO_DATAO[lopd_idx] <= #UDLY 0;
   5.465 +			end 
   5.466 +		      else if (GPIO_STB_I && !GPIO_ACK_O && !GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0011)
   5.467 +			PIO_DATAI[lopd_idx] <= #UDLY PIO_BOTH_IN[lopd_idx];
   5.468 +		      else if (GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0011)
   5.469 +			PIO_DATAO[lopd_idx] <= #UDLY GPIO_DAT_I_switch[lopd_idx-24];
   5.470 +		 end
   5.471 +	    end
   5.472 +	 end // if (GPIO_WB_DAT_WIDTH == 8)
   5.473 +	 
   5.474 +	 else if (GPIO_WB_DAT_WIDTH == 32) begin
   5.475 +	    genvar iopd_idx;
   5.476 +	    for (iopd_idx = 0; (iopd_idx < OUTPUT_WIDTH) && (iopd_idx < 8); iopd_idx = iopd_idx + 1)
   5.477 +	      begin
   5.478 +		 always @(posedge CLK_I or posedge RST_I)
   5.479 +		   if (RST_I) 
   5.480 +		     begin
   5.481 +			PIO_DATAI[iopd_idx] <= #UDLY 0;
   5.482 +			PIO_DATAO[iopd_idx] <= #UDLY 0;
   5.483 +		     end 
   5.484 +		   else if (GPIO_STB_I && !GPIO_ACK_O && !GPIO_WE_I && ADR_0 == 1'b1 && GPIO_SEL_I_switch[0])
   5.485 +		     PIO_DATAI[iopd_idx] <= #UDLY PIO_BOTH_IN[iopd_idx];
   5.486 +		   else if (GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && ADR_0 == 1'b1 && GPIO_SEL_I_switch[0])
   5.487 +		     PIO_DATAO[iopd_idx] <= #UDLY GPIO_DAT_I_switch[iopd_idx];
   5.488 +	      end
   5.489 +	    if (OUTPUT_WIDTH > 8) begin
   5.490 +	       genvar jopd_idx;
   5.491 +	       for (jopd_idx = 8; (jopd_idx < OUTPUT_WIDTH) && (jopd_idx < 16); jopd_idx = jopd_idx + 1)
   5.492 +		 begin
   5.493 +		    always @(posedge CLK_I or posedge RST_I)
   5.494 +		      if (RST_I) 
   5.495 +			begin
   5.496 +			   PIO_DATAI[jopd_idx] <= #UDLY 0;
   5.497 +			   PIO_DATAO[jopd_idx] <= #UDLY 0;
   5.498 +			end 
   5.499 +		      else if (GPIO_STB_I && !GPIO_ACK_O && !GPIO_WE_I && ADR_0 == 1'b1 && GPIO_SEL_I_switch[1])
   5.500 +		      	PIO_DATAI[jopd_idx] <= #UDLY PIO_BOTH_IN[jopd_idx];
   5.501 +		      else if (GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && ADR_0 == 1'b1 && GPIO_SEL_I_switch[1])
   5.502 +			PIO_DATAO[jopd_idx] <= #UDLY GPIO_DAT_I_switch[jopd_idx];
   5.503 +		 end
   5.504 +	    end
   5.505 +	    if (OUTPUT_WIDTH > 16) begin
   5.506 +	       genvar kopd_idx;
   5.507 +	       for (kopd_idx = 16; (kopd_idx < OUTPUT_WIDTH) && (kopd_idx < 24); kopd_idx = kopd_idx + 1)
   5.508 +		 begin
   5.509 +		    always @(posedge CLK_I or posedge RST_I)
   5.510 +		      if (RST_I) 
   5.511 +			begin
   5.512 +			   PIO_DATAI[kopd_idx] <= #UDLY 0;
   5.513 +			   PIO_DATAO[kopd_idx] <= #UDLY 0;
   5.514 +			end 
   5.515 +		      else if (GPIO_STB_I && !GPIO_ACK_O && !GPIO_WE_I && ADR_0 == 1'b1 && GPIO_SEL_I_switch[2])
   5.516 +			PIO_DATAI[kopd_idx] <= #UDLY PIO_BOTH_IN[kopd_idx];
   5.517 +		      else if (GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && ADR_0 == 1'b1 && GPIO_SEL_I_switch[2])
   5.518 +			PIO_DATAO[kopd_idx] <= #UDLY GPIO_DAT_I_switch[kopd_idx];
   5.519 +		 end
   5.520 +	    end
   5.521 +	    if (OUTPUT_WIDTH > 24) begin
   5.522 +	       genvar lopd_idx;
   5.523 +	       for (lopd_idx = 24; (lopd_idx < OUTPUT_WIDTH) && (lopd_idx < 32); lopd_idx = lopd_idx + 1)
   5.524 +		 begin
   5.525 +		    always @(posedge CLK_I or posedge RST_I)
   5.526 +		      if (RST_I) 
   5.527 +			begin
   5.528 +			   PIO_DATAI[lopd_idx] <= #UDLY 0;
   5.529 +			   PIO_DATAO[lopd_idx] <= #UDLY 0;
   5.530 +			end 
   5.531 +		      else if (GPIO_STB_I && !GPIO_ACK_O && !GPIO_WE_I && ADR_0 == 1'b1 && GPIO_SEL_I_switch[3])
   5.532 +			PIO_DATAI[lopd_idx] <= #UDLY PIO_BOTH_IN[lopd_idx];
   5.533 +		      else if (GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && ADR_0 == 1'b1 && GPIO_SEL_I_switch[3])
   5.534 +			PIO_DATAO[lopd_idx] <= #UDLY GPIO_DAT_I_switch[lopd_idx];
   5.535 +		 end
   5.536 +	    end
   5.537 +         end // if (GPIO_WB_DAT_WIDTH == 32)
   5.538 +	 
   5.539 +         assign  PIO_BOTH_OUT = PIO_DATAO[OUTPUT_WIDTH-1:0];
   5.540 +      end
   5.541 +   endgenerate
   5.542 +   
   5.543 +   assign  PIO_DATA_RE_EN = GPIO_STB_I && !GPIO_ACK_O && !GPIO_WE_I && (GPIO_ADR_I[3:2] == 2'b00);
   5.544 +   
   5.545 +   assign  PIO_TRI_RE_EN  = GPIO_STB_I &&  GPIO_ACK_O && !GPIO_WE_I && (GPIO_ADR_I[3:2] == 2'b01);
   5.546 +   
   5.547 +   assign  IRQ_MASK_RE_EN = GPIO_STB_I &&  GPIO_ACK_O && !GPIO_WE_I && (GPIO_ADR_I[3:2] == 2'b10);
   5.548 +   
   5.549 +   assign  PIO_DATA_WR_EN = GPIO_STB_I &&  GPIO_ACK_O &&  GPIO_WE_I && (GPIO_ADR_I[3:2] == 2'b00);
   5.550 +   generate
   5.551 +      if (GPIO_WB_DAT_WIDTH == 8) begin
   5.552 +	 assign  PIO_DATA_WR_EN_0 = GPIO_STB_I &&  GPIO_ACK_O &&  GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0000;
   5.553 +	 assign  PIO_DATA_WR_EN_1 = GPIO_STB_I &&  GPIO_ACK_O &&  GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0001;
   5.554 +	 assign  PIO_DATA_WR_EN_2 = GPIO_STB_I &&  GPIO_ACK_O &&  GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0010;
   5.555 +	 assign  PIO_DATA_WR_EN_3 = GPIO_STB_I &&  GPIO_ACK_O &&  GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0011;
   5.556 +      end
   5.557 +   endgenerate
   5.558 +   
   5.559 +   assign  PIO_TRI_WR_EN  = GPIO_STB_I &&  GPIO_ACK_O &&  GPIO_WE_I && (GPIO_ADR_I[3:2] == 4'b01);
   5.560 +   generate
   5.561 +      if (GPIO_WB_DAT_WIDTH == 8) begin
   5.562 +	 assign  PIO_TRI_WR_EN_0  = GPIO_STB_I &&  GPIO_ACK_O &&  GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0100;
   5.563 +	 assign  PIO_TRI_WR_EN_1  = GPIO_STB_I &&  GPIO_ACK_O &&  GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0101;
   5.564 +	 assign  PIO_TRI_WR_EN_2  = GPIO_STB_I &&  GPIO_ACK_O &&  GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0110;
   5.565 +	 assign  PIO_TRI_WR_EN_3  = GPIO_STB_I &&  GPIO_ACK_O &&  GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b0111;
   5.566 +      end
   5.567 +   endgenerate
   5.568 +   
   5.569 +   assign  IRQ_MASK_WR_EN   = GPIO_STB_I &&  GPIO_ACK_O &&  GPIO_WE_I && (GPIO_ADR_I[3:2] == 2'b10);
   5.570 +   generate
   5.571 +      if (GPIO_WB_DAT_WIDTH == 8) begin
   5.572 +	 assign  IRQ_MASK_WR_EN_0 = GPIO_STB_I &&  GPIO_ACK_O &&  GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b1000;
   5.573 +	 assign  IRQ_MASK_WR_EN_1 = GPIO_STB_I &&  GPIO_ACK_O &&  GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b1001;
   5.574 +	 assign  IRQ_MASK_WR_EN_2 = GPIO_STB_I &&  GPIO_ACK_O &&  GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b1010;
   5.575 +	 assign  IRQ_MASK_WR_EN_3 = GPIO_STB_I &&  GPIO_ACK_O &&  GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b1011;
   5.576 +      end
   5.577 +   endgenerate
   5.578 +   
   5.579 +   assign  EDGE_CAP_WR_EN   = GPIO_STB_I &&  GPIO_ACK_O &&  GPIO_WE_I && (GPIO_ADR_I[3:2] == 2'b11);
   5.580 +   generate
   5.581 +      if (GPIO_WB_DAT_WIDTH == 8) begin
   5.582 +	 assign  EDGE_CAP_WR_EN_0 = GPIO_STB_I &&  GPIO_ACK_O &&  GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b1100;
   5.583 +	 assign  EDGE_CAP_WR_EN_1 = GPIO_STB_I &&  GPIO_ACK_O &&  GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b1101;
   5.584 +	 assign  EDGE_CAP_WR_EN_2 = GPIO_STB_I &&  GPIO_ACK_O &&  GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b1110;
   5.585 +	 assign  EDGE_CAP_WR_EN_3 = GPIO_STB_I &&  GPIO_ACK_O &&  GPIO_WE_I && GPIO_ADR_I[3:0] == 4'b1111;
   5.586 +      end
   5.587 +   endgenerate
   5.588 +   
   5.589 +   generate
   5.590 +      
   5.591 +      if (GPIO_WB_DAT_WIDTH == 8) begin
   5.592 +	 
   5.593 +	 genvar iti;
   5.594 +	 for (iti = 0; (iti < DATA_WIDTH) && (iti < 8); iti = iti + 1)
   5.595 +           begin : itio_inst
   5.596 +              TRI_PIO 
   5.597 +		#(.DATA_WIDTH(1),
   5.598 +		  .IRQ_MODE(IRQ_MODE),
   5.599 +		  .LEVEL(LEVEL),
   5.600 +		  .EDGE(EDGE),
   5.601 +		  .POSE_EDGE_IRQ(POSE_EDGE_IRQ),
   5.602 +		  .NEGE_EDGE_IRQ(NEGE_EDGE_IRQ),
   5.603 +		  .EITHER_EDGE_IRQ(EITHER_EDGE_IRQ))
   5.604 +              TP 
   5.605 +		(.CLK_I(CLK_I),
   5.606 +		 .RST_I(RST_I),
   5.607 +		 .DAT_I(GPIO_DAT_I_switch[iti]),
   5.608 +		 .DAT_O(tpio_out[iti]),
   5.609 +		 .PIO_IO(PIO_IO[iti]),
   5.610 +		 .IRQ_O(IRQ_TRI_TEMP[iti]),
   5.611 +		 .PIO_TRI_WR_EN(PIO_TRI_WR_EN_0),
   5.612 +		 .PIO_TRI_RE_EN(PIO_TRI_RE_EN),
   5.613 +		 .PIO_DATA_WR_EN(PIO_DATA_WR_EN_0),
   5.614 +		 .PIO_DATA_RE_EN(PIO_DATA_RE_EN),
   5.615 +		 .IRQ_MASK_WR_EN(IRQ_MASK_WR_EN_0),
   5.616 +		 .IRQ_MASK_RE_EN(IRQ_MASK_RE_EN),
   5.617 +		 .EDGE_CAP_WR_EN(EDGE_CAP_WR_EN_0));
   5.618 +           end
   5.619 +	 if (DATA_WIDTH > 8) begin
   5.620 +	    genvar jti;
   5.621 +	    for (jti = 8; (jti < DATA_WIDTH) && (jti < 16); jti = jti + 1)
   5.622 +              begin : jtio_inst
   5.623 +		 TRI_PIO 
   5.624 +		   #(.DATA_WIDTH(1),
   5.625 +		     .IRQ_MODE(IRQ_MODE),
   5.626 +		     .LEVEL(LEVEL),
   5.627 +		     .EDGE(EDGE),
   5.628 +		     .POSE_EDGE_IRQ(POSE_EDGE_IRQ),
   5.629 +		     .NEGE_EDGE_IRQ(NEGE_EDGE_IRQ),
   5.630 +		     .EITHER_EDGE_IRQ(EITHER_EDGE_IRQ))
   5.631 +		 TP 
   5.632 +		   (.CLK_I(CLK_I),
   5.633 +		    .RST_I(RST_I),
   5.634 +		    .DAT_I(GPIO_DAT_I_switch[jti-8]),
   5.635 +		    .DAT_O(tpio_out[jti]),
   5.636 +		    .PIO_IO(PIO_IO[jti]),
   5.637 +		    .IRQ_O(IRQ_TRI_TEMP[jti]),
   5.638 +		    .PIO_TRI_WR_EN(PIO_TRI_WR_EN_1),
   5.639 +		    .PIO_TRI_RE_EN(PIO_TRI_RE_EN),
   5.640 +		    .PIO_DATA_WR_EN(PIO_DATA_WR_EN_1),
   5.641 +		    .PIO_DATA_RE_EN(PIO_DATA_RE_EN),
   5.642 +		    .IRQ_MASK_WR_EN(IRQ_MASK_WR_EN_1),
   5.643 +		    .IRQ_MASK_RE_EN(IRQ_MASK_RE_EN),
   5.644 +		    .EDGE_CAP_WR_EN(EDGE_CAP_WR_EN_1));
   5.645 +              end
   5.646 +	 end
   5.647 +	 if (DATA_WIDTH > 16) begin
   5.648 +	    genvar kti;
   5.649 +	    for (kti = 16; (kti < DATA_WIDTH) && (kti < 24); kti = kti + 1)
   5.650 +              begin : ktio_inst
   5.651 +		 TRI_PIO 
   5.652 +		   #(.DATA_WIDTH(1),
   5.653 +		     .IRQ_MODE(IRQ_MODE),
   5.654 +		     .LEVEL(LEVEL),
   5.655 +		     .EDGE(EDGE),
   5.656 +		     .POSE_EDGE_IRQ(POSE_EDGE_IRQ),
   5.657 +		     .NEGE_EDGE_IRQ(NEGE_EDGE_IRQ),
   5.658 +		     .EITHER_EDGE_IRQ(EITHER_EDGE_IRQ))
   5.659 +		 TP 
   5.660 +		   (.CLK_I(CLK_I),
   5.661 +		    .RST_I(RST_I),
   5.662 +		    .DAT_I(GPIO_DAT_I_switch[kti-16]),
   5.663 +		    .DAT_O(tpio_out[kti]),
   5.664 +		    .PIO_IO(PIO_IO[kti]),
   5.665 +		    .IRQ_O(IRQ_TRI_TEMP[kti]),
   5.666 +		    .PIO_TRI_WR_EN(PIO_TRI_WR_EN_2),
   5.667 +		    .PIO_TRI_RE_EN(PIO_TRI_RE_EN),
   5.668 +		    .PIO_DATA_WR_EN(PIO_DATA_WR_EN_2),
   5.669 +		    .PIO_DATA_RE_EN(PIO_DATA_RE_EN),
   5.670 +		    .IRQ_MASK_WR_EN(IRQ_MASK_WR_EN_2),
   5.671 +		    .IRQ_MASK_RE_EN(IRQ_MASK_RE_EN),
   5.672 +		    .EDGE_CAP_WR_EN(EDGE_CAP_WR_EN_2));
   5.673 +              end
   5.674 +	 end
   5.675 +	 if (DATA_WIDTH > 24) begin
   5.676 +	    genvar lti;
   5.677 +	    for (lti = 24; (lti < DATA_WIDTH) && (lti < 32); lti = lti + 1)
   5.678 +              begin : ltio_inst
   5.679 +		 TRI_PIO 
   5.680 +		   #(.DATA_WIDTH(1),
   5.681 +		     .IRQ_MODE(IRQ_MODE),
   5.682 +		     .LEVEL(LEVEL),
   5.683 +		     .EDGE(EDGE),
   5.684 +		     .POSE_EDGE_IRQ(POSE_EDGE_IRQ),
   5.685 +		     .NEGE_EDGE_IRQ(NEGE_EDGE_IRQ),
   5.686 +		     .EITHER_EDGE_IRQ(EITHER_EDGE_IRQ))
   5.687 +		 TP 
   5.688 +		   (.CLK_I(CLK_I),
   5.689 +		    .RST_I(RST_I),
   5.690 +		    .DAT_I(GPIO_DAT_I_switch[lti-24]),
   5.691 +		    .DAT_O(tpio_out[lti]),
   5.692 +		    .PIO_IO(PIO_IO[lti]),
   5.693 +		    .IRQ_O(IRQ_TRI_TEMP[lti]),
   5.694 +		    .PIO_TRI_WR_EN(PIO_TRI_WR_EN_3),
   5.695 +		    .PIO_TRI_RE_EN(PIO_TRI_RE_EN),
   5.696 +		    .PIO_DATA_WR_EN(PIO_DATA_WR_EN_3),
   5.697 +		    .PIO_DATA_RE_EN(PIO_DATA_RE_EN),
   5.698 +		    .IRQ_MASK_WR_EN(IRQ_MASK_WR_EN_3),
   5.699 +		    .IRQ_MASK_RE_EN(IRQ_MASK_RE_EN),
   5.700 +		    .EDGE_CAP_WR_EN(EDGE_CAP_WR_EN_3));
   5.701 +              end
   5.702 +	 end
   5.703 +	 
   5.704 +      end // if (GPIO_WB_DAT_WIDTH == 8)
   5.705 +      
   5.706 +      else if (GPIO_WB_DAT_WIDTH == 32) begin
   5.707 +	 
   5.708 +	 genvar iti;
   5.709 +	 for (iti = 0; (iti < DATA_WIDTH) && (iti < 8); iti = iti + 1)
   5.710 +           begin : itio_inst
   5.711 +              TRI_PIO 
   5.712 +		#(.DATA_WIDTH(1),
   5.713 +		  .IRQ_MODE(IRQ_MODE),
   5.714 +		  .LEVEL(LEVEL),
   5.715 +		  .EDGE(EDGE),
   5.716 +		  .POSE_EDGE_IRQ(POSE_EDGE_IRQ),
   5.717 +		  .NEGE_EDGE_IRQ(NEGE_EDGE_IRQ),
   5.718 +		  .EITHER_EDGE_IRQ(EITHER_EDGE_IRQ))
   5.719 +              TP 
   5.720 +		(.CLK_I(CLK_I),
   5.721 +		 .RST_I(RST_I),
   5.722 +		 .DAT_I(GPIO_DAT_I_switch[iti]),
   5.723 +		 .DAT_O(tpio_out[iti]),
   5.724 +		 .PIO_IO(PIO_IO[iti]),
   5.725 +		 .IRQ_O(IRQ_TRI_TEMP[iti]),
   5.726 +		 .PIO_TRI_WR_EN(PIO_TRI_WR_EN & GPIO_SEL_I_switch[0]),
   5.727 +		 .PIO_TRI_RE_EN(PIO_TRI_RE_EN),
   5.728 +		 .PIO_DATA_WR_EN(PIO_DATA_WR_EN & GPIO_SEL_I_switch[0]),
   5.729 +		 .PIO_DATA_RE_EN(PIO_DATA_RE_EN),
   5.730 +		 .IRQ_MASK_WR_EN(IRQ_MASK_WR_EN & GPIO_SEL_I_switch[0]),
   5.731 +		 .IRQ_MASK_RE_EN(IRQ_MASK_RE_EN),
   5.732 +		 .EDGE_CAP_WR_EN(EDGE_CAP_WR_EN & GPIO_SEL_I_switch[0]));
   5.733 +           end
   5.734 +	 if (DATA_WIDTH > 8) begin
   5.735 +	    genvar jti;
   5.736 +	    for (jti = 8; (jti < DATA_WIDTH) && (jti < 16); jti = jti + 1)
   5.737 +              begin : jtio_inst
   5.738 +		 TRI_PIO 
   5.739 +		   #(.DATA_WIDTH(1),
   5.740 +		     .IRQ_MODE(IRQ_MODE),
   5.741 +		     .LEVEL(LEVEL),
   5.742 +		     .EDGE(EDGE),
   5.743 +		     .POSE_EDGE_IRQ(POSE_EDGE_IRQ),
   5.744 +		     .NEGE_EDGE_IRQ(NEGE_EDGE_IRQ),
   5.745 +		     .EITHER_EDGE_IRQ(EITHER_EDGE_IRQ))
   5.746 +		 TP 
   5.747 +		   (.CLK_I(CLK_I),
   5.748 +		    .RST_I(RST_I),
   5.749 +		    .DAT_I(GPIO_DAT_I_switch[jti]),
   5.750 +		    .DAT_O(tpio_out[jti]),
   5.751 +		    .PIO_IO(PIO_IO[jti]),
   5.752 +		    .IRQ_O(IRQ_TRI_TEMP[jti]),
   5.753 +		    .PIO_TRI_WR_EN(PIO_TRI_WR_EN & GPIO_SEL_I_switch[1]),
   5.754 +		    .PIO_TRI_RE_EN(PIO_TRI_RE_EN),
   5.755 +		    .PIO_DATA_WR_EN(PIO_DATA_WR_EN & GPIO_SEL_I_switch[1]),
   5.756 +		    .PIO_DATA_RE_EN(PIO_DATA_RE_EN),
   5.757 +		    .IRQ_MASK_WR_EN(IRQ_MASK_WR_EN & GPIO_SEL_I_switch[1]),
   5.758 +		    .IRQ_MASK_RE_EN(IRQ_MASK_RE_EN),
   5.759 +		    .EDGE_CAP_WR_EN(EDGE_CAP_WR_EN & GPIO_SEL_I_switch[1]));
   5.760 +              end
   5.761 +	 end
   5.762 +	 if (DATA_WIDTH > 16) begin
   5.763 +	    genvar kti;
   5.764 +	    for (kti = 16; (kti < DATA_WIDTH) && (kti < 24); kti = kti + 1)
   5.765 +              begin : ktio_inst
   5.766 +		 TRI_PIO 
   5.767 +		   #(.DATA_WIDTH(1),
   5.768 +		     .IRQ_MODE(IRQ_MODE),
   5.769 +		     .LEVEL(LEVEL),
   5.770 +		     .EDGE(EDGE),
   5.771 +		     .POSE_EDGE_IRQ(POSE_EDGE_IRQ),
   5.772 +		     .NEGE_EDGE_IRQ(NEGE_EDGE_IRQ),
   5.773 +		     .EITHER_EDGE_IRQ(EITHER_EDGE_IRQ))
   5.774 +		 TP 
   5.775 +		   (.CLK_I(CLK_I),
   5.776 +		    .RST_I(RST_I),
   5.777 +		    .DAT_I(GPIO_DAT_I_switch[kti]),
   5.778 +		    .DAT_O(tpio_out[kti]),
   5.779 +		    .PIO_IO(PIO_IO[kti]),
   5.780 +		    .IRQ_O(IRQ_TRI_TEMP[kti]),
   5.781 +		    .PIO_TRI_WR_EN(PIO_TRI_WR_EN & GPIO_SEL_I_switch[2]),
   5.782 +		    .PIO_TRI_RE_EN(PIO_TRI_RE_EN),
   5.783 +		    .PIO_DATA_WR_EN(PIO_DATA_WR_EN & GPIO_SEL_I_switch[2]),
   5.784 +		    .PIO_DATA_RE_EN(PIO_DATA_RE_EN),
   5.785 +		    .IRQ_MASK_WR_EN(IRQ_MASK_WR_EN & GPIO_SEL_I_switch[2]),
   5.786 +		    .IRQ_MASK_RE_EN(IRQ_MASK_RE_EN),
   5.787 +		    .EDGE_CAP_WR_EN(EDGE_CAP_WR_EN & GPIO_SEL_I_switch[2]));
   5.788 +              end
   5.789 +	 end
   5.790 +	 if (DATA_WIDTH > 24) begin
   5.791 +	    genvar lti;
   5.792 +	    for (lti = 24; (lti < DATA_WIDTH) && (lti < 32); lti = lti + 1)
   5.793 +              begin : ltio_inst
   5.794 +		 TRI_PIO 
   5.795 +		   #(.DATA_WIDTH(1),
   5.796 +		     .IRQ_MODE(IRQ_MODE),
   5.797 +		     .LEVEL(LEVEL),
   5.798 +		     .EDGE(EDGE),
   5.799 +		     .POSE_EDGE_IRQ(POSE_EDGE_IRQ),
   5.800 +		     .NEGE_EDGE_IRQ(NEGE_EDGE_IRQ),
   5.801 +		     .EITHER_EDGE_IRQ(EITHER_EDGE_IRQ))
   5.802 +		 TP 
   5.803 +		   (.CLK_I(CLK_I),
   5.804 +		    .RST_I(RST_I),
   5.805 +		    .DAT_I(GPIO_DAT_I_switch[lti]),
   5.806 +		    .DAT_O(tpio_out[lti]),
   5.807 +		    .PIO_IO(PIO_IO[lti]),
   5.808 +		    .IRQ_O(IRQ_TRI_TEMP[lti]),
   5.809 +		    .PIO_TRI_WR_EN(PIO_TRI_WR_EN & GPIO_SEL_I_switch[3]),
   5.810 +		    .PIO_TRI_RE_EN(PIO_TRI_RE_EN),
   5.811 +		    .PIO_DATA_WR_EN(PIO_DATA_WR_EN & GPIO_SEL_I_switch[3]),
   5.812 +		    .PIO_DATA_RE_EN(PIO_DATA_RE_EN),
   5.813 +		    .IRQ_MASK_WR_EN(IRQ_MASK_WR_EN & GPIO_SEL_I_switch[3]),
   5.814 +		    .IRQ_MASK_RE_EN(IRQ_MASK_RE_EN),
   5.815 +		    .EDGE_CAP_WR_EN(EDGE_CAP_WR_EN & GPIO_SEL_I_switch[3]));
   5.816 +              end
   5.817 +	 end
   5.818 +	 
   5.819 +      end // if (GPIO_WB_DAT_WIDTH == 32)
   5.820 +            
   5.821 +   endgenerate
   5.822 +   
   5.823 +   
   5.824 +   wire read_addr_0, read_addr_4, read_addr_8, read_addr_C;
   5.825     assign read_addr_0 =                   (ADR_0 & GPIO_STB_I & ~GPIO_WE_I) ;   
   5.826     assign read_addr_4 =                   (ADR_4 & GPIO_STB_I & ~GPIO_WE_I) ;   
   5.827     assign read_addr_8 = (IRQ_MODE == 1 && (ADR_8 & GPIO_STB_I & ~GPIO_WE_I));   
   5.828 -   assign read_addr_C = (IRQ_MODE == 1 && (ADR_C & GPIO_STB_I & ~GPIO_WE_I));   
   5.829 -
   5.830 -   always @(posedge CLK_I or posedge RST_I)
   5.831 -     if(RST_I)
   5.832 -       GPIO_ACK_O       <= #UDLY 1'b0;
   5.833 -     else if( GPIO_STB_I && !GPIO_ACK_O)
   5.834 -       GPIO_ACK_O       <= #UDLY 1'b1;
   5.835 -     else
   5.836 -       GPIO_ACK_O       <= #UDLY 1'b0;   
   5.837 -
   5.838 -   generate
   5.839 -      if (INPUT_PORTS_ONLY == 1) begin   
   5.840 -         always @(posedge CLK_I or posedge RST_I)
   5.841 -           if (RST_I)
   5.842 -             PIO_DATA <= #UDLY 0;
   5.843 -           else if (GPIO_STB_I && !GPIO_ACK_O && !GPIO_WE_I && ADR_0 == 1'b1 && GPIO_SEL_I == 4'b1111)       
   5.844 -             PIO_DATA <= #UDLY PIO_IN;
   5.845 -         end
   5.846 -   endgenerate
   5.847 - 
   5.848 -   generate   
   5.849 -      if (OUTPUT_PORTS_ONLY == 1) begin
   5.850 -        always @(posedge CLK_I or posedge RST_I)
   5.851 -          if (RST_I)
   5.852 -            PIO_DATA <= #UDLY 0;
   5.853 -          else if (GPIO_STB_I && !GPIO_ACK_O && GPIO_WE_I && ADR_0 == 1'b1 && GPIO_SEL_I == 4'b1111)
   5.854 -            PIO_DATA <= #UDLY GPIO_DAT_I[DATA_WIDTH-1:0];   
   5.855 -            
   5.856 -        assign  PIO_OUT = PIO_DATA;
   5.857 -        end
   5.858 -   endgenerate
   5.859 +   assign read_addr_C = (IRQ_MODE == 1 && (ADR_C & GPIO_STB_I & ~GPIO_WE_I));
   5.860     
   5.861 -   generate
   5.862 -      if (BOTH_INPUT_AND_OUTPUT == 1) begin   
   5.863 -        always @(posedge CLK_I or posedge RST_I)
   5.864 -          if (RST_I) begin
   5.865 -            PIO_DATAI <= #UDLY 0;
   5.866 -            PIO_DATAO <= #UDLY 0;
   5.867 -          end else if (GPIO_STB_I && !GPIO_ACK_O && !GPIO_WE_I && (ADR_0 == 1'b1) && GPIO_SEL_I == 4'b1111)
   5.868 -            PIO_DATAI <= #UDLY PIO_BOTH_IN;
   5.869 -          else if (GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && (ADR_0 == 1'b1) && GPIO_SEL_I == 4'b1111)
   5.870 -            PIO_DATAO <= #UDLY GPIO_DAT_I[OUTPUT_WIDTH-1:0];
   5.871 -               
   5.872 -        assign  PIO_BOTH_OUT = PIO_DATAO[OUTPUT_WIDTH-1:0];
   5.873 -        end
   5.874 -   endgenerate
   5.875 -   
   5.876 -   assign  PIO_DATA_RE_EN = GPIO_STB_I && !GPIO_ACK_O && !GPIO_WE_I && (ADR_0 == 1'b1) && GPIO_SEL_I == 4'b1111;
   5.877 -   assign  PIO_TRI_RE_EN  = GPIO_STB_I &&  GPIO_ACK_O && !GPIO_WE_I && (ADR_4 == 1'b1) && GPIO_SEL_I == 4'b1111;
   5.878 -   assign  IRQ_MASK_RE_EN = GPIO_STB_I &&  GPIO_ACK_O && !GPIO_WE_I && (ADR_8 == 1'b1) && GPIO_SEL_I == 4'b1111;
   5.879 -   assign  PIO_DATA_WR_EN = GPIO_STB_I &&  GPIO_ACK_O &&  GPIO_WE_I && (ADR_0 == 1'b1) && GPIO_SEL_I == 4'b1111;
   5.880 -   assign  PIO_TRI_WR_EN  = GPIO_STB_I &&  GPIO_ACK_O &&  GPIO_WE_I && (ADR_4 == 1'b1) && GPIO_SEL_I == 4'b1111;
   5.881 -   assign  IRQ_MASK_WR_EN = GPIO_STB_I &&  GPIO_ACK_O &&  GPIO_WE_I && (ADR_8 == 1'b1) && GPIO_SEL_I == 4'b1111;
   5.882 -   assign  EDGE_CAP_WR_EN = GPIO_STB_I &&  GPIO_ACK_O &&  GPIO_WE_I && (ADR_C == 1'b1) && GPIO_SEL_I == 4'b1111;
   5.883 +   wire read_byte_0, read_byte_1, read_byte_2, read_byte_3;
   5.884 +   wire read_byte_4, read_byte_5, read_byte_6, read_byte_7;
   5.885 +   wire read_byte_8, read_byte_9, read_byte_A, read_byte_B;
   5.886 +   wire read_byte_C, read_byte_D, read_byte_E, read_byte_F;
   5.887 +   assign read_byte_0 =                   ((GPIO_ADR_I[3:0] == 4'b0000) & GPIO_STB_I & ~GPIO_WE_I) ;   
   5.888 +   assign read_byte_1 =                   ((GPIO_ADR_I[3:0] == 4'b0001) & GPIO_STB_I & ~GPIO_WE_I) ;   
   5.889 +   assign read_byte_2 =                   ((GPIO_ADR_I[3:0] == 4'b0010) & GPIO_STB_I & ~GPIO_WE_I) ;   
   5.890 +   assign read_byte_3 =                   ((GPIO_ADR_I[3:0] == 4'b0011) & GPIO_STB_I & ~GPIO_WE_I) ;   
   5.891 +   assign read_byte_4 =                   ((GPIO_ADR_I[3:0] == 4'b0100) & GPIO_STB_I & ~GPIO_WE_I) ;   
   5.892 +   assign read_byte_5 =                   ((GPIO_ADR_I[3:0] == 4'b0101) & GPIO_STB_I & ~GPIO_WE_I) ;   
   5.893 +   assign read_byte_6 =                   ((GPIO_ADR_I[3:0] == 4'b0110) & GPIO_STB_I & ~GPIO_WE_I) ;   
   5.894 +   assign read_byte_7 =                   ((GPIO_ADR_I[3:0] == 4'b0111) & GPIO_STB_I & ~GPIO_WE_I) ;   
   5.895 +   assign read_byte_8 = (IRQ_MODE == 1 && ((GPIO_ADR_I[3:0] == 4'b1000) & GPIO_STB_I & ~GPIO_WE_I));   
   5.896 +   assign read_byte_9 = (IRQ_MODE == 1 && ((GPIO_ADR_I[3:0] == 4'b1001) & GPIO_STB_I & ~GPIO_WE_I));   
   5.897 +   assign read_byte_A = (IRQ_MODE == 1 && ((GPIO_ADR_I[3:0] == 4'b1010) & GPIO_STB_I & ~GPIO_WE_I));   
   5.898 +   assign read_byte_B = (IRQ_MODE == 1 && ((GPIO_ADR_I[3:0] == 4'b1011) & GPIO_STB_I & ~GPIO_WE_I));   
   5.899 +   assign read_byte_C = (IRQ_MODE == 1 && ((GPIO_ADR_I[3:0] == 4'b1100) & GPIO_STB_I & ~GPIO_WE_I));   
   5.900 +   assign read_byte_D = (IRQ_MODE == 1 && ((GPIO_ADR_I[3:0] == 4'b1101) & GPIO_STB_I & ~GPIO_WE_I));   
   5.901 +   assign read_byte_E = (IRQ_MODE == 1 && ((GPIO_ADR_I[3:0] == 4'b1110) & GPIO_STB_I & ~GPIO_WE_I));   
   5.902 +   assign read_byte_F = (IRQ_MODE == 1 && ((GPIO_ADR_I[3:0] == 4'b1111) & GPIO_STB_I & ~GPIO_WE_I));   
   5.903     
   5.904     generate
   5.905 -      genvar     ti;
   5.906 -      for (ti = 0 ; ti < DATA_WIDTH; ti = ti + 1)
   5.907 -         begin : tio_inst
   5.908 -            TRI_PIO #(.DATA_WIDTH(DATA_WIDTH),
   5.909 -               .IRQ_MODE(IRQ_MODE),
   5.910 -               .LEVEL(LEVEL),
   5.911 -               .EDGE(EDGE),
   5.912 -               .POSE_EDGE_IRQ(POSE_EDGE_IRQ),
   5.913 -               .NEGE_EDGE_IRQ(NEGE_EDGE_IRQ),
   5.914 -               .EITHER_EDGE_IRQ(EITHER_EDGE_IRQ))
   5.915 -            TP (.CLK_I(CLK_I),
   5.916 -           .RST_I(RST_I),
   5.917 -           .DAT_I(GPIO_DAT_I[ti]),
   5.918 -           .DAT_O(tpio_out[ti]),
   5.919 -           .PIO_IO(PIO_IO[ti]),
   5.920 -           .IRQ_O(IRQ_TRI_TEMP[ti]),
   5.921 -           .PIO_TRI_WR_EN(PIO_TRI_WR_EN),
   5.922 -           .PIO_TRI_RE_EN(PIO_TRI_RE_EN),
   5.923 -           .PIO_DATA_WR_EN(PIO_DATA_WR_EN),
   5.924 -           .PIO_DATA_RE_EN(PIO_DATA_RE_EN),
   5.925 -           .IRQ_MASK_WR_EN(IRQ_MASK_WR_EN),
   5.926 -           .IRQ_MASK_RE_EN(IRQ_MASK_RE_EN),
   5.927 -           .EDGE_CAP_WR_EN(EDGE_CAP_WR_EN));
   5.928 -         end
   5.929 -   endgenerate
   5.930  
   5.931 -   generate      
   5.932 -     if (INPUT_PORTS_ONLY == 1)
   5.933 -       assign GPIO_DAT_O = read_addr_0 ? PIO_DATA : 
   5.934 -                           read_addr_8 ? IRQ_MASK :
   5.935 -                           read_addr_C ? EDGE_CAPTURE :
   5.936 -                           0;
   5.937 -     else if (BOTH_INPUT_AND_OUTPUT == 1)
   5.938 -       assign GPIO_DAT_O = read_addr_0 ? PIO_DATAI : 
   5.939 -                           read_addr_8 ? IRQ_MASK_BOTH :
   5.940 -                           read_addr_C ? EDGE_CAPTURE_BOTH :
   5.941 -                           0;
   5.942 -     else if (TRISTATE_PORTS == 1)
   5.943 -       assign GPIO_DAT_O = read_addr_0 ? tpio_out : 
   5.944 -                           read_addr_4 ? tpio_out : 
   5.945 -                           read_addr_8 ? tpio_out :
   5.946 -                           read_addr_C ? IRQ_TRI_TEMP :
   5.947 -                           0;
   5.948 -     else
   5.949 -       assign GPIO_DAT_O = 0;
   5.950 +      if (GPIO_WB_DAT_WIDTH == 8) begin
   5.951 +	 
   5.952 +	 if (INPUT_PORTS_ONLY == 1) begin
   5.953 +	    if (DATA_WIDTH > 24)
   5.954 +	      assign GPIO_DAT_O_switch = read_byte_0 ? PIO_DATA[ 7: 0] :
   5.955 +					 read_byte_1 ? PIO_DATA[15: 8] :
   5.956 +					 read_byte_2 ? PIO_DATA[23:16] :
   5.957 +					 read_byte_3 ? PIO_DATA[DATA_WIDTH-1:24] :
   5.958 +					 read_byte_8 ? IRQ_MASK[ 7: 0] :
   5.959 +					 read_byte_9 ? IRQ_MASK[15: 8] :
   5.960 +					 read_byte_A ? IRQ_MASK[23:16] :
   5.961 +					 read_byte_B ? IRQ_MASK[DATA_WIDTH-1:24] :
   5.962 +					 read_byte_C ? EDGE_CAPTURE[ 7: 0] :
   5.963 +					 read_byte_D ? EDGE_CAPTURE[15: 8] :
   5.964 +					 read_byte_E ? EDGE_CAPTURE[23:16] :
   5.965 +					 read_byte_F ? EDGE_CAPTURE[DATA_WIDTH-1:24] :
   5.966 +					 0;
   5.967 +	    else if (DATA_WIDTH > 16)
   5.968 +	      assign GPIO_DAT_O_switch = read_byte_0 ? PIO_DATA[ 7: 0] :
   5.969 +					 read_byte_1 ? PIO_DATA[15: 8] :
   5.970 +					 read_byte_2 ? PIO_DATA[DATA_WIDTH-1:16] :
   5.971 +					 read_byte_3 ? 8'h00 :
   5.972 +					 read_byte_8 ? IRQ_MASK[ 7: 0] :
   5.973 +					 read_byte_9 ? IRQ_MASK[15: 8] :
   5.974 +					 read_byte_A ? IRQ_MASK[DATA_WIDTH-1:16] :
   5.975 +					 read_byte_B ? 8'h00 :
   5.976 +					 read_byte_C ? EDGE_CAPTURE[ 7: 0] :
   5.977 +					 read_byte_D ? EDGE_CAPTURE[15: 8] :
   5.978 +					 read_byte_E ? EDGE_CAPTURE[DATA_WIDTH-1:16] :
   5.979 +					 read_byte_F ? 8'h00 :
   5.980 +					 0;
   5.981 +	    else if (DATA_WIDTH > 8)
   5.982 +	      assign GPIO_DAT_O_switch = read_byte_0 ? PIO_DATA[ 7: 0] :
   5.983 +					 read_byte_1 ? PIO_DATA[DATA_WIDTH-1: 8] :
   5.984 +					 read_byte_2 ? 8'h00 :
   5.985 +					 read_byte_3 ? 8'h00 :
   5.986 +					 read_byte_8 ? IRQ_MASK[ 7: 0] :
   5.987 +					 read_byte_9 ? IRQ_MASK[DATA_WIDTH-1: 8] :
   5.988 +					 read_byte_A ? 8'h00 :
   5.989 +					 read_byte_B ? 8'h00 :
   5.990 +					 read_byte_C ? EDGE_CAPTURE[ 7: 0] :
   5.991 +					 read_byte_D ? EDGE_CAPTURE[DATA_WIDTH-1: 8] :
   5.992 +					 read_byte_E ? 8'h00 :
   5.993 +					 read_byte_F ? 8'h00 :
   5.994 +					 0;
   5.995 +	    else
   5.996 +	      assign GPIO_DAT_O_switch = read_byte_0 ? PIO_DATA[DATA_WIDTH-1: 0] :
   5.997 +					 read_byte_1 ? 8'h00 :
   5.998 +					 read_byte_2 ? 8'h00 :
   5.999 +					 read_byte_3 ? 8'h00 :
  5.1000 +					 read_byte_8 ? IRQ_MASK[DATA_WIDTH-1: 0] :
  5.1001 +					 read_byte_9 ? 8'h00 :
  5.1002 +					 read_byte_A ? 8'h00 :
  5.1003 +					 read_byte_B ? 8'h00 :
  5.1004 +					 read_byte_C ? EDGE_CAPTURE[DATA_WIDTH-1: 0] :
  5.1005 +					 read_byte_D ? 8'h00 :
  5.1006 +					 read_byte_E ? 8'h00 :
  5.1007 +					 read_byte_F ? 8'h00 :
  5.1008 +					 0;
  5.1009 +	 end
  5.1010 +	 else if (BOTH_INPUT_AND_OUTPUT == 1) begin
  5.1011 +	    if (INPUT_WIDTH > 24)
  5.1012 +	      assign GPIO_DAT_O_switch = read_byte_0 ? PIO_DATAI[ 7: 0] :
  5.1013 +					 read_byte_1 ? PIO_DATAI[15: 8] :
  5.1014 +					 read_byte_2 ? PIO_DATAI[23:16] :
  5.1015 +					 read_byte_3 ? PIO_DATAI[INPUT_WIDTH-1:24] :
  5.1016 +					 read_byte_8 ? IRQ_MASK_BOTH[ 7: 0] :
  5.1017 +					 read_byte_9 ? IRQ_MASK_BOTH[15: 8] :
  5.1018 +					 read_byte_A ? IRQ_MASK_BOTH[23:16] :
  5.1019 +					 read_byte_B ? IRQ_MASK_BOTH[INPUT_WIDTH-1:24] :
  5.1020 +					 read_byte_C ? EDGE_CAPTURE_BOTH[ 7: 0] :
  5.1021 +					 read_byte_D ? EDGE_CAPTURE_BOTH[15: 8] :
  5.1022 +					 read_byte_E ? EDGE_CAPTURE_BOTH[23:16] :
  5.1023 +					 read_byte_F ? EDGE_CAPTURE_BOTH[INPUT_WIDTH-1:24] :
  5.1024 +					 0;
  5.1025 +	    else if (INPUT_WIDTH > 16)
  5.1026 +	      assign GPIO_DAT_O_switch = read_byte_0 ? PIO_DATAI[ 7: 0] :
  5.1027 +					 read_byte_1 ? PIO_DATAI[15: 8] :
  5.1028 +					 read_byte_2 ? PIO_DATAI[INPUT_WIDTH-1:16] :
  5.1029 +					 read_byte_3 ? 8'h00 :
  5.1030 +					 read_byte_8 ? IRQ_MASK_BOTH[ 7: 0] :
  5.1031 +					 read_byte_9 ? IRQ_MASK_BOTH[15: 8] :
  5.1032 +					 read_byte_A ? IRQ_MASK_BOTH[INPUT_WIDTH-1:16] :
  5.1033 +					 read_byte_B ? 8'h00 :
  5.1034 +					 read_byte_C ? EDGE_CAPTURE_BOTH[ 7: 0] :
  5.1035 +					 read_byte_D ? EDGE_CAPTURE_BOTH[15: 8] :
  5.1036 +					 read_byte_E ? EDGE_CAPTURE_BOTH[INPUT_WIDTH-1:16] :
  5.1037 +					 read_byte_F ? 8'h00 :
  5.1038 +					 0;
  5.1039 +	    else if (INPUT_WIDTH > 8)      
  5.1040 +	      assign GPIO_DAT_O_switch = read_byte_0 ? PIO_DATAI[ 7: 0] :
  5.1041 +					 read_byte_1 ? PIO_DATAI[INPUT_WIDTH-1: 8] :
  5.1042 +					 read_byte_2 ? 8'h00 :
  5.1043 +					 read_byte_3 ? 8'h00 :
  5.1044 +					 read_byte_8 ? IRQ_MASK_BOTH[ 7: 0] :
  5.1045 +					 read_byte_9 ? IRQ_MASK_BOTH[INPUT_WIDTH-1: 8] :
  5.1046 +					 read_byte_A ? 8'h00 :
  5.1047 +					 read_byte_B ? 8'h00 :
  5.1048 +					 read_byte_C ? EDGE_CAPTURE_BOTH[ 7: 0] :
  5.1049 +					 read_byte_D ? EDGE_CAPTURE_BOTH[INPUT_WIDTH-1: 8] :
  5.1050 +					 read_byte_E ? 8'h00 :
  5.1051 +					 read_byte_F ? 8'h00 :
  5.1052 +					 0;
  5.1053 +	    else
  5.1054 +	      assign GPIO_DAT_O_switch = read_byte_0 ? PIO_DATAI[INPUT_WIDTH-1: 0] :
  5.1055 +					 read_byte_1 ? 8'h00 :
  5.1056 +					 read_byte_2 ? 8'h00 :
  5.1057 +					 read_byte_3 ? 8'h00 :
  5.1058 +					 read_byte_8 ? IRQ_MASK_BOTH[INPUT_WIDTH-1: 0] :
  5.1059 +					 read_byte_9 ? 8'h00 :
  5.1060 +					 read_byte_A ? 8'h00 :
  5.1061 +					 read_byte_B ? 8'h00 :
  5.1062 +					 read_byte_C ? EDGE_CAPTURE_BOTH[INPUT_WIDTH-1: 0] :
  5.1063 +					 read_byte_D ? 8'h00 :
  5.1064 +					 read_byte_E ? 8'h00 :
  5.1065 +					 read_byte_F ? 8'h00 :
  5.1066 +					 0;
  5.1067 +	 end
  5.1068 +	 else if (TRISTATE_PORTS == 1) begin
  5.1069 +	    if (DATA_WIDTH > 24)
  5.1070 +	      assign GPIO_DAT_O_switch = read_byte_0 ? tpio_out[ 7: 0] :
  5.1071 +					 read_byte_1 ? tpio_out[15: 8] :
  5.1072 +					 read_byte_2 ? tpio_out[23:16] :
  5.1073 +					 read_byte_3 ? tpio_out[DATA_WIDTH-1:24] :
  5.1074 +					 read_byte_4 ? tpio_out[ 7: 0] :
  5.1075 +					 read_byte_5 ? tpio_out[15: 8] :
  5.1076 +					 read_byte_6 ? tpio_out[23:16] :
  5.1077 +					 read_byte_7 ? tpio_out[DATA_WIDTH-1:24] :
  5.1078 +					 read_byte_8 ? tpio_out[ 7: 0] :
  5.1079 +					 read_byte_9 ? tpio_out[15: 8] :
  5.1080 +					 read_byte_A ? tpio_out[23:16] :
  5.1081 +					 read_byte_B ? tpio_out[DATA_WIDTH-1:24] :
  5.1082 +					 read_byte_C ? IRQ_TRI_TEMP[ 7: 0] :
  5.1083 +					 read_byte_D ? IRQ_TRI_TEMP[15: 8] :
  5.1084 +					 read_byte_E ? IRQ_TRI_TEMP[23:16] :
  5.1085 +					 read_byte_F ? IRQ_TRI_TEMP[DATA_WIDTH-1:24] :
  5.1086 +					 0;
  5.1087 +	    else if (DATA_WIDTH > 16)
  5.1088 +	      assign GPIO_DAT_O_switch = read_byte_0 ? tpio_out[ 7: 0] :
  5.1089 +					 read_byte_1 ? tpio_out[15: 8] :
  5.1090 +					 read_byte_2 ? tpio_out[DATA_WIDTH-1:16] :
  5.1091 +					 read_byte_3 ? 8'h00 :
  5.1092 +					 read_byte_4 ? tpio_out[ 7: 0] :
  5.1093 +					 read_byte_5 ? tpio_out[15: 8] :
  5.1094 +					 read_byte_6 ? tpio_out[DATA_WIDTH-1:16] :
  5.1095 +					 read_byte_7 ? 8'h00 :
  5.1096 +					 read_byte_8 ? tpio_out[ 7: 0] :
  5.1097 +					 read_byte_9 ? tpio_out[15: 8] :
  5.1098 +					 read_byte_A ? tpio_out[DATA_WIDTH-1:16] :
  5.1099 +					 read_byte_B ? 8'h00 :
  5.1100 +					 read_byte_C ? IRQ_TRI_TEMP[ 7: 0] :
  5.1101 +					 read_byte_D ? IRQ_TRI_TEMP[15: 8] :
  5.1102 +					 read_byte_E ? IRQ_TRI_TEMP[DATA_WIDTH-1:16] :
  5.1103 +					 read_byte_F ? 8'h00 :
  5.1104 +					 0;
  5.1105 +	    else if (DATA_WIDTH > 8)
  5.1106 +	      assign GPIO_DAT_O_switch = read_byte_0 ? tpio_out[ 7: 0] :
  5.1107 +					 read_byte_1 ? tpio_out[DATA_WIDTH-1: 8] :
  5.1108 +					 read_byte_2 ? 8'h00 :
  5.1109 +					 read_byte_3 ? 8'h00 :
  5.1110 +					 read_byte_4 ? tpio_out[ 7: 0] :
  5.1111 +					 read_byte_5 ? tpio_out[DATA_WIDTH-1: 8] :
  5.1112 +					 read_byte_6 ? 8'h00 :
  5.1113 +					 read_byte_7 ? 8'h00 :
  5.1114 +					 read_byte_8 ? tpio_out[ 7: 0] :
  5.1115 +					 read_byte_9 ? tpio_out[DATA_WIDTH-1: 8] :
  5.1116 +					 read_byte_A ? 8'h00 :
  5.1117 +					 read_byte_B ? 8'h00 :
  5.1118 +					 read_byte_C ? IRQ_TRI_TEMP[ 7: 0] :
  5.1119 +					 read_byte_D ? IRQ_TRI_TEMP[DATA_WIDTH-1: 8] :
  5.1120 +					 read_byte_E ? 8'h00 :
  5.1121 +					 read_byte_F ? 8'h00 :
  5.1122 +					 0;
  5.1123 +	    else
  5.1124 +	      assign GPIO_DAT_O_switch = read_byte_0 ? tpio_out[DATA_WIDTH-1: 0] :
  5.1125 +					 read_byte_1 ? 8'h00 :
  5.1126 +					 read_byte_2 ? 8'h00 :
  5.1127 +					 read_byte_3 ? 8'h00 :
  5.1128 +					 read_byte_4 ? tpio_out[DATA_WIDTH-1: 0] :
  5.1129 +					 read_byte_5 ? 8'h00 :
  5.1130 +					 read_byte_6 ? 8'h00 :
  5.1131 +					 read_byte_7 ? 8'h00 :
  5.1132 +					 read_byte_8 ? tpio_out[DATA_WIDTH-1: 0] :
  5.1133 +					 read_byte_9 ? 8'h00 :
  5.1134 +					 read_byte_A ? 8'h00 :
  5.1135 +					 read_byte_B ? 8'h00 :
  5.1136 +					 read_byte_C ? IRQ_TRI_TEMP[DATA_WIDTH-1: 0] :
  5.1137 +					 read_byte_D ? 8'h00 :
  5.1138 +					 read_byte_E ? 8'h00 :
  5.1139 +					 read_byte_F ? 8'h00 :
  5.1140 +					 0;
  5.1141 +	 end
  5.1142 +	 else
  5.1143 +	   assign GPIO_DAT_O_switch = 0;
  5.1144 +	 
  5.1145 +      end // if (GPIO_WB_DAT_WIDTH == 8)
  5.1146 +      
  5.1147 +      else if (GPIO_WB_DAT_WIDTH == 32) begin
  5.1148 +	 
  5.1149 +	 if (INPUT_PORTS_ONLY == 1)
  5.1150 +	   assign GPIO_DAT_O_switch = read_addr_0 ? PIO_DATA : 
  5.1151 +				      read_addr_8 ? IRQ_MASK :
  5.1152 +				      read_addr_C ? EDGE_CAPTURE :
  5.1153 +				      0;
  5.1154 +	 else if (BOTH_INPUT_AND_OUTPUT == 1)
  5.1155 +	   assign GPIO_DAT_O_switch = read_addr_0 ? PIO_DATAI : 
  5.1156 +				      read_addr_8 ? IRQ_MASK_BOTH :
  5.1157 +				      read_addr_C ? EDGE_CAPTURE_BOTH :
  5.1158 +				      0;
  5.1159 +	 else if (TRISTATE_PORTS == 1)
  5.1160 +	   assign GPIO_DAT_O_switch = read_addr_0 ? tpio_out : 
  5.1161 +				      read_addr_4 ? tpio_out : 
  5.1162 +				      read_addr_8 ? tpio_out :
  5.1163 +				      read_addr_C ? IRQ_TRI_TEMP :
  5.1164 +				      0;
  5.1165 +	 else
  5.1166 +	   assign GPIO_DAT_O_switch = 0;
  5.1167 +	 
  5.1168 +      end // if (GPIO_WB_DAT_WIDTH == 32)
  5.1169 +            
  5.1170     endgenerate
  5.1171     
  5.1172 -//-----------------------------------------------------------------------------
  5.1173 -//-------------------------------IRQ Generation--------------------------------
  5.1174 -//-----------------------------------------------------------------------------
  5.1175 +   
  5.1176 +   
  5.1177 +   //-----------------------------------------------------------------------------
  5.1178 +   //-------------------------------IRQ Generation--------------------------------
  5.1179 +   //-----------------------------------------------------------------------------
  5.1180     generate
  5.1181 +      
  5.1182        if (IRQ_MODE == 1) begin
  5.1183 -        always @(posedge CLK_I or posedge RST_I)
  5.1184 -          if (RST_I) begin
  5.1185 -            IRQ_MASK      <= #UDLY 0;
  5.1186 -            IRQ_MASK_BOTH <= #UDLY 0;
  5.1187 -          end else if (IRQ_MASK_WR_EN) begin
  5.1188 -            IRQ_MASK      <= #UDLY GPIO_DAT_I[DATA_WIDTH-1:0];   
  5.1189 -            IRQ_MASK_BOTH <= #UDLY GPIO_DAT_I[INPUT_WIDTH-1:0];   
  5.1190 -          end
  5.1191 -        end
  5.1192 +	 
  5.1193 +	 if (GPIO_WB_DAT_WIDTH == 8) begin
  5.1194 +	    
  5.1195 +	    genvar im_idx;
  5.1196 +	    for (im_idx = 0; (im_idx < DATA_WIDTH) && (im_idx < 8); im_idx = im_idx + 1)
  5.1197 +	      begin
  5.1198 +		 always @(posedge CLK_I or posedge RST_I)
  5.1199 +		   if (RST_I)
  5.1200 +		     IRQ_MASK[im_idx] <= #UDLY 0;
  5.1201 +		   else if (IRQ_MASK_WR_EN_0)
  5.1202 +		     IRQ_MASK[im_idx] <= #UDLY GPIO_DAT_I_switch[im_idx];
  5.1203 +	      end
  5.1204 +	    if (DATA_WIDTH > 8) begin
  5.1205 +	       genvar jm_idx;
  5.1206 +	       for (jm_idx = 8; (jm_idx < DATA_WIDTH) && (jm_idx < 16); jm_idx = jm_idx + 1)
  5.1207 +		 begin
  5.1208 +		    always @(posedge CLK_I or posedge RST_I)
  5.1209 +		      if (RST_I)
  5.1210 +			IRQ_MASK[jm_idx] <= #UDLY 0;
  5.1211 +		      else if (IRQ_MASK_WR_EN_1)
  5.1212 +			IRQ_MASK[jm_idx] <= #UDLY GPIO_DAT_I_switch[jm_idx-8];
  5.1213 +		 end
  5.1214 +	    end
  5.1215 +	    if (DATA_WIDTH > 16) begin
  5.1216 +	       genvar km_idx;
  5.1217 +	       for (km_idx = 16; (km_idx < DATA_WIDTH) && (km_idx < 24); km_idx = km_idx + 1)
  5.1218 +		 begin
  5.1219 +		    always @(posedge CLK_I or posedge RST_I)
  5.1220 +		      if (RST_I)
  5.1221 +			IRQ_MASK[km_idx] <= #UDLY 0;
  5.1222 +		      else if (IRQ_MASK_WR_EN_2)
  5.1223 +			IRQ_MASK[km_idx] <= #UDLY GPIO_DAT_I_switch[km_idx-16];
  5.1224 +		 end
  5.1225 +	    end
  5.1226 +	    if (DATA_WIDTH > 24) begin
  5.1227 +	       genvar lm_idx;
  5.1228 +	       for (lm_idx = 24; (lm_idx < DATA_WIDTH) && (lm_idx < 32); lm_idx = lm_idx + 1)
  5.1229 +		 begin
  5.1230 +		    always @(posedge CLK_I or posedge RST_I)
  5.1231 +		      if (RST_I)
  5.1232 +			IRQ_MASK[lm_idx] <= #UDLY 0;
  5.1233 +		      else if (IRQ_MASK_WR_EN_3)
  5.1234 +			IRQ_MASK[lm_idx] <= #UDLY GPIO_DAT_I_switch[lm_idx-24];
  5.1235 +		 end
  5.1236 +	    end
  5.1237 +	    
  5.1238 +	    genvar imb_idx;
  5.1239 +	    for (imb_idx = 0; (imb_idx < INPUT_WIDTH) && (imb_idx < 8); imb_idx = imb_idx + 1)
  5.1240 +	      begin
  5.1241 +		 always @(posedge CLK_I or posedge RST_I)
  5.1242 +		   if (RST_I)
  5.1243 +		     IRQ_MASK_BOTH[imb_idx] <= #UDLY 0;
  5.1244 +		   else if (IRQ_MASK_WR_EN_0)
  5.1245 +		     IRQ_MASK_BOTH[imb_idx] <= #UDLY GPIO_DAT_I_switch[imb_idx];
  5.1246 +	      end
  5.1247 +	    if (INPUT_WIDTH > 8) begin
  5.1248 +	       genvar jmb_idx;
  5.1249 +	       for (jmb_idx = 8; (jmb_idx < INPUT_WIDTH) && (jmb_idx < 16); jmb_idx = jmb_idx + 1)
  5.1250 +		 begin
  5.1251 +		    always @(posedge CLK_I or posedge RST_I)
  5.1252 +		      if (RST_I)
  5.1253 +			IRQ_MASK_BOTH[jmb_idx] <= #UDLY 0;
  5.1254 +		      else if (IRQ_MASK_WR_EN_1)
  5.1255 +			IRQ_MASK_BOTH[jmb_idx] <= #UDLY GPIO_DAT_I_switch[jmb_idx-8];
  5.1256 +		 end
  5.1257 +	    end
  5.1258 +	    if (INPUT_WIDTH > 16) begin
  5.1259 +	       genvar kmb_idx;
  5.1260 +	       for (kmb_idx = 16; (kmb_idx < INPUT_WIDTH) && (kmb_idx < 24); kmb_idx = kmb_idx + 1)
  5.1261 +		 begin
  5.1262 +		    always @(posedge CLK_I or posedge RST_I)
  5.1263 +		      if (RST_I)
  5.1264 +			IRQ_MASK_BOTH[kmb_idx] <= #UDLY 0;
  5.1265 +		      else if (IRQ_MASK_WR_EN_2)
  5.1266 +			IRQ_MASK_BOTH[kmb_idx] <= #UDLY GPIO_DAT_I_switch[kmb_idx-16];
  5.1267 +		 end
  5.1268 +	    end
  5.1269 +	    if (INPUT_WIDTH > 24) begin
  5.1270 +	       genvar lmb_idx;
  5.1271 +	       for (lmb_idx = 24; (lmb_idx < INPUT_WIDTH) && (lmb_idx < 32); lmb_idx = lmb_idx + 1)
  5.1272 +		 begin
  5.1273 +		    always @(posedge CLK_I or posedge RST_I)
  5.1274 +		      if (RST_I)
  5.1275 +			IRQ_MASK_BOTH[lmb_idx] <= #UDLY 0;
  5.1276 +		      else if (IRQ_MASK_WR_EN_3)
  5.1277 +			IRQ_MASK_BOTH[lmb_idx] <= #UDLY GPIO_DAT_I_switch[lmb_idx-24];
  5.1278 +		 end
  5.1279 +	    end
  5.1280 +	    
  5.1281 +	 end // if (GPIO_WB_DAT_WIDTH == 8)
  5.1282 +	 else if (GPIO_WB_DAT_WIDTH == 32) begin
  5.1283 +	    
  5.1284 +	    genvar im_idx;
  5.1285 +	    for (im_idx = 0; (im_idx < DATA_WIDTH) && (im_idx < 8); im_idx = im_idx + 1)
  5.1286 +	      begin
  5.1287 +		 always @(posedge CLK_I or posedge RST_I)
  5.1288 +		   if (RST_I)
  5.1289 +		     IRQ_MASK[im_idx] <= #UDLY 0;
  5.1290 +		   else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[0])
  5.1291 +		     IRQ_MASK[im_idx] <= #UDLY GPIO_DAT_I_switch[im_idx];
  5.1292 +	      end
  5.1293 +	    if (DATA_WIDTH > 8) begin
  5.1294 +	       genvar jm_idx;
  5.1295 +	       for (jm_idx = 8; (jm_idx < DATA_WIDTH) && (jm_idx < 16); jm_idx = jm_idx + 1)
  5.1296 +		 begin
  5.1297 +		    always @(posedge CLK_I or posedge RST_I)
  5.1298 +		      if (RST_I)
  5.1299 +			IRQ_MASK[jm_idx] <= #UDLY 0;
  5.1300 +		      else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[1])
  5.1301 +			IRQ_MASK[jm_idx] <= #UDLY GPIO_DAT_I_switch[jm_idx];
  5.1302 +		 end
  5.1303 +	    end
  5.1304 +	    if (DATA_WIDTH > 16) begin
  5.1305 +	       genvar km_idx;
  5.1306 +	       for (km_idx = 16; (km_idx < DATA_WIDTH) && (km_idx < 24); km_idx = km_idx + 1)
  5.1307 +		 begin
  5.1308 +		    always @(posedge CLK_I or posedge RST_I)
  5.1309 +		      if (RST_I)
  5.1310 +			IRQ_MASK[km_idx] <= #UDLY 0;
  5.1311 +		      else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[2])
  5.1312 +			IRQ_MASK[km_idx] <= #UDLY GPIO_DAT_I_switch[km_idx];
  5.1313 +		 end
  5.1314 +	    end
  5.1315 +	    if (DATA_WIDTH > 24) begin
  5.1316 +	       genvar lm_idx;
  5.1317 +	       for (lm_idx = 24; (lm_idx < DATA_WIDTH) && (lm_idx < 32); lm_idx = lm_idx + 1)
  5.1318 +		 begin
  5.1319 +		    always @(posedge CLK_I or posedge RST_I)
  5.1320 +		      if (RST_I)
  5.1321 +			IRQ_MASK[lm_idx] <= #UDLY 0;
  5.1322 +		      else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[3])
  5.1323 +			IRQ_MASK[lm_idx] <= #UDLY GPIO_DAT_I_switch[lm_idx];
  5.1324 +		 end
  5.1325 +	    end
  5.1326 +	    
  5.1327 +	    genvar imb_idx;
  5.1328 +	    for (imb_idx = 0; (imb_idx < INPUT_WIDTH) && (imb_idx < 8); imb_idx = imb_idx + 1)
  5.1329 +	      begin
  5.1330 +		 always @(posedge CLK_I or posedge RST_I)
  5.1331 +		   if (RST_I)
  5.1332 +		     IRQ_MASK_BOTH[imb_idx] <= #UDLY 0;
  5.1333 +		   else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[0])
  5.1334 +		     IRQ_MASK_BOTH[imb_idx] <= #UDLY GPIO_DAT_I_switch[imb_idx];
  5.1335 +	      end
  5.1336 +	    if (INPUT_WIDTH > 8) begin
  5.1337 +	       genvar jmb_idx;
  5.1338 +	       for (jmb_idx = 8; (jmb_idx < INPUT_WIDTH) && (jmb_idx < 16); jmb_idx = jmb_idx + 1)
  5.1339 +		 begin
  5.1340 +		    always @(posedge CLK_I or posedge RST_I)
  5.1341 +		      if (RST_I)
  5.1342 +			IRQ_MASK_BOTH[jmb_idx] <= #UDLY 0;
  5.1343 +		      else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[1])
  5.1344 +			IRQ_MASK_BOTH[jmb_idx] <= #UDLY GPIO_DAT_I_switch[jmb_idx];
  5.1345 +		 end
  5.1346 +	    end
  5.1347 +	    if (INPUT_WIDTH > 16) begin
  5.1348 +	       genvar kmb_idx;
  5.1349 +	       for (kmb_idx = 16; (kmb_idx < INPUT_WIDTH) && (kmb_idx < 24); kmb_idx = kmb_idx + 1)
  5.1350 +		 begin
  5.1351 +		    always @(posedge CLK_I or posedge RST_I)
  5.1352 +		      if (RST_I)
  5.1353 +			IRQ_MASK_BOTH[kmb_idx] <= #UDLY 0;
  5.1354 +		      else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[2])
  5.1355 +			IRQ_MASK_BOTH[kmb_idx] <= #UDLY GPIO_DAT_I_switch[kmb_idx];
  5.1356 +		 end
  5.1357 +	    end
  5.1358 +	    if (INPUT_WIDTH > 24) begin
  5.1359 +	       genvar lmb_idx;
  5.1360 +	       for (lmb_idx = 24; (lmb_idx < INPUT_WIDTH) && (lmb_idx < 32); lmb_idx = lmb_idx + 1)
  5.1361 +		 begin
  5.1362 +		    always @(posedge CLK_I or posedge RST_I)
  5.1363 +		      if (RST_I)
  5.1364 +			IRQ_MASK_BOTH[lmb_idx] <= #UDLY 0;
  5.1365 +		      else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[3])
  5.1366 +			IRQ_MASK_BOTH[lmb_idx] <= #UDLY GPIO_DAT_I_switch[lmb_idx];
  5.1367 +		 end
  5.1368 +	    end
  5.1369 +	    
  5.1370 +	 end // if (GPIO_WB_DAT_WIDTH == 32)
  5.1371 +	 	 
  5.1372 +      end // if (IRQ_MODE == 1)
  5.1373 +            
  5.1374     endgenerate
  5.1375 -
  5.1376 +   
  5.1377 +   
  5.1378 +   
  5.1379     generate 
  5.1380        //--------------------------------
  5.1381        //--INPUT_PORTS_ONLY MODE IRQ
  5.1382        //--------------------------------
  5.1383 -      if (IRQ_MODE == 1 && INPUT_PORTS_ONLY == 1 && LEVEL == 1) begin   
  5.1384 -         //level mode IRQ
  5.1385 -         always @(posedge CLK_I or posedge RST_I)
  5.1386 -           if (RST_I)
  5.1387 -             IRQ_TEMP <= #UDLY 0;
  5.1388 -           else if (IRQ_MASK_WR_EN)
  5.1389 -             IRQ_TEMP <= #UDLY IRQ_TEMP & GPIO_DAT_I[DATA_WIDTH-1:0];
  5.1390 -              else
  5.1391 -             IRQ_TEMP <= #UDLY PIO_IN & IRQ_MASK;//bit-and   
  5.1392 +      if ((IRQ_MODE == 1) && (INPUT_PORTS_ONLY == 1) && (LEVEL == 1)) begin
  5.1393 +	 // level mode IRQ
  5.1394 +	 
  5.1395 +	 if (GPIO_WB_DAT_WIDTH == 8) begin
  5.1396 +	    
  5.1397 +	    genvar i;
  5.1398 +	    for (i = 0; (i < DATA_WIDTH) && (i < 8); i = i + 1)
  5.1399 +	      begin
  5.1400 +		 always @(posedge CLK_I or posedge RST_I)
  5.1401 +		   if (RST_I)
  5.1402 +		  IRQ_TEMP[i] <= #UDLY 0;
  5.1403 +		   else if (IRQ_MASK_WR_EN_0)
  5.1404 +		     IRQ_TEMP[i] <= #UDLY IRQ_TEMP[i] & GPIO_DAT_I_switch[i];
  5.1405 +		   else
  5.1406 +		     IRQ_TEMP[i] <= #UDLY PIO_IN[i] & IRQ_MASK[i];
  5.1407 +	      end
  5.1408 +	    if (DATA_WIDTH > 8) begin
  5.1409 +	       genvar j;
  5.1410 +	       for (j = 8; (j < DATA_WIDTH) && (j < 16); j = j + 1)
  5.1411 +		 begin
  5.1412 +		    always @(posedge CLK_I or posedge RST_I)
  5.1413 +		      if (RST_I)
  5.1414 +			IRQ_TEMP[j] <= #UDLY 0;
  5.1415 +		      else if (IRQ_MASK_WR_EN_1)
  5.1416 +			IRQ_TEMP[j] <= #UDLY IRQ_TEMP[j] & GPIO_DAT_I_switch[j-8];
  5.1417 +		      else
  5.1418 +			IRQ_TEMP[j] <= #UDLY PIO_IN[j] & IRQ_MASK[j];
  5.1419 +		 end
  5.1420 +	    end
  5.1421 +	    if (DATA_WIDTH > 16) begin
  5.1422 +	       genvar k;
  5.1423 +	       for (k = 16; (k < DATA_WIDTH) && (k < 24); k = k + 1)
  5.1424 +		 begin
  5.1425 +		    always @(posedge CLK_I or posedge RST_I)
  5.1426 +		      if (RST_I)
  5.1427 +			IRQ_TEMP[k] <= #UDLY 0;
  5.1428 +		      else if (IRQ_MASK_WR_EN_2)		  
  5.1429 +			IRQ_TEMP[k] <= #UDLY IRQ_TEMP[k] & GPIO_DAT_I_switch[k-16];
  5.1430 +		      else
  5.1431 +			IRQ_TEMP[k] <= #UDLY PIO_IN[k] & IRQ_MASK[k];
  5.1432 +		 end
  5.1433 +	    end
  5.1434 +	    if (DATA_WIDTH > 24) begin
  5.1435 +	       genvar l;
  5.1436 +	       for (l = 24; (l < DATA_WIDTH) && (l < 32); l = l + 1)
  5.1437 +		 begin
  5.1438 +		    always @(posedge CLK_I or posedge RST_I)
  5.1439 +		      if (RST_I)
  5.1440 +			IRQ_TEMP[l] <= #UDLY 0;
  5.1441 +		      else if (IRQ_MASK_WR_EN_3)
  5.1442 +			IRQ_TEMP[l] <= #UDLY IRQ_TEMP[l] & GPIO_DAT_I_switch[l-24];
  5.1443 +		      else
  5.1444 +			IRQ_TEMP[l] <= #UDLY PIO_IN[l] & IRQ_MASK[l];
  5.1445 +		 end
  5.1446 +	    end
  5.1447 +	    
  5.1448 +	 end // if (GPIO_WB_DAT_WIDTH == 8)
  5.1449 +	 
  5.1450 +	 else if (GPIO_WB_DAT_WIDTH == 32) begin
  5.1451 +	    
  5.1452 +	    genvar i;
  5.1453 +	    for (i = 0; (i < DATA_WIDTH) && (i < 8); i = i + 1)
  5.1454 +	      begin
  5.1455 +		 always @(posedge CLK_I or posedge RST_I)
  5.1456 +		   if (RST_I)
  5.1457 +		  IRQ_TEMP[i] <= #UDLY 0;
  5.1458 +		   else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[0])
  5.1459 +		     IRQ_TEMP[i] <= #UDLY IRQ_TEMP[i] & GPIO_DAT_I_switch[i];
  5.1460 +		   else
  5.1461 +		     IRQ_TEMP[i] <= #UDLY PIO_IN[i] & IRQ_MASK[i];
  5.1462 +	      end
  5.1463 +	    if (DATA_WIDTH > 8) begin
  5.1464 +	       genvar j;
  5.1465 +	       for (j = 8; (j < DATA_WIDTH) && (j < 16); j = j + 1)
  5.1466 +		 begin
  5.1467 +		    always @(posedge CLK_I or posedge RST_I)
  5.1468 +		      if (RST_I)
  5.1469 +			IRQ_TEMP[j] <= #UDLY 0;
  5.1470 +		      else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[1])
  5.1471 +			IRQ_TEMP[j] <= #UDLY IRQ_TEMP[j] & GPIO_DAT_I_switch[j];
  5.1472 +		      else
  5.1473 +			IRQ_TEMP[j] <= #UDLY PIO_IN[j] & IRQ_MASK[j];
  5.1474 +		 end
  5.1475 +	    end
  5.1476 +	    if (DATA_WIDTH > 16) begin
  5.1477 +	       genvar k;
  5.1478 +	       for (k = 16; (k < DATA_WIDTH) && (k < 24); k = k + 1)
  5.1479 +		 begin
  5.1480 +		    always @(posedge CLK_I or posedge RST_I)
  5.1481 +		      if (RST_I)
  5.1482 +			IRQ_TEMP[k] <= #UDLY 0;
  5.1483 +		      else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[2])		  
  5.1484 +			IRQ_TEMP[k] <= #UDLY IRQ_TEMP[k] & GPIO_DAT_I_switch[k];
  5.1485 +		      else
  5.1486 +			IRQ_TEMP[k] <= #UDLY PIO_IN[k] & IRQ_MASK[k];
  5.1487 +		 end
  5.1488 +	    end
  5.1489 +	    if (DATA_WIDTH > 24) begin
  5.1490 +	       genvar l;
  5.1491 +	       for (l = 24; (l < DATA_WIDTH) && (l < 32); l = l + 1)
  5.1492 +		 begin
  5.1493 +		    always @(posedge CLK_I or posedge RST_I)
  5.1494 +		      if (RST_I)
  5.1495 +			IRQ_TEMP[l] <= #UDLY 0;
  5.1496 +		      else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[3])
  5.1497 +			IRQ_TEMP[l] <= #UDLY IRQ_TEMP[l] & GPIO_DAT_I_switch[l];
  5.1498 +		      else
  5.1499 +			IRQ_TEMP[l] <= #UDLY PIO_IN[l] & IRQ_MASK[l];
  5.1500 +		 end
  5.1501 +	    end
  5.1502 +	    
  5.1503 +	 end // if (GPIO_WB_DAT_WIDTH == 32)
  5.1504 +	 	 
  5.1505           assign   IRQ_O = |IRQ_TEMP;
  5.1506 -      end else if (IRQ_MODE == 1 && INPUT_PORTS_ONLY == 1 && EDGE == 1) begin   
  5.1507 +	 
  5.1508 +      end // if ((IRQ_MODE == 1) && (INPUT_PORTS_ONLY == 1) && (LEVEL == 1))
  5.1509 +      
  5.1510 +      else if ((IRQ_MODE == 1) && (INPUT_PORTS_ONLY == 1) && (EDGE == 1)) begin
  5.1511 +	 // edge mode IRQ
  5.1512 +	 
  5.1513           always @(posedge CLK_I or posedge RST_I)
  5.1514             if (RST_I)
  5.1515               PIO_DATA_DLY <= #UDLY 0;
  5.1516             else
  5.1517               PIO_DATA_DLY <= PIO_IN;
  5.1518 -
  5.1519 +	 
  5.1520           // edge-capture register bits are treated as individual bits.
  5.1521 -         genvar i;
  5.1522 -         for( i = 0; i < DATA_WIDTH; i = i + 1)
  5.1523 -         begin
  5.1524 -             always @(posedge CLK_I or posedge RST_I)
  5.1525 -                 if (RST_I)
  5.1526 -                   EDGE_CAPTURE[i] <= #UDLY 0;
  5.1527 -                 else if (|(PIO_IN[i] & ~PIO_DATA_DLY[i]) && (POSE_EDGE_IRQ == 1))
  5.1528 -                   EDGE_CAPTURE[i] <= #UDLY PIO_IN[i] & ~PIO_DATA_DLY[i];
  5.1529 -                 else if (|(~PIO_IN[i] & PIO_DATA_DLY[i]) && (NEGE_EDGE_IRQ == 1))
  5.1530 -                   EDGE_CAPTURE[i] <= #UDLY ~PIO_IN[i] & PIO_DATA_DLY[i];
  5.1531 -                 else if (|(PIO_IN[i] & ~PIO_DATA_DLY[i]) && (EITHER_EDGE_IRQ == 1))
  5.1532 -                   EDGE_CAPTURE[i] <= #UDLY PIO_IN[i] & ~PIO_DATA_DLY[i];
  5.1533 -                 else if (|(~PIO_IN[i] & PIO_DATA_DLY[i]) && (EITHER_EDGE_IRQ == 1))
  5.1534 -                   EDGE_CAPTURE[i] <= #UDLY ~PIO_IN[i] & PIO_DATA_DLY[i];
  5.1535 -                 else if ( (~IRQ_MASK[i]) & GPIO_DAT_I[i] & IRQ_MASK_WR_EN )
  5.1536 -                   // interrupt mask is being set, so clear edge-capture
  5.1537 -                   EDGE_CAPTURE[i] <= #UDLY 0;
  5.1538 -                 else if (EDGE_CAP_WR_EN)
  5.1539 -                   // user's writing to the edge register, so update edge capture
  5.1540 -                   // register
  5.1541 -                   EDGE_CAPTURE[i] <= #UDLY EDGE_CAPTURE[i] & GPIO_DAT_I[i];
  5.1542 -         end
  5.1543 -         assign  IRQ_O = |(EDGE_CAPTURE & IRQ_MASK);
  5.1544 +	 if (GPIO_WB_DAT_WIDTH == 8) begin
  5.1545 +	    
  5.1546 +            genvar i;
  5.1547 +            for (i = 0; (i < DATA_WIDTH) && (i < 8); i = i + 1)
  5.1548 +              begin
  5.1549 +		 always @(posedge CLK_I or posedge RST_I)
  5.1550 +                   if (RST_I)
  5.1551 +                     EDGE_CAPTURE[i] <= #UDLY 0;
  5.1552 +                   else if (|(PIO_IN[i] & ~PIO_DATA_DLY[i]) && (POSE_EDGE_IRQ == 1))
  5.1553 +                     EDGE_CAPTURE[i] <= #UDLY PIO_IN[i] & ~PIO_DATA_DLY[i];
  5.1554 +                   else if (|(~PIO_IN[i] & PIO_DATA_DLY[i]) && (NEGE_EDGE_IRQ == 1))
  5.1555 +                     EDGE_CAPTURE[i] <= #UDLY ~PIO_IN[i] & PIO_DATA_DLY[i];
  5.1556 +                   else if (|(PIO_IN[i] & ~PIO_DATA_DLY[i]) && (EITHER_EDGE_IRQ == 1))
  5.1557 +                     EDGE_CAPTURE[i] <= #UDLY PIO_IN[i] & ~PIO_DATA_DLY[i];
  5.1558 +                   else if (|(~PIO_IN[i] & PIO_DATA_DLY[i]) && (EITHER_EDGE_IRQ == 1))
  5.1559 +                     EDGE_CAPTURE[i] <= #UDLY ~PIO_IN[i] & PIO_DATA_DLY[i];
  5.1560 +                   else if ( (~IRQ_MASK[i]) & GPIO_DAT_I_switch[i] & IRQ_MASK_WR_EN_0)
  5.1561 +                     // interrupt mask is being set, so clear edge-capture
  5.1562 +                     EDGE_CAPTURE[i] <= #UDLY 0;
  5.1563 +                   else if (EDGE_CAP_WR_EN_0)
  5.1564 +                     // user's writing to the edge register, so update edge capture
  5.1565 +                     // register
  5.1566 +                     EDGE_CAPTURE[i] <= #UDLY EDGE_CAPTURE[i] & GPIO_DAT_I_switch[i];
  5.1567 +              end
  5.1568 +	    
  5.1569 +	    if (DATA_WIDTH > 8) begin
  5.1570 +               genvar j;
  5.1571 +               for (j = 8; (j < DATA_WIDTH) && (j < 16); j = j + 1)
  5.1572 +		 begin
  5.1573 +		    always @(posedge CLK_I or posedge RST_I)
  5.1574 +                      if (RST_I)
  5.1575 +			EDGE_CAPTURE[j] <= #UDLY 0;
  5.1576 +                      else if (|(PIO_IN[j] & ~PIO_DATA_DLY[j]) && (POSE_EDGE_IRQ == 1))
  5.1577 +			EDGE_CAPTURE[j] <= #UDLY PIO_IN[j] & ~PIO_DATA_DLY[j];
  5.1578 +                      else if (|(~PIO_IN[j] & PIO_DATA_DLY[j]) && (NEGE_EDGE_IRQ == 1))
  5.1579 +			EDGE_CAPTURE[j] <= #UDLY ~PIO_IN[j] & PIO_DATA_DLY[j];
  5.1580 +                      else if (|(PIO_IN[j] & ~PIO_DATA_DLY[j]) && (EITHER_EDGE_IRQ == 1))
  5.1581 +			EDGE_CAPTURE[j] <= #UDLY PIO_IN[j] & ~PIO_DATA_DLY[j];
  5.1582 +                      else if (|(~PIO_IN[j] & PIO_DATA_DLY[j]) && (EITHER_EDGE_IRQ == 1))
  5.1583 +			EDGE_CAPTURE[j] <= #UDLY ~PIO_IN[j] & PIO_DATA_DLY[j];
  5.1584 +                      else if ( (~IRQ_MASK[j]) & GPIO_DAT_I_switch[j-8] & IRQ_MASK_WR_EN_1)
  5.1585 +			// interrupt mask is being set, so clear edge-capture
  5.1586 +			EDGE_CAPTURE[j] <= #UDLY 0;
  5.1587 +                      else if (EDGE_CAP_WR_EN_1)
  5.1588 +			// user's writing to the edge register, so update edge capture
  5.1589 +			// register
  5.1590 +			EDGE_CAPTURE[j] <= #UDLY EDGE_CAPTURE[j] & GPIO_DAT_I_switch[j-8];
  5.1591 +		 end
  5.1592 +	    end
  5.1593 +	    
  5.1594 +	    if (DATA_WIDTH > 16) begin
  5.1595 +               genvar k;
  5.1596 +               for (k = 16; (k < DATA_WIDTH) && (k < 24); k = k + 1)
  5.1597 +		 begin
  5.1598 +		    always @(posedge CLK_I or posedge RST_I)
  5.1599 +                      if (RST_I)
  5.1600 +			EDGE_CAPTURE[k] <= #UDLY 0;
  5.1601 +                      else if (|(PIO_IN[k] & ~PIO_DATA_DLY[k]) && (POSE_EDGE_IRQ == 1))
  5.1602 +			EDGE_CAPTURE[k] <= #UDLY PIO_IN[k] & ~PIO_DATA_DLY[k];
  5.1603 +                      else if (|(~PIO_IN[k] & PIO_DATA_DLY[k]) && (NEGE_EDGE_IRQ == 1))
  5.1604 +			EDGE_CAPTURE[k] <= #UDLY ~PIO_IN[k] & PIO_DATA_DLY[k];
  5.1605 +                      else if (|(PIO_IN[k] & ~PIO_DATA_DLY[k]) && (EITHER_EDGE_IRQ == 1))
  5.1606 +			EDGE_CAPTURE[k] <= #UDLY PIO_IN[k] & ~PIO_DATA_DLY[k];
  5.1607 +                      else if (|(~PIO_IN[k] & PIO_DATA_DLY[k]) && (EITHER_EDGE_IRQ == 1))
  5.1608 +			EDGE_CAPTURE[k] <= #UDLY ~PIO_IN[k] & PIO_DATA_DLY[k];
  5.1609 +                      else if ( (~IRQ_MASK[k]) & GPIO_DAT_I_switch[k-16] & IRQ_MASK_WR_EN_2)
  5.1610 +			// interrupt mask is being set, so clear edge-capture
  5.1611 +			EDGE_CAPTURE[k] <= #UDLY 0;
  5.1612 +                      else if (EDGE_CAP_WR_EN_2)
  5.1613 +			// user's writing to the edge register, so update edge capture
  5.1614 +			// register
  5.1615 +			EDGE_CAPTURE[k] <= #UDLY EDGE_CAPTURE[k] & GPIO_DAT_I_switch[k-16];
  5.1616 +		 end
  5.1617 +	    end
  5.1618 +	    
  5.1619 +	    if (DATA_WIDTH > 24) begin
  5.1620 +               genvar l;
  5.1621 +               for (l = 24; l < DATA_WIDTH; l = l + 1)
  5.1622 +		 begin
  5.1623 +		    always @(posedge CLK_I or posedge RST_I)
  5.1624 +                      if (RST_I)
  5.1625 +			EDGE_CAPTURE[l] <= #UDLY 0;
  5.1626 +                      else if (|(PIO_IN[l] & ~PIO_DATA_DLY[l]) && (POSE_EDGE_IRQ == 1))
  5.1627 +			EDGE_CAPTURE[l] <= #UDLY PIO_IN[l] & ~PIO_DATA_DLY[l];
  5.1628 +                      else if (|(~PIO_IN[l] & PIO_DATA_DLY[l]) && (NEGE_EDGE_IRQ == 1))
  5.1629 +			EDGE_CAPTURE[l] <= #UDLY ~PIO_IN[l] & PIO_DATA_DLY[l];
  5.1630 +                      else if (|(PIO_IN[l] & ~PIO_DATA_DLY[l]) && (EITHER_EDGE_IRQ == 1))
  5.1631 +			EDGE_CAPTURE[l] <= #UDLY PIO_IN[l] & ~PIO_DATA_DLY[l];
  5.1632 +                      else if (|(~PIO_IN[l] & PIO_DATA_DLY[l]) && (EITHER_EDGE_IRQ == 1))
  5.1633 +			EDGE_CAPTURE[l] <= #UDLY ~PIO_IN[l] & PIO_DATA_DLY[l];
  5.1634 +                      else if ( (~IRQ_MASK[l]) & GPIO_DAT_I_switch[l-24] & IRQ_MASK_WR_EN_3)
  5.1635 +			// interrupt mask is being set, so clear edge-capture
  5.1636 +			EDGE_CAPTURE[l] <= #UDLY 0;
  5.1637 +                      else if (EDGE_CAP_WR_EN_3)
  5.1638 +			// user's writing to the edge register, so update edge capture
  5.1639 +			// register
  5.1640 +			EDGE_CAPTURE[l] <= #UDLY EDGE_CAPTURE[l] & GPIO_DAT_I_switch[l-24];
  5.1641 +		 end
  5.1642 +	    end
  5.1643 +	    
  5.1644 +	 end // if (GPIO_WB_DAT_WIDTH == 8)
  5.1645 +	 else if (GPIO_WB_DAT_WIDTH == 32) begin
  5.1646 +	    
  5.1647 +            genvar i;
  5.1648 +            for (i = 0; (i < DATA_WIDTH) && (i < 8); i = i + 1)
  5.1649 +              begin
  5.1650 +		 always @(posedge CLK_I or posedge RST_I)
  5.1651 +                   if (RST_I)
  5.1652 +                     EDGE_CAPTURE[i] <= #UDLY 0;
  5.1653 +                   else if (|(PIO_IN[i] & ~PIO_DATA_DLY[i]) && (POSE_EDGE_IRQ == 1))
  5.1654 +                     EDGE_CAPTURE[i] <= #UDLY PIO_IN[i] & ~PIO_DATA_DLY[i];
  5.1655 +                   else if (|(~PIO_IN[i] & PIO_DATA_DLY[i]) && (NEGE_EDGE_IRQ == 1))
  5.1656 +                     EDGE_CAPTURE[i] <= #UDLY ~PIO_IN[i] & PIO_DATA_DLY[i];
  5.1657 +                   else if (|(PIO_IN[i] & ~PIO_DATA_DLY[i]) && (EITHER_EDGE_IRQ == 1))
  5.1658 +                     EDGE_CAPTURE[i] <= #UDLY PIO_IN[i] & ~PIO_DATA_DLY[i];
  5.1659 +                   else if (|(~PIO_IN[i] & PIO_DATA_DLY[i]) && (EITHER_EDGE_IRQ == 1))
  5.1660 +                     EDGE_CAPTURE[i] <= #UDLY ~PIO_IN[i] & PIO_DATA_DLY[i];
  5.1661 +                   else if ( (~IRQ_MASK[i]) & GPIO_DAT_I_switch[i] & IRQ_MASK_WR_EN && GPIO_SEL_I_switch[0])
  5.1662 +                     // interrupt mask is being set, so clear edge-capture
  5.1663 +                     EDGE_CAPTURE[i] <= #UDLY 0;
  5.1664 +                   else if (EDGE_CAP_WR_EN && GPIO_SEL_I_switch[0])
  5.1665 +                     // user's writing to the edge register, so update edge capture
  5.1666 +                     // register
  5.1667 +                     EDGE_CAPTURE[i] <= #UDLY EDGE_CAPTURE[i] & GPIO_DAT_I_switch[i];
  5.1668 +              end
  5.1669 +	    
  5.1670 +	    if (DATA_WIDTH > 8) begin
  5.1671 +               genvar j;
  5.1672 +               for (j = 8; (j < DATA_WIDTH) && (j < 16); j = j + 1)
  5.1673 +		 begin
  5.1674 +		    always @(posedge CLK_I or posedge RST_I)
  5.1675 +                      if (RST_I)
  5.1676 +			EDGE_CAPTURE[j] <= #UDLY 0;
  5.1677 +                      else if (|(PIO_IN[j] & ~PIO_DATA_DLY[j]) && (POSE_EDGE_IRQ == 1))
  5.1678 +			EDGE_CAPTURE[j] <= #UDLY PIO_IN[j] & ~PIO_DATA_DLY[j];
  5.1679 +                      else if (|(~PIO_IN[j] & PIO_DATA_DLY[j]) && (NEGE_EDGE_IRQ == 1))
  5.1680 +			EDGE_CAPTURE[j] <= #UDLY ~PIO_IN[j] & PIO_DATA_DLY[j];
  5.1681 +                      else if (|(PIO_IN[j] & ~PIO_DATA_DLY[j]) && (EITHER_EDGE_IRQ == 1))
  5.1682 +			EDGE_CAPTURE[j] <= #UDLY PIO_IN[j] & ~PIO_DATA_DLY[j];
  5.1683 +                      else if (|(~PIO_IN[j] & PIO_DATA_DLY[j]) && (EITHER_EDGE_IRQ == 1))
  5.1684 +			EDGE_CAPTURE[j] <= #UDLY ~PIO_IN[j] & PIO_DATA_DLY[j];
  5.1685 +                      else if ( (~IRQ_MASK[j]) & GPIO_DAT_I_switch[j-8] & IRQ_MASK_WR_EN && GPIO_SEL_I_switch[0])
  5.1686 +			// interrupt mask is being set, so clear edge-capture
  5.1687 +			EDGE_CAPTURE[j] <= #UDLY 0;
  5.1688 +                      else if (EDGE_CAP_WR_EN && GPIO_SEL_I_switch[0])
  5.1689 +			// user's writing to the edge register, so update edge capture
  5.1690 +			// register
  5.1691 +			EDGE_CAPTURE[j] <= #UDLY EDGE_CAPTURE[j] & GPIO_DAT_I_switch[j];
  5.1692 +		 end
  5.1693 +	    end
  5.1694 +	    
  5.1695 +	    if (DATA_WIDTH > 16) begin
  5.1696 +               genvar k;
  5.1697 +               for (k = 16; (k < DATA_WIDTH) && (k < 24); k = k + 1)
  5.1698 +		 begin
  5.1699 +		    always @(posedge CLK_I or posedge RST_I)
  5.1700 +                      if (RST_I)
  5.1701 +			EDGE_CAPTURE[k] <= #UDLY 0;
  5.1702 +                      else if (|(PIO_IN[k] & ~PIO_DATA_DLY[k]) && (POSE_EDGE_IRQ == 1))
  5.1703 +			EDGE_CAPTURE[k] <= #UDLY PIO_IN[k] & ~PIO_DATA_DLY[k];
  5.1704 +                      else if (|(~PIO_IN[k] & PIO_DATA_DLY[k]) && (NEGE_EDGE_IRQ == 1))
  5.1705 +			EDGE_CAPTURE[k] <= #UDLY ~PIO_IN[k] & PIO_DATA_DLY[k];
  5.1706 +                      else if (|(PIO_IN[k] & ~PIO_DATA_DLY[k]) && (EITHER_EDGE_IRQ == 1))
  5.1707 +			EDGE_CAPTURE[k] <= #UDLY PIO_IN[k] & ~PIO_DATA_DLY[k];
  5.1708 +                      else if (|(~PIO_IN[k] & PIO_DATA_DLY[k]) && (EITHER_EDGE_IRQ == 1))
  5.1709 +			EDGE_CAPTURE[k] <= #UDLY ~PIO_IN[k] & PIO_DATA_DLY[k];
  5.1710 +                      else if ( (~IRQ_MASK[k]) & GPIO_DAT_I_switch[k-16] & IRQ_MASK_WR_EN && GPIO_SEL_I_switch[2])
  5.1711 +			// interrupt mask is being set, so clear edge-capture
  5.1712 +			EDGE_CAPTURE[k] <= #UDLY 0;
  5.1713 +                      else if (EDGE_CAP_WR_EN && GPIO_SEL_I_switch[2])
  5.1714 +			// user's writing to the edge register, so update edge capture
  5.1715 +			// register
  5.1716 +			EDGE_CAPTURE[k] <= #UDLY EDGE_CAPTURE[k] & GPIO_DAT_I_switch[k];
  5.1717 +		 end
  5.1718 +	    end
  5.1719 +	    
  5.1720 +	    if (DATA_WIDTH > 24) begin
  5.1721 +               genvar l;
  5.1722 +               for (l = 24; l < DATA_WIDTH; l = l + 1)
  5.1723 +		 begin
  5.1724 +		    always @(posedge CLK_I or posedge RST_I)
  5.1725 +                      if (RST_I)
  5.1726 +			EDGE_CAPTURE[l] <= #UDLY 0;
  5.1727 +                      else if (|(PIO_IN[l] & ~PIO_DATA_DLY[l]) && (POSE_EDGE_IRQ == 1))
  5.1728 +			EDGE_CAPTURE[l] <= #UDLY PIO_IN[l] & ~PIO_DATA_DLY[l];
  5.1729 +                      else if (|(~PIO_IN[l] & PIO_DATA_DLY[l]) && (NEGE_EDGE_IRQ == 1))
  5.1730 +			EDGE_CAPTURE[l] <= #UDLY ~PIO_IN[l] & PIO_DATA_DLY[l];
  5.1731 +                      else if (|(PIO_IN[l] & ~PIO_DATA_DLY[l]) && (EITHER_EDGE_IRQ == 1))
  5.1732 +			EDGE_CAPTURE[l] <= #UDLY PIO_IN[l] & ~PIO_DATA_DLY[l];
  5.1733 +                      else if (|(~PIO_IN[l] & PIO_DATA_DLY[l]) && (EITHER_EDGE_IRQ == 1))
  5.1734 +			EDGE_CAPTURE[l] <= #UDLY ~PIO_IN[l] & PIO_DATA_DLY[l];
  5.1735 +                      else if ( (~IRQ_MASK[l]) & GPIO_DAT_I_switch[l-24] & IRQ_MASK_WR_EN && GPIO_SEL_I_switch[3])
  5.1736 +			// interrupt mask is being set, so clear edge-capture
  5.1737 +			EDGE_CAPTURE[l] <= #UDLY 0;
  5.1738 +                      else if (EDGE_CAP_WR_EN && GPIO_SEL_I_switch[3])
  5.1739 +			// user's writing to the edge register, so update edge capture
  5.1740 +			// register
  5.1741 +			EDGE_CAPTURE[l] <= #UDLY EDGE_CAPTURE[l] & GPIO_DAT_I_switch[l];
  5.1742 +		 end
  5.1743 +	    end
  5.1744 +	    
  5.1745 +	 end // if (GPIO_WB_DAT_WIDTH == 32)
  5.1746 +	 
  5.1747 +         assign  IRQ_O = |(EDGE_CAPTURE[DATA_WIDTH-1:0] & IRQ_MASK[DATA_WIDTH-1:0]);
  5.1748 +	 
  5.1749 +      end // if ((IRQ_MODE == 1) && (INPUT_PORTS_ONLY == 1) && (EDGE == 1))
  5.1750 +			   
  5.1751 +      //----------------------------------
  5.1752 +      //--BOTH_INPUT_AND_OUTPUT MODE IRQ
  5.1753 +      //----------------------------------
  5.1754 +      else if  ((IRQ_MODE == 1) && (BOTH_INPUT_AND_OUTPUT == 1) && (LEVEL == 1)) begin
  5.1755  
  5.1756 -     //----------------------------------
  5.1757 -     //--BOTH_INPUT_AND_OUTPUT MODE IRQ
  5.1758 -     //----------------------------------
  5.1759 -     end else if  (IRQ_MODE == 1 && BOTH_INPUT_AND_OUTPUT == 1 && LEVEL == 1) begin
  5.1760 -         always @(posedge CLK_I or posedge RST_I)
  5.1761 -            if (RST_I)
  5.1762 -              IRQ_TEMP_BOTH <= #UDLY 0;
  5.1763 -            else if (IRQ_MASK_WR_EN)
  5.1764 -              IRQ_TEMP_BOTH <= #UDLY IRQ_TEMP_BOTH & GPIO_DAT_I[INPUT_WIDTH-1:0];   
  5.1765 -            else 
  5.1766 -              IRQ_TEMP_BOTH <= #UDLY PIO_BOTH_IN & IRQ_MASK_BOTH;   
  5.1767 -         assign   IRQ_O = |IRQ_TEMP_BOTH;
  5.1768 -
  5.1769 -     //edge mode IRQ
  5.1770 -     end else if  (IRQ_MODE == 1 && BOTH_INPUT_AND_OUTPUT == 1 && EDGE == 1) begin   
  5.1771 +	 if (GPIO_WB_DAT_WIDTH == 8) begin
  5.1772 +	    
  5.1773 +	    genvar iitb_idx;
  5.1774 +	    for (iitb_idx = 0; (iitb_idx < INPUT_WIDTH) && (iitb_idx < 8); iitb_idx = iitb_idx + 1)
  5.1775 +	      begin
  5.1776 +		 always @(posedge CLK_I or posedge RST_I)
  5.1777 +		   if (RST_I)
  5.1778 +		     IRQ_TEMP_BOTH[iitb_idx] <= #UDLY 0;
  5.1779 +		   else if (IRQ_MASK_WR_EN_0)
  5.1780 +		     IRQ_TEMP_BOTH[iitb_idx] <= #UDLY IRQ_TEMP_BOTH[iitb_idx] & GPIO_DAT_I_switch[iitb_idx];
  5.1781 +		   else
  5.1782 +		     IRQ_TEMP_BOTH[iitb_idx] <= #UDLY PIO_BOTH_IN[iitb_idx] & IRQ_MASK_BOTH[iitb_idx];
  5.1783 +	      end 
  5.1784 +	    if (INPUT_WIDTH > 8) begin
  5.1785 +	       genvar jitb_idx;
  5.1786 +	       for (jitb_idx = 8; (jitb_idx < INPUT_WIDTH) && (jitb_idx < 16); jitb_idx = jitb_idx + 1)
  5.1787 +		 begin
  5.1788 +		    always @(posedge CLK_I or posedge RST_I)
  5.1789 +		      if (RST_I)
  5.1790 +			IRQ_TEMP_BOTH[jitb_idx] <= #UDLY 0;
  5.1791 +		      else if (IRQ_MASK_WR_EN_1)
  5.1792 +			IRQ_TEMP_BOTH[jitb_idx] <= #UDLY IRQ_TEMP_BOTH[jitb_idx] & GPIO_DAT_I_switch[jitb_idx - 8];
  5.1793 +		      else
  5.1794 +			IRQ_TEMP_BOTH[jitb_idx] <= #UDLY PIO_BOTH_IN[jitb_idx] & IRQ_MASK_BOTH[jitb_idx];
  5.1795 +		 end 
  5.1796 +	    end
  5.1797 +	    if (INPUT_WIDTH > 16) begin
  5.1798 +	       genvar kitb_idx;
  5.1799 +	       for (kitb_idx = 16; (kitb_idx < INPUT_WIDTH) && (kitb_idx < 24); kitb_idx = kitb_idx + 1)
  5.1800 +		 begin
  5.1801 +		    always @(posedge CLK_I or posedge RST_I)
  5.1802 +		      if (RST_I)
  5.1803 +			IRQ_TEMP_BOTH[kitb_idx] <= #UDLY 0;
  5.1804 +		      else if (IRQ_MASK_WR_EN_2)
  5.1805 +			IRQ_TEMP_BOTH[kitb_idx] <= #UDLY IRQ_TEMP_BOTH[kitb_idx] & GPIO_DAT_I_switch[kitb_idx - 16];
  5.1806 +		      else
  5.1807 +			IRQ_TEMP_BOTH[kitb_idx] <= #UDLY PIO_BOTH_IN[kitb_idx] & IRQ_MASK_BOTH[kitb_idx];
  5.1808 +		 end 
  5.1809 +	    end
  5.1810 +	    if (INPUT_WIDTH > 24) begin
  5.1811 +	       genvar litb_idx;
  5.1812 +	       for (litb_idx = 24; (litb_idx < INPUT_WIDTH) && (litb_idx < 24); litb_idx = litb_idx + 1)
  5.1813 +		 begin
  5.1814 +		    always @(posedge CLK_I or posedge RST_I)
  5.1815 +		      if (RST_I)
  5.1816 +			IRQ_TEMP_BOTH[litb_idx] <= #UDLY 0;
  5.1817 +		      else if (IRQ_MASK_WR_EN_3)
  5.1818 +			IRQ_TEMP_BOTH[litb_idx] <= #UDLY IRQ_TEMP_BOTH[litb_idx] & GPIO_DAT_I_switch[litb_idx - 24];
  5.1819 +		      else
  5.1820 +			IRQ_TEMP_BOTH[litb_idx] <= #UDLY PIO_BOTH_IN[litb_idx] & IRQ_MASK_BOTH[litb_idx];
  5.1821 +		 end 
  5.1822 +	    end
  5.1823 +	    
  5.1824 +	 end // if (GPIO_WB_DAT_WIDTH == 8)
  5.1825 +	 
  5.1826 +	 else if (GPIO_WB_DAT_WIDTH == 32) begin
  5.1827 +	    
  5.1828 +	    genvar iitb_idx;
  5.1829 +	    for (iitb_idx = 0; (iitb_idx < INPUT_WIDTH) && (iitb_idx < 8); iitb_idx = iitb_idx + 1)
  5.1830 +	      begin
  5.1831 +		 always @(posedge CLK_I or posedge RST_I)
  5.1832 +		   if (RST_I)
  5.1833 +		     IRQ_TEMP_BOTH[iitb_idx] <= #UDLY 0;
  5.1834 +		   else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[0])
  5.1835 +		     IRQ_TEMP_BOTH[iitb_idx] <= #UDLY IRQ_TEMP_BOTH[iitb_idx] & GPIO_DAT_I_switch[iitb_idx];
  5.1836 +		   else
  5.1837 +		     IRQ_TEMP_BOTH[iitb_idx] <= #UDLY PIO_BOTH_IN[iitb_idx] & IRQ_MASK_BOTH[iitb_idx];
  5.1838 +	      end 
  5.1839 +	    if (INPUT_WIDTH > 8) begin
  5.1840 +	       genvar jitb_idx;
  5.1841 +	       for (jitb_idx = 8; (jitb_idx < INPUT_WIDTH) && (jitb_idx < 16); jitb_idx = jitb_idx + 1)
  5.1842 +		 begin
  5.1843 +		    always @(posedge CLK_I or posedge RST_I)
  5.1844 +		      if (RST_I)
  5.1845 +			IRQ_TEMP_BOTH[jitb_idx] <= #UDLY 0;
  5.1846 +		      else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[1])
  5.1847 +			IRQ_TEMP_BOTH[jitb_idx] <= #UDLY IRQ_TEMP_BOTH[jitb_idx] & GPIO_DAT_I_switch[jitb_idx];
  5.1848 +		      else
  5.1849 +			IRQ_TEMP_BOTH[jitb_idx] <= #UDLY PIO_BOTH_IN[jitb_idx] & IRQ_MASK_BOTH[jitb_idx];
  5.1850 +		 end 
  5.1851 +	    end
  5.1852 +	    if (INPUT_WIDTH > 16) begin
  5.1853 +	       genvar kitb_idx;
  5.1854 +	       for (kitb_idx = 16; (kitb_idx < INPUT_WIDTH) && (kitb_idx < 24); kitb_idx = kitb_idx + 1)
  5.1855 +		 begin
  5.1856 +		    always @(posedge CLK_I or posedge RST_I)
  5.1857 +		      if (RST_I)
  5.1858 +			IRQ_TEMP_BOTH[kitb_idx] <= #UDLY 0;
  5.1859 +		      else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[2])
  5.1860 +			IRQ_TEMP_BOTH[kitb_idx] <= #UDLY IRQ_TEMP_BOTH[kitb_idx] & GPIO_DAT_I_switch[kitb_idx];
  5.1861 +		      else
  5.1862 +			IRQ_TEMP_BOTH[kitb_idx] <= #UDLY PIO_BOTH_IN[kitb_idx] & IRQ_MASK_BOTH[kitb_idx];
  5.1863 +		 end 
  5.1864 +	    end
  5.1865 +	    if (INPUT_WIDTH > 24) begin
  5.1866 +	       genvar litb_idx;
  5.1867 +	       for (litb_idx = 24; (litb_idx < INPUT_WIDTH) && (litb_idx < 24); litb_idx = litb_idx + 1)
  5.1868 +		 begin
  5.1869 +		    always @(posedge CLK_I or posedge RST_I)
  5.1870 +		      if (RST_I)
  5.1871 +			IRQ_TEMP_BOTH[litb_idx] <= #UDLY 0;
  5.1872 +		      else if (IRQ_MASK_WR_EN && GPIO_SEL_I_switch[3])
  5.1873 +			IRQ_TEMP_BOTH[litb_idx] <= #UDLY IRQ_TEMP_BOTH[litb_idx] & GPIO_DAT_I_switch[litb_idx];
  5.1874 +		      else
  5.1875 +			IRQ_TEMP_BOTH[litb_idx] <= #UDLY PIO_BOTH_IN[litb_idx] & IRQ_MASK_BOTH[litb_idx];
  5.1876 +		 end 
  5.1877 +	    end
  5.1878 +	    
  5.1879 +	 end // if (GPIO_WB_DAT_WIDTH == 32)
  5.1880 +	 
  5.1881 +	 assign IRQ_O = |IRQ_TEMP_BOTH;
  5.1882 +	 
  5.1883 +      end // if ((IRQ_MODE == 1) && (BOTH_INPUT_AND_OUTPUT == 1) && (LEVEL == 1))
  5.1884 +      
  5.1885 +      // edge mode IRQ
  5.1886 +      else if ((IRQ_MODE == 1) && (BOTH_INPUT_AND_OUTPUT == 1) && (EDGE == 1)) begin
  5.1887 +	 
  5.1888           always @(posedge CLK_I or posedge RST_I)
  5.1889             if (RST_I)
  5.1890               PIO_DATA_DLY_BOTH <= #UDLY 0;
  5.1891             else
  5.1892               PIO_DATA_DLY_BOTH <= PIO_BOTH_IN;
  5.1893 -
  5.1894 +	 
  5.1895           // edge-capture register bits are treated as individual bits.
  5.1896 -         genvar i_both;
  5.1897 -         for( i_both = 0; i_both < INPUT_WIDTH; i_both = i_both + 1)
  5.1898 -         begin
  5.1899 -         always @(posedge CLK_I or posedge RST_I)
  5.1900 -           if (RST_I)
  5.1901 -             EDGE_CAPTURE_BOTH[i_both] <= #UDLY 0;
  5.1902 -           else if (|(PIO_BOTH_IN[i_both] & ~PIO_DATA_DLY_BOTH[i_both]) && POSE_EDGE_IRQ == 1)
  5.1903 -             EDGE_CAPTURE_BOTH[i_both] <= #UDLY PIO_BOTH_IN[i_both] & ~PIO_DATA_DLY_BOTH[i_both];
  5.1904 -           else if (|(~PIO_BOTH_IN[i_both] & PIO_DATA_DLY_BOTH[i_both]) &&  NEGE_EDGE_IRQ == 1)
  5.1905 -             EDGE_CAPTURE_BOTH[i_both] <= #UDLY ~PIO_BOTH_IN[i_both] & PIO_DATA_DLY_BOTH[i_both];
  5.1906 -           else if (|(PIO_BOTH_IN[i_both] & ~PIO_DATA_DLY_BOTH[i_both]) && EITHER_EDGE_IRQ == 1)
  5.1907 -             EDGE_CAPTURE_BOTH[i_both] <= #UDLY PIO_BOTH_IN[i_both] & ~PIO_DATA_DLY_BOTH[i_both];
  5.1908 -           else if (|(~PIO_BOTH_IN[i_both] & PIO_DATA_DLY_BOTH[i_both]) && EITHER_EDGE_IRQ == 1)
  5.1909 -             EDGE_CAPTURE_BOTH[i_both] <= #UDLY ~PIO_BOTH_IN[i_both] & PIO_DATA_DLY_BOTH[i_both];
  5.1910 -           else if ( (~IRQ_MASK_BOTH[i_both]) & GPIO_DAT_I[i_both] & IRQ_MASK_WR_EN )
  5.1911 -             // interrupt mask is being set, so clear edge-capture
  5.1912 -             EDGE_CAPTURE_BOTH[i_both] <= #UDLY 0;
  5.1913 -           else if (EDGE_CAP_WR_EN)
  5.1914 -             // user's writing to the edge register, so update edge capture
  5.1915 -             // register
  5.1916 -             EDGE_CAPTURE_BOTH[i_both] <= #UDLY EDGE_CAPTURE_BOTH[i_both] & GPIO_DAT_I[i_both];
  5.1917 -         end
  5.1918 +	 if (GPIO_WB_DAT_WIDTH == 8) begin
  5.1919 +	    
  5.1920 +	    genvar i_both;
  5.1921 +	    for (i_both = 0; (i_both < INPUT_WIDTH) && (i_both < 8); i_both = i_both + 1)
  5.1922 +	      begin
  5.1923 +		 always @(posedge CLK_I or posedge RST_I)
  5.1924 +		   if (RST_I)
  5.1925 +		     EDGE_CAPTURE_BOTH[i_both] <= #UDLY 0;
  5.1926 +		   else if (|(PIO_BOTH_IN[i_both] & ~PIO_DATA_DLY_BOTH[i_both]) && POSE_EDGE_IRQ == 1)
  5.1927 +		     EDGE_CAPTURE_BOTH[i_both] <= #UDLY PIO_BOTH_IN[i_both] & ~PIO_DATA_DLY_BOTH[i_both];
  5.1928 +		   else if (|(~PIO_BOTH_IN[i_both] & PIO_DATA_DLY_BOTH[i_both]) &&  NEGE_EDGE_IRQ == 1)
  5.1929 +		     EDGE_CAPTURE_BOTH[i_both] <= #UDLY ~PIO_BOTH_IN[i_both] & PIO_DATA_DLY_BOTH[i_both];
  5.1930 +		   else if (|(PIO_BOTH_IN[i_both] & ~PIO_DATA_DLY_BOTH[i_both]) && EITHER_EDGE_IRQ == 1)
  5.1931 +		     EDGE_CAPTURE_BOTH[i_both] <= #UDLY PIO_BOTH_IN[i_both] & ~PIO_DATA_DLY_BOTH[i_both];
  5.1932 +		   else if (|(~PIO_BOTH_IN[i_both] & PIO_DATA_DLY_BOTH[i_both]) && EITHER_EDGE_IRQ == 1)
  5.1933 +		     EDGE_CAPTURE_BOTH[i_both] <= #UDLY ~PIO_BOTH_IN[i_both] & PIO_DATA_DLY_BOTH[i_both];
  5.1934 +		   else if ( (~IRQ_MASK_BOTH[i_both]) & GPIO_DAT_I_switch[i_both] & IRQ_MASK_WR_EN_0 )
  5.1935 +		     // interrupt mask is being set, so clear edge-capture
  5.1936 +		     EDGE_CAPTURE_BOTH[i_both] <= #UDLY 0;
  5.1937 +		   else if (EDGE_CAP_WR_EN_0)
  5.1938 +		     // user's writing to the edge register, so update edge capture
  5.1939 +		     // register
  5.1940 +		     EDGE_CAPTURE_BOTH[i_both] <= #UDLY EDGE_CAPTURE_BOTH[i_both] & GPIO_DAT_I_switch[i_both];
  5.1941 +	      end
  5.1942 +	    if (INPUT_WIDTH > 8) begin
  5.1943 +	       genvar j_both;
  5.1944 +	       for (j_both = 8; (j_both < INPUT_WIDTH) && (j_both < 16); j_both = j_both + 1)
  5.1945 +		 begin
  5.1946 +		    always @(posedge CLK_I or posedge RST_I)
  5.1947 +		      if (RST_I)
  5.1948 +			EDGE_CAPTURE_BOTH[j_both] <= #UDLY 0;
  5.1949 +		      else if (|(PIO_BOTH_IN[j_both] & ~PIO_DATA_DLY_BOTH[j_both]) && POSE_EDGE_IRQ == 1)
  5.1950 +			EDGE_CAPTURE_BOTH[j_both] <= #UDLY PIO_BOTH_IN[j_both] & ~PIO_DATA_DLY_BOTH[j_both];
  5.1951 +		      else if (|(~PIO_BOTH_IN[j_both] & PIO_DATA_DLY_BOTH[j_both]) &&  NEGE_EDGE_IRQ == 1)
  5.1952 +			EDGE_CAPTURE_BOTH[j_both] <= #UDLY ~PIO_BOTH_IN[j_both] & PIO_DATA_DLY_BOTH[j_both];
  5.1953 +		      else if (|(PIO_BOTH_IN[j_both] & ~PIO_DATA_DLY_BOTH[j_both]) && EITHER_EDGE_IRQ == 1)
  5.1954 +			EDGE_CAPTURE_BOTH[j_both] <= #UDLY PIO_BOTH_IN[j_both] & ~PIO_DATA_DLY_BOTH[j_both];
  5.1955 +		      else if (|(~PIO_BOTH_IN[j_both] & PIO_DATA_DLY_BOTH[j_both]) && EITHER_EDGE_IRQ == 1)
  5.1956 +			EDGE_CAPTURE_BOTH[j_both] <= #UDLY ~PIO_BOTH_IN[j_both] & PIO_DATA_DLY_BOTH[j_both];
  5.1957 +		      else if ( (~IRQ_MASK_BOTH[j_both]) & GPIO_DAT_I_switch[j_both-8] & IRQ_MASK_WR_EN_1 )
  5.1958 +			// interrupt mask is being set, so clear edge-capture
  5.1959 +			EDGE_CAPTURE_BOTH[j_both] <= #UDLY 0;
  5.1960 +		      else if (EDGE_CAP_WR_EN_1)
  5.1961 +			// user's writing to the edge register, so update edge capture
  5.1962 +			// register
  5.1963 +			EDGE_CAPTURE_BOTH[j_both] <= #UDLY EDGE_CAPTURE_BOTH[j_both] & GPIO_DAT_I_switch[j_both-8];
  5.1964 +		 end
  5.1965 +	    end
  5.1966 +	    if (INPUT_WIDTH > 16) begin
  5.1967 +	       genvar k_both;
  5.1968 +	       for (k_both = 16; (k_both < INPUT_WIDTH) && (k_both < 24); k_both = k_both + 1)
  5.1969 +		 begin
  5.1970 +		    always @(posedge CLK_I or posedge RST_I)
  5.1971 +		      if (RST_I)
  5.1972 +			EDGE_CAPTURE_BOTH[k_both] <= #UDLY 0;
  5.1973 +		      else if (|(PIO_BOTH_IN[k_both] & ~PIO_DATA_DLY_BOTH[k_both]) && POSE_EDGE_IRQ == 1)
  5.1974 +			EDGE_CAPTURE_BOTH[k_both] <= #UDLY PIO_BOTH_IN[k_both] & ~PIO_DATA_DLY_BOTH[k_both];
  5.1975 +		      else if (|(~PIO_BOTH_IN[k_both] & PIO_DATA_DLY_BOTH[k_both]) &&  NEGE_EDGE_IRQ == 1)
  5.1976 +			EDGE_CAPTURE_BOTH[k_both] <= #UDLY ~PIO_BOTH_IN[k_both] & PIO_DATA_DLY_BOTH[k_both];
  5.1977 +		      else if (|(PIO_BOTH_IN[k_both] & ~PIO_DATA_DLY_BOTH[k_both]) && EITHER_EDGE_IRQ == 1)
  5.1978 +			EDGE_CAPTURE_BOTH[k_both] <= #UDLY PIO_BOTH_IN[k_both] & ~PIO_DATA_DLY_BOTH[k_both];
  5.1979 +		      else if (|(~PIO_BOTH_IN[k_both] & PIO_DATA_DLY_BOTH[k_both]) && EITHER_EDGE_IRQ == 1)
  5.1980 +			EDGE_CAPTURE_BOTH[k_both] <= #UDLY ~PIO_BOTH_IN[k_both] & PIO_DATA_DLY_BOTH[k_both];
  5.1981 +		      else if ( (~IRQ_MASK_BOTH[k_both]) & GPIO_DAT_I_switch[k_both-16] & IRQ_MASK_WR_EN_2 )
  5.1982 +			// interrupt mask is being set, so clear edge-capture
  5.1983 +			EDGE_CAPTURE_BOTH[k_both] <= #UDLY 0;
  5.1984 +		      else if (EDGE_CAP_WR_EN_2)
  5.1985 +			// user's writing to the edge register, so update edge capture
  5.1986 +			// register
  5.1987 +			EDGE_CAPTURE_BOTH[k_both] <= #UDLY EDGE_CAPTURE_BOTH[k_both] & GPIO_DAT_I_switch[k_both-16];
  5.1988 +		 end
  5.1989 +	    end
  5.1990 +	    if (INPUT_WIDTH > 24) begin
  5.1991 +	       genvar l_both;
  5.1992 +	       for (l_both = 24; (l_both < INPUT_WIDTH) && (l_both < 32); l_both = l_both + 1)
  5.1993 +		 begin
  5.1994 +		    always @(posedge CLK_I or posedge RST_I)
  5.1995 +		      if (RST_I)
  5.1996 +			EDGE_CAPTURE_BOTH[l_both] <= #UDLY 0;
  5.1997 +		      else if (|(PIO_BOTH_IN[l_both] & ~PIO_DATA_DLY_BOTH[l_both]) && POSE_EDGE_IRQ == 1)
  5.1998 +			EDGE_CAPTURE_BOTH[l_both] <= #UDLY PIO_BOTH_IN[l_both] & ~PIO_DATA_DLY_BOTH[l_both];
  5.1999 +		      else if (|(~PIO_BOTH_IN[l_both] & PIO_DATA_DLY_BOTH[l_both]) &&  NEGE_EDGE_IRQ == 1)
  5.2000 +			EDGE_CAPTURE_BOTH[l_both] <= #UDLY ~PIO_BOTH_IN[l_both] & PIO_DATA_DLY_BOTH[l_both];
  5.2001 +		      else if (|(PIO_BOTH_IN[l_both] & ~PIO_DATA_DLY_BOTH[l_both]) && EITHER_EDGE_IRQ == 1)
  5.2002 +			EDGE_CAPTURE_BOTH[l_both] <= #UDLY PIO_BOTH_IN[l_both] & ~PIO_DATA_DLY_BOTH[l_both];
  5.2003 +		      else if (|(~PIO_BOTH_IN[l_both] & PIO_DATA_DLY_BOTH[l_both]) && EITHER_EDGE_IRQ == 1)
  5.2004 +			EDGE_CAPTURE_BOTH[l_both] <= #UDLY ~PIO_BOTH_IN[l_both] & PIO_DATA_DLY_BOTH[l_both];
  5.2005 +		      else if ( (~IRQ_MASK_BOTH[l_both]) & GPIO_DAT_I_switch[l_both-24] & IRQ_MASK_WR_EN_3 )
  5.2006 +			// interrupt mask is being set, so clear edge-capture
  5.2007 +			EDGE_CAPTURE_BOTH[l_both] <= #UDLY 0;
  5.2008 +		      else if (EDGE_CAP_WR_EN_3)
  5.2009 +			// user's writing to the edge register, so update edge capture
  5.2010 +			// register
  5.2011 +			EDGE_CAPTURE_BOTH[l_both] <= #UDLY EDGE_CAPTURE_BOTH[l_both] & GPIO_DAT_I_switch[l_both-24];
  5.2012 +		 end
  5.2013 +	    end
  5.2014 +	    
  5.2015 +	 end // if (GPIO_WB_DAT_WIDTH == 8)
  5.2016 +	 else if (GPIO_WB_DAT_WIDTH == 32) begin
  5.2017 +	    
  5.2018 +	    genvar i_both;
  5.2019 +	    for (i_both = 0; (i_both < INPUT_WIDTH) && (i_both < 8); i_both = i_both + 1)
  5.2020 +	      begin
  5.2021 +		 always @(posedge CLK_I or posedge RST_I)
  5.2022 +		   if (RST_I)
  5.2023 +		     EDGE_CAPTURE_BOTH[i_both] <= #UDLY 0;
  5.2024 +		   else if (|(PIO_BOTH_IN[i_both] & ~PIO_DATA_DLY_BOTH[i_both]) && POSE_EDGE_IRQ == 1)
  5.2025 +		     EDGE_CAPTURE_BOTH[i_both] <= #UDLY PIO_BOTH_IN[i_both] & ~PIO_DATA_DLY_BOTH[i_both];
  5.2026 +		   else if (|(~PIO_BOTH_IN[i_both] & PIO_DATA_DLY_BOTH[i_both]) &&  NEGE_EDGE_IRQ == 1)
  5.2027 +		     EDGE_CAPTURE_BOTH[i_both] <= #UDLY ~PIO_BOTH_IN[i_both] & PIO_DATA_DLY_BOTH[i_both];
  5.2028 +		   else if (|(PIO_BOTH_IN[i_both] & ~PIO_DATA_DLY_BOTH[i_both]) && EITHER_EDGE_IRQ == 1)
  5.2029 +		     EDGE_CAPTURE_BOTH[i_both] <= #UDLY PIO_BOTH_IN[i_both] & ~PIO_DATA_DLY_BOTH[i_both];
  5.2030 +		   else if (|(~PIO_BOTH_IN[i_both] & PIO_DATA_DLY_BOTH[i_both]) && EITHER_EDGE_IRQ == 1)
  5.2031 +		     EDGE_CAPTURE_BOTH[i_both] <= #UDLY ~PIO_BOTH_IN[i_both] & PIO_DATA_DLY_BOTH[i_both];
  5.2032 +		   else if ( (~IRQ_MASK_BOTH[i_both]) & GPIO_DAT_I_switch[i_both] & IRQ_MASK_WR_EN && GPIO_SEL_I_switch[0])
  5.2033 +		     // interrupt mask is being set, so clear edge-capture
  5.2034 +		     EDGE_CAPTURE_BOTH[i_both] <= #UDLY 0;
  5.2035 +		   else if (EDGE_CAP_WR_EN && GPIO_SEL_I_switch[0])
  5.2036 +		     // user's writing to the edge register, so update edge capture
  5.2037 +		     // register
  5.2038 +		     EDGE_CAPTURE_BOTH[i_both] <= #UDLY EDGE_CAPTURE_BOTH[i_both] & GPIO_DAT_I_switch[i_both];
  5.2039 +	      end
  5.2040 +	    if (INPUT_WIDTH > 8) begin
  5.2041 +	       genvar j_both;
  5.2042 +	       for (j_both = 8; (j_both < INPUT_WIDTH) && (j_both < 16); j_both = j_both + 1)
  5.2043 +		 begin
  5.2044 +		    always @(posedge CLK_I or posedge RST_I)
  5.2045 +		      if (RST_I)
  5.2046 +			EDGE_CAPTURE_BOTH[j_both] <= #UDLY 0;
  5.2047 +		      else if (|(PIO_BOTH_IN[j_both] & ~PIO_DATA_DLY_BOTH[j_both]) && POSE_EDGE_IRQ == 1)
  5.2048 +			EDGE_CAPTURE_BOTH[j_both] <= #UDLY PIO_BOTH_IN[j_both] & ~PIO_DATA_DLY_BOTH[j_both];
  5.2049 +		      else if (|(~PIO_BOTH_IN[j_both] & PIO_DATA_DLY_BOTH[j_both]) &&  NEGE_EDGE_IRQ == 1)
  5.2050 +			EDGE_CAPTURE_BOTH[j_both] <= #UDLY ~PIO_BOTH_IN[j_both] & PIO_DATA_DLY_BOTH[j_both];
  5.2051 +		      else if (|(PIO_BOTH_IN[j_both] & ~PIO_DATA_DLY_BOTH[j_both]) && EITHER_EDGE_IRQ == 1)
  5.2052 +			EDGE_CAPTURE_BOTH[j_both] <= #UDLY PIO_BOTH_IN[j_both] & ~PIO_DATA_DLY_BOTH[j_both];
  5.2053 +		      else if (|(~PIO_BOTH_IN[j_both] & PIO_DATA_DLY_BOTH[j_both]) && EITHER_EDGE_IRQ == 1)
  5.2054 +			EDGE_CAPTURE_BOTH[j_both] <= #UDLY ~PIO_BOTH_IN[j_both] & PIO_DATA_DLY_BOTH[j_both];
  5.2055 +		      else if ( (~IRQ_MASK_BOTH[j_both]) & GPIO_DAT_I_switch[j_both-8] & IRQ_MASK_WR_EN && GPIO_SEL_I_switch[1])
  5.2056 +			// interrupt mask is being set, so clear edge-capture
  5.2057 +			EDGE_CAPTURE_BOTH[j_both] <= #UDLY 0;
  5.2058 +		      else if (EDGE_CAP_WR_EN && GPIO_SEL_I_switch[1])
  5.2059 +			// user's writing to the edge register, so update edge capture
  5.2060 +			// register
  5.2061 +			EDGE_CAPTURE_BOTH[j_both] <= #UDLY EDGE_CAPTURE_BOTH[j_both] & GPIO_DAT_I_switch[j_both];
  5.2062 +		 end
  5.2063 +	    end
  5.2064 +	    if (INPUT_WIDTH > 16) begin
  5.2065 +	       genvar k_both;
  5.2066 +	       for (k_both = 16; (k_both < INPUT_WIDTH) && (k_both < 24); k_both = k_both + 1)
  5.2067 +		 begin
  5.2068 +		    always @(posedge CLK_I or posedge RST_I)
  5.2069 +		      if (RST_I)
  5.2070 +			EDGE_CAPTURE_BOTH[k_both] <= #UDLY 0;
  5.2071 +		      else if (|(PIO_BOTH_IN[k_both] & ~PIO_DATA_DLY_BOTH[k_both]) && POSE_EDGE_IRQ == 1)
  5.2072 +			EDGE_CAPTURE_BOTH[k_both] <= #UDLY PIO_BOTH_IN[k_both] & ~PIO_DATA_DLY_BOTH[k_both];
  5.2073 +		      else if (|(~PIO_BOTH_IN[k_both] & PIO_DATA_DLY_BOTH[k_both]) &&  NEGE_EDGE_IRQ == 1)
  5.2074 +			EDGE_CAPTURE_BOTH[k_both] <= #UDLY ~PIO_BOTH_IN[k_both] & PIO_DATA_DLY_BOTH[k_both];
  5.2075 +		      else if (|(PIO_BOTH_IN[k_both] & ~PIO_DATA_DLY_BOTH[k_both]) && EITHER_EDGE_IRQ == 1)
  5.2076 +			EDGE_CAPTURE_BOTH[k_both] <= #UDLY PIO_BOTH_IN[k_both] & ~PIO_DATA_DLY_BOTH[k_both];
  5.2077 +		      else if (|(~PIO_BOTH_IN[k_both] & PIO_DATA_DLY_BOTH[k_both]) && EITHER_EDGE_IRQ == 1)
  5.2078 +			EDGE_CAPTURE_BOTH[k_both] <= #UDLY ~PIO_BOTH_IN[k_both] & PIO_DATA_DLY_BOTH[k_both];
  5.2079 +		      else if ( (~IRQ_MASK_BOTH[k_both]) & GPIO_DAT_I_switch[k_both-16] & IRQ_MASK_WR_EN && GPIO_SEL_I_switch[2])
  5.2080 +			// interrupt mask is being set, so clear edge-capture
  5.2081 +			EDGE_CAPTURE_BOTH[k_both] <= #UDLY 0;
  5.2082 +		      else if (EDGE_CAP_WR_EN && GPIO_SEL_I_switch[2])
  5.2083 +			// user's writing to the edge register, so update edge capture
  5.2084 +			// register
  5.2085 +			EDGE_CAPTURE_BOTH[k_both] <= #UDLY EDGE_CAPTURE_BOTH[k_both] & GPIO_DAT_I_switch[k_both];
  5.2086 +		 end
  5.2087 +	    end
  5.2088 +	    if (INPUT_WIDTH > 24) begin
  5.2089 +	       genvar l_both;
  5.2090 +	       for (l_both = 24; (l_both < INPUT_WIDTH) && (l_both < 32); l_both = l_both + 1)
  5.2091 +		 begin
  5.2092 +		    always @(posedge CLK_I or posedge RST_I)
  5.2093 +		      if (RST_I)
  5.2094 +			EDGE_CAPTURE_BOTH[l_both] <= #UDLY 0;
  5.2095 +		      else if (|(PIO_BOTH_IN[l_both] & ~PIO_DATA_DLY_BOTH[l_both]) && POSE_EDGE_IRQ == 1)
  5.2096 +			EDGE_CAPTURE_BOTH[l_both] <= #UDLY PIO_BOTH_IN[l_both] & ~PIO_DATA_DLY_BOTH[l_both];
  5.2097 +		      else if (|(~PIO_BOTH_IN[l_both] & PIO_DATA_DLY_BOTH[l_both]) &&  NEGE_EDGE_IRQ == 1)
  5.2098 +			EDGE_CAPTURE_BOTH[l_both] <= #UDLY ~PIO_BOTH_IN[l_both] & PIO_DATA_DLY_BOTH[l_both];
  5.2099 +		      else if (|(PIO_BOTH_IN[l_both] & ~PIO_DATA_DLY_BOTH[l_both]) && EITHER_EDGE_IRQ == 1)
  5.2100 +			EDGE_CAPTURE_BOTH[l_both] <= #UDLY PIO_BOTH_IN[l_both] & ~PIO_DATA_DLY_BOTH[l_both];
  5.2101 +		      else if (|(~PIO_BOTH_IN[l_both] & PIO_DATA_DLY_BOTH[l_both]) && EITHER_EDGE_IRQ == 1)
  5.2102 +			EDGE_CAPTURE_BOTH[l_both] <= #UDLY ~PIO_BOTH_IN[l_both] & PIO_DATA_DLY_BOTH[l_both];
  5.2103 +		      else if ( (~IRQ_MASK_BOTH[l_both]) & GPIO_DAT_I_switch[l_both-24] & IRQ_MASK_WR_EN && GPIO_SEL_I_switch[3])
  5.2104 +			// interrupt mask is being set, so clear edge-capture
  5.2105 +			EDGE_CAPTURE_BOTH[l_both] <= #UDLY 0;
  5.2106 +		      else if (EDGE_CAP_WR_EN && GPIO_SEL_I_switch[3])
  5.2107 +			// user's writing to the edge register, so update edge capture
  5.2108 +			// register
  5.2109 +			EDGE_CAPTURE_BOTH[l_both] <= #UDLY EDGE_CAPTURE_BOTH[l_both] & GPIO_DAT_I_switch[l_both];
  5.2110 +		 end
  5.2111 +	    end
  5.2112 +	    
  5.2113 +	 end // if (GPIO_WB_DAT_WIDTH == 32)
  5.2114 +	 
  5.2115           assign   IRQ_O = |(EDGE_CAPTURE_BOTH & IRQ_MASK_BOTH);
  5.2116  
  5.2117 -     end else if (IRQ_MODE == 1 && TRISTATE_PORTS == 1) begin
  5.2118 +      end // if ((IRQ_MODE == 1) && (BOTH_INPUT_AND_OUTPUT == 1) && (EDGE == 1))
  5.2119 +      
  5.2120 +      else if (IRQ_MODE == 1 && TRISTATE_PORTS == 1) begin
  5.2121 +	 
  5.2122           assign  IRQ_O = |IRQ_TRI_TEMP; 
  5.2123 -     end else
  5.2124 +      end
  5.2125 +      
  5.2126 +      else begin
  5.2127 +	 
  5.2128           assign  IRQ_O = 1'b0;
  5.2129 -   endgenerate   
  5.2130 +      end
  5.2131 +      
  5.2132 +   endgenerate
  5.2133 +   
  5.2134  
  5.2135  endmodule
  5.2136  `endif // GPIO_V

     6.1 --- a/rtl/verilog/tpio.v	Fri Aug 13 10:41:29 2010 +0100
     6.2 +++ b/rtl/verilog/tpio.v	Sat Aug 06 01:43:24 2011 +0100
     6.3 @@ -1,18 +1,39 @@
     6.4 -// =============================================================================
     6.5 -//                           COPYRIGHT NOTICE
     6.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation
     6.7 -// ALL RIGHTS RESERVED
     6.8 -// This confidential and proprietary software may be used only as authorised by
     6.9 -// a licensing agreement from Lattice Semiconductor Corporation.
    6.10 -// The entire notice above must be reproduced on all authorized copies and
    6.11 -// copies may only be made to the extent permitted by a licensing agreement from
    6.12 -// Lattice Semiconductor Corporation.
    6.13 +//   ==================================================================
    6.14 +//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
    6.15 +//   ------------------------------------------------------------------
    6.16 +//   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
    6.17 +//   ALL RIGHTS RESERVED 
    6.18 +//   ------------------------------------------------------------------
    6.19 +//
    6.20 +//   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
    6.21 +//
    6.22 +//   Permission:
    6.23 +//
    6.24 +//      Lattice Semiconductor grants permission to use this code
    6.25 +//      pursuant to the terms of the Lattice Semiconductor Corporation
    6.26 +//      Open Source License Agreement.  
    6.27 +//
    6.28 +//   Disclaimer:
    6.29  //
    6.30 -// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
    6.31 -// 5555 NE Moore Court                            408-826-6000 (other locations)
    6.32 -// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
    6.33 -// U.S.A                                   email: techsupport@latticesemi.com
    6.34 -// ============================================================================/
    6.35 +//      Lattice Semiconductor provides no warranty regarding the use or
    6.36 +//      functionality of this code. It is the user's responsibility to
    6.37 +//      verify the user’s design for consistency and functionality through
    6.38 +//      the use of formal verification methods.
    6.39 +//
    6.40 +//   --------------------------------------------------------------------
    6.41 +//
    6.42 +//                  Lattice Semiconductor Corporation
    6.43 +//                  5555 NE Moore Court
    6.44 +//                  Hillsboro, OR 97214
    6.45 +//                  U.S.A
    6.46 +//
    6.47 +//                  TEL: 1-800-Lattice (USA and Canada)
    6.48 +//                         503-286-8001 (other locations)
    6.49 +//
    6.50 +//                  web: http://www.latticesemi.com/
    6.51 +//                  email: techsupport@latticesemi.com
    6.52 +//
    6.53 +//   --------------------------------------------------------------------
    6.54  //                         FILE DETAILS
    6.55  //                         FILE DETAILS
    6.56  // Project          : GPIO for LM32