Sat, 06 Aug 2011 01:40:34 +0100
Update comments per latest Lattice code dump (LM32 v3.8)
1 // ==================================================================
2 // >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
3 // ------------------------------------------------------------------
4 // Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
5 // ALL RIGHTS RESERVED
6 // ------------------------------------------------------------------
7 //
8 // IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
9 //
10 // Permission:
11 //
12 // Lattice Semiconductor grants permission to use this code
13 // pursuant to the terms of the Lattice Semiconductor Corporation
14 // Open Source License Agreement.
15 //
16 // Disclaimer:
17 //
18 // Lattice Semiconductor provides no warranty regarding the use or
19 // functionality of this code. It is the user's responsibility to
20 // verify the user’s design for consistency and functionality through
21 // the use of formal verification methods.
22 //
23 // --------------------------------------------------------------------
24 //
25 // Lattice Semiconductor Corporation
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29 //
30 // TEL: 1-800-Lattice (USA and Canada)
31 // 503-286-8001 (other locations)
32 //
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35 //
36 // --------------------------------------------------------------------
37 // FILE DETAILS
38 // Project : LM32 Timer
39 // File : timer.v
40 // Title : Timer component core file
41 // Dependencies : None
42 // Version : 7.0
43 // : Initial Release
44 // Version : 7.0SP2, 3.0
45 // : No Change
46 // =============================================================================
47 `ifndef TIMER_FILE
48 `define TIMER_FILE
49 module timer #(
50 parameter PERIOD_NUM = 20,//decimal
51 parameter PERIOD_WIDTH = 16,//decimal
52 parameter WRITEABLE_PERIOD = 1,
53 parameter READABLE_SNAPSHOT = 1,
54 parameter START_STOP_CONTROL = 1,
55 parameter TIMEOUT_PULSE = 1,
56 parameter WATCHDOG = 0)
57 (
58 //slave port
59 S_ADR_I, //32bits
60 S_DAT_I, //32bits
61 S_WE_I,
62 S_STB_I,
63 S_CYC_I,
64 S_CTI_I,
65 S_BTE_I,
66 S_LOCK_I,
67 S_SEL_I,
68 S_DAT_O, //32bits
69 S_ACK_O,
70 S_RTY_O,
71 S_ERR_O,
72 S_INT_O,
73 RSTREQ_O, //resetrequest, only used when WatchDog enabled
74 TOPULSE_O, //timeoutpulse, only used when TimeOutPulse enabled
75 //system clock and reset
76 CLK_I,
77 RST_I
78 );
80 input [31:0] S_ADR_I;
81 input [31:0] S_DAT_I;
82 input S_WE_I;
83 input S_STB_I;
84 input S_CYC_I;
85 input [2:0] S_CTI_I;
86 input S_LOCK_I;
87 input [3:0] S_SEL_I;
88 input [1:0] S_BTE_I;
89 output [31:0] S_DAT_O;
90 output S_ACK_O;
91 output S_INT_O;
92 output S_RTY_O;
93 output S_ERR_O;
94 output RSTREQ_O;
95 output TOPULSE_O;
97 input CLK_I;
98 input RST_I;
100 parameter UDLY = 1;
101 parameter ST_IDLE = 2'b00;
102 parameter ST_CNT = 2'b01;
103 parameter ST_STOP = 2'b10;
105 reg dw00_cs;
106 reg dw04_cs;
107 reg dw08_cs;
108 reg dw0c_cs;
109 reg reg_wr;
110 reg reg_rd;
111 reg [31:0] latch_s_data;
112 reg [1:0] reg_04_data;
113 reg reg_run;
114 reg reg_stop;
115 reg reg_start;
116 reg [1:0] status;
117 reg [PERIOD_WIDTH-1:0] internal_counter;
118 reg [PERIOD_WIDTH-1:0] reg_08_data;
119 reg s_ack_dly;
120 reg s_ack_2dly;
121 reg s_ack_pre;
122 reg RSTREQ_O;
123 reg TOPULSE_O;
124 reg reg_to;
126 wire reg_cont;
127 wire reg_ito;
128 wire [1:0] read_00_data;
129 wire [1:0] read_04_data;
130 wire [PERIOD_WIDTH-1:0] read_08_data;
131 wire [PERIOD_WIDTH-1:0] read_0c_data;
132 wire [PERIOD_WIDTH-1:0] reg_period;
133 wire S_ACK_O;
134 wire [31:0] S_DAT_O;
135 wire S_INT_O;
137 assign S_RTY_O = 1'b0;
138 assign S_ERR_O = 1'b0;
140 always @(posedge CLK_I or posedge RST_I)
141 if(RST_I)
142 latch_s_data <= #UDLY 32'h0;
143 else
144 latch_s_data <= #UDLY S_DAT_I;
146 always @(posedge CLK_I or posedge RST_I)
147 if(RST_I)
148 begin
149 dw00_cs <= #UDLY 1'b0;
150 dw04_cs <= #UDLY 1'b0;
151 dw08_cs <= #UDLY 1'b0;
152 dw0c_cs <= #UDLY 1'b0;
153 end
154 else
155 begin
156 dw00_cs <= #UDLY (!(|S_ADR_I[5:2]));
157 dw04_cs <= #UDLY (S_ADR_I[5:2] == 4'h1);
158 dw08_cs <= #UDLY (S_ADR_I[5:2] == 4'h2);
159 dw0c_cs <= #UDLY (S_ADR_I[5:2] == 4'h3);
160 end
162 always @(posedge CLK_I or posedge RST_I)
163 if(RST_I)
164 begin
165 reg_wr <= #UDLY 1'b0;
166 reg_rd <= #UDLY 1'b0;
167 end
168 else
169 begin
170 reg_wr <= #UDLY S_WE_I && S_STB_I && S_CYC_I;
171 reg_rd <= #UDLY !S_WE_I && S_STB_I && S_CYC_I;
172 end
174 generate
175 if (START_STOP_CONTROL == 1)
177 always @(posedge CLK_I or posedge RST_I)
178 if(RST_I)
179 begin
180 status <= #UDLY ST_IDLE;
181 internal_counter <= #UDLY 'h0;
182 end
183 else
184 case(status)
185 ST_IDLE:
186 begin
187 if(reg_wr && dw08_cs)
188 begin
189 internal_counter <= #UDLY (WRITEABLE_PERIOD == 1) ? latch_s_data : reg_period;
190 end
191 else if(reg_start && !reg_stop)
192 begin
193 status <= #UDLY ST_CNT;
194 if(|reg_period)
195 internal_counter <= #UDLY reg_period - 1;
196 end
197 end
198 ST_CNT:
199 begin
200 if(reg_stop && (|internal_counter))
201 status <= #UDLY ST_STOP;
202 else if(reg_wr && dw08_cs)
203 begin
204 internal_counter <= #UDLY (WRITEABLE_PERIOD == 1) ? latch_s_data : reg_period;
205 if(!(|internal_counter) && !reg_cont)
206 status <= #UDLY ST_IDLE;
207 end
208 else if(!(|internal_counter))
209 begin
210 if(!reg_cont)
211 begin
212 status <= #UDLY ST_IDLE;
213 end
214 internal_counter <= #UDLY reg_period;
215 end
216 else
217 internal_counter <= #UDLY internal_counter - 1;
218 end
219 ST_STOP:
220 begin
221 if(reg_start && !reg_stop)
222 status <= #UDLY ST_CNT;
223 else if(reg_wr && dw08_cs)
224 begin
225 internal_counter <= #UDLY (WRITEABLE_PERIOD == 1) ? latch_s_data : reg_period;
226 end
227 end
228 default:
229 begin
230 status <= #UDLY ST_IDLE;
231 internal_counter <= #UDLY 'h0;
232 end
233 endcase
234 endgenerate
237 generate
238 if (START_STOP_CONTROL == 0)
239 always @(posedge CLK_I or posedge RST_I)
240 if(RST_I)
241 internal_counter <= #UDLY 'h0;
242 else if ((reg_wr && dw08_cs) && (WATCHDOG == 1) || !(|internal_counter))
243 internal_counter <= #UDLY reg_period;
244 else
245 internal_counter <= #UDLY internal_counter - 1;
246 endgenerate
248 always @(posedge CLK_I or posedge RST_I)
249 if(RST_I)
250 reg_to <= #UDLY 1'b0;
251 else if(reg_wr && dw00_cs && (!latch_s_data[0]))
252 reg_to <= #UDLY 1'b0;
253 else if(!(|internal_counter) && reg_ito && ((START_STOP_CONTROL == 0) || reg_run))
254 reg_to <= #UDLY 1'b1;
256 generate
257 if (START_STOP_CONTROL == 1)
258 always @(posedge CLK_I or posedge RST_I)
259 if(RST_I)
260 reg_run <= #UDLY 1'b0;
261 else if(reg_stop)
262 reg_run <= #UDLY 1'b0;
263 else if(reg_start)
264 reg_run <= #UDLY 1'b1;
265 else
266 reg_run <= #UDLY (status !== ST_IDLE);
267 endgenerate
269 assign read_00_data = (START_STOP_CONTROL == 1) ? {reg_run,reg_to} : {1'b1,reg_to};
271 //reg_04:control
272 assign {reg_cont,reg_ito} = reg_04_data;
274 generate
275 if (START_STOP_CONTROL == 1)
276 always @(posedge CLK_I or posedge RST_I)
277 if(RST_I)
278 reg_stop <= #UDLY 1'b0;
279 else if(reg_wr && dw04_cs)
280 begin
281 if(latch_s_data[3] && !latch_s_data[2] && !reg_stop)
282 reg_stop <= #UDLY 1'b1;
283 else if(!latch_s_data[3] && latch_s_data[2] && reg_stop)
284 reg_stop <= #UDLY 1'b0;
285 end
287 always @(posedge CLK_I or posedge RST_I)
288 if(RST_I)
289 reg_start <= #UDLY 1'b0;
290 else if(reg_wr && dw04_cs && !reg_run)
291 reg_start <= #UDLY latch_s_data[2];
292 else
293 reg_start <= #UDLY 1'b0;
294 endgenerate
296 always @(posedge CLK_I or posedge RST_I)
297 if(RST_I)
298 reg_04_data <= #UDLY 2'h0;
299 else if(reg_wr && dw04_cs)
300 reg_04_data <= #UDLY latch_s_data[1:0];
302 assign read_04_data = reg_04_data;
304 generate
305 if (WRITEABLE_PERIOD == 1) begin
306 assign reg_period = reg_08_data;
307 assign read_08_data = reg_08_data;
308 always @(posedge CLK_I or posedge RST_I) begin
309 if (RST_I)
310 reg_08_data <= #UDLY PERIOD_NUM;
311 else if ((reg_wr && dw08_cs) && (START_STOP_CONTROL == 1))
312 reg_08_data <= #UDLY latch_s_data;
313 end
314 end
315 else
316 assign reg_period = PERIOD_NUM;
317 endgenerate
319 generate
320 if (READABLE_SNAPSHOT == 1)
321 assign read_0c_data = internal_counter;
322 endgenerate
324 always @(posedge CLK_I or posedge RST_I)
325 if(RST_I)
326 begin
327 s_ack_pre <= #UDLY 1'b0;
328 s_ack_dly <= #UDLY 1'b0;
329 s_ack_2dly <= #UDLY 1'b0;
330 end
331 else
332 begin
333 s_ack_pre <= #UDLY S_STB_I && S_CYC_I;
334 s_ack_dly <= #UDLY s_ack_pre;
335 s_ack_2dly <= #UDLY s_ack_dly;
336 end
338 assign S_ACK_O = s_ack_dly & !s_ack_2dly;
339 assign S_DAT_O = (dw00_cs & !S_WE_I & S_STB_I) ? read_00_data :
340 (dw04_cs & !S_WE_I & S_STB_I) ? read_04_data :
341 (dw08_cs & !S_WE_I & S_STB_I & WRITEABLE_PERIOD) ? read_08_data :
342 (dw0c_cs & !S_WE_I & S_STB_I & READABLE_SNAPSHOT) ? read_0c_data :
343 32'h0;
344 assign S_INT_O = reg_to;
346 generate
347 if (WATCHDOG == 1)
348 always @(posedge CLK_I or posedge RST_I) begin
349 if(RST_I)
350 RSTREQ_O <= #UDLY 1'b0;
351 else if(!(|internal_counter) && !RSTREQ_O && ((START_STOP_CONTROL == 0) || reg_run))
352 RSTREQ_O <= #UDLY 1'b1;
353 else
354 RSTREQ_O <= #UDLY 1'b0;
355 end
356 endgenerate
359 generate
360 if (TIMEOUT_PULSE == 1)
361 //TOPULSE_O
362 always @(posedge CLK_I or posedge RST_I)
363 if(RST_I)
364 TOPULSE_O <= #UDLY 1'b0;
365 else if(!(|internal_counter) && !TOPULSE_O && ((START_STOP_CONTROL == 0) || reg_run))
366 TOPULSE_O <= #UDLY 1'b1;
367 else
368 TOPULSE_O <= #UDLY 1'b0;
369 endgenerate
371 endmodule
372 `endif