IPCores/wb_sdram / changelog

add basic R/W test

• Tue, 10 Aug 2010 17:36:00 +0100
• by Philip Pemberton <philpem@philpem.me.uk> [Tue, 10 Aug 2010 17:36:00 +0100] rev 4
• add basic R/W test

add refresh timer and refresh FSM logic

• Tue, 10 Aug 2010 14:41:06 +0100
• by Philip Pemberton <philpem@philpem.me.uk> [Tue, 10 Aug 2010 14:41:06 +0100] rev 3
• add refresh timer and refresh FSM logic

implement (almost) complete SDRAM init sequence

• Tue, 10 Aug 2010 13:23:58 +0100
• by Philip Pemberton <philpem@philpem.me.uk> [Tue, 10 Aug 2010 13:23:58 +0100] rev 2
• implement (almost) complete SDRAM init sequence

make spinstate more noticeable on LA, fix CKE init timer

• Tue, 10 Aug 2010 12:58:34 +0100
• by Philip Pemberton <philpem@philpem.me.uk> [Tue, 10 Aug 2010 12:58:34 +0100] rev 1
• make spinstate more noticeable on LA, fix CKE init timer
  
  cke init timer was running 1cy longer than it should have

add clock generator DCM and preliminary homebrew WISHBONE SDRAM controller

• Mon, 09 Aug 2010 20:45:49 +0100
• by Philip Pemberton <philpem@philpem.me.uk> [Mon, 09 Aug 2010 20:45:49 +0100] rev 0
• add clock generator DCM and preliminary homebrew WISHBONE SDRAM controller