Tue, 10 Aug 2010 18:04:05 +0100
make test work like a R/W checkerboard instead (looks better on the LA)
1 /****************************************************************************
2 *
3 *
4 ****************************************************************************/
6 module wb_sdram (
7 // Clocks and resets
8 input wb_clk_i, // WISHBONE clock
9 input wb_rst_i, // WISHBONE reset
11 // WISHBONE bus
12 input [31:0] wb_adr_i, // WISHBONE address
13 input [31:0] wb_dat_i, // WISHBONE data in
14 output reg [31:0] wb_dat_o, // WISHBONE data out
15 input [3:0] wb_sel_i, // WISHBONE byte select
16 input wb_we_i, // WISHBONE write enable (R/#W)
17 input wb_cyc_i, // WISHBONE cycle
18 input wb_stb_i, // WISHBONE strobe
19 output wb_ack_o, // WISHBONE cycle acknowledge (data available, DTACK)
20 output wb_err_o, // WISHBONE bus error
21 output wb_rty_o, // WISHBONE retry-later
23 // SDRAM
24 output reg sdram_cke, // SDRAM clock enable
25 output sdram_cs_n, // SDRAM chip select (active low)
26 output sdram_ras_n, // SDRAM row address strobe (active low)
27 output sdram_cas_n, // SDRAM column address strobe (active low)
28 output sdram_we_n, // SDRAM write enable (active low)
29 output [11:0] sdram_a, // SDRAM address
30 output reg [1:0] sdram_ba, // SDRAM bank address
31 output reg [3:0] sdram_dqm, // SDRAM data mask (OE#; 0=active, 1=disabled)
32 inout [31:0] sdram_dq, // SDRAM data bus
34 // Debugging
35 output /*reg*/ [2:0] debug // debug bits
36 );
39 /****
40 * SDRAM data output buffer
41 ****/
42 // OE=1 for output mode, 0 for input
43 reg sdram_dq_oe;
44 // SDRAM output register
45 reg [31:0] sdram_dq_r;
46 assign sdram_dq = sdram_dq_oe ? sdram_dq_r : 32'hZZZZ;
50 /****
51 * State timer
52 * This is used to ensure that the state machine abides by RAM timing
53 * restrictions.
54 ****/
55 reg [31:0] timer;
58 /****
59 * MODE logic
60 ****/
61 reg [5:0] sdram_mode;
62 reg [11:0] sdram_addr;
63 assign sdram_cs_n = sdram_mode[3];
64 assign sdram_ras_n = sdram_mode[2];
65 assign sdram_cas_n = sdram_mode[1];
66 assign sdram_we_n = sdram_mode[0];
67 assign sdram_a = {sdram_addr[11], (sdram_mode[5] ? sdram_mode[4] : sdram_addr[10]), sdram_addr[9:0]};
69 // SDRAM chip instructions
70 // The bit order is as specified in the ISSI datasheet: A10 Override, A10, CS#, RAS#, CAS#, WE#.
71 // If A10 Override is set, then A10 will be overridden to the value specified in the M_ constant.
72 localparam M_BankActivate = 6'b0X0011;
73 localparam M_PrechargeBank = 6'b100010;
74 localparam M_PrechargeAll = 6'b110010;
75 localparam M_Write = 6'b100100;
76 localparam M_WritePrecharge = 6'b110100;
77 localparam M_Read = 6'b100101;
78 localparam M_ReadPrecharge = 6'b110101;
79 localparam M_LoadModeRegister = 6'b0X0000;
80 localparam M_Nop = 6'b0X0111;
81 localparam M_BurstStop = 6'b0X0110;
82 localparam M_Inhibit = 6'b0X1XXX; // maybe X1111?
83 localparam M_AutoRefresh = 6'b0X0001;
86 /****
87 * Refresh Timer
88 ****/
89 parameter REFRESH_INTERVAL = 32'd390 - 32'd1;
90 reg [31:0] refresh_timer;
91 reg refresh_req, refresh_ack, refresh_timer_en;
92 always @(posedge wb_clk_i) begin
93 if (wb_rst_i | !refresh_timer_en) begin
94 // Reset; clear timer, unset REFRESH REQUEST
95 refresh_req <= 1'b0;
96 refresh_timer <= REFRESH_INTERVAL;
97 end else if (refresh_ack) begin
98 // Refresh Ack, clear Refresh Request.
99 refresh_req <= 1'b0;
100 end else if (refresh_timer == 0) begin
101 // Refresh timer timed out, make a Refresh Request and reload the timer
102 refresh_req <= 1'b1;
103 refresh_timer <= REFRESH_INTERVAL;
104 end else begin
105 // Otherwise just decrement the timer
106 refresh_timer <= refresh_timer - 32'd1;
107 end
108 end
110 assign debug = { 1'b0, refresh_req, refresh_ack };
113 /****
114 * Address decoder
115 ****/
116 wire [8:0] column_addr;
117 wire [11:0] row_addr;
118 wire [1:0] bank_addr;
120 // Convert a 22-bit linear address into an SDRAM address
121 assign column_addr = wb_adr_i[8:0];
122 assign bank_addr = wb_adr_i[10:9];
123 assign row_addr = wb_adr_i[21:11];
126 /****
127 * Finite State Machine
128 ****/
129 localparam ST_INIT1 = 32'd0;
130 localparam ST_INIT2 = 32'd1;
131 localparam ST_NOP1 = 32'd2;
132 localparam ST_PrechargeAll = 32'd3;
133 localparam ST_PrechargeAll_Wait = 32'd4;
134 localparam ST_AutoRefresh1 = 32'd5;
135 localparam ST_AutoRefresh1_Wait = 32'd6;
136 localparam ST_AutoRefresh2 = 32'd7;
137 localparam ST_AutoRefresh2_Wait = 32'd8;
138 localparam ST_LoadModeRegister = 32'd9;
139 localparam ST_LoadModeRegister_Wait = 32'd10;
140 localparam ST_Spin = 32'd11; // <<== main 'spin' / 'idle' state
141 localparam ST_Refresh = 32'd12;
142 localparam ST_Refresh_Wait = 32'd13;
143 localparam ST_Test_Activate = 32'd500;
144 localparam ST_Test_Activate_Wait = 32'd501;
145 localparam ST_Test_Read = 32'd502;
146 localparam ST_Test_Read_Wait = 32'd503;
147 localparam ST_Test_Read_Finish = 32'd504;
148 localparam ST_Test_Write = 32'd505;
149 localparam ST_Test_Precharge_All = 32'd506;
150 localparam ST_Test_Precharge_All_Wait = 32'd507;
152 reg [31:0] state;
153 reg [31:0] captured_data;
154 always @(posedge wb_clk_i) begin
155 if (wb_rst_i) begin
156 // Initialise state machine and timer
157 state <= ST_INIT1;
158 // debug <= 3'd0;
159 timer <= 32'd0;
161 // Clear REFRESH ACK flag and disable refresh timer
162 refresh_ack <= 1'b0;
163 refresh_timer_en <= 1'b0;
165 // Initialisation state for SDRAM
166 sdram_cke <= 1'b0;
167 sdram_mode <= M_Inhibit;
168 sdram_addr <= 12'h000;
169 sdram_ba <= 2'b00;
170 sdram_dqm <= 4'b0000;
171 sdram_dq_oe <= 1'b0; // data output disabled
172 sdram_dq_r <= 32'd0;
173 end else begin
174 // timer logic
175 if (timer > 32'd0) begin
176 timer <= timer - 32'd1;
177 end
179 // state machine logic
180 case (state)
181 ST_INIT1: begin
182 // INIT1: Set up for initial power-up wait
183 state <= ST_INIT2;
184 timer <= 32'd50_000; // TODO: dependent on core clock rate. Needs to be >= 100us
186 // SDRAM state
187 sdram_cke <= 1'b0; // clock disabled
188 sdram_mode <= M_Inhibit;
189 sdram_addr <= 12'h000;
190 sdram_ba <= 2'b00;
191 sdram_dqm <= 4'b1111;
192 sdram_dq_oe <= 1'b0; // data output disabled
193 sdram_dq_r <= 32'd0;
194 end
196 ST_INIT2: begin
197 // INIT2: Power-up wait. Keep CKE low until ~50 cycles before
198 // the end of the power-up wait, then bring CKE high.
199 if (timer == 32'd0) begin
200 // Timer hit zero. Send a NOP.
201 state <= ST_NOP1;
202 end else if (timer < 32'd50) begin
203 // Timer value is more than zero but less than 50; CKE is on, but
204 // keep waiting for the timer to actually expire.
205 sdram_cke <= 1'b1;
206 state <= ST_INIT2;
207 // debug <= 3'd1;
208 end
209 sdram_mode <= M_Inhibit;
210 end
212 ST_NOP1: begin
213 // Apply one or more NOP commands to the SDRAM
214 sdram_mode <= M_Nop;
215 state <= ST_PrechargeAll;
216 end
218 ST_PrechargeAll: begin
219 // Precharge All, then wait T_rp (20ns)
220 sdram_mode <= M_PrechargeAll;
221 timer <= 32'd0; // wait 1tcy (40ns) ---> TIMER HERE
222 state <= ST_PrechargeAll_Wait;
223 end
225 ST_PrechargeAll_Wait: begin
226 // Wait for T_rp after Precharge All
227 sdram_mode <= M_Nop;
228 if (timer == 32'd0) begin
229 // Timer hit zero. Continue
230 state <= ST_AutoRefresh1;
231 end
232 end
234 ST_AutoRefresh1: begin
235 // Auto Refresh 1 of 2, wait T_rfc (70ns) after each
236 sdram_mode <= M_AutoRefresh;
237 timer <= 32'd1; // wait 2tcy (80ns) ---> TIMER HERE
238 state <= ST_AutoRefresh1_Wait;
239 end
241 ST_AutoRefresh1_Wait: begin
242 // Wait for T_rfc
243 sdram_mode <= M_Nop;
244 if (timer == 32'd0) begin
245 // Timer hit zero. Continue
246 state <= ST_AutoRefresh2;
247 end
248 end
250 ST_AutoRefresh2: begin
251 // Auto Refresh 2 of 2, wait T_rfc (70ns) after each
252 sdram_mode <= M_AutoRefresh;
253 timer <= 32'd1; // wait 2tcy (80ns) ---> TIMER HERE
254 state <= ST_AutoRefresh2_Wait;
255 end
257 ST_AutoRefresh2_Wait: begin
258 // Wait for T_rfc
259 sdram_mode <= M_Nop;
260 if (timer == 32'd0) begin
261 // Timer hit zero. Continue
262 state <= ST_LoadModeRegister;
263 end
264 end
266 ST_LoadModeRegister: begin
267 // Load Mode Register
268 /**
269 * Mode register:
270 * - BS0,1 = 00 [RFU]
271 * - A11,10 = 00 [RFU]
272 * - A9 = 0 [WBL -- write burst length same as read burst length]
273 * - A8,7 = 00 [Test Mode off]
274 * - A6..4 = 010 [CAS Latency = 2 clocks]
275 * - A3 = 0 [Burst type = sequential]
276 * - A2..0 = 000 [Burst length = 1 word]
277 */
278 sdram_ba <= 2'b00;
279 sdram_addr <= 12'b00_0_00_010_000;
280 sdram_mode <= M_LoadModeRegister;
282 // Wait T_mrd (2 clock cycles)
283 timer <= 32'd1; // (2cy)-1 ---> TIMER HERE
284 state <= ST_LoadModeRegister_Wait;
285 end
287 ST_LoadModeRegister_Wait: begin
288 // Wait for LMR to complete
289 sdram_mode <= M_Nop;
290 sdram_ba <= 2'd0;
291 sdram_addr <= 12'd0;
292 if (timer == 32'd0) begin
293 // Timer hit zero. Continue
294 state <= ST_Spin;
295 end
296 end
298 ST_Spin: begin
299 // Enable refresh timer
300 refresh_timer_en <= 1'b1;
302 sdram_mode <= M_Inhibit;
304 if (refresh_req) begin
305 // Refresh request received. Ack it and do a refresh.
306 refresh_ack <= 1'b1;
307 state <= ST_Refresh;
308 end else begin
309 //state <= ST_Spin; // NOTE: turned off to run a ram test...
310 state <= ST_Test_Activate;
311 end
312 end
314 ST_Refresh: begin
315 // Refresh timer timed out; do a refresh run
316 // Start by clearing the ACK flag (which was set by the Spin state)
317 refresh_ack <= 1'b0;
318 // Tell the SDRAM to do a Refresh
319 sdram_mode <= M_AutoRefresh;
320 // Wait for T_rfc
321 timer <= 32'd1; // wait Trfc (70ns ideally, we give 80ns) ---> TIMER HERE
322 state <= ST_Refresh_Wait;
323 end
325 ST_Refresh_Wait: begin
326 // Wait for T_rfc
327 sdram_mode <= M_Nop;
328 if (timer == 32'd0) begin
329 // Timer hit zero. Go back to spin state.
330 state <= ST_Spin;
331 end
332 end
334 ST_Test_Activate: begin
335 // Activate bank
336 sdram_mode <= M_BankActivate;
337 sdram_addr <= row_addr;
338 sdram_ba <= bank_addr;
339 timer <= 32'd0; // wait Trcd (20ns ideally, this is 40ns) ---> TIMER HERE
340 state <= ST_Test_Activate_Wait;
341 end
343 ST_Test_Activate_Wait: begin
344 // Wait for Activate Bank to complete
345 sdram_mode <= M_Nop;
346 if (timer == 32'd0) begin
347 state <= ST_Test_Read;
348 end
349 end
351 ST_Test_Read: begin
352 // Do the Read operation
353 sdram_mode <= M_Read;
354 sdram_addr <= column_addr;
355 sdram_dqm <= 4'b0000; // Allow data through (DQM = OE# = 1 to mask off, 0 to allow)
356 timer <= 32'd2 - 32'd1; // wait CAS# Latency (2 clock cycles) ---> TIMER HERE
357 state <= ST_Test_Read_Wait;
358 end
360 ST_Test_Read_Wait: begin
361 // Wait for CAS latency
362 sdram_mode <= M_Nop;
363 sdram_dqm <= 4'b1111; // Disable SDRAM output buffers
364 if (timer == 32'd0) begin
365 state <= ST_Test_Read_Finish;
366 captured_data <= sdram_dq;
367 end
368 end
370 ST_Test_Read_Finish: begin
371 // Additional NOP after read to avoid bus contention if next transaction is a write
372 sdram_mode <= M_Nop;
373 sdram_dqm <= 4'b1111; // Disable SDRAM output buffers
374 state <= ST_Test_Write;
375 end
377 ST_Test_Write: begin
378 // Write to SDRAM
379 sdram_mode <= M_Write;
380 sdram_addr <= column_addr;
381 sdram_dq_r <= ~captured_data; //32'h55AA_BCDE;
382 sdram_dq_oe <= 1'b1; // output enable
383 sdram_dqm <= 4'b0000; // Allow data through (DQM = OE# = 1 to mask off, 0 to allow)
384 state <= ST_Test_Precharge_All;
385 end
387 ST_Test_Precharge_All: begin
388 // Precharge All
389 sdram_mode <= M_PrechargeAll;
390 sdram_addr <= 12'd0;
391 sdram_dq_oe <= 1'b0; // output disable
392 sdram_dqm <= 4'b1111; // Disable SDRAM output buffers
393 sdram_dq_r <= 32'd0;
394 state <= ST_Spin;
395 // Wait T_rp (20ns)
396 timer <= 32'd0; // wait 1tcy (40ns) ---> TIMER HERE
397 state <= ST_Test_Precharge_All_Wait;
398 end
400 ST_Test_Precharge_All_Wait: begin
401 // Wait for T_rp after Precharge All
402 sdram_mode <= M_Nop;
403 if (timer == 32'd0) begin
404 // Timer hit zero. Continue
405 state <= ST_Spin;
406 end
407 end
408 endcase
409 end
410 end
412 endmodule