Tue, 10 Aug 2010 14:41:06 +0100
add refresh timer and refresh FSM logic
1 /****************************************************************************
2 *
3 *
4 ****************************************************************************/
6 module wb_sdram (
7 // Clocks and resets
8 input wb_clk_i, // WISHBONE clock
9 input wb_rst_i, // WISHBONE reset
11 // WISHBONE bus
12 input [31:0] wb_adr_i, // WISHBONE address
13 input [31:0] wb_dat_i, // WISHBONE data in
14 output reg [31:0] wb_dat_o, // WISHBONE data out
15 input [3:0] wb_sel_i, // WISHBONE byte select
16 input wb_we_i, // WISHBONE write enable (R/#W)
17 input wb_cyc_i, // WISHBONE cycle
18 input wb_stb_i, // WISHBONE strobe
19 output wb_ack_o, // WISHBONE cycle acknowledge (data available, DTACK)
20 output wb_err_o, // WISHBONE bus error
21 output wb_rty_o, // WISHBONE retry-later
23 // SDRAM
24 output reg sdram_cke, // SDRAM clock enable
25 output sdram_cs_n, // SDRAM chip select (active low)
26 output sdram_ras_n, // SDRAM row address strobe (active low)
27 output sdram_cas_n, // SDRAM column address strobe (active low)
28 output sdram_we_n, // SDRAM write enable (active low)
29 output [11:0] sdram_a, // SDRAM address
30 output reg [1:0] sdram_ba, // SDRAM bank address
31 output reg [3:0] sdram_dqm, // SDRAM data mask (OE#; 0=active, 1=disabled)
32 inout [31:0] sdram_dq, // SDRAM data bus
34 // Debugging
35 output /*reg*/ [2:0] debug // debug bits
36 );
39 /****
40 * SDRAM data output buffer
41 ****/
42 // OE=1 for output mode, 0 for input
43 reg sdram_dq_oe;
44 // SDRAM output register
45 reg [31:0] sdram_dq_r;
46 assign sdram_dq = sdram_dq_oe ? sdram_dq_r : 32'hZZZZ;
50 /****
51 * State timer
52 * This is used to ensure that the state machine abides by RAM timing
53 * restrictions.
54 ****/
55 reg [31:0] timer;
58 /****
59 * MODE logic
60 ****/
61 reg [5:0] sdram_mode;
62 reg [11:0] sdram_addr;
63 assign sdram_cs_n = sdram_mode[3];
64 assign sdram_ras_n = sdram_mode[2];
65 assign sdram_cas_n = sdram_mode[1];
66 assign sdram_we_n = sdram_mode[0];
67 assign sdram_a = {sdram_addr[11], (sdram_mode[5] ? sdram_mode[4] : sdram_addr[10]), sdram_addr[9:0]};
69 // SDRAM chip instructions
70 // The bit order is as specified in the ISSI datasheet: A10 Override, A10, CS#, RAS#, CAS#, WE#.
71 // If A10 Override is set, then A10 will be overridden to the value specified in the M_ constant.
72 localparam M_BankActivate = 6'b0X0011;
73 localparam M_PrechargeBank = 6'b100010;
74 localparam M_PrechargeAll = 6'b110010;
75 localparam M_Write = 6'b100100;
76 localparam M_WritePrecharge = 6'b110100;
77 localparam M_Read = 6'b100101;
78 localparam M_ReadPrecharge = 6'b110101;
79 localparam M_LoadModeRegister = 6'b0X0000;
80 localparam M_Nop = 6'b0X0111;
81 localparam M_BurstStop = 6'b0X0110;
82 localparam M_Inhibit = 6'b0X1XXX; // maybe X1111?
83 localparam M_AutoRefresh = 6'b0X0001;
86 /****
87 * Refresh Timer
88 ****/
89 parameter REFRESH_INTERVAL = 32'd390 - 32'd1;
90 reg [31:0] refresh_timer;
91 reg refresh_req, refresh_ack, refresh_timer_en;
92 always @(posedge wb_clk_i) begin
93 if (wb_rst_i | !refresh_timer_en) begin
94 // Reset; clear timer, unset REFRESH REQUEST
95 refresh_req <= 1'b0;
96 refresh_timer <= REFRESH_INTERVAL;
97 end else if (refresh_ack) begin
98 // Refresh Ack, clear Refresh Request.
99 refresh_req <= 1'b0;
100 end else if (refresh_timer == 0) begin
101 // Refresh timer timed out, make a Refresh Request and reload the timer
102 refresh_req <= 1'b1;
103 refresh_timer <= REFRESH_INTERVAL;
104 end else begin
105 // Otherwise just decrement the timer
106 refresh_timer <= refresh_timer - 32'd1;
107 end
108 end
110 assign debug = { 1'b0, refresh_req, refresh_ack };
112 /****
113 * Finite State Machine
114 ****/
115 localparam ST_INIT1 = 32'd0;
116 localparam ST_INIT2 = 32'd1;
117 localparam ST_NOP1 = 32'd2;
118 localparam ST_PrechargeAll = 32'd3;
119 localparam ST_PrechargeAll_Wait = 32'd4;
120 localparam ST_AutoRefresh1 = 32'd5;
121 localparam ST_AutoRefresh1_Wait = 32'd6;
122 localparam ST_AutoRefresh2 = 32'd7;
123 localparam ST_AutoRefresh2_Wait = 32'd8;
124 localparam ST_LoadModeRegister = 32'd9;
125 localparam ST_LoadModeRegister_Wait = 32'd10;
126 localparam ST_Spin = 32'd11; // <<== main 'spin' / 'idle' state
127 localparam ST_Refresh = 32'd12;
128 localparam ST_Refresh_Wait = 32'd13;
130 reg [31:0] state;
131 always @(posedge wb_clk_i) begin
132 if (wb_rst_i) begin
133 // Initialise state machine and timer
134 state <= ST_INIT1;
135 // debug <= 3'd0;
136 timer <= 32'd0;
138 // Clear REFRESH ACK flag and disable refresh timer
139 refresh_ack <= 1'b0;
140 refresh_timer_en <= 1'b0;
142 // Initialisation state for SDRAM
143 sdram_cke <= 1'b0;
144 sdram_mode <= M_Inhibit;
145 sdram_addr <= 12'h000;
146 sdram_ba <= 2'b00;
147 sdram_dqm <= 4'b0000;
148 sdram_dq_oe <= 1'b0; // data output disabled
149 sdram_dq_r <= 32'd0;
150 end else begin
151 // timer logic
152 if (timer > 32'd0) begin
153 timer <= timer - 32'd1;
154 end
156 // state machine logic
157 case (state)
158 ST_INIT1: begin
159 // INIT1: Set up for initial power-up wait
160 state <= ST_INIT2;
161 timer <= 32'd50_000; // TODO: dependent on core clock rate. Needs to be >= 100us
163 // SDRAM state
164 sdram_cke <= 1'b0; // clock disabled
165 sdram_mode <= M_Inhibit;
166 sdram_addr <= 12'h000;
167 sdram_ba <= 2'b00;
168 sdram_dqm <= 4'b1111;
169 sdram_dq_oe <= 1'b0; // data output disabled
170 sdram_dq_r <= 32'd0;
171 end
173 ST_INIT2: begin
174 // INIT2: Power-up wait. Keep CKE low until ~50 cycles before
175 // the end of the power-up wait, then bring CKE high.
176 if (timer == 32'd0) begin
177 // Timer hit zero. Send a NOP.
178 state <= ST_NOP1;
179 end else if (timer < 32'd50) begin
180 // Timer value is more than zero but less than 50; CKE is on, but
181 // keep waiting for the timer to actually expire.
182 sdram_cke <= 1'b1;
183 state <= ST_INIT2;
184 // debug <= 3'd1;
185 end
186 sdram_mode <= M_Inhibit;
187 end
189 ST_NOP1: begin
190 // Apply one or more NOP commands to the SDRAM
191 sdram_mode <= M_Nop;
192 state <= ST_PrechargeAll;
193 end
195 ST_PrechargeAll: begin
196 // Precharge All, then wait T_rp (20ns)
197 sdram_mode <= M_PrechargeAll;
198 timer <= 32'd0; // wait 1tcy (40ns) ---> TIMER HERE
199 state <= ST_PrechargeAll_Wait;
200 end
202 ST_PrechargeAll_Wait: begin
203 // Wait for T_rp after Precharge All
204 sdram_mode <= M_Nop;
205 if (timer == 32'd0) begin
206 // Timer hit zero. Continue
207 state <= ST_AutoRefresh1;
208 end
209 end
211 ST_AutoRefresh1: begin
212 // Auto Refresh 1 of 2, wait T_rfc (70ns) after each
213 sdram_mode <= M_AutoRefresh;
214 timer <= 32'd1; // wait 2tcy (80ns) ---> TIMER HERE
215 state <= ST_AutoRefresh1_Wait;
216 end
218 ST_AutoRefresh1_Wait: begin
219 // Wait for T_rfc
220 sdram_mode <= M_Nop;
221 if (timer == 32'd0) begin
222 // Timer hit zero. Continue
223 state <= ST_AutoRefresh2;
224 end
225 end
227 ST_AutoRefresh2: begin
228 // Auto Refresh 2 of 2, wait T_rfc (70ns) after each
229 sdram_mode <= M_AutoRefresh;
230 timer <= 32'd1; // wait 2tcy (80ns) ---> TIMER HERE
231 state <= ST_AutoRefresh2_Wait;
232 end
234 ST_AutoRefresh2_Wait: begin
235 // Wait for T_rfc
236 sdram_mode <= M_Nop;
237 if (timer == 32'd0) begin
238 // Timer hit zero. Continue
239 state <= ST_LoadModeRegister;
240 end
241 end
243 ST_LoadModeRegister: begin
244 // Load Mode Register
245 /**
246 * Mode register:
247 * - BS0,1 = 00 [RFU]
248 * - A11,10 = 00 [RFU]
249 * - A9 = 0 [WBL -- write burst length same as read burst length]
250 * - A8,7 = 00 [Test Mode off]
251 * - A6..4 = 010 [CAS Latency = 2 clocks]
252 * - A3 = 0 [Burst type = sequential]
253 * - A2..0 = 000 [Burst length = 1 word]
254 */
255 sdram_ba <= 2'b00;
256 sdram_addr <= 12'b00_0_00_010_000;
257 sdram_mode <= M_LoadModeRegister;
259 // Wait T_mrd (2 clock cycles)
260 timer <= 32'd1; // (2cy)-1 ---> TIMER HERE
261 state <= ST_LoadModeRegister_Wait;
262 end
264 ST_LoadModeRegister_Wait: begin
265 // Wait for LMR to complete
266 sdram_mode <= M_Nop;
267 sdram_ba <= 2'd0;
268 sdram_addr <= 12'd0;
269 if (timer == 32'd0) begin
270 // Timer hit zero. Continue
271 state <= ST_Spin;
272 end
273 end
275 ST_Spin: begin
276 // Enable refresh timer
277 refresh_timer_en <= 1'b1;
279 sdram_mode <= M_Inhibit;
281 if (refresh_req) begin
282 // Refresh request received. Ack it and do a refresh.
283 refresh_ack <= 1'b1;
284 state <= ST_Refresh;
285 end else begin
286 state <= ST_Spin;
287 end
288 end
290 ST_Refresh: begin
291 // Refresh timer timed out; do a refresh run
292 // Start by clearing the ACK flag (which was set by the Spin state)
293 refresh_ack <= 1'b0;
294 // Tell the SDRAM to do a Refresh
295 sdram_mode <= M_AutoRefresh;
296 // Wait for T_rfc
297 timer <= 32'd1; // wait Trfc (70ns ideally, we give 80ns) ---> TIMER HERE
298 state <= ST_Refresh_Wait;
299 end
301 ST_Refresh_Wait: begin
302 // Wait for T_rfc
303 sdram_mode <= M_Nop;
304 if (timer == 32'd0) begin
305 // Timer hit zero. Go back to spin state.
306 state <= ST_Spin;
307 end
308 end
309 endcase
310 end
311 end
313 endmodule