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IPCores/wb_sdram / changelog

changelog

[wb_sdram] tidy up refresh time parameterisation

  • Tue, 10 Aug 2010 22:49:21 +0100
  • by Philip Pemberton <philpem@philpem.me.uk> [Tue, 10 Aug 2010 22:49:21 +0100] rev 12
  • [wb_sdram] tidy up refresh time parameterisation

[wb_sdram] lock debug pins low

  • Tue, 10 Aug 2010 22:14:22 +0100
  • by Philip Pemberton <philpem@philpem.me.uk> [Tue, 10 Aug 2010 22:14:22 +0100] rev 11
  • [wb_sdram] lock debug pins low

[wb_sdram] parameterise timing and CAS latency

  • Tue, 10 Aug 2010 22:11:51 +0100
  • by Philip Pemberton <philpem@philpem.me.uk> [Tue, 10 Aug 2010 22:11:51 +0100] rev 10
  • [wb_sdram] parameterise timing and CAS latency

[wb_sdram] move ACK logic around and set DQM from wb_sel_i

  • Tue, 10 Aug 2010 19:23:01 +0100
  • by Philip Pemberton <philpem@philpem.me.uk> [Tue, 10 Aug 2010 19:23:01 +0100] rev 9
  • [wb_sdram] move ACK logic around and set DQM from wb_sel_i

    write mask (DQM) is now set from WB_SEL_I. reads still pull the whole word.

[wb_sdram] add drivers for unused WISHBONE i/os

  • Tue, 10 Aug 2010 18:35:50 +0100
  • by Philip Pemberton <philpem@philpem.me.uk> [Tue, 10 Aug 2010 18:35:50 +0100] rev 8
  • [wb_sdram] add drivers for unused WISHBONE i/os

[wb_sdram] remove test logic and convert into a proper WISHBONE peripheral

  • Tue, 10 Aug 2010 18:33:25 +0100
  • by Philip Pemberton <philpem@philpem.me.uk> [Tue, 10 Aug 2010 18:33:25 +0100] rev 7
  • [wb_sdram] remove test logic and convert into a proper WISHBONE peripheral

make test work like a R/W checkerboard instead (looks better on the LA)

  • Tue, 10 Aug 2010 18:04:05 +0100
  • by Philip Pemberton <philpem@philpem.me.uk> [Tue, 10 Aug 2010 18:04:05 +0100] rev 6
  • make test work like a R/W checkerboard instead (looks better on the LA)

add NOP after read to avoid bus contention when doing back-to-back R/Ws

  • Tue, 10 Aug 2010 17:42:18 +0100
  • by Philip Pemberton <philpem@philpem.me.uk> [Tue, 10 Aug 2010 17:42:18 +0100] rev 5
  • add NOP after read to avoid bus contention when doing back-to-back R/Ws

add basic R/W test

  • Tue, 10 Aug 2010 17:36:00 +0100
  • by Philip Pemberton <philpem@philpem.me.uk> [Tue, 10 Aug 2010 17:36:00 +0100] rev 4
  • add basic R/W test

add refresh timer and refresh FSM logic

  • Tue, 10 Aug 2010 14:41:06 +0100
  • by Philip Pemberton <philpem@philpem.me.uk> [Tue, 10 Aug 2010 14:41:06 +0100] rev 3
  • add refresh timer and refresh FSM logic

implement (almost) complete SDRAM init sequence

  • Tue, 10 Aug 2010 13:23:58 +0100
  • by Philip Pemberton <philpem@philpem.me.uk> [Tue, 10 Aug 2010 13:23:58 +0100] rev 2
  • implement (almost) complete SDRAM init sequence

make spinstate more noticeable on LA, fix CKE init timer

  • Tue, 10 Aug 2010 12:58:34 +0100
  • by Philip Pemberton <philpem@philpem.me.uk> [Tue, 10 Aug 2010 12:58:34 +0100] rev 1
  • make spinstate more noticeable on LA, fix CKE init timer

    cke init timer was running 1cy longer than it should have
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