IPCores/wb_sdram / changelog

parameterise data and addr. buses, tidy up

• Wed, 18 Aug 2010 14:10:48 +0100
• by Philip Pemberton <philpem@philpem.me.uk> [Wed, 18 Aug 2010 14:10:48 +0100] rev 17
• parameterise data and addr. buses, tidy up
  
  Parameterised the width of the data and address buses, and the number of
  COLUMN, ROW and BANK address bits.
  
  Tidied up code to (hopefully!) work when bus widths are changed.

[wb_sdram] add nice comments to explain sdram timings

• Wed, 11 Aug 2010 01:19:03 +0100
• by Philip Pemberton <philpem@philpem.me.uk> [Wed, 11 Aug 2010 01:19:03 +0100] rev 16
• [wb_sdram] add nice comments to explain sdram timings

fully parameterise CLOCK_RATE and SDRAM timing

• Wed, 11 Aug 2010 01:15:20 +0100
• by Philip Pemberton <philpem@philpem.me.uk> [Wed, 11 Aug 2010 01:15:20 +0100] rev 15
• fully parameterise CLOCK_RATE and SDRAM timing

[wb_sdram] code tidy up

• Tue, 10 Aug 2010 23:11:10 +0100
• by Philip Pemberton <philpem@philpem.me.uk> [Tue, 10 Aug 2010 23:11:10 +0100] rev 14
• [wb_sdram] code tidy up

[wb_sdram] add note re. CL=3 testing

• Tue, 10 Aug 2010 22:51:47 +0100
• by Philip Pemberton <philpem@philpem.me.uk> [Tue, 10 Aug 2010 22:51:47 +0100] rev 13
• [wb_sdram] add note re. CL=3 testing

[wb_sdram] tidy up refresh time parameterisation

• Tue, 10 Aug 2010 22:49:21 +0100
• by Philip Pemberton <philpem@philpem.me.uk> [Tue, 10 Aug 2010 22:49:21 +0100] rev 12
• [wb_sdram] tidy up refresh time parameterisation

[wb_sdram] lock debug pins low

• Tue, 10 Aug 2010 22:14:22 +0100
• by Philip Pemberton <philpem@philpem.me.uk> [Tue, 10 Aug 2010 22:14:22 +0100] rev 11
• [wb_sdram] lock debug pins low

[wb_sdram] parameterise timing and CAS latency

• Tue, 10 Aug 2010 22:11:51 +0100
• by Philip Pemberton <philpem@philpem.me.uk> [Tue, 10 Aug 2010 22:11:51 +0100] rev 10
• [wb_sdram] parameterise timing and CAS latency

[wb_sdram] move ACK logic around and set DQM from wb_sel_i

• Tue, 10 Aug 2010 19:23:01 +0100
• by Philip Pemberton <philpem@philpem.me.uk> [Tue, 10 Aug 2010 19:23:01 +0100] rev 9
• [wb_sdram] move ACK logic around and set DQM from wb_sel_i
  
  write mask (DQM) is now set from WB_SEL_I. reads still pull the whole word.

[wb_sdram] add drivers for unused WISHBONE i/os

• Tue, 10 Aug 2010 18:35:50 +0100
• by Philip Pemberton <philpem@philpem.me.uk> [Tue, 10 Aug 2010 18:35:50 +0100] rev 8
• [wb_sdram] add drivers for unused WISHBONE i/os

[wb_sdram] remove test logic and convert into a proper WISHBONE peripheral

• Tue, 10 Aug 2010 18:33:25 +0100
• by Philip Pemberton <philpem@philpem.me.uk> [Tue, 10 Aug 2010 18:33:25 +0100] rev 7
• [wb_sdram] remove test logic and convert into a proper WISHBONE peripheral

make test work like a R/W checkerboard instead (looks better on the LA)

• Tue, 10 Aug 2010 18:04:05 +0100
• by Philip Pemberton <philpem@philpem.me.uk> [Tue, 10 Aug 2010 18:04:05 +0100] rev 6
• make test work like a R/W checkerboard instead (looks better on the LA)