IPCores/wb_sdram: shortlog

shortlog

[wb_sdram] remove test logic and convert into a proper WISHBONE peripheral Philip Pemberton Tue, 10 Aug 2010 18:33:25 +0100	changeset files
make test work like a R/W checkerboard instead (looks better on the LA) Philip Pemberton Tue, 10 Aug 2010 18:04:05 +0100	changeset files
add NOP after read to avoid bus contention when doing back-to-back R/Ws Philip Pemberton Tue, 10 Aug 2010 17:42:18 +0100	changeset files
add basic R/W test Philip Pemberton Tue, 10 Aug 2010 17:36:00 +0100	changeset files
add refresh timer and refresh FSM logic Philip Pemberton Tue, 10 Aug 2010 14:41:06 +0100	changeset files
implement (almost) complete SDRAM init sequence Philip Pemberton Tue, 10 Aug 2010 13:23:58 +0100	changeset files
make spinstate more noticeable on LA, fix CKE init timer Philip Pemberton Tue, 10 Aug 2010 12:58:34 +0100	changeset files

less more | (0) +7 +10 tip