Sat, 27 Nov 2010 01:13:12 +0000
initial commit
1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 1.2 +++ b/.hgignore Sat Nov 27 01:13:12 2010 +0000 1.3 @@ -0,0 +1,7 @@ 1.4 +syntax: glob 1.5 +obj/*.o 1.6 +dep/*.d 1.7 +*~ 1.8 +.*.sw? 1.9 +.~lock* 1.10 +.buildnum
2.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 2.2 +++ b/Makefile Sat Nov 27 01:13:12 2010 +0000 2.3 @@ -0,0 +1,454 @@ 2.4 +# Phil's multiplatform makefile template 2.5 +# With auto-incrementing build number and automatic version.h generation 2.6 +# Version 1.8, 2010-02-15 2.7 +# 2.8 +# The latest version of this Makefile can be found at http://www.philpem.me.uk/ 2.9 +# 2.10 +# 2.11 +# Copyright (c) 2010 Philip Pemberton <code@philpem.me.uk> 2.12 +# 2.13 +# Permission is hereby granted, free of charge, to any person obtaining a copy 2.14 +# of this software and associated documentation files (the "Software"), to deal 2.15 +# in the Software without restriction, including without limitation the rights 2.16 +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 2.17 +# copies of the Software, and to permit persons to whom the Software is 2.18 +# furnished to do so, subject to the following conditions: 2.19 +# 2.20 +# The above copyright notice and this permission notice shall be included in 2.21 +# all copies or substantial portions of the Software. 2.22 +# 2.23 +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 2.24 +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 2.25 +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 2.26 +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 2.27 +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 2.28 +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 2.29 +# THE SOFTWARE. 2.30 +# 2.31 +# 2.32 +# Instructions for use: 2.33 +# Run 'make init' to create the required directories 2.34 +# Add your source files to the 'SOURCES' list, and change the TARGET filename 2.35 +# Set the desired build type and platform in the BUILD_TYPE and PLATFORM 2.36 +# variables respectively 2.37 +# Set your project type (C only, or C++) in the SRC_TYPE variable 2.38 +# Add any libraries you need to link against to the 'LIB' list 2.39 +# Run 'make' 2.40 +# 2.41 +# Object files are created in the 'obj' subdirectory, from source code in the 2.42 +# 'src' directory. Dependency files are created in the 'dep' directory from 2.43 +# the same source code the object files are created from. 2.44 +# 2.45 +# Supported targets are: 2.46 +# all Build everything. 2.47 +# update-revision Increment the build number without building anything. 2.48 +# clean-versioninfo Delete src/version.h (will be rebuilt on the next 2.49 +# 'make all'). 2.50 +# init Initialise the build system for a new project. 2.51 +# WARNING: overwrites .buildnum and src/version.h.in! 2.52 +# cleandep Delete all dependency files. 2.53 +# clean Delete all dependency, intermediate and target files. 2.54 +# tidy Delete all dependency and intermediate files, leaving 2.55 +# the target file intact. 2.56 +# 2.57 +# If you want to reset the build number to zero, delete '.buildnum'. This 2.58 +# should be done whenever the major or minor version changes. Excluding 2.59 +# .buildnum from version control may also be a good idea, depending on how 2.60 +# you want your build numbers to work. 2.61 +# 2.62 +# The BUILD_TYPE variable contains the current build type. There are two 2.63 +# supported build types: 2.64 +# debug Debug mode - object files are compiled with debug information 2.65 +# and the target is left unstripped. 2.66 +# release Release mode - object files are not compiled with debug info, 2.67 +# and the target is fed through strip to remove redundant 2.68 +# data. 2.69 +# 2.70 +# The PLATFORM variable contains the current target platform. There are two 2.71 +# supported platforms: 2.72 +# linux GNU/Linux with GNU Compiler Collection 2.73 +# win32 Windows 32-bit with MinGW 2.74 +# 2.75 +# The EXTSRC variable is used to specify other files to build. It is typically 2.76 +# used to specify platform or build-type specific source files, e.g. 2.77 +# 2.78 +# ifeq ($(BUILD_TYPE),debug-memwatch) 2.79 +# CFLAGS += -g -ggdb 2.80 +# CPPFLAGS += -DMEMWATCH 2.81 +# INCPATH += ./memwatch 2.82 +# EXTSRC += memwatch/memwatch.c 2.83 +# endif 2.84 +# 2.85 +# (example taken from one of my projects that allowed the use of Memwatch to 2.86 +# track down memory allocation/deallocation bugs) 2.87 +# 2.88 +# 2.89 +# Change history: 2.90 +# 1.8 - Now supports the use of the wxWidgets GUI framework. To turn 2.91 +# this on, set ENABLE_WX to "yes". 2.92 +# 1.7 - Now creates a basic Hgignore file and directory keepers for the 2.93 +# dep and obj directories. 2.94 +# 1.6 - Added CFLAGS and CXXFLAGS to the command-lines for the dependency 2.95 +# building commands. This was causing issues with C99 / C++0x mode. 2.96 +# 1.5 - Added support for Mercurial revision (changeset ID) display 2.97 +# Fixed a few issues with Subversion support (svn: and version 0 would 2.98 +# be displayed for exported code) 2.99 +# 2.100 + 2.101 +#### 2.102 +# Build configuration 2.103 +#### 2.104 + 2.105 +# version information -- major.minor.extra 2.106 +# note that VER_EXTRA can be overridden on the command line, e.g.: 2.107 +# make VER_EXTRA=12345 all 2.108 +VER_MAJOR = 0 2.109 +VER_MINOR = 0 2.110 +VER_EXTRA ?= 2.111 + 2.112 +# build platform: win32 or linux 2.113 +PLATFORM ?= linux 2.114 +# build type: release or debug 2.115 +BUILD_TYPE ?= debug 2.116 + 2.117 +# target executable 2.118 +TARGET = 3b1emu 2.119 + 2.120 +# source files that produce object files 2.121 +SRC = main.c musashi/m68kcpu.c musashi/m68kops.c 2.122 + 2.123 +# source type - either "c" or "cpp" (C or C++) 2.124 +SRC_TYPE = c 2.125 + 2.126 +# additional object files that don't necessarily include source 2.127 +EXT_OBJ = 2.128 +# libraries to link in -- these will be specified as "-l" parameters, the -l 2.129 +# is prepended automatically 2.130 +LIB = sdl 2.131 +# library paths -- where to search for the above libraries 2.132 +LIBPATH = musashi 2.133 +# include paths -- where to search for #include files (in addition to the 2.134 +# standard paths 2.135 +INCPATH = musashi 2.136 +# garbage files that should be deleted on a 'make clean' or 'make tidy' 2.137 +GARBAGE = obj/musashi/m68kmake obj/musashi/m68kmake.exe obj/musashi/m68kmake.o 2.138 + 2.139 +# extra dependencies - files that we don't necessarily know how to build, but 2.140 +# that are required for building the application; e.g. object files or 2.141 +# libraries in sub or parent directories 2.142 +EXTDEP = 2.143 + 2.144 +# Extra libraries 2.145 +# wxWidgets: set to "yes" to enable, anything else to disable 2.146 +ENABLE_WX = no 2.147 +# wxWidgets: list of wxWidgets libraries to enable 2.148 +WX_LIBS = std 2.149 + 2.150 +#### 2.151 +# Win32 target-specific settings 2.152 +#### 2.153 +ifeq ($(strip $(PLATFORM)),win32) 2.154 + # windows executables have a .exe suffix 2.155 + TARGET := $(addsuffix .exe,$(TARGET)) 2.156 + # console mode application 2.157 + EXT_CFLAGS = -mconsole 2.158 +endif 2.159 + 2.160 + 2.161 +#### 2.162 +# Tool setup 2.163 +#### 2.164 +MAKE = make 2.165 +CC = gcc 2.166 +CXX = g++ 2.167 +CFLAGS = -Wall -pedantic -std=gnu99 $(EXT_CFLAGS) 2.168 +CXXFLAGS= -Wall -pedantic -std=gnu++0x $(EXT_CXXFLAGS) 2.169 +LDFLAGS = $(EXT_LDFLAGS) 2.170 +RM = rm 2.171 +STRIP = strip 2.172 + 2.173 +############################################################################### 2.174 +# You should not need to touch anything below here, unless you're adding a new 2.175 +# platform or build type (or changing the version string format) 2.176 +############################################################################### 2.177 + 2.178 +#### 2.179 +# A quick sanity check on the platform type 2.180 +#### 2.181 +ifneq ($(PLATFORM),linux) 2.182 +ifneq ($(PLATFORM),win32) 2.183 + $(error Platform '$(PLATFORM)' not supported. Supported platforms are: linux, win32) 2.184 +endif 2.185 +endif 2.186 + 2.187 +#### 2.188 +# Version info generation 2.189 +#### 2.190 +# get the current build number 2.191 +VER_BUILDNUM = $(shell cat .buildnum) 2.192 + 2.193 +#### --- begin Subversion revision grabber --- 2.194 +# there are two ways to get the SVN revision - use svnversion, or use svn info 2.195 +# then pipe through awk. which one you use is up to you. 2.196 +VER_SVNREV = $(shell LANG=C svn info 2>/dev/null || echo 'Revision: exported' | awk '/^Revision:/ { print$$2 }' ) 2.197 +#VER_SVNREV = $(shell svnversion .) 2.198 + 2.199 +# if the version string is "exported", then the CSD was not checked out of SVN 2.200 +# note that if the CSD is not an SVN checkout, then @@svnrev@@ will be set to 2.201 +# zero. 2.202 +ifeq ($(VER_SVNREV),exported) 2.203 + VER_VCS = none 2.204 + VER_VCSREV = 0 2.205 +else 2.206 + VER_VCS = svn 2.207 + VER_VCSREV = $(VER_SVNREV) 2.208 +endif 2.209 + 2.210 +#### --- begin Mercurial revision grabber --- 2.211 +# If SVN didn't give us a revision, try Mercurial instead 2.212 +ifeq ($(VER_VCS),none) 2.213 + # get the current Mercurial changeset number 2.214 + VER_HGREV=$(shell ((hg tip --template "{node|short}") || echo "000000000000") 2>/dev/null) 2.215 + ifneq ($(VER_HGREV),000000000000) 2.216 + # a non-empty repo 2.217 + VER_VCS = hg 2.218 + VER_VCSREV = $(VER_HGREV) 2.219 + else 2.220 + # either an empty Hg repo, or no repo at all 2.221 + VER_VCS = none 2.222 + VER_VCSREV = 0 2.223 + endif 2.224 +endif 2.225 + 2.226 +#### --- end version grabbers --- 2.227 + 2.228 +# start creating the revision string 2.229 +VER_FULLSTR = $(VER_MAJOR).$(VER_MINOR).$(VER_BUILDNUM)$(VER_EXTRA) 2.230 + 2.231 +# if this is a VCS release, include the SVN revision in the version string 2.232 +# also create a revision string that is either "svn:12345", "hg:12345" or 2.233 +# blank 2.234 +ifneq ($(VER_VCS),none) 2.235 + VER_FULLSTR += ($(VER_VCS) $(VER_VCSREV)) 2.236 + VER_VCSSTR = $(VER_VCS):$(VER_VCSREV) 2.237 +else 2.238 + VER_VCSSTR = 2.239 +endif 2.240 + 2.241 + 2.242 +#### 2.243 +# Build-type specific configuration 2.244 +#### 2.245 +ifeq ($(BUILD_TYPE),debug) 2.246 + CFLAGS += -g -ggdb -DDEBUG 2.247 + CXXFLAGS += -g -ggdb -DDEBUG 2.248 +else 2.249 + ifeq ($(BUILD_TYPE),release) 2.250 + CFLAGS += -O2 2.251 + CXXFLAGS += -O2 2.252 + else 2.253 + $(error Unsupported build type: '$(BUILD_TYPE)') 2.254 + endif 2.255 +endif 2.256 + 2.257 +#### 2.258 +# wxWidgets support 2.259 +#### 2.260 +ifeq ($(ENABLE_WX),yes) 2.261 + ifeq ($(BUILD_TYPE),debug) 2.262 + LIBLNK += `wx-config --debug --libs $(WX_LIBS)` 2.263 + CFLAGS += `wx-config --debug --cflags $(WX_LIBS)` 2.264 + CXXFLAGS += `wx-config --debug --cxxflags $(WX_LIBS)` 2.265 + CPPFLAGS += `wx-config --debug --cppflags $(WX_LIBS)` 2.266 + else 2.267 + ifeq ($(BUILD_TYPE),release) 2.268 + LIBLNK += `wx-config --libs $(WX_LIBS)` 2.269 + CFLAGS += `wx-config --cflags $(WX_LIBS)` 2.270 + CPPFLAGS += `wx-config --cppflags $(WX_LIBS)` 2.271 + CXXFLAGS += `wx-config --cxxflags $(WX_LIBS)` 2.272 + else 2.273 + $(error Unsupported build type: '$(BUILD_TYPE)') 2.274 + endif 2.275 + endif 2.276 +endif 2.277 + 2.278 +#### 2.279 +# rules 2.280 +#### 2.281 + 2.282 +# object files 2.283 +OBJ = $(addprefix obj/, $(addsuffix .o, $(basename $(SRC))) $(EXT_OBJ)) $(addsuffix .o, $(basename $(EXTSRC))) 2.284 + 2.285 +# dependency files 2.286 +DEPFILES = $(addprefix dep/, $(addsuffix .d, $(basename $(SRC))) $(EXT_OBJ)) $(addsuffix .d, $(basename $(EXTSRC))) 2.287 + 2.288 +# path commands 2.289 +LIBLNK += $(addprefix -l, $(LIB)) 2.290 +LIBPTH += $(addprefix -L, $(LIBPATH)) 2.291 +INCPTH += $(addprefix -I, $(INCPATH)) 2.292 + 2.293 +CPPFLAGS += $(INCPTH) 2.294 + 2.295 +#### 2.296 +# Make sure there is at least one object file to be linked in 2.297 +#### 2.298 +ifeq ($(strip $(OBJ)),) 2.299 + $(error Unable to build: no object or source files specified in Makefile) 2.300 +endif 2.301 + 2.302 +#### 2.303 +# targets 2.304 +#### 2.305 +.PHONY: default all update-revision versionheader clean-versioninfo init cleandep clean tidy 2.306 + 2.307 +all: update-revision 2.308 + @$(MAKE) versionheader 2.309 + $(MAKE) $(TARGET) 2.310 + 2.311 +# increment the current build number 2.312 +NEWBUILD=$(shell expr $(VER_BUILDNUM) + 1) 2.313 +update-revision: 2.314 + @echo $(NEWBUILD) > .buildnum 2.315 + 2.316 +versionheader: 2.317 + @sed -e 's/@@date@@/$(shell LC_ALL=C date)/g' \ 2.318 + -e 's/@@time@@/$(shell LC_ALL=C date +%T)/g' \ 2.319 + -e 's/@@whoami@@/$(shell whoami)/g' \ 2.320 + -e 's/@@hostname@@/$(shell hostname)/g' \ 2.321 + -e 's|@@compiler@@|$(shell $(CC) $(CFLAGS) -v 2>&1 | tail -n 1 | sed -e "s;|;/;")|g' \ 2.322 + -e 's/@@majorver@@/$(VER_MAJOR)/g' \ 2.323 + -e 's/@@minorver@@/$(VER_MINOR)/g' \ 2.324 + -e 's/@@extraver@@/$(subst \",,$(VER_EXTRA))/g' \ 2.325 + -e 's/@@buildnum@@/$(VER_BUILDNUM)/g' \ 2.326 + -e 's/@@buildtype@@/$(BUILD_TYPE)/g' \ 2.327 + -e 's/@@vcs@@/$(VER_VCS)/g' \ 2.328 + -e 's/@@vcsrev@@/$(VER_VCSREV)/g' \ 2.329 + -e 's/@@vcsstr@@/$(VER_VCSSTR)/g' \ 2.330 + -e 's/@@fullverstr@@/$(VER_FULLSTR)/g' \ 2.331 + -e 's/@@cflags@@/$(CFLAGS)/g' \ 2.332 + < src/version.h.in > src/version.h 2.333 + 2.334 +# version.h creation stuff based on code from the Xen makefile 2.335 +clean-versioninfo: 2.336 + @if [ ! -r src/version.h -o -O src/version.h ]; then \ 2.337 + rm -f src/version.h; \ 2.338 + fi 2.339 + @echo 0 > .buildnum 2.340 + 2.341 +# initialise the build system for a new project 2.342 +init: 2.343 + @mkdir -p src dep obj 2.344 + @echo "This file is a directory-keeper. Do not delete it." > dep/.keepme 2.345 + @echo "This file is a directory-keeper. Do not delete it." > obj/.keepme 2.346 + @echo 0 > .buildnum 2.347 + @echo 'syntax: glob' > .hgignore 2.348 + @echo 'obj/*.o' >> .hgignore 2.349 + @echo 'dep/*.d' >> .hgignore 2.350 + @echo '*~' >> .hgignore 2.351 + @echo '.*.sw?' >> .hgignore 2.352 + @echo '#define VER_COMPILE_DATE "@@date@@"' > src/version.h.in 2.353 + @echo '#define VER_COMPILE_TIME "@@time@@"' >> src/version.h.in 2.354 + @echo '#define VER_COMPILE_BY "@@whoami@@"' >> src/version.h.in 2.355 + @echo '#define VER_COMPILE_HOST "@@hostname@@"' >> src/version.h.in 2.356 + @echo '#define VER_COMPILER "@@compiler@@"' >> src/version.h.in 2.357 + @echo '#define VER_BUILD_TYPE "@@buildtype@@"' >> src/version.h.in 2.358 + @echo '#define VER_CFLAGS "@@cflags@@"' >> src/version.h.in 2.359 + @echo '' >> src/version.h.in 2.360 + @echo '#define VER_MAJOR @@majorver@@' >> src/version.h.in 2.361 + @echo '#define VER_MINOR @@minorver@@' >> src/version.h.in 2.362 + @echo '#define VER_BUILDNUM @@buildnum@@' >> src/version.h.in 2.363 + @echo '#define VER_EXTRA "@@extraver@@"' >> src/version.h.in 2.364 + @echo '#define VER_VCSREV "@@vcsstr@@"' >> src/version.h.in 2.365 + @echo '' >> src/version.h.in 2.366 + @echo '#define VER_FULLSTR "@@fullverstr@@"' >> src/version.h.in 2.367 + @echo '' >> src/version.h.in 2.368 + @echo Build system initialised 2.369 + 2.370 +# remove the dependency files 2.371 +cleandep: 2.372 + -rm $(DEPFILES) 2.373 + 2.374 +# remove the dependency files and any target or intermediate build files 2.375 +clean: cleandep clean-versioninfo 2.376 + -rm $(OBJ) $(TARGET) $(GARBAGE) 2.377 + 2.378 +# remove any dependency or intermediate build files 2.379 +tidy: cleandep clean-versioninfo 2.380 + -rm $(OBJ) $(GARBAGE) 2.381 + 2.382 +################################# 2.383 + 2.384 +$(TARGET): $(OBJ) $(EXTDEP) 2.385 +ifeq ($(SRC_TYPE),c) 2.386 + $(CC) $(CXXFLAGS) $(LDFLAGS) $(OBJ) $(LIBPTH) $(LIBLNK) -o $@ 2.387 +else 2.388 + $(CXX) $(CXXFLAGS) $(LDFLAGS) $(OBJ) $(LIBPTH) $(LIBLNK) -o $@ 2.389 +endif 2.390 +ifeq ($(BUILD_TYPE),release) 2.391 + $(STRIP) $(TARGET) 2.392 +endif 2.393 + 2.394 +### 2.395 +# extra rules 2.396 +# example: 2.397 +#src/parser.c: src/parser.h 2.398 + 2.399 + 2.400 +#### 2.401 +## musashi build rules 2.402 +# 68k CPU builder 2.403 +obj/musashi/m68kmake: obj/musashi/m68kmake.o 2.404 + $(CC) $(CFLAGS) $(CPPFLAGS) obj/musashi/m68kmake.o -o $@ 2.405 +# 68k CPU sources 2.406 +src/musashi/m68kops.h src/musashi/m68kops.c: obj/musashi/m68kmake src/musashi/m68k_in.c 2.407 + ./obj/musashi/m68kmake src/musashi src/musashi/m68k_in.c 2.408 + 2.409 +#### 2.410 +# make object files from C source files 2.411 +obj/%.o: src/%.c 2.412 + $(CC) -c $(CFLAGS) $(CPPFLAGS) $< -o $@ 2.413 + 2.414 +## 2.415 +# make object files from C++ source files 2.416 +obj/%.o: src/%.cc 2.417 + $(CXX) -c $(CXXFLAGS) $(CPPFLAGS) $< -o $@ 2.418 + 2.419 +obj/%.o: src/%.cpp 2.420 + $(CXX) -c $(CXXFLAGS) $(CPPFLAGS) $< -o $@ 2.421 + 2.422 +### 2.423 +# make C files from yacc/bison source 2.424 +src/%.h src/%.c: src/%.y 2.425 + $(YACC) $(YFLAGS) -d $< 2.426 + mv -f y.tab.c $*.c 2.427 + mv -f y.tab.h $*.h 2.428 + 2.429 +### 2.430 +# make C files from lex/flex source 2.431 +src/%.c: src/%.l 2.432 + $(LEX) $(LFLAGS) -o$@ $< 2.433 + 2.434 +### 2.435 +# make dependencies for our source files 2.436 +dep/%.d: src/%.c 2.437 + $(CC) -MM $(CFLAGS) $(CPPFLAGS) $< > $@.$$$$; \ 2.438 + sed 's,\($*\)\.o[ :]*,obj/\1.o $@ : ,g' < $@.$$$$ > $@; \ 2.439 + rm -f $@.$$$$ 2.440 + 2.441 +dep/%.d: src/%.cpp 2.442 + $(CXX) -MM $(CXXFLAGS) $(CPPFLAGS) $< > $@.$$$$; \ 2.443 + sed 's,\($*\)\.o[ :]*,obj/\1.o $@ : ,g' < $@.$$$$ > $@; \ 2.444 + rm -f $@.$$$$ 2.445 + 2.446 +dep/%.d: src/%.cc 2.447 + $(CXX) -MM $(CXXFLAGS) $(CPPFLAGS) $< > $@.$$$$; \ 2.448 + sed 's,\($*\)\.o[ :]*,obj/\1.o $@ : ,g' < $@.$$$$ > $@; \ 2.449 + rm -f $@.$$$$ 2.450 + 2.451 +#### 2.452 +# pull in the dependency files, but only for 'make $(TARGET)' 2.453 +#### 2.454 + 2.455 +ifeq ($(MAKECMDGOALS),$(TARGET)) 2.456 + -include $(DEPFILES) 2.457 +endif
3.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 3.2 +++ b/dep/.keepme Sat Nov 27 01:13:12 2010 +0000 3.3 @@ -0,0 +1,1 @@ 3.4 +This file is a directory-keeper. Do not delete it.
5.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 5.2 +++ b/obj/.keepme Sat Nov 27 01:13:12 2010 +0000 5.3 @@ -0,0 +1,1 @@ 5.4 +This file is a directory-keeper. Do not delete it.
7.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 7.2 +++ b/src/main.c Sat Nov 27 01:13:12 2010 +0000 7.3 @@ -0,0 +1,6 @@ 7.4 +#include <stdio.h> 7.5 + 7.6 +int main(void) 7.7 +{ 7.8 + return 0; 7.9 +}
8.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 8.2 +++ b/src/musashi/LICENSE Sat Nov 27 01:13:12 2010 +0000 8.3 @@ -0,0 +1,16 @@ 8.4 +From private email, dated 2010-Nov-26, 20:43 GMT: 8.5 + 8.6 +From: Karl Stenerud <kstenerud@gmail.com> 8.7 +Subject: Re: Musashi 68k emulator 8.8 + 8.9 +On 2010-11-26, at 12:36 PM, Philip Pemberton wrote: 8.10 + 8.11 +> > I do have one question, though more related to licensing than the core itself... 8.12 +> > 8.13 +> > I was planning to release my emulator under an open-source licence, probably the GPL or something along those lines (the worst case scenario IMO would be someone adding a ton of nice features then refusing to release the source). 8.14 +> > 8.15 +> > The "non-commercial use only" restriction in the Musashi license would seem to be at odds with the GPL, and would make it somewhat more difficult to tie in GPL-licensed libraries. Is there any possibility of getting v3.31 released under a less restrictive license, maybe GPL or LGPL? 8.16 +> > 8.17 + 8.18 +Sure, no problem. I usually release stuff under an Apache license nowadays, but feel free to pick any FOSS license. 8.19 +
9.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 9.2 +++ b/src/musashi/example/Makefile Sat Nov 27 01:13:12 2010 +0000 9.3 @@ -0,0 +1,40 @@ 9.4 +CC = gcc 9.5 +WARNINGS = -Wall -pedantic 9.6 +CFLAGS = $(WARNINGS) -c -Iobj -I. -I.. 9.7 +LFLAGS = $(WARNINGS) 9.8 + 9.9 +all: obj sim 9.10 + 9.11 +clean: 9.12 + rm -rf obj 9.13 + rm -f sim 9.14 + 9.15 +obj: 9.16 + mkdir obj 9.17 + 9.18 +sim: obj/sim.o obj/m68kcpu.o obj/m68kops.o obj/m68kopac.o obj/m68kopdm.o obj/m68kopnz.o 9.19 + $(CC) $(LFLAGS) obj/sim.o obj/m68kcpu.o obj/m68kops.o obj/m68kopac.o obj/m68kopdm.o obj/m68kopnz.o -o sim 9.20 + 9.21 +obj/sim.o: sim.c sim.h ../m68k.h ../m68kconf.h 9.22 + $(CC) $(CFLAGS) sim.c -o obj/sim.o 9.23 + 9.24 +obj/m68kcpu.o: sim.h obj/m68kops.h sim.h ../m68k.h ../m68kconf.h 9.25 + $(CC) $(CFLAGS) ../m68kcpu.c -o obj/m68kcpu.o 9.26 + 9.27 +obj/m68kops.o: obj/m68kmake obj/m68kops.h obj/m68kops.c sim.h ../m68k.h ../m68kconf.h 9.28 + $(CC) $(CFLAGS) obj/m68kops.c -o obj/m68kops.o 9.29 + 9.30 +obj/m68kopac.o: obj/m68kmake obj/m68kops.h obj/m68kopac.c sim.h ../m68k.h ../m68kconf.h 9.31 + $(CC) $(CFLAGS) obj/m68kopac.c -o obj/m68kopac.o 9.32 + 9.33 +obj/m68kopdm.o: obj/m68kmake obj/m68kops.h obj/m68kopdm.c sim.h ../m68k.h ../m68kconf.h 9.34 + $(CC) $(CFLAGS) obj/m68kopdm.c -o obj/m68kopdm.o 9.35 + 9.36 +obj/m68kopnz.o: obj/m68kmake obj/m68kops.h obj/m68kopnz.c sim.h ../m68k.h ../m68kconf.h 9.37 + $(CC) $(CFLAGS) obj/m68kopnz.c -o obj/m68kopnz.o 9.38 + 9.39 +obj/m68kops.h: obj/m68kmake 9.40 + obj/m68kmake obj ../m68k_in.c 9.41 + 9.42 +obj/m68kmake: ../m68kmake.c ../m68k_in.c 9.43 + $(CC) $(WARNINGS) ../m68kmake.c -o obj/m68kmake
10.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 10.2 +++ b/src/musashi/example/example.txt Sat Nov 27 01:13:12 2010 +0000 10.3 @@ -0,0 +1,301 @@ 10.4 +EXAMPLE: 10.5 +------- 10.6 +As an example, I'll build an imaginary hardware platform. 10.7 + 10.8 + 10.9 +The system is fairly simple, comprising of a 000, an input device, an output 10.10 +device, a non-maskable-interrupt device, and an interrupt controller. 10.11 + 10.12 + 10.13 +The input device receives input from the user and asserts its interrupt 10.14 +request line until its value is read. Reading from the input device's 10.15 +memory-mapped port will both clear its interrupt request and read an ASCII 10.16 +representation (8 bits) of what the user entered. 10.17 + 10.18 +The output device reads value when it is selected through its memory-mapped 10.19 +port and outputs it to a display. The value it reads will be interpreted as 10.20 +an ASCII value and output to the display. The output device is fairly slow 10.21 +(it can only process 1 byte per second), and so it asserts its interrupt 10.22 +request line when it is ready to receive a byte. Writing to the output device 10.23 +sends a byte to it. If the output device is not ready, the write is ignored. 10.24 +Reading from the output device returns 0 and clears its interrupt request line 10.25 +until another byte is written to it and 1 second elapses. 10.26 + 10.27 +The non-maskable-interrupt (NMI) device, as can be surmised from the name, 10.28 +generates a non-maskable-interrupt. This is connected to some kind of external 10.29 +switch that the user can push to generate a NMI. 10.30 + 10.31 +Since there are 3 devices interrupting the CPU, an interrupt controller is 10.32 +needed. The interrupt controller takes 7 inputs and encodes the highest 10.33 +priority asserted line on the 3 output pins. the input device is wired to IN2 10.34 +and the output device is wired to IN1 on the controller. The NMI device is 10.35 +wired to IN7 and all the other inputs are wired low. 10.36 + 10.37 +The bus is also connected to a 1K ROM and a 256 byte RAM. 10.38 +Beware: This platform places ROM and RAM in the same address range and uses 10.39 + the FC pins to select the correct address space! 10.40 + (You didn't expect me to make it easy, did you? =) 10.41 + 10.42 +There are two ways to handle address spaces with Musashi: 10.43 + 10.44 +1. Enable M68K_SEPARATE_READS and make handler functions for immediate and 10.45 + pc-relative reads. 10.46 + 10.47 +2. Enable M68K_EMULATE_FC and make a callback function for function code 10.48 + changes. 10.49 + 10.50 +Both methods will work in this case, but I've opted for the "more correct" 10.51 +function code pin emulation for this example. 10.52 + 10.53 + 10.54 + 10.55 +Here is the schematic in all its ASCII splendour: 10.56 +------------------------------------------------- 10.57 + 10.58 + NMI TIED 10.59 + SWITCH LOW 10.60 + | | 10.61 + | +-+-+-+ 10.62 + | | | | | +------------------------------------------------+ 10.63 + | | | | | | +------------------------------------+ | 10.64 + | | | | | | | | | 10.65 + +-------------+ | | 10.66 + |7 6 5 4 3 2 1| | | 10.67 + | | | | 10.68 + | INT CONTRLR | | | 10.69 + | | | | 10.70 + |i i i | | | 10.71 + |2 1 0 | | | 10.72 + +-------------+ | | 10.73 + | | | | | 10.74 + | | | +--------------------------------+--+ | | 10.75 + o o o | | | | | 10.76 + +--------------+ +-------+ +----------+ +---------+ +----------+ 10.77 + | I I I a | | | | | | r a i | | i | 10.78 + | 2 1 0 23 | | | | | | e c | | | 10.79 + | | | | | | | a k | | | 10.80 + | | | | | | | d | | | 10.81 + | | | | | | | | | | 10.82 + | M68000 | | ROM | | RAM | | IN | | OUT | 10.83 + | | | | | | | | | | 10.84 + | a9|--|a9 |--| |--| |--| | 10.85 + | a8|--|a8 |--| |--| |--| | 10.86 + | a7|--|a7 |--|a7 |--| |--| | 10.87 + | a6|--|a6 |--|a6 |--| |--| | 10.88 + | a5|--|a5 |--|a5 |--| |--| | 10.89 + | a4|--|a4 |--|a4 |--| |--| | 10.90 + | a3|--|a3 |--|a3 |--| |--| | 10.91 + | a2|--|a2 |--|a2 |--| |--| | 10.92 + | a1|--|a1 |--|a1 |--| |--| | 10.93 + | a0|--|a0 |--|a0 |--| |--| | 10.94 + | | | | | | | | | | 10.95 + | d15|--|d15 |--|d15 |--| |--| | 10.96 + | d14|--|d14 |--|d14 |--| |--| | 10.97 + | d13|--|d13 |--|d13 |--| |--| | 10.98 + | d12|--|d12 |--|d12 |--| |--| | 10.99 + | d11|--|d11 |--|d11 |--| |--| | 10.100 + | d10|--|d10 |--|d10 |--| |--| | 10.101 + | d9|--|d9 |--|d9 |--| |--| | 10.102 + | d8|--|d8 |--|d8 |--| |--| | 10.103 + | d7|--|d7 |--|d7 |--|d7 |--|d7 | 10.104 + | d6|--|d6 |--|d6 |--|d6 |--|d6 | 10.105 + | d5|--|d5 |--|d5 |--|d5 |--|d5 | 10.106 + | d4|--|d4 |--|d4 |--|d4 |--|d4 | 10.107 + | d3|--|d3 |--|d3 |--|d3 |--|d3 | 10.108 + | d2|--|d2 |--|d2 |--|d2 |--|d2 | 10.109 + | d1|--|d1 |--|d1 |--|d1 |--|d1 w | 10.110 + | d0|--|d0 |--|d0 |--|d0 |--|d0 r | 10.111 + | | | | | | | | | i a | 10.112 + | a F F F | | | | | | | | t c | 10.113 + |22 rW 2 1 0 | | cs | | cs rW | | | | e k | 10.114 + +--------------+ +-------+ +----------+ +---------+ +----------+ 10.115 + | | | | | | | | | | 10.116 + | | | | | | | | | | 10.117 + | | | | | +-------+ +-----+ | +---+ | 10.118 + | | | | | | IC1 | | IC2 | | |AND| | 10.119 + | | | | | |a b c d| |a b c| | +---+ | 10.120 + | | | | | +-------+ +-----+ | | | | 10.121 + | | | | | | | | | | | | | | +--+ 10.122 + | | | | | | | | | | | | | | | 10.123 + | | | | | | | | | | | | | | | 10.124 + | | | | | | | | | | | | | | | 10.125 + | | | | +-----)-)-+-)----)-)-+ | | | 10.126 + | | | +-------)-+---)----)-+ | | | 10.127 + | | +---------+-----)----+ | | | 10.128 + | | | | | | 10.129 + | +------------------+-----------+----------------------+ | 10.130 + | | 10.131 + +-----------------------------------------------------------+ 10.132 + 10.133 +IC1: output=1 if a=0 and b=1 and c=0 and d=0 10.134 +IC2: output=1 if a=0 and b=0 and c=1 10.135 + 10.136 + 10.137 + 10.138 +Here is the listing for program.bin: 10.139 +----------------------------------- 10.140 + 10.141 + INPUT_ADDRESS equ $800000 10.142 + OUTPUT_ADDRESS equ $400000 10.143 + CIRCULAR_BUFFER equ $c0 10.144 + CAN_OUTPUT equ $d0 10.145 + STACK_AREA equ $100 10.146 + 10.147 + vector_table: 10.148 +00000000 0000 0100 dc.l STACK_AREA * 0: SP 10.149 +00000004 0000 00c0 dc.l init * 1: PC 10.150 +00000008 0000 0148 dc.l unhandled_exception * 2: bus error 10.151 +0000000c 0000 0148 dc.l unhandled_exception * 3: address error 10.152 +00000010 0000 0148 dc.l unhandled_exception * 4: illegal instruction 10.153 +00000014 0000 0148 dc.l unhandled_exception * 5: zero divide 10.154 +00000018 0000 0148 dc.l unhandled_exception * 6: chk 10.155 +0000001c 0000 0148 dc.l unhandled_exception * 7: trapv 10.156 +00000020 0000 0148 dc.l unhandled_exception * 8: privilege violation 10.157 +00000024 0000 0148 dc.l unhandled_exception * 9: trace 10.158 +00000028 0000 0148 dc.l unhandled_exception * 10: 1010 10.159 +0000002c 0000 0148 dc.l unhandled_exception * 11: 1111 10.160 +00000030 0000 0148 dc.l unhandled_exception * 12: - 10.161 +00000034 0000 0148 dc.l unhandled_exception * 13: - 10.162 +00000038 0000 0148 dc.l unhandled_exception * 14: - 10.163 +0000003c 0000 0148 dc.l unhandled_exception * 15: uninitialized interrupt 10.164 +00000040 0000 0148 dc.l unhandled_exception * 16: - 10.165 +00000044 0000 0148 dc.l unhandled_exception * 17: - 10.166 +00000048 0000 0148 dc.l unhandled_exception * 18: - 10.167 +0000004c 0000 0148 dc.l unhandled_exception * 19: - 10.168 +00000050 0000 0148 dc.l unhandled_exception * 20: - 10.169 +00000054 0000 0148 dc.l unhandled_exception * 21: - 10.170 +00000058 0000 0148 dc.l unhandled_exception * 22: - 10.171 +0000005c 0000 0148 dc.l unhandled_exception * 23: - 10.172 +00000060 0000 0148 dc.l unhandled_exception * 24: spurious interrupt 10.173 +00000064 0000 0136 dc.l output_ready * 25: l1 irq 10.174 +00000068 0000 010e dc.l input_ready * 26: l2 irq 10.175 +0000006c 0000 0148 dc.l unhandled_exception * 27: l3 irq 10.176 +00000070 0000 0148 dc.l unhandled_exception * 28: l4 irq 10.177 +00000074 0000 0148 dc.l unhandled_exception * 29: l5 irq 10.178 +00000078 0000 0148 dc.l unhandled_exception * 30: l6 irq 10.179 +0000007c 0000 014e dc.l nmi * 31: l7 irq 10.180 +00000080 0000 0148 dc.l unhandled_exception * 32: trap 0 10.181 +00000084 0000 0148 dc.l unhandled_exception * 33: trap 1 10.182 +00000088 0000 0148 dc.l unhandled_exception * 34: trap 2 10.183 +0000008c 0000 0148 dc.l unhandled_exception * 35: trap 3 10.184 +00000090 0000 0148 dc.l unhandled_exception * 36: trap 4 10.185 +00000094 0000 0148 dc.l unhandled_exception * 37: trap 5 10.186 +00000098 0000 0148 dc.l unhandled_exception * 38: trap 6 10.187 +0000009c 0000 0148 dc.l unhandled_exception * 39: trap 7 10.188 +000000a0 0000 0148 dc.l unhandled_exception * 40: trap 8 10.189 +000000a4 0000 0148 dc.l unhandled_exception * 41: trap 9 10.190 +000000a8 0000 0148 dc.l unhandled_exception * 42: trap 10 10.191 +000000ac 0000 0148 dc.l unhandled_exception * 43: trap 11 10.192 +000000b0 0000 0148 dc.l unhandled_exception * 44: trap 12 10.193 +000000b4 0000 0148 dc.l unhandled_exception * 45: trap 13 10.194 +000000b8 0000 0148 dc.l unhandled_exception * 46: trap 14 10.195 +000000bc 0000 0148 dc.l unhandled_exception * 47: trap 15 10.196 + * This is the end of the useful part of the table. 10.197 + * We will now do the Capcom thing and put code starting at $c0. 10.198 + 10.199 + init: 10.200 + * Copy the exception vector table to RAM. 10.201 +000000c0 227c 0000 0000 move.l #0, a1 * a1 is RAM index 10.202 +000000c6 303c 002f move.w #47, d0 * d0 is counter (48 vectors) 10.203 +000000ca 41fa 0006 lea.l (copy_table,PC), a0 * a0 is scratch 10.204 +000000ce 2208 move.l a0, d1 * d1 is ROM index 10.205 +000000d0 4481 neg.l d1 10.206 + copy_table: 10.207 +000000d2 22fb 18fe dc.l $22fb18fe * #%#$ as68k generates 020 code here 10.208 + * move.l (copy_table,PC,d1.l), (a1)+ 10.209 +000000d6 5841 addq #4, d1 10.210 +000000d8 51c8 fff8 dbf d0, copy_table 10.211 + 10.212 + main_init: 10.213 + * Initialize main program 10.214 +000000dc 11fc 0000 00d0 move.b #0, CAN_OUTPUT 10.215 +000000e2 4df8 00c0 lea.l CIRCULAR_BUFFER, a6 10.216 +000000e6 7c00 moveq #0, d6 * output buffer ptr 10.217 +000000e8 7e00 moveq #0, d7 * input buffer ptr 10.218 +000000ea 027c f8ff andi #$f8ff, SR * clear interrupt mask 10.219 + main: 10.220 + * Main program 10.221 +000000ee 4a38 00d0 tst.b CAN_OUTPUT * can we output? 10.222 +000000f2 67fa beq main 10.223 +000000f4 be06 cmp.b d6, d7 * is there data? 10.224 +000000f6 67f6 beq main 10.225 +000000f8 11fc 0000 00d0 move.b #0, CAN_OUTPUT 10.226 +000000fe 13f6 6000 0040 move.b (0,a6,d6.w), OUTPUT_ADDRESS * write data 10.227 + 0000 10.228 +00000106 5246 addq #1, d6 10.229 +00000108 0206 000f andi.b #15, d6 * update circular buffer 10.230 +0000010c 60e0 bra main 10.231 + 10.232 + 10.233 + input_ready: 10.234 +0000010e 2f00 move.l d0, -(a7) 10.235 +00000110 2f01 move.l d1, -(a7) 10.236 +00000112 1239 0080 0000 move.b INPUT_ADDRESS, d1 * read data 10.237 +00000118 1007 move.b d7, d0 * check if buffer full 10.238 +0000011a 5240 addq #1, d0 10.239 +0000011c 0200 000f andi.b #15, d0 10.240 +00000120 bc00 cmp.b d0, d6 10.241 +00000122 6700 000c beq input_ready_quit * throw away if full 10.242 +00000126 1d81 7000 move.b d1, (0,a6,d7.w) * store the data 10.243 +0000012a 5247 addq #1, d7 10.244 +0000012c 0207 000f andi.b #15, d7 * update circular buffer 10.245 + input_ready_quit: 10.246 +00000130 221f move.l (a7)+, d1 10.247 +00000132 201f move.l (a7)+, d0 10.248 +00000134 4e73 rte 10.249 + 10.250 + output_ready: 10.251 +00000136 2f00 move.l d0, -(a7) 10.252 +00000138 11fc 0001 00d0 move.b #1, CAN_OUTPUT 10.253 +0000013e 1039 0040 0000 move.b OUTPUT_ADDRESS, d0 * acknowledge the interrupt 10.254 +00000144 201f move.l (a7)+, d0 10.255 +00000146 4e73 rte 10.256 + 10.257 + unhandled_exception: 10.258 +00000148 4e72 2700 stop #$2700 * wait for NMI 10.259 +0000014c 60fa bra unhandled_exception * shouldn't get here 10.260 + 10.261 + nmi: 10.262 + * perform a soft reset 10.263 +0000014e 46fc 2700 move #$2700, SR * set status register 10.264 +00000152 2e7a feac move.l (vector_table,PC), a7 * reset stack pointer 10.265 +00000156 4e70 reset * reset peripherals 10.266 +00000158 4efa feaa jmp (vector_table+4,PC) * reset program counter 10.267 + 10.268 + END 10.269 + 10.270 + 10.271 + 10.272 +Compiling the example host environment: 10.273 +-------------------------------------- 10.274 + 10.275 +The following assumes that you are using a GNU-based compiler such as gcc or 10.276 +djgpp for DOS (available free from www.delorie.com). 10.277 +If you are using a commercial compiler, you may have to modify the makefile 10.278 +or generate your own project file. 10.279 +Also note that part of the compilation process involves the compilation and 10.280 +invokation of the m68kmake program. 10.281 + 10.282 +- Copy the m68k files to a directory. Then copy the host environment files to 10.283 + the same directory, overwriting m68kconf.h. program.bin is the actual 68000 10.284 + program you will be running. 10.285 +- Modify osd_get_key() in sim.c to suit your environment (currently set for 10.286 + the free djgpp compiler, available from www.delorie.com, under DOS). 10.287 +- Type make 10.288 +- Perform the necessary animal sacrifices. 10.289 +- Type sim program.bin 10.290 + 10.291 + 10.292 +Keys: 10.293 + ESC - quits the simulator 10.294 + ~ - generates an NMI interrupt 10.295 + Any other key - Genearate input for the input device 10.296 + 10.297 + 10.298 +Note: I've cheated a bit in the emulation. There is no speed control 10.299 + to set the speed the CPU runs at; it simply runs as fast as your 10.300 + processor can run it. 10.301 + To add speed control, you will need a high-precision timestamp 10.302 + function (like the RDTSC instruction for newer Pentium CPUs) 10.303 + and a bit of arithmetic to make the cycles argument for m68k_execute(). 10.304 + I'll leave that as an excercise to the reader.
11.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 11.2 +++ b/src/musashi/example/history.txt Sat Nov 27 01:13:12 2010 +0000 11.3 @@ -0,0 +1,114 @@ 11.4 +The history of Musashi for anyone who might be interested: 11.5 +--------------------------------------------------------- 11.6 + 11.7 +Musashi was born out of sheer boredom. 11.8 +I needed something to code, and so having had fun with a few of the emulators 11.9 +around, I decided to try my hand at CPU emulation. 11.10 +I had owned an Amiga for many years and had done some assembly coding on it so 11.11 +I figured it would be the ideal chip to cut my teeth on. 11.12 +Had I known then how much work was involved in emulating a chip like this, I 11.13 +may not have even started ;-) 11.14 + 11.15 + 11.16 + 11.17 +12-May-1998: First outline 11.18 + 11.19 +11-Jun-1998: Early disassembler 11.20 + 11.21 +20-Nov-1998: First prototype v0.1 11.22 + 11.23 +04-Dec-1998: Final prototype v0.4 11.24 + 11.25 +20-Dec-1998: Beta release of Musashi v0.5 that could run Rastan Saga under MAME 11.26 + (barely). 11.27 + 11.28 +06-Jan-1999: Musashi 1.0 released 11.29 + 11.30 +17-Mar-1999: Musashi 2.0 released 11.31 + - Major code overhaul. 11.32 + - Replaced monolithic codebase with a code generator program. 11.33 + - Added correct m68000 timing. 11.34 + - Moved timing into the opcode handlers. 11.35 + 11.36 +25-Mar-1999: Musashi 2.1 released 11.37 + - Added support for m68010. 11.38 + - Many bugfixes. 11.39 + 11.40 +13-May-1999: Musashi 2.2 released 11.41 + - Added support for m68020. 11.42 + - Lots of bugfixes. 11.43 + 11.44 +05-Apr-2000: Musashi 3.0 released 11.45 + - Major code overhaul. 11.46 + - Rewrote code generator program and changed the format of 11.47 + m68k_in.c. 11.48 + - Added support for m68ec020. 11.49 + - Removed timing from the opcode handlers. 11.50 + - Added correct timing for m68000, m68010, and m68020. 11.51 + Note: 68020 timing is the cache timing from the manual. 11.52 + - Removed the m68k_peek_xxx() and m68k_poke_xxx() instructions and 11.53 + replaced them with m68k_get_reg() and m68k_set_reg(). 11.54 + - Added support for function codes. 11.55 + - Revamped m68kconf.h to be easier to configure and more powerful. 11.56 + - Added option to separate immediate and normal reads. 11.57 + - Added support for (undocumented) m68000 instruction prefetch. 11.58 + - Rewrote indexed addressing mode handling. 11.59 + - Rewrote interrupt handling. 11.60 + - Fixed a masking bug for m68k_get_reg() when requesting the PC. 11.61 + - Moved the instruction table sorting routine to m68kmake.c so 11.62 + that it is invoked at compile time rather than at runtime. 11.63 + - Rewrote the exception handling routines to support different 11.64 + stack frames (needed for m68020 emulation). 11.65 + - Rewrote faster status register and condition code flag handling 11.66 + functions / macros. 11.67 + - Fixed function code handling to fetch from program space when 11.68 + using pc-relative addressing. 11.69 + - Fixed initial program counter and stack pointer fetching on 11.70 + reset (loads from program space now). 11.71 + - A lot of code cleanup. 11.72 + - LOTS of bugfixes (especially in the m68020 code). 11.73 + 11.74 +28-May-2000: Musashi 3.1 released 11.75 + - Fixed bug in m68k_get_reg() that retrieved the wrong value for 11.76 + the status register. 11.77 + - Fixed register bug in movec. 11.78 + - Fixed cpu type comparison problem that caused indexed 11.79 + addressing modes to be incorrectly interpreted when in m68ec020 11.80 + mode. 11.81 + - Added code to speed up busy waiting on some branch instructions. 11.82 + - Fixed some bfxxx opcode bugs. 11.83 + 11.84 +14-Aug-2000: Musashi 3.2 released 11.85 + - Fixed RTE bug that killed the program counter when in m68020 11.86 + mode. 11.87 + - Minor fixes in negx and nbcd. 11.88 + - renamed d68k.c to m68kdasm.c and merged d68k.h into m68k.h. 11.89 + d68k_read_xxx() instructions have been renamed to 11.90 + m68k_read_xxx_disassembler(). 11.91 + - Rewrote exception processing and fixed 68020 stack frame 11.92 + problems. 11.93 + - FINALLY fixed the mull and divl instructions. 11.94 + - Added 64-bit safe code fixes. 11.95 + - Added 64-bit optimizations (these will only be ANSI compliant 11.96 + under c9x, and so to use them you must turn on M68K_USE_64_BIT 11.97 + in m68kconf.h). 11.98 + 11.99 +27-Jan-2001: Musashi 3.3 released 11.100 + Note: This is the last release of Musashi before I separate the 11.101 + 68020 core. 11.102 + - Fixed problem when displaying negative numbers in disassembler 11.103 + - Fixed cpu type selector - was allowing 020 instructions to be 11.104 + disassembled when in 000 mode. 11.105 + - Fixed opcode jumptable generator (ambiguous operators in the 11.106 + test for f-line ops) 11.107 + - Fixed signed/unsigned problem in divl and mull opcodes (not 11.108 + sure if this was causing an error but best to be sure) 11.109 + - Cleaned up the naming scheme for the opcode handlers 11.110 + 11.111 +02-Feb-2001: Musashi 3.3.1 released 11.112 + Note: due to the pc-relative requirement for some new drivers 11.113 + in MAME, I've released this small update. 11.114 + - Added pc-relative read modes 11.115 + - small optimizations to the exception handling that will help 11.116 + when splitting the cores 11.117 + - Updated the example (oops!)
12.1 Binary file src/musashi/example/program.bin has changed
13.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 13.2 +++ b/src/musashi/example/readme.txt Sat Nov 27 01:13:12 2010 +0000 13.3 @@ -0,0 +1,315 @@ 13.4 + MUSASHI 13.5 + ======= 13.6 + 13.7 + Version 3.3 13.8 + 13.9 + A portable Motorola M680x0 processor emulation engine. 13.10 + Copyright 1998-2001 Karl Stenerud. All rights reserved. 13.11 + 13.12 + 13.13 + 13.14 +INTRODUCTION: 13.15 +------------ 13.16 + 13.17 +Musashi is a Motorola 68000, 68010, 68EC020, and 68020 emulator written in C. 13.18 +This emulator was written with two goals in mind: portability and speed. 13.19 + 13.20 +The emulator is written to ANSI C specifications with the exception that I use 13.21 +inline functions. This is not compliant to the ANSI spec, but will be 13.22 +compliant to the ANSI C9X spec. 13.23 + 13.24 +It has been successfully running in the MAME project (www.mame.net) for over 2 13.25 +years and so has had time to mature. 13.26 + 13.27 + 13.28 + 13.29 +LICENSE AND COPYRIGHT: 13.30 +--------------------- 13.31 + 13.32 +The Musashi M680x0 emulator is copyright 1998-2001 Karl Stenerud. 13.33 + 13.34 +The source code included in this archive is provided AS-IS, free for any 13.35 +non-commercial purpose. 13.36 + 13.37 +If you build a program using this core, please give credit to the author. 13.38 + 13.39 +If you wish to use this core in a commercial environment, please contact 13.40 +the author to discuss commercial licensing. 13.41 + 13.42 + 13.43 + 13.44 +AVAILABILITY: 13.45 +------------ 13.46 +The latest version of this code can be obtained at: 13.47 +http://kstenerud.cjb.net 13.48 + 13.49 + 13.50 + 13.51 +CONTACTING THE AUTHOR: 13.52 +--------------------- 13.53 +I can be reached at kstenerud@mame.net 13.54 + 13.55 + 13.56 + 13.57 +BASIC CONFIGURATION: 13.58 +------------------- 13.59 +The basic configuration will give you a standard 68000 that has sufficient 13.60 +functionality to work in a primitive environment. 13.61 + 13.62 +This setup assumes that you only have 1 device interrupting it, that the 13.63 +device will always request an autovectored interrupt, and it will always clear 13.64 +the interrupt before the interrupt service routine finishes (but could 13.65 +possibly re-assert the interrupt). 13.66 +You will have only one address space, no tracing, and no instruction prefetch. 13.67 + 13.68 +To implement the basic configuration: 13.69 + 13.70 +- Open m68kconf.h and verify that the settings for INLINE and DECL_SPEC will 13.71 + work with your compiler. (They are set for gcc) 13.72 + 13.73 +- In your host program, implement the following functions: 13.74 + unsigned int m68k_read_memory_8(unsigned int address); 13.75 + unsigned int m68k_read_memory_16(unsigned int address); 13.76 + unsigned int m68k_read_memory_32(unsigned int address); 13.77 + void m68k_write_memory_8(unsigned int address, unsigned int value); 13.78 + void m68k_write_memory_16(unsigned int address, unsigned int value); 13.79 + void m68k_write_memory_32(unsigned int address, unsigned int value); 13.80 + 13.81 +- In your host program, be sure to call m68k_pulse_reset() once before calling 13.82 + any of the other functions as this initializes the core. 13.83 + 13.84 +- Use m68k_execute() to execute instructions and m68k_set_irq() to cause an 13.85 + interrupt. 13.86 + 13.87 + 13.88 + 13.89 +ADDING PROPER INTERRUPT HANDLING: 13.90 +-------------------------------- 13.91 +The interrupt handling in the basic configuration doesn't emulate the 13.92 +interrupt acknowledge phase of the CPU and automatically clears an interrupt 13.93 +request during interrupt processing. 13.94 +While this works for most systems, you may need more accurate interrupt 13.95 +handling. 13.96 + 13.97 +To add proper interrupt handling: 13.98 + 13.99 +- In m68kconf.h, set M68K_EMULATE_INT_ACK to OPT_SPECIFY_HANDLER 13.100 + 13.101 +- In m68kconf.h, set M68K_INT_ACK_CALLBACK(A) to your interrupt acknowledge 13.102 + routine 13.103 + 13.104 +- Your interrupt acknowledge routine must return an interrupt vector, 13.105 + M68K_INT_ACK_AUTOVECTOR, or M68K_INT_ACK_SPURIOUS. most m68k 13.106 + implementations just use autovectored interrupts. 13.107 + 13.108 +- When the interrupting device is satisfied, you must call m68k_set_irq(0) to 13.109 + remove the interrupt request. 13.110 + 13.111 + 13.112 + 13.113 +MULTIPLE INTERRUPTS: 13.114 +------------------- 13.115 +The above system will work if you have only one device interrupting the CPU, 13.116 +but if you have more than one device, you must do a bit more. 13.117 + 13.118 +To add multiple interrupts: 13.119 + 13.120 +- You must make an interrupt arbitration device that will take the highest 13.121 + priority interrupt and encode it onto the IRQ pins on the CPU. 13.122 + 13.123 +- The interrupt arbitration device should use m68k_set_irq() to set the 13.124 + highest pending interrupt, or 0 for no interrupts pending. 13.125 + 13.126 + 13.127 + 13.128 +SEPARATE IMMEDIATE AND PC-RELATIVE READS: 13.129 +---------------------------------------- 13.130 +You can write faster memory access functions if you know whether you are 13.131 +fetching from ROM or RAM. Immediate reads are always from the program space 13.132 +(Always in ROM unless it is running self-modifying code). 13.133 +This will also separate the pc-relative reads, since some systems treat 13.134 +PROGRAM mode reads and DATA mode reads differently (for program encryption, 13.135 +for instance). See the section below (ADDRESS SPACE) for an explanation of 13.136 +PROGRAM and DATA mode. 13.137 + 13.138 +To enable separate reads: 13.139 + 13.140 +- In m68kconf.h, turn on M68K_SEPARATE_READS. 13.141 + 13.142 +- In your host program, implement the following functions: 13.143 + unsigned int m68k_read_immediate_16(unsigned int address); 13.144 + unsigned int m68k_read_immediate_32(unsigned int address); 13.145 + 13.146 + unsigned int m68k_read_pcrelative_8(unsigned int address); 13.147 + unsigned int m68k_read_pcrelative_16(unsigned int address); 13.148 + unsigned int m68k_read_pcrelative_32(unsigned int address); 13.149 + 13.150 +- If you need to know the current PC (for banking and such), set 13.151 + M68K_MONITOR_PC to OPT_SPECIFY_HANDLER, and set M68K_SET_PC_CALLBACK(A) to 13.152 + your routine. 13.153 + 13.154 + 13.155 + 13.156 +ADDRESS SPACES: 13.157 +-------------- 13.158 +Most systems will only implement one address space, placing ROM at the lower 13.159 +addresses and RAM at the higher. However, there is the possibility that a 13.160 +system will implement ROM and RAM in the same address range, but in different 13.161 +address spaces, or will have different mamory types that require different 13.162 +handling for the program and the data. 13.163 + 13.164 +The 68k accomodates this by allowing different program spaces, the most 13.165 +important to us being PROGRAM and DATA space. Here is a breakdown of 13.166 +how information is fetched: 13.167 + 13.168 +- All immediate reads are fetched from PROGRAM space. 13.169 + 13.170 +- All PC-relative reads are fetched from PROGRAM space. 13.171 + 13.172 +- The initial stack pointer and program counter are fetched from PROGRAM space. 13.173 + 13.174 +- All other reads (except for those from the moves instruction for 68020) 13.175 + are fetched from DATA space. 13.176 + 13.177 +The m68k deals with this by encoding the requested address space on the 13.178 +function code pins: 13.179 + 13.180 + FC 13.181 + Address Space 210 13.182 + ------------------ --- 13.183 + USER DATA 001 13.184 + USER PROGRAM 010 13.185 + SUPERVISOR DATA 101 13.186 + SUPERVISOR PROGRAM 110 13.187 + CPU SPACE 111 <-- not emulated in this core since we emulate 13.188 + interrupt acknowledge in another way. 13.189 + 13.190 +Problems arise here if you need to emulate this distinction (if, for example, 13.191 +your ROM and RAM are at the same address range, with RAM and ROM enable 13.192 +wired to the function code pins). 13.193 + 13.194 +There are 2 ways to deal with this situation using Musashi: 13.195 + 13.196 +1. If you only need the distinction between PROGRAM and DATA (the most common), 13.197 + you can just separate the reads (see the preceeding section). This is the 13.198 + faster solution. 13.199 + 13.200 +2. You can emulate the function code pins entirely. 13.201 + 13.202 +To emulate the function code pins: 13.203 + 13.204 +- In m68kconf.h, set M68K_EMULATE_FC to OPT_SPECIFY_HANDLER and set 13.205 + M68K_SET_FC_CALLBACK(A) to your function code handler function. 13.206 + 13.207 +- Your function code handler should select the proper address space for 13.208 + subsequent calls to m68k_read_xx (and m68k_write_xx for 68010+). 13.209 + 13.210 +Note: immediate reads are always done from program space, so technically you 13.211 + don't need to implement the separate immediate reads, although you could 13.212 + gain more speed improvements leaving them in and doing some clever 13.213 + programming. 13.214 + 13.215 + 13.216 + 13.217 +USING DIFFERENT CPU TYPES: 13.218 +------------------------- 13.219 +The default is to enable only the 68000 cpu type. To change this, change the 13.220 +settings for M68K_EMULATE_010 etc in m68kconf.h. 13.221 + 13.222 +To set the CPU type you want to use: 13.223 + 13.224 +- Make sure it is enabled in m68kconf.h. Current switches are: 13.225 + M68K_EMULATE_010 13.226 + M68K_EMULATE_EC020 13.227 + M68K_EMULATE_020 13.228 + 13.229 +- In your host program, call m68k_set_cpu_type() and then call 13.230 + m68k_pulse_reset(). Valid CPU types are: 13.231 + M68K_CPU_TYPE_68000, 13.232 + M68K_CPU_TYPE_68010, 13.233 + M68K_CPU_TYPE_68EC020, 13.234 + M68K_CPU_TYPE_68020 13.235 + 13.236 + 13.237 + 13.238 +CLOCK FREQUENCY: 13.239 +--------------- 13.240 +In order to emulate the correct clock frequency, you will have to calculate 13.241 +how long it takes the emulation to execute a certain number of "cycles" and 13.242 +vary your calls to m68k_execute() accordingly. 13.243 +As well, it is a good idea to take away the CPU's timeslice when it writes to 13.244 +a memory-mapped port in order to give the device it wrote to a chance to 13.245 +react. 13.246 + 13.247 +You can use the functions m68k_cycles_run(), m68k_cycles_remaining(), 13.248 +m68k_modify_timeslice(), and m68k_end_timeslice() to do this. 13.249 +Try to use large cycle values in your calls to m68k_execute() since it will 13.250 +increase throughput. You can always take away the timeslice later. 13.251 + 13.252 + 13.253 + 13.254 +MORE CORRECT EMULATION: 13.255 +---------------------- 13.256 +You may need to enable these in order to properly emulate some of the more 13.257 +obscure functions of the m68k: 13.258 + 13.259 +- M68K_EMULATE_BKPT_ACK causes the CPU to call a breakpoint handler on a BKPT 13.260 + instruction 13.261 + 13.262 +- M68K_EMULATE_TRACE causes the CPU to generate trace exceptions when the 13.263 + trace bits are set 13.264 + 13.265 +- M68K_EMULATE_RESET causes the CPU to call a reset handler on a RESET 13.266 + instruction. 13.267 + 13.268 +- M68K_EMULATE_PREFETCH emulates the 4-word instruction prefetch that is part 13.269 + of the 68000/68010 (needed for Amiga emulation). 13.270 + 13.271 +- call m68k_pulse_halt() to emulate the HALT pin. 13.272 + 13.273 + 13.274 + 13.275 +CONVENIENCE FUNCTIONS: 13.276 +--------------------- 13.277 +These are in here for programmer convenience: 13.278 + 13.279 +- M68K_INSTRUCTION_HOOK lets you call a handler before each instruction. 13.280 + 13.281 +- M68K_LOG_ENABLE and M68K_LOG_1010_1111 lets you log illegal and A/F-line 13.282 + instructions. 13.283 + 13.284 + 13.285 + 13.286 +MULTIPLE CPU EMULATION: 13.287 +---------------------- 13.288 +The default is to use only one CPU. To use more than one CPU in this core, 13.289 +there are some things to keep in mind: 13.290 + 13.291 +- To have different cpus call different functions, use OPT_ON instead of 13.292 + OPT_SPECIFY_HANDLER, and use the m68k_set_xxx_callback() functions to set 13.293 + your callback handlers on a per-cpu basis. 13.294 + 13.295 +- Be sure to call set_cpu_type() for each CPU you use. 13.296 + 13.297 +- Use m68k_set_context() and m68k_get_context() to switch to another CPU. 13.298 + 13.299 + 13.300 + 13.301 +LOAD AND SAVE CPU CONTEXTS FROM DISK: 13.302 +------------------------------------ 13.303 +You can use them68k_load_context() and m68k_save_context() functions to load 13.304 +and save the CPU state to disk. 13.305 + 13.306 + 13.307 + 13.308 +GET/SET INFORMATION FROM THE CPU: 13.309 +-------------------------------- 13.310 +You can use m68k_get_reg() and m68k_set_reg() to gain access to the internals 13.311 +of the CPU. 13.312 + 13.313 + 13.314 + 13.315 +EXAMPLE: 13.316 +------- 13.317 + 13.318 +I have included a file example.zip that contains a full example.
14.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 14.2 +++ b/src/musashi/example/sim.c Sat Nov 27 01:13:12 2010 +0000 14.3 @@ -0,0 +1,478 @@ 14.4 +#include <stdio.h> 14.5 +#include <stdlib.h> 14.6 +#include <stdarg.h> 14.7 +#include <time.h> 14.8 +#include "sim.h" 14.9 +#include "m68k.h" 14.10 + 14.11 +/* Memory-mapped IO ports */ 14.12 +#define INPUT_ADDRESS 0x800000 14.13 +#define OUTPUT_ADDRESS 0x400000 14.14 + 14.15 +/* IRQ connections */ 14.16 +#define IRQ_NMI_DEVICE 7 14.17 +#define IRQ_INPUT_DEVICE 2 14.18 +#define IRQ_OUTPUT_DEVICE 1 14.19 + 14.20 +/* Time between characters sent to output device (seconds) */ 14.21 +#define OUTPUT_DEVICE_PERIOD 1 14.22 + 14.23 +/* ROM and RAM sizes */ 14.24 +#define MAX_ROM 0xfff 14.25 +#define MAX_RAM 0xff 14.26 + 14.27 + 14.28 +/* Read/write macros */ 14.29 +#define READ_BYTE(BASE, ADDR) (BASE)[ADDR] 14.30 +#define READ_WORD(BASE, ADDR) (((BASE)[ADDR]<<8) | \ 14.31 + (BASE)[(ADDR)+1]) 14.32 +#define READ_LONG(BASE, ADDR) (((BASE)[ADDR]<<24) | \ 14.33 + ((BASE)[(ADDR)+1]<<16) | \ 14.34 + ((BASE)[(ADDR)+2]<<8) | \ 14.35 + (BASE)[(ADDR)+3]) 14.36 + 14.37 +#define WRITE_BYTE(BASE, ADDR, VAL) (BASE)[ADDR] = (VAL)%0xff 14.38 +#define WRITE_WORD(BASE, ADDR, VAL) (BASE)[ADDR] = ((VAL)>>8) & 0xff; \ 14.39 + (BASE)[(ADDR)+1] = (VAL)&0xff 14.40 +#define WRITE_LONG(BASE, ADDR, VAL) (BASE)[ADDR] = ((VAL)>>24) & 0xff; \ 14.41 + (BASE)[(ADDR)+1] = ((VAL)>>16)&0xff; \ 14.42 + (BASE)[(ADDR)+2] = ((VAL)>>8)&0xff; \ 14.43 + (BASE)[(ADDR)+3] = (VAL)&0xff 14.44 + 14.45 + 14.46 +/* Prototypes */ 14.47 +void exit_error(char* fmt, ...); 14.48 +int osd_get_char(void); 14.49 + 14.50 +unsigned int m68k_read_memory_8(unsigned int address); 14.51 +unsigned int m68k_read_memory_16(unsigned int address); 14.52 +unsigned int m68k_read_memory_32(unsigned int address); 14.53 +void m68k_write_memory_8(unsigned int address, unsigned int value); 14.54 +void m68k_write_memory_16(unsigned int address, unsigned int value); 14.55 +void m68k_write_memory_32(unsigned int address, unsigned int value); 14.56 +void cpu_pulse_reset(void); 14.57 +void cpu_set_fc(unsigned int fc); 14.58 +int cpu_irq_ack(int level); 14.59 + 14.60 +void nmi_device_reset(void); 14.61 +void nmi_device_update(void); 14.62 +int nmi_device_ack(void); 14.63 + 14.64 +void input_device_reset(void); 14.65 +void input_device_update(void); 14.66 +int input_device_ack(void); 14.67 +unsigned int input_device_read(void); 14.68 +void input_device_write(unsigned int value); 14.69 + 14.70 +void output_device_reset(void); 14.71 +void output_device_update(void); 14.72 +int output_device_ack(void); 14.73 +unsigned int output_device_read(void); 14.74 +void output_device_write(unsigned int value); 14.75 + 14.76 +void int_controller_set(unsigned int value); 14.77 +void int_controller_clear(unsigned int value); 14.78 + 14.79 +void get_user_input(void); 14.80 + 14.81 + 14.82 +/* Data */ 14.83 +unsigned int g_quit = 0; /* 1 if we want to quit */ 14.84 +unsigned int g_nmi = 0; /* 1 if nmi pending */ 14.85 + 14.86 +int g_input_device_value = -1; /* Current value in input device */ 14.87 + 14.88 +unsigned int g_output_device_ready = 0; /* 1 if output device is ready */ 14.89 +time_t g_output_device_last_output; /* Time of last char output */ 14.90 + 14.91 +unsigned int g_int_controller_pending = 0; /* list of pending interrupts */ 14.92 +unsigned int g_int_controller_highest_int = 0; /* Highest pending interrupt */ 14.93 + 14.94 +unsigned char g_rom[MAX_ROM+1]; /* ROM */ 14.95 +unsigned char g_ram[MAX_RAM+1]; /* RAM */ 14.96 +unsigned int g_fc; /* Current function code from CPU */ 14.97 + 14.98 + 14.99 +/* Exit with an error message. Use printf syntax. */ 14.100 +void exit_error(char* fmt, ...) 14.101 +{ 14.102 + va_list args; 14.103 + va_start(args, fmt); 14.104 + vfprintf(stderr, fmt, args); 14.105 + va_end(args); 14.106 + fprintf(stderr, "\n"); 14.107 + 14.108 + exit(EXIT_FAILURE); 14.109 +} 14.110 + 14.111 +/* OS-dependant code to get a character from the user. 14.112 + * This function must not block, and must either return an ASCII code or -1. 14.113 + */ 14.114 +//#include <conio.h> 14.115 +int osd_get_char(void) 14.116 +{ 14.117 + int ch = -1; 14.118 +/* if(kbhit()) 14.119 + { 14.120 + while(kbhit()) 14.121 + ch = getch(); 14.122 + } 14.123 +*/ return ch; 14.124 +} 14.125 + 14.126 + 14.127 +/* Read data from RAM, ROM, or a device */ 14.128 +unsigned int m68k_read_memory_8(unsigned int address) 14.129 +{ 14.130 + if(g_fc & 2) /* Program */ 14.131 + { 14.132 + if(address > MAX_ROM) 14.133 + exit_error("Attempted to read byte from ROM address %08x", address); 14.134 + return READ_BYTE(g_rom, address); 14.135 + } 14.136 + 14.137 + /* Otherwise it's data space */ 14.138 + switch(address) 14.139 + { 14.140 + case INPUT_ADDRESS: 14.141 + return input_device_read(); 14.142 + case OUTPUT_ADDRESS: 14.143 + return output_device_read(); 14.144 + default: 14.145 + break; 14.146 + } 14.147 + if(address > MAX_RAM) 14.148 + exit_error("Attempted to read byte from RAM address %08x", address); 14.149 + return READ_BYTE(g_ram, address); 14.150 +} 14.151 + 14.152 +unsigned int m68k_read_memory_16(unsigned int address) 14.153 +{ 14.154 + if(g_fc & 2) /* Program */ 14.155 + { 14.156 + if(address > MAX_ROM) 14.157 + exit_error("Attempted to read word from ROM address %08x", address); 14.158 + return READ_WORD(g_rom, address); 14.159 + } 14.160 + 14.161 + /* Otherwise it's data space */ 14.162 + switch(address) 14.163 + { 14.164 + case INPUT_ADDRESS: 14.165 + return input_device_read(); 14.166 + case OUTPUT_ADDRESS: 14.167 + return output_device_read(); 14.168 + default: 14.169 + break; 14.170 + } 14.171 + if(address > MAX_RAM) 14.172 + exit_error("Attempted to read word from RAM address %08x", address); 14.173 + return READ_WORD(g_ram, address); 14.174 +} 14.175 + 14.176 +unsigned int m68k_read_memory_32(unsigned int address) 14.177 +{ 14.178 + if(g_fc & 2) /* Program */ 14.179 + { 14.180 + if(address > MAX_ROM) 14.181 + exit_error("Attempted to read long from ROM address %08x", address); 14.182 + return READ_LONG(g_rom, address); 14.183 + } 14.184 + 14.185 + /* Otherwise it's data space */ 14.186 + switch(address) 14.187 + { 14.188 + case INPUT_ADDRESS: 14.189 + return input_device_read(); 14.190 + case OUTPUT_ADDRESS: 14.191 + return output_device_read(); 14.192 + default: 14.193 + break; 14.194 + } 14.195 + if(address > MAX_RAM) 14.196 + exit_error("Attempted to read long from RAM address %08x", address); 14.197 + return READ_LONG(g_ram, address); 14.198 +} 14.199 + 14.200 + 14.201 +/* Write data to RAM or a device */ 14.202 +void m68k_write_memory_8(unsigned int address, unsigned int value) 14.203 +{ 14.204 + if(g_fc & 2) /* Program */ 14.205 + exit_error("Attempted to write %02x to ROM address %08x", value&0xff, address); 14.206 + 14.207 + /* Otherwise it's data space */ 14.208 + switch(address) 14.209 + { 14.210 + case INPUT_ADDRESS: 14.211 + input_device_write(value&0xff); 14.212 + return; 14.213 + case OUTPUT_ADDRESS: 14.214 + output_device_write(value&0xff); 14.215 + return; 14.216 + default: 14.217 + break; 14.218 + } 14.219 + if(address > MAX_RAM) 14.220 + exit_error("Attempted to write %02x to RAM address %08x", value&0xff, address); 14.221 + WRITE_BYTE(g_ram, address, value); 14.222 +} 14.223 + 14.224 +void m68k_write_memory_16(unsigned int address, unsigned int value) 14.225 +{ 14.226 + if(g_fc & 2) /* Program */ 14.227 + exit_error("Attempted to write %04x to ROM address %08x", value&0xffff, address); 14.228 + 14.229 + /* Otherwise it's data space */ 14.230 + switch(address) 14.231 + { 14.232 + case INPUT_ADDRESS: 14.233 + input_device_write(value&0xffff); 14.234 + return; 14.235 + case OUTPUT_ADDRESS: 14.236 + output_device_write(value&0xffff); 14.237 + return; 14.238 + default: 14.239 + break; 14.240 + } 14.241 + if(address > MAX_RAM) 14.242 + exit_error("Attempted to write %04x to RAM address %08x", value&0xffff, address); 14.243 + WRITE_WORD(g_ram, address, value); 14.244 +} 14.245 + 14.246 +void m68k_write_memory_32(unsigned int address, unsigned int value) 14.247 +{ 14.248 + if(g_fc & 2) /* Program */ 14.249 + exit_error("Attempted to write %08x to ROM address %08x", value, address); 14.250 + 14.251 + /* Otherwise it's data space */ 14.252 + switch(address) 14.253 + { 14.254 + case INPUT_ADDRESS: 14.255 + input_device_write(value); 14.256 + return; 14.257 + case OUTPUT_ADDRESS: 14.258 + output_device_write(value); 14.259 + return; 14.260 + default: 14.261 + break; 14.262 + } 14.263 + if(address > MAX_RAM) 14.264 + exit_error("Attempted to write %08x to RAM address %08x", value, address); 14.265 + WRITE_LONG(g_ram, address, value); 14.266 +} 14.267 + 14.268 +/* Called when the CPU pulses the RESET line */ 14.269 +void cpu_pulse_reset(void) 14.270 +{ 14.271 + nmi_device_reset(); 14.272 + output_device_reset(); 14.273 + input_device_reset(); 14.274 +} 14.275 + 14.276 +/* Called when the CPU changes the function code pins */ 14.277 +void cpu_set_fc(unsigned int fc) 14.278 +{ 14.279 + g_fc = fc; 14.280 +} 14.281 + 14.282 +/* Called when the CPU acknowledges an interrupt */ 14.283 +int cpu_irq_ack(int level) 14.284 +{ 14.285 + switch(level) 14.286 + { 14.287 + case IRQ_NMI_DEVICE: 14.288 + return nmi_device_ack(); 14.289 + case IRQ_INPUT_DEVICE: 14.290 + return input_device_ack(); 14.291 + case IRQ_OUTPUT_DEVICE: 14.292 + return output_device_ack(); 14.293 + } 14.294 + return M68K_INT_ACK_SPURIOUS; 14.295 +} 14.296 + 14.297 + 14.298 + 14.299 + 14.300 +/* Implementation for the NMI device */ 14.301 +void nmi_device_reset(void) 14.302 +{ 14.303 + g_nmi = 0; 14.304 +} 14.305 + 14.306 +void nmi_device_update(void) 14.307 +{ 14.308 + if(g_nmi) 14.309 + { 14.310 + g_nmi = 0; 14.311 + int_controller_set(IRQ_NMI_DEVICE); 14.312 + } 14.313 +} 14.314 + 14.315 +int nmi_device_ack(void) 14.316 +{ 14.317 + printf("\nNMI\n");fflush(stdout); 14.318 + int_controller_clear(IRQ_NMI_DEVICE); 14.319 + return M68K_INT_ACK_AUTOVECTOR; 14.320 +} 14.321 + 14.322 + 14.323 +/* Implementation for the input device */ 14.324 +void input_device_reset(void) 14.325 +{ 14.326 + g_input_device_value = -1; 14.327 + int_controller_clear(IRQ_INPUT_DEVICE); 14.328 +} 14.329 + 14.330 +void input_device_update(void) 14.331 +{ 14.332 + if(g_input_device_value >= 0) 14.333 + int_controller_set(IRQ_INPUT_DEVICE); 14.334 +} 14.335 + 14.336 +int input_device_ack(void) 14.337 +{ 14.338 + return M68K_INT_ACK_AUTOVECTOR; 14.339 +} 14.340 + 14.341 +unsigned int input_device_read(void) 14.342 +{ 14.343 + int value = g_input_device_value > 0 ? g_input_device_value : 0; 14.344 + int_controller_clear(IRQ_INPUT_DEVICE); 14.345 + g_input_device_value = -1; 14.346 + return value; 14.347 +} 14.348 + 14.349 +void input_device_write(unsigned int value) 14.350 +{ 14.351 +} 14.352 + 14.353 + 14.354 +/* Implementation for the output device */ 14.355 +void output_device_reset(void) 14.356 +{ 14.357 + g_output_device_last_output = time(NULL); 14.358 + g_output_device_ready = 0; 14.359 + int_controller_clear(IRQ_OUTPUT_DEVICE); 14.360 +} 14.361 + 14.362 +void output_device_update(void) 14.363 +{ 14.364 + if(!g_output_device_ready) 14.365 + { 14.366 + if((time(NULL) - g_output_device_last_output) >= OUTPUT_DEVICE_PERIOD) 14.367 + { 14.368 + g_output_device_ready = 1; 14.369 + int_controller_set(IRQ_OUTPUT_DEVICE); 14.370 + } 14.371 + } 14.372 +} 14.373 + 14.374 +int output_device_ack(void) 14.375 +{ 14.376 + return M68K_INT_ACK_AUTOVECTOR; 14.377 +} 14.378 + 14.379 +unsigned int output_device_read(void) 14.380 +{ 14.381 + int_controller_clear(IRQ_OUTPUT_DEVICE); 14.382 + return 0; 14.383 +} 14.384 + 14.385 +void output_device_write(unsigned int value) 14.386 +{ 14.387 + char ch; 14.388 + if(g_output_device_ready) 14.389 + { 14.390 + ch = value & 0xff; 14.391 + printf("%c", ch); 14.392 + g_output_device_last_output = time(NULL); 14.393 + g_output_device_ready = 0; 14.394 + int_controller_clear(IRQ_OUTPUT_DEVICE); 14.395 + } 14.396 +} 14.397 + 14.398 + 14.399 +/* Implementation for the interrupt controller */ 14.400 +void int_controller_set(unsigned int value) 14.401 +{ 14.402 + unsigned int old_pending = g_int_controller_pending; 14.403 + 14.404 + g_int_controller_pending |= (1<<value); 14.405 + 14.406 + if(old_pending != g_int_controller_pending && value > g_int_controller_highest_int) 14.407 + { 14.408 + g_int_controller_highest_int = value; 14.409 + m68k_set_irq(g_int_controller_highest_int); 14.410 + } 14.411 +} 14.412 + 14.413 +void int_controller_clear(unsigned int value) 14.414 +{ 14.415 + g_int_controller_pending &= ~(1<<value); 14.416 + 14.417 + for(g_int_controller_highest_int = 7;g_int_controller_highest_int > 0;g_int_controller_highest_int--) 14.418 + if(g_int_controller_pending & (1<<g_int_controller_highest_int)) 14.419 + break; 14.420 + 14.421 + m68k_set_irq(g_int_controller_highest_int); 14.422 +} 14.423 + 14.424 + 14.425 +/* Parse user input and update any devices that need user input */ 14.426 +void get_user_input(void) 14.427 +{ 14.428 + static int last_ch = -1; 14.429 + int ch = osd_get_char(); 14.430 + 14.431 + if(ch >= 0) 14.432 + { 14.433 + switch(ch) 14.434 + { 14.435 + case 0x1b: 14.436 + g_quit = 1; 14.437 + break; 14.438 + case '~': 14.439 + if(last_ch != ch) 14.440 + g_nmi = 1; 14.441 + break; 14.442 + default: 14.443 + g_input_device_value = ch; 14.444 + } 14.445 + } 14.446 + last_ch = ch; 14.447 +} 14.448 + 14.449 + 14.450 +/* The main loop */ 14.451 +int main(int argc, char* argv[]) 14.452 +{ 14.453 + FILE* fhandle; 14.454 + 14.455 + if(argc != 2) 14.456 + exit_error("Usage: sim <program file>"); 14.457 + 14.458 + if((fhandle = fopen(argv[1], "rb")) == NULL) 14.459 + exit_error("Unable to open %s", argv[1]); 14.460 + 14.461 + if(fread(g_rom, 1, MAX_ROM+1, fhandle) <= 0) 14.462 + exit_error("Error reading %s", argv[1]); 14.463 + 14.464 + 14.465 + m68k_pulse_reset(); 14.466 + input_device_reset(); 14.467 + output_device_reset(); 14.468 + nmi_device_reset(); 14.469 + 14.470 + g_quit = 0; 14.471 + while(!g_quit) 14.472 + { 14.473 + get_user_input(); 14.474 + /* Note that I am not emulating the correct clock speed! */ 14.475 + m68k_execute(1000); 14.476 + output_device_update(); 14.477 + input_device_update(); 14.478 + nmi_device_update(); 14.479 + } 14.480 + return 0; 14.481 +}
15.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 15.2 +++ b/src/musashi/example/sim.h Sat Nov 27 01:13:12 2010 +0000 15.3 @@ -0,0 +1,14 @@ 15.4 +#ifndef SIM__HEADER 15.5 +#define SIM__HEADER 15.6 + 15.7 +unsigned int m68k_read_memory_8(unsigned int address); 15.8 +unsigned int m68k_read_memory_16(unsigned int address); 15.9 +unsigned int m68k_read_memory_32(unsigned int address); 15.10 +void m68k_write_memory_8(unsigned int address, unsigned int value); 15.11 +void m68k_write_memory_16(unsigned int address, unsigned int value); 15.12 +void m68k_write_memory_32(unsigned int address, unsigned int value); 15.13 +void cpu_pulse_reset(void); 15.14 +void cpu_set_fc(unsigned int fc); 15.15 +int cpu_irq_ack(int level); 15.16 + 15.17 +#endif /* SIM__HEADER */
16.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 16.2 +++ b/src/musashi/history.txt Sat Nov 27 01:13:12 2010 +0000 16.3 @@ -0,0 +1,114 @@ 16.4 +The history of Musashi for anyone who might be interested: 16.5 +--------------------------------------------------------- 16.6 + 16.7 +Musashi was born out of sheer boredom. 16.8 +I needed something to code, and so having had fun with a few of the emulators 16.9 +around, I decided to try my hand at CPU emulation. 16.10 +I had owned an Amiga for many years and had done some assembly coding on it so 16.11 +I figured it would be the ideal chip to cut my teeth on. 16.12 +Had I known then how much work was involved in emulating a chip like this, I 16.13 +may not have even started ;-) 16.14 + 16.15 + 16.16 + 16.17 +12-May-1998: First outline 16.18 + 16.19 +11-Jun-1998: Early disassembler 16.20 + 16.21 +20-Nov-1998: First prototype v0.1 16.22 + 16.23 +04-Dec-1998: Final prototype v0.4 16.24 + 16.25 +20-Dec-1998: Beta release of Musashi v0.5 that could run Rastan Saga under MAME 16.26 + (barely). 16.27 + 16.28 +06-Jan-1999: Musashi 1.0 released 16.29 + 16.30 +17-Mar-1999: Musashi 2.0 released 16.31 + - Major code overhaul. 16.32 + - Replaced monolithic codebase with a code generator program. 16.33 + - Added correct m68000 timing. 16.34 + - Moved timing into the opcode handlers. 16.35 + 16.36 +25-Mar-1999: Musashi 2.1 released 16.37 + - Added support for m68010. 16.38 + - Many bugfixes. 16.39 + 16.40 +13-May-1999: Musashi 2.2 released 16.41 + - Added support for m68020. 16.42 + - Lots of bugfixes. 16.43 + 16.44 +05-Apr-2000: Musashi 3.0 released 16.45 + - Major code overhaul. 16.46 + - Rewrote code generator program and changed the format of 16.47 + m68k_in.c. 16.48 + - Added support for m68ec020. 16.49 + - Removed timing from the opcode handlers. 16.50 + - Added correct timing for m68000, m68010, and m68020. 16.51 + Note: 68020 timing is the cache timing from the manual. 16.52 + - Removed the m68k_peek_xxx() and m68k_poke_xxx() instructions and 16.53 + replaced them with m68k_get_reg() and m68k_set_reg(). 16.54 + - Added support for function codes. 16.55 + - Revamped m68kconf.h to be easier to configure and more powerful. 16.56 + - Added option to separate immediate and normal reads. 16.57 + - Added support for (undocumented) m68000 instruction prefetch. 16.58 + - Rewrote indexed addressing mode handling. 16.59 + - Rewrote interrupt handling. 16.60 + - Fixed a masking bug for m68k_get_reg() when requesting the PC. 16.61 + - Moved the instruction table sorting routine to m68kmake.c so 16.62 + that it is invoked at compile time rather than at runtime. 16.63 + - Rewrote the exception handling routines to support different 16.64 + stack frames (needed for m68020 emulation). 16.65 + - Rewrote faster status register and condition code flag handling 16.66 + functions / macros. 16.67 + - Fixed function code handling to fetch from program space when 16.68 + using pc-relative addressing. 16.69 + - Fixed initial program counter and stack pointer fetching on 16.70 + reset (loads from program space now). 16.71 + - A lot of code cleanup. 16.72 + - LOTS of bugfixes (especially in the m68020 code). 16.73 + 16.74 +28-May-2000: Musashi 3.1 released 16.75 + - Fixed bug in m68k_get_reg() that retrieved the wrong value for 16.76 + the status register. 16.77 + - Fixed register bug in movec. 16.78 + - Fixed cpu type comparison problem that caused indexed 16.79 + addressing modes to be incorrectly interpreted when in m68ec020 16.80 + mode. 16.81 + - Added code to speed up busy waiting on some branch instructions. 16.82 + - Fixed some bfxxx opcode bugs. 16.83 + 16.84 +14-Aug-2000: Musashi 3.2 released 16.85 + - Fixed RTE bug that killed the program counter when in m68020 16.86 + mode. 16.87 + - Minor fixes in negx and nbcd. 16.88 + - renamed d68k.c to m68kdasm.c and merged d68k.h into m68k.h. 16.89 + d68k_read_xxx() instructions have been renamed to 16.90 + m68k_read_xxx_disassembler(). 16.91 + - Rewrote exception processing and fixed 68020 stack frame 16.92 + problems. 16.93 + - FINALLY fixed the mull and divl instructions. 16.94 + - Added 64-bit safe code fixes. 16.95 + - Added 64-bit optimizations (these will only be ANSI compliant 16.96 + under c9x, and so to use them you must turn on M68K_USE_64_BIT 16.97 + in m68kconf.h). 16.98 + 16.99 +27-Jan-2001: Musashi 3.3 released 16.100 + Note: This is the last release of Musashi before I separate the 16.101 + 68020 core. 16.102 + - Fixed problem when displaying negative numbers in disassembler 16.103 + - Fixed cpu type selector - was allowing 020 instructions to be 16.104 + disassembled when in 000 mode. 16.105 + - Fixed opcode jumptable generator (ambiguous operators in the 16.106 + test for f-line ops) 16.107 + - Fixed signed/unsigned problem in divl and mull opcodes (not 16.108 + sure if this was causing an error but best to be sure) 16.109 + - Cleaned up the naming scheme for the opcode handlers 16.110 + 16.111 +02-Feb-2001: Musashi 3.3.1 released 16.112 + Note: due to the pc-relative requirement for some new drivers 16.113 + in MAME, I've released this small update. 16.114 + - Added pc-relative read modes 16.115 + - small optimizations to the exception handling that will help 16.116 + when splitting the cores 16.117 + - Updated the example (oops!)
17.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 17.2 +++ b/src/musashi/m68k.h Sat Nov 27 01:13:12 2010 +0000 17.3 @@ -0,0 +1,339 @@ 17.4 +#ifndef M68K__HEADER 17.5 +#define M68K__HEADER 17.6 + 17.7 +/* ======================================================================== */ 17.8 +/* ========================= LICENSING & COPYRIGHT ======================== */ 17.9 +/* ======================================================================== */ 17.10 +/* 17.11 + * MUSASHI 17.12 + * Version 3.3 17.13 + * 17.14 + * A portable Motorola M680x0 processor emulation engine. 17.15 + * Copyright 1998-2001 Karl Stenerud. All rights reserved. 17.16 + * 17.17 + * This code may be freely used for non-commercial purposes as long as this 17.18 + * copyright notice remains unaltered in the source code and any binary files 17.19 + * containing this code in compiled form. 17.20 + * 17.21 + * All other lisencing terms must be negotiated with the author 17.22 + * (Karl Stenerud). 17.23 + * 17.24 + * The latest version of this code can be obtained at: 17.25 + * http://kstenerud.cjb.net 17.26 + */ 17.27 + 17.28 + 17.29 + 17.30 +/* ======================================================================== */ 17.31 +/* ============================ GENERAL DEFINES =========================== */ 17.32 + 17.33 +/* ======================================================================== */ 17.34 + 17.35 +/* There are 7 levels of interrupt to the 68K. 17.36 + * A transition from < 7 to 7 will cause a non-maskable interrupt (NMI). 17.37 + */ 17.38 +#define M68K_IRQ_NONE 0 17.39 +#define M68K_IRQ_1 1 17.40 +#define M68K_IRQ_2 2 17.41 +#define M68K_IRQ_3 3 17.42 +#define M68K_IRQ_4 4 17.43 +#define M68K_IRQ_5 5 17.44 +#define M68K_IRQ_6 6 17.45 +#define M68K_IRQ_7 7 17.46 + 17.47 + 17.48 +/* Special interrupt acknowledge values. 17.49 + * Use these as special returns from the interrupt acknowledge callback 17.50 + * (specified later in this header). 17.51 + */ 17.52 + 17.53 +/* Causes an interrupt autovector (0x18 + interrupt level) to be taken. 17.54 + * This happens in a real 68K if VPA or AVEC is asserted during an interrupt 17.55 + * acknowledge cycle instead of DTACK. 17.56 + */ 17.57 +#define M68K_INT_ACK_AUTOVECTOR 0xffffffff 17.58 + 17.59 +/* Causes the spurious interrupt vector (0x18) to be taken 17.60 + * This happens in a real 68K if BERR is asserted during the interrupt 17.61 + * acknowledge cycle (i.e. no devices responded to the acknowledge). 17.62 + */ 17.63 +#define M68K_INT_ACK_SPURIOUS 0xfffffffe 17.64 + 17.65 + 17.66 +/* CPU types for use in m68k_set_cpu_type() */ 17.67 +enum 17.68 +{ 17.69 + M68K_CPU_TYPE_INVALID, 17.70 + M68K_CPU_TYPE_68000, 17.71 + M68K_CPU_TYPE_68010, 17.72 + M68K_CPU_TYPE_68EC020, 17.73 + M68K_CPU_TYPE_68020, 17.74 + M68K_CPU_TYPE_68030, /* Supported by disassembler ONLY */ 17.75 + M68K_CPU_TYPE_68040 /* Supported by disassembler ONLY */ 17.76 +}; 17.77 + 17.78 +/* Registers used by m68k_get_reg() and m68k_set_reg() */ 17.79 +typedef enum 17.80 +{ 17.81 + /* Real registers */ 17.82 + M68K_REG_D0, /* Data registers */ 17.83 + M68K_REG_D1, 17.84 + M68K_REG_D2, 17.85 + M68K_REG_D3, 17.86 + M68K_REG_D4, 17.87 + M68K_REG_D5, 17.88 + M68K_REG_D6, 17.89 + M68K_REG_D7, 17.90 + M68K_REG_A0, /* Address registers */ 17.91 + M68K_REG_A1, 17.92 + M68K_REG_A2, 17.93 + M68K_REG_A3, 17.94 + M68K_REG_A4, 17.95 + M68K_REG_A5, 17.96 + M68K_REG_A6, 17.97 + M68K_REG_A7, 17.98 + M68K_REG_PC, /* Program Counter */ 17.99 + M68K_REG_SR, /* Status Register */ 17.100 + M68K_REG_SP, /* The current Stack Pointer (located in A7) */ 17.101 + M68K_REG_USP, /* User Stack Pointer */ 17.102 + M68K_REG_ISP, /* Interrupt Stack Pointer */ 17.103 + M68K_REG_MSP, /* Master Stack Pointer */ 17.104 + M68K_REG_SFC, /* Source Function Code */ 17.105 + M68K_REG_DFC, /* Destination Function Code */ 17.106 + M68K_REG_VBR, /* Vector Base Register */ 17.107 + M68K_REG_CACR, /* Cache Control Register */ 17.108 + M68K_REG_CAAR, /* Cache Address Register */ 17.109 + 17.110 + /* Assumed registers */ 17.111 + /* These are cheat registers which emulate the 1-longword prefetch 17.112 + * present in the 68000 and 68010. 17.113 + */ 17.114 + M68K_REG_PREF_ADDR, /* Last prefetch address */ 17.115 + M68K_REG_PREF_DATA, /* Last prefetch data */ 17.116 + 17.117 + /* Convenience registers */ 17.118 + M68K_REG_PPC, /* Previous value in the program counter */ 17.119 + M68K_REG_IR, /* Instruction register */ 17.120 + M68K_REG_CPU_TYPE /* Type of CPU being run */ 17.121 +} m68k_register_t; 17.122 + 17.123 +/* ======================================================================== */ 17.124 +/* ====================== FUNCTIONS CALLED BY THE CPU ===================== */ 17.125 +/* ======================================================================== */ 17.126 + 17.127 +/* You will have to implement these functions */ 17.128 + 17.129 +/* read/write functions called by the CPU to access memory. 17.130 + * while values used are 32 bits, only the appropriate number 17.131 + * of bits are relevant (i.e. in write_memory_8, only the lower 8 bits 17.132 + * of value should be written to memory). 17.133 + * 17.134 + * NOTE: I have separated the immediate and PC-relative memory fetches 17.135 + * from the other memory fetches because some systems require 17.136 + * differentiation between PROGRAM and DATA fetches (usually 17.137 + * for security setups such as encryption). 17.138 + * This separation can either be achieved by setting 17.139 + * M68K_SEPARATE_READS in m68kconf.h and defining 17.140 + * the read functions, or by setting M68K_EMULATE_FC and 17.141 + * making a function code callback function. 17.142 + * Using the callback offers better emulation coverage 17.143 + * because you can also monitor whether the CPU is in SYSTEM or 17.144 + * USER mode, but it is also slower. 17.145 + */ 17.146 + 17.147 +/* Read from anywhere */ 17.148 +unsigned int m68k_read_memory_8(unsigned int address); 17.149 +unsigned int m68k_read_memory_16(unsigned int address); 17.150 +unsigned int m68k_read_memory_32(unsigned int address); 17.151 + 17.152 +/* Read data immediately following the PC */ 17.153 +unsigned int m68k_read_immediate_16(unsigned int address); 17.154 +unsigned int m68k_read_immediate_32(unsigned int address); 17.155 + 17.156 +/* Read data relative to the PC */ 17.157 +unsigned int m68k_read_pcrelative_8(unsigned int address); 17.158 +unsigned int m68k_read_pcrelative_16(unsigned int address); 17.159 +unsigned int m68k_read_pcrelative_32(unsigned int address); 17.160 + 17.161 +/* Memory access for the disassembler */ 17.162 +unsigned int m68k_read_disassembler_8 (unsigned int address); 17.163 +unsigned int m68k_read_disassembler_16 (unsigned int address); 17.164 +unsigned int m68k_read_disassembler_32 (unsigned int address); 17.165 + 17.166 +/* Write to anywhere */ 17.167 +void m68k_write_memory_8(unsigned int address, unsigned int value); 17.168 +void m68k_write_memory_16(unsigned int address, unsigned int value); 17.169 +void m68k_write_memory_32(unsigned int address, unsigned int value); 17.170 + 17.171 + 17.172 + 17.173 +/* ======================================================================== */ 17.174 +/* ============================== CALLBACKS =============================== */ 17.175 +/* ======================================================================== */ 17.176 + 17.177 +/* These functions allow you to set callbacks to the host when specific events 17.178 + * occur. Note that you must enable the corresponding value in m68kconf.h 17.179 + * in order for these to do anything useful. 17.180 + * Note: I have defined default callbacks which are used if you have enabled 17.181 + * the corresponding #define in m68kconf.h but either haven't assigned a 17.182 + * callback or have assigned a callback of NULL. 17.183 + */ 17.184 + 17.185 +/* Set the callback for an interrupt acknowledge. 17.186 + * You must enable M68K_EMULATE_INT_ACK in m68kconf.h. 17.187 + * The CPU will call the callback with the interrupt level being acknowledged. 17.188 + * The host program must return either a vector from 0x02-0xff, or one of the 17.189 + * special interrupt acknowledge values specified earlier in this header. 17.190 + * If this is not implemented, the CPU will always assume an autovectored 17.191 + * interrupt, and will automatically clear the interrupt request when it 17.192 + * services the interrupt. 17.193 + * Default behavior: return M68K_INT_ACK_AUTOVECTOR. 17.194 + */ 17.195 +void m68k_set_int_ack_callback(int (*callback)(int int_level)); 17.196 + 17.197 + 17.198 +/* Set the callback for a breakpoint acknowledge (68010+). 17.199 + * You must enable M68K_EMULATE_BKPT_ACK in m68kconf.h. 17.200 + * The CPU will call the callback with whatever was in the data field of the 17.201 + * BKPT instruction for 68020+, or 0 for 68010. 17.202 + * Default behavior: do nothing. 17.203 + */ 17.204 +void m68k_set_bkpt_ack_callback(void (*callback)(unsigned int data)); 17.205 + 17.206 + 17.207 +/* Set the callback for the RESET instruction. 17.208 + * You must enable M68K_EMULATE_RESET in m68kconf.h. 17.209 + * The CPU calls this callback every time it encounters a RESET instruction. 17.210 + * Default behavior: do nothing. 17.211 + */ 17.212 +void m68k_set_reset_instr_callback(void (*callback)(void)); 17.213 + 17.214 + 17.215 +/* Set the callback for informing of a large PC change. 17.216 + * You must enable M68K_MONITOR_PC in m68kconf.h. 17.217 + * The CPU calls this callback with the new PC value every time the PC changes 17.218 + * by a large value (currently set for changes by longwords). 17.219 + * Default behavior: do nothing. 17.220 + */ 17.221 +void m68k_set_pc_changed_callback(void (*callback)(unsigned int new_pc)); 17.222 + 17.223 + 17.224 +/* Set the callback for CPU function code changes. 17.225 + * You must enable M68K_EMULATE_FC in m68kconf.h. 17.226 + * The CPU calls this callback with the function code before every memory 17.227 + * access to set the CPU's function code according to what kind of memory 17.228 + * access it is (supervisor/user, program/data and such). 17.229 + * Default behavior: do nothing. 17.230 + */ 17.231 +void m68k_set_fc_callback(void (*callback)(unsigned int new_fc)); 17.232 + 17.233 + 17.234 +/* Set a callback for the instruction cycle of the CPU. 17.235 + * You must enable M68K_INSTRUCTION_HOOK in m68kconf.h. 17.236 + * The CPU calls this callback just before fetching the opcode in the 17.237 + * instruction cycle. 17.238 + * Default behavior: do nothing. 17.239 + */ 17.240 +void m68k_set_instr_hook_callback(void (*callback)(void)); 17.241 + 17.242 + 17.243 + 17.244 +/* ======================================================================== */ 17.245 +/* ====================== FUNCTIONS TO ACCESS THE CPU ===================== */ 17.246 +/* ======================================================================== */ 17.247 + 17.248 +/* Use this function to set the CPU type you want to emulate. 17.249 + * Currently supported types are: M68K_CPU_TYPE_68000, M68K_CPU_TYPE_68010, 17.250 + * M68K_CPU_TYPE_EC020, and M68K_CPU_TYPE_68020. 17.251 + */ 17.252 +void m68k_set_cpu_type(unsigned int cpu_type); 17.253 + 17.254 +/* Pulse the RESET pin on the CPU. 17.255 + * You *MUST* reset the CPU at least once to initialize the emulation 17.256 + * Note: If you didn't call m68k_set_cpu_type() before resetting 17.257 + * the CPU for the first time, the CPU will be set to 17.258 + * M68K_CPU_TYPE_68000. 17.259 + */ 17.260 +void m68k_pulse_reset(void); 17.261 + 17.262 +/* execute num_cycles worth of instructions. returns number of cycles used */ 17.263 +int m68k_execute(int num_cycles); 17.264 + 17.265 +/* These functions let you read/write/modify the number of cycles left to run 17.266 + * while m68k_execute() is running. 17.267 + * These are useful if the 68k accesses a memory-mapped port on another device 17.268 + * that requires immediate processing by another CPU. 17.269 + */ 17.270 +int m68k_cycles_run(void); /* Number of cycles run so far */ 17.271 +int m68k_cycles_remaining(void); /* Number of cycles left */ 17.272 +void m68k_modify_timeslice(int cycles); /* Modify cycles left */ 17.273 +void m68k_end_timeslice(void); /* End timeslice now */ 17.274 + 17.275 +/* Set the IPL0-IPL2 pins on the CPU (IRQ). 17.276 + * A transition from < 7 to 7 will cause a non-maskable interrupt (NMI). 17.277 + * Setting IRQ to 0 will clear an interrupt request. 17.278 + */ 17.279 +void m68k_set_irq(unsigned int int_level); 17.280 + 17.281 + 17.282 +/* Halt the CPU as if you pulsed the HALT pin. */ 17.283 +void m68k_pulse_halt(void); 17.284 + 17.285 + 17.286 +/* Context switching to allow multiple CPUs */ 17.287 + 17.288 +/* Get the size of the cpu context in bytes */ 17.289 +unsigned int m68k_context_size(void); 17.290 + 17.291 +/* Get a cpu context */ 17.292 +unsigned int m68k_get_context(void* dst); 17.293 + 17.294 +/* set the current cpu context */ 17.295 +void m68k_set_context(void* dst); 17.296 + 17.297 +/* Save the current cpu context to disk. 17.298 + * You must provide a function pointer of the form: 17.299 + * void save_value(char* identifier, unsigned int value) 17.300 + */ 17.301 +void m68k_save_context( void (*save_value)(char* identifier, unsigned int value)); 17.302 + 17.303 +/* Load a cpu context from disk. 17.304 + * You must provide a function pointer of the form: 17.305 + * unsigned int load_value(char* identifier) 17.306 + */ 17.307 +void m68k_load_context(unsigned int (*load_value)(char* identifier)); 17.308 + 17.309 + 17.310 + 17.311 +/* Peek at the internals of a CPU context. This can either be a context 17.312 + * retrieved using m68k_get_context() or the currently running context. 17.313 + * If context is NULL, the currently running CPU context will be used. 17.314 + */ 17.315 +unsigned int m68k_get_reg(void* context, m68k_register_t reg); 17.316 + 17.317 +/* Poke values into the internals of the currently running CPU context */ 17.318 +void m68k_set_reg(m68k_register_t reg, unsigned int value); 17.319 + 17.320 +/* Check if an instruction is valid for the specified CPU type */ 17.321 +unsigned int m68k_is_valid_instruction(unsigned int instruction, unsigned int cpu_type); 17.322 + 17.323 +/* Disassemble 1 instruction using the epecified CPU type at pc. Stores 17.324 + * disassembly in str_buff and returns the size of the instruction in bytes. 17.325 + */ 17.326 +unsigned int m68k_disassemble(char* str_buff, unsigned int pc, unsigned int cpu_type); 17.327 + 17.328 + 17.329 +/* ======================================================================== */ 17.330 +/* ============================= CONFIGURATION ============================ */ 17.331 +/* ======================================================================== */ 17.332 + 17.333 +/* Import the configuration for this build */ 17.334 +#include "m68kconf.h" 17.335 + 17.336 + 17.337 + 17.338 +/* ======================================================================== */ 17.339 +/* ============================== END OF FILE ============================= */ 17.340 +/* ======================================================================== */ 17.341 + 17.342 +#endif /* M68K__HEADER */
18.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 18.2 +++ b/src/musashi/m68k_in.c Sat Nov 27 01:13:12 2010 +0000 18.3 @@ -0,0 +1,9989 @@ 18.4 +/* ======================================================================== */ 18.5 +/* ========================= LICENSING & COPYRIGHT ======================== */ 18.6 +/* ======================================================================== */ 18.7 +/* 18.8 + * MUSASHI 18.9 + * Version 3.3 18.10 + * 18.11 + * A portable Motorola M680x0 processor emulation engine. 18.12 + * Copyright 1998-2001 Karl Stenerud. All rights reserved. 18.13 + * 18.14 + * This code may be freely used for non-commercial purposes as long as this 18.15 + * copyright notice remains unaltered in the source code and any binary files 18.16 + * containing this code in compiled form. 18.17 + * 18.18 + * All other lisencing terms must be negotiated with the author 18.19 + * (Karl Stenerud). 18.20 + * 18.21 + * The latest version of this code can be obtained at: 18.22 + * http://kstenerud.cjb.net 18.23 + */ 18.24 + 18.25 + 18.26 + 18.27 +/* Input file for m68kmake 18.28 + * ----------------------- 18.29 + * 18.30 + * All sections begin with 80 X's in a row followed by an end-of-line 18.31 + * sequence. 18.32 + * After this, m68kmake will expect to find one of the following section 18.33 + * identifiers: 18.34 + * M68KMAKE_PROTOTYPE_HEADER - header for opcode handler prototypes 18.35 + * M68KMAKE_PROTOTYPE_FOOTER - footer for opcode handler prototypes 18.36 + * M68KMAKE_TABLE_HEADER - header for opcode handler jumptable 18.37 + * M68KMAKE_TABLE_FOOTER - footer for opcode handler jumptable 18.38 + * M68KMAKE_TABLE_BODY - the table itself 18.39 + * M68KMAKE_OPCODE_HANDLER_HEADER - header for opcode handler implementation 18.40 + * M68KMAKE_OPCODE_HANDLER_FOOTER - footer for opcode handler implementation 18.41 + * M68KMAKE_OPCODE_HANDLER_BODY - body section for opcode handler implementation 18.42 + * 18.43 + * NOTE: M68KMAKE_OPCODE_HANDLER_BODY must be last in the file and 18.44 + * M68KMAKE_TABLE_BODY must be second last in the file. 18.45 + * 18.46 + * The M68KMAKE_OPHANDLER_BODY section contains the opcode handler 18.47 + * primitives themselves. Each opcode handler begins with: 18.48 + * M68KMAKE_OP(A, B, C, D) 18.49 + * 18.50 + * where A is the opcode handler name, B is the size of the operation, 18.51 + * C denotes any special processing mode, and D denotes a specific 18.52 + * addressing mode. 18.53 + * For C and D where nothing is specified, use "." 18.54 + * 18.55 + * Example: 18.56 + * M68KMAKE_OP(abcd, 8, rr, .) abcd, size 8, register to register, default EA 18.57 + * M68KMAKE_OP(abcd, 8, mm, ax7) abcd, size 8, memory to memory, register X is A7 18.58 + * M68KMAKE_OP(tst, 16, ., pcix) tst, size 16, PCIX addressing 18.59 + * 18.60 + * All opcode handler primitives end with a closing curly brace "}" at column 1 18.61 + * 18.62 + * NOTE: Do not place a M68KMAKE_OP() directive inside the opcode handler, 18.63 + * and do not put a closing curly brace at column 1 unless it is 18.64 + * marking the end of the handler! 18.65 + * 18.66 + * Inside the handler, m68kmake will recognize M68KMAKE_GET_OPER_xx_xx, 18.67 + * M68KMAKE_GET_EA_xx_xx, and M68KMAKE_CC directives, and create multiple 18.68 + * opcode handlers to handle variations in the opcode handler. 18.69 + * Note: M68KMAKE_CC will only be interpreted in condition code opcodes. 18.70 + * As well, M68KMAKE_GET_EA_xx_xx and M68KMAKE_GET_OPER_xx_xx will only 18.71 + * be interpreted on instructions where the corresponding table entry 18.72 + * specifies multiple effective addressing modes. 18.73 + * Example: 18.74 + * clr 32 . . 0100001010...... A+-DXWL... U U U 12 6 4 18.75 + * 18.76 + * This table entry says that the clr.l opcde has 7 variations (A+-DXWL). 18.77 + * It is run in user or supervisor mode for all CPUs, and uses 12 cycles for 18.78 + * 68000, 6 cycles for 68010, and 4 cycles for 68020. 18.79 + */ 18.80 + 18.81 +XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX 18.82 +M68KMAKE_PROTOTYPE_HEADER 18.83 + 18.84 +#ifndef M68KOPS__HEADER 18.85 +#define M68KOPS__HEADER 18.86 + 18.87 +/* ======================================================================== */ 18.88 +/* ============================ OPCODE HANDLERS =========================== */ 18.89 +/* ======================================================================== */ 18.90 + 18.91 + 18.92 + 18.93 +XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX 18.94 +M68KMAKE_PROTOTYPE_FOOTER 18.95 + 18.96 + 18.97 +/* Build the opcode handler table */ 18.98 +void m68ki_build_opcode_table(void); 18.99 + 18.100 +extern void (*m68ki_instruction_jump_table[0x10000])(void); /* opcode handler jump table */ 18.101 +extern unsigned char m68ki_cycles[][0x10000]; 18.102 + 18.103 + 18.104 +/* ======================================================================== */ 18.105 +/* ============================== END OF FILE ============================= */ 18.106 +/* ======================================================================== */ 18.107 + 18.108 +#endif /* M68KOPS__HEADER */ 18.109 + 18.110 + 18.111 + 18.112 +XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX 18.113 +M68KMAKE_TABLE_HEADER 18.114 + 18.115 +/* ======================================================================== */ 18.116 +/* ========================= OPCODE TABLE BUILDER ========================= */ 18.117 +/* ======================================================================== */ 18.118 + 18.119 +#include "m68kops.h" 18.120 + 18.121 +#define NUM_CPU_TYPES 3 18.122 + 18.123 +void (*m68ki_instruction_jump_table[0x10000])(void); /* opcode handler jump table */ 18.124 +unsigned char m68ki_cycles[NUM_CPU_TYPES][0x10000]; /* Cycles used by CPU type */ 18.125 + 18.126 +/* This is used to generate the opcode handler jump table */ 18.127 +typedef struct 18.128 +{ 18.129 + void (*opcode_handler)(void); /* handler function */ 18.130 + unsigned int mask; /* mask on opcode */ 18.131 + unsigned int match; /* what to match after masking */ 18.132 + unsigned char cycles[NUM_CPU_TYPES]; /* cycles each cpu type takes */ 18.133 +} opcode_handler_struct; 18.134 + 18.135 + 18.136 +/* Opcode handler table */ 18.137 +static opcode_handler_struct m68k_opcode_handler_table[] = 18.138 +{ 18.139 +/* function mask match 000 010 020 */ 18.140 + 18.141 + 18.142 + 18.143 +XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX 18.144 +M68KMAKE_TABLE_FOOTER 18.145 + 18.146 + {0, 0, 0, {0, 0, 0}} 18.147 +}; 18.148 + 18.149 + 18.150 +/* Build the opcode handler jump table */ 18.151 +void m68ki_build_opcode_table(void) 18.152 +{ 18.153 + opcode_handler_struct *ostruct; 18.154 + int instr; 18.155 + int i; 18.156 + int j; 18.157 + int k; 18.158 + 18.159 + for(i = 0; i < 0x10000; i++) 18.160 + { 18.161 + /* default to illegal */ 18.162 + m68ki_instruction_jump_table[i] = m68k_op_illegal; 18.163 + for(k=0;k<NUM_CPU_TYPES;k++) 18.164 + m68ki_cycles[k][i] = 0; 18.165 + } 18.166 + 18.167 + ostruct = m68k_opcode_handler_table; 18.168 + while(ostruct->mask != 0xff00) 18.169 + { 18.170 + for(i = 0;i < 0x10000;i++) 18.171 + { 18.172 + if((i & ostruct->mask) == ostruct->match) 18.173 + { 18.174 + m68ki_instruction_jump_table[i] = ostruct->opcode_handler; 18.175 + for(k=0;k<NUM_CPU_TYPES;k++) 18.176 + m68ki_cycles[k][i] = ostruct->cycles[k]; 18.177 + } 18.178 + } 18.179 + ostruct++; 18.180 + } 18.181 + while(ostruct->mask == 0xff00) 18.182 + { 18.183 + for(i = 0;i <= 0xff;i++) 18.184 + { 18.185 + m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler; 18.186 + for(k=0;k<NUM_CPU_TYPES;k++) 18.187 + m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k]; 18.188 + } 18.189 + ostruct++; 18.190 + } 18.191 + while(ostruct->mask == 0xf1f8) 18.192 + { 18.193 + for(i = 0;i < 8;i++) 18.194 + { 18.195 + for(j = 0;j < 8;j++) 18.196 + { 18.197 + instr = ostruct->match | (i << 9) | j; 18.198 + m68ki_instruction_jump_table[instr] = ostruct->opcode_handler; 18.199 + for(k=0;k<NUM_CPU_TYPES;k++) 18.200 + m68ki_cycles[k][instr] = ostruct->cycles[k]; 18.201 + if((instr & 0xf000) == 0xe000 && (!(instr & 0x20))) 18.202 + m68ki_cycles[0][instr] = m68ki_cycles[1][instr] = ostruct->cycles[k] + ((((j-1)&7)+1)<<1); 18.203 + } 18.204 + } 18.205 + ostruct++; 18.206 + } 18.207 + while(ostruct->mask == 0xfff0) 18.208 + { 18.209 + for(i = 0;i <= 0x0f;i++) 18.210 + { 18.211 + m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler; 18.212 + for(k=0;k<NUM_CPU_TYPES;k++) 18.213 + m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k]; 18.214 + } 18.215 + ostruct++; 18.216 + } 18.217 + while(ostruct->mask == 0xf1ff) 18.218 + { 18.219 + for(i = 0;i <= 0x07;i++) 18.220 + { 18.221 + m68ki_instruction_jump_table[ostruct->match | (i << 9)] = ostruct->opcode_handler; 18.222 + for(k=0;k<NUM_CPU_TYPES;k++) 18.223 + m68ki_cycles[k][ostruct->match | (i << 9)] = ostruct->cycles[k]; 18.224 + } 18.225 + ostruct++; 18.226 + } 18.227 + while(ostruct->mask == 0xfff8) 18.228 + { 18.229 + for(i = 0;i <= 0x07;i++) 18.230 + { 18.231 + m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler; 18.232 + for(k=0;k<NUM_CPU_TYPES;k++) 18.233 + m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k]; 18.234 + } 18.235 + ostruct++; 18.236 + } 18.237 + while(ostruct->mask == 0xffff) 18.238 + { 18.239 + m68ki_instruction_jump_table[ostruct->match] = ostruct->opcode_handler; 18.240 + for(k=0;k<NUM_CPU_TYPES;k++) 18.241 + m68ki_cycles[k][ostruct->match] = ostruct->cycles[k]; 18.242 + ostruct++; 18.243 + } 18.244 +} 18.245 + 18.246 + 18.247 +/* ======================================================================== */ 18.248 +/* ============================== END OF FILE ============================= */ 18.249 +/* ======================================================================== */ 18.250 + 18.251 + 18.252 + 18.253 +XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX 18.254 +M68KMAKE_OPCODE_HANDLER_HEADER 18.255 + 18.256 +#include "m68kcpu.h" 18.257 + 18.258 +/* ======================================================================== */ 18.259 +/* ========================= INSTRUCTION HANDLERS ========================= */ 18.260 +/* ======================================================================== */ 18.261 + 18.262 + 18.263 + 18.264 +XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX 18.265 +M68KMAKE_OPCODE_HANDLER_FOOTER 18.266 + 18.267 +/* ======================================================================== */ 18.268 +/* ============================== END OF FILE ============================= */ 18.269 +/* ======================================================================== */ 18.270 + 18.271 + 18.272 + 18.273 +XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX 18.274 +M68KMAKE_TABLE_BODY 18.275 + 18.276 +The following table is arranged as follows: 18.277 + 18.278 +name: Opcode mnemonic 18.279 + 18.280 +size: Operation size 18.281 + 18.282 +spec proc: Special processing mode: 18.283 + .: normal 18.284 + s: static operand 18.285 + r: register operand 18.286 + rr: register to register 18.287 + mm: memory to memory 18.288 + er: effective address to register 18.289 + re: register to effective address 18.290 + dd: data register to data register 18.291 + da: data register to address register 18.292 + aa: address register to address register 18.293 + cr: control register to register 18.294 + rc: register to control register 18.295 + toc: to condition code register 18.296 + tos: to status register 18.297 + tou: to user stack pointer 18.298 + frc: from condition code register 18.299 + frs: from status register 18.300 + fru: from user stack pointer 18.301 + * for move.x, the special processing mode is a specific 18.302 + destination effective addressing mode. 18.303 + 18.304 +spec ea: Specific effective addressing mode: 18.305 + .: normal 18.306 + i: immediate 18.307 + d: data register 18.308 + a: address register 18.309 + ai: address register indirect 18.310 + pi: address register indirect with postincrement 18.311 + pd: address register indirect with predecrement 18.312 + di: address register indirect with displacement 18.313 + ix: address register indirect with index 18.314 + aw: absolute word address 18.315 + al: absolute long address 18.316 + pcdi: program counter relative with displacement 18.317 + pcix: program counter relative with index 18.318 + a7: register specified in instruction is A7 18.319 + ax7: register field X of instruction is A7 18.320 + ay7: register field Y of instruction is A7 18.321 + axy7: register fields X and Y of instruction are A7 18.322 + 18.323 +bit pattern: Pattern to recognize this opcode. "." means don't care. 18.324 + 18.325 +allowed ea: List of allowed addressing modes: 18.326 + .: not present 18.327 + A: address register indirect 18.328 + +: ARI (address register indirect) with postincrement 18.329 + -: ARI with predecrement 18.330 + D: ARI with displacement 18.331 + X: ARI with index 18.332 + W: absolute word address 18.333 + L: absolute long address 18.334 + d: program counter indirect with displacement 18.335 + x: program counter indirect with index 18.336 + I: immediate 18.337 +mode: CPU operating mode for each cpu type. U = user or supervisor, 18.338 + S = supervisor only, "." = opcode not present. 18.339 + 18.340 +cpu cycles: Base number of cycles required to execute this opcode on the 18.341 + specified CPU type. 18.342 + Use "." if CPU does not have this opcode. 18.343 + 18.344 + 18.345 + 18.346 + spec spec allowed ea mode cpu cycles 18.347 +name size proc ea bit pattern A+-DXWLdxI 0 1 2 000 010 020 comments 18.348 +====== ==== ==== ==== ================ ========== = = = === === === ============= 18.349 +M68KMAKE_TABLE_START 18.350 +1010 0 . . 1010............ .......... U U U 4 4 4 18.351 +1111 0 . . 1111............ .......... U U U 4 4 4 18.352 +abcd 8 rr . 1100...100000... .......... U U U 6 6 4 18.353 +abcd 8 mm ax7 1100111100001... .......... U U U 18 18 16 18.354 +abcd 8 mm ay7 1100...100001111 .......... U U U 18 18 16 18.355 +abcd 8 mm axy7 1100111100001111 .......... U U U 18 18 16 18.356 +abcd 8 mm . 1100...100001... .......... U U U 18 18 16 18.357 +add 8 er d 1101...000000... .......... U U U 4 4 2 18.358 +add 8 er . 1101...000...... A+-DXWLdxI U U U 4 4 2 18.359 +add 16 er d 1101...001000... .......... U U U 4 4 2 18.360 +add 16 er a 1101...001001... .......... U U U 4 4 2 18.361 +add 16 er . 1101...001...... A+-DXWLdxI U U U 4 4 2 18.362 +add 32 er d 1101...010000... .......... U U U 6 6 2 18.363 +add 32 er a 1101...010001... .......... U U U 6 6 2 18.364 +add 32 er . 1101...010...... A+-DXWLdxI U U U 6 6 2 18.365 +add 8 re . 1101...100...... A+-DXWL... U U U 8 8 4 18.366 +add 16 re . 1101...101...... A+-DXWL... U U U 8 8 4 18.367 +add 32 re . 1101...110...... A+-DXWL... U U U 12 12 4 18.368 +adda 16 . d 1101...011000... .......... U U U 8 8 2 18.369 +adda 16 . a 1101...011001... .......... U U U 8 8 2 18.370 +adda 16 . . 1101...011...... A+-DXWLdxI U U U 8 8 2 18.371 +adda 32 . d 1101...111000... .......... U U U 6 6 2 18.372 +adda 32 . a 1101...111001... .......... U U U 6 6 2 18.373 +adda 32 . . 1101...111...... A+-DXWLdxI U U U 6 6 2 18.374 +addi 8 . d 0000011000000... .......... U U U 8 8 2 18.375 +addi 8 . . 0000011000...... A+-DXWL... U U U 12 12 4 18.376 +addi 16 . d 0000011001000... .......... U U U 8 8 2 18.377 +addi 16 . . 0000011001...... A+-DXWL... U U U 12 12 4 18.378 +addi 32 . d 0000011010000... .......... U U U 16 14 2 18.379 +addi 32 . . 0000011010...... A+-DXWL... U U U 20 20 4 18.380 +addq 8 . d 0101...000000... .......... U U U 4 4 2 18.381 +addq 8 . . 0101...000...... A+-DXWL... U U U 8 8 4 18.382 +addq 16 . d 0101...001000... .......... U U U 4 4 2 18.383 +addq 16 . a 0101...001001... .......... U U U 4 4 2 18.384 +addq 16 . . 0101...001...... A+-DXWL... U U U 8 8 4 18.385 +addq 32 . d 0101...010000... .......... U U U 8 8 2 18.386 +addq 32 . a 0101...010001... .......... U U U 8 8 2 18.387 +addq 32 . . 0101...010...... A+-DXWL... U U U 12 12 4 18.388 +addx 8 rr . 1101...100000... .......... U U U 4 4 2 18.389 +addx 16 rr . 1101...101000... .......... U U U 4 4 2 18.390 +addx 32 rr . 1101...110000... .......... U U U 8 6 2 18.391 +addx 8 mm ax7 1101111100001... .......... U U U 18 18 12 18.392 +addx 8 mm ay7 1101...100001111 .......... U U U 18 18 12 18.393 +addx 8 mm axy7 1101111100001111 .......... U U U 18 18 12 18.394 +addx 8 mm . 1101...100001... .......... U U U 18 18 12 18.395 +addx 16 mm . 1101...101001... .......... U U U 18 18 12 18.396 +addx 32 mm . 1101...110001... .......... U U U 30 30 12 18.397 +and 8 er d 1100...000000... .......... U U U 4 4 2 18.398 +and 8 er . 1100...000...... A+-DXWLdxI U U U 4 4 2 18.399 +and 16 er d 1100...001000... .......... U U U 4 4 2 18.400 +and 16 er . 1100...001...... A+-DXWLdxI U U U 4 4 2 18.401 +and 32 er d 1100...010000... .......... U U U 6 6 2 18.402 +and 32 er . 1100...010...... A+-DXWLdxI U U U 6 6 2 18.403 +and 8 re . 1100...100...... A+-DXWL... U U U 8 8 4 18.404 +and 16 re . 1100...101...... A+-DXWL... U U U 8 8 4 18.405 +and 32 re . 1100...110...... A+-DXWL... U U U 12 12 4 18.406 +andi 16 toc . 0000001000111100 .......... U U U 20 16 12 18.407 +andi 16 tos . 0000001001111100 .......... S S S 20 16 12 18.408 +andi 8 . d 0000001000000... .......... U U U 8 8 2 18.409 +andi 8 . . 0000001000...... A+-DXWL... U U U 12 12 4 18.410 +andi 16 . d 0000001001000... .......... U U U 8 8 2 18.411 +andi 16 . . 0000001001...... A+-DXWL... U U U 12 12 4 18.412 +andi 32 . d 0000001010000... .......... U U U 14 14 2 18.413 +andi 32 . . 0000001010...... A+-DXWL... U U U 20 20 4 18.414 +asr 8 s . 1110...000000... .......... U U U 6 6 6 18.415 +asr 16 s . 1110...001000... .......... U U U 6 6 6 18.416 +asr 32 s . 1110...010000... .......... U U U 8 8 6 18.417 +asr 8 r . 1110...000100... .......... U U U 6 6 6 18.418 +asr 16 r . 1110...001100... .......... U U U 6 6 6 18.419 +asr 32 r . 1110...010100... .......... U U U 8 8 6 18.420 +asr 16 . . 1110000011...... A+-DXWL... U U U 8 8 5 18.421 +asl 8 s . 1110...100000... .......... U U U 6 6 8 18.422 +asl 16 s . 1110...101000... .......... U U U 6 6 8 18.423 +asl 32 s . 1110...110000... .......... U U U 8 8 8 18.424 +asl 8 r . 1110...100100... .......... U U U 6 6 8 18.425 +asl 16 r . 1110...101100... .......... U U U 6 6 8 18.426 +asl 32 r . 1110...110100... .......... U U U 8 8 8 18.427 +asl 16 . . 1110000111...... A+-DXWL... U U U 8 8 6 18.428 +bcc 8 . . 0110............ .......... U U U 8 8 6 18.429 +bcc 16 . . 0110....00000000 .......... U U U 10 10 6 18.430 +bcc 32 . . 0110....11111111 .......... . . U . . 6 18.431 +bchg 8 r . 0000...101...... A+-DXWL... U U U 8 8 4 18.432 +bchg 32 r d 0000...101000... .......... U U U 8 8 4 18.433 +bchg 8 s . 0000100001...... A+-DXWL... U U U 12 12 4 18.434 +bchg 32 s d 0000100001000... .......... U U U 12 12 4 18.435 +bclr 8 r . 0000...110...... A+-DXWL... U U U 8 10 4 18.436 +bclr 32 r d 0000...110000... .......... U U U 10 10 4 18.437 +bclr 8 s . 0000100010...... A+-DXWL... U U U 12 12 4 18.438 +bclr 32 s d 0000100010000... .......... U U U 14 14 4 18.439 +bfchg 32 . d 1110101011000... .......... . . U . . 12 timing not quite correct 18.440 +bfchg 32 . . 1110101011...... A..DXWL... . . U . . 20 18.441 +bfclr 32 . d 1110110011000... .......... . . U . . 12 18.442 +bfclr 32 . . 1110110011...... A..DXWL... . . U . . 20 18.443 +bfexts 32 . d 1110101111000... .......... . . U . . 8 18.444 +bfexts 32 . . 1110101111...... A..DXWLdx. . . U . . 15 18.445 +bfextu 32 . d 1110100111000... .......... . . U . . 8 18.446 +bfextu 32 . . 1110100111...... A..DXWLdx. . . U . . 15 18.447 +bfffo 32 . d 1110110111000... .......... . . U . . 18 18.448 +bfffo 32 . . 1110110111...... A..DXWLdx. . . U . . 28 18.449 +bfins 32 . d 1110111111000... .......... . . U . . 10 18.450 +bfins 32 . . 1110111111...... A..DXWL... . . U . . 17 18.451 +bfset 32 . d 1110111011000... .......... . . U . . 12 18.452 +bfset 32 . . 1110111011...... A..DXWL... . . U . . 20 18.453 +bftst 32 . d 1110100011000... .......... . . U . . 6 18.454 +bftst 32 . . 1110100011...... A..DXWLdx. . . U . . 13 18.455 +bkpt 0 . . 0100100001001... .......... . U U . 10 10 18.456 +bra 8 . . 01100000........ .......... U U U 10 10 10 18.457 +bra 16 . . 0110000000000000 .......... U U U 10 10 10 18.458 +bra 32 . . 0110000011111111 .......... U U U . . 10 18.459 +bset 32 r d 0000...111000... .......... U U U 8 8 4 18.460 +bset 8 r . 0000...111...... A+-DXWL... U U U 8 8 4 18.461 +bset 8 s . 0000100011...... A+-DXWL... U U U 12 12 4 18.462 +bset 32 s d 0000100011000... .......... U U U 12 12 4 18.463 +bsr 8 . . 01100001........ .......... U U U 18 18 7 18.464 +bsr 16 . . 0110000100000000 .......... U U U 18 18 7 18.465 +bsr 32 . . 0110000111111111 .......... . . U . . 7 18.466 +btst 8 r . 0000...100...... A+-DXWLdxI U U U 4 4 4 18.467 +btst 32 r d 0000...100000... .......... U U U 6 6 4 18.468 +btst 8 s . 0000100000...... A+-DXWLdx. U U U 8 8 4 18.469 +btst 32 s d 0000100000000... .......... U U U 10 10 4 18.470 +callm 32 . . 0000011011...... A..DXWLdx. . . U . . 60 not properly emulated 18.471 +cas 8 . . 0000101011...... A+-DXWL... . . U . . 12 18.472 +cas 16 . . 0000110011...... A+-DXWL... . . U . . 12 18.473 +cas 32 . . 0000111011...... A+-DXWL... . . U . . 12 18.474 +cas2 16 . . 0000110011111100 .......... . . U . . 12 18.475 +cas2 32 . . 0000111011111100 .......... . . U . . 12 18.476 +chk 16 . d 0100...110000... .......... U U U 10 8 8 18.477 +chk 16 . . 0100...110...... A+-DXWLdxI U U U 10 8 8 18.478 +chk 32 . d 0100...100000... .......... . . U . . 8 18.479 +chk 32 . . 0100...100...... A+-DXWLdxI . . U . . 8 18.480 +chk2cmp2 8 . . 0000000011...... A..DXWLdx. . . U . . 18 18.481 +chk2cmp2 16 . . 0000001011...... A..DXWLdx. . . U . . 18 18.482 +chk2cmp2 32 . . 0000010011...... A..DXWLdx. . . U . . 18 18.483 +clr 8 . d 0100001000000... .......... U U U 4 4 2 18.484 +clr 8 . . 0100001000...... A+-DXWL... U U U 8 4 4 18.485 +clr 16 . d 0100001001000... .......... U U U 4 4 2 18.486 +clr 16 . . 0100001001...... A+-DXWL... U U U 8 4 4 18.487 +clr 32 . d 0100001010000... .......... U U U 6 6 2 18.488 +clr 32 . . 0100001010...... A+-DXWL... U U U 12 6 4 18.489 +cmp 8 . d 1011...000000... .......... U U U 4 4 2 18.490 +cmp 8 . . 1011...000...... A+-DXWLdxI U U U 4 4 2 18.491 +cmp 16 . d 1011...001000... .......... U U U 4 4 2 18.492 +cmp 16 . a 1011...001001... .......... U U U 4 4 2 18.493 +cmp 16 . . 1011...001...... A+-DXWLdxI U U U 4 4 2 18.494 +cmp 32 . d 1011...010000... .......... U U U 6 6 2 18.495 +cmp 32 . a 1011...010001... .......... U U U 6 6 2 18.496 +cmp 32 . . 1011...010...... A+-DXWLdxI U U U 6 6 2 18.497 +cmpa 16 . d 1011...011000... .......... U U U 6 6 4 18.498 +cmpa 16 . a 1011...011001... .......... U U U 6 6 4 18.499 +cmpa 16 . . 1011...011...... A+-DXWLdxI U U U 6 6 4 18.500 +cmpa 32 . d 1011...111000... .......... U U U 6 6 4 18.501 +cmpa 32 . a 1011...111001... .......... U U U 6 6 4 18.502 +cmpa 32 . . 1011...111...... A+-DXWLdxI U U U 6 6 4 18.503 +cmpi 8 . d 0000110000000... .......... U U U 8 8 2 18.504 +cmpi 8 . . 0000110000...... A+-DXWL... U U U 8 8 2 18.505 +cmpi 8 . pcdi 0000110000111010 .......... . . U . . 7 18.506 +cmpi 8 . pcix 0000110000111011 .......... . . U . . 9 18.507 +cmpi 16 . d 0000110001000... .......... U U U 8 8 2 18.508 +cmpi 16 . . 0000110001...... A+-DXWL... U U U 8 8 2 18.509 +cmpi 16 . pcdi 0000110001111010 .......... . . U . . 7 18.510 +cmpi 16 . pcix 0000110001111011 .......... . . U . . 9 18.511 +cmpi 32 . d 0000110010000... .......... U U U 14 12 2 18.512 +cmpi 32 . . 0000110010...... A+-DXWL... U U U 12 12 2 18.513 +cmpi 32 . pcdi 0000110010111010 .......... . . U . . 7 18.514 +cmpi 32 . pcix 0000110010111011 .......... . . U . . 9 18.515 +cmpm 8 . ax7 1011111100001... .......... U U U 12 12 9 18.516 +cmpm 8 . ay7 1011...100001111 .......... U U U 12 12 9 18.517 +cmpm 8 . axy7 1011111100001111 .......... U U U 12 12 9 18.518 +cmpm 8 . . 1011...100001... .......... U U U 12 12 9 18.519 +cmpm 16 . . 1011...101001... .......... U U U 12 12 9 18.520 +cmpm 32 . . 1011...110001... .......... U U U 20 20 9 18.521 +cpbcc 32 . . 1111...01....... .......... . . U . . 4 unemulated 18.522 +cpdbcc 32 . . 1111...001001... .......... . . U . . 4 unemulated 18.523 +cpgen 32 . . 1111...000...... .......... . . U . . 4 unemulated 18.524 +cpscc 32 . . 1111...001...... .......... . . U . . 4 unemulated 18.525 +cptrapcc 32 . . 1111...001111... .......... . . U . . 4 unemulated 18.526 +dbt 16 . . 0101000011001... .......... U U U 12 12 6 18.527 +dbf 16 . . 0101000111001... .......... U U U 14 14 6 18.528 +dbcc 16 . . 0101....11001... .......... U U U 12 12 6 18.529 +divs 16 . d 1000...111000... .......... U U U 158 122 56 18.530 +divs 16 . . 1000...111...... A+-DXWLdxI U U U 158 122 56 18.531 +divu 16 . d 1000...011000... .......... U U U 140 108 44 18.532 +divu 16 . . 1000...011...... A+-DXWLdxI U U U 140 108 44 18.533 +divl 32 . d 0100110001000... .......... . . U . . 84 18.534 +divl 32 . . 0100110001...... A+-DXWLdxI . . U . . 84 18.535 +eor 8 . d 1011...100000... .......... U U U 4 4 2 18.536 +eor 8 . . 1011...100...... A+-DXWL... U U U 8 8 4 18.537 +eor 16 . d 1011...101000... .......... U U U 4 4 2 18.538 +eor 16 . . 1011...101...... A+-DXWL... U U U 8 8 4 18.539 +eor 32 . d 1011...110000... .......... U U U 8 6 2 18.540 +eor 32 . . 1011...110...... A+-DXWL... U U U 12 12 4 18.541 +eori 16 toc . 0000101000111100 .......... U U U 20 16 12 18.542 +eori 16 tos . 0000101001111100 .......... S S S 20 16 12 18.543 +eori 8 . d 0000101000000... .......... U U U 8 8 2 18.544 +eori 8 . . 0000101000...... A+-DXWL... U U U 12 12 4 18.545 +eori 16 . d 0000101001000... .......... U U U 8 8 2 18.546 +eori 16 . . 0000101001...... A+-DXWL... U U U 12 12 4 18.547 +eori 32 . d 0000101010000... .......... U U U 16 14 2 18.548 +eori 32 . . 0000101010...... A+-DXWL... U U U 20 20 4 18.549 +exg 32 dd . 1100...101000... .......... U U U 6 6 2 18.550 +exg 32 aa . 1100...101001... .......... U U U 6 6 2 18.551 +exg 32 da . 1100...110001... .......... U U U 6 6 2 18.552 +ext 16 . . 0100100010000... .......... U U U 4 4 4 18.553 +ext 32 . . 0100100011000... .......... U U U 4 4 4 18.554 +extb 32 . . 0100100111000... .......... . . U . . 4 18.555 +illegal 0 . . 0100101011111100 .......... U U U 4 4 4 18.556 +jmp 32 . . 0100111011...... A..DXWLdx. U U U 4 4 0 18.557 +jsr 32 . . 0100111010...... A..DXWLdx. U U U 12 12 0 18.558 +lea 32 . . 0100...111...... A..DXWLdx. U U U 0 0 2 18.559 +link 16 . a7 0100111001010111 .......... U U U 16 16 5 18.560 +link 16 . . 0100111001010... .......... U U U 16 16 5 18.561 +link 32 . a7 0100100000001111 .......... . . U . . 6 18.562 +link 32 . . 0100100000001... .......... . . U . . 6 18.563 +lsr 8 s . 1110...000001... .......... U U U 6 6 4 18.564 +lsr 16 s . 1110...001001... .......... U U U 6 6 4 18.565 +lsr 32 s . 1110...010001... .......... U U U 8 8 4 18.566 +lsr 8 r . 1110...000101... .......... U U U 6 6 6 18.567 +lsr 16 r . 1110...001101... .......... U U U 6 6 6 18.568 +lsr 32 r . 1110...010101... .......... U U U 8 8 6 18.569 +lsr 16 . . 1110001011...... A+-DXWL... U U U 8 8 5 18.570 +lsl 8 s . 1110...100001... .......... U U U 6 6 4 18.571 +lsl 16 s . 1110...101001... .......... U U U 6 6 4 18.572 +lsl 32 s . 1110...110001... .......... U U U 8 8 4 18.573 +lsl 8 r . 1110...100101... .......... U U U 6 6 6 18.574 +lsl 16 r . 1110...101101... .......... U U U 6 6 6 18.575 +lsl 32 r . 1110...110101... .......... U U U 8 8 6 18.576 +lsl 16 . . 1110001111...... A+-DXWL... U U U 8 8 5 18.577 +move 8 d d 0001...000000... .......... U U U 4 4 2 18.578 +move 8 d . 0001...000...... A+-DXWLdxI U U U 4 4 2 18.579 +move 8 ai d 0001...010000... .......... U U U 8 8 4 18.580 +move 8 ai . 0001...010...... A+-DXWLdxI U U U 8 8 4 18.581 +move 8 pi d 0001...011000... .......... U U U 8 8 4 18.582 +move 8 pi . 0001...011...... A+-DXWLdxI U U U 8 8 4 18.583 +move 8 pi7 d 0001111011000... .......... U U U 8 8 4 18.584 +move 8 pi7 . 0001111011...... A+-DXWLdxI U U U 8 8 4 18.585 +move 8 pd d 0001...100000... .......... U U U 8 8 5 18.586 +move 8 pd . 0001...100...... A+-DXWLdxI U U U 8 8 5 18.587 +move 8 pd7 d 0001111100000... .......... U U U 8 8 5 18.588 +move 8 pd7 . 0001111100...... A+-DXWLdxI U U U 8 8 5 18.589 +move 8 di d 0001...101000... .......... U U U 12 12 5 18.590 +move 8 di . 0001...101...... A+-DXWLdxI U U U 12 12 5 18.591 +move 8 ix d 0001...110000... .......... U U U 14 14 7 18.592 +move 8 ix . 0001...110...... A+-DXWLdxI U U U 14 14 7 18.593 +move 8 aw d 0001000111000... .......... U U U 12 12 4 18.594 +move 8 aw . 0001000111...... A+-DXWLdxI U U U 12 12 4 18.595 +move 8 al d 0001001111000... .......... U U U 16 16 6 18.596 +move 8 al . 0001001111...... A+-DXWLdxI U U U 16 16 6 18.597 +move 16 d d 0011...000000... .......... U U U 4 4 2 18.598 +move 16 d a 0011...000001... .......... U U U 4 4 2 18.599 +move 16 d . 0011...000...... A+-DXWLdxI U U U 4 4 2 18.600 +move 16 ai d 0011...010000... .......... U U U 8 8 4 18.601 +move 16 ai a 0011...010001... .......... U U U 8 8 4 18.602 +move 16 ai . 0011...010...... A+-DXWLdxI U U U 8 8 4 18.603 +move 16 pi d 0011...011000... .......... U U U 8 8 4 18.604 +move 16 pi a 0011...011001... .......... U U U 8 8 4 18.605 +move 16 pi . 0011...011...... A+-DXWLdxI U U U 8 8 4 18.606 +move 16 pd d 0011...100000... .......... U U U 8 8 5 18.607 +move 16 pd a 0011...100001... .......... U U U 8 8 5 18.608 +move 16 pd . 0011...100...... A+-DXWLdxI U U U 8 8 5 18.609 +move 16 di d 0011...101000... .......... U U U 12 12 5 18.610 +move 16 di a 0011...101001... .......... U U U 12 12 5 18.611 +move 16 di . 0011...101...... A+-DXWLdxI U U U 12 12 5 18.612 +move 16 ix d 0011...110000... .......... U U U 14 14 7 18.613 +move 16 ix a 0011...110001... .......... U U U 14 14 7 18.614 +move 16 ix . 0011...110...... A+-DXWLdxI U U U 14 14 7 18.615 +move 16 aw d 0011000111000... .......... U U U 12 12 4 18.616 +move 16 aw a 0011000111001... .......... U U U 12 12 4 18.617 +move 16 aw . 0011000111...... A+-DXWLdxI U U U 12 12 4 18.618 +move 16 al d 0011001111000... .......... U U U 16 16 6 18.619 +move 16 al a 0011001111001... .......... U U U 16 16 6 18.620 +move 16 al . 0011001111...... A+-DXWLdxI U U U 16 16 6 18.621 +move 32 d d 0010...000000... .......... U U U 4 4 2 18.622 +move 32 d a 0010...000001... .......... U U U 4 4 2 18.623 +move 32 d . 0010...000...... A+-DXWLdxI U U U 4 4 2 18.624 +move 32 ai d 0010...010000... .......... U U U 12 12 4 18.625 +move 32 ai a 0010...010001... .......... U U U 12 12 4 18.626 +move 32 ai . 0010...010...... A+-DXWLdxI U U U 12 12 4 18.627 +move 32 pi d 0010...011000... .......... U U U 12 12 4 18.628 +move 32 pi a 0010...011001... .......... U U U 12 12 4 18.629 +move 32 pi . 0010...011...... A+-DXWLdxI U U U 12 12 4 18.630 +move 32 pd d 0010...100000... .......... U U U 12 14 5 18.631 +move 32 pd a 0010...100001... .......... U U U 12 14 5 18.632 +move 32 pd . 0010...100...... A+-DXWLdxI U U U 12 14 5 18.633 +move 32 di d 0010...101000... .......... U U U 16 16 5 18.634 +move 32 di a 0010...101001... .......... U U U 16 16 5 18.635 +move 32 di . 0010...101...... A+-DXWLdxI U U U 16 16 5 18.636 +move 32 ix d 0010...110000... .......... U U U 18 18 7 18.637 +move 32 ix a 0010...110001... .......... U U U 18 18 7 18.638 +move 32 ix . 0010...110...... A+-DXWLdxI U U U 18 18 7 18.639 +move 32 aw d 0010000111000... .......... U U U 16 16 4 18.640 +move 32 aw a 0010000111001... .......... U U U 16 16 4 18.641 +move 32 aw . 0010000111...... A+-DXWLdxI U U U 16 16 4 18.642 +move 32 al d 0010001111000... .......... U U U 20 20 6 18.643 +move 32 al a 0010001111001... .......... U U U 20 20 6 18.644 +move 32 al . 0010001111...... A+-DXWLdxI U U U 20 20 6 18.645 +movea 16 . d 0011...001000... .......... U U U 4 4 2 18.646 +movea 16 . a 0011...001001... .......... U U U 4 4 2 18.647 +movea 16 . . 0011...001...... A+-DXWLdxI U U U 4 4 2 18.648 +movea 32 . d 0010...001000... .......... U U U 4 4 2 18.649 +movea 32 . a 0010...001001... .......... U U U 4 4 2 18.650 +movea 32 . . 0010...001...... A+-DXWLdxI U U U 4 4 2 18.651 +move 16 frc d 0100001011000... .......... . U U . 4 4 18.652 +move 16 frc . 0100001011...... A+-DXWL... . U U . 8 4 18.653 +move 16 toc d 0100010011000... .......... U U U 12 12 4 18.654 +move 16 toc . 0100010011...... A+-DXWLdxI U U U 12 12 4 18.655 +move 16 frs d 0100000011000... .......... U S S 6 4 8 U only for 000 18.656 +move 16 frs . 0100000011...... A+-DXWL... U S S 8 8 8 U only for 000 18.657 +move 16 tos d 0100011011000... .......... S S S 12 12 8 18.658 +move 16 tos . 0100011011...... A+-DXWLdxI S S S 12 12 8 18.659 +move 32 fru . 0100111001101... .......... S S S 4 6 2 18.660 +move 32 tou . 0100111001100... .......... S S S 4 6 2 18.661 +movec 32 cr . 0100111001111010 .......... . S S . 12 6 18.662 +movec 32 rc . 0100111001111011 .......... . S S . 10 12 18.663 +movem 16 re pd 0100100010100... .......... U U U 8 8 4 18.664 +movem 16 re . 0100100010...... A..DXWL... U U U 8 8 4 18.665 +movem 32 re pd 0100100011100... .......... U U U 8 8 4 18.666 +movem 32 re . 0100100011...... A..DXWL... U U U 8 8 4 18.667 +movem 16 er pi 0100110010011... .......... U U U 12 12 8 18.668 +movem 16 er . 0100110010...... A..DXWLdx. U U U 12 12 8 18.669 +movem 32 er pi 0100110011011... .......... U U U 12 12 8 18.670 +movem 32 er . 0100110011...... A..DXWLdx. U U U 12 12 8 18.671 +movep 16 er . 0000...100001... .......... U U U 16 16 12 18.672 +movep 32 er . 0000...101001... .......... U U U 24 24 18 18.673 +movep 16 re . 0000...110001... .......... U U U 16 16 11 18.674 +movep 32 re . 0000...111001... .......... U U U 24 24 17 18.675 +moveq 32 . . 0111...0........ .......... U U U 4 4 2 18.676 +moves 8 . . 0000111000...... A+-DXWL... . S S . 14 5 18.677 +moves 16 . . 0000111001...... A+-DXWL... . S S . 14 5 18.678 +moves 32 . . 0000111010...... A+-DXWL... . S S . 16 5 18.679 +muls 16 . d 1100...111000... .......... U U U 54 32 27 18.680 +muls 16 . . 1100...111...... A+-DXWLdxI U U U 54 32 27 18.681 +mulu 16 . d 1100...011000... .......... U U U 54 30 27 18.682 +mulu 16 . . 1100...011...... A+-DXWLdxI U U U 54 30 27 18.683 +mull 32 . d 0100110000000... .......... . . U . . 43 18.684 +mull 32 . . 0100110000...... A+-DXWLdxI . . U . . 43 18.685 +nbcd 8 . d 0100100000000... .......... U U U 6 6 6 18.686 +nbcd 8 . . 0100100000...... A+-DXWL... U U U 8 8 6 18.687 +neg 8 . d 0100010000000... .......... U U U 4 4 2 18.688 +neg 8 . . 0100010000...... A+-DXWL... U U U 8 8 4 18.689 +neg 16 . d 0100010001000... .......... U U U 4 4 2 18.690 +neg 16 . . 0100010001...... A+-DXWL... U U U 8 8 4 18.691 +neg 32 . d 0100010010000... .......... U U U 6 6 2 18.692 +neg 32 . . 0100010010...... A+-DXWL... U U U 12 12 4 18.693 +negx 8 . d 0100000000000... .......... U U U 4 4 2 18.694 +negx 8 . . 0100000000...... A+-DXWL... U U U 8 8 4 18.695 +negx 16 . d 0100000001000... .......... U U U 4 4 2 18.696 +negx 16 . . 0100000001...... A+-DXWL... U U U 8 8 4 18.697 +negx 32 . d 0100000010000... .......... U U U 6 6 2 18.698 +negx 32 . . 0100000010...... A+-DXWL... U U U 12 12 4 18.699 +nop 0 . . 0100111001110001 .......... U U U 4 4 2 18.700 +not 8 . d 0100011000000... .......... U U U 4 4 2 18.701 +not 8 . . 0100011000...... A+-DXWL... U U U 8 8 4 18.702 +not 16 . d 0100011001000... .......... U U U 4 4 2 18.703 +not 16 . . 0100011001...... A+-DXWL... U U U 8 8 4 18.704 +not 32 . d 0100011010000... .......... U U U 6 6 2 18.705 +not 32 . . 0100011010...... A+-DXWL... U U U 12 12 4 18.706 +or 8 er d 1000...000000... .......... U U U 4 4 2 18.707 +or 8 er . 1000...000...... A+-DXWLdxI U U U 4 4 2 18.708 +or 16 er d 1000...001000... .......... U U U 4 4 2 18.709 +or 16 er . 1000...001...... A+-DXWLdxI U U U 4 4 2 18.710 +or 32 er d 1000...010000... .......... U U U 6 6 2 18.711 +or 32 er . 1000...010...... A+-DXWLdxI U U U 6 6 2 18.712 +or 8 re . 1000...100...... A+-DXWL... U U U 8 8 4 18.713 +or 16 re . 1000...101...... A+-DXWL... U U U 8 8 4 18.714 +or 32 re . 1000...110...... A+-DXWL... U U U 12 12 4 18.715 +ori 16 toc . 0000000000111100 .......... U U U 20 16 12 18.716 +ori 16 tos . 0000000001111100 .......... S S S 20 16 12 18.717 +ori 8 . d 0000000000000... .......... U U U 8 8 2 18.718 +ori 8 . . 0000000000...... A+-DXWL... U U U 12 12 4 18.719 +ori 16 . d 0000000001000... .......... U U U 8 8 2 18.720 +ori 16 . . 0000000001...... A+-DXWL... U U U 12 12 4 18.721 +ori 32 . d 0000000010000... .......... U U U 16 14 2 18.722 +ori 32 . . 0000000010...... A+-DXWL... U U U 20 20 4 18.723 +pack 16 rr . 1000...101000... .......... . . U . . 6 18.724 +pack 16 mm ax7 1000111101001... .......... . . U . . 13 18.725 +pack 16 mm ay7 1000...101001111 .......... . . U . . 13 18.726 +pack 16 mm axy7 1000111101001111 .......... . . U . . 13 18.727 +pack 16 mm . 1000...101001... .......... . . U . . 13 18.728 +pea 32 . . 0100100001...... A..DXWLdx. U U U 6 6 5 18.729 +reset 0 . . 0100111001110000 .......... S S S 0 0 0 18.730 +ror 8 s . 1110...000011... .......... U U U 6 6 8 18.731 +ror 16 s . 1110...001011... .......... U U U 6 6 8 18.732 +ror 32 s . 1110...010011... .......... U U U 8 8 8 18.733 +ror 8 r . 1110...000111... .......... U U U 6 6 8 18.734 +ror 16 r . 1110...001111... .......... U U U 6 6 8 18.735 +ror 32 r . 1110...010111... .......... U U U 8 8 8 18.736 +ror 16 . . 1110011011...... A+-DXWL... U U U 8 8 7 18.737 +rol 8 s . 1110...100011... .......... U U U 6 6 8 18.738 +rol 16 s . 1110...101011... .......... U U U 6 6 8 18.739 +rol 32 s . 1110...110011... .......... U U U 8 8 8 18.740 +rol 8 r . 1110...100111... .......... U U U 6 6 8 18.741 +rol 16 r . 1110...101111... .......... U U U 6 6 8 18.742 +rol 32 r . 1110...110111... .......... U U U 8 8 8 18.743 +rol 16 . . 1110011111...... A+-DXWL... U U U 8 8 7 18.744 +roxr 8 s . 1110...000010... .......... U U U 6 6 12 18.745 +roxr 16 s . 1110...001010... .......... U U U 6 6 12 18.746 +roxr 32 s . 1110...010010... .......... U U U 8 8 12 18.747 +roxr 8 r . 1110...000110... .......... U U U 6 6 12 18.748 +roxr 16 r . 1110...001110... .......... U U U 6 6 12 18.749 +roxr 32 r . 1110...010110... .......... U U U 8 8 12 18.750 +roxr 16 . . 1110010011...... A+-DXWL... U U U 8 8 5 18.751 +roxl 8 s . 1110...100010... .......... U U U 6 6 12 18.752 +roxl 16 s . 1110...101010... .......... U U U 6 6 12 18.753 +roxl 32 s . 1110...110010... .......... U U U 8 8 12 18.754 +roxl 8 r . 1110...100110... .......... U U U 6 6 12 18.755 +roxl 16 r . 1110...101110... .......... U U U 6 6 12 18.756 +roxl 32 r . 1110...110110... .......... U U U 8 8 12 18.757 +roxl 16 . . 1110010111...... A+-DXWL... U U U 8 8 5 18.758 +rtd 32 . . 0100111001110100 .......... . U U . 16 10 18.759 +rte 32 . . 0100111001110011 .......... S S S 20 24 20 bus fault not emulated 18.760 +rtm 32 . . 000001101100.... .......... . . U . . 19 not properly emulated 18.761 +rtr 32 . . 0100111001110111 .......... U U U 20 20 14 18.762 +rts 32 . . 0100111001110101 .......... U U U 16 16 10 18.763 +sbcd 8 rr . 1000...100000... .......... U U U 6 6 4 18.764 +sbcd 8 mm ax7 1000111100001... .......... U U U 18 18 16 18.765 +sbcd 8 mm ay7 1000...100001111 .......... U U U 18 18 16 18.766 +sbcd 8 mm axy7 1000111100001111 .......... U U U 18 18 16 18.767 +sbcd 8 mm . 1000...100001... .......... U U U 18 18 16 18.768 +st 8 . d 0101000011000... .......... U U U 6 4 4 18.769 +st 8 . . 0101000011...... A+-DXWL... U U U 8 8 6 18.770 +sf 8 . d 0101000111000... .......... U U U 4 4 4 18.771 +sf 8 . . 0101000111...... A+-DXWL... U U U 8 8 6 18.772 +scc 8 . d 0101....11000... .......... U U U 4 4 4 18.773 +scc 8 . . 0101....11...... A+-DXWL... U U U 8 8 6 18.774 +stop 0 . . 0100111001110010 .......... S S S 4 4 8 18.775 +sub 8 er d 1001...000000... .......... U U U 4 4 2 18.776 +sub 8 er . 1001...000...... A+-DXWLdxI U U U 4 4 2 18.777 +sub 16 er d 1001...001000... .......... U U U 4 4 2 18.778 +sub 16 er a 1001...001001... .......... U U U 4 4 2 18.779 +sub 16 er . 1001...001...... A+-DXWLdxI U U U 4 4 2 18.780 +sub 32 er d 1001...010000... .......... U U U 6 6 2 18.781 +sub 32 er a 1001...010001... .......... U U U 6 6 2 18.782 +sub 32 er . 1001...010...... A+-DXWLdxI U U U 6 6 2 18.783 +sub 8 re . 1001...100...... A+-DXWL... U U U 8 8 4 18.784 +sub 16 re . 1001...101...... A+-DXWL... U U U 8 8 4 18.785 +sub 32 re . 1001...110...... A+-DXWL... U U U 12 12 4 18.786 +suba 16 . d 1001...011000... .......... U U U 8 8 2 18.787 +suba 16 . a 1001...011001... .......... U U U 8 8 2 18.788 +suba 16 . . 1001...011...... A+-DXWLdxI U U U 8 8 2 18.789 +suba 32 . d 1001...111000... .......... U U U 6 6 2 18.790 +suba 32 . a 1001...111001... .......... U U U 6 6 2 18.791 +suba 32 . . 1001...111...... A+-DXWLdxI U U U 6 6 2 18.792 +subi 8 . d 0000010000000... .......... U U U 8 8 2 18.793 +subi 8 . . 0000010000...... A+-DXWL... U U U 12 12 4 18.794 +subi 16 . d 0000010001000... .......... U U U 8 8 2 18.795 +subi 16 . . 0000010001...... A+-DXWL... U U U 12 12 4 18.796 +subi 32 . d 0000010010000... .......... U U U 16 14 2 18.797 +subi 32 . . 0000010010...... A+-DXWL... U U U 20 20 4 18.798 +subq 8 . d 0101...100000... .......... U U U 4 4 2 18.799 +subq 8 . . 0101...100...... A+-DXWL... U U U 8 8 4 18.800 +subq 16 . d 0101...101000... .......... U U U 4 4 2 18.801 +subq 16 . a 0101...101001... .......... U U U 8 4 2 18.802 +subq 16 . . 0101...101...... A+-DXWL... U U U 8 8 4 18.803 +subq 32 . d 0101...110000... .......... U U U 8 8 2 18.804 +subq 32 . a 0101...110001... .......... U U U 8 8 2 18.805 +subq 32 . . 0101...110...... A+-DXWL... U U U 12 12 4 18.806 +subx 8 rr . 1001...100000... .......... U U U 4 4 2 18.807 +subx 16 rr . 1001...101000... .......... U U U 4 4 2 18.808 +subx 32 rr . 1001...110000... .......... U U U 8 6 2 18.809 +subx 8 mm ax7 1001111100001... .......... U U U 18 18 12 18.810 +subx 8 mm ay7 1001...100001111 .......... U U U 18 18 12 18.811 +subx 8 mm axy7 1001111100001111 .......... U U U 18 18 12 18.812 +subx 8 mm . 1001...100001... .......... U U U 18 18 12 18.813 +subx 16 mm . 1001...101001... .......... U U U 18 18 12 18.814 +subx 32 mm . 1001...110001... .......... U U U 30 30 12 18.815 +swap 32 . . 0100100001000... .......... U U U 4 4 4 18.816 +tas 8 . d 0100101011000... .......... U U U 4 4 4 18.817 +tas 8 . . 0100101011...... A+-DXWL... U U U 14 14 12 18.818 +trap 0 . . 010011100100.... .......... U U U 4 4 4 18.819 +trapt 0 . . 0101000011111100 .......... . . U . . 4 18.820 +trapt 16 . . 0101000011111010 .......... . . U . . 6 18.821 +trapt 32 . . 0101000011111011 .......... . . U . . 8 18.822 +trapf 0 . . 0101000111111100 .......... . . U . . 4 18.823 +trapf 16 . . 0101000111111010 .......... . . U . . 6 18.824 +trapf 32 . . 0101000111111011 .......... . . U . . 8 18.825 +trapcc 0 . . 0101....11111100 .......... . . U . . 4 18.826 +trapcc 16 . . 0101....11111010 .......... . . U . . 6 18.827 +trapcc 32 . . 0101....11111011 .......... . . U . . 8 18.828 +trapv 0 . . 0100111001110110 .......... U U U 4 4 4 18.829 +tst 8 . d 0100101000000... .......... U U U 4 4 2 18.830 +tst 8 . . 0100101000...... A+-DXWL... U U U 4 4 2 18.831 +tst 8 . pcdi 0100101000111010 .......... . . U . . 7 18.832 +tst 8 . pcix 0100101000111011 .......... . . U . . 9 18.833 +tst 8 . i 0100101000111100 .......... . . U . . 6 18.834 +tst 16 . d 0100101001000... .......... U U U 4 4 2 18.835 +tst 16 . a 0100101001001... .......... . . U . . 2 18.836 +tst 16 . . 0100101001...... A+-DXWL... U U U 4 4 2 18.837 +tst 16 . pcdi 0100101001111010 .......... . . U . . 7 18.838 +tst 16 . pcix 0100101001111011 .......... . . U . . 9 18.839 +tst 16 . i 0100101001111100 .......... . . U . . 6 18.840 +tst 32 . d 0100101010000... .......... U U U 4 4 2 18.841 +tst 32 . a 0100101010001... .......... . . U . . 2 18.842 +tst 32 . . 0100101010...... A+-DXWL... U U U 4 4 2 18.843 +tst 32 . pcdi 0100101010111010 .......... . . U . . 7 18.844 +tst 32 . pcix 0100101010111011 .......... . . U . . 9 18.845 +tst 32 . i 0100101010111100 .......... . . U . . 6 18.846 +unlk 32 . a7 0100111001011111 .......... U U U 12 12 6 18.847 +unlk 32 . . 0100111001011... .......... U U U 12 12 6 18.848 +unpk 16 rr . 1000...110000... .......... . . U . . 8 18.849 +unpk 16 mm ax7 1000111110001... .......... . . U . . 13 18.850 +unpk 16 mm ay7 1000...110001111 .......... . . U . . 13 18.851 +unpk 16 mm axy7 1000111110001111 .......... . . U . . 13 18.852 +unpk 16 mm . 1000...110001... .......... . . U . . 13 18.853 + 18.854 + 18.855 + 18.856 +XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX 18.857 +M68KMAKE_OPCODE_HANDLER_BODY 18.858 + 18.859 +M68KMAKE_OP(1010, 0, ., .) 18.860 +{ 18.861 + m68ki_exception_1010(); 18.862 +} 18.863 + 18.864 + 18.865 +M68KMAKE_OP(1111, 0, ., .) 18.866 +{ 18.867 + m68ki_exception_1111(); 18.868 +} 18.869 + 18.870 + 18.871 +M68KMAKE_OP(abcd, 8, rr, .) 18.872 +{ 18.873 + uint* r_dst = &DX; 18.874 + uint src = DY; 18.875 + uint dst = *r_dst; 18.876 + uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1(); 18.877 + 18.878 + if(res > 9) 18.879 + res += 6; 18.880 + res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst); 18.881 + FLAG_X = FLAG_C = (res > 0x99) << 8; 18.882 + if(FLAG_C) 18.883 + res -= 0xa0; 18.884 + 18.885 + FLAG_N = NFLAG_8(res); /* officially undefined */ 18.886 + 18.887 + res = MASK_OUT_ABOVE_8(res); 18.888 + FLAG_Z |= res; 18.889 + 18.890 + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; 18.891 +} 18.892 + 18.893 + 18.894 +M68KMAKE_OP(abcd, 8, mm, ax7) 18.895 +{ 18.896 + uint src = OPER_AY_PD_8(); 18.897 + uint ea = EA_A7_PD_8(); 18.898 + uint dst = m68ki_read_8(ea); 18.899 + uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1(); 18.900 + 18.901 + if(res > 9) 18.902 + res += 6; 18.903 + res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst); 18.904 + FLAG_X = FLAG_C = (res > 0x99) << 8; 18.905 + if(FLAG_C) 18.906 + res -= 0xa0; 18.907 + 18.908 + FLAG_N = NFLAG_8(res); /* officially undefined */ 18.909 + 18.910 + res = MASK_OUT_ABOVE_8(res); 18.911 + FLAG_Z |= res; 18.912 + 18.913 + m68ki_write_8(ea, res); 18.914 +} 18.915 + 18.916 + 18.917 +M68KMAKE_OP(abcd, 8, mm, ay7) 18.918 +{ 18.919 + uint src = OPER_A7_PD_8(); 18.920 + uint ea = EA_AX_PD_8(); 18.921 + uint dst = m68ki_read_8(ea); 18.922 + uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1(); 18.923 + 18.924 + if(res > 9) 18.925 + res += 6; 18.926 + res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst); 18.927 + FLAG_X = FLAG_C = (res > 0x99) << 8; 18.928 + if(FLAG_C) 18.929 + res -= 0xa0; 18.930 + 18.931 + FLAG_N = NFLAG_8(res); /* officially undefined */ 18.932 + 18.933 + res = MASK_OUT_ABOVE_8(res); 18.934 + FLAG_Z |= res; 18.935 + 18.936 + m68ki_write_8(ea, res); 18.937 +} 18.938 + 18.939 + 18.940 +M68KMAKE_OP(abcd, 8, mm, axy7) 18.941 +{ 18.942 + uint src = OPER_A7_PD_8(); 18.943 + uint ea = EA_A7_PD_8(); 18.944 + uint dst = m68ki_read_8(ea); 18.945 + uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1(); 18.946 + 18.947 + if(res > 9) 18.948 + res += 6; 18.949 + res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst); 18.950 + FLAG_X = FLAG_C = (res > 0x99) << 8; 18.951 + if(FLAG_C) 18.952 + res -= 0xa0; 18.953 + 18.954 + FLAG_N = NFLAG_8(res); /* officially undefined */ 18.955 + 18.956 + res = MASK_OUT_ABOVE_8(res); 18.957 + FLAG_Z |= res; 18.958 + 18.959 + m68ki_write_8(ea, res); 18.960 +} 18.961 + 18.962 + 18.963 +M68KMAKE_OP(abcd, 8, mm, .) 18.964 +{ 18.965 + uint src = OPER_AY_PD_8(); 18.966 + uint ea = EA_AX_PD_8(); 18.967 + uint dst = m68ki_read_8(ea); 18.968 + uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1(); 18.969 + 18.970 + if(res > 9) 18.971 + res += 6; 18.972 + res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst); 18.973 + FLAG_X = FLAG_C = (res > 0x99) << 8; 18.974 + if(FLAG_C) 18.975 + res -= 0xa0; 18.976 + 18.977 + FLAG_N = NFLAG_8(res); /* officially undefined */ 18.978 + 18.979 + res = MASK_OUT_ABOVE_8(res); 18.980 + FLAG_Z |= res; 18.981 + 18.982 + m68ki_write_8(ea, res); 18.983 +} 18.984 + 18.985 + 18.986 +M68KMAKE_OP(add, 8, er, d) 18.987 +{ 18.988 + uint* r_dst = &DX; 18.989 + uint src = MASK_OUT_ABOVE_8(DY); 18.990 + uint dst = MASK_OUT_ABOVE_8(*r_dst); 18.991 + uint res = src + dst; 18.992 + 18.993 + FLAG_N = NFLAG_8(res); 18.994 + FLAG_V = VFLAG_ADD_8(src, dst, res); 18.995 + FLAG_X = FLAG_C = CFLAG_8(res); 18.996 + FLAG_Z = MASK_OUT_ABOVE_8(res); 18.997 + 18.998 + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; 18.999 +} 18.1000 + 18.1001 + 18.1002 +M68KMAKE_OP(add, 8, er, .) 18.1003 +{ 18.1004 + uint* r_dst = &DX; 18.1005 + uint src = M68KMAKE_GET_OPER_AY_8; 18.1006 + uint dst = MASK_OUT_ABOVE_8(*r_dst); 18.1007 + uint res = src + dst; 18.1008 + 18.1009 + FLAG_N = NFLAG_8(res); 18.1010 + FLAG_V = VFLAG_ADD_8(src, dst, res); 18.1011 + FLAG_X = FLAG_C = CFLAG_8(res); 18.1012 + FLAG_Z = MASK_OUT_ABOVE_8(res); 18.1013 + 18.1014 + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; 18.1015 +} 18.1016 + 18.1017 + 18.1018 +M68KMAKE_OP(add, 16, er, d) 18.1019 +{ 18.1020 + uint* r_dst = &DX; 18.1021 + uint src = MASK_OUT_ABOVE_16(DY); 18.1022 + uint dst = MASK_OUT_ABOVE_16(*r_dst); 18.1023 + uint res = src + dst; 18.1024 + 18.1025 + FLAG_N = NFLAG_16(res); 18.1026 + FLAG_V = VFLAG_ADD_16(src, dst, res); 18.1027 + FLAG_X = FLAG_C = CFLAG_16(res); 18.1028 + FLAG_Z = MASK_OUT_ABOVE_16(res); 18.1029 + 18.1030 + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; 18.1031 +} 18.1032 + 18.1033 + 18.1034 +M68KMAKE_OP(add, 16, er, a) 18.1035 +{ 18.1036 + uint* r_dst = &DX; 18.1037 + uint src = MASK_OUT_ABOVE_16(AY); 18.1038 + uint dst = MASK_OUT_ABOVE_16(*r_dst); 18.1039 + uint res = src + dst; 18.1040 + 18.1041 + FLAG_N = NFLAG_16(res); 18.1042 + FLAG_V = VFLAG_ADD_16(src, dst, res); 18.1043 + FLAG_X = FLAG_C = CFLAG_16(res); 18.1044 + FLAG_Z = MASK_OUT_ABOVE_16(res); 18.1045 + 18.1046 + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; 18.1047 +} 18.1048 + 18.1049 + 18.1050 +M68KMAKE_OP(add, 16, er, .) 18.1051 +{ 18.1052 + uint* r_dst = &DX; 18.1053 + uint src = M68KMAKE_GET_OPER_AY_16; 18.1054 + uint dst = MASK_OUT_ABOVE_16(*r_dst); 18.1055 + uint res = src + dst; 18.1056 + 18.1057 + FLAG_N = NFLAG_16(res); 18.1058 + FLAG_V = VFLAG_ADD_16(src, dst, res); 18.1059 + FLAG_X = FLAG_C = CFLAG_16(res); 18.1060 + FLAG_Z = MASK_OUT_ABOVE_16(res); 18.1061 + 18.1062 + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; 18.1063 +} 18.1064 + 18.1065 + 18.1066 +M68KMAKE_OP(add, 32, er, d) 18.1067 +{ 18.1068 + uint* r_dst = &DX; 18.1069 + uint src = DY; 18.1070 + uint dst = *r_dst; 18.1071 + uint res = src + dst; 18.1072 + 18.1073 + FLAG_N = NFLAG_32(res); 18.1074 + FLAG_V = VFLAG_ADD_32(src, dst, res); 18.1075 + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); 18.1076 + FLAG_Z = MASK_OUT_ABOVE_32(res); 18.1077 + 18.1078 + *r_dst = FLAG_Z; 18.1079 +} 18.1080 + 18.1081 + 18.1082 +M68KMAKE_OP(add, 32, er, a) 18.1083 +{ 18.1084 + uint* r_dst = &DX; 18.1085 + uint src = AY; 18.1086 + uint dst = *r_dst; 18.1087 + uint res = src + dst; 18.1088 + 18.1089 + FLAG_N = NFLAG_32(res); 18.1090 + FLAG_V = VFLAG_ADD_32(src, dst, res); 18.1091 + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); 18.1092 + FLAG_Z = MASK_OUT_ABOVE_32(res); 18.1093 + 18.1094 + *r_dst = FLAG_Z; 18.1095 +} 18.1096 + 18.1097 + 18.1098 +M68KMAKE_OP(add, 32, er, .) 18.1099 +{ 18.1100 + uint* r_dst = &DX; 18.1101 + uint src = M68KMAKE_GET_OPER_AY_32; 18.1102 + uint dst = *r_dst; 18.1103 + uint res = src + dst; 18.1104 + 18.1105 + FLAG_N = NFLAG_32(res); 18.1106 + FLAG_V = VFLAG_ADD_32(src, dst, res); 18.1107 + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); 18.1108 + FLAG_Z = MASK_OUT_ABOVE_32(res); 18.1109 + 18.1110 + *r_dst = FLAG_Z; 18.1111 +} 18.1112 + 18.1113 + 18.1114 +M68KMAKE_OP(add, 8, re, .) 18.1115 +{ 18.1116 + uint ea = M68KMAKE_GET_EA_AY_8; 18.1117 + uint src = MASK_OUT_ABOVE_8(DX); 18.1118 + uint dst = m68ki_read_8(ea); 18.1119 + uint res = src + dst; 18.1120 + 18.1121 + FLAG_N = NFLAG_8(res); 18.1122 + FLAG_V = VFLAG_ADD_8(src, dst, res); 18.1123 + FLAG_X = FLAG_C = CFLAG_8(res); 18.1124 + FLAG_Z = MASK_OUT_ABOVE_8(res); 18.1125 + 18.1126 + m68ki_write_8(ea, FLAG_Z); 18.1127 +} 18.1128 + 18.1129 + 18.1130 +M68KMAKE_OP(add, 16, re, .) 18.1131 +{ 18.1132 + uint ea = M68KMAKE_GET_EA_AY_16; 18.1133 + uint src = MASK_OUT_ABOVE_16(DX); 18.1134 + uint dst = m68ki_read_16(ea); 18.1135 + uint res = src + dst; 18.1136 + 18.1137 + FLAG_N = NFLAG_16(res); 18.1138 + FLAG_V = VFLAG_ADD_16(src, dst, res); 18.1139 + FLAG_X = FLAG_C = CFLAG_16(res); 18.1140 + FLAG_Z = MASK_OUT_ABOVE_16(res); 18.1141 + 18.1142 + m68ki_write_16(ea, FLAG_Z); 18.1143 +} 18.1144 + 18.1145 + 18.1146 +M68KMAKE_OP(add, 32, re, .) 18.1147 +{ 18.1148 + uint ea = M68KMAKE_GET_EA_AY_32; 18.1149 + uint src = DX; 18.1150 + uint dst = m68ki_read_32(ea); 18.1151 + uint res = src + dst; 18.1152 + 18.1153 + FLAG_N = NFLAG_32(res); 18.1154 + FLAG_V = VFLAG_ADD_32(src, dst, res); 18.1155 + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); 18.1156 + FLAG_Z = MASK_OUT_ABOVE_32(res); 18.1157 + 18.1158 + m68ki_write_32(ea, FLAG_Z); 18.1159 +} 18.1160 + 18.1161 + 18.1162 +M68KMAKE_OP(adda, 16, ., d) 18.1163 +{ 18.1164 + uint* r_dst = &AX; 18.1165 + 18.1166 + *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(DY)); 18.1167 +} 18.1168 + 18.1169 + 18.1170 +M68KMAKE_OP(adda, 16, ., a) 18.1171 +{ 18.1172 + uint* r_dst = &AX; 18.1173 + 18.1174 + *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(AY)); 18.1175 +} 18.1176 + 18.1177 + 18.1178 +M68KMAKE_OP(adda, 16, ., .) 18.1179 +{ 18.1180 + uint* r_dst = &AX; 18.1181 + 18.1182 + *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(M68KMAKE_GET_OPER_AY_16)); 18.1183 +} 18.1184 + 18.1185 + 18.1186 +M68KMAKE_OP(adda, 32, ., d) 18.1187 +{ 18.1188 + uint* r_dst = &AX; 18.1189 + 18.1190 + *r_dst = MASK_OUT_ABOVE_32(*r_dst + DY); 18.1191 +} 18.1192 + 18.1193 + 18.1194 +M68KMAKE_OP(adda, 32, ., a) 18.1195 +{ 18.1196 + uint* r_dst = &AX; 18.1197 + 18.1198 + *r_dst = MASK_OUT_ABOVE_32(*r_dst + AY); 18.1199 +} 18.1200 + 18.1201 + 18.1202 +M68KMAKE_OP(adda, 32, ., .) 18.1203 +{ 18.1204 + uint* r_dst = &AX; 18.1205 + 18.1206 + *r_dst = MASK_OUT_ABOVE_32(*r_dst + M68KMAKE_GET_OPER_AY_32); 18.1207 +} 18.1208 + 18.1209 + 18.1210 +M68KMAKE_OP(addi, 8, ., d) 18.1211 +{ 18.1212 + uint* r_dst = &DY; 18.1213 + uint src = OPER_I_8(); 18.1214 + uint dst = MASK_OUT_ABOVE_8(*r_dst); 18.1215 + uint res = src + dst; 18.1216 + 18.1217 + FLAG_N = NFLAG_8(res); 18.1218 + FLAG_V = VFLAG_ADD_8(src, dst, res); 18.1219 + FLAG_X = FLAG_C = CFLAG_8(res); 18.1220 + FLAG_Z = MASK_OUT_ABOVE_8(res); 18.1221 + 18.1222 + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; 18.1223 +} 18.1224 + 18.1225 + 18.1226 +M68KMAKE_OP(addi, 8, ., .) 18.1227 +{ 18.1228 + uint src = OPER_I_8(); 18.1229 + uint ea = M68KMAKE_GET_EA_AY_8; 18.1230 + uint dst = m68ki_read_8(ea); 18.1231 + uint res = src + dst; 18.1232 + 18.1233 + FLAG_N = NFLAG_8(res); 18.1234 + FLAG_V = VFLAG_ADD_8(src, dst, res); 18.1235 + FLAG_X = FLAG_C = CFLAG_8(res); 18.1236 + FLAG_Z = MASK_OUT_ABOVE_8(res); 18.1237 + 18.1238 + m68ki_write_8(ea, FLAG_Z); 18.1239 +} 18.1240 + 18.1241 + 18.1242 +M68KMAKE_OP(addi, 16, ., d) 18.1243 +{ 18.1244 + uint* r_dst = &DY; 18.1245 + uint src = OPER_I_16(); 18.1246 + uint dst = MASK_OUT_ABOVE_16(*r_dst); 18.1247 + uint res = src + dst; 18.1248 + 18.1249 + FLAG_N = NFLAG_16(res); 18.1250 + FLAG_V = VFLAG_ADD_16(src, dst, res); 18.1251 + FLAG_X = FLAG_C = CFLAG_16(res); 18.1252 + FLAG_Z = MASK_OUT_ABOVE_16(res); 18.1253 + 18.1254 + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; 18.1255 +} 18.1256 + 18.1257 + 18.1258 +M68KMAKE_OP(addi, 16, ., .) 18.1259 +{ 18.1260 + uint src = OPER_I_16(); 18.1261 + uint ea = M68KMAKE_GET_EA_AY_16; 18.1262 + uint dst = m68ki_read_16(ea); 18.1263 + uint res = src + dst; 18.1264 + 18.1265 + FLAG_N = NFLAG_16(res); 18.1266 + FLAG_V = VFLAG_ADD_16(src, dst, res); 18.1267 + FLAG_X = FLAG_C = CFLAG_16(res); 18.1268 + FLAG_Z = MASK_OUT_ABOVE_16(res); 18.1269 + 18.1270 + m68ki_write_16(ea, FLAG_Z); 18.1271 +} 18.1272 + 18.1273 + 18.1274 +M68KMAKE_OP(addi, 32, ., d) 18.1275 +{ 18.1276 + uint* r_dst = &DY; 18.1277 + uint src = OPER_I_32(); 18.1278 + uint dst = *r_dst; 18.1279 + uint res = src + dst; 18.1280 + 18.1281 + FLAG_N = NFLAG_32(res); 18.1282 + FLAG_V = VFLAG_ADD_32(src, dst, res); 18.1283 + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); 18.1284 + FLAG_Z = MASK_OUT_ABOVE_32(res); 18.1285 + 18.1286 + *r_dst = FLAG_Z; 18.1287 +} 18.1288 + 18.1289 + 18.1290 +M68KMAKE_OP(addi, 32, ., .) 18.1291 +{ 18.1292 + uint src = OPER_I_32(); 18.1293 + uint ea = M68KMAKE_GET_EA_AY_32; 18.1294 + uint dst = m68ki_read_32(ea); 18.1295 + uint res = src + dst; 18.1296 + 18.1297 + FLAG_N = NFLAG_32(res); 18.1298 + FLAG_V = VFLAG_ADD_32(src, dst, res); 18.1299 + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); 18.1300 + FLAG_Z = MASK_OUT_ABOVE_32(res); 18.1301 + 18.1302 + m68ki_write_32(ea, FLAG_Z); 18.1303 +} 18.1304 + 18.1305 + 18.1306 +M68KMAKE_OP(addq, 8, ., d) 18.1307 +{ 18.1308 + uint* r_dst = &DY; 18.1309 + uint src = (((REG_IR >> 9) - 1) & 7) + 1; 18.1310 + uint dst = MASK_OUT_ABOVE_8(*r_dst); 18.1311 + uint res = src + dst; 18.1312 + 18.1313 + FLAG_N = NFLAG_8(res); 18.1314 + FLAG_V = VFLAG_ADD_8(src, dst, res); 18.1315 + FLAG_X = FLAG_C = CFLAG_8(res); 18.1316 + FLAG_Z = MASK_OUT_ABOVE_8(res); 18.1317 + 18.1318 + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; 18.1319 +} 18.1320 + 18.1321 + 18.1322 +M68KMAKE_OP(addq, 8, ., .) 18.1323 +{ 18.1324 + uint src = (((REG_IR >> 9) - 1) & 7) + 1; 18.1325 + uint ea = M68KMAKE_GET_EA_AY_8; 18.1326 + uint dst = m68ki_read_8(ea); 18.1327 + uint res = src + dst; 18.1328 + 18.1329 + FLAG_N = NFLAG_8(res); 18.1330 + FLAG_V = VFLAG_ADD_8(src, dst, res); 18.1331 + FLAG_X = FLAG_C = CFLAG_8(res); 18.1332 + FLAG_Z = MASK_OUT_ABOVE_8(res); 18.1333 + 18.1334 + m68ki_write_8(ea, FLAG_Z); 18.1335 +} 18.1336 + 18.1337 + 18.1338 +M68KMAKE_OP(addq, 16, ., d) 18.1339 +{ 18.1340 + uint* r_dst = &DY; 18.1341 + uint src = (((REG_IR >> 9) - 1) & 7) + 1; 18.1342 + uint dst = MASK_OUT_ABOVE_16(*r_dst); 18.1343 + uint res = src + dst; 18.1344 + 18.1345 + FLAG_N = NFLAG_16(res); 18.1346 + FLAG_V = VFLAG_ADD_16(src, dst, res); 18.1347 + FLAG_X = FLAG_C = CFLAG_16(res); 18.1348 + FLAG_Z = MASK_OUT_ABOVE_16(res); 18.1349 + 18.1350 + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; 18.1351 +} 18.1352 + 18.1353 + 18.1354 +M68KMAKE_OP(addq, 16, ., a) 18.1355 +{ 18.1356 + uint* r_dst = &AY; 18.1357 + 18.1358 + *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1); 18.1359 +} 18.1360 + 18.1361 + 18.1362 +M68KMAKE_OP(addq, 16, ., .) 18.1363 +{ 18.1364 + uint src = (((REG_IR >> 9) - 1) & 7) + 1; 18.1365 + uint ea = M68KMAKE_GET_EA_AY_16; 18.1366 + uint dst = m68ki_read_16(ea); 18.1367 + uint res = src + dst; 18.1368 + 18.1369 + FLAG_N = NFLAG_16(res); 18.1370 + FLAG_V = VFLAG_ADD_16(src, dst, res); 18.1371 + FLAG_X = FLAG_C = CFLAG_16(res); 18.1372 + FLAG_Z = MASK_OUT_ABOVE_16(res); 18.1373 + 18.1374 + m68ki_write_16(ea, FLAG_Z); 18.1375 +} 18.1376 + 18.1377 + 18.1378 +M68KMAKE_OP(addq, 32, ., d) 18.1379 +{ 18.1380 + uint* r_dst = &DY; 18.1381 + uint src = (((REG_IR >> 9) - 1) & 7) + 1; 18.1382 + uint dst = *r_dst; 18.1383 + uint res = src + dst; 18.1384 + 18.1385 + FLAG_N = NFLAG_32(res); 18.1386 + FLAG_V = VFLAG_ADD_32(src, dst, res); 18.1387 + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); 18.1388 + FLAG_Z = MASK_OUT_ABOVE_32(res); 18.1389 + 18.1390 + *r_dst = FLAG_Z; 18.1391 +} 18.1392 + 18.1393 + 18.1394 +M68KMAKE_OP(addq, 32, ., a) 18.1395 +{ 18.1396 + uint* r_dst = &AY; 18.1397 + 18.1398 + *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1); 18.1399 +} 18.1400 + 18.1401 + 18.1402 +M68KMAKE_OP(addq, 32, ., .) 18.1403 +{ 18.1404 + uint src = (((REG_IR >> 9) - 1) & 7) + 1; 18.1405 + uint ea = M68KMAKE_GET_EA_AY_32; 18.1406 + uint dst = m68ki_read_32(ea); 18.1407 + uint res = src + dst; 18.1408 + 18.1409 + 18.1410 + FLAG_N = NFLAG_32(res); 18.1411 + FLAG_V = VFLAG_ADD_32(src, dst, res); 18.1412 + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); 18.1413 + FLAG_Z = MASK_OUT_ABOVE_32(res); 18.1414 + 18.1415 + m68ki_write_32(ea, FLAG_Z); 18.1416 +} 18.1417 + 18.1418 + 18.1419 +M68KMAKE_OP(addx, 8, rr, .) 18.1420 +{ 18.1421 + uint* r_dst = &DX; 18.1422 + uint src = MASK_OUT_ABOVE_8(DY); 18.1423 + uint dst = MASK_OUT_ABOVE_8(*r_dst); 18.1424 + uint res = src + dst + XFLAG_AS_1(); 18.1425 + 18.1426 + FLAG_N = NFLAG_8(res); 18.1427 + FLAG_V = VFLAG_ADD_8(src, dst, res); 18.1428 + FLAG_X = FLAG_C = CFLAG_8(res); 18.1429 + 18.1430 + res = MASK_OUT_ABOVE_8(res); 18.1431 + FLAG_Z |= res; 18.1432 + 18.1433 + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; 18.1434 +} 18.1435 + 18.1436 + 18.1437 +M68KMAKE_OP(addx, 16, rr, .) 18.1438 +{ 18.1439 + uint* r_dst = &DX; 18.1440 + uint src = MASK_OUT_ABOVE_16(DY); 18.1441 + uint dst = MASK_OUT_ABOVE_16(*r_dst); 18.1442 + uint res = src + dst + XFLAG_AS_1(); 18.1443 + 18.1444 + FLAG_N = NFLAG_16(res); 18.1445 + FLAG_V = VFLAG_ADD_16(src, dst, res); 18.1446 + FLAG_X = FLAG_C = CFLAG_16(res); 18.1447 + 18.1448 + res = MASK_OUT_ABOVE_16(res); 18.1449 + FLAG_Z |= res; 18.1450 + 18.1451 + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; 18.1452 +} 18.1453 + 18.1454 + 18.1455 +M68KMAKE_OP(addx, 32, rr, .) 18.1456 +{ 18.1457 + uint* r_dst = &DX; 18.1458 + uint src = DY; 18.1459 + uint dst = *r_dst; 18.1460 + uint res = src + dst + XFLAG_AS_1(); 18.1461 + 18.1462 + FLAG_N = NFLAG_32(res); 18.1463 + FLAG_V = VFLAG_ADD_32(src, dst, res); 18.1464 + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); 18.1465 + 18.1466 + res = MASK_OUT_ABOVE_32(res); 18.1467 + FLAG_Z |= res; 18.1468 + 18.1469 + *r_dst = res; 18.1470 +} 18.1471 + 18.1472 + 18.1473 +M68KMAKE_OP(addx, 8, mm, ax7) 18.1474 +{ 18.1475 + uint src = OPER_AY_PD_8(); 18.1476 + uint ea = EA_A7_PD_8(); 18.1477 + uint dst = m68ki_read_8(ea); 18.1478 + uint res = src + dst + XFLAG_AS_1(); 18.1479 + 18.1480 + FLAG_N = NFLAG_8(res); 18.1481 + FLAG_V = VFLAG_ADD_8(src, dst, res); 18.1482 + FLAG_X = FLAG_C = CFLAG_8(res); 18.1483 + 18.1484 + res = MASK_OUT_ABOVE_8(res); 18.1485 + FLAG_Z |= res; 18.1486 + 18.1487 + m68ki_write_8(ea, res); 18.1488 +} 18.1489 + 18.1490 + 18.1491 +M68KMAKE_OP(addx, 8, mm, ay7) 18.1492 +{ 18.1493 + uint src = OPER_A7_PD_8(); 18.1494 + uint ea = EA_AX_PD_8(); 18.1495 + uint dst = m68ki_read_8(ea); 18.1496 + uint res = src + dst + XFLAG_AS_1(); 18.1497 + 18.1498 + FLAG_N = NFLAG_8(res); 18.1499 + FLAG_V = VFLAG_ADD_8(src, dst, res); 18.1500 + FLAG_X = FLAG_C = CFLAG_8(res); 18.1501 + 18.1502 + res = MASK_OUT_ABOVE_8(res); 18.1503 + FLAG_Z |= res; 18.1504 + 18.1505 + m68ki_write_8(ea, res); 18.1506 +} 18.1507 + 18.1508 + 18.1509 +M68KMAKE_OP(addx, 8, mm, axy7) 18.1510 +{ 18.1511 + uint src = OPER_A7_PD_8(); 18.1512 + uint ea = EA_A7_PD_8(); 18.1513 + uint dst = m68ki_read_8(ea); 18.1514 + uint res = src + dst + XFLAG_AS_1(); 18.1515 + 18.1516 + FLAG_N = NFLAG_8(res); 18.1517 + FLAG_V = VFLAG_ADD_8(src, dst, res); 18.1518 + FLAG_X = FLAG_C = CFLAG_8(res); 18.1519 + 18.1520 + res = MASK_OUT_ABOVE_8(res); 18.1521 + FLAG_Z |= res; 18.1522 + 18.1523 + m68ki_write_8(ea, res); 18.1524 +} 18.1525 + 18.1526 + 18.1527 +M68KMAKE_OP(addx, 8, mm, .) 18.1528 +{ 18.1529 + uint src = OPER_AY_PD_8(); 18.1530 + uint ea = EA_AX_PD_8(); 18.1531 + uint dst = m68ki_read_8(ea); 18.1532 + uint res = src + dst + XFLAG_AS_1(); 18.1533 + 18.1534 + FLAG_N = NFLAG_8(res); 18.1535 + FLAG_V = VFLAG_ADD_8(src, dst, res); 18.1536 + FLAG_X = FLAG_C = CFLAG_8(res); 18.1537 + 18.1538 + res = MASK_OUT_ABOVE_8(res); 18.1539 + FLAG_Z |= res; 18.1540 + 18.1541 + m68ki_write_8(ea, res); 18.1542 +} 18.1543 + 18.1544 + 18.1545 +M68KMAKE_OP(addx, 16, mm, .) 18.1546 +{ 18.1547 + uint src = OPER_AY_PD_16(); 18.1548 + uint ea = EA_AX_PD_16(); 18.1549 + uint dst = m68ki_read_16(ea); 18.1550 + uint res = src + dst + XFLAG_AS_1(); 18.1551 + 18.1552 + FLAG_N = NFLAG_16(res); 18.1553 + FLAG_V = VFLAG_ADD_16(src, dst, res); 18.1554 + FLAG_X = FLAG_C = CFLAG_16(res); 18.1555 + 18.1556 + res = MASK_OUT_ABOVE_16(res); 18.1557 + FLAG_Z |= res; 18.1558 + 18.1559 + m68ki_write_16(ea, res); 18.1560 +} 18.1561 + 18.1562 + 18.1563 +M68KMAKE_OP(addx, 32, mm, .) 18.1564 +{ 18.1565 + uint src = OPER_AY_PD_32(); 18.1566 + uint ea = EA_AX_PD_32(); 18.1567 + uint dst = m68ki_read_32(ea); 18.1568 + uint res = src + dst + XFLAG_AS_1(); 18.1569 + 18.1570 + FLAG_N = NFLAG_32(res); 18.1571 + FLAG_V = VFLAG_ADD_32(src, dst, res); 18.1572 + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); 18.1573 + 18.1574 + res = MASK_OUT_ABOVE_32(res); 18.1575 + FLAG_Z |= res; 18.1576 + 18.1577 + m68ki_write_32(ea, res); 18.1578 +} 18.1579 + 18.1580 + 18.1581 +M68KMAKE_OP(and, 8, er, d) 18.1582 +{ 18.1583 + FLAG_Z = MASK_OUT_ABOVE_8(DX &= (DY | 0xffffff00)); 18.1584 + 18.1585 + FLAG_N = NFLAG_8(FLAG_Z); 18.1586 + FLAG_C = CFLAG_CLEAR; 18.1587 + FLAG_V = VFLAG_CLEAR; 18.1588 +} 18.1589 + 18.1590 + 18.1591 +M68KMAKE_OP(and, 8, er, .) 18.1592 +{ 18.1593 + FLAG_Z = MASK_OUT_ABOVE_8(DX &= (M68KMAKE_GET_OPER_AY_8 | 0xffffff00)); 18.1594 + 18.1595 + FLAG_N = NFLAG_8(FLAG_Z); 18.1596 + FLAG_C = CFLAG_CLEAR; 18.1597 + FLAG_V = VFLAG_CLEAR; 18.1598 +} 18.1599 + 18.1600 + 18.1601 +M68KMAKE_OP(and, 16, er, d) 18.1602 +{ 18.1603 + FLAG_Z = MASK_OUT_ABOVE_16(DX &= (DY | 0xffff0000)); 18.1604 + 18.1605 + FLAG_N = NFLAG_16(FLAG_Z); 18.1606 + FLAG_C = CFLAG_CLEAR; 18.1607 + FLAG_V = VFLAG_CLEAR; 18.1608 +} 18.1609 + 18.1610 + 18.1611 +M68KMAKE_OP(and, 16, er, .) 18.1612 +{ 18.1613 + FLAG_Z = MASK_OUT_ABOVE_16(DX &= (M68KMAKE_GET_OPER_AY_16 | 0xffff0000)); 18.1614 + 18.1615 + FLAG_N = NFLAG_16(FLAG_Z); 18.1616 + FLAG_C = CFLAG_CLEAR; 18.1617 + FLAG_V = VFLAG_CLEAR; 18.1618 +} 18.1619 + 18.1620 + 18.1621 +M68KMAKE_OP(and, 32, er, d) 18.1622 +{ 18.1623 + FLAG_Z = DX &= DY; 18.1624 + 18.1625 + FLAG_N = NFLAG_32(FLAG_Z); 18.1626 + FLAG_C = CFLAG_CLEAR; 18.1627 + FLAG_V = VFLAG_CLEAR; 18.1628 +} 18.1629 + 18.1630 + 18.1631 +M68KMAKE_OP(and, 32, er, .) 18.1632 +{ 18.1633 + FLAG_Z = DX &= M68KMAKE_GET_OPER_AY_32; 18.1634 + 18.1635 + FLAG_N = NFLAG_32(FLAG_Z); 18.1636 + FLAG_C = CFLAG_CLEAR; 18.1637 + FLAG_V = VFLAG_CLEAR; 18.1638 +} 18.1639 + 18.1640 + 18.1641 +M68KMAKE_OP(and, 8, re, .) 18.1642 +{ 18.1643 + uint ea = M68KMAKE_GET_EA_AY_8; 18.1644 + uint res = DX & m68ki_read_8(ea); 18.1645 + 18.1646 + FLAG_N = NFLAG_8(res); 18.1647 + FLAG_C = CFLAG_CLEAR; 18.1648 + FLAG_V = VFLAG_CLEAR; 18.1649 + FLAG_Z = MASK_OUT_ABOVE_8(res); 18.1650 + 18.1651 + m68ki_write_8(ea, FLAG_Z); 18.1652 +} 18.1653 + 18.1654 + 18.1655 +M68KMAKE_OP(and, 16, re, .) 18.1656 +{ 18.1657 + uint ea = M68KMAKE_GET_EA_AY_16; 18.1658 + uint res = DX & m68ki_read_16(ea); 18.1659 + 18.1660 + FLAG_N = NFLAG_16(res); 18.1661 + FLAG_C = CFLAG_CLEAR; 18.1662 + FLAG_V = VFLAG_CLEAR; 18.1663 + FLAG_Z = MASK_OUT_ABOVE_16(res); 18.1664 + 18.1665 + m68ki_write_16(ea, FLAG_Z); 18.1666 +} 18.1667 + 18.1668 + 18.1669 +M68KMAKE_OP(and, 32, re, .) 18.1670 +{ 18.1671 + uint ea = M68KMAKE_GET_EA_AY_32; 18.1672 + uint res = DX & m68ki_read_32(ea); 18.1673 + 18.1674 + FLAG_N = NFLAG_32(res); 18.1675 + FLAG_Z = res; 18.1676 + FLAG_C = CFLAG_CLEAR; 18.1677 + FLAG_V = VFLAG_CLEAR; 18.1678 + 18.1679 + m68ki_write_32(ea, res); 18.1680 +} 18.1681 + 18.1682 + 18.1683 +M68KMAKE_OP(andi, 8, ., d) 18.1684 +{ 18.1685 + FLAG_Z = MASK_OUT_ABOVE_8(DY &= (OPER_I_8() | 0xffffff00)); 18.1686 + 18.1687 + FLAG_N = NFLAG_8(FLAG_Z); 18.1688 + FLAG_C = CFLAG_CLEAR; 18.1689 + FLAG_V = VFLAG_CLEAR; 18.1690 +} 18.1691 + 18.1692 + 18.1693 +M68KMAKE_OP(andi, 8, ., .) 18.1694 +{ 18.1695 + uint src = OPER_I_8(); 18.1696 + uint ea = M68KMAKE_GET_EA_AY_8; 18.1697 + uint res = src & m68ki_read_8(ea); 18.1698 + 18.1699 + FLAG_N = NFLAG_8(res); 18.1700 + FLAG_Z = res; 18.1701 + FLAG_C = CFLAG_CLEAR; 18.1702 + FLAG_V = VFLAG_CLEAR; 18.1703 + 18.1704 + m68ki_write_8(ea, res); 18.1705 +} 18.1706 + 18.1707 + 18.1708 +M68KMAKE_OP(andi, 16, ., d) 18.1709 +{ 18.1710 + FLAG_Z = MASK_OUT_ABOVE_16(DY &= (OPER_I_16() | 0xffff0000)); 18.1711 + 18.1712 + FLAG_N = NFLAG_16(FLAG_Z); 18.1713 + FLAG_C = CFLAG_CLEAR; 18.1714 + FLAG_V = VFLAG_CLEAR; 18.1715 +} 18.1716 + 18.1717 + 18.1718 +M68KMAKE_OP(andi, 16, ., .) 18.1719 +{ 18.1720 + uint src = OPER_I_16(); 18.1721 + uint ea = M68KMAKE_GET_EA_AY_16; 18.1722 + uint res = src & m68ki_read_16(ea); 18.1723 + 18.1724 + FLAG_N = NFLAG_16(res); 18.1725 + FLAG_Z = res; 18.1726 + FLAG_C = CFLAG_CLEAR; 18.1727 + FLAG_V = VFLAG_CLEAR; 18.1728 + 18.1729 + m68ki_write_16(ea, res); 18.1730 +} 18.1731 + 18.1732 + 18.1733 +M68KMAKE_OP(andi, 32, ., d) 18.1734 +{ 18.1735 + FLAG_Z = DY &= (OPER_I_32()); 18.1736 + 18.1737 + FLAG_N = NFLAG_32(FLAG_Z); 18.1738 + FLAG_C = CFLAG_CLEAR; 18.1739 + FLAG_V = VFLAG_CLEAR; 18.1740 +} 18.1741 + 18.1742 + 18.1743 +M68KMAKE_OP(andi, 32, ., .) 18.1744 +{ 18.1745 + uint src = OPER_I_32(); 18.1746 + uint ea = M68KMAKE_GET_EA_AY_32; 18.1747 + uint res = src & m68ki_read_32(ea); 18.1748 + 18.1749 + FLAG_N = NFLAG_32(res); 18.1750 + FLAG_Z = res; 18.1751 + FLAG_C = CFLAG_CLEAR; 18.1752 + FLAG_V = VFLAG_CLEAR; 18.1753 + 18.1754 + m68ki_write_32(ea, res); 18.1755 +} 18.1756 + 18.1757 + 18.1758 +M68KMAKE_OP(andi, 16, toc, .) 18.1759 +{ 18.1760 + m68ki_set_ccr(m68ki_get_ccr() & OPER_I_16()); 18.1761 +} 18.1762 + 18.1763 + 18.1764 +M68KMAKE_OP(andi, 16, tos, .) 18.1765 +{ 18.1766 + if(FLAG_S) 18.1767 + { 18.1768 + uint src = OPER_I_16(); 18.1769 + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ 18.1770 + m68ki_set_sr(m68ki_get_sr() & src); 18.1771 + return; 18.1772 + } 18.1773 + m68ki_exception_privilege_violation(); 18.1774 +} 18.1775 + 18.1776 + 18.1777 +M68KMAKE_OP(asr, 8, s, .) 18.1778 +{ 18.1779 + uint* r_dst = &DY; 18.1780 + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; 18.1781 + uint src = MASK_OUT_ABOVE_8(*r_dst); 18.1782 + uint res = src >> shift; 18.1783 + 18.1784 + if(GET_MSB_8(src)) 18.1785 + res |= m68ki_shift_8_table[shift]; 18.1786 + 18.1787 + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; 18.1788 + 18.1789 + FLAG_N = NFLAG_8(res); 18.1790 + FLAG_Z = res; 18.1791 + FLAG_V = VFLAG_CLEAR; 18.1792 + FLAG_X = FLAG_C = src << (9-shift); 18.1793 +} 18.1794 + 18.1795 + 18.1796 +M68KMAKE_OP(asr, 16, s, .) 18.1797 +{ 18.1798 + uint* r_dst = &DY; 18.1799 + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; 18.1800 + uint src = MASK_OUT_ABOVE_16(*r_dst); 18.1801 + uint res = src >> shift; 18.1802 + 18.1803 + if(GET_MSB_16(src)) 18.1804 + res |= m68ki_shift_16_table[shift]; 18.1805 + 18.1806 + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; 18.1807 + 18.1808 + FLAG_N = NFLAG_16(res); 18.1809 + FLAG_Z = res; 18.1810 + FLAG_V = VFLAG_CLEAR; 18.1811 + FLAG_X = FLAG_C = src << (9-shift); 18.1812 +} 18.1813 + 18.1814 + 18.1815 +M68KMAKE_OP(asr, 32, s, .) 18.1816 +{ 18.1817 + uint* r_dst = &DY; 18.1818 + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; 18.1819 + uint src = *r_dst; 18.1820 + uint res = src >> shift; 18.1821 + 18.1822 + if(GET_MSB_32(src)) 18.1823 + res |= m68ki_shift_32_table[shift]; 18.1824 + 18.1825 + *r_dst = res; 18.1826 + 18.1827 + FLAG_N = NFLAG_32(res); 18.1828 + FLAG_Z = res; 18.1829 + FLAG_V = VFLAG_CLEAR; 18.1830 + FLAG_X = FLAG_C = src << (9-shift); 18.1831 +} 18.1832 + 18.1833 + 18.1834 +M68KMAKE_OP(asr, 8, r, .) 18.1835 +{ 18.1836 + uint* r_dst = &DY; 18.1837 + uint shift = DX & 0x3f; 18.1838 + uint src = MASK_OUT_ABOVE_8(*r_dst); 18.1839 + uint res = src >> shift; 18.1840 + 18.1841 + if(shift != 0) 18.1842 + { 18.1843 + USE_CYCLES(shift<<CYC_SHIFT); 18.1844 + 18.1845 + if(shift < 8) 18.1846 + { 18.1847 + if(GET_MSB_8(src)) 18.1848 + res |= m68ki_shift_8_table[shift]; 18.1849 + 18.1850 + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; 18.1851 + 18.1852 + FLAG_X = FLAG_C = src << (9-shift); 18.1853 + FLAG_N = NFLAG_8(res); 18.1854 + FLAG_Z = res; 18.1855 + FLAG_V = VFLAG_CLEAR; 18.1856 + return; 18.1857 + } 18.1858 + 18.1859 + if(GET_MSB_8(src)) 18.1860 + { 18.1861 + *r_dst |= 0xff; 18.1862 + FLAG_C = CFLAG_SET; 18.1863 + FLAG_X = XFLAG_SET; 18.1864 + FLAG_N = NFLAG_SET; 18.1865 + FLAG_Z = ZFLAG_CLEAR; 18.1866 + FLAG_V = VFLAG_CLEAR; 18.1867 + return; 18.1868 + } 18.1869 + 18.1870 + *r_dst &= 0xffffff00; 18.1871 + FLAG_C = CFLAG_CLEAR; 18.1872 + FLAG_X = XFLAG_CLEAR; 18.1873 + FLAG_N = NFLAG_CLEAR; 18.1874 + FLAG_Z = ZFLAG_SET; 18.1875 + FLAG_V = VFLAG_CLEAR; 18.1876 + return; 18.1877 + } 18.1878 + 18.1879 + FLAG_C = CFLAG_CLEAR; 18.1880 + FLAG_N = NFLAG_8(src); 18.1881 + FLAG_Z = src; 18.1882 + FLAG_V = VFLAG_CLEAR; 18.1883 +} 18.1884 + 18.1885 + 18.1886 +M68KMAKE_OP(asr, 16, r, .) 18.1887 +{ 18.1888 + uint* r_dst = &DY; 18.1889 + uint shift = DX & 0x3f; 18.1890 + uint src = MASK_OUT_ABOVE_16(*r_dst); 18.1891 + uint res = src >> shift; 18.1892 + 18.1893 + if(shift != 0) 18.1894 + { 18.1895 + USE_CYCLES(shift<<CYC_SHIFT); 18.1896 + 18.1897 + if(shift < 16) 18.1898 + { 18.1899 + if(GET_MSB_16(src)) 18.1900 + res |= m68ki_shift_16_table[shift]; 18.1901 + 18.1902 + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; 18.1903 + 18.1904 + FLAG_C = FLAG_X = (src >> (shift - 1))<<8; 18.1905 + FLAG_N = NFLAG_16(res); 18.1906 + FLAG_Z = res; 18.1907 + FLAG_V = VFLAG_CLEAR; 18.1908 + return; 18.1909 + } 18.1910 + 18.1911 + if(GET_MSB_16(src)) 18.1912 + { 18.1913 + *r_dst |= 0xffff; 18.1914 + FLAG_C = CFLAG_SET; 18.1915 + FLAG_X = XFLAG_SET; 18.1916 + FLAG_N = NFLAG_SET; 18.1917 + FLAG_Z = ZFLAG_CLEAR; 18.1918 + FLAG_V = VFLAG_CLEAR; 18.1919 + return; 18.1920 + } 18.1921 + 18.1922 + *r_dst &= 0xffff0000; 18.1923 + FLAG_C = CFLAG_CLEAR; 18.1924 + FLAG_X = XFLAG_CLEAR; 18.1925 + FLAG_N = NFLAG_CLEAR; 18.1926 + FLAG_Z = ZFLAG_SET; 18.1927 + FLAG_V = VFLAG_CLEAR; 18.1928 + return; 18.1929 + } 18.1930 + 18.1931 + FLAG_C = CFLAG_CLEAR; 18.1932 + FLAG_N = NFLAG_16(src); 18.1933 + FLAG_Z = src; 18.1934 + FLAG_V = VFLAG_CLEAR; 18.1935 +} 18.1936 + 18.1937 + 18.1938 +M68KMAKE_OP(asr, 32, r, .) 18.1939 +{ 18.1940 + uint* r_dst = &DY; 18.1941 + uint shift = DX & 0x3f; 18.1942 + uint src = *r_dst; 18.1943 + uint res = src >> shift; 18.1944 + 18.1945 + if(shift != 0) 18.1946 + { 18.1947 + USE_CYCLES(shift<<CYC_SHIFT); 18.1948 + 18.1949 + if(shift < 32) 18.1950 + { 18.1951 + if(GET_MSB_32(src)) 18.1952 + res |= m68ki_shift_32_table[shift]; 18.1953 + 18.1954 + *r_dst = res; 18.1955 + 18.1956 + FLAG_C = FLAG_X = (src >> (shift - 1))<<8; 18.1957 + FLAG_N = NFLAG_32(res); 18.1958 + FLAG_Z = res; 18.1959 + FLAG_V = VFLAG_CLEAR; 18.1960 + return; 18.1961 + } 18.1962 + 18.1963 + if(GET_MSB_32(src)) 18.1964 + { 18.1965 + *r_dst = 0xffffffff; 18.1966 + FLAG_C = CFLAG_SET; 18.1967 + FLAG_X = XFLAG_SET; 18.1968 + FLAG_N = NFLAG_SET; 18.1969 + FLAG_Z = ZFLAG_CLEAR; 18.1970 + FLAG_V = VFLAG_CLEAR; 18.1971 + return; 18.1972 + } 18.1973 + 18.1974 + *r_dst = 0; 18.1975 + FLAG_C = CFLAG_CLEAR; 18.1976 + FLAG_X = XFLAG_CLEAR; 18.1977 + FLAG_N = NFLAG_CLEAR; 18.1978 + FLAG_Z = ZFLAG_SET; 18.1979 + FLAG_V = VFLAG_CLEAR; 18.1980 + return; 18.1981 + } 18.1982 + 18.1983 + FLAG_C = CFLAG_CLEAR; 18.1984 + FLAG_N = NFLAG_32(src); 18.1985 + FLAG_Z = src; 18.1986 + FLAG_V = VFLAG_CLEAR; 18.1987 +} 18.1988 + 18.1989 + 18.1990 +M68KMAKE_OP(asr, 16, ., .) 18.1991 +{ 18.1992 + uint ea = M68KMAKE_GET_EA_AY_16; 18.1993 + uint src = m68ki_read_16(ea); 18.1994 + uint res = src >> 1; 18.1995 + 18.1996 + if(GET_MSB_16(src)) 18.1997 + res |= 0x8000; 18.1998 + 18.1999 + m68ki_write_16(ea, res); 18.2000 + 18.2001 + FLAG_N = NFLAG_16(res); 18.2002 + FLAG_Z = res; 18.2003 + FLAG_V = VFLAG_CLEAR; 18.2004 + FLAG_C = FLAG_X = src << 8; 18.2005 +} 18.2006 + 18.2007 + 18.2008 +M68KMAKE_OP(asl, 8, s, .) 18.2009 +{ 18.2010 + uint* r_dst = &DY; 18.2011 + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; 18.2012 + uint src = MASK_OUT_ABOVE_8(*r_dst); 18.2013 + uint res = MASK_OUT_ABOVE_8(src << shift); 18.2014 + 18.2015 + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; 18.2016 + 18.2017 + FLAG_X = FLAG_C = src << shift; 18.2018 + FLAG_N = NFLAG_8(res); 18.2019 + FLAG_Z = res; 18.2020 + src &= m68ki_shift_8_table[shift + 1]; 18.2021 + FLAG_V = (!(src == 0 || (src == m68ki_shift_8_table[shift + 1] && shift < 8)))<<7; 18.2022 +} 18.2023 + 18.2024 + 18.2025 +M68KMAKE_OP(asl, 16, s, .) 18.2026 +{ 18.2027 + uint* r_dst = &DY; 18.2028 + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; 18.2029 + uint src = MASK_OUT_ABOVE_16(*r_dst); 18.2030 + uint res = MASK_OUT_ABOVE_16(src << shift); 18.2031 + 18.2032 + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; 18.2033 + 18.2034 + FLAG_N = NFLAG_16(res); 18.2035 + FLAG_Z = res; 18.2036 + FLAG_X = FLAG_C = src >> (8-shift); 18.2037 + src &= m68ki_shift_16_table[shift + 1]; 18.2038 + FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7; 18.2039 +} 18.2040 + 18.2041 + 18.2042 +M68KMAKE_OP(asl, 32, s, .) 18.2043 +{ 18.2044 + uint* r_dst = &DY; 18.2045 + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; 18.2046 + uint src = *r_dst; 18.2047 + uint res = MASK_OUT_ABOVE_32(src << shift); 18.2048 + 18.2049 + *r_dst = res; 18.2050 + 18.2051 + FLAG_N = NFLAG_32(res); 18.2052 + FLAG_Z = res; 18.2053 + FLAG_X = FLAG_C = src >> (24-shift); 18.2054 + src &= m68ki_shift_32_table[shift + 1]; 18.2055 + FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7; 18.2056 +} 18.2057 + 18.2058 + 18.2059 +M68KMAKE_OP(asl, 8, r, .) 18.2060 +{ 18.2061 + uint* r_dst = &DY; 18.2062 + uint shift = DX & 0x3f; 18.2063 + uint src = MASK_OUT_ABOVE_8(*r_dst); 18.2064 + uint res = MASK_OUT_ABOVE_8(src << shift); 18.2065 + 18.2066 + if(shift != 0) 18.2067 + { 18.2068 + USE_CYCLES(shift<<CYC_SHIFT); 18.2069 + 18.2070 + if(shift < 8) 18.2071 + { 18.2072 + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; 18.2073 + FLAG_X = FLAG_C = src << shift; 18.2074 + FLAG_N = NFLAG_8(res); 18.2075 + FLAG_Z = res; 18.2076 + src &= m68ki_shift_8_table[shift + 1]; 18.2077 + FLAG_V = (!(src == 0 || src == m68ki_shift_8_table[shift + 1]))<<7; 18.2078 + return; 18.2079 + } 18.2080 + 18.2081 + *r_dst &= 0xffffff00; 18.2082 + FLAG_X = FLAG_C = ((shift == 8 ? src & 1 : 0))<<8; 18.2083 + FLAG_N = NFLAG_CLEAR; 18.2084 + FLAG_Z = ZFLAG_SET; 18.2085 + FLAG_V = (!(src == 0))<<7; 18.2086 + return; 18.2087 + } 18.2088 + 18.2089 + FLAG_C = CFLAG_CLEAR; 18.2090 + FLAG_N = NFLAG_8(src); 18.2091 + FLAG_Z = src; 18.2092 + FLAG_V = VFLAG_CLEAR; 18.2093 +} 18.2094 + 18.2095 + 18.2096 +M68KMAKE_OP(asl, 16, r, .) 18.2097 +{ 18.2098 + uint* r_dst = &DY; 18.2099 + uint shift = DX & 0x3f; 18.2100 + uint src = MASK_OUT_ABOVE_16(*r_dst); 18.2101 + uint res = MASK_OUT_ABOVE_16(src << shift); 18.2102 + 18.2103 + if(shift != 0) 18.2104 + { 18.2105 + USE_CYCLES(shift<<CYC_SHIFT); 18.2106 + 18.2107 + if(shift < 16) 18.2108 + { 18.2109 + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; 18.2110 + FLAG_X = FLAG_C = (src << shift) >> 8; 18.2111 + FLAG_N = NFLAG_16(res); 18.2112 + FLAG_Z = res; 18.2113 + src &= m68ki_shift_16_table[shift + 1]; 18.2114 + FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7; 18.2115 + return; 18.2116 + } 18.2117 + 18.2118 + *r_dst &= 0xffff0000; 18.2119 + FLAG_X = FLAG_C = ((shift == 16 ? src & 1 : 0))<<8; 18.2120 + FLAG_N = NFLAG_CLEAR; 18.2121 + FLAG_Z = ZFLAG_SET; 18.2122 + FLAG_V = (!(src == 0))<<7; 18.2123 + return; 18.2124 + } 18.2125 + 18.2126 + FLAG_C = CFLAG_CLEAR; 18.2127 + FLAG_N = NFLAG_16(src); 18.2128 + FLAG_Z = src; 18.2129 + FLAG_V = VFLAG_CLEAR; 18.2130 +} 18.2131 + 18.2132 + 18.2133 +M68KMAKE_OP(asl, 32, r, .) 18.2134 +{ 18.2135 + uint* r_dst = &DY; 18.2136 + uint shift = DX & 0x3f; 18.2137 + uint src = *r_dst; 18.2138 + uint res = MASK_OUT_ABOVE_32(src << shift); 18.2139 + 18.2140 + if(shift != 0) 18.2141 + { 18.2142 + USE_CYCLES(shift<<CYC_SHIFT); 18.2143 + 18.2144 + if(shift < 32) 18.2145 + { 18.2146 + *r_dst = res; 18.2147 + FLAG_X = FLAG_C = (src >> (32 - shift)) << 8; 18.2148 + FLAG_N = NFLAG_32(res); 18.2149 + FLAG_Z = res; 18.2150 + src &= m68ki_shift_32_table[shift + 1]; 18.2151 + FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7; 18.2152 + return; 18.2153 + } 18.2154 + 18.2155 + *r_dst = 0; 18.2156 + FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8; 18.2157 + FLAG_N = NFLAG_CLEAR; 18.2158 + FLAG_Z = ZFLAG_SET; 18.2159 + FLAG_V = (!(src == 0))<<7; 18.2160 + return; 18.2161 + } 18.2162 + 18.2163 + FLAG_C = CFLAG_CLEAR; 18.2164 + FLAG_N = NFLAG_32(src); 18.2165 + FLAG_Z = src; 18.2166 + FLAG_V = VFLAG_CLEAR; 18.2167 +} 18.2168 + 18.2169 + 18.2170 +M68KMAKE_OP(asl, 16, ., .) 18.2171 +{ 18.2172 + uint ea = M68KMAKE_GET_EA_AY_16; 18.2173 + uint src = m68ki_read_16(ea); 18.2174 + uint res = MASK_OUT_ABOVE_16(src << 1); 18.2175 + 18.2176 + m68ki_write_16(ea, res); 18.2177 + 18.2178 + FLAG_N = NFLAG_16(res); 18.2179 + FLAG_Z = res; 18.2180 + FLAG_X = FLAG_C = src >> 7; 18.2181 + src &= 0xc000; 18.2182 + FLAG_V = (!(src == 0 || src == 0xc000))<<7; 18.2183 +} 18.2184 + 18.2185 + 18.2186 +M68KMAKE_OP(bcc, 8, ., .) 18.2187 +{ 18.2188 + if(M68KMAKE_CC) 18.2189 + { 18.2190 + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ 18.2191 + m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR)); 18.2192 + return; 18.2193 + } 18.2194 + USE_CYCLES(CYC_BCC_NOTAKE_B); 18.2195 +} 18.2196 + 18.2197 + 18.2198 +M68KMAKE_OP(bcc, 16, ., .) 18.2199 +{ 18.2200 + if(M68KMAKE_CC) 18.2201 + { 18.2202 + uint offset = OPER_I_16(); 18.2203 + REG_PC -= 2; 18.2204 + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ 18.2205 + m68ki_branch_16(offset); 18.2206 + return; 18.2207 + } 18.2208 + REG_PC += 2; 18.2209 + USE_CYCLES(CYC_BCC_NOTAKE_W); 18.2210 +} 18.2211 + 18.2212 + 18.2213 +M68KMAKE_OP(bcc, 32, ., .) 18.2214 +{ 18.2215 + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) 18.2216 + { 18.2217 + if(M68KMAKE_CC) 18.2218 + { 18.2219 + uint offset = OPER_I_32(); 18.2220 + REG_PC -= 4; 18.2221 + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ 18.2222 + m68ki_branch_32(offset); 18.2223 + return; 18.2224 + } 18.2225 + REG_PC += 4; 18.2226 + return; 18.2227 + } 18.2228 + m68ki_exception_illegal(); 18.2229 +} 18.2230 + 18.2231 + 18.2232 +M68KMAKE_OP(bchg, 32, r, d) 18.2233 +{ 18.2234 + uint* r_dst = &DY; 18.2235 + uint mask = 1 << (DX & 0x1f); 18.2236 + 18.2237 + FLAG_Z = *r_dst & mask; 18.2238 + *r_dst ^= mask; 18.2239 +} 18.2240 + 18.2241 + 18.2242 +M68KMAKE_OP(bchg, 8, r, .) 18.2243 +{ 18.2244 + uint ea = M68KMAKE_GET_EA_AY_8; 18.2245 + uint src = m68ki_read_8(ea); 18.2246 + uint mask = 1 << (DX & 7); 18.2247 + 18.2248 + FLAG_Z = src & mask; 18.2249 + m68ki_write_8(ea, src ^ mask); 18.2250 +} 18.2251 + 18.2252 + 18.2253 +M68KMAKE_OP(bchg, 32, s, d) 18.2254 +{ 18.2255 + uint* r_dst = &DY; 18.2256 + uint mask = 1 << (OPER_I_8() & 0x1f); 18.2257 + 18.2258 + FLAG_Z = *r_dst & mask; 18.2259 + *r_dst ^= mask; 18.2260 +} 18.2261 + 18.2262 + 18.2263 +M68KMAKE_OP(bchg, 8, s, .) 18.2264 +{ 18.2265 + uint mask = 1 << (OPER_I_8() & 7); 18.2266 + uint ea = M68KMAKE_GET_EA_AY_8; 18.2267 + uint src = m68ki_read_8(ea); 18.2268 + 18.2269 + FLAG_Z = src & mask; 18.2270 + m68ki_write_8(ea, src ^ mask); 18.2271 +} 18.2272 + 18.2273 + 18.2274 +M68KMAKE_OP(bclr, 32, r, d) 18.2275 +{ 18.2276 + uint* r_dst = &DY; 18.2277 + uint mask = 1 << (DX & 0x1f); 18.2278 + 18.2279 + FLAG_Z = *r_dst & mask; 18.2280 + *r_dst &= ~mask; 18.2281 +} 18.2282 + 18.2283 + 18.2284 +M68KMAKE_OP(bclr, 8, r, .) 18.2285 +{ 18.2286 + uint ea = M68KMAKE_GET_EA_AY_8; 18.2287 + uint src = m68ki_read_8(ea); 18.2288 + uint mask = 1 << (DX & 7); 18.2289 + 18.2290 + FLAG_Z = src & mask; 18.2291 + m68ki_write_8(ea, src & ~mask); 18.2292 +} 18.2293 + 18.2294 + 18.2295 +M68KMAKE_OP(bclr, 32, s, d) 18.2296 +{ 18.2297 + uint* r_dst = &DY; 18.2298 + uint mask = 1 << (OPER_I_8() & 0x1f); 18.2299 + 18.2300 + FLAG_Z = *r_dst & mask; 18.2301 + *r_dst &= ~mask; 18.2302 +} 18.2303 + 18.2304 + 18.2305 +M68KMAKE_OP(bclr, 8, s, .) 18.2306 +{ 18.2307 + uint mask = 1 << (OPER_I_8() & 7); 18.2308 + uint ea = M68KMAKE_GET_EA_AY_8; 18.2309 + uint src = m68ki_read_8(ea); 18.2310 + 18.2311 + FLAG_Z = src & mask; 18.2312 + m68ki_write_8(ea, src & ~mask); 18.2313 +} 18.2314 + 18.2315 + 18.2316 +M68KMAKE_OP(bfchg, 32, ., d) 18.2317 +{ 18.2318 + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) 18.2319 + { 18.2320 + uint word2 = OPER_I_16(); 18.2321 + uint offset = (word2>>6)&31; 18.2322 + uint width = word2; 18.2323 + uint* data = &DY; 18.2324 + uint64 mask; 18.2325 + 18.2326 + 18.2327 + if(BIT_B(word2)) 18.2328 + offset = REG_D[offset&7]; 18.2329 + if(BIT_5(word2)) 18.2330 + width = REG_D[width&7]; 18.2331 + 18.2332 + offset &= 31; 18.2333 + width = ((width-1) & 31) + 1; 18.2334 + 18.2335 + mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); 18.2336 + mask = ROR_32(mask, offset); 18.2337 + 18.2338 + FLAG_N = NFLAG_32(*data<<offset); 18.2339 + FLAG_Z = *data & mask; 18.2340 + FLAG_V = VFLAG_CLEAR; 18.2341 + FLAG_C = CFLAG_CLEAR; 18.2342 + 18.2343 + *data ^= mask; 18.2344 + 18.2345 + return; 18.2346 + } 18.2347 + m68ki_exception_illegal(); 18.2348 +} 18.2349 + 18.2350 + 18.2351 +M68KMAKE_OP(bfchg, 32, ., .) 18.2352 +{ 18.2353 + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) 18.2354 + { 18.2355 + uint word2 = OPER_I_16(); 18.2356 + sint offset = (word2>>6)&31; 18.2357 + uint width = word2; 18.2358 + uint mask_base; 18.2359 + uint data_long; 18.2360 + uint mask_long; 18.2361 + uint data_byte = 0; 18.2362 + uint mask_byte = 0; 18.2363 + uint ea = M68KMAKE_GET_EA_AY_8; 18.2364 + 18.2365 + 18.2366 + if(BIT_B(word2)) 18.2367 + offset = MAKE_INT_32(REG_D[offset&7]); 18.2368 + if(BIT_5(word2)) 18.2369 + width = REG_D[width&7]; 18.2370 + 18.2371 + /* Offset is signed so we have to use ugly math =( */ 18.2372 + ea += offset / 8; 18.2373 + offset %= 8; 18.2374 + if(offset < 0) 18.2375 + { 18.2376 + offset += 8; 18.2377 + ea--; 18.2378 + } 18.2379 + width = ((width-1) & 31) + 1; 18.2380 + 18.2381 + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); 18.2382 + mask_long = mask_base >> offset; 18.2383 + 18.2384 + data_long = m68ki_read_32(ea); 18.2385 + FLAG_N = NFLAG_32(data_long << offset); 18.2386 + FLAG_Z = data_long & mask_long; 18.2387 + FLAG_V = VFLAG_CLEAR; 18.2388 + FLAG_C = CFLAG_CLEAR; 18.2389 + 18.2390 + m68ki_write_32(ea, data_long ^ mask_long); 18.2391 + 18.2392 + if((width + offset) > 32) 18.2393 + { 18.2394 + mask_byte = MASK_OUT_ABOVE_8(mask_base); 18.2395 + data_byte = m68ki_read_8(ea+4); 18.2396 + FLAG_Z |= (data_byte & mask_byte); 18.2397 + m68ki_write_8(ea+4, data_byte ^ mask_byte); 18.2398 + } 18.2399 + return; 18.2400 + } 18.2401 + m68ki_exception_illegal(); 18.2402 +} 18.2403 + 18.2404 + 18.2405 +M68KMAKE_OP(bfclr, 32, ., d) 18.2406 +{ 18.2407 + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) 18.2408 + { 18.2409 + uint word2 = OPER_I_16(); 18.2410 + uint offset = (word2>>6)&31; 18.2411 + uint width = word2; 18.2412 + uint* data = &DY; 18.2413 + uint64 mask; 18.2414 + 18.2415 + 18.2416 + if(BIT_B(word2)) 18.2417 + offset = REG_D[offset&7]; 18.2418 + if(BIT_5(word2)) 18.2419 + width = REG_D[width&7]; 18.2420 + 18.2421 + 18.2422 + offset &= 31; 18.2423 + width = ((width-1) & 31) + 1; 18.2424 + 18.2425 + 18.2426 + mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); 18.2427 + mask = ROR_32(mask, offset); 18.2428 + 18.2429 + FLAG_N = NFLAG_32(*data<<offset); 18.2430 + FLAG_Z = *data & mask; 18.2431 + FLAG_V = VFLAG_CLEAR; 18.2432 + FLAG_C = CFLAG_CLEAR; 18.2433 + 18.2434 + *data &= ~mask; 18.2435 + 18.2436 + return; 18.2437 + } 18.2438 + m68ki_exception_illegal(); 18.2439 +} 18.2440 + 18.2441 + 18.2442 +M68KMAKE_OP(bfclr, 32, ., .) 18.2443 +{ 18.2444 + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) 18.2445 + { 18.2446 + uint word2 = OPER_I_16(); 18.2447 + sint offset = (word2>>6)&31; 18.2448 + uint width = word2; 18.2449 + uint mask_base; 18.2450 + uint data_long; 18.2451 + uint mask_long; 18.2452 + uint data_byte = 0; 18.2453 + uint mask_byte = 0; 18.2454 + uint ea = M68KMAKE_GET_EA_AY_8; 18.2455 + 18.2456 + 18.2457 + if(BIT_B(word2)) 18.2458 + offset = MAKE_INT_32(REG_D[offset&7]); 18.2459 + if(BIT_5(word2)) 18.2460 + width = REG_D[width&7]; 18.2461 + 18.2462 + /* Offset is signed so we have to use ugly math =( */ 18.2463 + ea += offset / 8; 18.2464 + offset %= 8; 18.2465 + if(offset < 0) 18.2466 + { 18.2467 + offset += 8; 18.2468 + ea--; 18.2469 + } 18.2470 + width = ((width-1) & 31) + 1; 18.2471 + 18.2472 + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); 18.2473 + mask_long = mask_base >> offset; 18.2474 + 18.2475 + data_long = m68ki_read_32(ea); 18.2476 + FLAG_N = NFLAG_32(data_long << offset); 18.2477 + FLAG_Z = data_long & mask_long; 18.2478 + FLAG_V = VFLAG_CLEAR; 18.2479 + FLAG_C = CFLAG_CLEAR; 18.2480 + 18.2481 + m68ki_write_32(ea, data_long & ~mask_long); 18.2482 + 18.2483 + if((width + offset) > 32) 18.2484 + { 18.2485 + mask_byte = MASK_OUT_ABOVE_8(mask_base); 18.2486 + data_byte = m68ki_read_8(ea+4); 18.2487 + FLAG_Z |= (data_byte & mask_byte); 18.2488 + m68ki_write_8(ea+4, data_byte & ~mask_byte); 18.2489 + } 18.2490 + return; 18.2491 + } 18.2492 + m68ki_exception_illegal(); 18.2493 +} 18.2494 + 18.2495 + 18.2496 +M68KMAKE_OP(bfexts, 32, ., d) 18.2497 +{ 18.2498 + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) 18.2499 + { 18.2500 + uint word2 = OPER_I_16(); 18.2501 + uint offset = (word2>>6)&31; 18.2502 + uint width = word2; 18.2503 + uint64 data = DY; 18.2504 + 18.2505 + 18.2506 + if(BIT_B(word2)) 18.2507 + offset = REG_D[offset&7]; 18.2508 + if(BIT_5(word2)) 18.2509 + width = REG_D[width&7]; 18.2510 + 18.2511 + offset &= 31; 18.2512 + width = ((width-1) & 31) + 1; 18.2513 + 18.2514 + data = ROL_32(data, offset); 18.2515 + FLAG_N = NFLAG_32(data); 18.2516 + data = MAKE_INT_32(data) >> (32 - width); 18.2517 + 18.2518 + FLAG_Z = data; 18.2519 + FLAG_V = VFLAG_CLEAR; 18.2520 + FLAG_C = CFLAG_CLEAR; 18.2521 + 18.2522 + REG_D[(word2>>12)&7] = data; 18.2523 + 18.2524 + return; 18.2525 + } 18.2526 + m68ki_exception_illegal(); 18.2527 +} 18.2528 + 18.2529 + 18.2530 +M68KMAKE_OP(bfexts, 32, ., .) 18.2531 +{ 18.2532 + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) 18.2533 + { 18.2534 + uint word2 = OPER_I_16(); 18.2535 + sint offset = (word2>>6)&31; 18.2536 + uint width = word2; 18.2537 + uint data; 18.2538 + uint ea = M68KMAKE_GET_EA_AY_8; 18.2539 + 18.2540 + 18.2541 + if(BIT_B(word2)) 18.2542 + offset = MAKE_INT_32(REG_D[offset&7]); 18.2543 + if(BIT_5(word2)) 18.2544 + width = REG_D[width&7]; 18.2545 + 18.2546 + /* Offset is signed so we have to use ugly math =( */ 18.2547 + ea += offset / 8; 18.2548 + offset %= 8; 18.2549 + if(offset < 0) 18.2550 + { 18.2551 + offset += 8; 18.2552 + ea--; 18.2553 + } 18.2554 + width = ((width-1) & 31) + 1; 18.2555 + 18.2556 + data = m68ki_read_32(ea); 18.2557 + 18.2558 + data = MASK_OUT_ABOVE_32(data<<offset); 18.2559 + 18.2560 + if((offset+width) > 32) 18.2561 + data |= (m68ki_read_8(ea+4) << offset) >> 8; 18.2562 + 18.2563 + FLAG_N = NFLAG_32(data); 18.2564 + data = MAKE_INT_32(data) >> (32 - width); 18.2565 + 18.2566 + FLAG_Z = data; 18.2567 + FLAG_V = VFLAG_CLEAR; 18.2568 + FLAG_C = CFLAG_CLEAR; 18.2569 + 18.2570 + REG_D[(word2 >> 12) & 7] = data; 18.2571 + 18.2572 + return; 18.2573 + } 18.2574 + m68ki_exception_illegal(); 18.2575 +} 18.2576 + 18.2577 + 18.2578 +M68KMAKE_OP(bfextu, 32, ., d) 18.2579 +{ 18.2580 + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) 18.2581 + { 18.2582 + uint word2 = OPER_I_16(); 18.2583 + uint offset = (word2>>6)&31; 18.2584 + uint width = word2; 18.2585 + uint64 data = DY; 18.2586 + 18.2587 + 18.2588 + if(BIT_B(word2)) 18.2589 + offset = REG_D[offset&7]; 18.2590 + if(BIT_5(word2)) 18.2591 + width = REG_D[width&7]; 18.2592 + 18.2593 + offset &= 31; 18.2594 + width = ((width-1) & 31) + 1; 18.2595 + 18.2596 + data = ROL_32(data, offset); 18.2597 + FLAG_N = NFLAG_32(data); 18.2598 + data >>= 32 - width; 18.2599 + 18.2600 + FLAG_Z = data; 18.2601 + FLAG_V = VFLAG_CLEAR; 18.2602 + FLAG_C = CFLAG_CLEAR; 18.2603 + 18.2604 + REG_D[(word2>>12)&7] = data; 18.2605 + 18.2606 + return; 18.2607 + } 18.2608 + m68ki_exception_illegal(); 18.2609 +} 18.2610 + 18.2611 + 18.2612 +M68KMAKE_OP(bfextu, 32, ., .) 18.2613 +{ 18.2614 + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) 18.2615 + { 18.2616 + uint word2 = OPER_I_16(); 18.2617 + sint offset = (word2>>6)&31; 18.2618 + uint width = word2; 18.2619 + uint data; 18.2620 + uint ea = M68KMAKE_GET_EA_AY_8; 18.2621 + 18.2622 + 18.2623 + if(BIT_B(word2)) 18.2624 + offset = MAKE_INT_32(REG_D[offset&7]); 18.2625 + if(BIT_5(word2)) 18.2626 + width = REG_D[width&7]; 18.2627 + 18.2628 + /* Offset is signed so we have to use ugly math =( */ 18.2629 + ea += offset / 8; 18.2630 + offset %= 8; 18.2631 + if(offset < 0) 18.2632 + { 18.2633 + offset += 8; 18.2634 + ea--; 18.2635 + } 18.2636 + width = ((width-1) & 31) + 1; 18.2637 + 18.2638 + data = m68ki_read_32(ea); 18.2639 + data = MASK_OUT_ABOVE_32(data<<offset); 18.2640 + 18.2641 + if((offset+width) > 32) 18.2642 + data |= (m68ki_read_8(ea+4) << offset) >> 8; 18.2643 + 18.2644 + FLAG_N = NFLAG_32(data); 18.2645 + data >>= (32 - width); 18.2646 + 18.2647 + FLAG_Z = data; 18.2648 + FLAG_V = VFLAG_CLEAR; 18.2649 + FLAG_C = CFLAG_CLEAR; 18.2650 + 18.2651 + REG_D[(word2 >> 12) & 7] = data; 18.2652 + 18.2653 + return; 18.2654 + } 18.2655 + m68ki_exception_illegal(); 18.2656 +} 18.2657 + 18.2658 + 18.2659 +M68KMAKE_OP(bfffo, 32, ., d) 18.2660 +{ 18.2661 + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) 18.2662 + { 18.2663 + uint word2 = OPER_I_16(); 18.2664 + uint offset = (word2>>6)&31; 18.2665 + uint width = word2; 18.2666 + uint64 data = DY; 18.2667 + uint bit; 18.2668 + 18.2669 + 18.2670 + if(BIT_B(word2)) 18.2671 + offset = REG_D[offset&7]; 18.2672 + if(BIT_5(word2)) 18.2673 + width = REG_D[width&7]; 18.2674 + 18.2675 + offset &= 31; 18.2676 + width = ((width-1) & 31) + 1; 18.2677 + 18.2678 + data = ROL_32(data, offset); 18.2679 + FLAG_N = NFLAG_32(data); 18.2680 + data >>= 32 - width; 18.2681 + 18.2682 + FLAG_Z = data; 18.2683 + FLAG_V = VFLAG_CLEAR; 18.2684 + FLAG_C = CFLAG_CLEAR; 18.2685 + 18.2686 + for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1) 18.2687 + offset++; 18.2688 + 18.2689 + REG_D[(word2>>12)&7] = offset; 18.2690 + 18.2691 + return; 18.2692 + } 18.2693 + m68ki_exception_illegal(); 18.2694 +} 18.2695 + 18.2696 + 18.2697 +M68KMAKE_OP(bfffo, 32, ., .) 18.2698 +{ 18.2699 + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) 18.2700 + { 18.2701 + uint word2 = OPER_I_16(); 18.2702 + sint offset = (word2>>6)&31; 18.2703 + sint local_offset; 18.2704 + uint width = word2; 18.2705 + uint data; 18.2706 + uint bit; 18.2707 + uint ea = M68KMAKE_GET_EA_AY_8; 18.2708 + 18.2709 + 18.2710 + if(BIT_B(word2)) 18.2711 + offset = MAKE_INT_32(REG_D[offset&7]); 18.2712 + if(BIT_5(word2)) 18.2713 + width = REG_D[width&7]; 18.2714 + 18.2715 + /* Offset is signed so we have to use ugly math =( */ 18.2716 + ea += offset / 8; 18.2717 + local_offset = offset % 8; 18.2718 + if(local_offset < 0) 18.2719 + { 18.2720 + local_offset += 8; 18.2721 + ea--; 18.2722 + } 18.2723 + width = ((width-1) & 31) + 1; 18.2724 + 18.2725 + data = m68ki_read_32(ea); 18.2726 + data = MASK_OUT_ABOVE_32(data<<local_offset); 18.2727 + 18.2728 + if((local_offset+width) > 32) 18.2729 + data |= (m68ki_read_8(ea+4) << local_offset) >> 8; 18.2730 + 18.2731 + FLAG_N = NFLAG_32(data); 18.2732 + data >>= (32 - width); 18.2733 + 18.2734 + FLAG_Z = data; 18.2735 + FLAG_V = VFLAG_CLEAR; 18.2736 + FLAG_C = CFLAG_CLEAR; 18.2737 + 18.2738 + for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1) 18.2739 + offset++; 18.2740 + 18.2741 + REG_D[(word2>>12)&7] = offset; 18.2742 + 18.2743 + return; 18.2744 + } 18.2745 + m68ki_exception_illegal(); 18.2746 +} 18.2747 + 18.2748 + 18.2749 +M68KMAKE_OP(bfins, 32, ., d) 18.2750 +{ 18.2751 + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) 18.2752 + { 18.2753 + uint word2 = OPER_I_16(); 18.2754 + uint offset = (word2>>6)&31; 18.2755 + uint width = word2; 18.2756 + uint* data = &DY; 18.2757 + uint64 mask; 18.2758 + uint64 insert = REG_D[(word2>>12)&7]; 18.2759 + 18.2760 + 18.2761 + if(BIT_B(word2)) 18.2762 + offset = REG_D[offset&7]; 18.2763 + if(BIT_5(word2)) 18.2764 + width = REG_D[width&7]; 18.2765 + 18.2766 + 18.2767 + offset &= 31; 18.2768 + width = ((width-1) & 31) + 1; 18.2769 + 18.2770 + 18.2771 + mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); 18.2772 + mask = ROR_32(mask, offset); 18.2773 + 18.2774 + insert = MASK_OUT_ABOVE_32(insert << (32 - width)); 18.2775 + FLAG_N = NFLAG_32(insert); 18.2776 + FLAG_Z = insert; 18.2777 + insert = ROR_32(insert, offset); 18.2778 + 18.2779 + FLAG_V = VFLAG_CLEAR; 18.2780 + FLAG_C = CFLAG_CLEAR; 18.2781 + 18.2782 + *data &= ~mask; 18.2783 + *data |= insert; 18.2784 + 18.2785 + return; 18.2786 + } 18.2787 + m68ki_exception_illegal(); 18.2788 +} 18.2789 + 18.2790 + 18.2791 +M68KMAKE_OP(bfins, 32, ., .) 18.2792 +{ 18.2793 + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) 18.2794 + { 18.2795 + uint word2 = OPER_I_16(); 18.2796 + sint offset = (word2>>6)&31; 18.2797 + uint width = word2; 18.2798 + uint insert_base = REG_D[(word2>>12)&7]; 18.2799 + uint insert_long; 18.2800 + uint insert_byte; 18.2801 + uint mask_base; 18.2802 + uint data_long; 18.2803 + uint mask_long; 18.2804 + uint data_byte = 0; 18.2805 + uint mask_byte = 0; 18.2806 + uint ea = M68KMAKE_GET_EA_AY_8; 18.2807 + 18.2808 + 18.2809 + if(BIT_B(word2)) 18.2810 + offset = MAKE_INT_32(REG_D[offset&7]); 18.2811 + if(BIT_5(word2)) 18.2812 + width = REG_D[width&7]; 18.2813 + 18.2814 + /* Offset is signed so we have to use ugly math =( */ 18.2815 + ea += offset / 8; 18.2816 + offset %= 8; 18.2817 + if(offset < 0) 18.2818 + { 18.2819 + offset += 8; 18.2820 + ea--; 18.2821 + } 18.2822 + width = ((width-1) & 31) + 1; 18.2823 + 18.2824 + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); 18.2825 + mask_long = mask_base >> offset; 18.2826 + 18.2827 + insert_base = MASK_OUT_ABOVE_32(insert_base << (32 - width)); 18.2828 + FLAG_N = NFLAG_32(insert_base); 18.2829 + FLAG_Z = insert_base; 18.2830 + insert_long = insert_base >> offset; 18.2831 + 18.2832 + data_long = m68ki_read_32(ea); 18.2833 + FLAG_V = VFLAG_CLEAR; 18.2834 + FLAG_C = CFLAG_CLEAR; 18.2835 + 18.2836 + m68ki_write_32(ea, (data_long & ~mask_long) | insert_long); 18.2837 + 18.2838 + if((width + offset) > 32) 18.2839 + { 18.2840 + mask_byte = MASK_OUT_ABOVE_8(mask_base); 18.2841 + insert_byte = MASK_OUT_ABOVE_8(insert_base); 18.2842 + data_byte = m68ki_read_8(ea+4); 18.2843 + FLAG_Z |= (data_byte & mask_byte); 18.2844 + m68ki_write_8(ea+4, (data_byte & ~mask_byte) | insert_byte); 18.2845 + } 18.2846 + return; 18.2847 + } 18.2848 + m68ki_exception_illegal(); 18.2849 +} 18.2850 + 18.2851 + 18.2852 +M68KMAKE_OP(bfset, 32, ., d) 18.2853 +{ 18.2854 + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) 18.2855 + { 18.2856 + uint word2 = OPER_I_16(); 18.2857 + uint offset = (word2>>6)&31; 18.2858 + uint width = word2; 18.2859 + uint* data = &DY; 18.2860 + uint64 mask; 18.2861 + 18.2862 + 18.2863 + if(BIT_B(word2)) 18.2864 + offset = REG_D[offset&7]; 18.2865 + if(BIT_5(word2)) 18.2866 + width = REG_D[width&7]; 18.2867 + 18.2868 + 18.2869 + offset &= 31; 18.2870 + width = ((width-1) & 31) + 1; 18.2871 + 18.2872 + 18.2873 + mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); 18.2874 + mask = ROR_32(mask, offset); 18.2875 + 18.2876 + FLAG_N = NFLAG_32(*data<<offset); 18.2877 + FLAG_Z = *data & mask; 18.2878 + FLAG_V = VFLAG_CLEAR; 18.2879 + FLAG_C = CFLAG_CLEAR; 18.2880 + 18.2881 + *data |= mask; 18.2882 + 18.2883 + return; 18.2884 + } 18.2885 + m68ki_exception_illegal(); 18.2886 +} 18.2887 + 18.2888 + 18.2889 +M68KMAKE_OP(bfset, 32, ., .) 18.2890 +{ 18.2891 + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) 18.2892 + { 18.2893 + uint word2 = OPER_I_16(); 18.2894 + sint offset = (word2>>6)&31; 18.2895 + uint width = word2; 18.2896 + uint mask_base; 18.2897 + uint data_long; 18.2898 + uint mask_long; 18.2899 + uint data_byte = 0; 18.2900 + uint mask_byte = 0; 18.2901 + uint ea = M68KMAKE_GET_EA_AY_8; 18.2902 + 18.2903 + 18.2904 + if(BIT_B(word2)) 18.2905 + offset = MAKE_INT_32(REG_D[offset&7]); 18.2906 + if(BIT_5(word2)) 18.2907 + width = REG_D[width&7]; 18.2908 + 18.2909 + /* Offset is signed so we have to use ugly math =( */ 18.2910 + ea += offset / 8; 18.2911 + offset %= 8; 18.2912 + if(offset < 0) 18.2913 + { 18.2914 + offset += 8; 18.2915 + ea--; 18.2916 + } 18.2917 + width = ((width-1) & 31) + 1; 18.2918 + 18.2919 + 18.2920 + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); 18.2921 + mask_long = mask_base >> offset; 18.2922 + 18.2923 + data_long = m68ki_read_32(ea); 18.2924 + FLAG_N = NFLAG_32(data_long << offset); 18.2925 + FLAG_Z = data_long & mask_long; 18.2926 + FLAG_V = VFLAG_CLEAR; 18.2927 + FLAG_C = CFLAG_CLEAR; 18.2928 + 18.2929 + m68ki_write_32(ea, data_long | mask_long); 18.2930 + 18.2931 + if((width + offset) > 32) 18.2932 + { 18.2933 + mask_byte = MASK_OUT_ABOVE_8(mask_base); 18.2934 + data_byte = m68ki_read_8(ea+4); 18.2935 + FLAG_Z |= (data_byte & mask_byte); 18.2936 + m68ki_write_8(ea+4, data_byte | mask_byte); 18.2937 + } 18.2938 + return; 18.2939 + } 18.2940 + m68ki_exception_illegal(); 18.2941 +} 18.2942 + 18.2943 + 18.2944 +M68KMAKE_OP(bftst, 32, ., d) 18.2945 +{ 18.2946 + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) 18.2947 + { 18.2948 + uint word2 = OPER_I_16(); 18.2949 + uint offset = (word2>>6)&31; 18.2950 + uint width = word2; 18.2951 + uint* data = &DY; 18.2952 + uint64 mask; 18.2953 + 18.2954 + 18.2955 + if(BIT_B(word2)) 18.2956 + offset = REG_D[offset&7]; 18.2957 + if(BIT_5(word2)) 18.2958 + width = REG_D[width&7]; 18.2959 + 18.2960 + 18.2961 + offset &= 31; 18.2962 + width = ((width-1) & 31) + 1; 18.2963 + 18.2964 + 18.2965 + mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); 18.2966 + mask = ROR_32(mask, offset); 18.2967 + 18.2968 + FLAG_N = NFLAG_32(*data<<offset); 18.2969 + FLAG_Z = *data & mask; 18.2970 + FLAG_V = VFLAG_CLEAR; 18.2971 + FLAG_C = CFLAG_CLEAR; 18.2972 + 18.2973 + return; 18.2974 + } 18.2975 + m68ki_exception_illegal(); 18.2976 +} 18.2977 + 18.2978 + 18.2979 +M68KMAKE_OP(bftst, 32, ., .) 18.2980 +{ 18.2981 + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) 18.2982 + { 18.2983 + uint word2 = OPER_I_16(); 18.2984 + sint offset = (word2>>6)&31; 18.2985 + uint width = word2; 18.2986 + uint mask_base; 18.2987 + uint data_long; 18.2988 + uint mask_long; 18.2989 + uint data_byte = 0; 18.2990 + uint mask_byte = 0; 18.2991 + uint ea = M68KMAKE_GET_EA_AY_8; 18.2992 + 18.2993 + if(BIT_B(word2)) 18.2994 + offset = MAKE_INT_32(REG_D[offset&7]); 18.2995 + if(BIT_5(word2)) 18.2996 + width = REG_D[width&7]; 18.2997 + 18.2998 + /* Offset is signed so we have to use ugly math =( */ 18.2999 + ea += offset / 8; 18.3000 + offset %= 8; 18.3001 + if(offset < 0) 18.3002 + { 18.3003 + offset += 8; 18.3004 + ea--; 18.3005 + } 18.3006 + width = ((width-1) & 31) + 1; 18.3007 + 18.3008 + 18.3009 + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); 18.3010 + mask_long = mask_base >> offset; 18.3011 + 18.3012 + data_long = m68ki_read_32(ea); 18.3013 + FLAG_N = ((data_long & (0x80000000 >> offset))<<offset)>>24; 18.3014 + FLAG_Z = data_long & mask_long; 18.3015 + FLAG_V = VFLAG_CLEAR; 18.3016 + FLAG_C = CFLAG_CLEAR; 18.3017 + 18.3018 + if((width + offset) > 32) 18.3019 + { 18.3020 + mask_byte = MASK_OUT_ABOVE_8(mask_base); 18.3021 + data_byte = m68ki_read_8(ea+4); 18.3022 + FLAG_Z |= (data_byte & mask_byte); 18.3023 + } 18.3024 + return; 18.3025 + } 18.3026 + m68ki_exception_illegal(); 18.3027 +} 18.3028 + 18.3029 + 18.3030 +M68KMAKE_OP(bkpt, 0, ., .) 18.3031 +{ 18.3032 + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) 18.3033 + { 18.3034 + m68ki_bkpt_ack(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE) ? REG_IR & 7 : 0); /* auto-disable (see m68kcpu.h) */ 18.3035 + } 18.3036 + m68ki_exception_illegal(); 18.3037 +} 18.3038 + 18.3039 + 18.3040 +M68KMAKE_OP(bra, 8, ., .) 18.3041 +{ 18.3042 + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ 18.3043 + m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR)); 18.3044 + if(REG_PC == REG_PPC) 18.3045 + USE_ALL_CYCLES(); 18.3046 +} 18.3047 + 18.3048 + 18.3049 +M68KMAKE_OP(bra, 16, ., .) 18.3050 +{ 18.3051 + uint offset = OPER_I_16(); 18.3052 + REG_PC -= 2; 18.3053 + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ 18.3054 + m68ki_branch_16(offset); 18.3055 + if(REG_PC == REG_PPC) 18.3056 + USE_ALL_CYCLES(); 18.3057 +} 18.3058 + 18.3059 + 18.3060 +M68KMAKE_OP(bra, 32, ., .) 18.3061 +{ 18.3062 + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) 18.3063 + { 18.3064 + uint offset = OPER_I_32(); 18.3065 + REG_PC -= 4; 18.3066 + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ 18.3067 + m68ki_branch_32(offset); 18.3068 + if(REG_PC == REG_PPC) 18.3069 + USE_ALL_CYCLES(); 18.3070 + return; 18.3071 + } 18.3072 + m68ki_exception_illegal(); 18.3073 +} 18.3074 + 18.3075 + 18.3076 +M68KMAKE_OP(bset, 32, r, d) 18.3077 +{ 18.3078 + uint* r_dst = &DY; 18.3079 + uint mask = 1 << (DX & 0x1f); 18.3080 + 18.3081 + FLAG_Z = *r_dst & mask; 18.3082 + *r_dst |= mask; 18.3083 +} 18.3084 + 18.3085 + 18.3086 +M68KMAKE_OP(bset, 8, r, .) 18.3087 +{ 18.3088 + uint ea = M68KMAKE_GET_EA_AY_8; 18.3089 + uint src = m68ki_read_8(ea); 18.3090 + uint mask = 1 << (DX & 7); 18.3091 + 18.3092 + FLAG_Z = src & mask; 18.3093 + m68ki_write_8(ea, src | mask); 18.3094 +} 18.3095 + 18.3096 + 18.3097 +M68KMAKE_OP(bset, 32, s, d) 18.3098 +{ 18.3099 + uint* r_dst = &DY; 18.3100 + uint mask = 1 << (OPER_I_8() & 0x1f); 18.3101 + 18.3102 + FLAG_Z = *r_dst & mask; 18.3103 + *r_dst |= mask; 18.3104 +} 18.3105 + 18.3106 + 18.3107 +M68KMAKE_OP(bset, 8, s, .) 18.3108 +{ 18.3109 + uint mask = 1 << (OPER_I_8() & 7); 18.3110 + uint ea = M68KMAKE_GET_EA_AY_8; 18.3111 + uint src = m68ki_read_8(ea); 18.3112 + 18.3113 + FLAG_Z = src & mask; 18.3114 + m68ki_write_8(ea, src | mask); 18.3115 +} 18.3116 + 18.3117 + 18.3118 +M68KMAKE_OP(bsr, 8, ., .) 18.3119 +{ 18.3120 + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ 18.3121 + m68ki_push_32(REG_PC); 18.3122 + m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR)); 18.3123 +} 18.3124 + 18.3125 + 18.3126 +M68KMAKE_OP(bsr, 16, ., .) 18.3127 +{ 18.3128 + uint offset = OPER_I_16(); 18.3129 + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ 18.3130 + m68ki_push_32(REG_PC); 18.3131 + REG_PC -= 2; 18.3132 + m68ki_branch_16(offset); 18.3133 +} 18.3134 + 18.3135 + 18.3136 +M68KMAKE_OP(bsr, 32, ., .) 18.3137 +{ 18.3138 + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) 18.3139 + { 18.3140 + uint offset = OPER_I_32(); 18.3141 + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ 18.3142 + m68ki_push_32(REG_PC); 18.3143 + REG_PC -= 4; 18.3144 + m68ki_branch_32(offset); 18.3145 + return; 18.3146 + } 18.3147 + m68ki_exception_illegal(); 18.3148 +} 18.3149 + 18.3150 + 18.3151 +M68KMAKE_OP(btst, 32, r, d) 18.3152 +{ 18.3153 + FLAG_Z = DY & (1 << (DX & 0x1f)); 18.3154 +} 18.3155 + 18.3156 + 18.3157 +M68KMAKE_OP(btst, 8, r, .) 18.3158 +{ 18.3159 + FLAG_Z = M68KMAKE_GET_OPER_AY_8 & (1 << (DX & 7)); 18.3160 +} 18.3161 + 18.3162 + 18.3163 +M68KMAKE_OP(btst, 32, s, d) 18.3164 +{ 18.3165 + FLAG_Z = DY & (1 << (OPER_I_8() & 0x1f)); 18.3166 +} 18.3167 + 18.3168 + 18.3169 +M68KMAKE_OP(btst, 8, s, .) 18.3170 +{ 18.3171 + uint bit = OPER_I_8() & 7; 18.3172 + 18.3173 + FLAG_Z = M68KMAKE_GET_OPER_AY_8 & (1 << bit); 18.3174 +} 18.3175 + 18.3176 + 18.3177 +M68KMAKE_OP(callm, 32, ., .) 18.3178 +{ 18.3179 + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) 18.3180 + { 18.3181 + uint ea = M68KMAKE_GET_EA_AY_32; 18.3182 + 18.3183 + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ 18.3184 + REG_PC += 2; 18.3185 +(void)ea; /* just to avoid an 'unused variable' warning */ 18.3186 + M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", 18.3187 + m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, 18.3188 + m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); 18.3189 + return; 18.3190 + } 18.3191 + m68ki_exception_illegal(); 18.3192 +} 18.3193 + 18.3194 + 18.3195 +M68KMAKE_OP(cas, 8, ., .) 18.3196 +{ 18.3197 + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) 18.3198 + { 18.3199 + uint word2 = OPER_I_16(); 18.3200 + uint ea = M68KMAKE_GET_EA_AY_8; 18.3201 + uint dest = m68ki_read_8(ea); 18.3202 + uint* compare = ®_D[word2 & 7]; 18.3203 + uint res = dest - MASK_OUT_ABOVE_8(*compare); 18.3204 + 18.3205 + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ 18.3206 + FLAG_N = NFLAG_8(res); 18.3207 + FLAG_Z = MASK_OUT_ABOVE_8(res); 18.3208 + FLAG_V = VFLAG_SUB_8(*compare, dest, res); 18.3209 + FLAG_C = CFLAG_8(res); 18.3210 + 18.3211 + if(COND_NE()) 18.3212 + *compare = MASK_OUT_BELOW_8(*compare) | dest; 18.3213 + else 18.3214 + { 18.3215 + USE_CYCLES(3); 18.3216 + m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7])); 18.3217 + } 18.3218 + return; 18.3219 + } 18.3220 + m68ki_exception_illegal(); 18.3221 +} 18.3222 + 18.3223 + 18.3224 +M68KMAKE_OP(cas, 16, ., .) 18.3225 +{ 18.3226 + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) 18.3227 + { 18.3228 + uint word2 = OPER_I_16(); 18.3229 + uint ea = M68KMAKE_GET_EA_AY_16; 18.3230 + uint dest = m68ki_read_16(ea); 18.3231 + uint* compare = ®_D[word2 & 7]; 18.3232 + uint res = dest - MASK_OUT_ABOVE_16(*compare); 18.3233 + 18.3234 + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ 18.3235 + FLAG_N = NFLAG_16(res); 18.3236 + FLAG_Z = MASK_OUT_ABOVE_16(res); 18.3237 + FLAG_V = VFLAG_SUB_16(*compare, dest, res); 18.3238 + FLAG_C = CFLAG_16(res); 18.3239 + 18.3240 + if(COND_NE()) 18.3241 + *compare = MASK_OUT_BELOW_16(*compare) | dest; 18.3242 + else 18.3243 + { 18.3244 + USE_CYCLES(3); 18.3245 + m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7])); 18.3246 + } 18.3247 + return; 18.3248 + } 18.3249 + m68ki_exception_illegal(); 18.3250 +} 18.3251 + 18.3252 + 18.3253 +M68KMAKE_OP(cas, 32, ., .) 18.3254 +{ 18.3255 + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) 18.3256 + { 18.3257 + uint word2 = OPER_I_16(); 18.3258 + uint ea = M68KMAKE_GET_EA_AY_32; 18.3259 + uint dest = m68ki_read_32(ea); 18.3260 + uint* compare = ®_D[word2 & 7]; 18.3261 + uint res = dest - *compare; 18.3262 + 18.3263 + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ 18.3264 + FLAG_N = NFLAG_32(res); 18.3265 + FLAG_Z = MASK_OUT_ABOVE_32(res); 18.3266 + FLAG_V = VFLAG_SUB_32(*compare, dest, res); 18.3267 + FLAG_C = CFLAG_SUB_32(*compare, dest, res); 18.3268 + 18.3269 + if(COND_NE()) 18.3270 + *compare = dest; 18.3271 + else 18.3272 + { 18.3273 + USE_CYCLES(3); 18.3274 + m68ki_write_32(ea, REG_D[(word2 >> 6) & 7]); 18.3275 + } 18.3276 + return; 18.3277 + } 18.3278 + m68ki_exception_illegal(); 18.3279 +} 18.3280 + 18.3281 + 18.3282 +M68KMAKE_OP(cas2, 16, ., .) 18.3283 +{ 18.3284 + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) 18.3285 + { 18.3286 + uint word2 = OPER_I_32(); 18.3287 + uint* compare1 = ®_D[(word2 >> 16) & 7]; 18.3288 + uint ea1 = REG_DA[(word2 >> 28) & 15]; 18.3289 + uint dest1 = m68ki_read_16(ea1); 18.3290 + uint res1 = dest1 - MASK_OUT_ABOVE_16(*compare1); 18.3291 + uint* compare2 = ®_D[word2 & 7]; 18.3292 + uint ea2 = REG_DA[(word2 >> 12) & 15]; 18.3293 + uint dest2 = m68ki_read_16(ea2); 18.3294 + uint res2; 18.3295 + 18.3296 + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ 18.3297 + FLAG_N = NFLAG_16(res1); 18.3298 + FLAG_Z = MASK_OUT_ABOVE_16(res1); 18.3299 + FLAG_V = VFLAG_SUB_16(*compare1, dest1, res1); 18.3300 + FLAG_C = CFLAG_16(res1); 18.3301 + 18.3302 + if(COND_EQ()) 18.3303 + { 18.3304 + res2 = dest2 - MASK_OUT_ABOVE_16(*compare2); 18.3305 + 18.3306 + FLAG_N = NFLAG_16(res2); 18.3307 + FLAG_Z = MASK_OUT_ABOVE_16(res2); 18.3308 + FLAG_V = VFLAG_SUB_16(*compare2, dest2, res2); 18.3309 + FLAG_C = CFLAG_16(res2); 18.3310 + 18.3311 + if(COND_EQ()) 18.3312 + { 18.3313 + USE_CYCLES(3); 18.3314 + m68ki_write_16(ea1, REG_D[(word2 >> 22) & 7]); 18.3315 + m68ki_write_16(ea2, REG_D[(word2 >> 6) & 7]); 18.3316 + return; 18.3317 + } 18.3318 + } 18.3319 + *compare1 = BIT_1F(word2) ? MAKE_INT_16(dest1) : MASK_OUT_BELOW_16(*compare1) | dest1; 18.3320 + *compare2 = BIT_F(word2) ? MAKE_INT_16(dest2) : MASK_OUT_BELOW_16(*compare2) | dest2; 18.3321 + return; 18.3322 + } 18.3323 + m68ki_exception_illegal(); 18.3324 +} 18.3325 + 18.3326 + 18.3327 +M68KMAKE_OP(cas2, 32, ., .) 18.3328 +{ 18.3329 + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) 18.3330 + { 18.3331 + uint word2 = OPER_I_32(); 18.3332 + uint* compare1 = ®_D[(word2 >> 16) & 7]; 18.3333 + uint ea1 = REG_DA[(word2 >> 28) & 15]; 18.3334 + uint dest1 = m68ki_read_32(ea1); 18.3335 + uint res1 = dest1 - *compare1; 18.3336 + uint* compare2 = ®_D[word2 & 7]; 18.3337 + uint ea2 = REG_DA[(word2 >> 12) & 15]; 18.3338 + uint dest2 = m68ki_read_32(ea2); 18.3339 + uint res2; 18.3340 + 18.3341 + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ 18.3342 + FLAG_N = NFLAG_32(res1); 18.3343 + FLAG_Z = MASK_OUT_ABOVE_32(res1); 18.3344 + FLAG_V = VFLAG_SUB_32(*compare1, dest1, res1); 18.3345 + FLAG_C = CFLAG_SUB_32(*compare1, dest1, res1); 18.3346 + 18.3347 + if(COND_EQ()) 18.3348 + { 18.3349 + res2 = dest2 - *compare2; 18.3350 + 18.3351 + FLAG_N = NFLAG_32(res2); 18.3352 + FLAG_Z = MASK_OUT_ABOVE_32(res2); 18.3353 + FLAG_V = VFLAG_SUB_32(*compare2, dest2, res2); 18.3354 + FLAG_C = CFLAG_SUB_32(*compare2, dest2, res2); 18.3355 + 18.3356 + if(COND_EQ()) 18.3357 + { 18.3358 + USE_CYCLES(3); 18.3359 + m68ki_write_32(ea1, REG_D[(word2 >> 22) & 7]); 18.3360 + m68ki_write_32(ea2, REG_D[(word2 >> 6) & 7]); 18.3361 + return; 18.3362 + } 18.3363 + } 18.3364 + *compare1 = dest1; 18.3365 + *compare2 = dest2; 18.3366 + return; 18.3367 + } 18.3368 + m68ki_exception_illegal(); 18.3369 +} 18.3370 + 18.3371 + 18.3372 +M68KMAKE_OP(chk, 16, ., d) 18.3373 +{ 18.3374 + sint src = MAKE_INT_16(DX); 18.3375 + sint bound = MAKE_INT_16(DY); 18.3376 + 18.3377 + if(src >= 0 && src <= bound) 18.3378 + { 18.3379 + return; 18.3380 + } 18.3381 + FLAG_N = (src < 0)<<7; 18.3382 + m68ki_exception_trap(EXCEPTION_CHK); 18.3383 +} 18.3384 + 18.3385 + 18.3386 +M68KMAKE_OP(chk, 16, ., .) 18.3387 +{ 18.3388 + sint src = MAKE_INT_16(DX); 18.3389 + sint bound = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16); 18.3390 + 18.3391 + if(src >= 0 && src <= bound) 18.3392 + { 18.3393 + return; 18.3394 + } 18.3395 + FLAG_N = (src < 0)<<7; 18.3396 + m68ki_exception_trap(EXCEPTION_CHK); 18.3397 +} 18.3398 + 18.3399 + 18.3400 +M68KMAKE_OP(chk, 32, ., d) 18.3401 +{ 18.3402 + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) 18.3403 + { 18.3404 + sint src = MAKE_INT_32(DX); 18.3405 + sint bound = MAKE_INT_32(DY); 18.3406 + 18.3407 + if(src >= 0 && src <= bound) 18.3408 + { 18.3409 + return; 18.3410 + } 18.3411 + FLAG_N = (src < 0)<<7; 18.3412 + m68ki_exception_trap(EXCEPTION_CHK); 18.3413 + return; 18.3414 + } 18.3415 + m68ki_exception_illegal(); 18.3416 +} 18.3417 + 18.3418 + 18.3419 +M68KMAKE_OP(chk, 32, ., .) 18.3420 +{ 18.3421 + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) 18.3422 + { 18.3423 + sint src = MAKE_INT_32(DX); 18.3424 + sint bound = MAKE_INT_32(M68KMAKE_GET_OPER_AY_32); 18.3425 + 18.3426 + if(src >= 0 && src <= bound) 18.3427 + { 18.3428 + return; 18.3429 + } 18.3430 + FLAG_N = (src < 0)<<7; 18.3431 + m68ki_exception_trap(EXCEPTION_CHK); 18.3432 + return; 18.3433 + } 18.3434 + m68ki_exception_illegal(); 18.3435 +} 18.3436 + 18.3437 + 18.3438 +M68KMAKE_OP(chk2cmp2, 8, ., .) 18.3439 +{ 18.3440 + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) 18.3441 + { 18.3442 + uint word2 = OPER_I_16(); 18.3443 + uint compare = REG_DA[(word2 >> 12) & 15]; 18.3444 + uint ea = M68KMAKE_GET_EA_AY_8; 18.3445 + uint lower_bound = m68ki_read_8(ea); 18.3446 + uint upper_bound = m68ki_read_8(ea + 1); 18.3447 + 18.3448 + if(!BIT_F(word2)) 18.3449 + compare = MAKE_INT_8(compare); 18.3450 + 18.3451 + FLAG_C = compare - lower_bound; 18.3452 + FLAG_Z = MASK_OUT_ABOVE_8(FLAG_C); 18.3453 + if(COND_CS()) 18.3454 + { 18.3455 + if(BIT_B(word2)) 18.3456 + m68ki_exception_trap(EXCEPTION_CHK); 18.3457 + return; 18.3458 + } 18.3459 + 18.3460 + FLAG_C = upper_bound - compare; 18.3461 + FLAG_Z = MASK_OUT_ABOVE_8(FLAG_C); 18.3462 + if(COND_CS() && BIT_B(word2)) 18.3463 + m68ki_exception_trap(EXCEPTION_CHK); 18.3464 + 18.3465 + return; 18.3466 + } 18.3467 + m68ki_exception_illegal(); 18.3468 +} 18.3469 + 18.3470 + 18.3471 +M68KMAKE_OP(chk2cmp2, 16, ., .) 18.3472 +{ 18.3473 + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) 18.3474 + { 18.3475 + uint word2 = OPER_I_16(); 18.3476 + uint compare = REG_DA[(word2 >> 12) & 15]; 18.3477 + uint ea = M68KMAKE_GET_EA_AY_16; 18.3478 + uint lower_bound = m68ki_read_16(ea); 18.3479 + uint upper_bound = m68ki_read_16(ea + 1); 18.3480 + 18.3481 + if(!BIT_F(word2)) 18.3482 + compare = MAKE_INT_16(compare); 18.3483 + 18.3484 + FLAG_C = compare - lower_bound; 18.3485 + FLAG_Z = MASK_OUT_ABOVE_16(FLAG_C); 18.3486 + FLAG_C = CFLAG_16(FLAG_C); 18.3487 + if(COND_CS()) 18.3488 + { 18.3489 + if(BIT_B(word2)) 18.3490 + m68ki_exception_trap(EXCEPTION_CHK); 18.3491 + return; 18.3492 + } 18.3493 + 18.3494 + FLAG_C = upper_bound - compare; 18.3495 + FLAG_Z = MASK_OUT_ABOVE_16(FLAG_C); 18.3496 + FLAG_C = CFLAG_16(FLAG_C); 18.3497 + if(COND_CS() && BIT_B(word2)) 18.3498 + m68ki_exception_trap(EXCEPTION_CHK); 18.3499 + 18.3500 + return; 18.3501 + } 18.3502 + m68ki_exception_illegal(); 18.3503 +} 18.3504 + 18.3505 + 18.3506 +M68KMAKE_OP(chk2cmp2, 32, ., .) 18.3507 +{ 18.3508 + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) 18.3509 + { 18.3510 + uint word2 = OPER_I_16(); 18.3511 + uint compare = REG_DA[(word2 >> 12) & 15]; 18.3512 + uint ea = M68KMAKE_GET_EA_AY_32; 18.3513 + uint lower_bound = m68ki_read_32(ea); 18.3514 + uint upper_bound = m68ki_read_32(ea + 1); 18.3515 + 18.3516 + FLAG_C = compare - lower_bound; 18.3517 + FLAG_Z = MASK_OUT_ABOVE_32(FLAG_C); 18.3518 + FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C); 18.3519 + if(COND_CS()) 18.3520 + { 18.3521 + if(BIT_B(word2)) 18.3522 + m68ki_exception_trap(EXCEPTION_CHK); 18.3523 + return; 18.3524 + } 18.3525 + 18.3526 + FLAG_C = upper_bound - compare; 18.3527 + FLAG_Z = MASK_OUT_ABOVE_32(FLAG_C); 18.3528 + FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C); 18.3529 + if(COND_CS() && BIT_B(word2)) 18.3530 + m68ki_exception_trap(EXCEPTION_CHK); 18.3531 + 18.3532 + return; 18.3533 + } 18.3534 + m68ki_exception_illegal(); 18.3535 +} 18.3536 + 18.3537 + 18.3538 +M68KMAKE_OP(clr, 8, ., d) 18.3539 +{ 18.3540 + DY &= 0xffffff00; 18.3541 + 18.3542 + FLAG_N = NFLAG_CLEAR; 18.3543 + FLAG_V = VFLAG_CLEAR; 18.3544 + FLAG_C = CFLAG_CLEAR; 18.3545 + FLAG_Z = ZFLAG_SET; 18.3546 +} 18.3547 + 18.3548 + 18.3549 +M68KMAKE_OP(clr, 8, ., .) 18.3550 +{ 18.3551 + m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0); 18.3552 + 18.3553 + FLAG_N = NFLAG_CLEAR; 18.3554 + FLAG_V = VFLAG_CLEAR; 18.3555 + FLAG_C = CFLAG_CLEAR; 18.3556 + FLAG_Z = ZFLAG_SET; 18.3557 +} 18.3558 + 18.3559 + 18.3560 +M68KMAKE_OP(clr, 16, ., d) 18.3561 +{ 18.3562 + DY &= 0xffff0000; 18.3563 + 18.3564 + FLAG_N = NFLAG_CLEAR; 18.3565 + FLAG_V = VFLAG_CLEAR; 18.3566 + FLAG_C = CFLAG_CLEAR; 18.3567 + FLAG_Z = ZFLAG_SET; 18.3568 +} 18.3569 + 18.3570 + 18.3571 +M68KMAKE_OP(clr, 16, ., .) 18.3572 +{ 18.3573 + m68ki_write_16(M68KMAKE_GET_EA_AY_16, 0); 18.3574 + 18.3575 + FLAG_N = NFLAG_CLEAR; 18.3576 + FLAG_V = VFLAG_CLEAR; 18.3577 + FLAG_C = CFLAG_CLEAR; 18.3578 + FLAG_Z = ZFLAG_SET; 18.3579 +} 18.3580 + 18.3581 + 18.3582 +M68KMAKE_OP(clr, 32, ., d) 18.3583 +{ 18.3584 + DY = 0; 18.3585 + 18.3586 + FLAG_N = NFLAG_CLEAR; 18.3587 + FLAG_V = VFLAG_CLEAR; 18.3588 + FLAG_C = CFLAG_CLEAR; 18.3589 + FLAG_Z = ZFLAG_SET; 18.3590 +} 18.3591 + 18.3592 + 18.3593 +M68KMAKE_OP(clr, 32, ., .) 18.3594 +{ 18.3595 + m68ki_write_32(M68KMAKE_GET_EA_AY_32, 0); 18.3596 + 18.3597 + FLAG_N = NFLAG_CLEAR; 18.3598 + FLAG_V = VFLAG_CLEAR; 18.3599 + FLAG_C = CFLAG_CLEAR; 18.3600 + FLAG_Z = ZFLAG_SET; 18.3601 +} 18.3602 + 18.3603 + 18.3604 +M68KMAKE_OP(cmp, 8, ., d) 18.3605 +{ 18.3606 + uint src = MASK_OUT_ABOVE_8(DY); 18.3607 + uint dst = MASK_OUT_ABOVE_8(DX); 18.3608 + uint res = dst - src; 18.3609 + 18.3610 + FLAG_N = NFLAG_8(res); 18.3611 + FLAG_Z = MASK_OUT_ABOVE_8(res); 18.3612 + FLAG_V = VFLAG_SUB_8(src, dst, res); 18.3613 + FLAG_C = CFLAG_8(res); 18.3614 +} 18.3615 + 18.3616 + 18.3617 +M68KMAKE_OP(cmp, 8, ., .) 18.3618 +{ 18.3619 + uint src = M68KMAKE_GET_OPER_AY_8; 18.3620 + uint dst = MASK_OUT_ABOVE_8(DX); 18.3621 + uint res = dst - src; 18.3622 + 18.3623 + FLAG_N = NFLAG_8(res); 18.3624 + FLAG_Z = MASK_OUT_ABOVE_8(res); 18.3625 + FLAG_V = VFLAG_SUB_8(src, dst, res); 18.3626 + FLAG_C = CFLAG_8(res); 18.3627 +} 18.3628 + 18.3629 + 18.3630 +M68KMAKE_OP(cmp, 16, ., d) 18.3631 +{ 18.3632 + uint src = MASK_OUT_ABOVE_16(DY); 18.3633 + uint dst = MASK_OUT_ABOVE_16(DX); 18.3634 + uint res = dst - src; 18.3635 + 18.3636 + FLAG_N = NFLAG_16(res); 18.3637 + FLAG_Z = MASK_OUT_ABOVE_16(res); 18.3638 + FLAG_V = VFLAG_SUB_16(src, dst, res); 18.3639 + FLAG_C = CFLAG_16(res); 18.3640 +} 18.3641 + 18.3642 + 18.3643 +M68KMAKE_OP(cmp, 16, ., a) 18.3644 +{ 18.3645 + uint src = MASK_OUT_ABOVE_16(AY); 18.3646 + uint dst = MASK_OUT_ABOVE_16(DX); 18.3647 + uint res = dst - src; 18.3648 + 18.3649 + FLAG_N = NFLAG_16(res); 18.3650 + FLAG_Z = MASK_OUT_ABOVE_16(res); 18.3651 + FLAG_V = VFLAG_SUB_16(src, dst, res); 18.3652 + FLAG_C = CFLAG_16(res); 18.3653 +} 18.3654 + 18.3655 + 18.3656 +M68KMAKE_OP(cmp, 16, ., .) 18.3657 +{ 18.3658 + uint src = M68KMAKE_GET_OPER_AY_16; 18.3659 + uint dst = MASK_OUT_ABOVE_16(DX); 18.3660 + uint res = dst - src; 18.3661 + 18.3662 + FLAG_N = NFLAG_16(res); 18.3663 + FLAG_Z = MASK_OUT_ABOVE_16(res); 18.3664 + FLAG_V = VFLAG_SUB_16(src, dst, res); 18.3665 + FLAG_C = CFLAG_16(res); 18.3666 +} 18.3667 + 18.3668 + 18.3669 +M68KMAKE_OP(cmp, 32, ., d) 18.3670 +{ 18.3671 + uint src = DY; 18.3672 + uint dst = DX; 18.3673 + uint res = dst - src; 18.3674 + 18.3675 + FLAG_N = NFLAG_32(res); 18.3676 + FLAG_Z = MASK_OUT_ABOVE_32(res); 18.3677 + FLAG_V = VFLAG_SUB_32(src, dst, res); 18.3678 + FLAG_C = CFLAG_SUB_32(src, dst, res); 18.3679 +} 18.3680 + 18.3681 + 18.3682 +M68KMAKE_OP(cmp, 32, ., a) 18.3683 +{ 18.3684 + uint src = AY; 18.3685 + uint dst = DX; 18.3686 + uint res = dst - src; 18.3687 + 18.3688 + FLAG_N = NFLAG_32(res); 18.3689 + FLAG_Z = MASK_OUT_ABOVE_32(res); 18.3690 + FLAG_V = VFLAG_SUB_32(src, dst, res); 18.3691 + FLAG_C = CFLAG_SUB_32(src, dst, res); 18.3692 +} 18.3693 + 18.3694 + 18.3695 +M68KMAKE_OP(cmp, 32, ., .) 18.3696 +{ 18.3697 + uint src = M68KMAKE_GET_OPER_AY_32; 18.3698 + uint dst = DX; 18.3699 + uint res = dst - src; 18.3700 + 18.3701 + FLAG_N = NFLAG_32(res); 18.3702 + FLAG_Z = MASK_OUT_ABOVE_32(res); 18.3703 + FLAG_V = VFLAG_SUB_32(src, dst, res); 18.3704 + FLAG_C = CFLAG_SUB_32(src, dst, res); 18.3705 +} 18.3706 + 18.3707 + 18.3708 +M68KMAKE_OP(cmpa, 16, ., d) 18.3709 +{ 18.3710 + uint src = MAKE_INT_16(DY); 18.3711 + uint dst = AX; 18.3712 + uint res = dst - src; 18.3713 + 18.3714 + FLAG_N = NFLAG_32(res); 18.3715 + FLAG_Z = MASK_OUT_ABOVE_32(res); 18.3716 + FLAG_V = VFLAG_SUB_32(src, dst, res); 18.3717 + FLAG_C = CFLAG_SUB_32(src, dst, res); 18.3718 +} 18.3719 + 18.3720 + 18.3721 +M68KMAKE_OP(cmpa, 16, ., a) 18.3722 +{ 18.3723 + uint src = MAKE_INT_16(AY); 18.3724 + uint dst = AX; 18.3725 + uint res = dst - src; 18.3726 + 18.3727 + FLAG_N = NFLAG_32(res); 18.3728 + FLAG_Z = MASK_OUT_ABOVE_32(res); 18.3729 + FLAG_V = VFLAG_SUB_32(src, dst, res); 18.3730 + FLAG_C = CFLAG_SUB_32(src, dst, res); 18.3731 +} 18.3732 + 18.3733 + 18.3734 +M68KMAKE_OP(cmpa, 16, ., .) 18.3735 +{ 18.3736 + uint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16); 18.3737 + uint dst = AX; 18.3738 + uint res = dst - src; 18.3739 + 18.3740 + FLAG_N = NFLAG_32(res); 18.3741 + FLAG_Z = MASK_OUT_ABOVE_32(res); 18.3742 + FLAG_V = VFLAG_SUB_32(src, dst, res); 18.3743 + FLAG_C = CFLAG_SUB_32(src, dst, res); 18.3744 +} 18.3745 + 18.3746 + 18.3747 +M68KMAKE_OP(cmpa, 32, ., d) 18.3748 +{ 18.3749 + uint src = DY; 18.3750 + uint dst = AX; 18.3751 + uint res = dst - src; 18.3752 + 18.3753 + FLAG_N = NFLAG_32(res); 18.3754 + FLAG_Z = MASK_OUT_ABOVE_32(res); 18.3755 + FLAG_V = VFLAG_SUB_32(src, dst, res); 18.3756 + FLAG_C = CFLAG_SUB_32(src, dst, res); 18.3757 +} 18.3758 + 18.3759 + 18.3760 +M68KMAKE_OP(cmpa, 32, ., a) 18.3761 +{ 18.3762 + uint src = AY; 18.3763 + uint dst = AX; 18.3764 + uint res = dst - src; 18.3765 + 18.3766 + FLAG_N = NFLAG_32(res); 18.3767 + FLAG_Z = MASK_OUT_ABOVE_32(res); 18.3768 + FLAG_V = VFLAG_SUB_32(src, dst, res); 18.3769 + FLAG_C = CFLAG_SUB_32(src, dst, res); 18.3770 +} 18.3771 + 18.3772 + 18.3773 +M68KMAKE_OP(cmpa, 32, ., .) 18.3774 +{ 18.3775 + uint src = M68KMAKE_GET_OPER_AY_32; 18.3776 + uint dst = AX; 18.3777 + uint res = dst - src; 18.3778 + 18.3779 + FLAG_N = NFLAG_32(res); 18.3780 + FLAG_Z = MASK_OUT_ABOVE_32(res); 18.3781 + FLAG_V = VFLAG_SUB_32(src, dst, res); 18.3782 + FLAG_C = CFLAG_SUB_32(src, dst, res); 18.3783 +} 18.3784 + 18.3785 + 18.3786 +M68KMAKE_OP(cmpi, 8, ., d) 18.3787 +{ 18.3788 + uint src = OPER_I_8(); 18.3789 + uint dst = MASK_OUT_ABOVE_8(DY); 18.3790 + uint res = dst - src; 18.3791 + 18.3792 + FLAG_N = NFLAG_8(res); 18.3793 + FLAG_Z = MASK_OUT_ABOVE_8(res); 18.3794 + FLAG_V = VFLAG_SUB_8(src, dst, res); 18.3795 + FLAG_C = CFLAG_8(res); 18.3796 +} 18.3797 + 18.3798 + 18.3799 +M68KMAKE_OP(cmpi, 8, ., .) 18.3800 +{ 18.3801 + uint src = OPER_I_8(); 18.3802 + uint dst = M68KMAKE_GET_OPER_AY_8; 18.3803 + uint res = dst - src; 18.3804 + 18.3805 + FLAG_N = NFLAG_8(res); 18.3806 + FLAG_Z = MASK_OUT_ABOVE_8(res); 18.3807 + FLAG_V = VFLAG_SUB_8(src, dst, res); 18.3808 + FLAG_C = CFLAG_8(res); 18.3809 +} 18.3810 + 18.3811 + 18.3812 +M68KMAKE_OP(cmpi, 8, ., pcdi) 18.3813 +{ 18.3814 + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) 18.3815 + { 18.3816 + uint src = OPER_I_8(); 18.3817 + uint dst = OPER_PCDI_8(); 18.3818 + uint res = dst - src; 18.3819 + 18.3820 + FLAG_N = NFLAG_8(res); 18.3821 + FLAG_Z = MASK_OUT_ABOVE_8(res); 18.3822 + FLAG_V = VFLAG_SUB_8(src, dst, res); 18.3823 + FLAG_C = CFLAG_8(res); 18.3824 + return; 18.3825 + } 18.3826 + m68ki_exception_illegal(); 18.3827 +} 18.3828 + 18.3829 + 18.3830 +M68KMAKE_OP(cmpi, 8, ., pcix) 18.3831 +{ 18.3832 + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) 18.3833 + { 18.3834 + uint src = OPER_I_8(); 18.3835 + uint dst = OPER_PCIX_8(); 18.3836 + uint res = dst - src; 18.3837 + 18.3838 + FLAG_N = NFLAG_8(res); 18.3839 + FLAG_Z = MASK_OUT_ABOVE_8(res); 18.3840 + FLAG_V = VFLAG_SUB_8(src, dst, res); 18.3841 + FLAG_C = CFLAG_8(res); 18.3842 + return; 18.3843 + } 18.3844 + m68ki_exception_illegal(); 18.3845 +} 18.3846 + 18.3847 + 18.3848 +M68KMAKE_OP(cmpi, 16, ., d) 18.3849 +{ 18.3850 + uint src = OPER_I_16(); 18.3851 + uint dst = MASK_OUT_ABOVE_16(DY); 18.3852 + uint res = dst - src; 18.3853 + 18.3854 + FLAG_N = NFLAG_16(res); 18.3855 + FLAG_Z = MASK_OUT_ABOVE_16(res); 18.3856 + FLAG_V = VFLAG_SUB_16(src, dst, res); 18.3857 + FLAG_C = CFLAG_16(res); 18.3858 +} 18.3859 + 18.3860 + 18.3861 +M68KMAKE_OP(cmpi, 16, ., .) 18.3862 +{ 18.3863 + uint src = OPER_I_16(); 18.3864 + uint dst = M68KMAKE_GET_OPER_AY_16; 18.3865 + uint res = dst - src; 18.3866 + 18.3867 + FLAG_N = NFLAG_16(res); 18.3868 + FLAG_Z = MASK_OUT_ABOVE_16(res); 18.3869 + FLAG_V = VFLAG_SUB_16(src, dst, res); 18.3870 + FLAG_C = CFLAG_16(res); 18.3871 +} 18.3872 + 18.3873 + 18.3874 +M68KMAKE_OP(cmpi, 16, ., pcdi) 18.3875 +{ 18.3876 + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) 18.3877 + { 18.3878 + uint src = OPER_I_16(); 18.3879 + uint dst = OPER_PCDI_16(); 18.3880 + uint res = dst - src; 18.3881 + 18.3882 + FLAG_N = NFLAG_16(res); 18.3883 + FLAG_Z = MASK_OUT_ABOVE_16(res); 18.3884 + FLAG_V = VFLAG_SUB_16(src, dst, res); 18.3885 + FLAG_C = CFLAG_16(res); 18.3886 + return; 18.3887 + } 18.3888 + m68ki_exception_illegal(); 18.3889 +} 18.3890 + 18.3891 + 18.3892 +M68KMAKE_OP(cmpi, 16, ., pcix) 18.3893 +{ 18.3894 + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) 18.3895 + { 18.3896 + uint src = OPER_I_16(); 18.3897 + uint dst = OPER_PCIX_16(); 18.3898 + uint res = dst - src; 18.3899 + 18.3900 + FLAG_N = NFLAG_16(res); 18.3901 + FLAG_Z = MASK_OUT_ABOVE_16(res); 18.3902 + FLAG_V = VFLAG_SUB_16(src, dst, res); 18.3903 + FLAG_C = CFLAG_16(res); 18.3904 + return; 18.3905 + } 18.3906 + m68ki_exception_illegal(); 18.3907 +} 18.3908 + 18.3909 + 18.3910 +M68KMAKE_OP(cmpi, 32, ., d) 18.3911 +{ 18.3912 + uint src = OPER_I_32(); 18.3913 + uint dst = DY; 18.3914 + uint res = dst - src; 18.3915 + 18.3916 + FLAG_N = NFLAG_32(res); 18.3917 + FLAG_Z = MASK_OUT_ABOVE_32(res); 18.3918 + FLAG_V = VFLAG_SUB_32(src, dst, res); 18.3919 + FLAG_C = CFLAG_SUB_32(src, dst, res); 18.3920 +} 18.3921 + 18.3922 + 18.3923 +M68KMAKE_OP(cmpi, 32, ., .) 18.3924 +{ 18.3925 + uint src = OPER_I_32(); 18.3926 + uint dst = M68KMAKE_GET_OPER_AY_32; 18.3927 + uint res = dst - src; 18.3928 + 18.3929 + FLAG_N = NFLAG_32(res); 18.3930 + FLAG_Z = MASK_OUT_ABOVE_32(res); 18.3931 + FLAG_V = VFLAG_SUB_32(src, dst, res); 18.3932 + FLAG_C = CFLAG_SUB_32(src, dst, res); 18.3933 +} 18.3934 + 18.3935 + 18.3936 +M68KMAKE_OP(cmpi, 32, ., pcdi) 18.3937 +{ 18.3938 + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) 18.3939 + { 18.3940 + uint src = OPER_I_32(); 18.3941 + uint dst = OPER_PCDI_32(); 18.3942 + uint res = dst - src; 18.3943 + 18.3944 + FLAG_N = NFLAG_32(res); 18.3945 + FLAG_Z = MASK_OUT_ABOVE_32(res); 18.3946 + FLAG_V = VFLAG_SUB_32(src, dst, res); 18.3947 + FLAG_C = CFLAG_SUB_32(src, dst, res); 18.3948 + return; 18.3949 + } 18.3950 + m68ki_exception_illegal(); 18.3951 +} 18.3952 + 18.3953 + 18.3954 +M68KMAKE_OP(cmpi, 32, ., pcix) 18.3955 +{ 18.3956 + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) 18.3957 + { 18.3958 + uint src = OPER_I_32(); 18.3959 + uint dst = OPER_PCIX_32(); 18.3960 + uint res = dst - src; 18.3961 + 18.3962 + FLAG_N = NFLAG_32(res); 18.3963 + FLAG_Z = MASK_OUT_ABOVE_32(res); 18.3964 + FLAG_V = VFLAG_SUB_32(src, dst, res); 18.3965 + FLAG_C = CFLAG_SUB_32(src, dst, res); 18.3966 + return; 18.3967 + } 18.3968 + m68ki_exception_illegal(); 18.3969 +} 18.3970 + 18.3971 + 18.3972 +M68KMAKE_OP(cmpm, 8, ., ax7) 18.3973 +{ 18.3974 + uint src = OPER_AY_PI_8(); 18.3975 + uint dst = OPER_A7_PI_8(); 18.3976 + uint res = dst - src; 18.3977 + 18.3978 + FLAG_N = NFLAG_8(res); 18.3979 + FLAG_Z = MASK_OUT_ABOVE_8(res); 18.3980 + FLAG_V = VFLAG_SUB_8(src, dst, res); 18.3981 + FLAG_C = CFLAG_8(res); 18.3982 +} 18.3983 + 18.3984 + 18.3985 +M68KMAKE_OP(cmpm, 8, ., ay7) 18.3986 +{ 18.3987 + uint src = OPER_A7_PI_8(); 18.3988 + uint dst = OPER_AX_PI_8(); 18.3989 + uint res = dst - src; 18.3990 + 18.3991 + FLAG_N = NFLAG_8(res); 18.3992 + FLAG_Z = MASK_OUT_ABOVE_8(res); 18.3993 + FLAG_V = VFLAG_SUB_8(src, dst, res); 18.3994 + FLAG_C = CFLAG_8(res); 18.3995 +} 18.3996 + 18.3997 + 18.3998 +M68KMAKE_OP(cmpm, 8, ., axy7) 18.3999 +{ 18.4000 + uint src = OPER_A7_PI_8(); 18.4001 + uint dst = OPER_A7_PI_8(); 18.4002 + uint res = dst - src; 18.4003 + 18.4004 + FLAG_N = NFLAG_8(res); 18.4005 + FLAG_Z = MASK_OUT_ABOVE_8(res); 18.4006 + FLAG_V = VFLAG_SUB_8(src, dst, res); 18.4007 + FLAG_C = CFLAG_8(res); 18.4008 +} 18.4009 + 18.4010 + 18.4011 +M68KMAKE_OP(cmpm, 8, ., .) 18.4012 +{ 18.4013 + uint src = OPER_AY_PI_8(); 18.4014 + uint dst = OPER_AX_PI_8(); 18.4015 + uint res = dst - src; 18.4016 + 18.4017 + FLAG_N = NFLAG_8(res); 18.4018 + FLAG_Z = MASK_OUT_ABOVE_8(res); 18.4019 + FLAG_V = VFLAG_SUB_8(src, dst, res); 18.4020 + FLAG_C = CFLAG_8(res); 18.4021 +} 18.4022 + 18.4023 + 18.4024 +M68KMAKE_OP(cmpm, 16, ., .) 18.4025 +{ 18.4026 + uint src = OPER_AY_PI_16(); 18.4027 + uint dst = OPER_AX_PI_16(); 18.4028 + uint res = dst - src; 18.4029 + 18.4030 + FLAG_N = NFLAG_16(res); 18.4031 + FLAG_Z = MASK_OUT_ABOVE_16(res); 18.4032 + FLAG_V = VFLAG_SUB_16(src, dst, res); 18.4033 + FLAG_C = CFLAG_16(res); 18.4034 +} 18.4035 + 18.4036 + 18.4037 +M68KMAKE_OP(cmpm, 32, ., .) 18.4038 +{ 18.4039 + uint src = OPER_AY_PI_32(); 18.4040 + uint dst = OPER_AX_PI_32(); 18.4041 + uint res = dst - src; 18.4042 + 18.4043 + FLAG_N = NFLAG_32(res); 18.4044 + FLAG_Z = MASK_OUT_ABOVE_32(res); 18.4045 + FLAG_V = VFLAG_SUB_32(src, dst, res); 18.4046 + FLAG_C = CFLAG_SUB_32(src, dst, res); 18.4047 +} 18.4048 + 18.4049 + 18.4050 +M68KMAKE_OP(cpbcc, 32, ., .) 18.4051 +{ 18.4052 + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) 18.4053 + { 18.4054 + M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", 18.4055 + m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, 18.4056 + m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); 18.4057 + return; 18.4058 + } 18.4059 + m68ki_exception_1111(); 18.4060 +} 18.4061 + 18.4062 + 18.4063 +M68KMAKE_OP(cpdbcc, 32, ., .) 18.4064 +{ 18.4065 + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) 18.4066 + { 18.4067 + M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", 18.4068 + m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, 18.4069 + m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); 18.4070 + return; 18.4071 + } 18.4072 + m68ki_exception_1111(); 18.4073 +} 18.4074 + 18.4075 + 18.4076 +M68KMAKE_OP(cpgen, 32, ., .) 18.4077 +{ 18.4078 + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) 18.4079 + { 18.4080 + M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", 18.4081 + m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, 18.4082 + m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); 18.4083 + return; 18.4084 + } 18.4085 + m68ki_exception_1111(); 18.4086 +} 18.4087 + 18.4088 + 18.4089 +M68KMAKE_OP(cpscc, 32, ., .) 18.4090 +{ 18.4091 + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) 18.4092 + { 18.4093 + M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", 18.4094 + m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, 18.4095 + m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); 18.4096 + return; 18.4097 + } 18.4098 + m68ki_exception_1111(); 18.4099 +} 18.4100 + 18.4101 + 18.4102 +M68KMAKE_OP(cptrapcc, 32, ., .) 18.4103 +{ 18.4104 + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) 18.4105 + { 18.4106 + M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", 18.4107 + m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, 18.4108 + m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); 18.4109 + return; 18.4110 + } 18.4111 + m68ki_exception_1111(); 18.4112 +} 18.4113 + 18.4114 + 18.4115 +M68KMAKE_OP(dbt, 16, ., .) 18.4116 +{ 18.4117 + REG_PC += 2; 18.4118 +} 18.4119 + 18.4120 + 18.4121 +M68KMAKE_OP(dbf, 16, ., .) 18.4122 +{ 18.4123 + uint* r_dst = &DY; 18.4124 + uint res = MASK_OUT_ABOVE_16(*r_dst - 1); 18.4125 + 18.4126 + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; 18.4127 + if(res != 0xffff) 18.4128 + { 18.4129 + uint offset = OPER_I_16(); 18.4130 + REG_PC -= 2; 18.4131 + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ 18.4132 + m68ki_branch_16(offset); 18.4133 + return; 18.4134 + } 18.4135 + REG_PC += 2; 18.4136 +} 18.4137 + 18.4138 + 18.4139 +M68KMAKE_OP(dbcc, 16, ., .) 18.4140 +{ 18.4141 + if(M68KMAKE_NOT_CC) 18.4142 + { 18.4143 + uint* r_dst = &DY; 18.4144 + uint res = MASK_OUT_ABOVE_16(*r_dst - 1); 18.4145 + 18.4146 + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; 18.4147 + if(res != 0xffff) 18.4148 + { 18.4149 + uint offset = OPER_I_16(); 18.4150 + REG_PC -= 2; 18.4151 + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ 18.4152 + m68ki_branch_16(offset); 18.4153 + USE_CYCLES(CYC_DBCC_F_NOEXP); 18.4154 + return; 18.4155 + } 18.4156 + REG_PC += 2; 18.4157 + USE_CYCLES(CYC_DBCC_F_EXP); 18.4158 + return; 18.4159 + } 18.4160 + REG_PC += 2; 18.4161 +} 18.4162 + 18.4163 + 18.4164 +M68KMAKE_OP(divs, 16, ., d) 18.4165 +{ 18.4166 + uint* r_dst = &DX; 18.4167 + sint src = MAKE_INT_16(DY); 18.4168 + sint quotient; 18.4169 + sint remainder; 18.4170 + 18.4171 + if(src != 0) 18.4172 + { 18.4173 + if((uint32)*r_dst == 0x80000000 && src == -1) 18.4174 + { 18.4175 + FLAG_Z = 0; 18.4176 + FLAG_N = NFLAG_CLEAR; 18.4177 + FLAG_V = VFLAG_CLEAR; 18.4178 + FLAG_C = CFLAG_CLEAR; 18.4179 + *r_dst = 0; 18.4180 + return; 18.4181 + } 18.4182 + 18.4183 + quotient = MAKE_INT_32(*r_dst) / src; 18.4184 + remainder = MAKE_INT_32(*r_dst) % src; 18.4185 + 18.4186 + if(quotient == MAKE_INT_16(quotient)) 18.4187 + { 18.4188 + FLAG_Z = quotient; 18.4189 + FLAG_N = NFLAG_16(quotient); 18.4190 + FLAG_V = VFLAG_CLEAR; 18.4191 + FLAG_C = CFLAG_CLEAR; 18.4192 + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); 18.4193 + return; 18.4194 + } 18.4195 + FLAG_V = VFLAG_SET; 18.4196 + return; 18.4197 + } 18.4198 + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); 18.4199 +} 18.4200 + 18.4201 + 18.4202 +M68KMAKE_OP(divs, 16, ., .) 18.4203 +{ 18.4204 + uint* r_dst = &DX; 18.4205 + sint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16); 18.4206 + sint quotient; 18.4207 + sint remainder; 18.4208 + 18.4209 + if(src != 0) 18.4210 + { 18.4211 + if((uint32)*r_dst == 0x80000000 && src == -1) 18.4212 + { 18.4213 + FLAG_Z = 0; 18.4214 + FLAG_N = NFLAG_CLEAR; 18.4215 + FLAG_V = VFLAG_CLEAR; 18.4216 + FLAG_C = CFLAG_CLEAR; 18.4217 + *r_dst = 0; 18.4218 + return; 18.4219 + } 18.4220 + 18.4221 + quotient = MAKE_INT_32(*r_dst) / src; 18.4222 + remainder = MAKE_INT_32(*r_dst) % src; 18.4223 + 18.4224 + if(quotient == MAKE_INT_16(quotient)) 18.4225 + { 18.4226 + FLAG_Z = quotient; 18.4227 + FLAG_N = NFLAG_16(quotient); 18.4228 + FLAG_V = VFLAG_CLEAR; 18.4229 + FLAG_C = CFLAG_CLEAR; 18.4230 + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); 18.4231 + return; 18.4232 + } 18.4233 + FLAG_V = VFLAG_SET; 18.4234 + return; 18.4235 + } 18.4236 + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); 18.4237 +} 18.4238 + 18.4239 + 18.4240 +M68KMAKE_OP(divu, 16, ., d) 18.4241 +{ 18.4242 + uint* r_dst = &DX; 18.4243 + uint src = MASK_OUT_ABOVE_16(DY); 18.4244 + 18.4245 + if(src != 0) 18.4246 + { 18.4247 + uint quotient = *r_dst / src; 18.4248 + uint remainder = *r_dst % src; 18.4249 + 18.4250 + if(quotient < 0x10000) 18.4251 + { 18.4252 + FLAG_Z = quotient; 18.4253 + FLAG_N = NFLAG_16(quotient); 18.4254 + FLAG_V = VFLAG_CLEAR; 18.4255 + FLAG_C = CFLAG_CLEAR; 18.4256 + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); 18.4257 + return; 18.4258 + } 18.4259 + FLAG_V = VFLAG_SET; 18.4260 + return; 18.4261 + } 18.4262 + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); 18.4263 +} 18.4264 + 18.4265 + 18.4266 +M68KMAKE_OP(divu, 16, ., .) 18.4267 +{ 18.4268 + uint* r_dst = &DX; 18.4269 + uint src = M68KMAKE_GET_OPER_AY_16; 18.4270 + 18.4271 + if(src != 0) 18.4272 + { 18.4273 + uint quotient = *r_dst / src; 18.4274 + uint remainder = *r_dst % src; 18.4275 + 18.4276 + if(quotient < 0x10000) 18.4277 + { 18.4278 + FLAG_Z = quotient; 18.4279 + FLAG_N = NFLAG_16(quotient); 18.4280 + FLAG_V = VFLAG_CLEAR; 18.4281 + FLAG_C = CFLAG_CLEAR; 18.4282 + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); 18.4283 + return; 18.4284 + } 18.4285 + FLAG_V = VFLAG_SET; 18.4286 + return; 18.4287 + } 18.4288 + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); 18.4289 +} 18.4290 + 18.4291 + 18.4292 +M68KMAKE_OP(divl, 32, ., d) 18.4293 +{ 18.4294 +#if M68K_USE_64_BIT 18.4295 + 18.4296 + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) 18.4297 + { 18.4298 + uint word2 = OPER_I_16(); 18.4299 + uint64 divisor = DY; 18.4300 + uint64 dividend = 0; 18.4301 + uint64 quotient = 0; 18.4302 + uint64 remainder = 0; 18.4303 + 18.4304 + if(divisor != 0) 18.4305 + { 18.4306 + if(BIT_A(word2)) /* 64 bit */ 18.4307 + { 18.4308 + dividend = REG_D[word2 & 7]; 18.4309 + dividend <<= 32; 18.4310 + dividend |= REG_D[(word2 >> 12) & 7]; 18.4311 + 18.4312 + if(BIT_B(word2)) /* signed */ 18.4313 + { 18.4314 + quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor)); 18.4315 + remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor)); 18.4316 + if((sint64)quotient != (sint64)((sint32)quotient)) 18.4317 + { 18.4318 + FLAG_V = VFLAG_SET; 18.4319 + return; 18.4320 + } 18.4321 + } 18.4322 + else /* unsigned */ 18.4323 + { 18.4324 + quotient = dividend / divisor; 18.4325 + if(quotient > 0xffffffff) 18.4326 + { 18.4327 + FLAG_V = VFLAG_SET; 18.4328 + return; 18.4329 + } 18.4330 + remainder = dividend % divisor; 18.4331 + } 18.4332 + } 18.4333 + else /* 32 bit */ 18.4334 + { 18.4335 + dividend = REG_D[(word2 >> 12) & 7]; 18.4336 + if(BIT_B(word2)) /* signed */ 18.4337 + { 18.4338 + quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor)); 18.4339 + remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor)); 18.4340 + } 18.4341 + else /* unsigned */ 18.4342 + { 18.4343 + quotient = dividend / divisor; 18.4344 + remainder = dividend % divisor; 18.4345 + } 18.4346 + } 18.4347 + 18.4348 + REG_D[word2 & 7] = remainder; 18.4349 + REG_D[(word2 >> 12) & 7] = quotient; 18.4350 + 18.4351 + FLAG_N = NFLAG_32(quotient); 18.4352 + FLAG_Z = quotient; 18.4353 + FLAG_V = VFLAG_CLEAR; 18.4354 + FLAG_C = CFLAG_CLEAR; 18.4355 + return; 18.4356 + } 18.4357 + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); 18.4358 + return; 18.4359 + } 18.4360 + m68ki_exception_illegal(); 18.4361 + 18.4362 +#else 18.4363 + 18.4364 + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) 18.4365 + { 18.4366 + uint word2 = OPER_I_16(); 18.4367 + uint divisor = DY; 18.4368 + uint dividend_hi = REG_D[word2 & 7]; 18.4369 + uint dividend_lo = REG_D[(word2 >> 12) & 7]; 18.4370 + uint quotient = 0; 18.4371 + uint remainder = 0; 18.4372 + uint dividend_neg = 0; 18.4373 + uint divisor_neg = 0; 18.4374 + sint i; 18.4375 + uint overflow; 18.4376 + 18.4377 + if(divisor != 0) 18.4378 + { 18.4379 + /* quad / long : long quotient, long remainder */ 18.4380 + if(BIT_A(word2)) 18.4381 + { 18.4382 + if(BIT_B(word2)) /* signed */ 18.4383 + { 18.4384 + /* special case in signed divide */ 18.4385 + if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff) 18.4386 + { 18.4387 + REG_D[word2 & 7] = 0; 18.4388 + REG_D[(word2 >> 12) & 7] = 0x80000000; 18.4389 + 18.4390 + FLAG_N = NFLAG_SET; 18.4391 + FLAG_Z = ZFLAG_CLEAR; 18.4392 + FLAG_V = VFLAG_CLEAR; 18.4393 + FLAG_C = CFLAG_CLEAR; 18.4394 + return; 18.4395 + } 18.4396 + if(GET_MSB_32(dividend_hi)) 18.4397 + { 18.4398 + dividend_neg = 1; 18.4399 + dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0)); 18.4400 + dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo); 18.4401 + } 18.4402 + if(GET_MSB_32(divisor)) 18.4403 + { 18.4404 + divisor_neg = 1; 18.4405 + divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor); 18.4406 + 18.4407 + } 18.4408 + } 18.4409 + 18.4410 + /* if the upper long is greater than the divisor, we're overflowing. */ 18.4411 + if(dividend_hi >= divisor) 18.4412 + { 18.4413 + FLAG_V = VFLAG_SET; 18.4414 + return; 18.4415 + } 18.4416 + 18.4417 + for(i = 31; i >= 0; i--) 18.4418 + { 18.4419 + quotient <<= 1; 18.4420 + remainder = (remainder << 1) + ((dividend_hi >> i) & 1); 18.4421 + if(remainder >= divisor) 18.4422 + { 18.4423 + remainder -= divisor; 18.4424 + quotient++; 18.4425 + } 18.4426 + } 18.4427 + for(i = 31; i >= 0; i--) 18.4428 + { 18.4429 + quotient <<= 1; 18.4430 + overflow = GET_MSB_32(remainder); 18.4431 + remainder = (remainder << 1) + ((dividend_lo >> i) & 1); 18.4432 + if(remainder >= divisor || overflow) 18.4433 + { 18.4434 + remainder -= divisor; 18.4435 + quotient++; 18.4436 + } 18.4437 + } 18.4438 + 18.4439 + if(BIT_B(word2)) /* signed */ 18.4440 + { 18.4441 + if(quotient > 0x7fffffff) 18.4442 + { 18.4443 + FLAG_V = VFLAG_SET; 18.4444 + return; 18.4445 + } 18.4446 + if(dividend_neg) 18.4447 + { 18.4448 + remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder); 18.4449 + quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); 18.4450 + } 18.4451 + if(divisor_neg) 18.4452 + quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); 18.4453 + } 18.4454 + 18.4455 + REG_D[word2 & 7] = remainder; 18.4456 + REG_D[(word2 >> 12) & 7] = quotient; 18.4457 + 18.4458 + FLAG_N = NFLAG_32(quotient); 18.4459 + FLAG_Z = quotient; 18.4460 + FLAG_V = VFLAG_CLEAR; 18.4461 + FLAG_C = CFLAG_CLEAR; 18.4462 + return; 18.4463 + } 18.4464 + 18.4465 + /* long / long: long quotient, maybe long remainder */ 18.4466 + if(BIT_B(word2)) /* signed */ 18.4467 + { 18.4468 + /* Special case in divide */ 18.4469 + if(dividend_lo == 0x80000000 && divisor == 0xffffffff) 18.4470 + { 18.4471 + FLAG_N = NFLAG_SET; 18.4472 + FLAG_Z = ZFLAG_CLEAR; 18.4473 + FLAG_V = VFLAG_CLEAR; 18.4474 + FLAG_C = CFLAG_CLEAR; 18.4475 + REG_D[(word2 >> 12) & 7] = 0x80000000; 18.4476 + REG_D[word2 & 7] = 0; 18.4477 + return; 18.4478 + } 18.4479 + REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor); 18.4480 + quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor); 18.4481 + } 18.4482 + else 18.4483 + { 18.4484 + REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor); 18.4485 + quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor); 18.4486 + } 18.4487 + 18.4488 + FLAG_N = NFLAG_32(quotient); 18.4489 + FLAG_Z = quotient; 18.4490 + FLAG_V = VFLAG_CLEAR; 18.4491 + FLAG_C = CFLAG_CLEAR; 18.4492 + return; 18.4493 + } 18.4494 + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); 18.4495 + return; 18.4496 + } 18.4497 + m68ki_exception_illegal(); 18.4498 + 18.4499 +#endif 18.4500 +} 18.4501 + 18.4502 + 18.4503 +M68KMAKE_OP(divl, 32, ., .) 18.4504 +{ 18.4505 +#if M68K_USE_64_BIT 18.4506 + 18.4507 + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) 18.4508 + { 18.4509 + uint word2 = OPER_I_16(); 18.4510 + uint64 divisor = M68KMAKE_GET_OPER_AY_32; 18.4511 + uint64 dividend = 0; 18.4512 + uint64 quotient = 0; 18.4513 + uint64 remainder = 0; 18.4514 + 18.4515 + if(divisor != 0) 18.4516 + { 18.4517 + if(BIT_A(word2)) /* 64 bit */ 18.4518 + { 18.4519 + dividend = REG_D[word2 & 7]; 18.4520 + dividend <<= 32; 18.4521 + dividend |= REG_D[(word2 >> 12) & 7]; 18.4522 + 18.4523 + if(BIT_B(word2)) /* signed */ 18.4524 + { 18.4525 + quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor)); 18.4526 + remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor)); 18.4527 + if((sint64)quotient != (sint64)((sint32)quotient)) 18.4528 + { 18.4529 + FLAG_V = VFLAG_SET; 18.4530 + return; 18.4531 + } 18.4532 + } 18.4533 + else /* unsigned */ 18.4534 + { 18.4535 + quotient = dividend / divisor; 18.4536 + if(quotient > 0xffffffff) 18.4537 + { 18.4538 + FLAG_V = VFLAG_SET; 18.4539 + return; 18.4540 + } 18.4541 + remainder = dividend % divisor; 18.4542 + } 18.4543 + } 18.4544 + else /* 32 bit */ 18.4545 + { 18.4546 + dividend = REG_D[(word2 >> 12) & 7]; 18.4547 + if(BIT_B(word2)) /* signed */ 18.4548 + { 18.4549 + quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor)); 18.4550 + remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor)); 18.4551 + } 18.4552 + else /* unsigned */ 18.4553 + { 18.4554 + quotient = dividend / divisor; 18.4555 + remainder = dividend % divisor; 18.4556 + } 18.4557 + } 18.4558 + 18.4559 + REG_D[word2 & 7] = remainder; 18.4560 + REG_D[(word2 >> 12) & 7] = quotient; 18.4561 + 18.4562 + FLAG_N = NFLAG_32(quotient); 18.4563 + FLAG_Z = quotient; 18.4564 + FLAG_V = VFLAG_CLEAR; 18.4565 + FLAG_C = CFLAG_CLEAR; 18.4566 + return; 18.4567 + } 18.4568 + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); 18.4569 + return; 18.4570 + } 18.4571 + m68ki_exception_illegal(); 18.4572 + 18.4573 +#else 18.4574 + 18.4575 + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) 18.4576 + { 18.4577 + uint word2 = OPER_I_16(); 18.4578 + uint divisor = M68KMAKE_GET_OPER_AY_32; 18.4579 + uint dividend_hi = REG_D[word2 & 7]; 18.4580 + uint dividend_lo = REG_D[(word2 >> 12) & 7]; 18.4581 + uint quotient = 0; 18.4582 + uint remainder = 0; 18.4583 + uint dividend_neg = 0; 18.4584 + uint divisor_neg = 0; 18.4585 + sint i; 18.4586 + uint overflow; 18.4587 + 18.4588 + if(divisor != 0) 18.4589 + { 18.4590 + /* quad / long : long quotient, long remainder */ 18.4591 + if(BIT_A(word2)) 18.4592 + { 18.4593 + if(BIT_B(word2)) /* signed */ 18.4594 + { 18.4595 + /* special case in signed divide */ 18.4596 + if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff) 18.4597 + { 18.4598 + REG_D[word2 & 7] = 0; 18.4599 + REG_D[(word2 >> 12) & 7] = 0x80000000; 18.4600 + 18.4601 + FLAG_N = NFLAG_SET; 18.4602 + FLAG_Z = ZFLAG_CLEAR; 18.4603 + FLAG_V = VFLAG_CLEAR; 18.4604 + FLAG_C = CFLAG_CLEAR; 18.4605 + return; 18.4606 + } 18.4607 + if(GET_MSB_32(dividend_hi)) 18.4608 + { 18.4609 + dividend_neg = 1; 18.4610 + dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0)); 18.4611 + dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo); 18.4612 + } 18.4613 + if(GET_MSB_32(divisor)) 18.4614 + { 18.4615 + divisor_neg = 1; 18.4616 + divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor); 18.4617 + 18.4618 + } 18.4619 + } 18.4620 + 18.4621 + /* if the upper long is greater than the divisor, we're overflowing. */ 18.4622 + if(dividend_hi >= divisor) 18.4623 + { 18.4624 + FLAG_V = VFLAG_SET; 18.4625 + return; 18.4626 + } 18.4627 + 18.4628 + for(i = 31; i >= 0; i--) 18.4629 + { 18.4630 + quotient <<= 1; 18.4631 + remainder = (remainder << 1) + ((dividend_hi >> i) & 1); 18.4632 + if(remainder >= divisor) 18.4633 + { 18.4634 + remainder -= divisor; 18.4635 + quotient++; 18.4636 + } 18.4637 + } 18.4638 + for(i = 31; i >= 0; i--) 18.4639 + { 18.4640 + quotient <<= 1; 18.4641 + overflow = GET_MSB_32(remainder); 18.4642 + remainder = (remainder << 1) + ((dividend_lo >> i) & 1); 18.4643 + if(remainder >= divisor || overflow) 18.4644 + { 18.4645 + remainder -= divisor; 18.4646 + quotient++; 18.4647 + } 18.4648 + } 18.4649 + 18.4650 + if(BIT_B(word2)) /* signed */ 18.4651 + { 18.4652 + if(quotient > 0x7fffffff) 18.4653 + { 18.4654 + FLAG_V = VFLAG_SET; 18.4655 + return; 18.4656 + } 18.4657 + if(dividend_neg) 18.4658 + { 18.4659 + remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder); 18.4660 + quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); 18.4661 + } 18.4662 + if(divisor_neg) 18.4663 + quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); 18.4664 + } 18.4665 + 18.4666 + REG_D[word2 & 7] = remainder; 18.4667 + REG_D[(word2 >> 12) & 7] = quotient; 18.4668 + 18.4669 + FLAG_N = NFLAG_32(quotient); 18.4670 + FLAG_Z = quotient; 18.4671 + FLAG_V = VFLAG_CLEAR; 18.4672 + FLAG_C = CFLAG_CLEAR; 18.4673 + return; 18.4674 + } 18.4675 + 18.4676 + /* long / long: long quotient, maybe long remainder */ 18.4677 + if(BIT_B(word2)) /* signed */ 18.4678 + { 18.4679 + /* Special case in divide */ 18.4680 + if(dividend_lo == 0x80000000 && divisor == 0xffffffff) 18.4681 + { 18.4682 + FLAG_N = NFLAG_SET; 18.4683 + FLAG_Z = ZFLAG_CLEAR; 18.4684 + FLAG_V = VFLAG_CLEAR; 18.4685 + FLAG_C = CFLAG_CLEAR; 18.4686 + REG_D[(word2 >> 12) & 7] = 0x80000000; 18.4687 + REG_D[word2 & 7] = 0; 18.4688 + return; 18.4689 + } 18.4690 + REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor); 18.4691 + quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor); 18.4692 + } 18.4693 + else 18.4694 + { 18.4695 + REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor); 18.4696 + quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor); 18.4697 + } 18.4698 + 18.4699 + FLAG_N = NFLAG_32(quotient); 18.4700 + FLAG_Z = quotient; 18.4701 + FLAG_V = VFLAG_CLEAR; 18.4702 + FLAG_C = CFLAG_CLEAR; 18.4703 + return; 18.4704 + } 18.4705 + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); 18.4706 + return; 18.4707 + } 18.4708 + m68ki_exception_illegal(); 18.4709 + 18.4710 +#endif 18.4711 +} 18.4712 + 18.4713 + 18.4714 +M68KMAKE_OP(eor, 8, ., d) 18.4715 +{ 18.4716 + uint res = MASK_OUT_ABOVE_8(DY ^= MASK_OUT_ABOVE_8(DX)); 18.4717 + 18.4718 + FLAG_N = NFLAG_8(res); 18.4719 + FLAG_Z = res; 18.4720 + FLAG_C = CFLAG_CLEAR; 18.4721 + FLAG_V = VFLAG_CLEAR; 18.4722 +} 18.4723 + 18.4724 + 18.4725 +M68KMAKE_OP(eor, 8, ., .) 18.4726 +{ 18.4727 + uint ea = M68KMAKE_GET_EA_AY_8; 18.4728 + uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea)); 18.4729 + 18.4730 + m68ki_write_8(ea, res); 18.4731 + 18.4732 + FLAG_N = NFLAG_8(res); 18.4733 + FLAG_Z = res; 18.4734 + FLAG_C = CFLAG_CLEAR; 18.4735 + FLAG_V = VFLAG_CLEAR; 18.4736 +} 18.4737 + 18.4738 + 18.4739 +M68KMAKE_OP(eor, 16, ., d) 18.4740 +{ 18.4741 + uint res = MASK_OUT_ABOVE_16(DY ^= MASK_OUT_ABOVE_16(DX)); 18.4742 + 18.4743 + FLAG_N = NFLAG_16(res); 18.4744 + FLAG_Z = res; 18.4745 + FLAG_C = CFLAG_CLEAR; 18.4746 + FLAG_V = VFLAG_CLEAR; 18.4747 +} 18.4748 + 18.4749 + 18.4750 +M68KMAKE_OP(eor, 16, ., .) 18.4751 +{ 18.4752 + uint ea = M68KMAKE_GET_EA_AY_16; 18.4753 + uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea)); 18.4754 + 18.4755 + m68ki_write_16(ea, res); 18.4756 + 18.4757 + FLAG_N = NFLAG_16(res); 18.4758 + FLAG_Z = res; 18.4759 + FLAG_C = CFLAG_CLEAR; 18.4760 + FLAG_V = VFLAG_CLEAR; 18.4761 +} 18.4762 + 18.4763 + 18.4764 +M68KMAKE_OP(eor, 32, ., d) 18.4765 +{ 18.4766 + uint res = DY ^= DX; 18.4767 + 18.4768 + FLAG_N = NFLAG_32(res); 18.4769 + FLAG_Z = res; 18.4770 + FLAG_C = CFLAG_CLEAR; 18.4771 + FLAG_V = VFLAG_CLEAR; 18.4772 +} 18.4773 + 18.4774 + 18.4775 +M68KMAKE_OP(eor, 32, ., .) 18.4776 +{ 18.4777 + uint ea = M68KMAKE_GET_EA_AY_32; 18.4778 + uint res = DX ^ m68ki_read_32(ea); 18.4779 + 18.4780 + m68ki_write_32(ea, res); 18.4781 + 18.4782 + FLAG_N = NFLAG_32(res); 18.4783 + FLAG_Z = res; 18.4784 + FLAG_C = CFLAG_CLEAR; 18.4785 + FLAG_V = VFLAG_CLEAR; 18.4786 +} 18.4787 + 18.4788 + 18.4789 +M68KMAKE_OP(eori, 8, ., d) 18.4790 +{ 18.4791 + uint res = MASK_OUT_ABOVE_8(DY ^= OPER_I_8()); 18.4792 + 18.4793 + FLAG_N = NFLAG_8(res); 18.4794 + FLAG_Z = res; 18.4795 + FLAG_C = CFLAG_CLEAR; 18.4796 + FLAG_V = VFLAG_CLEAR; 18.4797 +} 18.4798 + 18.4799 + 18.4800 +M68KMAKE_OP(eori, 8, ., .) 18.4801 +{ 18.4802 + uint src = OPER_I_8(); 18.4803 + uint ea = M68KMAKE_GET_EA_AY_8; 18.4804 + uint res = src ^ m68ki_read_8(ea); 18.4805 + 18.4806 + m68ki_write_8(ea, res); 18.4807 + 18.4808 + FLAG_N = NFLAG_8(res); 18.4809 + FLAG_Z = res; 18.4810 + FLAG_C = CFLAG_CLEAR; 18.4811 + FLAG_V = VFLAG_CLEAR; 18.4812 +} 18.4813 + 18.4814 + 18.4815 +M68KMAKE_OP(eori, 16, ., d) 18.4816 +{ 18.4817 + uint res = MASK_OUT_ABOVE_16(DY ^= OPER_I_16()); 18.4818 + 18.4819 + FLAG_N = NFLAG_16(res); 18.4820 + FLAG_Z = res; 18.4821 + FLAG_C = CFLAG_CLEAR; 18.4822 + FLAG_V = VFLAG_CLEAR; 18.4823 +} 18.4824 + 18.4825 + 18.4826 +M68KMAKE_OP(eori, 16, ., .) 18.4827 +{ 18.4828 + uint src = OPER_I_16(); 18.4829 + uint ea = M68KMAKE_GET_EA_AY_16; 18.4830 + uint res = src ^ m68ki_read_16(ea); 18.4831 + 18.4832 + m68ki_write_16(ea, res); 18.4833 + 18.4834 + FLAG_N = NFLAG_16(res); 18.4835 + FLAG_Z = res; 18.4836 + FLAG_C = CFLAG_CLEAR; 18.4837 + FLAG_V = VFLAG_CLEAR; 18.4838 +} 18.4839 + 18.4840 + 18.4841 +M68KMAKE_OP(eori, 32, ., d) 18.4842 +{ 18.4843 + uint res = DY ^= OPER_I_32(); 18.4844 + 18.4845 + FLAG_N = NFLAG_32(res); 18.4846 + FLAG_Z = res; 18.4847 + FLAG_C = CFLAG_CLEAR; 18.4848 + FLAG_V = VFLAG_CLEAR; 18.4849 +} 18.4850 + 18.4851 + 18.4852 +M68KMAKE_OP(eori, 32, ., .) 18.4853 +{ 18.4854 + uint src = OPER_I_32(); 18.4855 + uint ea = M68KMAKE_GET_EA_AY_32; 18.4856 + uint res = src ^ m68ki_read_32(ea); 18.4857 + 18.4858 + m68ki_write_32(ea, res); 18.4859 + 18.4860 + FLAG_N = NFLAG_32(res); 18.4861 + FLAG_Z = res; 18.4862 + FLAG_C = CFLAG_CLEAR; 18.4863 + FLAG_V = VFLAG_CLEAR; 18.4864 +} 18.4865 + 18.4866 + 18.4867 +M68KMAKE_OP(eori, 16, toc, .) 18.4868 +{ 18.4869 + m68ki_set_ccr(m68ki_get_ccr() ^ OPER_I_16()); 18.4870 +} 18.4871 + 18.4872 + 18.4873 +M68KMAKE_OP(eori, 16, tos, .) 18.4874 +{ 18.4875 + if(FLAG_S) 18.4876 + { 18.4877 + uint src = OPER_I_16(); 18.4878 + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ 18.4879 + m68ki_set_sr(m68ki_get_sr() ^ src); 18.4880 + return; 18.4881 + } 18.4882 + m68ki_exception_privilege_violation(); 18.4883 +} 18.4884 + 18.4885 + 18.4886 +M68KMAKE_OP(exg, 32, dd, .) 18.4887 +{ 18.4888 + uint* reg_a = &DX; 18.4889 + uint* reg_b = &DY; 18.4890 + uint tmp = *reg_a; 18.4891 + *reg_a = *reg_b; 18.4892 + *reg_b = tmp; 18.4893 +} 18.4894 + 18.4895 + 18.4896 +M68KMAKE_OP(exg, 32, aa, .) 18.4897 +{ 18.4898 + uint* reg_a = &AX; 18.4899 + uint* reg_b = &AY; 18.4900 + uint tmp = *reg_a; 18.4901 + *reg_a = *reg_b; 18.4902 + *reg_b = tmp; 18.4903 +} 18.4904 + 18.4905 + 18.4906 +M68KMAKE_OP(exg, 32, da, .) 18.4907 +{ 18.4908 + uint* reg_a = &DX; 18.4909 + uint* reg_b = &AY; 18.4910 + uint tmp = *reg_a; 18.4911 + *reg_a = *reg_b; 18.4912 + *reg_b = tmp; 18.4913 +} 18.4914 + 18.4915 + 18.4916 +M68KMAKE_OP(ext, 16, ., .) 18.4917 +{ 18.4918 + uint* r_dst = &DY; 18.4919 + 18.4920 + *r_dst = MASK_OUT_BELOW_16(*r_dst) | MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xff00 : 0); 18.4921 + 18.4922 + FLAG_N = NFLAG_16(*r_dst); 18.4923 + FLAG_Z = MASK_OUT_ABOVE_16(*r_dst); 18.4924 + FLAG_V = VFLAG_CLEAR; 18.4925 + FLAG_C = CFLAG_CLEAR; 18.4926 +} 18.4927 + 18.4928 + 18.4929 +M68KMAKE_OP(ext, 32, ., .) 18.4930 +{ 18.4931 + uint* r_dst = &DY; 18.4932 + 18.4933 + *r_dst = MASK_OUT_ABOVE_16(*r_dst) | (GET_MSB_16(*r_dst) ? 0xffff0000 : 0); 18.4934 + 18.4935 + FLAG_N = NFLAG_32(*r_dst); 18.4936 + FLAG_Z = *r_dst; 18.4937 + FLAG_V = VFLAG_CLEAR; 18.4938 + FLAG_C = CFLAG_CLEAR; 18.4939 +} 18.4940 + 18.4941 + 18.4942 +M68KMAKE_OP(extb, 32, ., .) 18.4943 +{ 18.4944 + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) 18.4945 + { 18.4946 + uint* r_dst = &DY; 18.4947 + 18.4948 + *r_dst = MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xffffff00 : 0); 18.4949 + 18.4950 + FLAG_N = NFLAG_32(*r_dst); 18.4951 + FLAG_Z = *r_dst; 18.4952 + FLAG_V = VFLAG_CLEAR; 18.4953 + FLAG_C = CFLAG_CLEAR; 18.4954 + return; 18.4955 + } 18.4956 + m68ki_exception_illegal(); 18.4957 +} 18.4958 + 18.4959 + 18.4960 +M68KMAKE_OP(illegal, 0, ., .) 18.4961 +{ 18.4962 + m68ki_exception_illegal(); 18.4963 +} 18.4964 + 18.4965 +M68KMAKE_OP(jmp, 32, ., .) 18.4966 +{ 18.4967 + m68ki_jump(M68KMAKE_GET_EA_AY_32); 18.4968 + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ 18.4969 + if(REG_PC == REG_PPC) 18.4970 + USE_ALL_CYCLES(); 18.4971 +} 18.4972 + 18.4973 + 18.4974 +M68KMAKE_OP(jsr, 32, ., .) 18.4975 +{ 18.4976 + uint ea = M68KMAKE_GET_EA_AY_32; 18.4977 + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ 18.4978 + m68ki_push_32(REG_PC); 18.4979 + m68ki_jump(ea); 18.4980 +} 18.4981 + 18.4982 + 18.4983 +M68KMAKE_OP(lea, 32, ., .) 18.4984 +{ 18.4985 + AX = M68KMAKE_GET_EA_AY_32; 18.4986 +} 18.4987 + 18.4988 + 18.4989 +M68KMAKE_OP(link, 16, ., a7) 18.4990 +{ 18.4991 + REG_A[7] -= 4; 18.4992 + m68ki_write_32(REG_A[7], REG_A[7]); 18.4993 + REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16())); 18.4994 +} 18.4995 + 18.4996 + 18.4997 +M68KMAKE_OP(link, 16, ., .) 18.4998 +{ 18.4999 + uint* r_dst = &AY; 18.5000 + 18.5001 + m68ki_push_32(*r_dst); 18.5002 + *r_dst = REG_A[7]; 18.5003 + REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16())); 18.5004 +} 18.5005 + 18.5006 + 18.5007 +M68KMAKE_OP(link, 32, ., a7) 18.5008 +{ 18.5009 + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) 18.5010 + { 18.5011 + REG_A[7] -= 4; 18.5012 + m68ki_write_32(REG_A[7], REG_A[7]); 18.5013 + REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32()); 18.5014 + return; 18.5015 + } 18.5016 + m68ki_exception_illegal(); 18.5017 +} 18.5018 + 18.5019 + 18.5020 +M68KMAKE_OP(link, 32, ., .) 18.5021 +{ 18.5022 + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) 18.5023 + { 18.5024 + uint* r_dst = &AY; 18.5025 + 18.5026 + m68ki_push_32(*r_dst); 18.5027 + *r_dst = REG_A[7]; 18.5028 + REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32()); 18.5029 + return; 18.5030 + } 18.5031 + m68ki_exception_illegal(); 18.5032 +} 18.5033 + 18.5034 + 18.5035 +M68KMAKE_OP(lsr, 8, s, .) 18.5036 +{ 18.5037 + uint* r_dst = &DY; 18.5038 + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; 18.5039 + uint src = MASK_OUT_ABOVE_8(*r_dst); 18.5040 + uint res = src >> shift; 18.5041 + 18.5042 + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; 18.5043 + 18.5044 + FLAG_N = NFLAG_CLEAR; 18.5045 + FLAG_Z = res; 18.5046 + FLAG_X = FLAG_C = src << (9-shift); 18.5047 + FLAG_V = VFLAG_CLEAR; 18.5048 +} 18.5049 + 18.5050 + 18.5051 +M68KMAKE_OP(lsr, 16, s, .) 18.5052 +{ 18.5053 + uint* r_dst = &DY; 18.5054 + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; 18.5055 + uint src = MASK_OUT_ABOVE_16(*r_dst); 18.5056 + uint res = src >> shift; 18.5057 + 18.5058 + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; 18.5059 + 18.5060 + FLAG_N = NFLAG_CLEAR; 18.5061 + FLAG_Z = res; 18.5062 + FLAG_X = FLAG_C = src << (9-shift); 18.5063 + FLAG_V = VFLAG_CLEAR; 18.5064 +} 18.5065 + 18.5066 + 18.5067 +M68KMAKE_OP(lsr, 32, s, .) 18.5068 +{ 18.5069 + uint* r_dst = &DY; 18.5070 + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; 18.5071 + uint src = *r_dst; 18.5072 + uint res = src >> shift; 18.5073 + 18.5074 + *r_dst = res; 18.5075 + 18.5076 + FLAG_N = NFLAG_CLEAR; 18.5077 + FLAG_Z = res; 18.5078 + FLAG_X = FLAG_C = src << (9-shift); 18.5079 + FLAG_V = VFLAG_CLEAR; 18.5080 +} 18.5081 + 18.5082 + 18.5083 +M68KMAKE_OP(lsr, 8, r, .) 18.5084 +{ 18.5085 + uint* r_dst = &DY; 18.5086 + uint shift = DX & 0x3f; 18.5087 + uint src = MASK_OUT_ABOVE_8(*r_dst); 18.5088 + uint res = src >> shift; 18.5089 + 18.5090 + if(shift != 0) 18.5091 + { 18.5092 + USE_CYCLES(shift<<CYC_SHIFT); 18.5093 + 18.5094 + if(shift <= 8) 18.5095 + { 18.5096 + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; 18.5097 + FLAG_X = FLAG_C = src << (9-shift); 18.5098 + FLAG_N = NFLAG_CLEAR; 18.5099 + FLAG_Z = res; 18.5100 + FLAG_V = VFLAG_CLEAR; 18.5101 + return; 18.5102 + } 18.5103 + 18.5104 + *r_dst &= 0xffffff00; 18.5105 + FLAG_X = XFLAG_CLEAR; 18.5106 + FLAG_C = CFLAG_CLEAR; 18.5107 + FLAG_N = NFLAG_CLEAR; 18.5108 + FLAG_Z = ZFLAG_SET; 18.5109 + FLAG_V = VFLAG_CLEAR; 18.5110 + return; 18.5111 + } 18.5112 + 18.5113 + FLAG_C = CFLAG_CLEAR; 18.5114 + FLAG_N = NFLAG_8(src); 18.5115 + FLAG_Z = src; 18.5116 + FLAG_V = VFLAG_CLEAR; 18.5117 +} 18.5118 + 18.5119 + 18.5120 +M68KMAKE_OP(lsr, 16, r, .) 18.5121 +{ 18.5122 + uint* r_dst = &DY; 18.5123 + uint shift = DX & 0x3f; 18.5124 + uint src = MASK_OUT_ABOVE_16(*r_dst); 18.5125 + uint res = src >> shift; 18.5126 + 18.5127 + if(shift != 0) 18.5128 + { 18.5129 + USE_CYCLES(shift<<CYC_SHIFT); 18.5130 + 18.5131 + if(shift <= 16) 18.5132 + { 18.5133 + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; 18.5134 + FLAG_C = FLAG_X = (src >> (shift - 1))<<8; 18.5135 + FLAG_N = NFLAG_CLEAR; 18.5136 + FLAG_Z = res; 18.5137 + FLAG_V = VFLAG_CLEAR; 18.5138 + return; 18.5139 + } 18.5140 + 18.5141 + *r_dst &= 0xffff0000; 18.5142 + FLAG_X = XFLAG_CLEAR; 18.5143 + FLAG_C = CFLAG_CLEAR; 18.5144 + FLAG_N = NFLAG_CLEAR; 18.5145 + FLAG_Z = ZFLAG_SET; 18.5146 + FLAG_V = VFLAG_CLEAR; 18.5147 + return; 18.5148 + } 18.5149 + 18.5150 + FLAG_C = CFLAG_CLEAR; 18.5151 + FLAG_N = NFLAG_16(src); 18.5152 + FLAG_Z = src; 18.5153 + FLAG_V = VFLAG_CLEAR; 18.5154 +} 18.5155 + 18.5156 + 18.5157 +M68KMAKE_OP(lsr, 32, r, .) 18.5158 +{ 18.5159 + uint* r_dst = &DY; 18.5160 + uint shift = DX & 0x3f; 18.5161 + uint src = *r_dst; 18.5162 + uint res = src >> shift; 18.5163 + 18.5164 + if(shift != 0) 18.5165 + { 18.5166 + USE_CYCLES(shift<<CYC_SHIFT); 18.5167 + 18.5168 + if(shift < 32) 18.5169 + { 18.5170 + *r_dst = res; 18.5171 + FLAG_C = FLAG_X = (src >> (shift - 1))<<8; 18.5172 + FLAG_N = NFLAG_CLEAR; 18.5173 + FLAG_Z = res; 18.5174 + FLAG_V = VFLAG_CLEAR; 18.5175 + return; 18.5176 + } 18.5177 + 18.5178 + *r_dst = 0; 18.5179 + FLAG_X = FLAG_C = (shift == 32 ? GET_MSB_32(src)>>23 : 0); 18.5180 + FLAG_N = NFLAG_CLEAR; 18.5181 + FLAG_Z = ZFLAG_SET; 18.5182 + FLAG_V = VFLAG_CLEAR; 18.5183 + return; 18.5184 + } 18.5185 + 18.5186 + FLAG_C = CFLAG_CLEAR; 18.5187 + FLAG_N = NFLAG_32(src); 18.5188 + FLAG_Z = src; 18.5189 + FLAG_V = VFLAG_CLEAR; 18.5190 +} 18.5191 + 18.5192 + 18.5193 +M68KMAKE_OP(lsr, 16, ., .) 18.5194 +{ 18.5195 + uint ea = M68KMAKE_GET_EA_AY_16; 18.5196 + uint src = m68ki_read_16(ea); 18.5197 + uint res = src >> 1; 18.5198 + 18.5199 + m68ki_write_16(ea, res); 18.5200 + 18.5201 + FLAG_N = NFLAG_CLEAR; 18.5202 + FLAG_Z = res; 18.5203 + FLAG_C = FLAG_X = src << 8; 18.5204 + FLAG_V = VFLAG_CLEAR; 18.5205 +} 18.5206 + 18.5207 + 18.5208 +M68KMAKE_OP(lsl, 8, s, .) 18.5209 +{ 18.5210 + uint* r_dst = &DY; 18.5211 + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; 18.5212 + uint src = MASK_OUT_ABOVE_8(*r_dst); 18.5213 + uint res = MASK_OUT_ABOVE_8(src << shift); 18.5214 + 18.5215 + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; 18.5216 + 18.5217 + FLAG_N = NFLAG_8(res); 18.5218 + FLAG_Z = res; 18.5219 + FLAG_X = FLAG_C = src << shift; 18.5220 + FLAG_V = VFLAG_CLEAR; 18.5221 +} 18.5222 + 18.5223 + 18.5224 +M68KMAKE_OP(lsl, 16, s, .) 18.5225 +{ 18.5226 + uint* r_dst = &DY; 18.5227 + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; 18.5228 + uint src = MASK_OUT_ABOVE_16(*r_dst); 18.5229 + uint res = MASK_OUT_ABOVE_16(src << shift); 18.5230 + 18.5231 + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; 18.5232 + 18.5233 + FLAG_N = NFLAG_16(res); 18.5234 + FLAG_Z = res; 18.5235 + FLAG_X = FLAG_C = src >> (8-shift); 18.5236 + FLAG_V = VFLAG_CLEAR; 18.5237 +} 18.5238 + 18.5239 + 18.5240 +M68KMAKE_OP(lsl, 32, s, .) 18.5241 +{ 18.5242 + uint* r_dst = &DY; 18.5243 + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; 18.5244 + uint src = *r_dst; 18.5245 + uint res = MASK_OUT_ABOVE_32(src << shift); 18.5246 + 18.5247 + *r_dst = res; 18.5248 + 18.5249 + FLAG_N = NFLAG_32(res); 18.5250 + FLAG_Z = res; 18.5251 + FLAG_X = FLAG_C = src >> (24-shift); 18.5252 + FLAG_V = VFLAG_CLEAR; 18.5253 +} 18.5254 + 18.5255 + 18.5256 +M68KMAKE_OP(lsl, 8, r, .) 18.5257 +{ 18.5258 + uint* r_dst = &DY; 18.5259 + uint shift = DX & 0x3f; 18.5260 + uint src = MASK_OUT_ABOVE_8(*r_dst); 18.5261 + uint res = MASK_OUT_ABOVE_8(src << shift); 18.5262 + 18.5263 + if(shift != 0) 18.5264 + { 18.5265 + USE_CYCLES(shift<<CYC_SHIFT); 18.5266 + 18.5267 + if(shift <= 8) 18.5268 + { 18.5269 + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; 18.5270 + FLAG_X = FLAG_C = src << shift; 18.5271 + FLAG_N = NFLAG_8(res); 18.5272 + FLAG_Z = res; 18.5273 + FLAG_V = VFLAG_CLEAR; 18.5274 + return; 18.5275 + } 18.5276 + 18.5277 + *r_dst &= 0xffffff00; 18.5278 + FLAG_X = XFLAG_CLEAR; 18.5279 + FLAG_C = CFLAG_CLEAR; 18.5280 + FLAG_N = NFLAG_CLEAR; 18.5281 + FLAG_Z = ZFLAG_SET; 18.5282 + FLAG_V = VFLAG_CLEAR; 18.5283 + return; 18.5284 + } 18.5285 + 18.5286 + FLAG_C = CFLAG_CLEAR; 18.5287 + FLAG_N = NFLAG_8(src); 18.5288 + FLAG_Z = src; 18.5289 + FLAG_V = VFLAG_CLEAR; 18.5290 +} 18.5291 + 18.5292 + 18.5293 +M68KMAKE_OP(lsl, 16, r, .) 18.5294 +{ 18.5295 + uint* r_dst = &DY; 18.5296 + uint shift = DX & 0x3f; 18.5297 + uint src = MASK_OUT_ABOVE_16(*r_dst); 18.5298 + uint res = MASK_OUT_ABOVE_16(src << shift); 18.5299 + 18.5300 + if(shift != 0) 18.5301 + { 18.5302 + USE_CYCLES(shift<<CYC_SHIFT); 18.5303 + 18.5304 + if(shift <= 16) 18.5305 + { 18.5306 + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; 18.5307 + FLAG_X = FLAG_C = (src << shift) >> 8; 18.5308 + FLAG_N = NFLAG_16(res); 18.5309 + FLAG_Z = res; 18.5310 + FLAG_V = VFLAG_CLEAR; 18.5311 + return; 18.5312 + } 18.5313 + 18.5314 + *r_dst &= 0xffff0000; 18.5315 + FLAG_X = XFLAG_CLEAR; 18.5316 + FLAG_C = CFLAG_CLEAR; 18.5317 + FLAG_N = NFLAG_CLEAR; 18.5318 + FLAG_Z = ZFLAG_SET; 18.5319 + FLAG_V = VFLAG_CLEAR; 18.5320 + return; 18.5321 + } 18.5322 + 18.5323 + FLAG_C = CFLAG_CLEAR; 18.5324 + FLAG_N = NFLAG_16(src); 18.5325 + FLAG_Z = src; 18.5326 + FLAG_V = VFLAG_CLEAR; 18.5327 +} 18.5328 + 18.5329 + 18.5330 +M68KMAKE_OP(lsl, 32, r, .) 18.5331 +{ 18.5332 + uint* r_dst = &DY; 18.5333 + uint shift = DX & 0x3f; 18.5334 + uint src = *r_dst; 18.5335 + uint res = MASK_OUT_ABOVE_32(src << shift); 18.5336 + 18.5337 + if(shift != 0) 18.5338 + { 18.5339 + USE_CYCLES(shift<<CYC_SHIFT); 18.5340 + 18.5341 + if(shift < 32) 18.5342 + { 18.5343 + *r_dst = res; 18.5344 + FLAG_X = FLAG_C = (src >> (32 - shift)) << 8; 18.5345 + FLAG_N = NFLAG_32(res); 18.5346 + FLAG_Z = res; 18.5347 + FLAG_V = VFLAG_CLEAR; 18.5348 + return; 18.5349 + } 18.5350 + 18.5351 + *r_dst = 0; 18.5352 + FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8; 18.5353 + FLAG_N = NFLAG_CLEAR; 18.5354 + FLAG_Z = ZFLAG_SET; 18.5355 + FLAG_V = VFLAG_CLEAR; 18.5356 + return; 18.5357 + } 18.5358 + 18.5359 + FLAG_C = CFLAG_CLEAR; 18.5360 + FLAG_N = NFLAG_32(src); 18.5361 + FLAG_Z = src; 18.5362 + FLAG_V = VFLAG_CLEAR; 18.5363 +} 18.5364 + 18.5365 + 18.5366 +M68KMAKE_OP(lsl, 16, ., .) 18.5367 +{ 18.5368 + uint ea = M68KMAKE_GET_EA_AY_16; 18.5369 + uint src = m68ki_read_16(ea); 18.5370 + uint res = MASK_OUT_ABOVE_16(src << 1); 18.5371 + 18.5372 + m68ki_write_16(ea, res); 18.5373 + 18.5374 + FLAG_N = NFLAG_16(res); 18.5375 + FLAG_Z = res; 18.5376 + FLAG_X = FLAG_C = src >> 7; 18.5377 + FLAG_V = VFLAG_CLEAR; 18.5378 +} 18.5379 + 18.5380 + 18.5381 +M68KMAKE_OP(move, 8, d, d) 18.5382 +{ 18.5383 + uint res = MASK_OUT_ABOVE_8(DY); 18.5384 + uint* r_dst = &DX; 18.5385 + 18.5386 + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; 18.5387 + 18.5388 + FLAG_N = NFLAG_8(res); 18.5389 + FLAG_Z = res; 18.5390 + FLAG_V = VFLAG_CLEAR; 18.5391 + FLAG_C = CFLAG_CLEAR; 18.5392 +} 18.5393 + 18.5394 + 18.5395 +M68KMAKE_OP(move, 8, d, .) 18.5396 +{ 18.5397 + uint res = M68KMAKE_GET_OPER_AY_8; 18.5398 + uint* r_dst = &DX; 18.5399 + 18.5400 + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; 18.5401 + 18.5402 + FLAG_N = NFLAG_8(res); 18.5403 + FLAG_Z = res; 18.5404 + FLAG_V = VFLAG_CLEAR; 18.5405 + FLAG_C = CFLAG_CLEAR; 18.5406 +} 18.5407 + 18.5408 + 18.5409 +M68KMAKE_OP(move, 8, ai, d) 18.5410 +{ 18.5411 + uint res = MASK_OUT_ABOVE_8(DY); 18.5412 + uint ea = EA_AX_AI_8(); 18.5413 + 18.5414 + m68ki_write_8(ea, res); 18.5415 + 18.5416 + FLAG_N = NFLAG_8(res); 18.5417 + FLAG_Z = res; 18.5418 + FLAG_V = VFLAG_CLEAR; 18.5419 + FLAG_C = CFLAG_CLEAR; 18.5420 +} 18.5421 + 18.5422 + 18.5423 +M68KMAKE_OP(move, 8, ai, .) 18.5424 +{ 18.5425 + uint res = M68KMAKE_GET_OPER_AY_8; 18.5426 + uint ea = EA_AX_AI_8(); 18.5427 + 18.5428 + m68ki_write_8(ea, res); 18.5429 + 18.5430 + FLAG_N = NFLAG_8(res); 18.5431 + FLAG_Z = res; 18.5432 + FLAG_V = VFLAG_CLEAR; 18.5433 + FLAG_C = CFLAG_CLEAR; 18.5434 +} 18.5435 + 18.5436 + 18.5437 +M68KMAKE_OP(move, 8, pi7, d) 18.5438 +{ 18.5439 + uint res = MASK_OUT_ABOVE_8(DY); 18.5440 + uint ea = EA_A7_PI_8(); 18.5441 + 18.5442 + m68ki_write_8(ea, res); 18.5443 + 18.5444 + FLAG_N = NFLAG_8(res); 18.5445 + FLAG_Z = res; 18.5446 + FLAG_V = VFLAG_CLEAR; 18.5447 + FLAG_C = CFLAG_CLEAR; 18.5448 +} 18.5449 + 18.5450 + 18.5451 +M68KMAKE_OP(move, 8, pi, d) 18.5452 +{ 18.5453 + uint res = MASK_OUT_ABOVE_8(DY); 18.5454 + uint ea = EA_AX_PI_8(); 18.5455 + 18.5456 + m68ki_write_8(ea, res); 18.5457 + 18.5458 + FLAG_N = NFLAG_8(res); 18.5459 + FLAG_Z = res; 18.5460 + FLAG_V = VFLAG_CLEAR; 18.5461 + FLAG_C = CFLAG_CLEAR; 18.5462 +} 18.5463 + 18.5464 + 18.5465 +M68KMAKE_OP(move, 8, pi7, .) 18.5466 +{ 18.5467 + uint res = M68KMAKE_GET_OPER_AY_8; 18.5468 + uint ea = EA_A7_PI_8(); 18.5469 + 18.5470 + m68ki_write_8(ea, res); 18.5471 + 18.5472 + FLAG_N = NFLAG_8(res); 18.5473 + FLAG_Z = res; 18.5474 + FLAG_V = VFLAG_CLEAR; 18.5475 + FLAG_C = CFLAG_CLEAR; 18.5476 +} 18.5477 + 18.5478 + 18.5479 +M68KMAKE_OP(move, 8, pi, .) 18.5480 +{ 18.5481 + uint res = M68KMAKE_GET_OPER_AY_8; 18.5482 + uint ea = EA_AX_PI_8(); 18.5483 + 18.5484 + m68ki_write_8(ea, res); 18.5485 + 18.5486 + FLAG_N = NFLAG_8(res); 18.5487 + FLAG_Z = res; 18.5488 + FLAG_V = VFLAG_CLEAR; 18.5489 + FLAG_C = CFLAG_CLEAR; 18.5490 +} 18.5491 + 18.5492 + 18.5493 +M68KMAKE_OP(move, 8, pd7, d) 18.5494 +{ 18.5495 + uint res = MASK_OUT_ABOVE_8(DY); 18.5496 + uint ea = EA_A7_PD_8(); 18.5497 + 18.5498 + m68ki_write_8(ea, res); 18.5499 + 18.5500 + FLAG_N = NFLAG_8(res); 18.5501 + FLAG_Z = res; 18.5502 + FLAG_V = VFLAG_CLEAR; 18.5503 + FLAG_C = CFLAG_CLEAR; 18.5504 +} 18.5505 + 18.5506 + 18.5507 +M68KMAKE_OP(move, 8, pd, d) 18.5508 +{ 18.5509 + uint res = MASK_OUT_ABOVE_8(DY); 18.5510 + uint ea = EA_AX_PD_8(); 18.5511 + 18.5512 + m68ki_write_8(ea, res); 18.5513 + 18.5514 + FLAG_N = NFLAG_8(res); 18.5515 + FLAG_Z = res; 18.5516 + FLAG_V = VFLAG_CLEAR; 18.5517 + FLAG_C = CFLAG_CLEAR; 18.5518 +} 18.5519 + 18.5520 + 18.5521 +M68KMAKE_OP(move, 8, pd7, .) 18.5522 +{ 18.5523 + uint res = M68KMAKE_GET_OPER_AY_8; 18.5524 + uint ea = EA_A7_PD_8(); 18.5525 + 18.5526 + m68ki_write_8(ea, res); 18.5527 + 18.5528 + FLAG_N = NFLAG_8(res); 18.5529 + FLAG_Z = res; 18.5530 + FLAG_V = VFLAG_CLEAR; 18.5531 + FLAG_C = CFLAG_CLEAR; 18.5532 +} 18.5533 + 18.5534 + 18.5535 +M68KMAKE_OP(move, 8, pd, .) 18.5536 +{ 18.5537 + uint res = M68KMAKE_GET_OPER_AY_8; 18.5538 + uint ea = EA_AX_PD_8(); 18.5539 + 18.5540 + m68ki_write_8(ea, res); 18.5541 + 18.5542 + FLAG_N = NFLAG_8(res); 18.5543 + FLAG_Z = res; 18.5544 + FLAG_V = VFLAG_CLEAR; 18.5545 + FLAG_C = CFLAG_CLEAR; 18.5546 +} 18.5547 + 18.5548 + 18.5549 +M68KMAKE_OP(move, 8, di, d) 18.5550 +{ 18.5551 + uint res = MASK_OUT_ABOVE_8(DY); 18.5552 + uint ea = EA_AX_DI_8(); 18.5553 + 18.5554 + m68ki_write_8(ea, res); 18.5555 + 18.5556 + FLAG_N = NFLAG_8(res); 18.5557 + FLAG_Z = res; 18.5558 + FLAG_V = VFLAG_CLEAR; 18.5559 + FLAG_C = CFLAG_CLEAR; 18.5560 +} 18.5561 + 18.5562 + 18.5563 +M68KMAKE_OP(move, 8, di, .) 18.5564 +{ 18.5565 + uint res = M68KMAKE_GET_OPER_AY_8; 18.5566 + uint ea = EA_AX_DI_8(); 18.5567 + 18.5568 + m68ki_write_8(ea, res); 18.5569 + 18.5570 + FLAG_N = NFLAG_8(res); 18.5571 + FLAG_Z = res; 18.5572 + FLAG_V = VFLAG_CLEAR; 18.5573 + FLAG_C = CFLAG_CLEAR; 18.5574 +} 18.5575 + 18.5576 + 18.5577 +M68KMAKE_OP(move, 8, ix, d) 18.5578 +{ 18.5579 + uint res = MASK_OUT_ABOVE_8(DY); 18.5580 + uint ea = EA_AX_IX_8(); 18.5581 + 18.5582 + m68ki_write_8(ea, res); 18.5583 + 18.5584 + FLAG_N = NFLAG_8(res); 18.5585 + FLAG_Z = res; 18.5586 + FLAG_V = VFLAG_CLEAR; 18.5587 + FLAG_C = CFLAG_CLEAR; 18.5588 +} 18.5589 + 18.5590 + 18.5591 +M68KMAKE_OP(move, 8, ix, .) 18.5592 +{ 18.5593 + uint res = M68KMAKE_GET_OPER_AY_8; 18.5594 + uint ea = EA_AX_IX_8(); 18.5595 + 18.5596 + m68ki_write_8(ea, res); 18.5597 + 18.5598 + FLAG_N = NFLAG_8(res); 18.5599 + FLAG_Z = res; 18.5600 + FLAG_V = VFLAG_CLEAR; 18.5601 + FLAG_C = CFLAG_CLEAR; 18.5602 +} 18.5603 + 18.5604 + 18.5605 +M68KMAKE_OP(move, 8, aw, d) 18.5606 +{ 18.5607 + uint res = MASK_OUT_ABOVE_8(DY); 18.5608 + uint ea = EA_AW_8(); 18.5609 + 18.5610 + m68ki_write_8(ea, res); 18.5611 + 18.5612 + FLAG_N = NFLAG_8(res); 18.5613 + FLAG_Z = res; 18.5614 + FLAG_V = VFLAG_CLEAR; 18.5615 + FLAG_C = CFLAG_CLEAR; 18.5616 +} 18.5617 + 18.5618 + 18.5619 +M68KMAKE_OP(move, 8, aw, .) 18.5620 +{ 18.5621 + uint res = M68KMAKE_GET_OPER_AY_8; 18.5622 + uint ea = EA_AW_8(); 18.5623 + 18.5624 + m68ki_write_8(ea, res); 18.5625 + 18.5626 + FLAG_N = NFLAG_8(res); 18.5627 + FLAG_Z = res; 18.5628 + FLAG_V = VFLAG_CLEAR; 18.5629 + FLAG_C = CFLAG_CLEAR; 18.5630 +} 18.5631 + 18.5632 + 18.5633 +M68KMAKE_OP(move, 8, al, d) 18.5634 +{ 18.5635 + uint res = MASK_OUT_ABOVE_8(DY); 18.5636 + uint ea = EA_AL_8(); 18.5637 + 18.5638 + m68ki_write_8(ea, res); 18.5639 + 18.5640 + FLAG_N = NFLAG_8(res); 18.5641 + FLAG_Z = res; 18.5642 + FLAG_V = VFLAG_CLEAR; 18.5643 + FLAG_C = CFLAG_CLEAR; 18.5644 +} 18.5645 + 18.5646 + 18.5647 +M68KMAKE_OP(move, 8, al, .) 18.5648 +{ 18.5649 + uint res = M68KMAKE_GET_OPER_AY_8; 18.5650 + uint ea = EA_AL_8(); 18.5651 + 18.5652 + m68ki_write_8(ea, res); 18.5653 + 18.5654 + FLAG_N = NFLAG_8(res); 18.5655 + FLAG_Z = res; 18.5656 + FLAG_V = VFLAG_CLEAR; 18.5657 + FLAG_C = CFLAG_CLEAR; 18.5658 +} 18.5659 + 18.5660 + 18.5661 +M68KMAKE_OP(move, 16, d, d) 18.5662 +{ 18.5663 + uint res = MASK_OUT_ABOVE_16(DY); 18.5664 + uint* r_dst = &DX; 18.5665 + 18.5666 + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; 18.5667 + 18.5668 + FLAG_N = NFLAG_16(res); 18.5669 + FLAG_Z = res; 18.5670 + FLAG_V = VFLAG_CLEAR; 18.5671 + FLAG_C = CFLAG_CLEAR; 18.5672 +} 18.5673 + 18.5674 + 18.5675 +M68KMAKE_OP(move, 16, d, a) 18.5676 +{ 18.5677 + uint res = MASK_OUT_ABOVE_16(AY); 18.5678 + uint* r_dst = &DX; 18.5679 + 18.5680 + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; 18.5681 + 18.5682 + FLAG_N = NFLAG_16(res); 18.5683 + FLAG_Z = res; 18.5684 + FLAG_V = VFLAG_CLEAR; 18.5685 + FLAG_C = CFLAG_CLEAR; 18.5686 +} 18.5687 + 18.5688 + 18.5689 +M68KMAKE_OP(move, 16, d, .) 18.5690 +{ 18.5691 + uint res = M68KMAKE_GET_OPER_AY_16; 18.5692 + uint* r_dst = &DX; 18.5693 + 18.5694 + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; 18.5695 + 18.5696 + FLAG_N = NFLAG_16(res); 18.5697 + FLAG_Z = res; 18.5698 + FLAG_V = VFLAG_CLEAR; 18.5699 + FLAG_C = CFLAG_CLEAR; 18.5700 +} 18.5701 + 18.5702 + 18.5703 +M68KMAKE_OP(move, 16, ai, d) 18.5704 +{ 18.5705 + uint res = MASK_OUT_ABOVE_16(DY); 18.5706 + uint ea = EA_AX_AI_16(); 18.5707 + 18.5708 + m68ki_write_16(ea, res); 18.5709 + 18.5710 + FLAG_N = NFLAG_16(res); 18.5711 + FLAG_Z = res; 18.5712 + FLAG_V = VFLAG_CLEAR; 18.5713 + FLAG_C = CFLAG_CLEAR; 18.5714 +} 18.5715 + 18.5716 + 18.5717 +M68KMAKE_OP(move, 16, ai, a) 18.5718 +{ 18.5719 + uint res = MASK_OUT_ABOVE_16(AY); 18.5720 + uint ea = EA_AX_AI_16(); 18.5721 + 18.5722 + m68ki_write_16(ea, res); 18.5723 + 18.5724 + FLAG_N = NFLAG_16(res); 18.5725 + FLAG_Z = res; 18.5726 + FLAG_V = VFLAG_CLEAR; 18.5727 + FLAG_C = CFLAG_CLEAR; 18.5728 +} 18.5729 + 18.5730 + 18.5731 +M68KMAKE_OP(move, 16, ai, .) 18.5732 +{ 18.5733 + uint res = M68KMAKE_GET_OPER_AY_16; 18.5734 + uint ea = EA_AX_AI_16(); 18.5735 + 18.5736 + m68ki_write_16(ea, res); 18.5737 + 18.5738 + FLAG_N = NFLAG_16(res); 18.5739 + FLAG_Z = res; 18.5740 + FLAG_V = VFLAG_CLEAR; 18.5741 + FLAG_C = CFLAG_CLEAR; 18.5742 +} 18.5743 + 18.5744 + 18.5745 +M68KMAKE_OP(move, 16, pi, d) 18.5746 +{ 18.5747 + uint res = MASK_OUT_ABOVE_16(DY); 18.5748 + uint ea = EA_AX_PI_16(); 18.5749 + 18.5750 + m68ki_write_16(ea, res); 18.5751 + 18.5752 + FLAG_N = NFLAG_16(res); 18.5753 + FLAG_Z = res; 18.5754 + FLAG_V = VFLAG_CLEAR; 18.5755 + FLAG_C = CFLAG_CLEAR; 18.5756 +} 18.5757 + 18.5758 + 18.5759 +M68KMAKE_OP(move, 16, pi, a) 18.5760 +{ 18.5761 + uint res = MASK_OUT_ABOVE_16(AY); 18.5762 + uint ea = EA_AX_PI_16(); 18.5763 + 18.5764 + m68ki_write_16(ea, res); 18.5765 + 18.5766 + FLAG_N = NFLAG_16(res); 18.5767 + FLAG_Z = res; 18.5768 + FLAG_V = VFLAG_CLEAR; 18.5769 + FLAG_C = CFLAG_CLEAR; 18.5770 +} 18.5771 + 18.5772 + 18.5773 +M68KMAKE_OP(move, 16, pi, .) 18.5774 +{ 18.5775 + uint res = M68KMAKE_GET_OPER_AY_16; 18.5776 + uint ea = EA_AX_PI_16(); 18.5777 + 18.5778 + m68ki_write_16(ea, res); 18.5779 + 18.5780 + FLAG_N = NFLAG_16(res); 18.5781 + FLAG_Z = res; 18.5782 + FLAG_V = VFLAG_CLEAR; 18.5783 + FLAG_C = CFLAG_CLEAR; 18.5784 +} 18.5785 + 18.5786 + 18.5787 +M68KMAKE_OP(move, 16, pd, d) 18.5788 +{ 18.5789 + uint res = MASK_OUT_ABOVE_16(DY); 18.5790 + uint ea = EA_AX_PD_16(); 18.5791 + 18.5792 + m68ki_write_16(ea, res); 18.5793 + 18.5794 + FLAG_N = NFLAG_16(res); 18.5795 + FLAG_Z = res; 18.5796 + FLAG_V = VFLAG_CLEAR; 18.5797 + FLAG_C = CFLAG_CLEAR; 18.5798 +} 18.5799 + 18.5800 + 18.5801 +M68KMAKE_OP(move, 16, pd, a) 18.5802 +{ 18.5803 + uint res = MASK_OUT_ABOVE_16(AY); 18.5804 + uint ea = EA_AX_PD_16(); 18.5805 + 18.5806 + m68ki_write_16(ea, res); 18.5807 + 18.5808 + FLAG_N = NFLAG_16(res); 18.5809 + FLAG_Z = res; 18.5810 + FLAG_V = VFLAG_CLEAR; 18.5811 + FLAG_C = CFLAG_CLEAR; 18.5812 +} 18.5813 + 18.5814 + 18.5815 +M68KMAKE_OP(move, 16, pd, .) 18.5816 +{ 18.5817 + uint res = M68KMAKE_GET_OPER_AY_16; 18.5818 + uint ea = EA_AX_PD_16(); 18.5819 + 18.5820 + m68ki_write_16(ea, res); 18.5821 + 18.5822 + FLAG_N = NFLAG_16(res); 18.5823 + FLAG_Z = res; 18.5824 + FLAG_V = VFLAG_CLEAR; 18.5825 + FLAG_C = CFLAG_CLEAR; 18.5826 +} 18.5827 + 18.5828 + 18.5829 +M68KMAKE_OP(move, 16, di, d) 18.5830 +{ 18.5831 + uint res = MASK_OUT_ABOVE_16(DY); 18.5832 + uint ea = EA_AX_DI_16(); 18.5833 + 18.5834 + m68ki_write_16(ea, res); 18.5835 + 18.5836 + FLAG_N = NFLAG_16(res); 18.5837 + FLAG_Z = res; 18.5838 + FLAG_V = VFLAG_CLEAR; 18.5839 + FLAG_C = CFLAG_CLEAR; 18.5840 +} 18.5841 + 18.5842 + 18.5843 +M68KMAKE_OP(move, 16, di, a) 18.5844 +{ 18.5845 + uint res = MASK_OUT_ABOVE_16(AY); 18.5846 + uint ea = EA_AX_DI_16(); 18.5847 + 18.5848 + m68ki_write_16(ea, res); 18.5849 + 18.5850 + FLAG_N = NFLAG_16(res); 18.5851 + FLAG_Z = res; 18.5852 + FLAG_V = VFLAG_CLEAR; 18.5853 + FLAG_C = CFLAG_CLEAR; 18.5854 +} 18.5855 + 18.5856 + 18.5857 +M68KMAKE_OP(move, 16, di, .) 18.5858 +{ 18.5859 + uint res = M68KMAKE_GET_OPER_AY_16; 18.5860 + uint ea = EA_AX_DI_16(); 18.5861 + 18.5862 + m68ki_write_16(ea, res); 18.5863 + 18.5864 + FLAG_N = NFLAG_16(res); 18.5865 + FLAG_Z = res; 18.5866 + FLAG_V = VFLAG_CLEAR; 18.5867 + FLAG_C = CFLAG_CLEAR; 18.5868 +} 18.5869 + 18.5870 + 18.5871 +M68KMAKE_OP(move, 16, ix, d) 18.5872 +{ 18.5873 + uint res = MASK_OUT_ABOVE_16(DY); 18.5874 + uint ea = EA_AX_IX_16(); 18.5875 + 18.5876 + m68ki_write_16(ea, res); 18.5877 + 18.5878 + FLAG_N = NFLAG_16(res); 18.5879 + FLAG_Z = res; 18.5880 + FLAG_V = VFLAG_CLEAR; 18.5881 + FLAG_C = CFLAG_CLEAR; 18.5882 +} 18.5883 + 18.5884 + 18.5885 +M68KMAKE_OP(move, 16, ix, a) 18.5886 +{ 18.5887 + uint res = MASK_OUT_ABOVE_16(AY); 18.5888 + uint ea = EA_AX_IX_16(); 18.5889 + 18.5890 + m68ki_write_16(ea, res); 18.5891 + 18.5892 + FLAG_N = NFLAG_16(res); 18.5893 + FLAG_Z = res; 18.5894 + FLAG_V = VFLAG_CLEAR; 18.5895 + FLAG_C = CFLAG_CLEAR; 18.5896 +} 18.5897 + 18.5898 + 18.5899 +M68KMAKE_OP(move, 16, ix, .) 18.5900 +{ 18.5901 + uint res = M68KMAKE_GET_OPER_AY_16; 18.5902 + uint ea = EA_AX_IX_16(); 18.5903 + 18.5904 + m68ki_write_16(ea, res); 18.5905 + 18.5906 + FLAG_N = NFLAG_16(res); 18.5907 + FLAG_Z = res; 18.5908 + FLAG_V = VFLAG_CLEAR; 18.5909 + FLAG_C = CFLAG_CLEAR; 18.5910 +} 18.5911 + 18.5912 + 18.5913 +M68KMAKE_OP(move, 16, aw, d) 18.5914 +{ 18.5915 + uint res = MASK_OUT_ABOVE_16(DY); 18.5916 + uint ea = EA_AW_16(); 18.5917 + 18.5918 + m68ki_write_16(ea, res); 18.5919 + 18.5920 + FLAG_N = NFLAG_16(res); 18.5921 + FLAG_Z = res; 18.5922 + FLAG_V = VFLAG_CLEAR; 18.5923 + FLAG_C = CFLAG_CLEAR; 18.5924 +} 18.5925 + 18.5926 + 18.5927 +M68KMAKE_OP(move, 16, aw, a) 18.5928 +{ 18.5929 + uint res = MASK_OUT_ABOVE_16(AY); 18.5930 + uint ea = EA_AW_16(); 18.5931 + 18.5932 + m68ki_write_16(ea, res); 18.5933 + 18.5934 + FLAG_N = NFLAG_16(res); 18.5935 + FLAG_Z = res; 18.5936 + FLAG_V = VFLAG_CLEAR;