3b1emu / file diff

     1.1 --- a/src/main.c	Wed Jan 16 00:41:51 2013 +0000
     1.2 +++ b/src/main.c	Fri Jan 18 17:03:48 2013 +0000
     1.3 @@ -291,49 +291,50 @@
     1.4  				}else{
     1.5  					printf("ERROR: DMA attempt with no drive selected!\n");
     1.6  				}
     1.7 -				if (!access_check_dma(state.dma_reading)) {
     1.8 -					break;
     1.9 -				}
    1.10 -				uint32_t newAddr;
    1.11 -				// Map logical address to a physical RAM address
    1.12 -				newAddr = mapAddr(state.dma_address, !state.dma_reading);
    1.13 +
    1.14 +				if (access_check_dma()) {
    1.15 +
    1.16 +					uint32_t newAddr;
    1.17 +					// Map logical address to a physical RAM address
    1.18 +					newAddr = MAP_ADDR(state.dma_address);
    1.19  
    1.20 -				if (!state.dma_reading) {
    1.21 -					// Data available. Get it from the FDC or HDC.
    1.22 -					if (state.fd_selected) {
    1.23 -						d = wd2797_read_reg(&state.fdc_ctx, WD2797_REG_DATA);
    1.24 -						d <<= 8;
    1.25 -						d += wd2797_read_reg(&state.fdc_ctx, WD2797_REG_DATA);
    1.26 -					}else if (state.hd_selected) {
    1.27 -						d = wd2010_read_data(&state.hdc_ctx);
    1.28 -						d <<= 8;
    1.29 -						d += wd2010_read_data(&state.hdc_ctx);
    1.30 -					}
    1.31 -					if (newAddr <= 0x1FFFFF) {
    1.32 -						WR16(state.base_ram, newAddr, state.base_ram_size - 1, d);
    1.33 -					} else if (newAddr >= 0x200000) {
    1.34 -						WR16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, d);
    1.35 -					}
    1.36 -				} else {
    1.37 -					// Data write to FDC or HDC.
    1.38 +					if (!state.dma_reading) {
    1.39 +						// Data available. Get it from the FDC or HDC.
    1.40 +						if (state.fd_selected) {
    1.41 +							d = wd2797_read_reg(&state.fdc_ctx, WD2797_REG_DATA);
    1.42 +							d <<= 8;
    1.43 +							d += wd2797_read_reg(&state.fdc_ctx, WD2797_REG_DATA);
    1.44 +						}else if (state.hd_selected) {
    1.45 +							d = wd2010_read_data(&state.hdc_ctx);
    1.46 +							d <<= 8;
    1.47 +							d += wd2010_read_data(&state.hdc_ctx);
    1.48 +						}
    1.49 +						if (newAddr <= 0x1FFFFF) {
    1.50 +							WR16(state.base_ram, newAddr, state.base_ram_size - 1, d);
    1.51 +						} else if (newAddr >= 0x200000) {
    1.52 +							WR16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, d);
    1.53 +						}
    1.54 +					} else {
    1.55 +						// Data write to FDC or HDC.
    1.56  
    1.57 -					// Get the data from RAM
    1.58 -					if (newAddr <= 0x1fffff) {
    1.59 -						d = RD16(state.base_ram, newAddr, state.base_ram_size - 1);
    1.60 -					} else {
    1.61 -						if (newAddr <= (state.exp_ram_size + 0x200000 - 1))
    1.62 -							d = RD16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
    1.63 -						else
    1.64 -							d = 0xffff;
    1.65 -					}
    1.66 +						// Get the data from RAM
    1.67 +						if (newAddr <= 0x1fffff) {
    1.68 +							d = RD16(state.base_ram, newAddr, state.base_ram_size - 1);
    1.69 +						} else {
    1.70 +							if (newAddr <= (state.exp_ram_size + 0x200000 - 1))
    1.71 +								d = RD16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
    1.72 +							else
    1.73 +								d = 0xffff;
    1.74 +						}
    1.75  
    1.76 -					// Send the data to the FDD or HDD
    1.77 -					if (state.fd_selected){
    1.78 -						wd2797_write_reg(&state.fdc_ctx, WD2797_REG_DATA, (d >> 8));
    1.79 -						wd2797_write_reg(&state.fdc_ctx, WD2797_REG_DATA, (d & 0xff));
    1.80 -					}else if (state.hd_selected){
    1.81 -						wd2010_write_data(&state.hdc_ctx, (d >> 8));
    1.82 -						wd2010_write_data(&state.hdc_ctx, (d & 0xff));
    1.83 +						// Send the data to the FDD or HDD
    1.84 +						if (state.fd_selected){
    1.85 +							wd2797_write_reg(&state.fdc_ctx, WD2797_REG_DATA, (d >> 8));
    1.86 +							wd2797_write_reg(&state.fdc_ctx, WD2797_REG_DATA, (d & 0xff));
    1.87 +						}else if (state.hd_selected){
    1.88 +							wd2010_write_data(&state.hdc_ctx, (d >> 8));
    1.89 +							wd2010_write_data(&state.hdc_ctx, (d & 0xff));
    1.90 +						}
    1.91  					}
    1.92  				}
    1.93