3b1emu / file diff

diff: src/main.c

src/main.c

changeset 78
c149c13aff1c
parent 69
afe655559cc0
parent 76
2ef98ea1e944
child 79
674226015c8a
     1.1 --- a/src/main.c	Wed Dec 29 01:38:54 2010 +0000
     1.2 +++ b/src/main.c	Wed Dec 29 09:04:43 2010 +0000
     1.3 @@ -204,12 +204,13 @@
     1.4  	 * The 3B1 CPU runs at 10MHz, with DMA running at 1MHz and video refreshing at
     1.5  	 * around 60Hz (???), with a 60Hz periodic interrupt.
     1.6  	 */
     1.7 -	const uint32_t TIMESLOT_FREQUENCY = 240;	// Hz
     1.8 +	const uint32_t TIMESLOT_FREQUENCY = 1000;//240;	// Hz
     1.9  	const uint32_t MILLISECS_PER_TIMESLOT = 1e3 / TIMESLOT_FREQUENCY;
    1.10  	const uint32_t CLOCKS_PER_60HZ = (10e6 / 60);
    1.11  	uint32_t next_timeslot = SDL_GetTicks() + MILLISECS_PER_TIMESLOT;
    1.12  	uint32_t clock_cycles = 0;
    1.13  	bool exitEmu = false;
    1.14 +	bool lastirq_fdc = false;
    1.15  	for (;;) {
    1.16  		// Run the CPU for however many cycles we need to. CPU core clock is
    1.17  		// 10MHz, and we're running at 240Hz/timeslot. Thus: 10e6/240 or
    1.18 @@ -217,8 +218,7 @@
    1.19  		clock_cycles += m68k_execute(10e6/TIMESLOT_FREQUENCY);
    1.20  
    1.21  		// Run the DMA engine
    1.22 -		//
    1.23 -		if (state.dmaen) { //((state.dma_count < 0x3fff) && state.dmaen) {
    1.24 +		if (state.dmaen) {
    1.25  			// DMA ready to go -- so do it.
    1.26  			size_t num = 0;
    1.27  			while (state.dma_count < 0x4000) {
    1.28 @@ -325,8 +325,13 @@
    1.29  		}
    1.30  
    1.31  		// Any interrupts? --> TODO: masking
    1.32 -/*		if (wd2797_get_irq(&state.fdc_ctx)) {
    1.33 -			m68k_set_irq(2);
    1.34 +/*		if (!lastirq_fdc) {
    1.35 +			if (wd2797_get_irq(&state.fdc_ctx)) {
    1.36 +				lastirq_fdc = true;
    1.37 +				m68k_set_irq(2);
    1.38 +			} else {
    1.39 +				lastirq_fdc = false;
    1.40 +			}
    1.41  		} else {
    1.42  			m68k_set_irq(0);
    1.43  		}