1.1 diff -r 51cbc7a44cd9 -r c149c13aff1c src/main.c 1.2 --- a/src/main.c Wed Dec 29 01:38:54 2010 +0000 1.3 +++ b/src/main.c Wed Dec 29 09:04:43 2010 +0000 1.4 @@ -204,12 +204,13 @@ 1.5 * The 3B1 CPU runs at 10MHz, with DMA running at 1MHz and video refreshing at 1.6 * around 60Hz (???), with a 60Hz periodic interrupt. 1.7 */ 1.8 - const uint32_t TIMESLOT_FREQUENCY = 240; // Hz 1.9 + const uint32_t TIMESLOT_FREQUENCY = 1000;//240; // Hz 1.10 const uint32_t MILLISECS_PER_TIMESLOT = 1e3 / TIMESLOT_FREQUENCY; 1.11 const uint32_t CLOCKS_PER_60HZ = (10e6 / 60); 1.12 uint32_t next_timeslot = SDL_GetTicks() + MILLISECS_PER_TIMESLOT; 1.13 uint32_t clock_cycles = 0; 1.14 bool exitEmu = false; 1.15 + bool lastirq_fdc = false; 1.16 for (;;) { 1.17 // Run the CPU for however many cycles we need to. CPU core clock is 1.18 // 10MHz, and we're running at 240Hz/timeslot. Thus: 10e6/240 or 1.19 @@ -217,8 +218,7 @@ 1.20 clock_cycles += m68k_execute(10e6/TIMESLOT_FREQUENCY); 1.21 1.22 // Run the DMA engine 1.23 - // 1.24 - if (state.dmaen) { //((state.dma_count < 0x3fff) && state.dmaen) { 1.25 + if (state.dmaen) { 1.26 // DMA ready to go -- so do it. 1.27 size_t num = 0; 1.28 while (state.dma_count < 0x4000) { 1.29 @@ -325,8 +325,13 @@ 1.30 } 1.31 1.32 // Any interrupts? --> TODO: masking 1.33 -/* if (wd2797_get_irq(&state.fdc_ctx)) { 1.34 - m68k_set_irq(2); 1.35 +/* if (!lastirq_fdc) { 1.36 + if (wd2797_get_irq(&state.fdc_ctx)) { 1.37 + lastirq_fdc = true; 1.38 + m68k_set_irq(2); 1.39 + } else { 1.40 + lastirq_fdc = false; 1.41 + } 1.42 } else { 1.43 m68k_set_irq(0); 1.44 }