1.1 diff -r e2dcbabc7e1c -r 3e99497dca33 src/main.c 1.2 --- a/src/main.c Sun Nov 28 20:02:45 2010 +0000 1.3 +++ b/src/main.c Sun Nov 28 20:52:53 2010 +0000 1.4 @@ -7,7 +7,7 @@ 1.5 #include "musashi/m68k.h" 1.6 #include "version.h" 1.7 1.8 -#define ROM_SIZE (32768/4) 1.9 +#define ROM_SIZE (32768/2) 1.10 1.11 void state_done(void); 1.12 1.13 @@ -21,10 +21,10 @@ 1.14 1.15 struct { 1.16 // Boot PROM can be up to 32Kbytes total size 1.17 - uint32_t rom[ROM_SIZE]; 1.18 + uint16_t rom[ROM_SIZE]; 1.19 1.20 // Main system RAM 1.21 - uint32_t *ram; 1.22 + uint16_t *ram; 1.23 size_t ram_size; // number of RAM bytes allocated 1.24 uint32_t ram_addr_mask; // address mask 1.25 1.26 @@ -74,12 +74,8 @@ 1.27 fread(romdat2, 1, romlen2, r14c); 1.28 1.29 // convert the ROM data 1.30 - for (size_t i=0; i<romlen; i+=2) { 1.31 - state.rom[i/2] = ( 1.32 - (romdat1[i+0] << 24) | 1.33 - (romdat2[i+0] << 16) | 1.34 - (romdat1[i+1] << 8) | 1.35 - (romdat2[i+1])); 1.36 + for (size_t i=0; i<romlen; i++) { 1.37 + state.rom[i] = ((romdat1[i] << 8) | (romdat2[i])); 1.38 } 1.39 1.40 // free the data arrays and close the files 1.41 @@ -102,48 +98,56 @@ 1.42 // TODO: find a way to make musashi use function pointers instead of hard coded callbacks, maybe use a context struct too 1.43 uint32_t m68k_read_memory_32(uint32_t address) 1.44 { 1.45 + uint32_t data = 0xFFFFFFFF; 1.46 + 1.47 + printf("RD32 %08X %d", address, state.romlmap); 1.48 + 1.49 // If ROMLMAP is set, force system to access ROM 1.50 if (!state.romlmap) 1.51 address |= 0x800000; 1.52 1.53 - if (address >= 0xC00000) { 1.54 - // I/O Registers B 1.55 - // TODO 1.56 - } else if ((address >= 0x800000) && (address <= 0xBFFFFF)) { 1.57 + if ((address >= 0x800000) && (address <= 0xBFFFFF)) { 1.58 // ROM access 1.59 - return state.rom[(address & (ROM_SIZE-1)) / 4]; 1.60 - } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) { 1.61 - // I/O Registers A 1.62 - // TODO 1.63 + data = ((state.rom[(address & (ROM_SIZE-1)) / 2] << 16) | (state.rom[((address & (ROM_SIZE-1)) / 2)+1])); 1.64 } else if (address <= 0x3FFFFF) { 1.65 // RAM 1.66 - return state.ram[(address & state.ram_addr_mask) / 4]; 1.67 + data = state.ram[(address & state.ram_addr_mask) / 2]; 1.68 } 1.69 - return 0xffffffff; 1.70 + 1.71 + printf(" ==> %04X\n", data); 1.72 + return data; 1.73 } 1.74 1.75 uint32_t m68k_read_memory_16(uint32_t address) 1.76 { 1.77 - if (address & 2) { 1.78 - return m68k_read_memory_32(address) & 0xFFFF; 1.79 - } else { 1.80 - return (m68k_read_memory_32(address) >> 16) & 0xFFFF; 1.81 - } 1.82 + uint16_t data = 0xFFFF; 1.83 + 1.84 + printf("RD16 %08X %d", address, state.romlmap); 1.85 + 1.86 + // If ROMLMAP is set, force system to access ROM 1.87 + if (!state.romlmap) 1.88 + address |= 0x800000; 1.89 + 1.90 + data = (m68k_read_memory_32(address) >> 16) & 0xFFFF; 1.91 + 1.92 + printf(" ==> %04X\n", data); 1.93 + return data; 1.94 } 1.95 1.96 uint32_t m68k_read_memory_8(uint32_t address) 1.97 { 1.98 + uint8_t data = 0xFF; 1.99 + 1.100 + printf("RD 8 %08X %d ", address, state.romlmap); 1.101 + 1.102 // If ROMLMAP is set, force system to access ROM 1.103 if (!state.romlmap) 1.104 address |= 0x800000; 1.105 1.106 - switch (address & 3) { 1.107 - case 3: return m68k_read_memory_32(address) & 0xFF; 1.108 - case 2: return (m68k_read_memory_32(address) >> 8) & 0xFF; 1.109 - case 1: return (m68k_read_memory_32(address) >> 16) & 0xFF; 1.110 - case 0: return (m68k_read_memory_32(address) >> 24) & 0xFF; 1.111 - } 1.112 - return 0xffffffff; 1.113 + data = m68k_read_memory_32(address) & 0xFF; 1.114 + 1.115 + printf("==> %02X\n", data); 1.116 + return data; 1.117 } 1.118 1.119 // write m68k memory 1.120 @@ -153,18 +157,19 @@ 1.121 if (!state.romlmap) 1.122 address |= 0x800000; 1.123 1.124 - if (address >= 0xC00000) { 1.125 - // I/O Registers B 1.126 - // TODO 1.127 - } else if ((address >= 0x800000) && (address <= 0xBFFFFF)) { 1.128 + printf("WR32 %08X %d %02X\n", address, state.romlmap, value); 1.129 + 1.130 + if ((address >= 0x800000) && (address <= 0xBFFFFF)) { 1.131 // ROM access 1.132 // TODO: bus error here? can't write to rom! 1.133 - } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) { 1.134 - // I/O Registers A 1.135 - // TODO 1.136 } else if (address <= 0x3FFFFF) { 1.137 // RAM 1.138 - state.ram[(address & state.ram_addr_mask) / 4] = value; 1.139 + state.ram[(address & state.ram_addr_mask) / 2] = (value >> 16); 1.140 + state.ram[((address & state.ram_addr_mask) / 2)+1] = value & 0xffff; 1.141 + } else { 1.142 + switch (address) { 1.143 + case 0xE43000: state.romlmap = ((value & 0x8000) == 0x8000); 1.144 + } 1.145 } 1.146 } 1.147 1.148 @@ -174,21 +179,18 @@ 1.149 if (!state.romlmap) 1.150 address |= 0x800000; 1.151 1.152 - if (address >= 0xC00000) { 1.153 - // I/O Registers B 1.154 - // TODO 1.155 - } else if ((address >= 0x800000) && (address <= 0xBFFFFF)) { 1.156 + printf("WR16 %08X %d %02X\n", address, state.romlmap, value); 1.157 + 1.158 + if ((address >= 0x800000) && (address <= 0xBFFFFF)) { 1.159 // ROM access 1.160 // TODO: bus error here? can't write to rom! 1.161 - } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) { 1.162 - // I/O Registers A 1.163 - // TODO 1.164 } else if (address <= 0x3FFFFF) { 1.165 // RAM 1.166 - if (address & 2) 1.167 - state.ram[(address & state.ram_addr_mask) / 4] = (state.ram[(address & state.ram_addr_mask) / 4] & 0xFFFF0000) | (value & 0xFFFF); 1.168 - else 1.169 - state.ram[(address & state.ram_addr_mask) / 4] = (state.ram[(address & state.ram_addr_mask) / 4] & 0x0000FFFF) | ((value & 0xFFFF) << 16); 1.170 + state.ram[(address & state.ram_addr_mask) / 2] = value & 0xFFFF; 1.171 + } else { 1.172 + switch (address) { 1.173 + case 0xE43000: state.romlmap = ((value & 0x8000) == 0x8000); 1.174 + } 1.175 } 1.176 } 1.177 1.178 @@ -198,26 +200,31 @@ 1.179 if (!state.romlmap) 1.180 address |= 0x800000; 1.181 1.182 - if (address >= 0xC00000) { 1.183 - // I/O Registers B 1.184 - // TODO 1.185 - } else if ((address >= 0x800000) && (address <= 0xBFFFFF)) { 1.186 + printf("WR 8 %08X %d %02X\n", address, state.romlmap, value); 1.187 + 1.188 + if ((address >= 0x800000) && (address <= 0xBFFFFF)) { 1.189 // ROM access 1.190 // TODO: bus error here? can't write to rom! 1.191 - } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) { 1.192 - // I/O Registers A 1.193 - // TODO 1.194 } else if (address <= 0x3FFFFF) { 1.195 // RAM 1.196 switch (address & 3) { 1.197 + // FIXME 1.198 case 3: state.ram[(address & state.ram_addr_mask) / 4] = (state.ram[(address & state.ram_addr_mask) / 4] & 0xFFFFFF00) | (value & 0xFF); 1.199 case 2: state.ram[(address & state.ram_addr_mask) / 4] = (state.ram[(address & state.ram_addr_mask) / 4] & 0xFFFF00FF) | ((value & 0xFF) << 8); 1.200 case 1: state.ram[(address & state.ram_addr_mask) / 4] = (state.ram[(address & state.ram_addr_mask) / 4] & 0xFF00FFFF) | ((value & 0xFF) << 16); 1.201 case 0: state.ram[(address & state.ram_addr_mask) / 4] = (state.ram[(address & state.ram_addr_mask) / 4] & 0x00FFFFFF) | ((value & 0xFF) << 24); 1.202 } 1.203 + } else { 1.204 + switch (address) { 1.205 + case 0xE43000: state.romlmap = ((value & 0x80) == 0x80); 1.206 + } 1.207 } 1.208 } 1.209 1.210 +uint32_t m68k_read_disassembler_32(uint32_t addr) { return m68k_read_memory_32(addr); } 1.211 +uint32_t m68k_read_disassembler_16(uint32_t addr) { return m68k_read_memory_16(addr); } 1.212 +uint32_t m68k_read_disassembler_8 (uint32_t addr) { return m68k_read_memory_8 (addr); } 1.213 + 1.214 int main(void) 1.215 { 1.216 // copyright banner 1.217 @@ -234,6 +241,10 @@ 1.218 m68k_set_cpu_type(M68K_CPU_TYPE_68010); 1.219 m68k_pulse_reset(); 1.220 1.221 + char dasm[512]; 1.222 + m68k_disassemble(dasm, 0x80001a, M68K_CPU_TYPE_68010); 1.223 + printf("%s\n", dasm); 1.224 + 1.225 // set up SDL 1.226 1.227 // emulation loop!