3b1emu: diff src/memory.c

     1.1 diff -r 0fa6f5a480a6 -r 609707511166 src/memory.c
     1.2 --- a/src/memory.c	Fri Apr 12 12:37:34 2013 +0100
     1.3 +++ b/src/memory.c	Fri Apr 12 16:26:25 2013 +0100
     1.4 @@ -88,7 +88,7 @@
     1.5  //		if (!(MAP_PAGEBITS(addr) & PAGE_BIT_PS0)) {
     1.6  			// FIXME FUCKUP The ruddy TRM is wrong AGAIN! If above line is uncommented, Really Bad Things Happen.
     1.7  		if ((MAP_PAGEBITS(addr) & PAGE_BIT_PS0)) {
     1.8 -			// Level 7 interrupt, PS0 clear, PS1 don't-care. Set PS0.
     1.9 +			// Level 7 interrupt, PS0 set, PS1 don't-care. Set PS0.
    1.10  			ps0_state = true;
    1.11  		}
    1.12  	} else {
    1.13 @@ -123,22 +123,16 @@
    1.14  	exit(-1);
    1.15  #endif
    1.16  
    1.17 -#ifdef MAPRAM_DEBUG_MESSAGES
    1.18 -	uint16_t old_pagebits = MAP_PAGEBITS(addr);
    1.19 -#endif
    1.20 -
    1.21 -	// PS1 is always set on access
    1.22 -	MAP_SET_PAGEBIT(addr, PAGE_BIT_PS1);
    1.23 +	if (!l7intr) {
    1.24 +		// PS1 is always set on access if no fault
    1.25 +		MAP_SET_PAGEBIT(addr, PAGE_BIT_PS1);
    1.26  
    1.27 -#ifdef MAPRAM_DEBUG_MESSAGES
    1.28 -	uint16_t new_pagebit1 = MAP_PAGEBITS(addr);
    1.29 -#endif
    1.30 -
    1.31 -	// Update PS0
    1.32 -	if (ps0_state) {
    1.33 -		MAP_SET_PAGEBIT(addr, PAGE_BIT_PS0);
    1.34 -	} else {
    1.35 -		MAP_CLR_PAGEBIT(addr, PAGE_BIT_PS0);
    1.36 +		// Update PS0
    1.37 +		if (ps0_state) {
    1.38 +			MAP_SET_PAGEBIT(addr, PAGE_BIT_PS0);
    1.39 +		} else {
    1.40 +			MAP_CLR_PAGEBIT(addr, PAGE_BIT_PS0);
    1.41 +		}
    1.42  	}
    1.43  
    1.44  #ifdef MAPRAM_DEBUG_MESSAGES
    1.45 @@ -259,6 +253,8 @@
    1.46  		fault = true;
    1.47  	}
    1.48  
    1.49 +	unsigned char pagebits_preup = MAP_PAGEBITS(addr & 0x3fffff);
    1.50 +
    1.51  	// Update the page bits first
    1.52  	update_page_bits(addr, fault, write);
    1.53  
    1.54 @@ -271,9 +267,10 @@
    1.55  		state.bsr0 |= (addr >> 16);
    1.56  		state.bsr1 = addr & 0xffff;
    1.57  
    1.58 -		LOG("CPU Bus Error or L7Intr while %s, vaddr %08X, map %08X, pagebits 0x%02X bsr0=%04X bsr1=%04X genstat=%04X", 
    1.59 +		LOG("CPU Bus Error or L7Intr while %s, vaddr %08X, map %08X, pagebits 0x%02X=>0x%02X bsr0=%04X bsr1=%04X genstat=%04X", 
    1.60  				write ? "writing" : "reading", addr,
    1.61  				MAPRAM_ADDR(addr & 0x3fffff),
    1.62 +				pagebits_preup,
    1.63  				MAP_PAGEBITS(addr & 0x3fffff),
    1.64  				state.bsr0, state.bsr1, state.genstat);
    1.65
3b1emu / file diff

diff: src/memory.c

src/memory.c
