1.1 diff -r fef12817c5e8 -r ceae676021ca src/main.c 1.2 --- a/src/main.c Wed Dec 01 22:34:15 2010 +0000 1.3 +++ b/src/main.c Wed Dec 01 22:43:52 2010 +0000 1.4 @@ -62,7 +62,6 @@ 1.5 * m68k memory read/write support functions for Musashi 1.6 ********************************************************/ 1.7 1.8 - 1.9 // read m68k memory 1.10 uint32_t m68k_read_memory_32(uint32_t address) 1.11 { 1.12 @@ -76,11 +75,14 @@ 1.13 // ROM access 1.14 data = RD32(state.rom, address, ROM_SIZE - 1); 1.15 } else if (address <= (state.ram_size - 1)) { 1.16 - // RAM 1.17 + // RAM access -- TODO: mapping 1.18 data = RD32(state.ram, address, state.ram_size - 1); 1.19 } else if ((address >= 0x420000) && (address <= 0x427FFF)) { 1.20 - // VRAM 1.21 + // VRAM access 1.22 data = RD32(state.vram, address, 0x7FFF); 1.23 + } else if ((address >= 0x400000) && (address <= 0x4007FF)) { 1.24 + // Map RAM access 1.25 + data = RD32(state.map, address, 0x7FF); 1.26 } else { 1.27 // I/O register -- TODO 1.28 printf("RD32 0x%08X [unknown I/O register]\n", address); 1.29 @@ -100,11 +102,14 @@ 1.30 // ROM access 1.31 data = RD16(state.rom, address, ROM_SIZE - 1); 1.32 } else if (address <= (state.ram_size - 1)) { 1.33 - // RAM 1.34 + // RAM access -- TODO: mapping 1.35 data = RD16(state.ram, address, state.ram_size - 1); 1.36 } else if ((address >= 0x420000) && (address <= 0x427FFF)) { 1.37 - // VRAM 1.38 + // VRAM access 1.39 data = RD16(state.vram, address, 0x7FFF); 1.40 + } else if ((address >= 0x400000) && (address <= 0x4007FF)) { 1.41 + // Map RAM access 1.42 + data = RD16(state.map, address, 0x7FF); 1.43 } else { 1.44 // I/O register -- TODO 1.45 printf("RD16 0x%08X [unknown I/O register]\n", address); 1.46 @@ -125,11 +130,14 @@ 1.47 // ROM access 1.48 data = RD8(state.rom, address, ROM_SIZE - 1); 1.49 } else if (address <= (state.ram_size - 1)) { 1.50 - // RAM 1.51 + // RAM access -- TODO: mapping 1.52 data = RD8(state.ram, address, state.ram_size - 1); 1.53 } else if ((address >= 0x420000) && (address <= 0x427FFF)) { 1.54 - // VRAM 1.55 + // VRAM access 1.56 data = RD8(state.vram, address, 0x7FFF); 1.57 + } else if ((address >= 0x400000) && (address <= 0x4007FF)) { 1.58 + // Map RAM access 1.59 + data = RD8(state.map, address, 0x7FF); 1.60 } else { 1.61 // I/O register -- TODO 1.62 printf("RD08 0x%08X [unknown I/O register]\n", address); 1.63 @@ -149,11 +157,14 @@ 1.64 // ROM access 1.65 // TODO: bus error here? can't write to rom! 1.66 } else if (address <= (state.ram_size - 1)) { 1.67 - // RAM access 1.68 + // RAM -- TODO: mapping 1.69 WR32(state.ram, address, state.ram_size - 1, value); 1.70 } else if ((address >= 0x420000) && (address <= 0x427FFF)) { 1.71 // VRAM access 1.72 WR32(state.vram, address, 0x7fff, value); 1.73 + } else if ((address >= 0x400000) && (address <= 0x4007FF)) { 1.74 + // Map RAM access 1.75 + WR32(state.map, address, 0x7FF, value); 1.76 } else { 1.77 switch (address) { 1.78 case 0xE43000: state.romlmap = ((value & 0x8000) == 0x8000); break; // GCR3: ROMLMAP 1.79 @@ -172,11 +183,14 @@ 1.80 // ROM access 1.81 // TODO: bus error here? can't write to rom! 1.82 } else if (address <= (state.ram_size - 1)) { 1.83 - // RAM access 1.84 + // RAM access -- TODO: mapping 1.85 WR16(state.ram, address, state.ram_size - 1, value); 1.86 } else if ((address >= 0x420000) && (address <= 0x427FFF)) { 1.87 // VRAM access 1.88 WR16(state.vram, address, 0x7fff, value); 1.89 + } else if ((address >= 0x400000) && (address <= 0x4007FF)) { 1.90 + // Map RAM access 1.91 + WR16(state.map, address, 0x7FF, value); 1.92 } else { 1.93 switch (address) { 1.94 case 0xE43000: state.romlmap = ((value & 0x8000) == 0x8000); break; // GCR3: ROMLMAP 1.95 @@ -203,11 +217,14 @@ 1.96 // ROM access 1.97 // TODO: bus error here? can't write to rom! 1.98 } else if (address <= (state.ram_size - 1)) { 1.99 - // RAM access 1.100 + // RAM access -- TODO: mapping 1.101 WR8(state.ram, address, state.ram_size - 1, value); 1.102 } else if ((address >= 0x420000) && (address <= 0x427FFF)) { 1.103 // VRAM access 1.104 WR8(state.vram, address, 0x7fff, value); 1.105 + } else if ((address >= 0x400000) && (address <= 0x4007FF)) { 1.106 + // Map RAM access 1.107 + WR8(state.map, address, 0x7FF, value); 1.108 } else { 1.109 switch (address) { 1.110 case 0xE43000: state.romlmap = ((value & 0x80) == 0x80); break; // GCR3: ROMLMAP 1.111 @@ -221,6 +238,11 @@ 1.112 uint32_t m68k_read_disassembler_16(uint32_t addr) { return m68k_read_memory_16(addr); } 1.113 uint32_t m68k_read_disassembler_8 (uint32_t addr) { return m68k_read_memory_8 (addr); } 1.114 1.115 + 1.116 +/**************************** 1.117 + * blessed be thy main()... 1.118 + ****************************/ 1.119 + 1.120 int main(void) 1.121 { 1.122 // copyright banner