1.1 diff -r c895256b528d -r f772d3c40531 src/memory.c 1.2 --- a/src/memory.c Tue Dec 28 17:31:28 2010 +0000 1.3 +++ b/src/memory.c Tue Dec 28 17:47:01 2010 +0000 1.4 @@ -561,11 +561,14 @@ 1.5 } else if (address <= 0x3fffff) { 1.6 // RAM access 1.7 uint32_t newAddr = mapAddr(address, false); 1.8 - if (newAddr <= 0x1fffff) 1.9 + if (newAddr <= 0x1fffff) { 1.10 return RD32(state.base_ram, newAddr, state.base_ram_size - 1); 1.11 - else 1.12 - return 0xFFFFFFFF; 1.13 - // TODO: expansion RAM 1.14 + } else { 1.15 + if (newAddr <= (state.exp_ram_size + 0x200000 - 1)) 1.16 + return RD32(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1); 1.17 + else 1.18 + return 0xffffffff; 1.19 + } 1.20 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) { 1.21 // I/O register space, zone A 1.22 switch (address & 0x0F0000) { 1.23 @@ -607,11 +610,14 @@ 1.24 } else if (address <= 0x3fffff) { 1.25 // RAM access 1.26 uint32_t newAddr = mapAddr(address, false); 1.27 - if (newAddr <= 0x1fffff) 1.28 + if (newAddr <= 0x1fffff) { 1.29 return RD16(state.base_ram, newAddr, state.base_ram_size - 1); 1.30 - else 1.31 - return 0xFFFF; 1.32 - // TODO: expansion RAM 1.33 + } else { 1.34 + if (newAddr <= (state.exp_ram_size + 0x200000 - 1)) 1.35 + return RD16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1); 1.36 + else 1.37 + return 0xffff; 1.38 + } 1.39 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) { 1.40 // I/O register space, zone A 1.41 switch (address & 0x0F0000) { 1.42 @@ -653,11 +659,14 @@ 1.43 } else if (address <= 0x3fffff) { 1.44 // RAM access 1.45 uint32_t newAddr = mapAddr(address, false); 1.46 - if (newAddr <= 0x1fffff) 1.47 + if (newAddr <= 0x1fffff) { 1.48 return RD8(state.base_ram, newAddr, state.base_ram_size - 1); 1.49 - else 1.50 - return 0xFFFFFFFF; 1.51 - // TODO: expansion RAM 1.52 + } else { 1.53 + if (newAddr <= (state.exp_ram_size + 0x200000 - 1)) 1.54 + return RD8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1); 1.55 + else 1.56 + return 0xff; 1.57 + } 1.58 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) { 1.59 // I/O register space, zone A 1.60 switch (address & 0x0F0000) { 1.61 @@ -696,9 +705,11 @@ 1.62 } else if (address <= 0x3FFFFF) { 1.63 // RAM access 1.64 uint32_t newAddr = mapAddr(address, true); 1.65 - if (newAddr <= 0x1fffff) 1.66 + if (newAddr <= 0x1fffff) { 1.67 WR32(state.base_ram, newAddr, state.base_ram_size - 1, value); 1.68 - // TODO: expansion ram 1.69 + } else { 1.70 +// WR32(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value); 1.71 + } 1.72 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) { 1.73 // I/O register space, zone A 1.74 switch (address & 0x0F0000) { 1.75 @@ -735,9 +746,11 @@ 1.76 } else if (address <= 0x3FFFFF) { 1.77 // RAM access 1.78 uint32_t newAddr = mapAddr(address, true); 1.79 - if (newAddr <= 0x1fffff) 1.80 + if (newAddr <= 0x1fffff) { 1.81 WR16(state.base_ram, newAddr, state.base_ram_size - 1, value); 1.82 - // TODO: expansion ram 1.83 + } else { 1.84 +// WR16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value); 1.85 + } 1.86 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) { 1.87 // I/O register space, zone A 1.88 switch (address & 0x0F0000) { 1.89 @@ -774,9 +787,11 @@ 1.90 } else if (address <= 0x3FFFFF) { 1.91 // RAM access 1.92 uint32_t newAddr = mapAddr(address, true); 1.93 - if (newAddr <= 0x1fffff) 1.94 + if (newAddr <= 0x1fffff) { 1.95 WR8(state.base_ram, newAddr, state.base_ram_size - 1, value); 1.96 - // TODO: expansion ram 1.97 + } else { 1.98 +// WR8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value); 1.99 + } 1.100 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) { 1.101 // I/O register space, zone A 1.102 switch (address & 0x0F0000) {