src/memory.c

changeset 136
f7d78dfb45d0
parent 129
8b24770dea79
child 139
d91346487fe9
     1.1 diff -r b826697f411a -r f7d78dfb45d0 src/memory.c
     1.2 --- a/src/memory.c	Wed Mar 13 00:43:25 2013 +0000
     1.3 +++ b/src/memory.c	Thu Apr 11 09:18:31 2013 +0100
     1.4 @@ -215,10 +215,10 @@
     1.5  			state.bsr1 = address & 0xffff;							\
     1.6  			LOG("Bus Error while reading, addr %08X, statcode %d", address, st);		\
     1.7  			if (state.ee) m68k_pulse_bus_error();					\
     1.8 -			if (bits == 32)											\
     1.9 +			if (bits >= 32)											\
    1.10  				return EMPTY & 0xFFFFFFFF;									\
    1.11  			else													\
    1.12 -				return EMPTY & ((1UL << bits)-1);								\
    1.13 +				return EMPTY & ((1ULL << bits)-1);								\
    1.14  		}															\
    1.15  	} while (0)
    1.16  /*}}}*/