1.1 diff -r 49526038b0fb -r fef12817c5e8 src/main.c 1.2 --- a/src/main.c Wed Dec 01 22:15:41 2010 +0000 1.3 +++ b/src/main.c Wed Dec 01 22:34:15 2010 +0000 1.4 @@ -18,6 +18,51 @@ 1.5 exit(EXIT_FAILURE); 1.6 } 1.7 1.8 +/*********************************** 1.9 + * Array read/write utility macros 1.10 + * "Don't Repeat Yourself" :) 1.11 + ***********************************/ 1.12 + 1.13 +/// Array read, 32-bit 1.14 +#define RD32(array, address, andmask) \ 1.15 + (((uint32_t)array[(address + 0) & (andmask)] << 24) | \ 1.16 + ((uint32_t)array[(address + 1) & (andmask)] << 16) | \ 1.17 + ((uint32_t)array[(address + 2) & (andmask)] << 8) | \ 1.18 + ((uint32_t)array[(address + 3) & (andmask)])) 1.19 + 1.20 +/// Array read, 16-bit 1.21 +#define RD16(array, address, andmask) \ 1.22 + (((uint32_t)array[(address + 0) & (andmask)] << 8) | \ 1.23 + ((uint32_t)array[(address + 1) & (andmask)])) 1.24 + 1.25 +/// Array read, 8-bit 1.26 +#define RD8(array, address, andmask) \ 1.27 + ((uint32_t)array[(address + 0) & (andmask)]) 1.28 + 1.29 +/// Array write, 32-bit 1.30 +#define WR32(array, address, andmask, value) { \ 1.31 + array[(address + 0) & (andmask)] = (value >> 24) & 0xff; \ 1.32 + array[(address + 1) & (andmask)] = (value >> 16) & 0xff; \ 1.33 + array[(address + 2) & (andmask)] = (value >> 8) & 0xff; \ 1.34 + array[(address + 3) & (andmask)] = value & 0xff; \ 1.35 +} 1.36 + 1.37 +/// Array write, 16-bit 1.38 +#define WR16(array, address, andmask, value) { \ 1.39 + array[(address + 0) & (andmask)] = (value >> 8) & 0xff; \ 1.40 + array[(address + 1) & (andmask)] = value & 0xff; \ 1.41 +} 1.42 + 1.43 +/// Array write, 8-bit 1.44 +#define WR8(array, address, andmask, value) \ 1.45 + array[(address + 0) & (andmask)] = value & 0xff; 1.46 + 1.47 + 1.48 +/******************************************************** 1.49 + * m68k memory read/write support functions for Musashi 1.50 + ********************************************************/ 1.51 + 1.52 + 1.53 // read m68k memory 1.54 uint32_t m68k_read_memory_32(uint32_t address) 1.55 { 1.56 @@ -29,22 +74,13 @@ 1.57 1.58 if ((address >= 0x800000) && (address <= 0xBFFFFF)) { 1.59 // ROM access 1.60 - data = (((uint32_t)state.rom[(address + 0) & (ROM_SIZE - 1)] << 24) | 1.61 - ((uint32_t)state.rom[(address + 1) & (ROM_SIZE - 1)] << 16) | 1.62 - ((uint32_t)state.rom[(address + 2) & (ROM_SIZE - 1)] << 8) | 1.63 - ((uint32_t)state.rom[(address + 3) & (ROM_SIZE - 1)])); 1.64 - } else if (address < state.ram_size - 1) { 1.65 + data = RD32(state.rom, address, ROM_SIZE - 1); 1.66 + } else if (address <= (state.ram_size - 1)) { 1.67 // RAM 1.68 - data = (((uint32_t)state.ram[address + 0] << 24) | 1.69 - ((uint32_t)state.ram[address + 1] << 16) | 1.70 - ((uint32_t)state.ram[address + 2] << 8) | 1.71 - ((uint32_t)state.ram[address + 3])); 1.72 + data = RD32(state.ram, address, state.ram_size - 1); 1.73 } else if ((address >= 0x420000) && (address <= 0x427FFF)) { 1.74 // VRAM 1.75 - data = (((uint32_t)state.vram[(address + 0) & 0x7fff] << 24) | 1.76 - ((uint32_t)state.vram[(address + 1) & 0x7fff] << 16) | 1.77 - ((uint32_t)state.vram[(address + 2) & 0x7fff] << 8) | 1.78 - ((uint32_t)state.vram[(address + 3) & 0x7fff])); 1.79 + data = RD32(state.vram, address, 0x7FFF); 1.80 } else { 1.81 // I/O register -- TODO 1.82 printf("RD32 0x%08X [unknown I/O register]\n", address); 1.83 @@ -62,16 +98,13 @@ 1.84 1.85 if ((address >= 0x800000) && (address <= 0xBFFFFF)) { 1.86 // ROM access 1.87 - data = ((state.rom[(address + 0) & (ROM_SIZE - 1)] << 8) | 1.88 - (state.rom[(address + 1) & (ROM_SIZE - 1)])); 1.89 - } else if (address < state.ram_size - 1) { 1.90 + data = RD16(state.rom, address, ROM_SIZE - 1); 1.91 + } else if (address <= (state.ram_size - 1)) { 1.92 // RAM 1.93 - data = ((state.ram[address + 0] << 8) | 1.94 - (state.ram[address + 1])); 1.95 + data = RD16(state.ram, address, state.ram_size - 1); 1.96 } else if ((address >= 0x420000) && (address <= 0x427FFF)) { 1.97 // VRAM 1.98 - data = (((uint16_t)state.vram[(address + 0) & 0x7fff] << 8) | 1.99 - ((uint16_t)state.vram[(address + 1) & 0x7fff])); 1.100 + data = RD16(state.vram, address, 0x7FFF); 1.101 } else { 1.102 // I/O register -- TODO 1.103 printf("RD16 0x%08X [unknown I/O register]\n", address); 1.104 @@ -90,13 +123,13 @@ 1.105 1.106 if ((address >= 0x800000) && (address <= 0xBFFFFF)) { 1.107 // ROM access 1.108 - data = state.rom[(address + 0) & (ROM_SIZE - 1)]; 1.109 - } else if (address < state.ram_size) { 1.110 - // RAM access 1.111 - data = state.ram[address + 0]; 1.112 + data = RD8(state.rom, address, ROM_SIZE - 1); 1.113 + } else if (address <= (state.ram_size - 1)) { 1.114 + // RAM 1.115 + data = RD8(state.ram, address, state.ram_size - 1); 1.116 } else if ((address >= 0x420000) && (address <= 0x427FFF)) { 1.117 // VRAM 1.118 - data = state.vram[(address + 0) & 0x7fff]; 1.119 + data = RD8(state.vram, address, 0x7FFF); 1.120 } else { 1.121 // I/O register -- TODO 1.122 printf("RD08 0x%08X [unknown I/O register]\n", address); 1.123 @@ -115,18 +148,12 @@ 1.124 if ((address >= 0x800000) && (address <= 0xBFFFFF)) { 1.125 // ROM access 1.126 // TODO: bus error here? can't write to rom! 1.127 - } else if (address < state.ram_size) { 1.128 + } else if (address <= (state.ram_size - 1)) { 1.129 // RAM access 1.130 - state.ram[address + 0] = (value >> 24) & 0xff; 1.131 - state.ram[address + 1] = (value >> 16) & 0xff; 1.132 - state.ram[address + 2] = (value >> 8) & 0xff; 1.133 - state.ram[address + 3] = value & 0xff; 1.134 + WR32(state.ram, address, state.ram_size - 1, value); 1.135 } else if ((address >= 0x420000) && (address <= 0x427FFF)) { 1.136 // VRAM access 1.137 - state.vram[(address + 0) & 0x7fff] = (value >> 24) & 0xff; 1.138 - state.vram[(address + 1) & 0x7fff] = (value >> 16) & 0xff; 1.139 - state.vram[(address + 2) & 0x7fff] = (value >> 8) & 0xff; 1.140 - state.vram[(address + 3) & 0x7fff] = value & 0xff; 1.141 + WR32(state.vram, address, 0x7fff, value); 1.142 } else { 1.143 switch (address) { 1.144 case 0xE43000: state.romlmap = ((value & 0x8000) == 0x8000); break; // GCR3: ROMLMAP 1.145 @@ -144,14 +171,12 @@ 1.146 if ((address >= 0x800000) && (address <= 0xBFFFFF)) { 1.147 // ROM access 1.148 // TODO: bus error here? can't write to rom! 1.149 - } else if (address < state.ram_size) { 1.150 + } else if (address <= (state.ram_size - 1)) { 1.151 // RAM access 1.152 - state.ram[address + 0] = (value >> 8) & 0xff; 1.153 - state.ram[address + 1] = value & 0xff; 1.154 + WR16(state.ram, address, state.ram_size - 1, value); 1.155 } else if ((address >= 0x420000) && (address <= 0x427FFF)) { 1.156 // VRAM access 1.157 - state.vram[(address + 0) & 0x7fff] = (value >> 8) & 0xff; 1.158 - state.vram[(address + 1) & 0x7fff] = value & 0xff; 1.159 + WR16(state.vram, address, 0x7fff, value); 1.160 } else { 1.161 switch (address) { 1.162 case 0xE43000: state.romlmap = ((value & 0x8000) == 0x8000); break; // GCR3: ROMLMAP 1.163 @@ -177,11 +202,12 @@ 1.164 if ((address >= 0x800000) && (address <= 0xBFFFFF)) { 1.165 // ROM access 1.166 // TODO: bus error here? can't write to rom! 1.167 - } else if (address < state.ram_size) { 1.168 - state.ram[address] = value & 0xff; 1.169 + } else if (address <= (state.ram_size - 1)) { 1.170 + // RAM access 1.171 + WR8(state.ram, address, state.ram_size - 1, value); 1.172 } else if ((address >= 0x420000) && (address <= 0x427FFF)) { 1.173 // VRAM access 1.174 - state.vram[address & 0x7fff] = value; 1.175 + WR8(state.vram, address, 0x7fff, value); 1.176 } else { 1.177 switch (address) { 1.178 case 0xE43000: state.romlmap = ((value & 0x80) == 0x80); break; // GCR3: ROMLMAP