3b1emu / files

     1.1 diff -r 1d55c8c7c1ac -r 4d59e4ceef52 src/memory.c
     1.2 --- a/src/memory.c	Thu Dec 02 23:37:49 2010 +0000
     1.3 +++ b/src/memory.c	Fri Dec 03 00:04:01 2010 +0000
     1.4 @@ -98,12 +98,12 @@
     1.5  				break;												\
     1.6  			case MEM_PAGEFAULT:										\
     1.7  				/* Page fault */									\
     1.8 -				state.genstat = 0x8FFF;								\
     1.9 +				state.genstat = 0x8BFF | (status.pie ? 0x0400 : 0);	\
    1.10  				fault = true;										\
    1.11  				break;												\
    1.12  			case MEM_UIE:											\
    1.13  				/* User access to memory above 4MB */				\
    1.14 -				state.genstat = 0x9EFF;								\
    1.15 +				state.genstat = 0x9AFF | (status.pie ? 0x0400 : 0);	\
    1.16  				fault = true;										\
    1.17  				break;												\
    1.18  			case MEM_KERNEL:										\
    1.19 @@ -145,12 +145,12 @@
    1.20  				break;												\
    1.21  			case MEM_PAGEFAULT:										\
    1.22  				/* Page fault */									\
    1.23 -				state.genstat = 0x8FFF;								\
    1.24 +				state.genstat = 0xCBFF | (status.pie ? 0x0400 : 0);	\
    1.25  				fault = true;										\
    1.26  				break;												\
    1.27  			case MEM_UIE:											\
    1.28  				/* User access to memory above 4MB */				\
    1.29 -				state.genstat = 0x9EFF;								\
    1.30 +				state.genstat = 0xDAFF | (status.pie ? 0x0400 : 0);	\
    1.31  				fault = true;										\
    1.32  				break;												\
    1.33  			case MEM_KERNEL:										\
    1.34 @@ -275,7 +275,8 @@
    1.35  				break;
    1.36  			case 0x0B0000:				// TM/DIALWR
    1.37  				break;
    1.38 -			case 0x0C0000:				// CSR
    1.39 +			case 0x0C0000:				// Clear Status Register
    1.40 +				handled = true;
    1.41  				break;
    1.42  			case 0x0D0000:				// DMA Address Register
    1.43  				break;
    1.44 @@ -439,7 +440,8 @@
    1.45  				break;
    1.46  			case 0x0B0000:				// TM/DIALWR
    1.47  				break;
    1.48 -			case 0x0C0000:				// CSR
    1.49 +			case 0x0C0000:				// Clear Status Register
    1.50 +				handled = true;
    1.51  				break;
    1.52  			case 0x0D0000:				// DMA Address Register
    1.53  				break;
    1.54 @@ -612,7 +614,8 @@
    1.55  				break;
    1.56  			case 0x0B0000:				// TM/DIALWR
    1.57  				break;
    1.58 -			case 0x0C0000:				// CSR
    1.59 +			case 0x0C0000:				// Clear Status Register
    1.60 +				handled = true;
    1.61  				break;
    1.62  			case 0x0D0000:				// DMA Address Register
    1.63  				break;
    1.64 @@ -770,7 +773,11 @@
    1.65  				break;
    1.66  			case 0x0B0000:				// TM/DIALWR
    1.67  				break;
    1.68 -			case 0x0C0000:				// CSR
    1.69 +			case 0x0C0000:				// Clear Status Register
    1.70 +				state.genstat = 0xFFFF;
    1.71 +				state.bsr0 = 0xFFFF;
    1.72 +				state.bsr1 = 0xFFFF;
    1.73 +				handled = true;
    1.74  				break;
    1.75  			case 0x0D0000:				// DMA Address Register
    1.76  				break;
    1.77 @@ -929,7 +936,11 @@
    1.78  				break;
    1.79  			case 0x0B0000:				// TM/DIALWR
    1.80  				break;
    1.81 -			case 0x0C0000:				// CSR
    1.82 +			case 0x0C0000:				// Clear Status Register
    1.83 +				state.genstat = 0xFFFF;
    1.84 +				state.bsr0 = 0xFFFF;
    1.85 +				state.bsr1 = 0xFFFF;
    1.86 +				handled = true;
    1.87  				break;
    1.88  			case 0x0D0000:				// DMA Address Register
    1.89  				break;
    1.90 @@ -1088,7 +1099,11 @@
    1.91  				break;
    1.92  			case 0x0B0000:				// TM/DIALWR
    1.93  				break;
    1.94 -			case 0x0C0000:				// CSR
    1.95 +			case 0x0C0000:				// Clear Status Register
    1.96 +				state.genstat = 0xFFFF;
    1.97 +				state.bsr0 = 0xFFFF;
    1.98 +				state.bsr1 = 0xFFFF;
    1.99 +				handled = true;
   1.100  				break;
   1.101  			case 0x0D0000:				// DMA Address Register
   1.102  				break;