Tue, 28 Dec 2010 17:23:04 +0000
fixes to Base RAM addressing -- 512K detected OK now, still need to deal with Expansion RAM detect issues
| src/memory.c | file | annotate | diff | revisions | |
| src/state.c | file | annotate | diff | revisions | |
| src/state.h | file | annotate | diff | revisions |
1.1 diff -r d2e3b9e5d082 -r 96f3df0b3cbb src/memory.c 1.2 --- a/src/memory.c Tue Dec 28 16:59:40 2010 +0000 1.3 +++ b/src/memory.c Tue Dec 28 17:23:04 2010 +0000 1.4 @@ -235,7 +235,7 @@ 1.5 // This handles the "dummy DMA transfer" mentioned in the docs 1.6 // TODO: access check, peripheral access 1.7 if (!state.idmarw) 1.8 - WR32(state.ram, mapAddr(address, false), state.ram_size - 1, 0xDEAD); 1.9 + WR32(state.base_ram, mapAddr(address, true), state.base_ram_size - 1, 0xDEAD); 1.10 state.dma_count++; 1.11 handled = true; 1.12 break; 1.13 @@ -557,26 +557,31 @@ 1.14 1.15 if ((address >= 0x800000) && (address <= 0xBFFFFF)) { 1.16 // ROM access 1.17 - data = RD32(state.rom, address, ROM_SIZE - 1); 1.18 - } else if (address <= (state.ram_size - 1)) { 1.19 + return RD32(state.rom, address, ROM_SIZE - 1); 1.20 + } else if (address <= 0x3fffff) { 1.21 // RAM access 1.22 - data = RD32(state.ram, mapAddr(address, false), state.ram_size - 1); 1.23 + uint32_t newAddr = mapAddr(address, false); 1.24 +// if (newAddr < state.base_ram_size) 1.25 + return RD32(state.base_ram, newAddr, state.base_ram_size - 1); 1.26 +// else 1.27 +// return 0xFFFFFFFF; 1.28 + // TODO: expansion RAM 1.29 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) { 1.30 // I/O register space, zone A 1.31 switch (address & 0x0F0000) { 1.32 case 0x000000: // Map RAM access 1.33 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD32 from MapRAM mirror, addr=0x%08X\n", address); 1.34 - data = RD32(state.map, address, 0x7FF); 1.35 + return RD32(state.map, address, 0x7FF); 1.36 break; 1.37 case 0x020000: // Video RAM 1.38 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD32 from VideoRAM mirror, addr=0x%08X\n", address); 1.39 - data = RD32(state.vram, address, 0x7FFF); 1.40 + return RD32(state.vram, address, 0x7FFF); 1.41 break; 1.42 default: 1.43 - data = IoRead(address, 32); 1.44 + return IoRead(address, 32); 1.45 } 1.46 } else { 1.47 - data = IoRead(address, 32); 1.48 + return IoRead(address, 32); 1.49 } 1.50 1.51 return data; 1.52 @@ -599,9 +604,14 @@ 1.53 if ((address >= 0x800000) && (address <= 0xBFFFFF)) { 1.54 // ROM access 1.55 data = RD16(state.rom, address, ROM_SIZE - 1); 1.56 - } else if (address <= (state.ram_size - 1)) { 1.57 + } else if (address <= 0x3fffff) { 1.58 // RAM access 1.59 - data = RD16(state.ram, mapAddr(address, false), state.ram_size - 1); 1.60 + uint32_t newAddr = mapAddr(address, false); 1.61 +// if (newAddr < state.base_ram_size) 1.62 + return RD16(state.base_ram, newAddr, state.base_ram_size - 1); 1.63 +// else 1.64 +// return 0xFFFFFFFF; 1.65 + // TODO: expansion RAM 1.66 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) { 1.67 // I/O register space, zone A 1.68 switch (address & 0x0F0000) { 1.69 @@ -640,9 +650,14 @@ 1.70 if ((address >= 0x800000) && (address <= 0xBFFFFF)) { 1.71 // ROM access 1.72 data = RD8(state.rom, address, ROM_SIZE - 1); 1.73 - } else if (address <= (state.ram_size - 1)) { 1.74 + } else if (address <= 0x3fffff) { 1.75 // RAM access 1.76 - data = RD8(state.ram, mapAddr(address, false), state.ram_size - 1); 1.77 + uint32_t newAddr = mapAddr(address, false); 1.78 +// if (newAddr < state.base_ram_size) 1.79 + return RD8(state.base_ram, newAddr, state.base_ram_size - 1); 1.80 +// else 1.81 +// return 0xFFFFFFFF; 1.82 + // TODO: expansion RAM 1.83 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) { 1.84 // I/O register space, zone A 1.85 switch (address & 0x0F0000) { 1.86 @@ -678,9 +693,11 @@ 1.87 1.88 if ((address >= 0x800000) && (address <= 0xBFFFFF)) { 1.89 // ROM access 1.90 - } else if (address <= (state.ram_size - 1)) { 1.91 + } else if (address <= 0x3FFFFF) { 1.92 // RAM access 1.93 - WR32(state.ram, mapAddr(address, false), state.ram_size - 1, value); 1.94 + uint32_t newAddr = mapAddr(address, true); 1.95 + if (newAddr <= 0x1fffff) //(state.base_ram_size - 1)) 1.96 + WR32(state.base_ram, newAddr, state.base_ram_size - 1, value); 1.97 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) { 1.98 // I/O register space, zone A 1.99 switch (address & 0x0F0000) { 1.100 @@ -714,9 +731,11 @@ 1.101 1.102 if ((address >= 0x800000) && (address <= 0xBFFFFF)) { 1.103 // ROM access 1.104 - } else if (address <= (state.ram_size - 1)) { 1.105 + } else if (address <= 0x3FFFFF) { 1.106 // RAM access 1.107 - WR16(state.ram, mapAddr(address, false), state.ram_size - 1, value); 1.108 + uint32_t newAddr = mapAddr(address, true); 1.109 + if (newAddr <= 0x1fffff) //(state.base_ram_size - 1)) 1.110 + WR16(state.base_ram, newAddr, state.base_ram_size - 1, value); 1.111 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) { 1.112 // I/O register space, zone A 1.113 switch (address & 0x0F0000) { 1.114 @@ -750,9 +769,11 @@ 1.115 1.116 if ((address >= 0x800000) && (address <= 0xBFFFFF)) { 1.117 // ROM access (read only!) 1.118 - } else if (address <= (state.ram_size - 1)) { 1.119 + } else if (address <= 0x3FFFFF) { 1.120 // RAM access 1.121 - WR8(state.ram, mapAddr(address, false), state.ram_size - 1, value); 1.122 + uint32_t newAddr = mapAddr(address, true); 1.123 + if (newAddr <= 0x1fffff) //(state.base_ram_size - 1)) 1.124 + WR8(state.base_ram, newAddr, state.base_ram_size - 1, value); 1.125 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) { 1.126 // I/O register space, zone A 1.127 switch (address & 0x0F0000) {
2.1 diff -r d2e3b9e5d082 -r 96f3df0b3cbb src/state.c 2.2 --- a/src/state.c Tue Dec 28 16:59:40 2010 +0000 2.3 +++ b/src/state.c Tue Dec 28 17:23:04 2010 +0000 2.4 @@ -8,8 +8,8 @@ 2.5 int state_init(size_t ramsize) 2.6 { 2.7 // Free RAM if it's allocated 2.8 - if (state.ram != NULL) 2.9 - free(state.ram); 2.10 + if (state.base_ram != NULL) 2.11 + free(state.base_ram); 2.12 2.13 // Initialise hardware registers 2.14 state.romlmap = false; 2.15 @@ -18,10 +18,10 @@ 2.16 // Basically: 512KiB minimum, 4MiB maximum, in increments of 512KiB. 2.17 if ((ramsize < 512*1024) || ((ramsize % (512*1024)) != 0)) 2.18 return -1; 2.19 - state.ram = malloc(ramsize); 2.20 - if (state.ram == NULL) 2.21 + state.base_ram = malloc(ramsize); 2.22 + if (state.base_ram == NULL) 2.23 return -2; 2.24 - state.ram_size = ramsize; 2.25 + state.base_ram_size = ramsize; 2.26 2.27 // Load ROMs 2.28 FILE *r14c, *r15c; 2.29 @@ -81,9 +81,9 @@ 2.30 2.31 void state_done() 2.32 { 2.33 - if (state.ram != NULL) { 2.34 - free(state.ram); 2.35 - state.ram = NULL; 2.36 + if (state.base_ram != NULL) { 2.37 + free(state.base_ram); 2.38 + state.base_ram = NULL; 2.39 } 2.40 2.41 // Deinitialise the disc controller
3.1 diff -r d2e3b9e5d082 -r 96f3df0b3cbb src/state.h 3.2 --- a/src/state.h Tue Dec 28 16:59:40 2010 +0000 3.3 +++ b/src/state.h Tue Dec 28 17:23:04 2010 +0000 3.4 @@ -29,8 +29,8 @@ 3.5 uint8_t rom[ROM_SIZE]; ///< Boot PROM data buffer 3.6 3.7 //// Main system RAM 3.8 - uint8_t *ram; ///< RAM data buffer 3.9 - size_t ram_size; ///< Size of RAM buffer in bytes 3.10 + uint8_t *base_ram; ///< Base RAM data buffer 3.11 + size_t base_ram_size; ///< Size of Base RAM buffer in bytes 3.12 3.13 /// Video RAM 3.14 uint8_t vram[0x8000];