Sun, 06 Mar 2011 21:17:31 +0000
[MERGE] Merge changes from LatticeMico32 v3.6
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philpem@8 | 130 | <h1>LatticeMico32 Processor <a title="View Reference Manual" href="lm32_archman.pdf" target="_blank" onmouseover="if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) ehlp_showtip(this,event,'View Reference Manual');" onmouseout="if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) ehlp_hidetip();"><img src="ds_icon_ast.jpg" x-maintain-ratio="TRUE" width="29px" height="31px" border="0" class="img_whs1"></a></h1> |
philpem@8 | 131 | |
philpem@8 | 132 | <p>The LatticeMico32 processor is a high-performance 32-bit microprocessor |
philpem@8 | 133 | optimized for Lattice Semiconductor field-programmable gate arrays. </p> |
philpem@8 | 134 | |
philpem@8 | 135 | <p class="whs2"><span style="font-style: italic;"><I>*If the |
philpem@8 | 136 | processor manual fails to open, see the note at the bottom of this page.</I></span></p> |
philpem@8 | 137 | |
philpem@8 | 138 | <h2>Revision History</h2> |
philpem@8 | 139 | |
philpem@8 | 140 | <table x-use-null-cells cellspacing="0" width="738" height="84" class="whs3"> |
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philpem@8 | 143 | //--></script> |
philpem@8 | 144 | <col class="whs4"> |
philpem@8 | 145 | <col class="whs5"> |
philpem@8 | 146 | |
philpem@8 | 147 | <tr valign="top" class="whs6"> |
philpem@8 | 148 | <td bgcolor="#DEE8F4" width="93px" class="whs7"> |
philpem@8 | 149 | <p class=Table |
philpem@8 | 150 | style="font-weight: bold;">Version</td> |
philpem@8 | 151 | <td bgcolor="#DEE8F4" width="598px" class="whs8"> |
philpem@8 | 152 | <p class=Table |
philpem@8 | 153 | style="font-weight: bold;">Description</td></tr> |
philpem@8 | 154 | |
philpem@8 | 155 | <tr valign="top" class="whs6"> |
philpem@8 | 156 | <td colspan="1" rowspan="1" width="93px" class="whs9"> |
philpem@8 | 157 | <p class=Table |
philpem@22 | 158 | style="font-weight: normal;">3.6</td> |
philpem@22 | 159 | <td colspan="1" rowspan="1" width="598px" class="whs10"> |
philpem@22 | 160 | <p class=whs10 |
philpem@22 | 161 | style="margin-left: 0px;">Fixed the issue of the processor locking |
philpem@22 | 162 | up when Instruction Cache is not used.</td></tr> |
philpem@22 | 163 | |
philpem@22 | 164 | <tr valign="top" class="whs6"> |
philpem@22 | 165 | <td colspan="1" rowspan="1" width="93px" class="whs9"> |
philpem@22 | 166 | <p class=Table |
philpem@8 | 167 | style="font-weight: normal;">3.5</td> |
philpem@8 | 168 | <td colspan="1" rowspan="1" width="598px" class="whs10"> |
philpem@8 | 169 | <p class=whs10 |
philpem@8 | 170 | style="margin-left: 0px;">Support added to allow Inline Memories to |
philpem@8 | 171 | be generated as non-power-of-two, as long as they are a multiple of 1024 |
philpem@8 | 172 | bytes</td></tr> |
philpem@8 | 173 | |
philpem@8 | 174 | <tr valign="top" class="whs6"> |
philpem@8 | 175 | <td colspan="1" rowspan="1" width="93px" class="whs9"> |
philpem@8 | 176 | <p class=Table |
philpem@22 | 177 | style="font-weight: normal;">3.4</td> |
philpem@22 | 178 | <td colspan="1" rowspan="1" width="598px" class="whs10"> |
philpem@22 | 179 | <p class=whs10 |
philpem@22 | 180 | style="margin-left: 0px;">Updated to support ispLEVER 7.2 SP1.</td></tr> |
philpem@22 | 181 | |
philpem@22 | 182 | <tr valign="top" class="whs6"> |
philpem@22 | 183 | <td colspan="1" rowspan="1" width="93px" class="whs9"> |
philpem@22 | 184 | <p class=Table |
philpem@8 | 185 | style="font-weight: normal;">3.3</td> |
philpem@8 | 186 | <td colspan="1" rowspan="1" width="598px" class="whs10"> |
philpem@8 | 187 | <p class=whs10 |
philpem@22 | 188 | style="margin-left: 0px;">Updated to support ispLEVER 7.2.</p> |
philpem@22 | 189 | <p class=whs10 |
philpem@8 | 190 | style="margin-left: 0px;">Added Inline Memory to support on-chip memory |
philpem@8 | 191 | connected through a local bus.</td></tr> |
philpem@8 | 192 | |
philpem@8 | 193 | <tr valign="top" class="whs6"> |
philpem@8 | 194 | <td colspan="1" rowspan="1" width="93px" class="whs9"> |
philpem@8 | 195 | <p class=Table |
philpem@8 | 196 | style="font-weight: normal;">3.2</td> |
philpem@8 | 197 | <td colspan="1" rowspan="1" width="598px" class="whs10"> |
philpem@8 | 198 | <p class=whs10 |
philpem@22 | 199 | style="margin-left: 0px;">Updated to support ispLEVER 7.1 SP1</p> |
philpem@22 | 200 | <p class=whs10 |
philpem@8 | 201 | style="margin-left: 0px;">Added Memory Type to instruction cache and |
philpem@8 | 202 | data cache.</td></tr> |
philpem@8 | 203 | |
philpem@8 | 204 | <tr valign="top" class="whs6"> |
philpem@8 | 205 | <td colspan="1" rowspan="1" width="93px" class="whs9"> |
philpem@8 | 206 | <p class=Table |
philpem@8 | 207 | style="font-weight: normal;">3.1</td> |
philpem@8 | 208 | <td colspan="1" rowspan="1" width="598px" class="whs10"> |
philpem@22 | 209 | <p class="whs11">Updated to support ispLEVER 7.1.</p> |
philpem@8 | 210 | <p class="whs11">Added static predictor to improve the behavior |
philpem@8 | 211 | of branches.</p> |
philpem@8 | 212 | <p class="whs11">Added support for optionally mapping the register |
philpem@8 | 213 | file to EBRs (on-chip memory).</p> |
philpem@8 | 214 | <p class="whs11">Added support for selecting between distributed |
philpem@8 | 215 | RAM and EBRs (pseudo-dual port or true-dual port) for instruction and |
philpem@8 | 216 | data caches.</td></tr> |
philpem@8 | 217 | |
philpem@8 | 218 | <tr valign="top" class="whs6"> |
philpem@8 | 219 | <td colspan="1" rowspan="1" width="93px" class="whs9"> |
philpem@8 | 220 | <p class=Table |
philpem@8 | 221 | style="font-weight: normal;"><span style="font-weight: normal;">3.0 |
philpem@22 | 222 | (7.0 SP2)</span></td> |
philpem@8 | 223 | <td colspan="1" rowspan="1" width="598px" class="whs10"> |
philpem@22 | 224 | <p class="whs11">Updated to support ispLEVER 7.0 SP2.</p> |
philpem@8 | 225 | <p class="whs11">Fixed incorrect handling of data cache miss |
philpem@8 | 226 | in the presence of an instruction cache miss.</td></tr> |
philpem@8 | 227 | |
philpem@8 | 228 | <tr valign="top" class="whs6"> |
philpem@8 | 229 | <td colspan="1" rowspan="1" width="93px" class="whs9"> |
philpem@8 | 230 | <p class="whs11">1.0</td> |
philpem@8 | 231 | <td colspan="1" rowspan="1" width="598px" class="whs10"> |
philpem@8 | 232 | <p class="whs11">Initial version.</td></tr> |
philpem@8 | 233 | <script language='JavaScript'><!-- |
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philpem@8 | 236 | </table> |
philpem@8 | 237 | |
philpem@8 | 238 | |
philpem@8 | 239 | |
philpem@8 | 240 | <h2>Dialog Box Parameters – |
philpem@8 | 241 | General Tab</h2> |
philpem@8 | 242 | |
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philpem@8 | 244 | <col class="whs13"> |
philpem@8 | 245 | <col class="whs14"> |
philpem@8 | 246 | |
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philpem@8 | 248 | <td bgcolor="#DEE8F4" width="167px" class="whs16"> |
philpem@8 | 249 | <p class=Table |
philpem@8 | 250 | style="font-weight: bold;">Parameter</td> |
philpem@8 | 251 | <td bgcolor="#DEE8F4" width="524px" class="whs17"> |
philpem@8 | 252 | <p class=Table |
philpem@8 | 253 | style="font-weight: bold;">Description</td></tr> |
philpem@8 | 254 | |
philpem@8 | 255 | <tr valign="top" class="whs15"> |
philpem@8 | 256 | <td colspan="1" rowspan="1" width="167px" class="whs18"> |
philpem@8 | 257 | <p class=Table |
philpem@8 | 258 | style="font-weight: normal;">Instance Name</td> |
philpem@8 | 259 | <td colspan="1" rowspan="1" width="524px" class="whs19"> |
philpem@8 | 260 | <p class=Table |
philpem@8 | 261 | style="margin-left: 14px;">Specifies the name of the LatticeMico32 |
philpem@8 | 262 | processor. Alphanumeric values and underscores are supported. The default |
philpem@8 | 263 | is LM32.</td></tr> |
philpem@8 | 264 | |
philpem@8 | 265 | <tr valign="top" class="whs15"> |
philpem@8 | 266 | <td colspan="2" rowspan="1" width="691px" class="whs20"> |
philpem@8 | 267 | <p class=Table |
philpem@8 | 268 | style="font-weight: bold;">Settings</td> |
philpem@8 | 269 | </tr> |
philpem@8 | 270 | |
philpem@8 | 271 | <tr valign="top" class="whs15"> |
philpem@8 | 272 | <td colspan="1" rowspan="1" width="167px" class="whs18"> |
philpem@8 | 273 | <p class=Table>Use EBRs for Register File</td> |
philpem@8 | 274 | <td colspan="1" rowspan="1" width="524px" class="whs21"> |
philpem@8 | 275 | <p class=Table>Uses embedded block RAMS for the register file.</td></tr> |
philpem@8 | 276 | |
philpem@8 | 277 | <tr valign="top" class="whs15"> |
philpem@8 | 278 | <td colspan="1" rowspan="1" width="167px" class="whs18"> |
philpem@8 | 279 | <p class=Table>Enable Divide</td> |
philpem@8 | 280 | <td colspan="1" rowspan="1" width="524px" class="whs21"> |
philpem@8 | 281 | <p class=Table>Enables the divide and modulus instructions (<span style="font-family: Verdana, sans-serif;">divu, |
philpem@8 | 282 | modu</span>).</td></tr> |
philpem@8 | 283 | |
philpem@8 | 284 | <tr valign="top" class="whs15"> |
philpem@8 | 285 | <td colspan="1" rowspan="1" width="167px" class="whs18"> |
philpem@8 | 286 | <p class=Table>Enable Sign Extend</td> |
philpem@8 | 287 | <td colspan="1" rowspan="1" width="524px" class="whs21"> |
philpem@8 | 288 | <p class=Table>Enables the sign-extension instructions (<span style="font-family: Verdana, sans-serif;">sextb, |
philpem@8 | 289 | sexth</span><span style="font-family: Arial, sans-serif;">)</span>.</td></tr> |
philpem@8 | 290 | |
philpem@8 | 291 | <tr valign="top" class="whs15"> |
philpem@8 | 292 | <td colspan="1" rowspan="1" width="167px" class="whs18"> |
philpem@8 | 293 | <p class=Table>Location of Exception Handlers</td> |
philpem@8 | 294 | <td colspan="1" rowspan="1" width="524px" class="whs21"> |
philpem@8 | 295 | <p class=Table>Specifies the default value for the vector table. This can |
philpem@8 | 296 | be changed by updating the EBA control register or status register.</p> |
philpem@8 | 297 | <p class=Table>This address must be aligned to a 256-byte boundary, since |
philpem@8 | 298 | the hardware ignores the least-significant byte. Unpredictable behavior |
philpem@8 | 299 | occurs when the exception base address and the exception vectors are not |
philpem@8 | 300 | aligned on a 256-byte boundary.</td></tr> |
philpem@8 | 301 | |
philpem@8 | 302 | <tr valign="top" class="whs15"> |
philpem@8 | 303 | <td colspan="2" rowspan="1" width="691px" class="whs20"> |
philpem@8 | 304 | <p class=Table |
philpem@8 | 305 | style="font-weight: bold;">Multiplier Settings</td> |
philpem@8 | 306 | </tr> |
philpem@8 | 307 | |
philpem@8 | 308 | <tr valign="top" class="whs15"> |
philpem@8 | 309 | <td colspan="1" rowspan="1" width="167px" class="whs18"> |
philpem@8 | 310 | <p class=Table>Enable Multiplier</td> |
philpem@8 | 311 | <td colspan="1" rowspan="1" width="524px" class="whs21"> |
philpem@8 | 312 | <p class=Table>Enables the multiply instructions (<span style="font-family: Verdana, sans-serif;">mul, |
philpem@8 | 313 | muli)</span>.</td></tr> |
philpem@8 | 314 | |
philpem@8 | 315 | <tr valign="top" class="whs15"> |
philpem@8 | 316 | <td colspan="1" rowspan="1" width="167px" class="whs18"> |
philpem@8 | 317 | <p class=Table>Enable Pipelined Multiplier (DSP Block if available)</td> |
philpem@8 | 318 | <td colspan="1" rowspan="1" width="524px" class="whs21"> |
philpem@8 | 319 | <p class=Table>Enables the multiplier using the DSP block, if available.</td></tr> |
philpem@8 | 320 | |
philpem@8 | 321 | <tr valign="top" class="whs15"> |
philpem@8 | 322 | <td colspan="1" rowspan="1" width="167px" class="whs18"> |
philpem@8 | 323 | <p class=Table>Enable Multicycle (LUT-based, 32 cycles) Multiplier</td> |
philpem@8 | 324 | <td colspan="1" rowspan="1" width="524px" class="whs21"> |
philpem@8 | 325 | <p class=Table>Enables the multiplier using LUTs.</td></tr> |
philpem@8 | 326 | |
philpem@8 | 327 | <tr valign="top" class="whs15"> |
philpem@8 | 328 | <td colspan="2" rowspan="1" width="691px" class="whs20"> |
philpem@8 | 329 | <p class=Table |
philpem@8 | 330 | style="font-weight: bold;">Instruction Cache</td> |
philpem@8 | 331 | </tr> |
philpem@8 | 332 | |
philpem@8 | 333 | <tr valign="top" class="whs15"> |
philpem@8 | 334 | <td colspan="1" rowspan="1" width="167px" class="whs18"> |
philpem@8 | 335 | <p class=Table>Instruction Cache Enabled</td> |
philpem@8 | 336 | <td colspan="1" rowspan="1" width="524px" class="whs19"> |
philpem@8 | 337 | <p class=Table |
philpem@8 | 338 | style="margin-left: 14px;">Determines whether an instruction cache |
philpem@8 | 339 | is implemented.</td></tr> |
philpem@8 | 340 | |
philpem@8 | 341 | <tr valign="top" class="whs15"> |
philpem@8 | 342 | <td colspan="1" rowspan="1" width="167px" class="whs18"> |
philpem@8 | 343 | <p class=Table>Number of Sets</td> |
philpem@8 | 344 | <td colspan="1" rowspan="1" width="524px" class="whs19"> |
philpem@8 | 345 | <p class=Table |
philpem@8 | 346 | style="margin-left: 14px;">Specifies the number of sets in the instruction |
philpem@8 | 347 | cache. Supported values are 128, 256, 512, 1024.</td></tr> |
philpem@8 | 348 | |
philpem@8 | 349 | <tr valign="top" class="whs15"> |
philpem@8 | 350 | <td colspan="1" rowspan="1" width="167px" class="whs18"> |
philpem@8 | 351 | <p class=Table>Set Associativity</td> |
philpem@8 | 352 | <td colspan="1" rowspan="1" width="524px" class="whs19"> |
philpem@8 | 353 | <p class=Table |
philpem@8 | 354 | style="margin-left: 14px;">Specifies the associativity of the instruction |
philpem@8 | 355 | cache. Supported values are 1, 2.</td></tr> |
philpem@8 | 356 | |
philpem@8 | 357 | <tr valign="top" class="whs15"> |
philpem@8 | 358 | <td colspan="1" rowspan="1" width="167px" class="whs18"> |
philpem@8 | 359 | <p class=Table>Bytes/Cache Line</td> |
philpem@8 | 360 | <td colspan="1" rowspan="1" width="524px" class="whs19"> |
philpem@8 | 361 | <p class=Table |
philpem@8 | 362 | style="margin-left: 15px;">Specifies the number of bytes per instruction |
philpem@8 | 363 | cache line. Supported values are 4, 8, 16.</td></tr> |
philpem@8 | 364 | |
philpem@8 | 365 | <tr valign="top" class="whs15"> |
philpem@8 | 366 | <td colspan="1" rowspan="1" width="167px" class="whs18"> |
philpem@8 | 367 | <p class=Table>Memory Type</td> |
philpem@8 | 368 | <td colspan="1" rowspan="1" width="524px" class="whs19"> |
philpem@8 | 369 | <p class=Table |
philpem@8 | 370 | style="margin-left: 15px;">Determines the FPGA resource to be used |
philpem@8 | 371 | to implement the instruction cache. The decision can be left to the synthesis |
philpem@8 | 372 | tool (Auto), or you can select from the following options:</p> |
philpem@8 | 373 | <ul type="disc" class="whs22"> |
philpem@8 | 374 | |
philpem@8 | 375 | <li class=kadov-p-CBullet><p class=Bullet>Auto – |
philpem@8 | 376 | Leaves the implementation of the instruction cache to the synthesis tool.</p></li> |
philpem@8 | 377 | |
philpem@8 | 378 | <li class=kadov-p-CBullet><p class=Bullet>Distributed RAM – |
philpem@8 | 379 | Implements the instruction cache as distributed RAM.</p></li> |
philpem@8 | 380 | |
philpem@8 | 381 | <li class=kadov-p-CBullet><p class=Bullet>Dual-Port EBR – |
philpem@8 | 382 | Implements the instruction cache as dual-port EBR (two read/write ports).</p></li> |
philpem@8 | 383 | |
philpem@8 | 384 | <li class=kadov-p-CBullet><p class=Bullet>Pseudo Dual-Port EBR – Implements |
philpem@8 | 385 | the instruction cache as pseudo-dual-port EBR (one read port and one write |
philpem@8 | 386 | port). </p></li> |
philpem@8 | 387 | </ul></td></tr> |
philpem@8 | 388 | |
philpem@8 | 389 | <tr valign="top" class="whs15"> |
philpem@8 | 390 | <td colspan="2" rowspan="1" width="691px" class="whs20"> |
philpem@8 | 391 | <p class=Table |
philpem@8 | 392 | style="font-weight: bold;">Debug Setting</td> |
philpem@8 | 393 | </tr> |
philpem@8 | 394 | |
philpem@8 | 395 | <tr valign="top" class="whs15"> |
philpem@8 | 396 | <td colspan="1" rowspan="1" width="167px" class="whs18"> |
philpem@8 | 397 | <p class=Table>Enable Debug Interface</td> |
philpem@8 | 398 | <td colspan="1" rowspan="1" width="524px" class="whs21"> |
philpem@8 | 399 | <p class=Table>Includes the debugger stub in the CPU, which is required |
philpem@8 | 400 | for debugging.</td></tr> |
philpem@8 | 401 | |
philpem@8 | 402 | <tr valign="top" class="whs15"> |
philpem@8 | 403 | <td colspan="1" rowspan="1" width="167px" class="whs18"> |
philpem@8 | 404 | <p class=Table># of H/W Watchpoint Registers</td> |
philpem@8 | 405 | <td colspan="1" rowspan="1" width="524px" class="whs21"> |
philpem@8 | 406 | <p class=Table |
philpem@8 | 407 | style="font-weight: normal;">Specifies the number of hardware watchpoint |
philpem@8 | 408 | registers to be used in the debugging process.</td></tr> |
philpem@8 | 409 | |
philpem@8 | 410 | <tr valign="top" class="whs15"> |
philpem@8 | 411 | <td colspan="1" rowspan="1" width="167px" class="whs18"> |
philpem@8 | 412 | <p class=Table>Enable Debugging Code in Flash or ROM</td> |
philpem@8 | 413 | <td colspan="1" rowspan="1" width="524px" class="whs21"> |
philpem@8 | 414 | <p class=Table |
philpem@8 | 415 | style="font-weight: normal;">Enables you to set hardware breakpoints |
philpem@8 | 416 | in read-only memory.</td></tr> |
philpem@8 | 417 | |
philpem@8 | 418 | <tr valign="top" class="whs15"> |
philpem@8 | 419 | <td colspan="1" rowspan="1" width="167px" class="whs18"> |
philpem@8 | 420 | <p class=Table># of H/W Breakpoint Registers</td> |
philpem@8 | 421 | <td colspan="1" rowspan="1" width="524px" class="whs21"> |
philpem@8 | 422 | <p class=Table>Specifies the number of hardware breakpoint registers to |
philpem@8 | 423 | be used in the debugging process.</td></tr> |
philpem@8 | 424 | |
philpem@8 | 425 | <tr valign="top" class="whs15"> |
philpem@8 | 426 | <td colspan="1" rowspan="1" width="167px" class="whs18"> |
philpem@8 | 427 | <p class=Table>Enable PC Trace</td> |
philpem@8 | 428 | <td colspan="1" rowspan="1" width="524px" class="whs21"> |
philpem@8 | 429 | <p class=Table>Enables the Program Counter Trace feature, which enables |
philpem@8 | 430 | you to run the program trace during debug to find items in your C or C++ |
philpem@8 | 431 | Code during debug, such as breakpoints and exceptions. Refer to <span |
philpem@22 | 432 | style="font-weight: bold;"><B>Help > Help Contents > C/C++ SPE</B></span> |
philpem@22 | 433 | and <span style="font-weight: bold;"><B>Debug > Concepts > Program |
philpem@22 | 434 | Counter Trace</B></span> for more information on Program Counter Trace.</td></tr> |
philpem@8 | 435 | |
philpem@8 | 436 | <tr valign="top" class="whs15"> |
philpem@8 | 437 | <td colspan="1" rowspan="1" width="167px" class="whs18"> |
philpem@8 | 438 | <p class=Table>Trace Depth</td> |
philpem@8 | 439 | <td colspan="1" rowspan="1" width="524px" class="whs21"> |
philpem@8 | 440 | <p class=Table>Enables you to specify the depth of the Program Counter |
philpem@8 | 441 | Trace buffer. Refer to <span style="font-weight: bold;"><B>Help > Help |
philpem@22 | 442 | Contents > C/C++ SPE</B></span> and <span style="font-weight: bold;"><B>Debug |
philpem@22 | 443 | > Concepts > Program Counter Trace</B></span> for more information on |
philpem@22 | 444 | Program Counter Trace.</td></tr> |
philpem@8 | 445 | |
philpem@8 | 446 | <tr valign="top" class="whs15"> |
philpem@8 | 447 | <td colspan="2" rowspan="1" width="691px" class="whs20"> |
philpem@8 | 448 | <p class=Table |
philpem@8 | 449 | style="font-weight: bold;">Shifter Settings</td> |
philpem@8 | 450 | </tr> |
philpem@8 | 451 | |
philpem@8 | 452 | <tr valign="top" class="whs15"> |
philpem@8 | 453 | <td colspan="1" rowspan="1" width="167px" class="whs18"> |
philpem@8 | 454 | <p class=Table>Enable Piplined Barrel Shifter</td> |
philpem@8 | 455 | <td colspan="1" rowspan="1" width="524px" class="whs19"> |
philpem@8 | 456 | <p>Enables the barrel shifter to be pipelined. The barrel shifter is implemented |
philpem@8 | 457 | to perform a shift operation in three cycles.</td></tr> |
philpem@8 | 458 | |
philpem@8 | 459 | <tr valign="top" class="whs15"> |
philpem@8 | 460 | <td colspan="1" rowspan="1" width="167px" class="whs18"> |
philpem@8 | 461 | <p class=Table>Enable Multicycle Barrel Shifter (up to 32 cycles)</td> |
philpem@8 | 462 | <td colspan="1" rowspan="1" width="524px" class="whs19"> |
philpem@8 | 463 | <p>Enables multi-cycle shift operation for the barrel shifter. The barrel |
philpem@8 | 464 | shifter is implemented to shift one bit per cycle and take thirty-two |
philpem@8 | 465 | cycles to complete.</td></tr> |
philpem@8 | 466 | |
philpem@8 | 467 | <tr valign="top" class="whs15"> |
philpem@8 | 468 | <td colspan="2" rowspan="1" width="691px" class="whs20"> |
philpem@8 | 469 | <p class=Table><span style="font-weight: bold;"><B>Data Cache</B></span></td> |
philpem@8 | 470 | </tr> |
philpem@8 | 471 | |
philpem@8 | 472 | <tr valign="top" class="whs15"> |
philpem@8 | 473 | <td colspan="1" rowspan="1" width="167px" class="whs18"> |
philpem@8 | 474 | <p class=Table>Data Cache Enabled</td> |
philpem@8 | 475 | <td colspan="1" rowspan="1" width="524px" class="whs21"> |
philpem@8 | 476 | <p class=Table>Determines whether a data cache is implemented.</td></tr> |
philpem@8 | 477 | |
philpem@8 | 478 | <tr valign="top" class="whs15"> |
philpem@8 | 479 | <td colspan="1" rowspan="1" width="167px" class="whs18"> |
philpem@8 | 480 | <p class=Table>Number of Sets</td> |
philpem@8 | 481 | <td colspan="1" rowspan="1" width="524px" class="whs21"> |
philpem@8 | 482 | <p class=Table>Specifies the number of sets in the data cache. Supported |
philpem@8 | 483 | values are 128, 256, 512, 1024.</td></tr> |
philpem@8 | 484 | |
philpem@8 | 485 | <tr valign="top" class="whs15"> |
philpem@8 | 486 | <td colspan="1" rowspan="1" width="167px" class="whs18"> |
philpem@8 | 487 | <p class=Table>Set Associativity</td> |
philpem@8 | 488 | <td colspan="1" rowspan="1" width="524px" class="whs21"> |
philpem@8 | 489 | <p class=Table>Specifies the associativity of the data cache. Supported |
philpem@8 | 490 | values are 1, 2.</td></tr> |
philpem@8 | 491 | |
philpem@8 | 492 | <tr valign="top" class="whs15"> |
philpem@8 | 493 | <td colspan="1" rowspan="1" width="167px" class="whs18"> |
philpem@8 | 494 | <p class=Table>Bytes/Cache Line</td> |
philpem@8 | 495 | <td colspan="1" rowspan="1" width="524px" class="whs21"> |
philpem@8 | 496 | <p class=Table>Specifies the number of bytes per data cache line. Supported |
philpem@8 | 497 | values are 4, 8, 16.</td></tr> |
philpem@8 | 498 | |
philpem@8 | 499 | <tr valign="top" class="whs15"> |
philpem@8 | 500 | <td colspan="1" rowspan="1" width="167px" class="whs23"> |
philpem@8 | 501 | <p class=Table>Memory Type</td> |
philpem@8 | 502 | <td colspan="1" rowspan="1" width="524px" class="whs24"> |
philpem@8 | 503 | <p class=Table>Determines the FPGA resource to be used to implement the |
philpem@8 | 504 | data cache. The decision can be left to the synthesis tool (Auto), or |
philpem@8 | 505 | you can select from the following options:</p> |
philpem@8 | 506 | <ul> |
philpem@8 | 507 | |
philpem@8 | 508 | <li class=kadov-p-CBullet><p class=Bullet>Auto – |
philpem@8 | 509 | Leaves the implementation of the data cache to the synthesis tool.</p></li> |
philpem@8 | 510 | |
philpem@8 | 511 | <li class=kadov-p-CBullet><p class=Bullet>Distributed RAM – |
philpem@8 | 512 | Implements the data cache as distributed RAM.</p></li> |
philpem@8 | 513 | |
philpem@8 | 514 | <li class=kadov-p-CBullet><p class=Bullet>Dual-Port EBR – |
philpem@8 | 515 | Implements the data cache as dual-port EBR (two read/write ports).</p></li> |
philpem@8 | 516 | </ul></td></tr> |
philpem@8 | 517 | </table> |
philpem@8 | 518 | |
philpem@8 | 519 | <p> </p> |
philpem@8 | 520 | |
philpem@8 | 521 | <h2>Dialog Box Parameters – |
philpem@8 | 522 | Inline Memory Tab</h2> |
philpem@8 | 523 | |
philpem@8 | 524 | <table x-use-null-cells cellspacing="0" class="whs12"> |
philpem@8 | 525 | <col class="whs13"> |
philpem@8 | 526 | <col class="whs14"> |
philpem@8 | 527 | |
philpem@8 | 528 | <tr valign="top" class="whs15"> |
philpem@8 | 529 | <td bgcolor="#DEE8F4" width="167px" class="whs25"> |
philpem@8 | 530 | <p class=Table |
philpem@8 | 531 | style="font-weight: bold;">Parameter</td> |
philpem@8 | 532 | <td bgcolor="#DEE8F4" width="524px" class="whs26"> |
philpem@8 | 533 | <p class=Table |
philpem@8 | 534 | style="font-weight: bold;">Description</td></tr> |
philpem@8 | 535 | |
philpem@8 | 536 | <tr valign="top" class="whs15"> |
philpem@8 | 537 | <td rowspan="1" colspan="2" width="691px" class="whs27"> |
philpem@8 | 538 | <p class=Table |
philpem@8 | 539 | style="font-weight: bold;">Instruction Inline Memory</td> |
philpem@8 | 540 | </tr> |
philpem@8 | 541 | |
philpem@8 | 542 | <tr valign="top" class="whs15"> |
philpem@8 | 543 | <td width="167px" class="whs28"> |
philpem@8 | 544 | <p class=Table>Enable</td> |
philpem@8 | 545 | <td width="524px" class="whs29"> |
philpem@8 | 546 | <p class=Table>Enables the instruction inline memory</td></tr> |
philpem@8 | 547 | |
philpem@8 | 548 | <tr valign="top" class="whs15"> |
philpem@8 | 549 | <td width="167px" class="whs28"> |
philpem@8 | 550 | <p class=Table>Instance Name</td> |
philpem@8 | 551 | <td width="524px" class="whs29"> |
philpem@8 | 552 | <p class=Table>Specifics the name of the instruction inline memory. Alphanumeric |
philpem@8 | 553 | values and underscores are supported. The default is Instruction_IM.</td></tr> |
philpem@8 | 554 | |
philpem@8 | 555 | <tr valign="top" class="whs15"> |
philpem@8 | 556 | <td width="167px" class="whs28"> |
philpem@8 | 557 | <p class=Table>Base Address</td> |
philpem@8 | 558 | <td width="524px" class="whs29"> |
philpem@8 | 559 | <p class=Table>Specifies the base address for the instruction inline memory. |
philpem@8 | 560 | The default is 0x10000000.</td></tr> |
philpem@8 | 561 | |
philpem@8 | 562 | <tr valign="top" class="whs15"> |
philpem@8 | 563 | <td width="167px" class="whs28"> |
philpem@8 | 564 | <p class=Table>Size of Memory in Bytes</td> |
philpem@8 | 565 | <td width="524px" class="whs29"> |
philpem@8 | 566 | <p class=Table>Specifies the size of the instruction inline memory.</td></tr> |
philpem@8 | 567 | |
philpem@8 | 568 | <tr valign="top" class="whs15"> |
philpem@8 | 569 | <td rowspan="1" colspan="2" width="691px" class="whs27"> |
philpem@8 | 570 | <p class=Table><span style="font-weight: bold;"><B>Memory File</B></span></td> |
philpem@8 | 571 | </tr> |
philpem@8 | 572 | |
philpem@8 | 573 | <tr valign="top" class="whs15"> |
philpem@8 | 574 | <td width="167px" class="whs28"> |
philpem@8 | 575 | <p class=Table>Initialization File Name</td> |
philpem@8 | 576 | <td width="524px" class="whs29"> |
philpem@8 | 577 | <p class=Table>Specifies the name of the memory initialization file for |
philpem@8 | 578 | instruction inline memory.</td></tr> |
philpem@8 | 579 | |
philpem@8 | 580 | <tr valign="top" class="whs15"> |
philpem@8 | 581 | <td width="167px" class="whs28"> |
philpem@8 | 582 | <p class=Table>File Format</td> |
philpem@8 | 583 | <td width="524px" class="whs29"> |
philpem@8 | 584 | <p class=Table>Specifies the format of the memory initialization file: |
philpem@8 | 585 | hex or binary.</td></tr> |
philpem@8 | 586 | |
philpem@8 | 587 | <tr valign="top" class="whs15"> |
philpem@8 | 588 | <td rowspan="1" colspan="2" width="691px" class="whs27"> |
philpem@8 | 589 | <p class=Table |
philpem@8 | 590 | style="font-weight: bold;">Data Inline Memory</td> |
philpem@8 | 591 | </tr> |
philpem@8 | 592 | |
philpem@8 | 593 | <tr valign="top" class="whs15"> |
philpem@8 | 594 | <td width="167px" class="whs28"> |
philpem@8 | 595 | <p class=Table>Enabled</td> |
philpem@8 | 596 | <td width="524px" class="whs29"> |
philpem@8 | 597 | <p class=Table>Enables the data inline memory.</td></tr> |
philpem@8 | 598 | |
philpem@8 | 599 | <tr valign="top" class="whs15"> |
philpem@8 | 600 | <td width="167px" class="whs28"> |
philpem@8 | 601 | <p class=Table>Instance Name</td> |
philpem@8 | 602 | <td width="524px" class="whs29"> |
philpem@8 | 603 | <p class=Table>Specifies the name of the data inline memory. Alphanumeric |
philpem@8 | 604 | values and underscores are supported. The default is Data_IM.</td></tr> |
philpem@8 | 605 | |
philpem@8 | 606 | <tr valign="top" class="whs15"> |
philpem@8 | 607 | <td width="167px" class="whs28"> |
philpem@8 | 608 | <p class=Table>Base Address</td> |
philpem@8 | 609 | <td width="524px" class="whs29"> |
philpem@8 | 610 | <p class=Table>Specifies the base address for the data inline memory. The |
philpem@8 | 611 | default is 0x20000000.</td></tr> |
philpem@8 | 612 | |
philpem@8 | 613 | <tr valign="top" class="whs15"> |
philpem@8 | 614 | <td width="167px" class="whs28"> |
philpem@8 | 615 | <p class=Table>Size of Memory in Bytes</td> |
philpem@8 | 616 | <td width="524px" class="whs29"> |
philpem@8 | 617 | <p class=Table>Specifies the size of the data inline memory.</td></tr> |
philpem@8 | 618 | |
philpem@8 | 619 | <tr valign="top" class="whs15"> |
philpem@8 | 620 | <td colspan="2" rowspan="1" width="691px" class="whs27"> |
philpem@8 | 621 | <p class=Table |
philpem@8 | 622 | style="font-weight: bold;">Memory File</td> |
philpem@8 | 623 | </tr> |
philpem@8 | 624 | |
philpem@8 | 625 | <tr valign="top" class="whs15"> |
philpem@8 | 626 | <td colspan="1" rowspan="1" width="167px" class="whs28"> |
philpem@8 | 627 | <p class=Table>Initialization File Name</td> |
philpem@8 | 628 | <td colspan="1" rowspan="1" width="524px" class="whs29"> |
philpem@8 | 629 | <p class=Table>Specifies the name of the memory initialization file for |
philpem@8 | 630 | data inline memory.</td></tr> |
philpem@8 | 631 | |
philpem@8 | 632 | <tr valign="top" class="whs15"> |
philpem@8 | 633 | <td colspan="1" rowspan="1" width="167px" class="whs30"> |
philpem@8 | 634 | <p class=Table>File Format</td> |
philpem@8 | 635 | <td colspan="1" rowspan="1" width="524px" class="whs31"> |
philpem@8 | 636 | <p class=Table>Specifies the format of the memory initialization file: |
philpem@8 | 637 | hex or binary.</td></tr> |
philpem@8 | 638 | </table> |
philpem@8 | 639 | |
philpem@8 | 640 | <p> </p> |
philpem@8 | 641 | |
philpem@8 | 642 | <p>For the revision history of the component RTL files, refer to the header |
philpem@8 | 643 | of each component Verilog source file. </p> |
philpem@8 | 644 | |
philpem@8 | 645 | <p><span style="font-weight: bold;"><B>Note</B></span>: If the processor manual |
philpem@8 | 646 | fails to open, click <img src="qm_icon.jpg" x-maintain-ratio="TRUE" width="14px" height="16px" border="0" class="img_whs32"> on the Available Components toolbar, |
philpem@8 | 647 | and then click the note button.</p> |
philpem@8 | 648 | |
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