document/lm32.htm

Sat, 06 Aug 2011 01:33:43 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Sat, 06 Aug 2011 01:33:43 +0100
changeset 29
a82f6ed53fa6
parent 22
35dc7ba83714
permissions
-rwxr-xr-x

Update documents for LM32 V3.8

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philpem@8 130 <h1>LatticeMico32 Processor &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<a title="View Reference Manual" href="lm32_archman.pdf" target="_blank" onmouseover="if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) ehlp_showtip(this,event,'View Reference Manual');" onmouseout="if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) ehlp_hidetip();"><img src="ds_icon_ast.jpg" x-maintain-ratio="TRUE" width="29px" height="31px" border="0" class="img_whs1"></a></h1>
philpem@8 131
philpem@8 132 <p>The LatticeMico32 processor is a high-performance 32-bit microprocessor
philpem@8 133 optimized for Lattice Semiconductor field-programmable gate arrays. </p>
philpem@8 134
philpem@8 135 <p class="whs2"><span style="font-style: italic;"><I>*If the
philpem@8 136 processor manual fails to open, see the note at the bottom of this page.</I></span></p>
philpem@8 137
philpem@8 138 <h2>Revision History</h2>
philpem@8 139
philpem@8 140 <table x-use-null-cells cellspacing="0" width="738" height="84" class="whs3">
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philpem@8 144 <col class="whs4">
philpem@8 145 <col class="whs5">
philpem@8 146
philpem@8 147 <tr valign="top" class="whs6">
philpem@8 148 <td bgcolor="#DEE8F4" width="93px" class="whs7">
philpem@8 149 <p class=Table
philpem@8 150 style="font-weight: bold;">Version</td>
philpem@8 151 <td bgcolor="#DEE8F4" width="598px" class="whs8">
philpem@8 152 <p class=Table
philpem@8 153 style="font-weight: bold;">Description</td></tr>
philpem@29 154
philpem@29 155 <tr valign="top" class="whs6">
philpem@29 156 <td colspan="1" rowspan="1" width="93px" class="whs9">
philpem@29 157 <p class=Table
philpem@29 158 style="font-weight: normal;">3.8</td>
philpem@29 159 <td colspan="1" rowspan="1" width="598px" class="whs10">
philpem@29 160 <p class=whs10
philpem@29 161 style="margin-left: 0px;">Added feature to dynamically switch EBA to DEBA via an input pin 'at_debug'. </p>
philpem@29 162 <p class=whs10
philpem@29 163 style="margin-left: 0px;">Fixed bug that identified the wrong instruction on a data bus error.</td></tr>
philpem@29 164
philpem@8 165
philpem@8 166 <tr valign="top" class="whs6">
philpem@8 167 <td colspan="1" rowspan="1" width="93px" class="whs9">
philpem@8 168 <p class=Table
philpem@29 169 style="font-weight: normal;">3.7</td>
philpem@29 170 <td colspan="1" rowspan="1" width="598px" class="whs10">
philpem@29 171 <p class=whs10
philpem@29 172 style="margin-left: 0px;">Fixed bug with inline memories larger than 64 Kbytes.</td></tr>
philpem@29 173
philpem@29 174 <tr valign="top" class="whs6">
philpem@29 175 <td colspan="1" rowspan="1" width="93px" class="whs9">
philpem@29 176 <p class=Table
philpem@22 177 style="font-weight: normal;">3.6</td>
philpem@22 178 <td colspan="1" rowspan="1" width="598px" class="whs10">
philpem@22 179 <p class=whs10
philpem@22 180 style="margin-left: 0px;">Fixed the issue of the processor locking
philpem@22 181 up when Instruction Cache is not used.</td></tr>
philpem@22 182
philpem@22 183 <tr valign="top" class="whs6">
philpem@22 184 <td colspan="1" rowspan="1" width="93px" class="whs9">
philpem@22 185 <p class=Table
philpem@8 186 style="font-weight: normal;">3.5</td>
philpem@8 187 <td colspan="1" rowspan="1" width="598px" class="whs10">
philpem@8 188 <p class=whs10
philpem@8 189 style="margin-left: 0px;">Support added to allow Inline Memories to
philpem@8 190 be generated as non-power-of-two, as long as they are a multiple of 1024
philpem@8 191 bytes</td></tr>
philpem@8 192
philpem@8 193 <tr valign="top" class="whs6">
philpem@8 194 <td colspan="1" rowspan="1" width="93px" class="whs9">
philpem@8 195 <p class=Table
philpem@22 196 style="font-weight: normal;">3.4</td>
philpem@22 197 <td colspan="1" rowspan="1" width="598px" class="whs10">
philpem@22 198 <p class=whs10
philpem@22 199 style="margin-left: 0px;">Updated to support ispLEVER 7.2 SP1.</td></tr>
philpem@22 200
philpem@22 201 <tr valign="top" class="whs6">
philpem@22 202 <td colspan="1" rowspan="1" width="93px" class="whs9">
philpem@22 203 <p class=Table
philpem@8 204 style="font-weight: normal;">3.3</td>
philpem@8 205 <td colspan="1" rowspan="1" width="598px" class="whs10">
philpem@8 206 <p class=whs10
philpem@22 207 style="margin-left: 0px;">Updated to support ispLEVER 7.2.</p>
philpem@22 208 <p class=whs10
philpem@8 209 style="margin-left: 0px;">Added Inline Memory to support on-chip memory
philpem@8 210 connected through a local bus.</td></tr>
philpem@8 211
philpem@8 212 <tr valign="top" class="whs6">
philpem@8 213 <td colspan="1" rowspan="1" width="93px" class="whs9">
philpem@8 214 <p class=Table
philpem@8 215 style="font-weight: normal;">3.2</td>
philpem@8 216 <td colspan="1" rowspan="1" width="598px" class="whs10">
philpem@8 217 <p class=whs10
philpem@22 218 style="margin-left: 0px;">Updated to support ispLEVER 7.1 SP1</p>
philpem@22 219 <p class=whs10
philpem@8 220 style="margin-left: 0px;">Added Memory Type to instruction cache and
philpem@8 221 data cache.</td></tr>
philpem@8 222
philpem@8 223 <tr valign="top" class="whs6">
philpem@8 224 <td colspan="1" rowspan="1" width="93px" class="whs9">
philpem@8 225 <p class=Table
philpem@8 226 style="font-weight: normal;">3.1</td>
philpem@8 227 <td colspan="1" rowspan="1" width="598px" class="whs10">
philpem@22 228 <p class="whs11">Updated to support ispLEVER 7.1.</p>
philpem@8 229 <p class="whs11">Added static predictor to improve the behavior
philpem@8 230 of branches.</p>
philpem@8 231 <p class="whs11">Added support for optionally mapping the register
philpem@8 232 file to EBRs (on-chip memory).</p>
philpem@8 233 <p class="whs11">Added support for selecting between distributed
philpem@8 234 RAM and EBRs (pseudo-dual port or true-dual port) for instruction and
philpem@8 235 data caches.</td></tr>
philpem@8 236
philpem@8 237 <tr valign="top" class="whs6">
philpem@8 238 <td colspan="1" rowspan="1" width="93px" class="whs9">
philpem@8 239 <p class=Table
philpem@8 240 style="font-weight: normal;"><span style="font-weight: normal;">3.0
philpem@22 241 (7.0 SP2)</span></td>
philpem@8 242 <td colspan="1" rowspan="1" width="598px" class="whs10">
philpem@22 243 <p class="whs11">Updated to support ispLEVER 7.0 SP2.</p>
philpem@8 244 <p class="whs11">Fixed incorrect handling of data cache miss
philpem@8 245 in the presence of an instruction cache miss.</td></tr>
philpem@8 246
philpem@8 247 <tr valign="top" class="whs6">
philpem@8 248 <td colspan="1" rowspan="1" width="93px" class="whs9">
philpem@8 249 <p class="whs11">1.0</td>
philpem@8 250 <td colspan="1" rowspan="1" width="598px" class="whs10">
philpem@8 251 <p class="whs11">Initial version.</td></tr>
philpem@8 252 <script language='JavaScript'><!--
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philpem@8 255 </table>
philpem@8 256
philpem@8 257 &nbsp;
philpem@8 258
philpem@8 259 <h2>Dialog Box Parameters &#8211;
philpem@8 260 General Tab</h2>
philpem@8 261
philpem@8 262 <table x-use-null-cells cellspacing="0" class="whs12">
philpem@8 263 <col class="whs13">
philpem@8 264 <col class="whs14">
philpem@8 265
philpem@8 266 <tr valign="top" class="whs15">
philpem@8 267 <td bgcolor="#DEE8F4" width="167px" class="whs16">
philpem@8 268 <p class=Table
philpem@8 269 style="font-weight: bold;">Parameter</td>
philpem@8 270 <td bgcolor="#DEE8F4" width="524px" class="whs17">
philpem@8 271 <p class=Table
philpem@8 272 style="font-weight: bold;">Description</td></tr>
philpem@8 273
philpem@8 274 <tr valign="top" class="whs15">
philpem@8 275 <td colspan="1" rowspan="1" width="167px" class="whs18">
philpem@8 276 <p class=Table
philpem@8 277 style="font-weight: normal;">Instance Name</td>
philpem@8 278 <td colspan="1" rowspan="1" width="524px" class="whs19">
philpem@8 279 <p class=Table
philpem@8 280 style="margin-left: 14px;">Specifies the name of the LatticeMico32
philpem@8 281 processor. Alphanumeric values and underscores are supported. The default
philpem@8 282 is LM32.</td></tr>
philpem@8 283
philpem@8 284 <tr valign="top" class="whs15">
philpem@8 285 <td colspan="2" rowspan="1" width="691px" class="whs20">
philpem@8 286 <p class=Table
philpem@8 287 style="font-weight: bold;">Settings</td>
philpem@8 288 </tr>
philpem@8 289
philpem@8 290 <tr valign="top" class="whs15">
philpem@8 291 <td colspan="1" rowspan="1" width="167px" class="whs18">
philpem@8 292 <p class=Table>Use EBRs for Register File</td>
philpem@8 293 <td colspan="1" rowspan="1" width="524px" class="whs21">
philpem@8 294 <p class=Table>Uses embedded block RAMS for the register file.</td></tr>
philpem@8 295
philpem@8 296 <tr valign="top" class="whs15">
philpem@8 297 <td colspan="1" rowspan="1" width="167px" class="whs18">
philpem@8 298 <p class=Table>Enable Divide</td>
philpem@8 299 <td colspan="1" rowspan="1" width="524px" class="whs21">
philpem@8 300 <p class=Table>Enables the divide and modulus instructions (<span style="font-family: Verdana, sans-serif;">divu,
philpem@8 301 modu</span>).</td></tr>
philpem@8 302
philpem@8 303 <tr valign="top" class="whs15">
philpem@8 304 <td colspan="1" rowspan="1" width="167px" class="whs18">
philpem@8 305 <p class=Table>Enable Sign Extend</td>
philpem@8 306 <td colspan="1" rowspan="1" width="524px" class="whs21">
philpem@8 307 <p class=Table>Enables the sign-extension instructions (<span style="font-family: Verdana, sans-serif;">sextb,
philpem@8 308 sexth</span><span style="font-family: Arial, sans-serif;">)</span>.</td></tr>
philpem@8 309
philpem@8 310 <tr valign="top" class="whs15">
philpem@8 311 <td colspan="1" rowspan="1" width="167px" class="whs18">
philpem@8 312 <p class=Table>Location of Exception Handlers</td>
philpem@8 313 <td colspan="1" rowspan="1" width="524px" class="whs21">
philpem@8 314 <p class=Table>Specifies the default value for the vector table. This can
philpem@8 315 be changed by updating the EBA control register or status register.</p>
philpem@8 316 <p class=Table>This address must be aligned to a 256-byte boundary, since
philpem@8 317 the hardware ignores the least-significant byte. Unpredictable behavior
philpem@8 318 occurs when the exception base address and the exception vectors are not
philpem@8 319 aligned on a 256-byte boundary.</td></tr>
philpem@8 320
philpem@8 321 <tr valign="top" class="whs15">
philpem@8 322 <td colspan="2" rowspan="1" width="691px" class="whs20">
philpem@8 323 <p class=Table
philpem@8 324 style="font-weight: bold;">Multiplier Settings</td>
philpem@8 325 </tr>
philpem@8 326
philpem@8 327 <tr valign="top" class="whs15">
philpem@8 328 <td colspan="1" rowspan="1" width="167px" class="whs18">
philpem@8 329 <p class=Table>Enable Multiplier</td>
philpem@8 330 <td colspan="1" rowspan="1" width="524px" class="whs21">
philpem@8 331 <p class=Table>Enables the multiply instructions (<span style="font-family: Verdana, sans-serif;">mul,
philpem@8 332 muli)</span>.</td></tr>
philpem@8 333
philpem@8 334 <tr valign="top" class="whs15">
philpem@8 335 <td colspan="1" rowspan="1" width="167px" class="whs18">
philpem@8 336 <p class=Table>Enable Pipelined Multiplier (DSP Block if available)</td>
philpem@8 337 <td colspan="1" rowspan="1" width="524px" class="whs21">
philpem@8 338 <p class=Table>Enables the multiplier using the DSP block, if available.</td></tr>
philpem@8 339
philpem@8 340 <tr valign="top" class="whs15">
philpem@8 341 <td colspan="1" rowspan="1" width="167px" class="whs18">
philpem@8 342 <p class=Table>Enable Multicycle (LUT-based, 32 cycles) Multiplier</td>
philpem@8 343 <td colspan="1" rowspan="1" width="524px" class="whs21">
philpem@8 344 <p class=Table>Enables the multiplier using LUTs.</td></tr>
philpem@8 345
philpem@8 346 <tr valign="top" class="whs15">
philpem@8 347 <td colspan="2" rowspan="1" width="691px" class="whs20">
philpem@8 348 <p class=Table
philpem@8 349 style="font-weight: bold;">Instruction Cache</td>
philpem@8 350 </tr>
philpem@8 351
philpem@8 352 <tr valign="top" class="whs15">
philpem@8 353 <td colspan="1" rowspan="1" width="167px" class="whs18">
philpem@8 354 <p class=Table>Instruction Cache Enabled</td>
philpem@8 355 <td colspan="1" rowspan="1" width="524px" class="whs19">
philpem@8 356 <p class=Table
philpem@8 357 style="margin-left: 14px;">Determines whether an instruction cache
philpem@8 358 is implemented.</td></tr>
philpem@8 359
philpem@8 360 <tr valign="top" class="whs15">
philpem@8 361 <td colspan="1" rowspan="1" width="167px" class="whs18">
philpem@8 362 <p class=Table>Number of Sets</td>
philpem@8 363 <td colspan="1" rowspan="1" width="524px" class="whs19">
philpem@8 364 <p class=Table
philpem@8 365 style="margin-left: 14px;">Specifies the number of sets in the instruction
philpem@8 366 cache. Supported values are 128, 256, 512, 1024.</td></tr>
philpem@8 367
philpem@8 368 <tr valign="top" class="whs15">
philpem@8 369 <td colspan="1" rowspan="1" width="167px" class="whs18">
philpem@8 370 <p class=Table>Set Associativity</td>
philpem@8 371 <td colspan="1" rowspan="1" width="524px" class="whs19">
philpem@8 372 <p class=Table
philpem@8 373 style="margin-left: 14px;">Specifies the associativity of the instruction
philpem@8 374 cache. Supported values are 1, 2.</td></tr>
philpem@8 375
philpem@8 376 <tr valign="top" class="whs15">
philpem@8 377 <td colspan="1" rowspan="1" width="167px" class="whs18">
philpem@8 378 <p class=Table>Bytes/Cache Line</td>
philpem@8 379 <td colspan="1" rowspan="1" width="524px" class="whs19">
philpem@8 380 <p class=Table
philpem@8 381 style="margin-left: 15px;">Specifies the number of bytes per instruction
philpem@8 382 cache line. Supported values are 4, 8, 16.</td></tr>
philpem@8 383
philpem@8 384 <tr valign="top" class="whs15">
philpem@8 385 <td colspan="1" rowspan="1" width="167px" class="whs18">
philpem@8 386 <p class=Table>Memory Type</td>
philpem@8 387 <td colspan="1" rowspan="1" width="524px" class="whs19">
philpem@8 388 <p class=Table
philpem@8 389 style="margin-left: 15px;">Determines the FPGA resource to be used
philpem@8 390 to implement the instruction cache. The decision can be left to the synthesis
philpem@8 391 tool (Auto), or you can select from the following options:</p>
philpem@8 392 <ul type="disc" class="whs22">
philpem@8 393
philpem@8 394 <li class=kadov-p-CBullet><p class=Bullet>Auto &#8211;
philpem@8 395 Leaves the implementation of the instruction cache to the synthesis tool.</p></li>
philpem@8 396
philpem@8 397 <li class=kadov-p-CBullet><p class=Bullet>Distributed RAM &#8211;
philpem@8 398 Implements the instruction cache as distributed RAM.</p></li>
philpem@8 399
philpem@8 400 <li class=kadov-p-CBullet><p class=Bullet>Dual-Port EBR &#8211;
philpem@8 401 Implements the instruction cache as dual-port EBR (two read/write ports).</p></li>
philpem@8 402
philpem@8 403 <li class=kadov-p-CBullet><p class=Bullet>Pseudo Dual-Port EBR &#8211; Implements
philpem@8 404 the instruction cache as pseudo-dual-port EBR (one read port and one write
philpem@8 405 port). </p></li>
philpem@8 406 </ul></td></tr>
philpem@8 407
philpem@8 408 <tr valign="top" class="whs15">
philpem@8 409 <td colspan="2" rowspan="1" width="691px" class="whs20">
philpem@8 410 <p class=Table
philpem@8 411 style="font-weight: bold;">Debug Setting</td>
philpem@8 412 </tr>
philpem@8 413
philpem@8 414 <tr valign="top" class="whs15">
philpem@8 415 <td colspan="1" rowspan="1" width="167px" class="whs18">
philpem@8 416 <p class=Table>Enable Debug Interface</td>
philpem@8 417 <td colspan="1" rowspan="1" width="524px" class="whs21">
philpem@8 418 <p class=Table>Includes the debugger stub in the CPU, which is required
philpem@8 419 for debugging.</td></tr>
philpem@8 420
philpem@8 421 <tr valign="top" class="whs15">
philpem@8 422 <td colspan="1" rowspan="1" width="167px" class="whs18">
philpem@8 423 <p class=Table># of H/W Watchpoint Registers</td>
philpem@8 424 <td colspan="1" rowspan="1" width="524px" class="whs21">
philpem@8 425 <p class=Table
philpem@8 426 style="font-weight: normal;">Specifies the number of hardware watchpoint
philpem@8 427 registers to be used in the debugging process.</td></tr>
philpem@8 428
philpem@8 429 <tr valign="top" class="whs15">
philpem@8 430 <td colspan="1" rowspan="1" width="167px" class="whs18">
philpem@8 431 <p class=Table>Enable Debugging Code in Flash or ROM</td>
philpem@8 432 <td colspan="1" rowspan="1" width="524px" class="whs21">
philpem@8 433 <p class=Table
philpem@8 434 style="font-weight: normal;">Enables you to set hardware breakpoints
philpem@8 435 in read-only memory.</td></tr>
philpem@8 436
philpem@8 437 <tr valign="top" class="whs15">
philpem@8 438 <td colspan="1" rowspan="1" width="167px" class="whs18">
philpem@8 439 <p class=Table># of H/W Breakpoint Registers</td>
philpem@8 440 <td colspan="1" rowspan="1" width="524px" class="whs21">
philpem@8 441 <p class=Table>Specifies the number of hardware breakpoint registers to
philpem@8 442 be used in the debugging process.</td></tr>
philpem@8 443
philpem@8 444 <tr valign="top" class="whs15">
philpem@8 445 <td colspan="1" rowspan="1" width="167px" class="whs18">
philpem@8 446 <p class=Table>Enable PC Trace</td>
philpem@8 447 <td colspan="1" rowspan="1" width="524px" class="whs21">
philpem@8 448 <p class=Table>Enables the Program Counter Trace feature, which enables
philpem@8 449 you to run the program trace during debug to find items in your C or C++
philpem@8 450 Code during debug, such as breakpoints and exceptions. Refer to <span
philpem@22 451 style="font-weight: bold;"><B>Help &gt; Help Contents &gt; C/C++ SPE</B></span>
philpem@22 452 and <span style="font-weight: bold;"><B>Debug &gt; Concepts &gt; Program
philpem@22 453 Counter Trace</B></span> for more information on Program Counter Trace.</td></tr>
philpem@8 454
philpem@8 455 <tr valign="top" class="whs15">
philpem@8 456 <td colspan="1" rowspan="1" width="167px" class="whs18">
philpem@8 457 <p class=Table>Trace Depth</td>
philpem@8 458 <td colspan="1" rowspan="1" width="524px" class="whs21">
philpem@8 459 <p class=Table>Enables you to specify the depth of the Program Counter
philpem@8 460 Trace buffer. Refer to <span style="font-weight: bold;"><B>Help &gt; Help
philpem@22 461 Contents &gt; C/C++ SPE</B></span> and <span style="font-weight: bold;"><B>Debug
philpem@22 462 &gt; Concepts &gt; Program Counter Trace</B></span> for more information on
philpem@22 463 Program Counter Trace.</td></tr>
philpem@29 464
philpem@29 465 <tr valign="top" class="whs15">
philpem@29 466 <td colspan="1" rowspan="1" width="167px" class="whs18">
philpem@29 467 <p class=Table>Enable Dynamic Mapping of Exception Handlers to Debugger</td>
philpem@29 468 <td colspan="1" rowspan="1" width="524px" class="whs21">
philpem@29 469 <p class=Table>This option gives the designer the ability to dynamically change EBA to debug stub by asserting an LM32 GPIO pin named at_debug. This pin is exposed to the design only when this option is enabled. Allowable values are 0 = EBA and 1 = DEBA.
philpem@29 470 </td></tr>
philpem@8 471
philpem@8 472 <tr valign="top" class="whs15">
philpem@8 473 <td colspan="2" rowspan="1" width="691px" class="whs20">
philpem@8 474 <p class=Table
philpem@8 475 style="font-weight: bold;">Shifter Settings</td>
philpem@8 476 </tr>
philpem@8 477
philpem@8 478 <tr valign="top" class="whs15">
philpem@8 479 <td colspan="1" rowspan="1" width="167px" class="whs18">
philpem@8 480 <p class=Table>Enable Piplined Barrel Shifter</td>
philpem@8 481 <td colspan="1" rowspan="1" width="524px" class="whs19">
philpem@8 482 <p>Enables the barrel shifter to be pipelined. The barrel shifter is implemented
philpem@8 483 to perform a shift operation in three cycles.</td></tr>
philpem@8 484
philpem@8 485 <tr valign="top" class="whs15">
philpem@8 486 <td colspan="1" rowspan="1" width="167px" class="whs18">
philpem@8 487 <p class=Table>Enable Multicycle Barrel Shifter (up to 32 cycles)</td>
philpem@8 488 <td colspan="1" rowspan="1" width="524px" class="whs19">
philpem@8 489 <p>Enables multi-cycle shift operation for the barrel shifter. The barrel
philpem@8 490 shifter is implemented to shift one bit per cycle and take thirty-two
philpem@8 491 cycles to complete.</td></tr>
philpem@8 492
philpem@8 493 <tr valign="top" class="whs15">
philpem@8 494 <td colspan="2" rowspan="1" width="691px" class="whs20">
philpem@8 495 <p class=Table><span style="font-weight: bold;"><B>Data Cache</B></span></td>
philpem@8 496 </tr>
philpem@8 497
philpem@8 498 <tr valign="top" class="whs15">
philpem@8 499 <td colspan="1" rowspan="1" width="167px" class="whs18">
philpem@8 500 <p class=Table>Data Cache Enabled</td>
philpem@8 501 <td colspan="1" rowspan="1" width="524px" class="whs21">
philpem@8 502 <p class=Table>Determines whether a data cache is implemented.</td></tr>
philpem@8 503
philpem@8 504 <tr valign="top" class="whs15">
philpem@8 505 <td colspan="1" rowspan="1" width="167px" class="whs18">
philpem@8 506 <p class=Table>Number of Sets</td>
philpem@8 507 <td colspan="1" rowspan="1" width="524px" class="whs21">
philpem@8 508 <p class=Table>Specifies the number of sets in the data cache. Supported
philpem@8 509 values are 128, 256, 512, 1024.</td></tr>
philpem@8 510
philpem@8 511 <tr valign="top" class="whs15">
philpem@8 512 <td colspan="1" rowspan="1" width="167px" class="whs18">
philpem@8 513 <p class=Table>Set Associativity</td>
philpem@8 514 <td colspan="1" rowspan="1" width="524px" class="whs21">
philpem@8 515 <p class=Table>Specifies the associativity of the data cache. Supported
philpem@8 516 values are 1, 2.</td></tr>
philpem@8 517
philpem@8 518 <tr valign="top" class="whs15">
philpem@8 519 <td colspan="1" rowspan="1" width="167px" class="whs18">
philpem@8 520 <p class=Table>Bytes/Cache Line</td>
philpem@8 521 <td colspan="1" rowspan="1" width="524px" class="whs21">
philpem@8 522 <p class=Table>Specifies the number of bytes per data cache line. Supported
philpem@8 523 values are 4, 8, 16.</td></tr>
philpem@8 524
philpem@8 525 <tr valign="top" class="whs15">
philpem@8 526 <td colspan="1" rowspan="1" width="167px" class="whs23">
philpem@8 527 <p class=Table>Memory Type</td>
philpem@8 528 <td colspan="1" rowspan="1" width="524px" class="whs24">
philpem@8 529 <p class=Table>Determines the FPGA resource to be used to implement the
philpem@8 530 data cache. The decision can be left to the synthesis tool (Auto), or
philpem@8 531 you can select from the following options:</p>
philpem@8 532 <ul>
philpem@8 533
philpem@8 534 <li class=kadov-p-CBullet><p class=Bullet>Auto &#8211;
philpem@8 535 Leaves the implementation of the data cache to the synthesis tool.</p></li>
philpem@8 536
philpem@8 537 <li class=kadov-p-CBullet><p class=Bullet>Distributed RAM &#8211;
philpem@8 538 Implements the data cache as distributed RAM.</p></li>
philpem@8 539
philpem@8 540 <li class=kadov-p-CBullet><p class=Bullet>Dual-Port EBR &#8211;
philpem@8 541 Implements the data cache as dual-port EBR (two read/write ports).</p></li>
philpem@8 542 </ul></td></tr>
philpem@8 543 </table>
philpem@8 544
philpem@8 545 <p>&nbsp;</p>
philpem@8 546
philpem@8 547 <h2>Dialog Box Parameters &#8211;
philpem@8 548 Inline Memory Tab</h2>
philpem@8 549
philpem@8 550 <table x-use-null-cells cellspacing="0" class="whs12">
philpem@8 551 <col class="whs13">
philpem@8 552 <col class="whs14">
philpem@8 553
philpem@8 554 <tr valign="top" class="whs15">
philpem@8 555 <td bgcolor="#DEE8F4" width="167px" class="whs25">
philpem@8 556 <p class=Table
philpem@8 557 style="font-weight: bold;">Parameter</td>
philpem@8 558 <td bgcolor="#DEE8F4" width="524px" class="whs26">
philpem@8 559 <p class=Table
philpem@8 560 style="font-weight: bold;">Description</td></tr>
philpem@8 561
philpem@8 562 <tr valign="top" class="whs15">
philpem@8 563 <td rowspan="1" colspan="2" width="691px" class="whs27">
philpem@8 564 <p class=Table
philpem@8 565 style="font-weight: bold;">Instruction Inline Memory</td>
philpem@8 566 </tr>
philpem@8 567
philpem@8 568 <tr valign="top" class="whs15">
philpem@8 569 <td width="167px" class="whs28">
philpem@8 570 <p class=Table>Enable</td>
philpem@8 571 <td width="524px" class="whs29">
philpem@8 572 <p class=Table>Enables the instruction inline memory</td></tr>
philpem@8 573
philpem@8 574 <tr valign="top" class="whs15">
philpem@8 575 <td width="167px" class="whs28">
philpem@8 576 <p class=Table>Instance Name</td>
philpem@8 577 <td width="524px" class="whs29">
philpem@8 578 <p class=Table>Specifics the name of the instruction inline memory. Alphanumeric
philpem@8 579 values and underscores are supported. The default is Instruction_IM.</td></tr>
philpem@8 580
philpem@8 581 <tr valign="top" class="whs15">
philpem@8 582 <td width="167px" class="whs28">
philpem@8 583 <p class=Table>Base Address</td>
philpem@8 584 <td width="524px" class="whs29">
philpem@8 585 <p class=Table>Specifies the base address for the instruction inline memory.
philpem@8 586 The default is 0x10000000.</td></tr>
philpem@8 587
philpem@8 588 <tr valign="top" class="whs15">
philpem@8 589 <td width="167px" class="whs28">
philpem@8 590 <p class=Table>Size of Memory in Bytes</td>
philpem@8 591 <td width="524px" class="whs29">
philpem@8 592 <p class=Table>Specifies the size of the instruction inline memory.</td></tr>
philpem@8 593
philpem@8 594 <tr valign="top" class="whs15">
philpem@8 595 <td rowspan="1" colspan="2" width="691px" class="whs27">
philpem@8 596 <p class=Table><span style="font-weight: bold;"><B>Memory File</B></span></td>
philpem@8 597 </tr>
philpem@8 598
philpem@8 599 <tr valign="top" class="whs15">
philpem@8 600 <td width="167px" class="whs28">
philpem@8 601 <p class=Table>Initialization File Name</td>
philpem@8 602 <td width="524px" class="whs29">
philpem@8 603 <p class=Table>Specifies the name of the memory initialization file for
philpem@8 604 instruction inline memory.</td></tr>
philpem@8 605
philpem@8 606 <tr valign="top" class="whs15">
philpem@8 607 <td width="167px" class="whs28">
philpem@8 608 <p class=Table>File Format</td>
philpem@8 609 <td width="524px" class="whs29">
philpem@8 610 <p class=Table>Specifies the format of the memory initialization file:
philpem@8 611 hex or binary.</td></tr>
philpem@8 612
philpem@8 613 <tr valign="top" class="whs15">
philpem@8 614 <td rowspan="1" colspan="2" width="691px" class="whs27">
philpem@8 615 <p class=Table
philpem@8 616 style="font-weight: bold;">Data Inline Memory</td>
philpem@8 617 </tr>
philpem@8 618
philpem@8 619 <tr valign="top" class="whs15">
philpem@8 620 <td width="167px" class="whs28">
philpem@8 621 <p class=Table>Enabled</td>
philpem@8 622 <td width="524px" class="whs29">
philpem@8 623 <p class=Table>Enables the data inline memory.</td></tr>
philpem@8 624
philpem@8 625 <tr valign="top" class="whs15">
philpem@8 626 <td width="167px" class="whs28">
philpem@8 627 <p class=Table>Instance Name</td>
philpem@8 628 <td width="524px" class="whs29">
philpem@8 629 <p class=Table>Specifies the name of the data inline memory. Alphanumeric
philpem@8 630 values and underscores are supported. The default is Data_IM.</td></tr>
philpem@8 631
philpem@8 632 <tr valign="top" class="whs15">
philpem@8 633 <td width="167px" class="whs28">
philpem@8 634 <p class=Table>Base Address</td>
philpem@8 635 <td width="524px" class="whs29">
philpem@8 636 <p class=Table>Specifies the base address for the data inline memory. The
philpem@8 637 default is 0x20000000.</td></tr>
philpem@8 638
philpem@8 639 <tr valign="top" class="whs15">
philpem@8 640 <td width="167px" class="whs28">
philpem@8 641 <p class=Table>Size of Memory in Bytes</td>
philpem@8 642 <td width="524px" class="whs29">
philpem@8 643 <p class=Table>Specifies the size of the data inline memory.</td></tr>
philpem@8 644
philpem@8 645 <tr valign="top" class="whs15">
philpem@8 646 <td colspan="2" rowspan="1" width="691px" class="whs27">
philpem@8 647 <p class=Table
philpem@8 648 style="font-weight: bold;">Memory File</td>
philpem@8 649 </tr>
philpem@8 650
philpem@8 651 <tr valign="top" class="whs15">
philpem@8 652 <td colspan="1" rowspan="1" width="167px" class="whs28">
philpem@8 653 <p class=Table>Initialization File Name</td>
philpem@8 654 <td colspan="1" rowspan="1" width="524px" class="whs29">
philpem@8 655 <p class=Table>Specifies the name of the memory initialization file for
philpem@8 656 data inline memory.</td></tr>
philpem@8 657
philpem@8 658 <tr valign="top" class="whs15">
philpem@8 659 <td colspan="1" rowspan="1" width="167px" class="whs30">
philpem@8 660 <p class=Table>File Format</td>
philpem@8 661 <td colspan="1" rowspan="1" width="524px" class="whs31">
philpem@8 662 <p class=Table>Specifies the format of the memory initialization file:
philpem@8 663 hex or binary.</td></tr>
philpem@8 664 </table>
philpem@8 665
philpem@8 666 <p>&nbsp;</p>
philpem@8 667
philpem@8 668 <p>For the revision history of the component RTL files, refer to the header
philpem@8 669 of each component Verilog source file. </p>
philpem@8 670
philpem@8 671 <p><span style="font-weight: bold;"><B>Note</B></span>: If the processor manual
philpem@8 672 fails to open, click <img src="qm_icon.jpg" x-maintain-ratio="TRUE" width="14px" height="16px" border="0" class="img_whs32"> on the Available Components toolbar,
philpem@8 673 and then click the note button.</p>
philpem@8 674
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