Sat, 06 Aug 2011 01:33:43 +0100
Update documents for LM32 V3.8
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130 <h1>LatticeMico32 Processor <a title="View Reference Manual" href="lm32_archman.pdf" target="_blank" onmouseover="if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) ehlp_showtip(this,event,'View Reference Manual');" onmouseout="if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) ehlp_hidetip();"><img src="ds_icon_ast.jpg" x-maintain-ratio="TRUE" width="29px" height="31px" border="0" class="img_whs1"></a></h1>
132 <p>The LatticeMico32 processor is a high-performance 32-bit microprocessor
133 optimized for Lattice Semiconductor field-programmable gate arrays. </p>
135 <p class="whs2"><span style="font-style: italic;"><I>*If the
136 processor manual fails to open, see the note at the bottom of this page.</I></span></p>
138 <h2>Revision History</h2>
140 <table x-use-null-cells cellspacing="0" width="738" height="84" class="whs3">
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143 //--></script>
144 <col class="whs4">
145 <col class="whs5">
147 <tr valign="top" class="whs6">
148 <td bgcolor="#DEE8F4" width="93px" class="whs7">
149 <p class=Table
150 style="font-weight: bold;">Version</td>
151 <td bgcolor="#DEE8F4" width="598px" class="whs8">
152 <p class=Table
153 style="font-weight: bold;">Description</td></tr>
155 <tr valign="top" class="whs6">
156 <td colspan="1" rowspan="1" width="93px" class="whs9">
157 <p class=Table
158 style="font-weight: normal;">3.8</td>
159 <td colspan="1" rowspan="1" width="598px" class="whs10">
160 <p class=whs10
161 style="margin-left: 0px;">Added feature to dynamically switch EBA to DEBA via an input pin 'at_debug'. </p>
162 <p class=whs10
163 style="margin-left: 0px;">Fixed bug that identified the wrong instruction on a data bus error.</td></tr>
166 <tr valign="top" class="whs6">
167 <td colspan="1" rowspan="1" width="93px" class="whs9">
168 <p class=Table
169 style="font-weight: normal;">3.7</td>
170 <td colspan="1" rowspan="1" width="598px" class="whs10">
171 <p class=whs10
172 style="margin-left: 0px;">Fixed bug with inline memories larger than 64 Kbytes.</td></tr>
174 <tr valign="top" class="whs6">
175 <td colspan="1" rowspan="1" width="93px" class="whs9">
176 <p class=Table
177 style="font-weight: normal;">3.6</td>
178 <td colspan="1" rowspan="1" width="598px" class="whs10">
179 <p class=whs10
180 style="margin-left: 0px;">Fixed the issue of the processor locking
181 up when Instruction Cache is not used.</td></tr>
183 <tr valign="top" class="whs6">
184 <td colspan="1" rowspan="1" width="93px" class="whs9">
185 <p class=Table
186 style="font-weight: normal;">3.5</td>
187 <td colspan="1" rowspan="1" width="598px" class="whs10">
188 <p class=whs10
189 style="margin-left: 0px;">Support added to allow Inline Memories to
190 be generated as non-power-of-two, as long as they are a multiple of 1024
191 bytes</td></tr>
193 <tr valign="top" class="whs6">
194 <td colspan="1" rowspan="1" width="93px" class="whs9">
195 <p class=Table
196 style="font-weight: normal;">3.4</td>
197 <td colspan="1" rowspan="1" width="598px" class="whs10">
198 <p class=whs10
199 style="margin-left: 0px;">Updated to support ispLEVER 7.2 SP1.</td></tr>
201 <tr valign="top" class="whs6">
202 <td colspan="1" rowspan="1" width="93px" class="whs9">
203 <p class=Table
204 style="font-weight: normal;">3.3</td>
205 <td colspan="1" rowspan="1" width="598px" class="whs10">
206 <p class=whs10
207 style="margin-left: 0px;">Updated to support ispLEVER 7.2.</p>
208 <p class=whs10
209 style="margin-left: 0px;">Added Inline Memory to support on-chip memory
210 connected through a local bus.</td></tr>
212 <tr valign="top" class="whs6">
213 <td colspan="1" rowspan="1" width="93px" class="whs9">
214 <p class=Table
215 style="font-weight: normal;">3.2</td>
216 <td colspan="1" rowspan="1" width="598px" class="whs10">
217 <p class=whs10
218 style="margin-left: 0px;">Updated to support ispLEVER 7.1 SP1</p>
219 <p class=whs10
220 style="margin-left: 0px;">Added Memory Type to instruction cache and
221 data cache.</td></tr>
223 <tr valign="top" class="whs6">
224 <td colspan="1" rowspan="1" width="93px" class="whs9">
225 <p class=Table
226 style="font-weight: normal;">3.1</td>
227 <td colspan="1" rowspan="1" width="598px" class="whs10">
228 <p class="whs11">Updated to support ispLEVER 7.1.</p>
229 <p class="whs11">Added static predictor to improve the behavior
230 of branches.</p>
231 <p class="whs11">Added support for optionally mapping the register
232 file to EBRs (on-chip memory).</p>
233 <p class="whs11">Added support for selecting between distributed
234 RAM and EBRs (pseudo-dual port or true-dual port) for instruction and
235 data caches.</td></tr>
237 <tr valign="top" class="whs6">
238 <td colspan="1" rowspan="1" width="93px" class="whs9">
239 <p class=Table
240 style="font-weight: normal;"><span style="font-weight: normal;">3.0
241 (7.0 SP2)</span></td>
242 <td colspan="1" rowspan="1" width="598px" class="whs10">
243 <p class="whs11">Updated to support ispLEVER 7.0 SP2.</p>
244 <p class="whs11">Fixed incorrect handling of data cache miss
245 in the presence of an instruction cache miss.</td></tr>
247 <tr valign="top" class="whs6">
248 <td colspan="1" rowspan="1" width="93px" class="whs9">
249 <p class="whs11">1.0</td>
250 <td colspan="1" rowspan="1" width="598px" class="whs10">
251 <p class="whs11">Initial version.</td></tr>
252 <script language='JavaScript'><!--
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254 //--></script>
255 </table>
257
259 <h2>Dialog Box Parameters –
260 General Tab</h2>
262 <table x-use-null-cells cellspacing="0" class="whs12">
263 <col class="whs13">
264 <col class="whs14">
266 <tr valign="top" class="whs15">
267 <td bgcolor="#DEE8F4" width="167px" class="whs16">
268 <p class=Table
269 style="font-weight: bold;">Parameter</td>
270 <td bgcolor="#DEE8F4" width="524px" class="whs17">
271 <p class=Table
272 style="font-weight: bold;">Description</td></tr>
274 <tr valign="top" class="whs15">
275 <td colspan="1" rowspan="1" width="167px" class="whs18">
276 <p class=Table
277 style="font-weight: normal;">Instance Name</td>
278 <td colspan="1" rowspan="1" width="524px" class="whs19">
279 <p class=Table
280 style="margin-left: 14px;">Specifies the name of the LatticeMico32
281 processor. Alphanumeric values and underscores are supported. The default
282 is LM32.</td></tr>
284 <tr valign="top" class="whs15">
285 <td colspan="2" rowspan="1" width="691px" class="whs20">
286 <p class=Table
287 style="font-weight: bold;">Settings</td>
288 </tr>
290 <tr valign="top" class="whs15">
291 <td colspan="1" rowspan="1" width="167px" class="whs18">
292 <p class=Table>Use EBRs for Register File</td>
293 <td colspan="1" rowspan="1" width="524px" class="whs21">
294 <p class=Table>Uses embedded block RAMS for the register file.</td></tr>
296 <tr valign="top" class="whs15">
297 <td colspan="1" rowspan="1" width="167px" class="whs18">
298 <p class=Table>Enable Divide</td>
299 <td colspan="1" rowspan="1" width="524px" class="whs21">
300 <p class=Table>Enables the divide and modulus instructions (<span style="font-family: Verdana, sans-serif;">divu,
301 modu</span>).</td></tr>
303 <tr valign="top" class="whs15">
304 <td colspan="1" rowspan="1" width="167px" class="whs18">
305 <p class=Table>Enable Sign Extend</td>
306 <td colspan="1" rowspan="1" width="524px" class="whs21">
307 <p class=Table>Enables the sign-extension instructions (<span style="font-family: Verdana, sans-serif;">sextb,
308 sexth</span><span style="font-family: Arial, sans-serif;">)</span>.</td></tr>
310 <tr valign="top" class="whs15">
311 <td colspan="1" rowspan="1" width="167px" class="whs18">
312 <p class=Table>Location of Exception Handlers</td>
313 <td colspan="1" rowspan="1" width="524px" class="whs21">
314 <p class=Table>Specifies the default value for the vector table. This can
315 be changed by updating the EBA control register or status register.</p>
316 <p class=Table>This address must be aligned to a 256-byte boundary, since
317 the hardware ignores the least-significant byte. Unpredictable behavior
318 occurs when the exception base address and the exception vectors are not
319 aligned on a 256-byte boundary.</td></tr>
321 <tr valign="top" class="whs15">
322 <td colspan="2" rowspan="1" width="691px" class="whs20">
323 <p class=Table
324 style="font-weight: bold;">Multiplier Settings</td>
325 </tr>
327 <tr valign="top" class="whs15">
328 <td colspan="1" rowspan="1" width="167px" class="whs18">
329 <p class=Table>Enable Multiplier</td>
330 <td colspan="1" rowspan="1" width="524px" class="whs21">
331 <p class=Table>Enables the multiply instructions (<span style="font-family: Verdana, sans-serif;">mul,
332 muli)</span>.</td></tr>
334 <tr valign="top" class="whs15">
335 <td colspan="1" rowspan="1" width="167px" class="whs18">
336 <p class=Table>Enable Pipelined Multiplier (DSP Block if available)</td>
337 <td colspan="1" rowspan="1" width="524px" class="whs21">
338 <p class=Table>Enables the multiplier using the DSP block, if available.</td></tr>
340 <tr valign="top" class="whs15">
341 <td colspan="1" rowspan="1" width="167px" class="whs18">
342 <p class=Table>Enable Multicycle (LUT-based, 32 cycles) Multiplier</td>
343 <td colspan="1" rowspan="1" width="524px" class="whs21">
344 <p class=Table>Enables the multiplier using LUTs.</td></tr>
346 <tr valign="top" class="whs15">
347 <td colspan="2" rowspan="1" width="691px" class="whs20">
348 <p class=Table
349 style="font-weight: bold;">Instruction Cache</td>
350 </tr>
352 <tr valign="top" class="whs15">
353 <td colspan="1" rowspan="1" width="167px" class="whs18">
354 <p class=Table>Instruction Cache Enabled</td>
355 <td colspan="1" rowspan="1" width="524px" class="whs19">
356 <p class=Table
357 style="margin-left: 14px;">Determines whether an instruction cache
358 is implemented.</td></tr>
360 <tr valign="top" class="whs15">
361 <td colspan="1" rowspan="1" width="167px" class="whs18">
362 <p class=Table>Number of Sets</td>
363 <td colspan="1" rowspan="1" width="524px" class="whs19">
364 <p class=Table
365 style="margin-left: 14px;">Specifies the number of sets in the instruction
366 cache. Supported values are 128, 256, 512, 1024.</td></tr>
368 <tr valign="top" class="whs15">
369 <td colspan="1" rowspan="1" width="167px" class="whs18">
370 <p class=Table>Set Associativity</td>
371 <td colspan="1" rowspan="1" width="524px" class="whs19">
372 <p class=Table
373 style="margin-left: 14px;">Specifies the associativity of the instruction
374 cache. Supported values are 1, 2.</td></tr>
376 <tr valign="top" class="whs15">
377 <td colspan="1" rowspan="1" width="167px" class="whs18">
378 <p class=Table>Bytes/Cache Line</td>
379 <td colspan="1" rowspan="1" width="524px" class="whs19">
380 <p class=Table
381 style="margin-left: 15px;">Specifies the number of bytes per instruction
382 cache line. Supported values are 4, 8, 16.</td></tr>
384 <tr valign="top" class="whs15">
385 <td colspan="1" rowspan="1" width="167px" class="whs18">
386 <p class=Table>Memory Type</td>
387 <td colspan="1" rowspan="1" width="524px" class="whs19">
388 <p class=Table
389 style="margin-left: 15px;">Determines the FPGA resource to be used
390 to implement the instruction cache. The decision can be left to the synthesis
391 tool (Auto), or you can select from the following options:</p>
392 <ul type="disc" class="whs22">
394 <li class=kadov-p-CBullet><p class=Bullet>Auto –
395 Leaves the implementation of the instruction cache to the synthesis tool.</p></li>
397 <li class=kadov-p-CBullet><p class=Bullet>Distributed RAM –
398 Implements the instruction cache as distributed RAM.</p></li>
400 <li class=kadov-p-CBullet><p class=Bullet>Dual-Port EBR –
401 Implements the instruction cache as dual-port EBR (two read/write ports).</p></li>
403 <li class=kadov-p-CBullet><p class=Bullet>Pseudo Dual-Port EBR – Implements
404 the instruction cache as pseudo-dual-port EBR (one read port and one write
405 port). </p></li>
406 </ul></td></tr>
408 <tr valign="top" class="whs15">
409 <td colspan="2" rowspan="1" width="691px" class="whs20">
410 <p class=Table
411 style="font-weight: bold;">Debug Setting</td>
412 </tr>
414 <tr valign="top" class="whs15">
415 <td colspan="1" rowspan="1" width="167px" class="whs18">
416 <p class=Table>Enable Debug Interface</td>
417 <td colspan="1" rowspan="1" width="524px" class="whs21">
418 <p class=Table>Includes the debugger stub in the CPU, which is required
419 for debugging.</td></tr>
421 <tr valign="top" class="whs15">
422 <td colspan="1" rowspan="1" width="167px" class="whs18">
423 <p class=Table># of H/W Watchpoint Registers</td>
424 <td colspan="1" rowspan="1" width="524px" class="whs21">
425 <p class=Table
426 style="font-weight: normal;">Specifies the number of hardware watchpoint
427 registers to be used in the debugging process.</td></tr>
429 <tr valign="top" class="whs15">
430 <td colspan="1" rowspan="1" width="167px" class="whs18">
431 <p class=Table>Enable Debugging Code in Flash or ROM</td>
432 <td colspan="1" rowspan="1" width="524px" class="whs21">
433 <p class=Table
434 style="font-weight: normal;">Enables you to set hardware breakpoints
435 in read-only memory.</td></tr>
437 <tr valign="top" class="whs15">
438 <td colspan="1" rowspan="1" width="167px" class="whs18">
439 <p class=Table># of H/W Breakpoint Registers</td>
440 <td colspan="1" rowspan="1" width="524px" class="whs21">
441 <p class=Table>Specifies the number of hardware breakpoint registers to
442 be used in the debugging process.</td></tr>
444 <tr valign="top" class="whs15">
445 <td colspan="1" rowspan="1" width="167px" class="whs18">
446 <p class=Table>Enable PC Trace</td>
447 <td colspan="1" rowspan="1" width="524px" class="whs21">
448 <p class=Table>Enables the Program Counter Trace feature, which enables
449 you to run the program trace during debug to find items in your C or C++
450 Code during debug, such as breakpoints and exceptions. Refer to <span
451 style="font-weight: bold;"><B>Help > Help Contents > C/C++ SPE</B></span>
452 and <span style="font-weight: bold;"><B>Debug > Concepts > Program
453 Counter Trace</B></span> for more information on Program Counter Trace.</td></tr>
455 <tr valign="top" class="whs15">
456 <td colspan="1" rowspan="1" width="167px" class="whs18">
457 <p class=Table>Trace Depth</td>
458 <td colspan="1" rowspan="1" width="524px" class="whs21">
459 <p class=Table>Enables you to specify the depth of the Program Counter
460 Trace buffer. Refer to <span style="font-weight: bold;"><B>Help > Help
461 Contents > C/C++ SPE</B></span> and <span style="font-weight: bold;"><B>Debug
462 > Concepts > Program Counter Trace</B></span> for more information on
463 Program Counter Trace.</td></tr>
465 <tr valign="top" class="whs15">
466 <td colspan="1" rowspan="1" width="167px" class="whs18">
467 <p class=Table>Enable Dynamic Mapping of Exception Handlers to Debugger</td>
468 <td colspan="1" rowspan="1" width="524px" class="whs21">
469 <p class=Table>This option gives the designer the ability to dynamically change EBA to debug stub by asserting an LM32 GPIO pin named at_debug. This pin is exposed to the design only when this option is enabled. Allowable values are 0 = EBA and 1 = DEBA.
470 </td></tr>
472 <tr valign="top" class="whs15">
473 <td colspan="2" rowspan="1" width="691px" class="whs20">
474 <p class=Table
475 style="font-weight: bold;">Shifter Settings</td>
476 </tr>
478 <tr valign="top" class="whs15">
479 <td colspan="1" rowspan="1" width="167px" class="whs18">
480 <p class=Table>Enable Piplined Barrel Shifter</td>
481 <td colspan="1" rowspan="1" width="524px" class="whs19">
482 <p>Enables the barrel shifter to be pipelined. The barrel shifter is implemented
483 to perform a shift operation in three cycles.</td></tr>
485 <tr valign="top" class="whs15">
486 <td colspan="1" rowspan="1" width="167px" class="whs18">
487 <p class=Table>Enable Multicycle Barrel Shifter (up to 32 cycles)</td>
488 <td colspan="1" rowspan="1" width="524px" class="whs19">
489 <p>Enables multi-cycle shift operation for the barrel shifter. The barrel
490 shifter is implemented to shift one bit per cycle and take thirty-two
491 cycles to complete.</td></tr>
493 <tr valign="top" class="whs15">
494 <td colspan="2" rowspan="1" width="691px" class="whs20">
495 <p class=Table><span style="font-weight: bold;"><B>Data Cache</B></span></td>
496 </tr>
498 <tr valign="top" class="whs15">
499 <td colspan="1" rowspan="1" width="167px" class="whs18">
500 <p class=Table>Data Cache Enabled</td>
501 <td colspan="1" rowspan="1" width="524px" class="whs21">
502 <p class=Table>Determines whether a data cache is implemented.</td></tr>
504 <tr valign="top" class="whs15">
505 <td colspan="1" rowspan="1" width="167px" class="whs18">
506 <p class=Table>Number of Sets</td>
507 <td colspan="1" rowspan="1" width="524px" class="whs21">
508 <p class=Table>Specifies the number of sets in the data cache. Supported
509 values are 128, 256, 512, 1024.</td></tr>
511 <tr valign="top" class="whs15">
512 <td colspan="1" rowspan="1" width="167px" class="whs18">
513 <p class=Table>Set Associativity</td>
514 <td colspan="1" rowspan="1" width="524px" class="whs21">
515 <p class=Table>Specifies the associativity of the data cache. Supported
516 values are 1, 2.</td></tr>
518 <tr valign="top" class="whs15">
519 <td colspan="1" rowspan="1" width="167px" class="whs18">
520 <p class=Table>Bytes/Cache Line</td>
521 <td colspan="1" rowspan="1" width="524px" class="whs21">
522 <p class=Table>Specifies the number of bytes per data cache line. Supported
523 values are 4, 8, 16.</td></tr>
525 <tr valign="top" class="whs15">
526 <td colspan="1" rowspan="1" width="167px" class="whs23">
527 <p class=Table>Memory Type</td>
528 <td colspan="1" rowspan="1" width="524px" class="whs24">
529 <p class=Table>Determines the FPGA resource to be used to implement the
530 data cache. The decision can be left to the synthesis tool (Auto), or
531 you can select from the following options:</p>
532 <ul>
534 <li class=kadov-p-CBullet><p class=Bullet>Auto –
535 Leaves the implementation of the data cache to the synthesis tool.</p></li>
537 <li class=kadov-p-CBullet><p class=Bullet>Distributed RAM –
538 Implements the data cache as distributed RAM.</p></li>
540 <li class=kadov-p-CBullet><p class=Bullet>Dual-Port EBR –
541 Implements the data cache as dual-port EBR (two read/write ports).</p></li>
542 </ul></td></tr>
543 </table>
545 <p> </p>
547 <h2>Dialog Box Parameters –
548 Inline Memory Tab</h2>
550 <table x-use-null-cells cellspacing="0" class="whs12">
551 <col class="whs13">
552 <col class="whs14">
554 <tr valign="top" class="whs15">
555 <td bgcolor="#DEE8F4" width="167px" class="whs25">
556 <p class=Table
557 style="font-weight: bold;">Parameter</td>
558 <td bgcolor="#DEE8F4" width="524px" class="whs26">
559 <p class=Table
560 style="font-weight: bold;">Description</td></tr>
562 <tr valign="top" class="whs15">
563 <td rowspan="1" colspan="2" width="691px" class="whs27">
564 <p class=Table
565 style="font-weight: bold;">Instruction Inline Memory</td>
566 </tr>
568 <tr valign="top" class="whs15">
569 <td width="167px" class="whs28">
570 <p class=Table>Enable</td>
571 <td width="524px" class="whs29">
572 <p class=Table>Enables the instruction inline memory</td></tr>
574 <tr valign="top" class="whs15">
575 <td width="167px" class="whs28">
576 <p class=Table>Instance Name</td>
577 <td width="524px" class="whs29">
578 <p class=Table>Specifics the name of the instruction inline memory. Alphanumeric
579 values and underscores are supported. The default is Instruction_IM.</td></tr>
581 <tr valign="top" class="whs15">
582 <td width="167px" class="whs28">
583 <p class=Table>Base Address</td>
584 <td width="524px" class="whs29">
585 <p class=Table>Specifies the base address for the instruction inline memory.
586 The default is 0x10000000.</td></tr>
588 <tr valign="top" class="whs15">
589 <td width="167px" class="whs28">
590 <p class=Table>Size of Memory in Bytes</td>
591 <td width="524px" class="whs29">
592 <p class=Table>Specifies the size of the instruction inline memory.</td></tr>
594 <tr valign="top" class="whs15">
595 <td rowspan="1" colspan="2" width="691px" class="whs27">
596 <p class=Table><span style="font-weight: bold;"><B>Memory File</B></span></td>
597 </tr>
599 <tr valign="top" class="whs15">
600 <td width="167px" class="whs28">
601 <p class=Table>Initialization File Name</td>
602 <td width="524px" class="whs29">
603 <p class=Table>Specifies the name of the memory initialization file for
604 instruction inline memory.</td></tr>
606 <tr valign="top" class="whs15">
607 <td width="167px" class="whs28">
608 <p class=Table>File Format</td>
609 <td width="524px" class="whs29">
610 <p class=Table>Specifies the format of the memory initialization file:
611 hex or binary.</td></tr>
613 <tr valign="top" class="whs15">
614 <td rowspan="1" colspan="2" width="691px" class="whs27">
615 <p class=Table
616 style="font-weight: bold;">Data Inline Memory</td>
617 </tr>
619 <tr valign="top" class="whs15">
620 <td width="167px" class="whs28">
621 <p class=Table>Enabled</td>
622 <td width="524px" class="whs29">
623 <p class=Table>Enables the data inline memory.</td></tr>
625 <tr valign="top" class="whs15">
626 <td width="167px" class="whs28">
627 <p class=Table>Instance Name</td>
628 <td width="524px" class="whs29">
629 <p class=Table>Specifies the name of the data inline memory. Alphanumeric
630 values and underscores are supported. The default is Data_IM.</td></tr>
632 <tr valign="top" class="whs15">
633 <td width="167px" class="whs28">
634 <p class=Table>Base Address</td>
635 <td width="524px" class="whs29">
636 <p class=Table>Specifies the base address for the data inline memory. The
637 default is 0x20000000.</td></tr>
639 <tr valign="top" class="whs15">
640 <td width="167px" class="whs28">
641 <p class=Table>Size of Memory in Bytes</td>
642 <td width="524px" class="whs29">
643 <p class=Table>Specifies the size of the data inline memory.</td></tr>
645 <tr valign="top" class="whs15">
646 <td colspan="2" rowspan="1" width="691px" class="whs27">
647 <p class=Table
648 style="font-weight: bold;">Memory File</td>
649 </tr>
651 <tr valign="top" class="whs15">
652 <td colspan="1" rowspan="1" width="167px" class="whs28">
653 <p class=Table>Initialization File Name</td>
654 <td colspan="1" rowspan="1" width="524px" class="whs29">
655 <p class=Table>Specifies the name of the memory initialization file for
656 data inline memory.</td></tr>
658 <tr valign="top" class="whs15">
659 <td colspan="1" rowspan="1" width="167px" class="whs30">
660 <p class=Table>File Format</td>
661 <td colspan="1" rowspan="1" width="524px" class="whs31">
662 <p class=Table>Specifies the format of the memory initialization file:
663 hex or binary.</td></tr>
664 </table>
666 <p> </p>
668 <p>For the revision history of the component RTL files, refer to the header
669 of each component Verilog source file. </p>
671 <p><span style="font-weight: bold;"><B>Note</B></span>: If the processor manual
672 fails to open, click <img src="qm_icon.jpg" x-maintain-ratio="TRUE" width="14px" height="16px" border="0" class="img_whs32"> on the Available Components toolbar,
673 and then click the note button.</p>
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