1.1 --- a/er1.v Sun Mar 06 19:23:51 2011 +0000 1.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 1.3 @@ -1,230 +0,0 @@ 1.4 -// ============================================================================= 1.5 -// COPYRIGHT NOTICE 1.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation 1.7 -// ALL RIGHTS RESERVED 1.8 -// This confidential and proprietary software may be used only as authorised by 1.9 -// a licensing agreement from Lattice Semiconductor Corporation. 1.10 -// The entire notice above must be reproduced on all authorized copies and 1.11 -// copies may only be made to the extent permitted by a licensing agreement from 1.12 -// Lattice Semiconductor Corporation. 1.13 -// 1.14 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 1.15 -// 5555 NE Moore Court 408-826-6000 (other locations) 1.16 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 1.17 -// U.S.A email: techsupport@latticesemi.com 1.18 -// =============================================================================/ 1.19 -// FILE DETAILS 1.20 -// Project : LatticeMico32 1.21 -// File : er1.v 1.22 -// Description: 1.23 -// This module is where the ER1 register implemented. ER1 and ER2 registers 1.24 -// can be registers implemented in Lattice FPGAs using normal FPGA's 1.25 -// programmable logic resources. Once they are implemented, they can be 1.26 -// accessed as if they are JTAG data registers through the FPGA JTAG port. 1.27 -// In order to accessing these registers, JTAG instructions ER1(0x32) or 1.28 -// ER2(0x38) needs to be written to the JTAG IR register for enabling the 1.29 -// ER1/ER2 accessing logic. The ER1 or ER2 accessing logic can only be 1.30 -// enabled one at a time. Once they are enabled, they will be disabled if 1.31 -// another JTAG instruction is written into the JTAG instruction register. 1.32 -// The registers allow dynamically accessing the FPGA internal information 1.33 -// even when the device is running. Therefore, they are very useful for some 1.34 -// of the IP cores. In order to let ER1/ER2 registers shared by multiple IP 1.35 -// cores or other designs, there is a ER1/ER2 structure patterned by Lattice. 1.36 -// The ER1/ER2 structure allows only one ER1 register but more than one ER2 1.37 -// registers in an FPGA device. Please refer to the related document for 1.38 -// this patterned ER1/ER2 structure. 1.39 -// Dependencies : None 1.40 -// Version : 6.0.14 1.41 -// : Initial Version 1.42 -// Version : 7.0SP2, 3.0 1.43 -// : No Change 1.44 -// Version : 3.1 1.45 -// : No Change 1.46 -// ============================================================================= 1.47 -module ER1 (input JTCK, 1.48 - input JTDI, 1.49 - output JTDO1, 1.50 - output reg JTDO2, 1.51 - input JSHIFT, 1.52 - input JUPDATE, 1.53 - input JRSTN, 1.54 - input JCE1, 1.55 - input [14:0] ER2_TDO, 1.56 - output reg [14:0] IP_ENABLE, 1.57 - input ISPTRACY_ER2_TDO, 1.58 - output ISPTRACY_ENABLE, 1.59 - output CONTROL_DATAN)/* synthesis syn_hier = hard */; 1.60 - 1.61 - 1.62 - wire controlDataNBit; 1.63 - wire ispTracyEnableBit; 1.64 - wire [3:0] encodedIpEnableBits; 1.65 - wire [9:0] er1TdiBit; 1.66 - wire captureDrER1; 1.67 - 1.68 - 1.69 - assign JTDO1 = er1TdiBit[0]; 1.70 - 1.71 - TYPEB BIT0 (.CLK(JTCK), 1.72 - .RESET_N(JRSTN), 1.73 - .CLKEN(JCE1), 1.74 - .TDI(er1TdiBit[1]), 1.75 - .TDO(er1TdiBit[0]), 1.76 - .DATA_IN(1'b0), 1.77 - .CAPTURE_DR(captureDrER1)); 1.78 - 1.79 - TYPEB BIT1 (.CLK(JTCK), 1.80 - .RESET_N(JRSTN), 1.81 - .CLKEN(JCE1), 1.82 - .TDI(er1TdiBit[2]), 1.83 - .TDO(er1TdiBit[1]), 1.84 - .DATA_IN(1'b0), 1.85 - .CAPTURE_DR(captureDrER1)); 1.86 - 1.87 - TYPEB BIT2 (.CLK(JTCK), 1.88 - .RESET_N(JRSTN), 1.89 - .CLKEN(JCE1), 1.90 - .TDI(er1TdiBit[3]), 1.91 - .TDO(er1TdiBit[2]), 1.92 - .DATA_IN(1'b1), 1.93 - .CAPTURE_DR(captureDrER1)); 1.94 - 1.95 - TYPEA BIT3 (.CLK(JTCK), 1.96 - .RESET_N(JRSTN), 1.97 - .CLKEN(JCE1), 1.98 - .TDI(er1TdiBit[4]), 1.99 - .TDO(er1TdiBit[3]), 1.100 - .DATA_OUT(controlDataNBit), 1.101 - .DATA_IN(controlDataNBit), 1.102 - .CAPTURE_DR(captureDrER1), 1.103 - .UPDATE_DR(JUPDATE)); 1.104 - 1.105 - assign CONTROL_DATAN = controlDataNBit; 1.106 - 1.107 - TYPEA BIT4 (.CLK(JTCK), 1.108 - .RESET_N(JRSTN), 1.109 - .CLKEN(JCE1), 1.110 - .TDI(er1TdiBit[5]), 1.111 - .TDO(er1TdiBit[4]), 1.112 - .DATA_OUT(ispTracyEnableBit), 1.113 - .DATA_IN(ispTracyEnableBit), 1.114 - .CAPTURE_DR(captureDrER1), 1.115 - .UPDATE_DR(JUPDATE) 1.116 - ); 1.117 - 1.118 - assign ISPTRACY_ENABLE = ispTracyEnableBit; 1.119 - 1.120 - TYPEA BIT5 (.CLK(JTCK), 1.121 - .RESET_N(JRSTN), 1.122 - .CLKEN(JCE1), 1.123 - .TDI(er1TdiBit[6]), 1.124 - .TDO(er1TdiBit[5]), 1.125 - .DATA_OUT(encodedIpEnableBits[0]), 1.126 - .DATA_IN(encodedIpEnableBits[0]), 1.127 - .CAPTURE_DR(captureDrER1), 1.128 - .UPDATE_DR(JUPDATE)); 1.129 - 1.130 - TYPEA BIT6 (.CLK(JTCK), 1.131 - .RESET_N(JRSTN), 1.132 - .CLKEN(JCE1), 1.133 - .TDI(er1TdiBit[7]), 1.134 - .TDO(er1TdiBit[6]), 1.135 - .DATA_OUT(encodedIpEnableBits[1]), 1.136 - .DATA_IN(encodedIpEnableBits[1]), 1.137 - .CAPTURE_DR(captureDrER1), 1.138 - .UPDATE_DR(JUPDATE)); 1.139 - 1.140 - TYPEA BIT7 (.CLK(JTCK), 1.141 - .RESET_N(JRSTN), 1.142 - .CLKEN(JCE1), 1.143 - .TDI(er1TdiBit[8]), 1.144 - .TDO(er1TdiBit[7]), 1.145 - .DATA_OUT(encodedIpEnableBits[2]), 1.146 - .DATA_IN(encodedIpEnableBits[2]), 1.147 - .CAPTURE_DR(captureDrER1), 1.148 - .UPDATE_DR(JUPDATE)); 1.149 - 1.150 - TYPEA BIT8 (.CLK(JTCK), 1.151 - .RESET_N(JRSTN), 1.152 - .CLKEN(JCE1), 1.153 - .TDI(er1TdiBit[9]), 1.154 - .TDO(er1TdiBit[8]), 1.155 - .DATA_OUT(encodedIpEnableBits[3]), 1.156 - .DATA_IN(encodedIpEnableBits[3]), 1.157 - .CAPTURE_DR(captureDrER1), 1.158 - .UPDATE_DR(JUPDATE) 1.159 - ); 1.160 - 1.161 - assign er1TdiBit[9] = JTDI; 1.162 - assign captureDrER1 = !JSHIFT & JCE1; 1.163 - 1.164 - always @ (encodedIpEnableBits,ISPTRACY_ER2_TDO, ER2_TDO) 1.165 - begin 1.166 - case (encodedIpEnableBits) 1.167 - 4'h0: begin 1.168 - IP_ENABLE <= 15'b000000000000000; 1.169 - JTDO2 <= ISPTRACY_ER2_TDO; 1.170 - end 1.171 - 4'h1: begin 1.172 - IP_ENABLE <= 15'b000000000000001; 1.173 - JTDO2 <= ER2_TDO[0]; 1.174 - end 1.175 - 4'h2: begin 1.176 - IP_ENABLE <= 15'b000000000000010; 1.177 - JTDO2 <= ER2_TDO[1]; 1.178 - end 1.179 - 4'h3: begin 1.180 - IP_ENABLE <= 15'b000000000000100; 1.181 - JTDO2 <= ER2_TDO[2]; 1.182 - end 1.183 - 4'h4: begin 1.184 - IP_ENABLE <= 15'b000000000001000; 1.185 - JTDO2 <= ER2_TDO[3]; 1.186 - end 1.187 - 4'h5: begin 1.188 - IP_ENABLE <= 15'b000000000010000; 1.189 - JTDO2 <= ER2_TDO[4]; 1.190 - end 1.191 - 4'h6: begin 1.192 - IP_ENABLE <= 15'b000000000100000; 1.193 - JTDO2 <= ER2_TDO[5]; 1.194 - end 1.195 - 4'h7: begin 1.196 - IP_ENABLE <= 15'b000000001000000; 1.197 - JTDO2 <= ER2_TDO[6]; 1.198 - end 1.199 - 4'h8: begin 1.200 - IP_ENABLE <= 15'b000000010000000; 1.201 - JTDO2 <= ER2_TDO[7]; 1.202 - end 1.203 - 4'h9: begin 1.204 - IP_ENABLE <= 15'b000000100000000; 1.205 - JTDO2 <= ER2_TDO[8]; 1.206 - end 1.207 - 4'hA: begin 1.208 - IP_ENABLE <= 15'b000001000000000; 1.209 - JTDO2 <= ER2_TDO[9]; 1.210 - end 1.211 - 4'hB: begin 1.212 - IP_ENABLE <= 15'b000010000000000; 1.213 - JTDO2 <= ER2_TDO[10]; 1.214 - end 1.215 - 4'hC: begin 1.216 - IP_ENABLE <= 15'b000100000000000; 1.217 - JTDO2 <= ER2_TDO[11]; 1.218 - end 1.219 - 4'hD: begin 1.220 - IP_ENABLE <= 15'b001000000000000; 1.221 - JTDO2 <= ER2_TDO[12]; 1.222 - end 1.223 - 4'hE: begin 1.224 - IP_ENABLE <= 15'b010000000000000; 1.225 - JTDO2 <= ER2_TDO[13]; 1.226 - end 1.227 - 4'hF: begin 1.228 - IP_ENABLE <= 15'b100000000000000; 1.229 - JTDO2 <= ER2_TDO[14]; 1.230 - end 1.231 - endcase 1.232 - end 1.233 -endmodule