IPCores/lm32_cpu / files

     1.1 --- a/JTAGB.v	Sun Mar 06 19:23:51 2011 +0000
     1.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
     1.3 @@ -1,42 +0,0 @@
     1.4 -// =============================================================================
     1.5 -//                           COPYRIGHT NOTICE
     1.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation
     1.7 -// ALL RIGHTS RESERVED
     1.8 -// This confidential and proprietary software may be used only as authorised by
     1.9 -// a licensing agreement from Lattice Semiconductor Corporation.
    1.10 -// The entire notice above must be reproduced on all authorized copies and
    1.11 -// copies may only be made to the extent permitted by a licensing agreement from
    1.12 -// Lattice Semiconductor Corporation.
    1.13 -//
    1.14 -// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
    1.15 -// 5555 NE Moore Court                            408-826-6000 (other locations)
    1.16 -// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
    1.17 -// U.S.A                                   email: techsupport@latticesemi.com
    1.18 -// =============================================================================/
    1.19 -//                         FILE DETAILS
    1.20 -// Project          : LatticeMico32
    1.21 -// File             : JTAGB.v
    1.22 -// Title            : JTAGB Black Box
    1.23 -// Dependencies     : None
    1.24 -// Version          : 6.0.14
    1.25 -//                  : Initial Release
    1.26 -// Version          : 7.0SP2, 3.0
    1.27 -//                  : No Change
    1.28 -// Version          : 3.1
    1.29 -//                  : No Change
    1.30 -// =============================================================================
    1.31 -module JTAGB (
    1.32 -         output JTCK,
    1.33 -         output JRTI1,
    1.34 -         output JRTI2,
    1.35 -         output JTDI,
    1.36 -         output JSHIFT,
    1.37 -         output JUPDATE,
    1.38 -         output JRSTN,
    1.39 -         output JCE1,
    1.40 -         output JCE2,
    1.41 -         input JTDO1,
    1.42 -         input JTDO2
    1.43 -      ) /*synthesis syn_black_box */; 
    1.44 -      
    1.45 -endmodule

     2.1 --- a/er1.v	Sun Mar 06 19:23:51 2011 +0000
     2.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
     2.3 @@ -1,230 +0,0 @@
     2.4 -// =============================================================================
     2.5 -//                           COPYRIGHT NOTICE
     2.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation
     2.7 -// ALL RIGHTS RESERVED
     2.8 -// This confidential and proprietary software may be used only as authorised by
     2.9 -// a licensing agreement from Lattice Semiconductor Corporation.
    2.10 -// The entire notice above must be reproduced on all authorized copies and
    2.11 -// copies may only be made to the extent permitted by a licensing agreement from
    2.12 -// Lattice Semiconductor Corporation.
    2.13 -//
    2.14 -// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
    2.15 -// 5555 NE Moore Court                            408-826-6000 (other locations)
    2.16 -// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
    2.17 -// U.S.A                                   email: techsupport@latticesemi.com
    2.18 -// =============================================================================/
    2.19 -//                         FILE DETAILS
    2.20 -// Project          : LatticeMico32
    2.21 -// File             : er1.v
    2.22 -// Description:
    2.23 -//    This module is where the ER1 register implemented. ER1 and ER2 registers
    2.24 -//    can be registers implemented in Lattice FPGAs using normal FPGA's
    2.25 -//    programmable logic resources.  Once they are implemented, they can be
    2.26 -//    accessed as if they are JTAG data registers through the FPGA JTAG port.
    2.27 -//    In order to accessing these registers, JTAG instructions ER1(0x32) or
    2.28 -//    ER2(0x38) needs to be written to the JTAG IR register for enabling the
    2.29 -//    ER1/ER2 accessing logic.  The ER1 or ER2 accessing logic can only be
    2.30 -//    enabled one at a time.  Once they are enabled, they will be disabled if
    2.31 -//    another JTAG instruction is written into the JTAG instruction register.
    2.32 -//    The registers allow dynamically accessing the FPGA internal information
    2.33 -//    even when the device is running.  Therefore, they are very useful for some
    2.34 -//    of the IP cores.  In order to let ER1/ER2 registers shared by multiple IP
    2.35 -//    cores or other designs, there is a ER1/ER2 structure patterned by Lattice.
    2.36 -//    The ER1/ER2 structure allows only one ER1 register but more than one ER2
    2.37 -//    registers in an FPGA device.  Please refer to the related document for
    2.38 -//    this patterned ER1/ER2 structure.
    2.39 -// Dependencies     : None
    2.40 -// Version          : 6.0.14
    2.41 -//                  : Initial Version
    2.42 -// Version          : 7.0SP2, 3.0
    2.43 -//                  : No Change
    2.44 -// Version          : 3.1
    2.45 -//                  : No Change
    2.46 -// =============================================================================
    2.47 -module ER1 (input  JTCK,
    2.48 -	    input  JTDI,
    2.49 -	    output JTDO1,
    2.50 -	    output reg JTDO2,
    2.51 -	    input  JSHIFT,
    2.52 -	    input  JUPDATE,
    2.53 -	    input  JRSTN,
    2.54 -	    input  JCE1,
    2.55 -	    input [14:0] ER2_TDO,
    2.56 -	    output reg [14:0] IP_ENABLE,
    2.57 -	    input  ISPTRACY_ER2_TDO,
    2.58 -	    output ISPTRACY_ENABLE,
    2.59 -	    output CONTROL_DATAN)/* synthesis syn_hier = hard */;
    2.60 -
    2.61 -
    2.62 -   wire 	   controlDataNBit;
    2.63 -   wire 	   ispTracyEnableBit;
    2.64 -   wire [3:0] 	   encodedIpEnableBits;
    2.65 -   wire [9:0] 	   er1TdiBit;
    2.66 -   wire 	   captureDrER1;
    2.67 -   
    2.68 -
    2.69 -   assign 	   JTDO1 = er1TdiBit[0];
    2.70 -   
    2.71 -   TYPEB BIT0 (.CLK(JTCK),
    2.72 -	       .RESET_N(JRSTN),
    2.73 -	       .CLKEN(JCE1),
    2.74 -	       .TDI(er1TdiBit[1]),
    2.75 -	       .TDO(er1TdiBit[0]),
    2.76 -	       .DATA_IN(1'b0),
    2.77 -	       .CAPTURE_DR(captureDrER1));
    2.78 -
    2.79 -   TYPEB BIT1 (.CLK(JTCK),
    2.80 -	       .RESET_N(JRSTN),
    2.81 -	       .CLKEN(JCE1),
    2.82 -	       .TDI(er1TdiBit[2]),
    2.83 -	       .TDO(er1TdiBit[1]),
    2.84 -	       .DATA_IN(1'b0),
    2.85 -	       .CAPTURE_DR(captureDrER1));
    2.86 -
    2.87 -   TYPEB BIT2 (.CLK(JTCK),
    2.88 -	       .RESET_N(JRSTN),
    2.89 -	       .CLKEN(JCE1),
    2.90 -	       .TDI(er1TdiBit[3]),
    2.91 -	       .TDO(er1TdiBit[2]),
    2.92 -	       .DATA_IN(1'b1),
    2.93 -	       .CAPTURE_DR(captureDrER1));
    2.94 -   
    2.95 -   TYPEA BIT3 (.CLK(JTCK),
    2.96 -	       .RESET_N(JRSTN),
    2.97 -	       .CLKEN(JCE1),
    2.98 -	       .TDI(er1TdiBit[4]),
    2.99 -	       .TDO(er1TdiBit[3]),
   2.100 -	       .DATA_OUT(controlDataNBit),
   2.101 -	       .DATA_IN(controlDataNBit),
   2.102 -	       .CAPTURE_DR(captureDrER1),
   2.103 -	       .UPDATE_DR(JUPDATE));
   2.104 -
   2.105 -   assign CONTROL_DATAN = controlDataNBit;
   2.106 -
   2.107 -   TYPEA BIT4 (.CLK(JTCK),
   2.108 -	       .RESET_N(JRSTN),
   2.109 -	       .CLKEN(JCE1),
   2.110 -	       .TDI(er1TdiBit[5]),
   2.111 -	       .TDO(er1TdiBit[4]),
   2.112 -	       .DATA_OUT(ispTracyEnableBit),
   2.113 -	       .DATA_IN(ispTracyEnableBit),
   2.114 -	       .CAPTURE_DR(captureDrER1),
   2.115 -	       .UPDATE_DR(JUPDATE)
   2.116 -	       );
   2.117 -
   2.118 -   assign ISPTRACY_ENABLE = ispTracyEnableBit;
   2.119 -
   2.120 -   TYPEA BIT5 (.CLK(JTCK),
   2.121 -	       .RESET_N(JRSTN),
   2.122 -	       .CLKEN(JCE1),
   2.123 -	       .TDI(er1TdiBit[6]),
   2.124 -	       .TDO(er1TdiBit[5]),
   2.125 -	       .DATA_OUT(encodedIpEnableBits[0]),
   2.126 -	       .DATA_IN(encodedIpEnableBits[0]),
   2.127 -	       .CAPTURE_DR(captureDrER1),
   2.128 -	       .UPDATE_DR(JUPDATE));
   2.129 -   
   2.130 -   TYPEA BIT6 (.CLK(JTCK),
   2.131 -	       .RESET_N(JRSTN),
   2.132 -	       .CLKEN(JCE1),
   2.133 -	       .TDI(er1TdiBit[7]),
   2.134 -	       .TDO(er1TdiBit[6]),
   2.135 -	       .DATA_OUT(encodedIpEnableBits[1]),
   2.136 -	       .DATA_IN(encodedIpEnableBits[1]),
   2.137 -	       .CAPTURE_DR(captureDrER1),
   2.138 -	       .UPDATE_DR(JUPDATE));
   2.139 -   
   2.140 -   TYPEA BIT7 (.CLK(JTCK),
   2.141 -	       .RESET_N(JRSTN),
   2.142 -	       .CLKEN(JCE1),
   2.143 -	       .TDI(er1TdiBit[8]),
   2.144 -	       .TDO(er1TdiBit[7]),
   2.145 -	       .DATA_OUT(encodedIpEnableBits[2]),
   2.146 -	       .DATA_IN(encodedIpEnableBits[2]),
   2.147 -	       .CAPTURE_DR(captureDrER1),
   2.148 -	       .UPDATE_DR(JUPDATE));
   2.149 -   
   2.150 -   TYPEA BIT8 (.CLK(JTCK),
   2.151 -	       .RESET_N(JRSTN),
   2.152 -	       .CLKEN(JCE1),
   2.153 -	       .TDI(er1TdiBit[9]),
   2.154 -	       .TDO(er1TdiBit[8]),
   2.155 -	       .DATA_OUT(encodedIpEnableBits[3]),
   2.156 -	       .DATA_IN(encodedIpEnableBits[3]),
   2.157 -	       .CAPTURE_DR(captureDrER1),
   2.158 -	       .UPDATE_DR(JUPDATE)
   2.159 -	       );
   2.160 -   
   2.161 -   assign er1TdiBit[9] = JTDI;
   2.162 -   assign captureDrER1  = !JSHIFT & JCE1;
   2.163 -   
   2.164 -   always @ (encodedIpEnableBits,ISPTRACY_ER2_TDO, ER2_TDO)
   2.165 -   begin
   2.166 -    case (encodedIpEnableBits)
   2.167 -      4'h0: begin 
   2.168 -      		IP_ENABLE <= 15'b000000000000000;
   2.169 -      		JTDO2 <= ISPTRACY_ER2_TDO;
   2.170 -      	    end
   2.171 -      4'h1: begin
   2.172 -      		IP_ENABLE <= 15'b000000000000001;
   2.173 -      		JTDO2 <= ER2_TDO[0];
   2.174 -      	    end	
   2.175 -      4'h2: begin
   2.176 -      		IP_ENABLE <= 15'b000000000000010;
   2.177 -      		JTDO2 <= ER2_TDO[1];
   2.178 -      	    end
   2.179 -      4'h3: begin
   2.180 -      		IP_ENABLE <= 15'b000000000000100;
   2.181 -      		JTDO2 <= ER2_TDO[2];
   2.182 -      	    end
   2.183 -      4'h4: begin
   2.184 -      		IP_ENABLE <= 15'b000000000001000;
   2.185 -      		JTDO2 <= ER2_TDO[3];
   2.186 -      	    end
   2.187 -      4'h5: begin
   2.188 -      		IP_ENABLE <= 15'b000000000010000;
   2.189 -      		JTDO2 <= ER2_TDO[4];
   2.190 -      	    end
   2.191 -      4'h6: begin
   2.192 -      		IP_ENABLE <= 15'b000000000100000;
   2.193 -      		JTDO2 <= ER2_TDO[5];
   2.194 -      	    end
   2.195 -      4'h7: begin
   2.196 -      		IP_ENABLE <= 15'b000000001000000;
   2.197 -      		JTDO2 <= ER2_TDO[6];
   2.198 -      	    end
   2.199 -      4'h8: begin
   2.200 -      		IP_ENABLE <= 15'b000000010000000;
   2.201 -      		JTDO2 <= ER2_TDO[7];
   2.202 -      	    end
   2.203 -      4'h9: begin
   2.204 -      		IP_ENABLE <= 15'b000000100000000;
   2.205 -      		JTDO2 <= ER2_TDO[8];
   2.206 -      	    end
   2.207 -      4'hA: begin
   2.208 -      		IP_ENABLE <= 15'b000001000000000;
   2.209 -      		JTDO2 <= ER2_TDO[9];
   2.210 -      	    end
   2.211 -      4'hB: begin
   2.212 -      		IP_ENABLE <= 15'b000010000000000;
   2.213 -      		JTDO2 <= ER2_TDO[10];
   2.214 -      	    end
   2.215 -      4'hC: begin
   2.216 -      		IP_ENABLE <= 15'b000100000000000;
   2.217 -      		JTDO2 <= ER2_TDO[11];
   2.218 -      	    end
   2.219 -      4'hD: begin
   2.220 -      		IP_ENABLE <= 15'b001000000000000;
   2.221 -      		JTDO2 <= ER2_TDO[12];
   2.222 -      	    end
   2.223 -      4'hE: begin
   2.224 -      		IP_ENABLE <= 15'b010000000000000;
   2.225 -      		JTDO2 <= ER2_TDO[13];
   2.226 -      	    end
   2.227 -      4'hF: begin
   2.228 -      		IP_ENABLE <= 15'b100000000000000;
   2.229 -      		JTDO2 <= ER2_TDO[14];
   2.230 -      	    end
   2.231 -    endcase
   2.232 -  end
   2.233 -endmodule

     3.1 --- a/jtag_cores.v	Sun Mar 06 19:23:51 2011 +0000
     3.2 +++ b/jtag_cores.v	Sun Mar 06 19:31:09 2011 +0000
     3.3 @@ -1,54 +1,6 @@
     3.4 -// ============================================================================
     3.5 -//                           COPYRIGHT NOTICE
     3.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation
     3.7 -// ALL RIGHTS RESERVED
     3.8 -// This confidential and proprietary software may be used only as authorised by
     3.9 -// a licensing agreement from Lattice Semiconductor Corporation.
    3.10 -// The entire notice above must be reproduced on all authorized copies and
    3.11 -// copies may only be made to the extent permitted by a licensing agreement from
    3.12 -// Lattice Semiconductor Corporation.
    3.13 -//
    3.14 -// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
    3.15 -// 5555 NE Moore Court                            408-826-6000 (other locations)
    3.16 -// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
    3.17 -// U.S.A                                   email: techsupport@latticesemi.com
    3.18 -// ============================================================================/
    3.19 -//                         FILE DETAILS
    3.20 -// Project          : LatticeMico32
    3.21 -// File             : jtag_cores.v
    3.22 -// Title            : Instantiates all IP cores on JTAG chain.
    3.23 -// Dependencies     : system_conf.v
    3.24 -// Version          : 6.0.14
    3.25 -//                  : modified to use jtagconn for LM32,
    3.26 -//                  : all technologies 7/10/07
    3.27 -// Version          : 7.0SP2, 3.0
    3.28 -//                  : No Change
    3.29 -// Version          : 3.1
    3.30 -//                  : No Change
    3.31 -// ============================================================================
    3.32 +// TODO
    3.33  
    3.34 -`include "system_conf.v"
    3.35 -
    3.36 -/////////////////////////////////////////////////////
    3.37 -// jtagconn16 Module Definition
    3.38 -/////////////////////////////////////////////////////
    3.39 -
    3.40 -module jtagconn16 (er2_tdo, jtck, jtdi, jshift, jupdate, jrstn, jce2, ip_enable) ;
    3.41 -    input  er2_tdo ; 
    3.42 -    output jtck ; 
    3.43 -    output jtdi ; 
    3.44 -    output jshift ; 
    3.45 -    output jupdate ; 
    3.46 -    output jrstn ; 
    3.47 -    output jce2 ; 
    3.48 -    output ip_enable ; 
    3.49 -endmodule
    3.50 -
    3.51 -/////////////////////////////////////////////////////
    3.52 -// Module interface
    3.53 -/////////////////////////////////////////////////////
    3.54 -
    3.55 -(* syn_hier="hard" *) module jtag_cores (
    3.56 +module jtag_cores (
    3.57      // ----- Inputs -------
    3.58      reg_d,
    3.59      reg_addr_d,
    3.60 @@ -58,19 +10,11 @@
    3.61      reg_addr_q,
    3.62      jtck,
    3.63      jrstn
    3.64 -    );
    3.65 -    
    3.66 -/////////////////////////////////////////////////////
    3.67 -// Inputs
    3.68 -/////////////////////////////////////////////////////
    3.69 +);
    3.70  
    3.71  input [7:0] reg_d;
    3.72  input [2:0] reg_addr_d;
    3.73  
    3.74 -/////////////////////////////////////////////////////
    3.75 -// Outputs
    3.76 -/////////////////////////////////////////////////////
    3.77 -   
    3.78  output reg_update;
    3.79  wire   reg_update;
    3.80  output [7:0] reg_q;
    3.81 @@ -79,47 +23,16 @@
    3.82  wire   [2:0] reg_addr_q;
    3.83  
    3.84  output jtck;
    3.85 -wire   jtck; 	/* synthesis syn_keep=1 */
    3.86 +wire   jtck;
    3.87  output jrstn;
    3.88 -wire   jrstn;  /* synthesis syn_keep=1 */	
    3.89 -
    3.90 -/////////////////////////////////////////////////////
    3.91 -// Instantiations
    3.92 -/////////////////////////////////////////////////////
    3.93 +wire   jrstn;
    3.94  
    3.95 -wire jtdi;          /* synthesis syn_keep=1 */
    3.96 -wire er2_tdo2;      /* synthesis syn_keep=1 */
    3.97 -wire jshift;        /* synthesis syn_keep=1 */
    3.98 -wire jupdate;       /* synthesis syn_keep=1 */
    3.99 -wire jce2;          /* synthesis syn_keep=1 */
   3.100 -wire ip_enable;     /* synthesis syn_keep=1 */
   3.101 -    
   3.102 -(* JTAG_IP="LM32", IP_ID="0", HUB_ID="0", syn_noprune=1 *) jtagconn16 jtagconn16_lm32_inst (
   3.103 -    .er2_tdo        (er2_tdo2),
   3.104 -    .jtck           (jtck),
   3.105 -    .jtdi           (jtdi),
   3.106 -    .jshift         (jshift),
   3.107 -    .jupdate        (jupdate),
   3.108 -    .jrstn          (jrstn),
   3.109 -    .jce2           (jce2),
   3.110 -    .ip_enable      (ip_enable)
   3.111 -);
   3.112 -    
   3.113 -(* syn_noprune=1 *) jtag_lm32 jtag_lm32_inst (
   3.114 -    .JTCK           (jtck),
   3.115 -    .JTDI           (jtdi),
   3.116 -    .JTDO2          (er2_tdo2),
   3.117 -    .JSHIFT         (jshift),
   3.118 -    .JUPDATE        (jupdate),
   3.119 -    .JRSTN          (jrstn),
   3.120 -    .JCE2           (jce2),
   3.121 -    .JTAGREG_ENABLE (ip_enable),
   3.122 -    .CONTROL_DATAN  (),
   3.123 -    .REG_UPDATE     (reg_update),
   3.124 -    .REG_D          (reg_d),
   3.125 -    .REG_ADDR_D     (reg_addr_d),
   3.126 -    .REG_Q          (reg_q),
   3.127 -    .REG_ADDR_Q     (reg_addr_q)
   3.128 -    );
   3.129 +assign reg_d = 8'hxx;
   3.130 +assign reg_addr_d = 3'bxxx;
   3.131 +assign reg_update = 1'b0;
   3.132 +assign reg_q = 8'hxx;
   3.133 +assign reg_addr_q = 3'bxxx;
   3.134 +assign jtck = 1'b0;
   3.135 +assign jrstn = 1'b1;
   3.136      
   3.137  endmodule

     4.1 --- a/jtag_lm32.v	Sun Mar 06 19:23:51 2011 +0000
     4.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
     4.3 @@ -1,200 +0,0 @@
     4.4 -// =============================================================================
     4.5 -//                           COPYRIGHT NOTICE
     4.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation
     4.7 -// ALL RIGHTS RESERVED
     4.8 -// This confidential and proprietary software may be used only as authorised by
     4.9 -// a licensing agreement from Lattice Semiconductor Corporation.
    4.10 -// The entire notice above must be reproduced on all authorized copies and
    4.11 -// copies may only be made to the extent permitted by a licensing agreement from
    4.12 -// Lattice Semiconductor Corporation.
    4.13 -//
    4.14 -// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
    4.15 -// 5555 NE Moore Court                            408-826-6000 (other locations)
    4.16 -// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
    4.17 -// U.S.A                                   email: techsupport@latticesemi.com
    4.18 -// =============================================================================/
    4.19 -//                         FILE DETAILS
    4.20 -// Project          : LatticeMico32
    4.21 -// File             : jtag_lm32.v
    4.22 -// Title            : JTAG data register for LM32 CPU debug interface
    4.23 -// Version          : 6.0.13
    4.24 -//                  : Initial Release
    4.25 -// Version          : 7.0SP2, 3.0
    4.26 -//                  : No Change
    4.27 -// Version          : 3.1
    4.28 -//                  : No Change
    4.29 -// =============================================================================
    4.30 -
    4.31 -/////////////////////////////////////////////////////
    4.32 -// Module interface
    4.33 -/////////////////////////////////////////////////////
    4.34 -
    4.35 -module jtag_lm32 (
    4.36 -	input JTCK,
    4.37 -	input JTDI,
    4.38 -	output JTDO2,
    4.39 -	input JSHIFT,
    4.40 -	input JUPDATE,
    4.41 -	input JRSTN,
    4.42 -	input JCE2,
    4.43 -	input JTAGREG_ENABLE,
    4.44 -	input CONTROL_DATAN,
    4.45 -	output REG_UPDATE,
    4.46 -	input [7:0] REG_D,
    4.47 -	input [2:0] REG_ADDR_D,
    4.48 -	output [7:0] REG_Q,
    4.49 -	output [2:0] REG_ADDR_Q
    4.50 -	);
    4.51 -
    4.52 -/////////////////////////////////////////////////////
    4.53 -// Internal nets and registers 
    4.54 -/////////////////////////////////////////////////////
    4.55 -
    4.56 -wire [9:0] tdibus;
    4.57 -
    4.58 -/////////////////////////////////////////////////////
    4.59 -// Instantiations
    4.60 -/////////////////////////////////////////////////////
    4.61 -   
    4.62 -TYPEA DATA_BIT0 (
    4.63 -    .CLK(JTCK),
    4.64 -    .RESET_N(JRSTN),
    4.65 -    .CLKEN(clk_enable),
    4.66 -    .TDI(JTDI),
    4.67 -    .TDO(tdibus[0]),
    4.68 -    .DATA_OUT(REG_Q[0]),
    4.69 -    .DATA_IN(REG_D[0]),
    4.70 -    .CAPTURE_DR(captureDr),
    4.71 -    .UPDATE_DR(JUPDATE)
    4.72 -    );
    4.73 -
    4.74 -TYPEA DATA_BIT1 (
    4.75 -    .CLK(JTCK),
    4.76 -    .RESET_N(JRSTN),
    4.77 -    .CLKEN(clk_enable),
    4.78 -    .TDI(tdibus[0]),
    4.79 -    .TDO(tdibus[1]),
    4.80 -    .DATA_OUT(REG_Q[1]),
    4.81 -    .DATA_IN(REG_D[1]),
    4.82 -    .CAPTURE_DR(captureDr),
    4.83 -    .UPDATE_DR(JUPDATE)
    4.84 -    );
    4.85 -
    4.86 -TYPEA DATA_BIT2 (
    4.87 -    .CLK(JTCK),
    4.88 -    .RESET_N(JRSTN),
    4.89 -    .CLKEN(clk_enable),
    4.90 -    .TDI(tdibus[1]),
    4.91 -    .TDO(tdibus[2]),
    4.92 -    .DATA_OUT(REG_Q[2]),
    4.93 -    .DATA_IN(REG_D[2]),
    4.94 -    .CAPTURE_DR(captureDr),
    4.95 -    .UPDATE_DR(JUPDATE)
    4.96 -    );
    4.97 -
    4.98 -TYPEA DATA_BIT3 (
    4.99 -    .CLK(JTCK),
   4.100 -    .RESET_N(JRSTN),
   4.101 -    .CLKEN(clk_enable),
   4.102 -    .TDI(tdibus[2]),
   4.103 -    .TDO(tdibus[3]),
   4.104 -    .DATA_OUT(REG_Q[3]),
   4.105 -    .DATA_IN(REG_D[3]),
   4.106 -    .CAPTURE_DR(captureDr),
   4.107 -    .UPDATE_DR(JUPDATE)
   4.108 -    );
   4.109 -
   4.110 -TYPEA DATA_BIT4 (
   4.111 -    .CLK(JTCK),
   4.112 -    .RESET_N(JRSTN),
   4.113 -    .CLKEN(clk_enable),
   4.114 -    .TDI(tdibus[3]),
   4.115 -    .TDO(tdibus[4]),
   4.116 -    .DATA_OUT(REG_Q[4]),
   4.117 -    .DATA_IN(REG_D[4]),
   4.118 -    .CAPTURE_DR(captureDr),
   4.119 -    .UPDATE_DR(JUPDATE)
   4.120 -    );
   4.121 -
   4.122 -TYPEA DATA_BIT5 (
   4.123 -    .CLK(JTCK),
   4.124 -    .RESET_N(JRSTN),
   4.125 -    .CLKEN(clk_enable),
   4.126 -    .TDI(tdibus[4]),
   4.127 -    .TDO(tdibus[5]),
   4.128 -    .DATA_OUT(REG_Q[5]),
   4.129 -    .DATA_IN(REG_D[5]),
   4.130 -    .CAPTURE_DR(captureDr),
   4.131 -    .UPDATE_DR(JUPDATE)
   4.132 -    );
   4.133 -
   4.134 -TYPEA DATA_BIT6 (
   4.135 -    .CLK(JTCK),
   4.136 -    .RESET_N(JRSTN),
   4.137 -    .CLKEN(clk_enable),
   4.138 -    .TDI(tdibus[5]),
   4.139 -    .TDO(tdibus[6]),
   4.140 -    .DATA_OUT(REG_Q[6]),
   4.141 -    .DATA_IN(REG_D[6]),
   4.142 -    .CAPTURE_DR(captureDr),
   4.143 -    .UPDATE_DR(JUPDATE)
   4.144 -    );
   4.145 -
   4.146 -TYPEA DATA_BIT7 (
   4.147 -    .CLK(JTCK),
   4.148 -    .RESET_N(JRSTN),
   4.149 -    .CLKEN(clk_enable),
   4.150 -    .TDI(tdibus[6]),
   4.151 -    .TDO(tdibus[7]),
   4.152 -    .DATA_OUT(REG_Q[7]),
   4.153 -    .DATA_IN(REG_D[7]),
   4.154 -    .CAPTURE_DR(captureDr),
   4.155 -    .UPDATE_DR(JUPDATE)
   4.156 -    );
   4.157 -
   4.158 -TYPEA ADDR_BIT0 (
   4.159 -    .CLK(JTCK),
   4.160 -    .RESET_N(JRSTN),
   4.161 -    .CLKEN(clk_enable),
   4.162 -    .TDI(tdibus[7]),
   4.163 -    .TDO(tdibus[8]),
   4.164 -    .DATA_OUT(REG_ADDR_Q[0]),
   4.165 -    .DATA_IN(REG_ADDR_D[0]),
   4.166 -    .CAPTURE_DR(captureDr),
   4.167 -    .UPDATE_DR(JUPDATE)
   4.168 -    );
   4.169 -
   4.170 -TYPEA ADDR_BIT1 (
   4.171 -    .CLK(JTCK),
   4.172 -    .RESET_N(JRSTN),
   4.173 -    .CLKEN(clk_enable),
   4.174 -    .TDI(tdibus[8]),
   4.175 -    .TDO(tdibus[9]),
   4.176 -    .DATA_OUT(REG_ADDR_Q[1]),
   4.177 -    .DATA_IN(REG_ADDR_D[1]),
   4.178 -    .CAPTURE_DR(captureDr),
   4.179 -    .UPDATE_DR(JUPDATE)
   4.180 -    );
   4.181 -
   4.182 -TYPEA ADDR_BIT2 (
   4.183 -    .CLK(JTCK),
   4.184 -    .RESET_N(JRSTN),
   4.185 -    .CLKEN(clk_enable),
   4.186 -    .TDI(tdibus[9]),
   4.187 -    .TDO(JTDO2),
   4.188 -    .DATA_OUT(REG_ADDR_Q[2]),
   4.189 -    .DATA_IN(REG_ADDR_D[2]),
   4.190 -    .CAPTURE_DR(captureDr),
   4.191 -    .UPDATE_DR(JUPDATE)
   4.192 -    );
   4.193 -
   4.194 -/////////////////////////////////////////////////////
   4.195 -// Combinational logic
   4.196 -/////////////////////////////////////////////////////
   4.197 -
   4.198 -assign clk_enable = JTAGREG_ENABLE & JCE2;
   4.199 -assign captureDr = !JSHIFT & JCE2;
   4.200 -// JCE2 is only active during shift
   4.201 -assign REG_UPDATE = JTAGREG_ENABLE & JUPDATE;
   4.202 - 
   4.203 -endmodule

     5.1 --- a/lm32_cpu.v	Sun Mar 06 19:23:51 2011 +0000
     5.2 +++ b/lm32_cpu.v	Sun Mar 06 19:31:09 2011 +0000
     5.3 @@ -1816,7 +1816,9 @@
     5.4                     ) 
     5.5  		|| (   (   (eret_d == `TRUE)
     5.6  			|| (scall_d == `TRUE)
     5.7 +`ifdef CFG_BUS_ERRORS_ENABLED
     5.8  			|| (bus_error_d == `TRUE)
     5.9 +`endif
    5.10  		       )
    5.11  		    && (   (load_q_x == `TRUE)
    5.12  			|| (load_q_m == `TRUE)

     6.1 --- a/lm32_include.v	Sun Mar 06 19:23:51 2011 +0000
     6.2 +++ b/lm32_include.v	Sun Mar 06 19:31:09 2011 +0000
     6.3 @@ -336,7 +336,6 @@
     6.4  
     6.5  // Whether to include context registers for debug exceptions
     6.6  // in addition to standard exception handling registers
     6.7 -// Bizarre - Removing this increases LUT count!
     6.8  `define CFG_DEBUG_EXCEPTIONS_ENABLED
     6.9  
    6.10  // Wishbone defines

     7.1 --- a/lm32_jtag.v	Sun Mar 06 19:23:51 2011 +0000
     7.2 +++ b/lm32_jtag.v	Sun Mar 06 19:31:09 2011 +0000
     7.3 @@ -103,8 +103,6 @@
     7.4      jtag_reg_addr_d
     7.5      );
     7.6  
     7.7 -   parameter lat_family = `LATTICE_FAMILY;
     7.8 -   
     7.9  /////////////////////////////////////////////////////
    7.10  // Inputs
    7.11  /////////////////////////////////////////////////////

     8.1 --- a/lm32_monitor.v	Sun Mar 06 19:23:51 2011 +0000
     8.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
     8.3 @@ -1,167 +0,0 @@
     8.4 -// =============================================================================
     8.5 -//                           COPYRIGHT NOTICE
     8.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation
     8.7 -// ALL RIGHTS RESERVED
     8.8 -// This confidential and proprietary software may be used only as authorised by
     8.9 -// a licensing agreement from Lattice Semiconductor Corporation.
    8.10 -// The entire notice above must be reproduced on all authorized copies and
    8.11 -// copies may only be made to the extent permitted by a licensing agreement from
    8.12 -// Lattice Semiconductor Corporation.
    8.13 -//
    8.14 -// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
    8.15 -// 5555 NE Moore Court                            408-826-6000 (other locations)
    8.16 -// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
    8.17 -// U.S.A                                   email: techsupport@latticesemi.com
    8.18 -// =============================================================================/
    8.19 -//                         FILE DETAILS
    8.20 -// Project          : LatticeMico32
    8.21 -// File             : lm32_monitor.v
    8.22 -// Title            : Debug monitor memory Wishbone interface
    8.23 -// Version          : 6.1.17
    8.24 -//                  : Initial Release
    8.25 -// Version          : 7.0SP2, 3.0
    8.26 -//                  : No Change
    8.27 -// Version          : 3.3
    8.28 -//                  : Removed port mismatch in instantiation of module
    8.29 -//                  : lm32_monitor_ram.
    8.30 -// =============================================================================
    8.31 -
    8.32 -`include "system_conf.v"
    8.33 -`include "lm32_include.v"
    8.34 -
    8.35 -/////////////////////////////////////////////////////
    8.36 -// Module interface
    8.37 -/////////////////////////////////////////////////////
    8.38 -
    8.39 -module lm32_monitor (
    8.40 -    // ----- Inputs -------
    8.41 -    clk_i, 
    8.42 -    rst_i,
    8.43 -    MON_ADR_I,
    8.44 -    MON_CYC_I,
    8.45 -    MON_DAT_I,
    8.46 -    MON_SEL_I,
    8.47 -    MON_STB_I,
    8.48 -    MON_WE_I,
    8.49 -    // ----- Outputs -------
    8.50 -    MON_ACK_O,
    8.51 -    MON_RTY_O,
    8.52 -    MON_DAT_O,
    8.53 -    MON_ERR_O
    8.54 -    );
    8.55 -
    8.56 -/////////////////////////////////////////////////////
    8.57 -// Inputs
    8.58 -/////////////////////////////////////////////////////
    8.59 -
    8.60 -input clk_i;                                        // Wishbone clock
    8.61 -input rst_i;                                        // Wishbone reset
    8.62 -input [10:2] MON_ADR_I;                             // Wishbone address
    8.63 -input MON_STB_I;                                    // Wishbone strobe
    8.64 -input MON_CYC_I;                                    // Wishbone cycle
    8.65 -input [`LM32_WORD_RNG] MON_DAT_I;                   // Wishbone write data
    8.66 -input [`LM32_BYTE_SELECT_RNG] MON_SEL_I;            // Wishbone byte select
    8.67 -input MON_WE_I;                                     // Wishbone write enable
    8.68 -   
    8.69 -/////////////////////////////////////////////////////
    8.70 -// Outputs
    8.71 -/////////////////////////////////////////////////////
    8.72 -
    8.73 -output MON_ACK_O;                                   // Wishbone acknowlege
    8.74 -reg    MON_ACK_O;
    8.75 -output [`LM32_WORD_RNG] MON_DAT_O;                  // Wishbone data output
    8.76 -reg    [`LM32_WORD_RNG] MON_DAT_O;
    8.77 -output MON_RTY_O;                                   // Wishbone retry
    8.78 -wire   MON_RTY_O;       
    8.79 -output MON_ERR_O;                                   // Wishbone error
    8.80 -wire   MON_ERR_O;
    8.81 -   
    8.82 -/////////////////////////////////////////////////////
    8.83 -// Internal nets and registers 
    8.84 -/////////////////////////////////////////////////////
    8.85 -
    8.86 -reg [1:0] state;                                    // Current state of FSM
    8.87 -wire [`LM32_WORD_RNG] data, dataB;                  // Data read from RAM
    8.88 -reg write_enable;                                   // RAM write enable
    8.89 -reg [`LM32_WORD_RNG] write_data;                    // RAM write data
    8.90 - 
    8.91 -/////////////////////////////////////////////////////
    8.92 -// Instantiations
    8.93 -/////////////////////////////////////////////////////
    8.94 -
    8.95 -lm32_monitor_ram ram (
    8.96 -    // ----- Inputs -------
    8.97 -    .ClockA             (clk_i),
    8.98 -    .ClockB             (clk_i),
    8.99 -    .ResetA             (rst_i),
   8.100 -    .ResetB             (rst_i),
   8.101 -    .ClockEnA           (`TRUE),
   8.102 -    .ClockEnB           (`FALSE),
   8.103 -    .AddressA           (MON_ADR_I[10:2]),
   8.104 -    .AddressB           (9'b0),
   8.105 -    .DataInA            (write_data),
   8.106 -    .DataInB            (32'b0),
   8.107 -    .WrA                (write_enable),
   8.108 -    .WrB                (`FALSE),
   8.109 -    // ----- Outputs -------
   8.110 -    .QA                 (data),
   8.111 -    .QB                 (dataB)
   8.112 -    );
   8.113 -
   8.114 -/////////////////////////////////////////////////////
   8.115 -// Combinational Logic
   8.116 -/////////////////////////////////////////////////////
   8.117 -
   8.118 -assign MON_RTY_O = `FALSE;
   8.119 -assign MON_ERR_O = `FALSE;
   8.120 -
   8.121 -/////////////////////////////////////////////////////
   8.122 -// Sequential Logic
   8.123 -/////////////////////////////////////////////////////
   8.124 -
   8.125 -always @(posedge clk_i `CFG_RESET_SENSITIVITY)
   8.126 -begin
   8.127 -    if (rst_i == `TRUE)
   8.128 -    begin
   8.129 -        write_enable <= `FALSE;
   8.130 -        MON_ACK_O <= `FALSE;
   8.131 -        MON_DAT_O <= {`LM32_WORD_WIDTH{1'bx}};
   8.132 -        state <= 2'b00;
   8.133 -    end
   8.134 -    else
   8.135 -    begin
   8.136 -        case (state)
   8.137 -        2'b00:
   8.138 -        begin
   8.139 -            // Wait for a Wishbone access
   8.140 -            if ((MON_STB_I == `TRUE) && (MON_CYC_I == `TRUE))
   8.141 -                state <= 2'b01;
   8.142 -        end
   8.143 -        2'b01:
   8.144 -        begin
   8.145 -            // Output read data to Wishbone
   8.146 -            MON_ACK_O <= `TRUE;
   8.147 -            MON_DAT_O <= data;
   8.148 -            // Sub-word writes are performed using read-modify-write  
   8.149 -            // as the Lattice EBRs don't support byte enables
   8.150 -            if (MON_WE_I == `TRUE)
   8.151 -                write_enable <= `TRUE;
   8.152 -            write_data[7:0] <= MON_SEL_I[0] ? MON_DAT_I[7:0] : data[7:0];
   8.153 -            write_data[15:8] <= MON_SEL_I[1] ? MON_DAT_I[15:8] : data[15:8];
   8.154 -            write_data[23:16] <= MON_SEL_I[2] ? MON_DAT_I[23:16] : data[23:16];
   8.155 -            write_data[31:24] <= MON_SEL_I[3] ? MON_DAT_I[31:24] : data[31:24];
   8.156 -            state <= 2'b10;
   8.157 -        end
   8.158 -        2'b10:
   8.159 -        begin
   8.160 -            // Wishbone access occurs in this cycle
   8.161 -            write_enable <= `FALSE;
   8.162 -            MON_ACK_O <= `FALSE;
   8.163 -            MON_DAT_O <= {`LM32_WORD_WIDTH{1'bx}};
   8.164 -            state <= 2'b00;
   8.165 -        end
   8.166 -        endcase        
   8.167 -    end
   8.168 -end
   8.169 -
   8.170 -endmodule

     9.1 --- a/lm32_monitor_ram.v	Sun Mar 06 19:23:51 2011 +0000
     9.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
     9.3 @@ -1,1682 +0,0 @@
     9.4 -// =============================================================================
     9.5 -//                           COPYRIGHT NOTICE
     9.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation
     9.7 -// ALL RIGHTS RESERVED
     9.8 -// This confidential and proprietary software may be used only as authorised by
     9.9 -// a licensing agreement from Lattice Semiconductor Corporation.
    9.10 -// The entire notice above must be reproduced on all authorized copies and
    9.11 -// copies may only be made to the extent permitted by a licensing agreement from
    9.12 -// Lattice Semiconductor Corporation.
    9.13 -//
    9.14 -// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
    9.15 -// 5555 NE Moore Court                            408-826-6000 (other locations)
    9.16 -// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
    9.17 -// U.S.A                                   email: techsupport@latticesemi.com
    9.18 -// =============================================================================/
    9.19 -//                         FILE DETAILS
    9.20 -// Project          : LatticeMico32
    9.21 -// File             : lm32_monitor_ram.v
    9.22 -// Title            : LM32 monitor RAM, hold the load/monitor code
    9.23 -// Dependencies     : system_conf.v
    9.24 -// Version          : 6.1.17
    9.25 -//                  : Initial Release
    9.26 -// Version          : version 7.0 (7.0SP2)
    9.27 -//                  : No Change
    9.28 -//                  : version 7.1: updated to fix r0 not being zero
    9.29 -//                  :     when hitting a breakpoint (CR 38134)
    9.30 -//                  : version 7.2: updated to also store ip/im registers
    9.31 -//                  :     and update im register when restoring stack
    9.32 -// =============================================================================
    9.33 -`include "system_conf.v"
    9.34 -
    9.35 -`timescale 1 ns / 1 ps
    9.36 -module lm32_monitor_ram (DataInA, DataInB, AddressA, AddressB, ClockA, 
    9.37 -			 ClockB, ClockEnA, ClockEnB, WrA, WrB, ResetA, ResetB, QA, QB);
    9.38 -   input [31:0] DataInA;
    9.39 -   input [31:0] DataInB;
    9.40 -   input [8:0] 	AddressA;
    9.41 -   input [8:0] 	AddressB;
    9.42 -   input 	ClockA;
    9.43 -   input 	ClockB;
    9.44 -   input 	ClockEnA;
    9.45 -   input 	ClockEnB;
    9.46 -   input 	WrA;
    9.47 -   input 	WrB;
    9.48 -   input 	ResetA;
    9.49 -   input 	ResetB;
    9.50 -   output [31:0] QA;
    9.51 -   output [31:0] QB;
    9.52 -
    9.53 -   parameter 	 lat_family = `LATTICE_FAMILY;
    9.54 -   
    9.55 -   generate
    9.56 -      if (lat_family == "ECP3") begin
    9.57 -
    9.58 -/* Verilog netlist generated by SCUBA ispLever_v8.0_ALPHA (69) */
    9.59 -/* Module Version: 7.0 */
    9.60 -/* c:\ispTOOLS8_0\ispFPGA\bin\nt\scuba.exe -w -lang verilog -synth synplify -bus_exp 7 -bb -arch ep5c00 -type bram -wp 11 -rp 1010 -addr_width 9 -data_width 32 -num_rows 512 -gsr DISABLED -writemode NORMAL -resetmode SYNC -memfile ../../lm32_monitor.mem -memformat hex -n lm32_monitor_ram -e  */
    9.61 -/* Tue Jun 16 18:01:57 2009 */
    9.62 -
    9.63 -    defparam lm32_monitor_ram_0_0_1.INITVAL_3F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
    9.64 -    defparam lm32_monitor_ram_0_0_1.INITVAL_3E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
    9.65 -    defparam lm32_monitor_ram_0_0_1.INITVAL_3D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
    9.66 -    defparam lm32_monitor_ram_0_0_1.INITVAL_3C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
    9.67 -    defparam lm32_monitor_ram_0_0_1.INITVAL_3B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
    9.68 -    defparam lm32_monitor_ram_0_0_1.INITVAL_3A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
    9.69 -    defparam lm32_monitor_ram_0_0_1.INITVAL_39 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
    9.70 -    defparam lm32_monitor_ram_0_0_1.INITVAL_38 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
    9.71 -    defparam lm32_monitor_ram_0_0_1.INITVAL_37 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
    9.72 -    defparam lm32_monitor_ram_0_0_1.INITVAL_36 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
    9.73 -    defparam lm32_monitor_ram_0_0_1.INITVAL_35 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
    9.74 -    defparam lm32_monitor_ram_0_0_1.INITVAL_34 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
    9.75 -    defparam lm32_monitor_ram_0_0_1.INITVAL_33 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
    9.76 -    defparam lm32_monitor_ram_0_0_1.INITVAL_32 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
    9.77 -    defparam lm32_monitor_ram_0_0_1.INITVAL_31 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
    9.78 -    defparam lm32_monitor_ram_0_0_1.INITVAL_30 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
    9.79 -    defparam lm32_monitor_ram_0_0_1.INITVAL_2F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
    9.80 -    defparam lm32_monitor_ram_0_0_1.INITVAL_2E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
    9.81 -    defparam lm32_monitor_ram_0_0_1.INITVAL_2D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
    9.82 -    defparam lm32_monitor_ram_0_0_1.INITVAL_2C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
    9.83 -    defparam lm32_monitor_ram_0_0_1.INITVAL_2B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
    9.84 -    defparam lm32_monitor_ram_0_0_1.INITVAL_2A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
    9.85 -    defparam lm32_monitor_ram_0_0_1.INITVAL_29 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
    9.86 -    defparam lm32_monitor_ram_0_0_1.INITVAL_28 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
    9.87 -    defparam lm32_monitor_ram_0_0_1.INITVAL_27 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
    9.88 -    defparam lm32_monitor_ram_0_0_1.INITVAL_26 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
    9.89 -    defparam lm32_monitor_ram_0_0_1.INITVAL_25 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
    9.90 -    defparam lm32_monitor_ram_0_0_1.INITVAL_24 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
    9.91 -    defparam lm32_monitor_ram_0_0_1.INITVAL_23 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
    9.92 -    defparam lm32_monitor_ram_0_0_1.INITVAL_22 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
    9.93 -    defparam lm32_monitor_ram_0_0_1.INITVAL_21 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
    9.94 -    defparam lm32_monitor_ram_0_0_1.INITVAL_20 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
    9.95 -    defparam lm32_monitor_ram_0_0_1.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
    9.96 -    defparam lm32_monitor_ram_0_0_1.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
    9.97 -    defparam lm32_monitor_ram_0_0_1.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
    9.98 -    defparam lm32_monitor_ram_0_0_1.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
    9.99 -    defparam lm32_monitor_ram_0_0_1.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
   9.100 -    defparam lm32_monitor_ram_0_0_1.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
   9.101 -    defparam lm32_monitor_ram_0_0_1.INITVAL_19 = "0x0000000000000000000000000000000000000000000000000000000000000000000000000003FF81" ;
   9.102 -    defparam lm32_monitor_ram_0_0_1.INITVAL_18 = "0x300003FF83300003FF85300003FF873FF4A1004F3FF8A300003FF8C300003FF8E300003FF9030000" ;
   9.103 -    defparam lm32_monitor_ram_0_0_1.INITVAL_17 = "0x3FF92300003FF94300003FF96300003FFC100800070003FFFB0000130001100003FF5B1001700000" ;
   9.104 -    defparam lm32_monitor_ram_0_0_1.INITVAL_16 = "0x068003FF70058003FF723FFFB300013FF6A00001100001FFAB00000068003FF7B058003FF7D3FFB1" ;
   9.105 -    defparam lm32_monitor_ram_0_0_1.INITVAL_15 = "0x3FF8D008003FFB4300000FFB61001B000361001A0002F10019000381001800038100130003310012" ;
   9.106 -    defparam lm32_monitor_ram_0_0_1.INITVAL_14 = "0x00033100110003310010000331000900033100080003310007010003FF89058003FF9C3FFF900800" ;
   9.107 -    defparam lm32_monitor_ram_0_0_1.INITVAL_13 = "0x070000FFFB30800070003FFD63FFB200800000041000A0004110006010003FF9A000000002410004" ;
   9.108 -    defparam lm32_monitor_ram_0_0_1.INITVAL_12 = "0x200081000C0001030014200181001C00020300240000000000000001000000000000000000010000" ;
   9.109 -    defparam lm32_monitor_ram_0_0_1.INITVAL_11 = "0x100010FFF310063000501004D000471006D00046100720002C100570001F10077010003FFBC00000" ;
   9.110 -    defparam lm32_monitor_ram_0_0_1.INITVAL_10 = "0x30000044003FC0010000100540FFFF0080010000100540FFFF008000880010004200081000C00010" ;
   9.111 -    defparam lm32_monitor_ram_0_0_1.INITVAL_0F = "0x30014200181001C00020300240FFDC0000000008100043FFDD100083FFDF100093FFE11000A3FFE3" ;
   9.112 -    defparam lm32_monitor_ram_0_0_1.INITVAL_0E = "0x1000B10008100040FFF8000000000C1000410008100083FFE7100093FFE91000A3FFEB1000B3FFED" ;
   9.113 -    defparam lm32_monitor_ram_0_0_1.INITVAL_0D = "0x100040FFF400000200000FFFF01000000000000210054100000FFFF01000100FF00000100FF00000" ;
   9.114 -    defparam lm32_monitor_ram_0_0_1.INITVAL_0C = "0x0FFFE1010001000000000007430084200002009830000300943000030090300003008C2007C10078" ;
   9.115 -    defparam lm32_monitor_ram_0_0_1.INITVAL_0B = "0x300702006C1006800064300602005C1005800054300502004C1004800044300402003C1003800034" ;
   9.116 -    defparam lm32_monitor_ram_0_0_1.INITVAL_0A = "0x300302002C1002800024300202001C1001800014300102000C100080000000074200842000020098" ;
   9.117 -    defparam lm32_monitor_ram_0_0_1.INITVAL_09 = "0x20000200942000020090200002008C3008010078300702006C1006800064300602005C1005800054" ;
   9.118 -    defparam lm32_monitor_ram_0_0_1.INITVAL_08 = "0x300502004C1004800044300402003C1003800034300302002C1002800024300202001C1001800014" ;
   9.119 -    defparam lm32_monitor_ram_0_0_1.INITVAL_07 = "0x300102000C10008000001F9A00E000000041007810000100881000110001100011000110001100FF" ;
   9.120 -    defparam lm32_monitor_ram_0_0_1.INITVAL_06 = "0x1F9A0100940080010090008001008C008001009C008001009800800300802007C00074300702006C" ;
   9.121 -    defparam lm32_monitor_ram_0_0_1.INITVAL_05 = "0x1006800064300602005C1005800054300502004C1004800044300402003C1003800034300302002C" ;
   9.122 -    defparam lm32_monitor_ram_0_0_1.INITVAL_04 = "0x1002800024300202001C1001800014300102000C100080000000000106603FFC530000007F40E000" ;
   9.123 -    defparam lm32_monitor_ram_0_0_1.INITVAL_03 = "0x0003E000BC1000400800200840000A000000000000046000C4100040080020084000120000000000" ;
   9.124 -    defparam lm32_monitor_ram_0_0_1.INITVAL_02 = "0x0004E000CC1000400800200840001A000000000000056000D4100040080020084000220000000000" ;
   9.125 -    defparam lm32_monitor_ram_0_0_1.INITVAL_01 = "0x00086000DC1000400800300840002A000000000000066000E4100040080020084000320000000000" ;
   9.126 -    defparam lm32_monitor_ram_0_0_1.INITVAL_00 = "0x00096000EC1000400800300840003A000000000000000000000000000000000000003E0000000000" ;
   9.127 -    defparam lm32_monitor_ram_0_0_1.CSDECODE_B = "0b000" ;
   9.128 -    defparam lm32_monitor_ram_0_0_1.CSDECODE_A = "0b000" ;
   9.129 -    defparam lm32_monitor_ram_0_0_1.WRITEMODE_B = "NORMAL" ;
   9.130 -    defparam lm32_monitor_ram_0_0_1.WRITEMODE_A = "NORMAL" ;
   9.131 -    defparam lm32_monitor_ram_0_0_1.GSR = "DISABLED" ;
   9.132 -    defparam lm32_monitor_ram_0_0_1.REGMODE_B = "NOREG" ;
   9.133 -    defparam lm32_monitor_ram_0_0_1.REGMODE_A = "NOREG" ;
   9.134 -    defparam lm32_monitor_ram_0_0_1.DATA_WIDTH_B = 18 ;
   9.135 -    defparam lm32_monitor_ram_0_0_1.DATA_WIDTH_A = 18 ;
   9.136 -    DP16KC lm32_monitor_ram_0_0_1 (.DIA0(DataInA[0]), .DIA1(DataInA[1]), 
   9.137 -        .DIA2(DataInA[2]), .DIA3(DataInA[3]), .DIA4(DataInA[4]), .DIA5(DataInA[5]), 
   9.138 -        .DIA6(DataInA[6]), .DIA7(DataInA[7]), .DIA8(DataInA[8]), .DIA9(DataInA[9]), 
   9.139 -        .DIA10(DataInA[10]), .DIA11(DataInA[11]), .DIA12(DataInA[12]), .DIA13(DataInA[13]), 
   9.140 -        .DIA14(DataInA[14]), .DIA15(DataInA[15]), .DIA16(DataInA[16]), .DIA17(DataInA[17]), 
   9.141 -        .ADA0(scuba_vhi), .ADA1(scuba_vhi), .ADA2(scuba_vlo), .ADA3(scuba_vlo), 
   9.142 -        .ADA4(AddressA[0]), .ADA5(AddressA[1]), .ADA6(AddressA[2]), .ADA7(AddressA[3]), 
   9.143 -        .ADA8(AddressA[4]), .ADA9(AddressA[5]), .ADA10(AddressA[6]), .ADA11(AddressA[7]), 
   9.144 -        .ADA12(AddressA[8]), .ADA13(scuba_vlo), .CEA(ClockEnA), .CLKA(ClockA), 
   9.145 -        .OCEA(ClockEnA), .WEA(WrA), .CSA0(scuba_vlo), .CSA1(scuba_vlo), 
   9.146 -        .CSA2(scuba_vlo), .RSTA(ResetA), .DIB0(DataInB[0]), .DIB1(DataInB[1]), 
   9.147 -        .DIB2(DataInB[2]), .DIB3(DataInB[3]), .DIB4(DataInB[4]), .DIB5(DataInB[5]), 
   9.148 -        .DIB6(DataInB[6]), .DIB7(DataInB[7]), .DIB8(DataInB[8]), .DIB9(DataInB[9]), 
   9.149 -        .DIB10(DataInB[10]), .DIB11(DataInB[11]), .DIB12(DataInB[12]), .DIB13(DataInB[13]), 
   9.150 -        .DIB14(DataInB[14]), .DIB15(DataInB[15]), .DIB16(DataInB[16]), .DIB17(DataInB[17]), 
   9.151 -        .ADB0(scuba_vhi), .ADB1(scuba_vhi), .ADB2(scuba_vlo), .ADB3(scuba_vlo), 
   9.152 -        .ADB4(AddressB[0]), .ADB5(AddressB[1]), .ADB6(AddressB[2]), .ADB7(AddressB[3]), 
   9.153 -        .ADB8(AddressB[4]), .ADB9(AddressB[5]), .ADB10(AddressB[6]), .ADB11(AddressB[7]), 
   9.154 -        .ADB12(AddressB[8]), .ADB13(scuba_vlo), .CEB(ClockEnB), .CLKB(ClockB), 
   9.155 -        .OCEB(ClockEnB), .WEB(WrB), .CSB0(scuba_vlo), .CSB1(scuba_vlo), 
   9.156 -        .CSB2(scuba_vlo), .RSTB(ResetB), .DOA0(QA[0]), .DOA1(QA[1]), .DOA2(QA[2]), 
   9.157 -        .DOA3(QA[3]), .DOA4(QA[4]), .DOA5(QA[5]), .DOA6(QA[6]), .DOA7(QA[7]), 
   9.158 -        .DOA8(QA[8]), .DOA9(QA[9]), .DOA10(QA[10]), .DOA11(QA[11]), .DOA12(QA[12]), 
   9.159 -        .DOA13(QA[13]), .DOA14(QA[14]), .DOA15(QA[15]), .DOA16(QA[16]), 
   9.160 -        .DOA17(QA[17]), .DOB0(QB[0]), .DOB1(QB[1]), .DOB2(QB[2]), .DOB3(QB[3]), 
   9.161 -        .DOB4(QB[4]), .DOB5(QB[5]), .DOB6(QB[6]), .DOB7(QB[7]), .DOB8(QB[8]), 
   9.162 -        .DOB9(QB[9]), .DOB10(QB[10]), .DOB11(QB[11]), .DOB12(QB[12]), .DOB13(QB[13]), 
   9.163 -        .DOB14(QB[14]), .DOB15(QB[15]), .DOB16(QB[16]), .DOB17(QB[17]))
   9.164 -             /* synthesis MEM_LPC_FILE="lm32_monitor_ram.lpc" */
   9.165 -             /* synthesis MEM_INIT_FILE="lm32_monitor.mem" */
   9.166 -             /* synthesis RESETMODE="SYNC" */;
   9.167 -
   9.168 -    VHI scuba_vhi_inst (.Z(scuba_vhi));
   9.169 -
   9.170 -    VLO scuba_vlo_inst (.Z(scuba_vlo));
   9.171 -
   9.172 -    defparam lm32_monitor_ram_0_1_0.INITVAL_3F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
   9.173 -    defparam lm32_monitor_ram_0_1_0.INITVAL_3E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
   9.174 -    defparam lm32_monitor_ram_0_1_0.INITVAL_3D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
   9.175 -    defparam lm32_monitor_ram_0_1_0.INITVAL_3C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
   9.176 -    defparam lm32_monitor_ram_0_1_0.INITVAL_3B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
   9.177 -    defparam lm32_monitor_ram_0_1_0.INITVAL_3A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
   9.178 -    defparam lm32_monitor_ram_0_1_0.INITVAL_39 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
   9.179 -    defparam lm32_monitor_ram_0_1_0.INITVAL_38 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
   9.180 -    defparam lm32_monitor_ram_0_1_0.INITVAL_37 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
   9.181 -    defparam lm32_monitor_ram_0_1_0.INITVAL_36 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
   9.182 -    defparam lm32_monitor_ram_0_1_0.INITVAL_35 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
   9.183 -    defparam lm32_monitor_ram_0_1_0.INITVAL_34 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
   9.184 -    defparam lm32_monitor_ram_0_1_0.INITVAL_33 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
   9.185 -    defparam lm32_monitor_ram_0_1_0.INITVAL_32 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
   9.186 -    defparam lm32_monitor_ram_0_1_0.INITVAL_31 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
   9.187 -    defparam lm32_monitor_ram_0_1_0.INITVAL_30 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
   9.188 -    defparam lm32_monitor_ram_0_1_0.INITVAL_2F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
   9.189 -    defparam lm32_monitor_ram_0_1_0.INITVAL_2E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
   9.190 -    defparam lm32_monitor_ram_0_1_0.INITVAL_2D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
   9.191 -    defparam lm32_monitor_ram_0_1_0.INITVAL_2C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
   9.192 -    defparam lm32_monitor_ram_0_1_0.INITVAL_2B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
   9.193 -    defparam lm32_monitor_ram_0_1_0.INITVAL_2A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
   9.194 -    defparam lm32_monitor_ram_0_1_0.INITVAL_29 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
   9.195 -    defparam lm32_monitor_ram_0_1_0.INITVAL_28 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
   9.196 -    defparam lm32_monitor_ram_0_1_0.INITVAL_27 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
   9.197 -    defparam lm32_monitor_ram_0_1_0.INITVAL_26 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
   9.198 -    defparam lm32_monitor_ram_0_1_0.INITVAL_25 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
   9.199 -    defparam lm32_monitor_ram_0_1_0.INITVAL_24 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
   9.200 -    defparam lm32_monitor_ram_0_1_0.INITVAL_23 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
   9.201 -    defparam lm32_monitor_ram_0_1_0.INITVAL_22 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
   9.202 -    defparam lm32_monitor_ram_0_1_0.INITVAL_21 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
   9.203 -    defparam lm32_monitor_ram_0_1_0.INITVAL_20 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
   9.204 -    defparam lm32_monitor_ram_0_1_0.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
   9.205 -    defparam lm32_monitor_ram_0_1_0.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
   9.206 -    defparam lm32_monitor_ram_0_1_0.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
   9.207 -    defparam lm32_monitor_ram_0_1_0.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
   9.208 -    defparam lm32_monitor_ram_0_1_0.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
   9.209 -    defparam lm32_monitor_ram_0_1_0.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
   9.210 -    defparam lm32_monitor_ram_0_1_0.INITVAL_19 = "0x000000000000000000000000000000000000000000000000000000000000000000000000000038FF" ;
   9.211 -    defparam lm32_monitor_ram_0_1_0.INITVAL_18 = "0x034D2038FF034C2038FF0349A038FF03EFF00D00038FF034CA038FF03492038FF0348A038FF03482" ;
   9.212 -    defparam lm32_monitor_ram_0_1_0.INITVAL_17 = "0x038FF0344A038FF03442038FF0343A038FF02E7002430038FF00D6300D5A00C5803EFF0136300D03" ;
   9.213 -    defparam lm32_monitor_ram_0_1_0.INITVAL_16 = "0x02E0803EFF02E0803EFF038FF00D5A03EFF00D63010580136300D0302E0803EFF02E0803EFF038FF" ;
   9.214 -    defparam lm32_monitor_ram_0_1_0.INITVAL_15 = "0x03EFF02E88038FF034DA0170801F100110801F100110801F100110801F100110801F100110801F10" ;
   9.215 -    defparam lm32_monitor_ram_0_1_0.INITVAL_14 = "0x0110801F100110801F100110801F100110801F100110801F0802E0803EFF02E0803EFF038FF02E70" ;
   9.216 -    defparam lm32_monitor_ram_0_1_0.INITVAL_13 = "0x024500110C0287302430038FF03EFF02E700110801F100110801F0802E0803EFF030E800DE700AE7" ;
   9.217 -    defparam lm32_monitor_ram_0_1_0.INITVAL_12 = "0x00AE400AE400AE400AE300AE300AE300AE300AE200D0000D0000D000342000D0000D0000D0003418" ;
   9.218 -    defparam lm32_monitor_ram_0_1_0.INITVAL_11 = "0x00D000170801F100110801F100110801F100110801F100110801F100110801F0802E0803EFF00E84" ;
   9.219 -    defparam lm32_monitor_ram_0_1_0.INITVAL_10 = "0x00E7B01E0401E030347000D0001708024700347000D00017080247002E08016E7016E4016E4016E4" ;
   9.220 -    defparam lm32_monitor_ram_0_1_0.INITVAL_0F = "0x016E3016E3016E3016E3016E200DE7030E800DE700AE703EFF010E003EFF010E003EFF010E003EFF" ;
   9.221 -    defparam lm32_monitor_ram_0_1_0.INITVAL_0E = "0x010E0016E0016E700DE7030E800DE700AE700AE000CE003EFF00CE003EFF00CE003EFF00CE003EFF" ;
   9.222 -    defparam lm32_monitor_ram_0_1_0.INITVAL_0D = "0x016E700DE7030E8034700171002470030E80110801F0803470017100247000808030E80081003478" ;
   9.223 -    defparam lm32_monitor_ram_0_1_0.INITVAL_0C = "0x011080081002478030F800AE700AE70340F00AE70340700AE70344F00AE70343F00AE700AE700AE7" ;
   9.224 -    defparam lm32_monitor_ram_0_1_0.INITVAL_0B = "0x00AE600AE600AE600AE600AE500AE500AE500AE500AE400AE400AE400AE400AE300AE300AE300AE3" ;
   9.225 -    defparam lm32_monitor_ram_0_1_0.INITVAL_0A = "0x00AE200AE200AE200AE200AE100AE100AE100AE100AE000AE000AE0030F000AE700AE70340F00AE7" ;
   9.226 -    defparam lm32_monitor_ram_0_1_0.INITVAL_09 = "0x0340700AE70344F00AE70343F00AE700AE700AE700AE600AE600AE600AE600AE500AE500AE500AE5" ;
   9.227 -    defparam lm32_monitor_ram_0_1_0.INITVAL_08 = "0x00AE400AE400AE400AE400AE300AE300AE300AE300AE200AE200AE200AE200AE100AE100AE100AE1" ;
   9.228 -    defparam lm32_monitor_ram_0_1_0.INITVAL_07 = "0x00AE000AE000AE0030E800DEF02EE8016E8016E800AE8016E8000080000800008000080000800808" ;
   9.229 -    defparam lm32_monitor_ram_0_1_0.INITVAL_06 = "0x00DE8016E802400016E802448016E802438016E802410016E802408016EF016EF016EF016EE016EE" ;
   9.230 -    defparam lm32_monitor_ram_0_1_0.INITVAL_05 = "0x016EE016EE016ED016ED016ED016ED016EC016EC016EC016EC016EB016EB016EB016EB016EA016EA" ;
   9.231 -    defparam lm32_monitor_ram_0_1_0.INITVAL_04 = "0x016EA016EA016E9016E9016E9016E9016E8016E8016E802600016E800DEF038FF00D0700DE702EE8" ;
   9.232 -    defparam lm32_monitor_ram_0_1_0.INITVAL_03 = "0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600" ;
   9.233 -    defparam lm32_monitor_ram_0_1_0.INITVAL_02 = "0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600" ;
   9.234 -    defparam lm32_monitor_ram_0_1_0.INITVAL_01 = "0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600" ;
   9.235 -    defparam lm32_monitor_ram_0_1_0.INITVAL_00 = "0x0380003E0000D0802EE0016E703E0002EE80260000D0000D0000D0000D0000D0003E000340802600" ;
   9.236 -    defparam lm32_monitor_ram_0_1_0.CSDECODE_B = "0b000" ;
   9.237 -    defparam lm32_monitor_ram_0_1_0.CSDECODE_A = "0b000" ;
   9.238 -    defparam lm32_monitor_ram_0_1_0.WRITEMODE_B = "NORMAL" ;
   9.239 -    defparam lm32_monitor_ram_0_1_0.WRITEMODE_A = "NORMAL" ;
   9.240 -    defparam lm32_monitor_ram_0_1_0.GSR = "DISABLED" ;
   9.241 -    defparam lm32_monitor_ram_0_1_0.REGMODE_B = "NOREG" ;
   9.242 -    defparam lm32_monitor_ram_0_1_0.REGMODE_A = "NOREG" ;
   9.243 -    defparam lm32_monitor_ram_0_1_0.DATA_WIDTH_B = 18 ;
   9.244 -    defparam lm32_monitor_ram_0_1_0.DATA_WIDTH_A = 18 ;
   9.245 -    DP16KC lm32_monitor_ram_0_1_0 (.DIA0(DataInA[18]), .DIA1(DataInA[19]), 
   9.246 -        .DIA2(DataInA[20]), .DIA3(DataInA[21]), .DIA4(DataInA[22]), .DIA5(DataInA[23]), 
   9.247 -        .DIA6(DataInA[24]), .DIA7(DataInA[25]), .DIA8(DataInA[26]), .DIA9(DataInA[27]), 
   9.248 -        .DIA10(DataInA[28]), .DIA11(DataInA[29]), .DIA12(DataInA[30]), .DIA13(DataInA[31]), 
   9.249 -        .DIA14(scuba_vlo), .DIA15(scuba_vlo), .DIA16(scuba_vlo), .DIA17(scuba_vlo), 
   9.250 -        .ADA0(scuba_vhi), .ADA1(scuba_vhi), .ADA2(scuba_vlo), .ADA3(scuba_vlo), 
   9.251 -        .ADA4(AddressA[0]), .ADA5(AddressA[1]), .ADA6(AddressA[2]), .ADA7(AddressA[3]), 
   9.252 -        .ADA8(AddressA[4]), .ADA9(AddressA[5]), .ADA10(AddressA[6]), .ADA11(AddressA[7]), 
   9.253 -        .ADA12(AddressA[8]), .ADA13(scuba_vlo), .CEA(ClockEnA), .CLKA(ClockA), 
   9.254 -        .OCEA(ClockEnA), .WEA(WrA), .CSA0(scuba_vlo), .CSA1(scuba_vlo), 
   9.255 -        .CSA2(scuba_vlo), .RSTA(ResetA), .DIB0(DataInB[18]), .DIB1(DataInB[19]), 
   9.256 -        .DIB2(DataInB[20]), .DIB3(DataInB[21]), .DIB4(DataInB[22]), .DIB5(DataInB[23]), 
   9.257 -        .DIB6(DataInB[24]), .DIB7(DataInB[25]), .DIB8(DataInB[26]), .DIB9(DataInB[27]), 
   9.258 -        .DIB10(DataInB[28]), .DIB11(DataInB[29]), .DIB12(DataInB[30]), .DIB13(DataInB[31]), 
   9.259 -        .DIB14(scuba_vlo), .DIB15(scuba_vlo), .DIB16(scuba_vlo), .DIB17(scuba_vlo), 
   9.260 -        .ADB0(scuba_vhi), .ADB1(scuba_vhi), .ADB2(scuba_vlo), .ADB3(scuba_vlo), 
   9.261 -        .ADB4(AddressB[0]), .ADB5(AddressB[1]), .ADB6(AddressB[2]), .ADB7(AddressB[3]), 
   9.262 -        .ADB8(AddressB[4]), .ADB9(AddressB[5]), .ADB10(AddressB[6]), .ADB11(AddressB[7]), 
   9.263 -        .ADB12(AddressB[8]), .ADB13(scuba_vlo), .CEB(ClockEnB), .CLKB(ClockB), 
   9.264 -        .OCEB(ClockEnB), .WEB(WrB), .CSB0(scuba_vlo), .CSB1(scuba_vlo), 
   9.265 -        .CSB2(scuba_vlo), .RSTB(ResetB), .DOA0(QA[18]), .DOA1(QA[19]), .DOA2(QA[20]), 
   9.266 -        .DOA3(QA[21]), .DOA4(QA[22]), .DOA5(QA[23]), .DOA6(QA[24]), .DOA7(QA[25]), 
   9.267 -        .DOA8(QA[26]), .DOA9(QA[27]), .DOA10(QA[28]), .DOA11(QA[29]), .DOA12(QA[30]), 
   9.268 -        .DOA13(QA[31]), .DOA14(), .DOA15(), .DOA16(), .DOA17(), .DOB0(QB[18]), 
   9.269 -        .DOB1(QB[19]), .DOB2(QB[20]), .DOB3(QB[21]), .DOB4(QB[22]), .DOB5(QB[23]), 
   9.270 -        .DOB6(QB[24]), .DOB7(QB[25]), .DOB8(QB[26]), .DOB9(QB[27]), .DOB10(QB[28]), 
   9.271 -        .DOB11(QB[29]), .DOB12(QB[30]), .DOB13(QB[31]), .DOB14(), .DOB15(), 
   9.272 -        .DOB16(), .DOB17())
   9.273 -             /* synthesis MEM_LPC_FILE="lm32_monitor_ram.lpc" */
   9.274 -             /* synthesis MEM_INIT_FILE="lm32_monitor.mem" */
   9.275 -             /* synthesis RESETMODE="SYNC" */;
   9.276 -
   9.277 -
   9.278 -
   9.279 -    // exemplar begin
   9.280 -    // exemplar attribute lm32_monitor_ram_0_0_1 MEM_LPC_FILE lm32_monitor_ram.lpc
   9.281 -    // exemplar attribute lm32_monitor_ram_0_0_1 MEM_INIT_FILE lm32_monitor.mem
   9.282 -    // exemplar attribute lm32_monitor_ram_0_0_1 RESETMODE SYNC
   9.283 -    // exemplar attribute lm32_monitor_ram_0_1_0 MEM_LPC_FILE lm32_monitor_ram.lpc
   9.284 -    // exemplar attribute lm32_monitor_ram_0_1_0 MEM_INIT_FILE lm32_monitor.mem
   9.285 -    // exemplar attribute lm32_monitor_ram_0_1_0 RESETMODE SYNC
   9.286 -    // exemplar end
   9.287 -
   9.288 -      end else if (lat_family == "EC" || lat_family == "ECP" || lat_family == "XP") begin
   9.289 -
   9.290 -/* Verilog netlist generated by SCUBA ispLever_v8.0_ALPHA (69) */
   9.291 -/* Module Version: 7.0 */
   9.292 -/* c:\ispTOOLS8_0\ispFPGA\bin\nt\scuba.exe -w -lang verilog -synth synplify -bus_exp 7 -bb -arch ep5g00 -type bram -wp 11 -rp 1010 -addr_width 9 -data_width 32 -num_rows 512 -gsr DISABLED -writemode NORMAL -resetmode SYNC -memfile ../../lm32_monitor.mem -memformat hex -n lm32_monitor_ram -e  */
   9.293 -/* Tue Jun 16 18:01:57 2009 */
   9.294 -
   9.295 -    // synopsys translate_off
   9.296 -    defparam lm32_monitor_ram_0_0_1.INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.297 -    defparam lm32_monitor_ram_0_0_1.INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.298 -    defparam lm32_monitor_ram_0_0_1.INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.299 -    defparam lm32_monitor_ram_0_0_1.INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.300 -    defparam lm32_monitor_ram_0_0_1.INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.301 -    defparam lm32_monitor_ram_0_0_1.INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.302 -    defparam lm32_monitor_ram_0_0_1.INITVAL_19 = 320'h0000000000000000000000000000000000000000000000000000000000000000000000000003FF81 ;
   9.303 -    defparam lm32_monitor_ram_0_0_1.INITVAL_18 = 320'h300003FF83300003FF85300003FF873FF4A1004F3FF8A300003FF8C300003FF8E300003FF9030000 ;
   9.304 -    defparam lm32_monitor_ram_0_0_1.INITVAL_17 = 320'h3FF92300003FF94300003FF96300003FFC100800070003FFFB0000130001100003FF5B1001700000 ;
   9.305 -    defparam lm32_monitor_ram_0_0_1.INITVAL_16 = 320'h068003FF70058003FF723FFFB300013FF6A00001100001FFAB00000068003FF7B058003FF7D3FFB1 ;
   9.306 -    defparam lm32_monitor_ram_0_0_1.INITVAL_15 = 320'h3FF8D008003FFB4300000FFB61001B000361001A0002F10019000381001800038100130003310012 ;
   9.307 -    defparam lm32_monitor_ram_0_0_1.INITVAL_14 = 320'h00033100110003310010000331000900033100080003310007010003FF89058003FF9C3FFF900800 ;
   9.308 -    defparam lm32_monitor_ram_0_0_1.INITVAL_13 = 320'h070000FFFB30800070003FFD63FFB200800000041000A0004110006010003FF9A000000002410004 ;
   9.309 -    defparam lm32_monitor_ram_0_0_1.INITVAL_12 = 320'h200081000C0001030014200181001C00020300240000000000000001000000000000000000010000 ;
   9.310 -    defparam lm32_monitor_ram_0_0_1.INITVAL_11 = 320'h100010FFF310063000501004D000471006D00046100720002C100570001F10077010003FFBC00000 ;
   9.311 -    defparam lm32_monitor_ram_0_0_1.INITVAL_10 = 320'h30000044003FC0010000100540FFFF0080010000100540FFFF008000880010004200081000C00010 ;
   9.312 -    defparam lm32_monitor_ram_0_0_1.INITVAL_0F = 320'h30014200181001C00020300240FFDC0000000008100043FFDD100083FFDF100093FFE11000A3FFE3 ;
   9.313 -    defparam lm32_monitor_ram_0_0_1.INITVAL_0E = 320'h1000B10008100040FFF8000000000C1000410008100083FFE7100093FFE91000A3FFEB1000B3FFED ;
   9.314 -    defparam lm32_monitor_ram_0_0_1.INITVAL_0D = 320'h100040FFF400000200000FFFF01000000000000210054100000FFFF01000100FF00000100FF00000 ;
   9.315 -    defparam lm32_monitor_ram_0_0_1.INITVAL_0C = 320'h0FFFE1010001000000000007430084200002009830000300943000030090300003008C2007C10078 ;
   9.316 -    defparam lm32_monitor_ram_0_0_1.INITVAL_0B = 320'h300702006C1006800064300602005C1005800054300502004C1004800044300402003C1003800034 ;
   9.317 -    defparam lm32_monitor_ram_0_0_1.INITVAL_0A = 320'h300302002C1002800024300202001C1001800014300102000C100080000000074200842000020098 ;
   9.318 -    defparam lm32_monitor_ram_0_0_1.INITVAL_09 = 320'h20000200942000020090200002008C3008010078300702006C1006800064300602005C1005800054 ;
   9.319 -    defparam lm32_monitor_ram_0_0_1.INITVAL_08 = 320'h300502004C1004800044300402003C1003800034300302002C1002800024300202001C1001800014 ;
   9.320 -    defparam lm32_monitor_ram_0_0_1.INITVAL_07 = 320'h300102000C10008000001F9A00E000000041007810000100881000110001100011000110001100FF ;
   9.321 -    defparam lm32_monitor_ram_0_0_1.INITVAL_06 = 320'h1F9A0100940080010090008001008C008001009C008001009800800300802007C00074300702006C ;
   9.322 -    defparam lm32_monitor_ram_0_0_1.INITVAL_05 = 320'h1006800064300602005C1005800054300502004C1004800044300402003C1003800034300302002C ;
   9.323 -    defparam lm32_monitor_ram_0_0_1.INITVAL_04 = 320'h1002800024300202001C1001800014300102000C100080000000000106603FFC530000007F40E000 ;
   9.324 -    defparam lm32_monitor_ram_0_0_1.INITVAL_03 = 320'h0003E000BC1000400800200840000A000000000000046000C4100040080020084000120000000000 ;
   9.325 -    defparam lm32_monitor_ram_0_0_1.INITVAL_02 = 320'h0004E000CC1000400800200840001A000000000000056000D4100040080020084000220000000000 ;
   9.326 -    defparam lm32_monitor_ram_0_0_1.INITVAL_01 = 320'h00086000DC1000400800300840002A000000000000066000E4100040080020084000320000000000 ;
   9.327 -    defparam lm32_monitor_ram_0_0_1.INITVAL_00 = 320'h00096000EC1000400800300840003A000000000000000000000000000000000000003E0000000000 ;
   9.328 -    defparam lm32_monitor_ram_0_0_1.CSDECODE_B = "000" ;
   9.329 -    defparam lm32_monitor_ram_0_0_1.CSDECODE_A = "000" ;
   9.330 -    defparam lm32_monitor_ram_0_0_1.WRITEMODE_B = "NORMAL" ;
   9.331 -    defparam lm32_monitor_ram_0_0_1.WRITEMODE_A = "NORMAL" ;
   9.332 -    defparam lm32_monitor_ram_0_0_1.GSR = "DISABLED" ;
   9.333 -    defparam lm32_monitor_ram_0_0_1.RESETMODE = "SYNC" ;
   9.334 -    defparam lm32_monitor_ram_0_0_1.REGMODE_B = "NOREG" ;
   9.335 -    defparam lm32_monitor_ram_0_0_1.REGMODE_A = "NOREG" ;
   9.336 -    defparam lm32_monitor_ram_0_0_1.DATA_WIDTH_B = 18 ;
   9.337 -    defparam lm32_monitor_ram_0_0_1.DATA_WIDTH_A = 18 ;
   9.338 -    // synopsys translate_on
   9.339 -    DP8KA lm32_monitor_ram_0_0_1 (.CEA(ClockEnA), .CLKA(ClockA), .WEA(WrA), 
   9.340 -        .CSA0(scuba_vlo), .CSA1(scuba_vlo), .CSA2(scuba_vlo), .RSTA(ResetA), 
   9.341 -        .CEB(ClockEnB), .CLKB(ClockB), .WEB(WrB), .CSB0(scuba_vlo), .CSB1(scuba_vlo), 
   9.342 -        .CSB2(scuba_vlo), .RSTB(ResetB), .DIA0(DataInA[0]), .DIA1(DataInA[1]), 
   9.343 -        .DIA2(DataInA[2]), .DIA3(DataInA[3]), .DIA4(DataInA[4]), .DIA5(DataInA[5]), 
   9.344 -        .DIA6(DataInA[6]), .DIA7(DataInA[7]), .DIA8(DataInA[8]), .DIA9(DataInA[9]), 
   9.345 -        .DIA10(DataInA[10]), .DIA11(DataInA[11]), .DIA12(DataInA[12]), .DIA13(DataInA[13]), 
   9.346 -        .DIA14(DataInA[14]), .DIA15(DataInA[15]), .DIA16(DataInA[16]), .DIA17(DataInA[17]), 
   9.347 -        .ADA0(scuba_vhi), .ADA1(scuba_vhi), .ADA2(scuba_vlo), .ADA3(scuba_vlo), 
   9.348 -        .ADA4(AddressA[0]), .ADA5(AddressA[1]), .ADA6(AddressA[2]), .ADA7(AddressA[3]), 
   9.349 -        .ADA8(AddressA[4]), .ADA9(AddressA[5]), .ADA10(AddressA[6]), .ADA11(AddressA[7]), 
   9.350 -        .ADA12(AddressA[8]), .DIB0(DataInB[0]), .DIB1(DataInB[1]), .DIB2(DataInB[2]), 
   9.351 -        .DIB3(DataInB[3]), .DIB4(DataInB[4]), .DIB5(DataInB[5]), .DIB6(DataInB[6]), 
   9.352 -        .DIB7(DataInB[7]), .DIB8(DataInB[8]), .DIB9(DataInB[9]), .DIB10(DataInB[10]), 
   9.353 -        .DIB11(DataInB[11]), .DIB12(DataInB[12]), .DIB13(DataInB[13]), .DIB14(DataInB[14]), 
   9.354 -        .DIB15(DataInB[15]), .DIB16(DataInB[16]), .DIB17(DataInB[17]), .ADB0(scuba_vhi), 
   9.355 -        .ADB1(scuba_vhi), .ADB2(scuba_vlo), .ADB3(scuba_vlo), .ADB4(AddressB[0]), 
   9.356 -        .ADB5(AddressB[1]), .ADB6(AddressB[2]), .ADB7(AddressB[3]), .ADB8(AddressB[4]), 
   9.357 -        .ADB9(AddressB[5]), .ADB10(AddressB[6]), .ADB11(AddressB[7]), .ADB12(AddressB[8]), 
   9.358 -        .DOA0(QA[0]), .DOA1(QA[1]), .DOA2(QA[2]), .DOA3(QA[3]), .DOA4(QA[4]), 
   9.359 -        .DOA5(QA[5]), .DOA6(QA[6]), .DOA7(QA[7]), .DOA8(QA[8]), .DOA9(QA[9]), 
   9.360 -        .DOA10(QA[10]), .DOA11(QA[11]), .DOA12(QA[12]), .DOA13(QA[13]), 
   9.361 -        .DOA14(QA[14]), .DOA15(QA[15]), .DOA16(QA[16]), .DOA17(QA[17]), 
   9.362 -        .DOB0(QB[0]), .DOB1(QB[1]), .DOB2(QB[2]), .DOB3(QB[3]), .DOB4(QB[4]), 
   9.363 -        .DOB5(QB[5]), .DOB6(QB[6]), .DOB7(QB[7]), .DOB8(QB[8]), .DOB9(QB[9]), 
   9.364 -        .DOB10(QB[10]), .DOB11(QB[11]), .DOB12(QB[12]), .DOB13(QB[13]), 
   9.365 -        .DOB14(QB[14]), .DOB15(QB[15]), .DOB16(QB[16]), .DOB17(QB[17]))
   9.366 -             /* synthesis MEM_LPC_FILE="lm32_monitor_ram.lpc" */
   9.367 -             /* synthesis MEM_INIT_FILE="lm32_monitor.mem" */
   9.368 -             /* synthesis INITVAL_1F="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.369 -             /* synthesis INITVAL_1E="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.370 -             /* synthesis INITVAL_1D="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.371 -             /* synthesis INITVAL_1C="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.372 -             /* synthesis INITVAL_1B="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.373 -             /* synthesis INITVAL_1A="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.374 -             /* synthesis INITVAL_19="0x0000000000000000000000000000000000000000000000000000000000000000000000000003FF81" */
   9.375 -             /* synthesis INITVAL_18="0x300003FF83300003FF85300003FF873FF4A1004F3FF8A300003FF8C300003FF8E300003FF9030000" */
   9.376 -             /* synthesis INITVAL_17="0x3FF92300003FF94300003FF96300003FFC100800070003FFFB0000130001100003FF5B1001700000" */
   9.377 -             /* synthesis INITVAL_16="0x068003FF70058003FF723FFFB300013FF6A00001100001FFAB00000068003FF7B058003FF7D3FFB1" */
   9.378 -             /* synthesis INITVAL_15="0x3FF8D008003FFB4300000FFB61001B000361001A0002F10019000381001800038100130003310012" */
   9.379 -             /* synthesis INITVAL_14="0x00033100110003310010000331000900033100080003310007010003FF89058003FF9C3FFF900800" */
   9.380 -             /* synthesis INITVAL_13="0x070000FFFB30800070003FFD63FFB200800000041000A0004110006010003FF9A000000002410004" */
   9.381 -             /* synthesis INITVAL_12="0x200081000C0001030014200181001C00020300240000000000000001000000000000000000010000" */
   9.382 -             /* synthesis INITVAL_11="0x100010FFF310063000501004D000471006D00046100720002C100570001F10077010003FFBC00000" */
   9.383 -             /* synthesis INITVAL_10="0x30000044003FC0010000100540FFFF0080010000100540FFFF008000880010004200081000C00010" */
   9.384 -             /* synthesis INITVAL_0F="0x30014200181001C00020300240FFDC0000000008100043FFDD100083FFDF100093FFE11000A3FFE3" */
   9.385 -             /* synthesis INITVAL_0E="0x1000B10008100040FFF8000000000C1000410008100083FFE7100093FFE91000A3FFEB1000B3FFED" */
   9.386 -             /* synthesis INITVAL_0D="0x100040FFF400000200000FFFF01000000000000210054100000FFFF01000100FF00000100FF00000" */
   9.387 -             /* synthesis INITVAL_0C="0x0FFFE1010001000000000007430084200002009830000300943000030090300003008C2007C10078" */
   9.388 -             /* synthesis INITVAL_0B="0x300702006C1006800064300602005C1005800054300502004C1004800044300402003C1003800034" */
   9.389 -             /* synthesis INITVAL_0A="0x300302002C1002800024300202001C1001800014300102000C100080000000074200842000020098" */
   9.390 -             /* synthesis INITVAL_09="0x20000200942000020090200002008C3008010078300702006C1006800064300602005C1005800054" */
   9.391 -             /* synthesis INITVAL_08="0x300502004C1004800044300402003C1003800034300302002C1002800024300202001C1001800014" */
   9.392 -             /* synthesis INITVAL_07="0x300102000C10008000001F9A00E000000041007810000100881000110001100011000110001100FF" */
   9.393 -             /* synthesis INITVAL_06="0x1F9A0100940080010090008001008C008001009C008001009800800300802007C00074300702006C" */
   9.394 -             /* synthesis INITVAL_05="0x1006800064300602005C1005800054300502004C1004800044300402003C1003800034300302002C" */
   9.395 -             /* synthesis INITVAL_04="0x1002800024300202001C1001800014300102000C100080000000000106603FFC530000007F40E000" */
   9.396 -             /* synthesis INITVAL_03="0x0003E000BC1000400800200840000A000000000000046000C4100040080020084000120000000000" */
   9.397 -             /* synthesis INITVAL_02="0x0004E000CC1000400800200840001A000000000000056000D4100040080020084000220000000000" */
   9.398 -             /* synthesis INITVAL_01="0x00086000DC1000400800300840002A000000000000066000E4100040080020084000320000000000" */
   9.399 -             /* synthesis INITVAL_00="0x00096000EC1000400800300840003A000000000000000000000000000000000000003E0000000000" */
   9.400 -             /* synthesis CSDECODE_B="000" */
   9.401 -             /* synthesis CSDECODE_A="000" */
   9.402 -             /* synthesis WRITEMODE_B="NORMAL" */
   9.403 -             /* synthesis WRITEMODE_A="NORMAL" */
   9.404 -             /* synthesis GSR="DISABLED" */
   9.405 -             /* synthesis RESETMODE="SYNC" */
   9.406 -             /* synthesis REGMODE_B="NOREG" */
   9.407 -             /* synthesis REGMODE_A="NOREG" */
   9.408 -             /* synthesis DATA_WIDTH_B="18" */
   9.409 -             /* synthesis DATA_WIDTH_A="18" */;
   9.410 -
   9.411 -    VHI scuba_vhi_inst (.Z(scuba_vhi));
   9.412 -
   9.413 -    VLO scuba_vlo_inst (.Z(scuba_vlo));
   9.414 -
   9.415 -    // synopsys translate_off
   9.416 -    defparam lm32_monitor_ram_0_1_0.INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.417 -    defparam lm32_monitor_ram_0_1_0.INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.418 -    defparam lm32_monitor_ram_0_1_0.INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.419 -    defparam lm32_monitor_ram_0_1_0.INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.420 -    defparam lm32_monitor_ram_0_1_0.INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.421 -    defparam lm32_monitor_ram_0_1_0.INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.422 -    defparam lm32_monitor_ram_0_1_0.INITVAL_19 = 320'h000000000000000000000000000000000000000000000000000000000000000000000000000038FF ;
   9.423 -    defparam lm32_monitor_ram_0_1_0.INITVAL_18 = 320'h034D2038FF034C2038FF0349A038FF03EFF00D00038FF034CA038FF03492038FF0348A038FF03482 ;
   9.424 -    defparam lm32_monitor_ram_0_1_0.INITVAL_17 = 320'h038FF0344A038FF03442038FF0343A038FF02E7002430038FF00D6300D5A00C5803EFF0136300D03 ;
   9.425 -    defparam lm32_monitor_ram_0_1_0.INITVAL_16 = 320'h02E0803EFF02E0803EFF038FF00D5A03EFF00D63010580136300D0302E0803EFF02E0803EFF038FF ;
   9.426 -    defparam lm32_monitor_ram_0_1_0.INITVAL_15 = 320'h03EFF02E88038FF034DA0170801F100110801F100110801F100110801F100110801F100110801F10 ;
   9.427 -    defparam lm32_monitor_ram_0_1_0.INITVAL_14 = 320'h0110801F100110801F100110801F100110801F100110801F0802E0803EFF02E0803EFF038FF02E70 ;
   9.428 -    defparam lm32_monitor_ram_0_1_0.INITVAL_13 = 320'h024500110C0287302430038FF03EFF02E700110801F100110801F0802E0803EFF030E800DE700AE7 ;
   9.429 -    defparam lm32_monitor_ram_0_1_0.INITVAL_12 = 320'h00AE400AE400AE400AE300AE300AE300AE300AE200D0000D0000D000342000D0000D0000D0003418 ;
   9.430 -    defparam lm32_monitor_ram_0_1_0.INITVAL_11 = 320'h00D000170801F100110801F100110801F100110801F100110801F100110801F0802E0803EFF00E84 ;
   9.431 -    defparam lm32_monitor_ram_0_1_0.INITVAL_10 = 320'h00E7B01E0401E030347000D0001708024700347000D00017080247002E08016E7016E4016E4016E4 ;
   9.432 -    defparam lm32_monitor_ram_0_1_0.INITVAL_0F = 320'h016E3016E3016E3016E3016E200DE7030E800DE700AE703EFF010E003EFF010E003EFF010E003EFF ;
   9.433 -    defparam lm32_monitor_ram_0_1_0.INITVAL_0E = 320'h010E0016E0016E700DE7030E800DE700AE700AE000CE003EFF00CE003EFF00CE003EFF00CE003EFF ;
   9.434 -    defparam lm32_monitor_ram_0_1_0.INITVAL_0D = 320'h016E700DE7030E8034700171002470030E80110801F0803470017100247000808030E80081003478 ;
   9.435 -    defparam lm32_monitor_ram_0_1_0.INITVAL_0C = 320'h011080081002478030F800AE700AE70340F00AE70340700AE70344F00AE70343F00AE700AE700AE7 ;
   9.436 -    defparam lm32_monitor_ram_0_1_0.INITVAL_0B = 320'h00AE600AE600AE600AE600AE500AE500AE500AE500AE400AE400AE400AE400AE300AE300AE300AE3 ;
   9.437 -    defparam lm32_monitor_ram_0_1_0.INITVAL_0A = 320'h00AE200AE200AE200AE200AE100AE100AE100AE100AE000AE000AE0030F000AE700AE70340F00AE7 ;
   9.438 -    defparam lm32_monitor_ram_0_1_0.INITVAL_09 = 320'h0340700AE70344F00AE70343F00AE700AE700AE700AE600AE600AE600AE600AE500AE500AE500AE5 ;
   9.439 -    defparam lm32_monitor_ram_0_1_0.INITVAL_08 = 320'h00AE400AE400AE400AE400AE300AE300AE300AE300AE200AE200AE200AE200AE100AE100AE100AE1 ;
   9.440 -    defparam lm32_monitor_ram_0_1_0.INITVAL_07 = 320'h00AE000AE000AE0030E800DEF02EE8016E8016E800AE8016E8000080000800008000080000800808 ;
   9.441 -    defparam lm32_monitor_ram_0_1_0.INITVAL_06 = 320'h00DE8016E802400016E802448016E802438016E802410016E802408016EF016EF016EF016EE016EE ;
   9.442 -    defparam lm32_monitor_ram_0_1_0.INITVAL_05 = 320'h016EE016EE016ED016ED016ED016ED016EC016EC016EC016EC016EB016EB016EB016EB016EA016EA ;
   9.443 -    defparam lm32_monitor_ram_0_1_0.INITVAL_04 = 320'h016EA016EA016E9016E9016E9016E9016E8016E8016E802600016E800DEF038FF00D0700DE702EE8 ;
   9.444 -    defparam lm32_monitor_ram_0_1_0.INITVAL_03 = 320'h0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600 ;
   9.445 -    defparam lm32_monitor_ram_0_1_0.INITVAL_02 = 320'h0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600 ;
   9.446 -    defparam lm32_monitor_ram_0_1_0.INITVAL_01 = 320'h0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600 ;
   9.447 -    defparam lm32_monitor_ram_0_1_0.INITVAL_00 = 320'h0380003E0000D0802EE0016E703E0002EE80260000D0000D0000D0000D0000D0003E000340802600 ;
   9.448 -    defparam lm32_monitor_ram_0_1_0.CSDECODE_B = "000" ;
   9.449 -    defparam lm32_monitor_ram_0_1_0.CSDECODE_A = "000" ;
   9.450 -    defparam lm32_monitor_ram_0_1_0.WRITEMODE_B = "NORMAL" ;
   9.451 -    defparam lm32_monitor_ram_0_1_0.WRITEMODE_A = "NORMAL" ;
   9.452 -    defparam lm32_monitor_ram_0_1_0.GSR = "DISABLED" ;
   9.453 -    defparam lm32_monitor_ram_0_1_0.RESETMODE = "SYNC" ;
   9.454 -    defparam lm32_monitor_ram_0_1_0.REGMODE_B = "NOREG" ;
   9.455 -    defparam lm32_monitor_ram_0_1_0.REGMODE_A = "NOREG" ;
   9.456 -    defparam lm32_monitor_ram_0_1_0.DATA_WIDTH_B = 18 ;
   9.457 -    defparam lm32_monitor_ram_0_1_0.DATA_WIDTH_A = 18 ;
   9.458 -    // synopsys translate_on
   9.459 -    DP8KA lm32_monitor_ram_0_1_0 (.CEA(ClockEnA), .CLKA(ClockA), .WEA(WrA), 
   9.460 -        .CSA0(scuba_vlo), .CSA1(scuba_vlo), .CSA2(scuba_vlo), .RSTA(ResetA), 
   9.461 -        .CEB(ClockEnB), .CLKB(ClockB), .WEB(WrB), .CSB0(scuba_vlo), .CSB1(scuba_vlo), 
   9.462 -        .CSB2(scuba_vlo), .RSTB(ResetB), .DIA0(DataInA[18]), .DIA1(DataInA[19]), 
   9.463 -        .DIA2(DataInA[20]), .DIA3(DataInA[21]), .DIA4(DataInA[22]), .DIA5(DataInA[23]), 
   9.464 -        .DIA6(DataInA[24]), .DIA7(DataInA[25]), .DIA8(DataInA[26]), .DIA9(DataInA[27]), 
   9.465 -        .DIA10(DataInA[28]), .DIA11(DataInA[29]), .DIA12(DataInA[30]), .DIA13(DataInA[31]), 
   9.466 -        .DIA14(scuba_vlo), .DIA15(scuba_vlo), .DIA16(scuba_vlo), .DIA17(scuba_vlo), 
   9.467 -        .ADA0(scuba_vhi), .ADA1(scuba_vhi), .ADA2(scuba_vlo), .ADA3(scuba_vlo), 
   9.468 -        .ADA4(AddressA[0]), .ADA5(AddressA[1]), .ADA6(AddressA[2]), .ADA7(AddressA[3]), 
   9.469 -        .ADA8(AddressA[4]), .ADA9(AddressA[5]), .ADA10(AddressA[6]), .ADA11(AddressA[7]), 
   9.470 -        .ADA12(AddressA[8]), .DIB0(DataInB[18]), .DIB1(DataInB[19]), .DIB2(DataInB[20]), 
   9.471 -        .DIB3(DataInB[21]), .DIB4(DataInB[22]), .DIB5(DataInB[23]), .DIB6(DataInB[24]), 
   9.472 -        .DIB7(DataInB[25]), .DIB8(DataInB[26]), .DIB9(DataInB[27]), .DIB10(DataInB[28]), 
   9.473 -        .DIB11(DataInB[29]), .DIB12(DataInB[30]), .DIB13(DataInB[31]), .DIB14(scuba_vlo), 
   9.474 -        .DIB15(scuba_vlo), .DIB16(scuba_vlo), .DIB17(scuba_vlo), .ADB0(scuba_vhi), 
   9.475 -        .ADB1(scuba_vhi), .ADB2(scuba_vlo), .ADB3(scuba_vlo), .ADB4(AddressB[0]), 
   9.476 -        .ADB5(AddressB[1]), .ADB6(AddressB[2]), .ADB7(AddressB[3]), .ADB8(AddressB[4]), 
   9.477 -        .ADB9(AddressB[5]), .ADB10(AddressB[6]), .ADB11(AddressB[7]), .ADB12(AddressB[8]), 
   9.478 -        .DOA0(QA[18]), .DOA1(QA[19]), .DOA2(QA[20]), .DOA3(QA[21]), .DOA4(QA[22]), 
   9.479 -        .DOA5(QA[23]), .DOA6(QA[24]), .DOA7(QA[25]), .DOA8(QA[26]), .DOA9(QA[27]), 
   9.480 -        .DOA10(QA[28]), .DOA11(QA[29]), .DOA12(QA[30]), .DOA13(QA[31]), 
   9.481 -        .DOA14(), .DOA15(), .DOA16(), .DOA17(), .DOB0(QB[18]), .DOB1(QB[19]), 
   9.482 -        .DOB2(QB[20]), .DOB3(QB[21]), .DOB4(QB[22]), .DOB5(QB[23]), .DOB6(QB[24]), 
   9.483 -        .DOB7(QB[25]), .DOB8(QB[26]), .DOB9(QB[27]), .DOB10(QB[28]), .DOB11(QB[29]), 
   9.484 -        .DOB12(QB[30]), .DOB13(QB[31]), .DOB14(), .DOB15(), .DOB16(), .DOB17())
   9.485 -             /* synthesis MEM_LPC_FILE="lm32_monitor_ram.lpc" */
   9.486 -             /* synthesis MEM_INIT_FILE="lm32_monitor.mem" */
   9.487 -             /* synthesis INITVAL_1F="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.488 -             /* synthesis INITVAL_1E="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.489 -             /* synthesis INITVAL_1D="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.490 -             /* synthesis INITVAL_1C="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.491 -             /* synthesis INITVAL_1B="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.492 -             /* synthesis INITVAL_1A="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.493 -             /* synthesis INITVAL_19="0x000000000000000000000000000000000000000000000000000000000000000000000000000038FF" */
   9.494 -             /* synthesis INITVAL_18="0x034D2038FF034C2038FF0349A038FF03EFF00D00038FF034CA038FF03492038FF0348A038FF03482" */
   9.495 -             /* synthesis INITVAL_17="0x038FF0344A038FF03442038FF0343A038FF02E7002430038FF00D6300D5A00C5803EFF0136300D03" */
   9.496 -             /* synthesis INITVAL_16="0x02E0803EFF02E0803EFF038FF00D5A03EFF00D63010580136300D0302E0803EFF02E0803EFF038FF" */
   9.497 -             /* synthesis INITVAL_15="0x03EFF02E88038FF034DA0170801F100110801F100110801F100110801F100110801F100110801F10" */
   9.498 -             /* synthesis INITVAL_14="0x0110801F100110801F100110801F100110801F100110801F0802E0803EFF02E0803EFF038FF02E70" */
   9.499 -             /* synthesis INITVAL_13="0x024500110C0287302430038FF03EFF02E700110801F100110801F0802E0803EFF030E800DE700AE7" */
   9.500 -             /* synthesis INITVAL_12="0x00AE400AE400AE400AE300AE300AE300AE300AE200D0000D0000D000342000D0000D0000D0003418" */
   9.501 -             /* synthesis INITVAL_11="0x00D000170801F100110801F100110801F100110801F100110801F100110801F0802E0803EFF00E84" */
   9.502 -             /* synthesis INITVAL_10="0x00E7B01E0401E030347000D0001708024700347000D00017080247002E08016E7016E4016E4016E4" */
   9.503 -             /* synthesis INITVAL_0F="0x016E3016E3016E3016E3016E200DE7030E800DE700AE703EFF010E003EFF010E003EFF010E003EFF" */
   9.504 -             /* synthesis INITVAL_0E="0x010E0016E0016E700DE7030E800DE700AE700AE000CE003EFF00CE003EFF00CE003EFF00CE003EFF" */
   9.505 -             /* synthesis INITVAL_0D="0x016E700DE7030E8034700171002470030E80110801F0803470017100247000808030E80081003478" */
   9.506 -             /* synthesis INITVAL_0C="0x011080081002478030F800AE700AE70340F00AE70340700AE70344F00AE70343F00AE700AE700AE7" */
   9.507 -             /* synthesis INITVAL_0B="0x00AE600AE600AE600AE600AE500AE500AE500AE500AE400AE400AE400AE400AE300AE300AE300AE3" */
   9.508 -             /* synthesis INITVAL_0A="0x00AE200AE200AE200AE200AE100AE100AE100AE100AE000AE000AE0030F000AE700AE70340F00AE7" */
   9.509 -             /* synthesis INITVAL_09="0x0340700AE70344F00AE70343F00AE700AE700AE700AE600AE600AE600AE600AE500AE500AE500AE5" */
   9.510 -             /* synthesis INITVAL_08="0x00AE400AE400AE400AE400AE300AE300AE300AE300AE200AE200AE200AE200AE100AE100AE100AE1" */
   9.511 -             /* synthesis INITVAL_07="0x00AE000AE000AE0030E800DEF02EE8016E8016E800AE8016E8000080000800008000080000800808" */
   9.512 -             /* synthesis INITVAL_06="0x00DE8016E802400016E802448016E802438016E802410016E802408016EF016EF016EF016EE016EE" */
   9.513 -             /* synthesis INITVAL_05="0x016EE016EE016ED016ED016ED016ED016EC016EC016EC016EC016EB016EB016EB016EB016EA016EA" */
   9.514 -             /* synthesis INITVAL_04="0x016EA016EA016E9016E9016E9016E9016E8016E8016E802600016E800DEF038FF00D0700DE702EE8" */
   9.515 -             /* synthesis INITVAL_03="0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600" */
   9.516 -             /* synthesis INITVAL_02="0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600" */
   9.517 -             /* synthesis INITVAL_01="0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600" */
   9.518 -             /* synthesis INITVAL_00="0x0380003E0000D0802EE0016E703E0002EE80260000D0000D0000D0000D0000D0003E000340802600" */
   9.519 -             /* synthesis CSDECODE_B="000" */
   9.520 -             /* synthesis CSDECODE_A="000" */
   9.521 -             /* synthesis WRITEMODE_B="NORMAL" */
   9.522 -             /* synthesis WRITEMODE_A="NORMAL" */
   9.523 -             /* synthesis GSR="DISABLED" */
   9.524 -             /* synthesis RESETMODE="SYNC" */
   9.525 -             /* synthesis REGMODE_B="NOREG" */
   9.526 -             /* synthesis REGMODE_A="NOREG" */
   9.527 -             /* synthesis DATA_WIDTH_B="18" */
   9.528 -             /* synthesis DATA_WIDTH_A="18" */;
   9.529 -
   9.530 -
   9.531 -
   9.532 -    // exemplar begin
   9.533 -    // exemplar attribute lm32_monitor_ram_0_0_1 MEM_LPC_FILE lm32_monitor_ram.lpc
   9.534 -    // exemplar attribute lm32_monitor_ram_0_0_1 MEM_INIT_FILE lm32_monitor.mem
   9.535 -    // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_1F 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
   9.536 -    // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_1E 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
   9.537 -    // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_1D 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
   9.538 -    // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_1C 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
   9.539 -    // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_1B 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
   9.540 -    // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_1A 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
   9.541 -    // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_19 0x0000000000000000000000000000000000000000000000000000000000000000000000000003FF81
   9.542 -    // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_18 0x300003FF83300003FF85300003FF873FF4A1004F3FF8A300003FF8C300003FF8E300003FF9030000
   9.543 -    // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_17 0x3FF92300003FF94300003FF96300003FFC100800070003FFFB0000130001100003FF5B1001700000
   9.544 -    // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_16 0x068003FF70058003FF723FFFB300013FF6A00001100001FFAB00000068003FF7B058003FF7D3FFB1
   9.545 -    // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_15 0x3FF8D008003FFB4300000FFB61001B000361001A0002F10019000381001800038100130003310012
   9.546 -    // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_14 0x00033100110003310010000331000900033100080003310007010003FF89058003FF9C3FFF900800
   9.547 -    // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_13 0x070000FFFB30800070003FFD63FFB200800000041000A0004110006010003FF9A000000002410004
   9.548 -    // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_12 0x200081000C0001030014200181001C00020300240000000000000001000000000000000000010000
   9.549 -    // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_11 0x100010FFF310063000501004D000471006D00046100720002C100570001F10077010003FFBC00000
   9.550 -    // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_10 0x30000044003FC0010000100540FFFF0080010000100540FFFF008000880010004200081000C00010
   9.551 -    // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_0F 0x30014200181001C00020300240FFDC0000000008100043FFDD100083FFDF100093FFE11000A3FFE3
   9.552 -    // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_0E 0x1000B10008100040FFF8000000000C1000410008100083FFE7100093FFE91000A3FFEB1000B3FFED
   9.553 -    // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_0D 0x100040FFF400000200000FFFF01000000000000210054100000FFFF01000100FF00000100FF00000
   9.554 -    // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_0C 0x0FFFE1010001000000000007430084200002009830000300943000030090300003008C2007C10078
   9.555 -    // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_0B 0x300702006C1006800064300602005C1005800054300502004C1004800044300402003C1003800034
   9.556 -    // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_0A 0x300302002C1002800024300202001C1001800014300102000C100080000000074200842000020098
   9.557 -    // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_09 0x20000200942000020090200002008C3008010078300702006C1006800064300602005C1005800054
   9.558 -    // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_08 0x300502004C1004800044300402003C1003800034300302002C1002800024300202001C1001800014
   9.559 -    // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_07 0x300102000C10008000001F9A00E000000041007810000100881000110001100011000110001100FF
   9.560 -    // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_06 0x1F9A0100940080010090008001008C008001009C008001009800800300802007C00074300702006C
   9.561 -    // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_05 0x1006800064300602005C1005800054300502004C1004800044300402003C1003800034300302002C
   9.562 -    // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_04 0x1002800024300202001C1001800014300102000C100080000000000106603FFC530000007F40E000
   9.563 -    // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_03 0x0003E000BC1000400800200840000A000000000000046000C4100040080020084000120000000000
   9.564 -    // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_02 0x0004E000CC1000400800200840001A000000000000056000D4100040080020084000220000000000
   9.565 -    // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_01 0x00086000DC1000400800300840002A000000000000066000E4100040080020084000320000000000
   9.566 -    // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_00 0x00096000EC1000400800300840003A000000000000000000000000000000000000003E0000000000
   9.567 -    // exemplar attribute lm32_monitor_ram_0_0_1 CSDECODE_B 000
   9.568 -    // exemplar attribute lm32_monitor_ram_0_0_1 CSDECODE_A 000
   9.569 -    // exemplar attribute lm32_monitor_ram_0_0_1 WRITEMODE_B NORMAL
   9.570 -    // exemplar attribute lm32_monitor_ram_0_0_1 WRITEMODE_A NORMAL
   9.571 -    // exemplar attribute lm32_monitor_ram_0_0_1 GSR DISABLED
   9.572 -    // exemplar attribute lm32_monitor_ram_0_0_1 RESETMODE SYNC
   9.573 -    // exemplar attribute lm32_monitor_ram_0_0_1 REGMODE_B NOREG
   9.574 -    // exemplar attribute lm32_monitor_ram_0_0_1 REGMODE_A NOREG
   9.575 -    // exemplar attribute lm32_monitor_ram_0_0_1 DATA_WIDTH_B 18
   9.576 -    // exemplar attribute lm32_monitor_ram_0_0_1 DATA_WIDTH_A 18
   9.577 -    // exemplar attribute lm32_monitor_ram_0_1_0 MEM_LPC_FILE lm32_monitor_ram.lpc
   9.578 -    // exemplar attribute lm32_monitor_ram_0_1_0 MEM_INIT_FILE lm32_monitor.mem
   9.579 -    // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_1F 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
   9.580 -    // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_1E 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
   9.581 -    // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_1D 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
   9.582 -    // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_1C 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
   9.583 -    // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_1B 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
   9.584 -    // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_1A 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
   9.585 -    // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_19 0x000000000000000000000000000000000000000000000000000000000000000000000000000038FF
   9.586 -    // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_18 0x034D2038FF034C2038FF0349A038FF03EFF00D00038FF034CA038FF03492038FF0348A038FF03482
   9.587 -    // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_17 0x038FF0344A038FF03442038FF0343A038FF02E7002430038FF00D6300D5A00C5803EFF0136300D03
   9.588 -    // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_16 0x02E0803EFF02E0803EFF038FF00D5A03EFF00D63010580136300D0302E0803EFF02E0803EFF038FF
   9.589 -    // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_15 0x03EFF02E88038FF034DA0170801F100110801F100110801F100110801F100110801F100110801F10
   9.590 -    // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_14 0x0110801F100110801F100110801F100110801F100110801F0802E0803EFF02E0803EFF038FF02E70
   9.591 -    // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_13 0x024500110C0287302430038FF03EFF02E700110801F100110801F0802E0803EFF030E800DE700AE7
   9.592 -    // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_12 0x00AE400AE400AE400AE300AE300AE300AE300AE200D0000D0000D000342000D0000D0000D0003418
   9.593 -    // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_11 0x00D000170801F100110801F100110801F100110801F100110801F100110801F0802E0803EFF00E84
   9.594 -    // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_10 0x00E7B01E0401E030347000D0001708024700347000D00017080247002E08016E7016E4016E4016E4
   9.595 -    // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_0F 0x016E3016E3016E3016E3016E200DE7030E800DE700AE703EFF010E003EFF010E003EFF010E003EFF
   9.596 -    // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_0E 0x010E0016E0016E700DE7030E800DE700AE700AE000CE003EFF00CE003EFF00CE003EFF00CE003EFF
   9.597 -    // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_0D 0x016E700DE7030E8034700171002470030E80110801F0803470017100247000808030E80081003478
   9.598 -    // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_0C 0x011080081002478030F800AE700AE70340F00AE70340700AE70344F00AE70343F00AE700AE700AE7
   9.599 -    // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_0B 0x00AE600AE600AE600AE600AE500AE500AE500AE500AE400AE400AE400AE400AE300AE300AE300AE3
   9.600 -    // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_0A 0x00AE200AE200AE200AE200AE100AE100AE100AE100AE000AE000AE0030F000AE700AE70340F00AE7
   9.601 -    // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_09 0x0340700AE70344F00AE70343F00AE700AE700AE700AE600AE600AE600AE600AE500AE500AE500AE5
   9.602 -    // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_08 0x00AE400AE400AE400AE400AE300AE300AE300AE300AE200AE200AE200AE200AE100AE100AE100AE1
   9.603 -    // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_07 0x00AE000AE000AE0030E800DEF02EE8016E8016E800AE8016E8000080000800008000080000800808
   9.604 -    // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_06 0x00DE8016E802400016E802448016E802438016E802410016E802408016EF016EF016EF016EE016EE
   9.605 -    // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_05 0x016EE016EE016ED016ED016ED016ED016EC016EC016EC016EC016EB016EB016EB016EB016EA016EA
   9.606 -    // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_04 0x016EA016EA016E9016E9016E9016E9016E8016E8016E802600016E800DEF038FF00D0700DE702EE8
   9.607 -    // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_03 0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600
   9.608 -    // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_02 0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600
   9.609 -    // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_01 0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600
   9.610 -    // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_00 0x0380003E0000D0802EE0016E703E0002EE80260000D0000D0000D0000D0000D0003E000340802600
   9.611 -    // exemplar attribute lm32_monitor_ram_0_1_0 CSDECODE_B 000
   9.612 -    // exemplar attribute lm32_monitor_ram_0_1_0 CSDECODE_A 000
   9.613 -    // exemplar attribute lm32_monitor_ram_0_1_0 WRITEMODE_B NORMAL
   9.614 -    // exemplar attribute lm32_monitor_ram_0_1_0 WRITEMODE_A NORMAL
   9.615 -    // exemplar attribute lm32_monitor_ram_0_1_0 GSR DISABLED
   9.616 -    // exemplar attribute lm32_monitor_ram_0_1_0 RESETMODE SYNC
   9.617 -    // exemplar attribute lm32_monitor_ram_0_1_0 REGMODE_B NOREG
   9.618 -    // exemplar attribute lm32_monitor_ram_0_1_0 REGMODE_A NOREG
   9.619 -    // exemplar attribute lm32_monitor_ram_0_1_0 DATA_WIDTH_B 18
   9.620 -    // exemplar attribute lm32_monitor_ram_0_1_0 DATA_WIDTH_A 18
   9.621 -    // exemplar end
   9.622 -
   9.623 -      end else if (lat_family == "ECP2" || lat_family == "ECP2M" || lat_family == "XP2") begin 
   9.624 -
   9.625 -/* Verilog netlist generated by SCUBA ispLever_v8.0_ALPHA (69) */
   9.626 -/* Module Version: 7.0 */
   9.627 -/* c:\ispTOOLS8_0\ispFPGA\bin\nt\scuba.exe -w -lang verilog -synth synplify -bus_exp 7 -bb -arch ep5a00 -type bram -wp 11 -rp 1010 -addr_width 9 -data_width 32 -num_rows 512 -gsr DISABLED -writemode NORMAL -resetmode SYNC -memfile ../../lm32_monitor.mem -memformat hex -e -n lm32_monitor_ram_ecp2  */
   9.628 -/* Tue Jun 16 18:01:57 2009 */
   9.629 -
   9.630 -    // synopsys translate_off
   9.631 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.632 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.633 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.634 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.635 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.636 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.637 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.638 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.639 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.640 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.641 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.642 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.643 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.644 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.645 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.646 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.647 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.648 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.649 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.650 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.651 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.652 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.653 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.654 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.655 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.656 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.657 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.658 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.659 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.660 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.661 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.662 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.663 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.664 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.665 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.666 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.667 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.668 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.669 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_19 = 320'h0000000000000000000000000000000000000000000000000000000000000000000000000003FF81 ;
   9.670 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_18 = 320'h300003FF83300003FF85300003FF873FF4A1004F3FF8A300003FF8C300003FF8E300003FF9030000 ;
   9.671 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_17 = 320'h3FF92300003FF94300003FF96300003FFC100800070003FFFB0000130001100003FF5B1001700000 ;
   9.672 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_16 = 320'h068003FF70058003FF723FFFB300013FF6A00001100001FFAB00000068003FF7B058003FF7D3FFB1 ;
   9.673 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_15 = 320'h3FF8D008003FFB4300000FFB61001B000361001A0002F10019000381001800038100130003310012 ;
   9.674 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_14 = 320'h00033100110003310010000331000900033100080003310007010003FF89058003FF9C3FFF900800 ;
   9.675 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_13 = 320'h070000FFFB30800070003FFD63FFB200800000041000A0004110006010003FF9A000000002410004 ;
   9.676 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_12 = 320'h200081000C0001030014200181001C00020300240000000000000001000000000000000000010000 ;
   9.677 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_11 = 320'h100010FFF310063000501004D000471006D00046100720002C100570001F10077010003FFBC00000 ;
   9.678 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_10 = 320'h30000044003FC0010000100540FFFF0080010000100540FFFF008000880010004200081000C00010 ;
   9.679 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_0F = 320'h30014200181001C00020300240FFDC0000000008100043FFDD100083FFDF100093FFE11000A3FFE3 ;
   9.680 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_0E = 320'h1000B10008100040FFF8000000000C1000410008100083FFE7100093FFE91000A3FFEB1000B3FFED ;
   9.681 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_0D = 320'h100040FFF400000200000FFFF01000000000000210054100000FFFF01000100FF00000100FF00000 ;
   9.682 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_0C = 320'h0FFFE1010001000000000007430084200002009830000300943000030090300003008C2007C10078 ;
   9.683 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_0B = 320'h300702006C1006800064300602005C1005800054300502004C1004800044300402003C1003800034 ;
   9.684 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_0A = 320'h300302002C1002800024300202001C1001800014300102000C100080000000074200842000020098 ;
   9.685 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_09 = 320'h20000200942000020090200002008C3008010078300702006C1006800064300602005C1005800054 ;
   9.686 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_08 = 320'h300502004C1004800044300402003C1003800034300302002C1002800024300202001C1001800014 ;
   9.687 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_07 = 320'h300102000C10008000001F9A00E000000041007810000100881000110001100011000110001100FF ;
   9.688 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_06 = 320'h1F9A0100940080010090008001008C008001009C008001009800800300802007C00074300702006C ;
   9.689 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_05 = 320'h1006800064300602005C1005800054300502004C1004800044300402003C1003800034300302002C ;
   9.690 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_04 = 320'h1002800024300202001C1001800014300102000C100080000000000106603FFC530000007F40E000 ;
   9.691 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_03 = 320'h0003E000BC1000400800200840000A000000000000046000C4100040080020084000120000000000 ;
   9.692 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_02 = 320'h0004E000CC1000400800200840001A000000000000056000D4100040080020084000220000000000 ;
   9.693 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_01 = 320'h00086000DC1000400800300840002A000000000000066000E4100040080020084000320000000000 ;
   9.694 -    defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_00 = 320'h00096000EC1000400800300840003A000000000000000000000000000000000000003E0000000000 ;
   9.695 -    defparam lm32_monitor_ram_ecp2_0_0_1.CSDECODE_B =  3'b000 ;
   9.696 -    defparam lm32_monitor_ram_ecp2_0_0_1.CSDECODE_A =  3'b000 ;
   9.697 -    defparam lm32_monitor_ram_ecp2_0_0_1.WRITEMODE_B = "NORMAL" ;
   9.698 -    defparam lm32_monitor_ram_ecp2_0_0_1.WRITEMODE_A = "NORMAL" ;
   9.699 -    defparam lm32_monitor_ram_ecp2_0_0_1.GSR = "DISABLED" ;
   9.700 -    defparam lm32_monitor_ram_ecp2_0_0_1.RESETMODE = "SYNC" ;
   9.701 -    defparam lm32_monitor_ram_ecp2_0_0_1.REGMODE_B = "NOREG" ;
   9.702 -    defparam lm32_monitor_ram_ecp2_0_0_1.REGMODE_A = "NOREG" ;
   9.703 -    defparam lm32_monitor_ram_ecp2_0_0_1.DATA_WIDTH_B = 18 ;
   9.704 -    defparam lm32_monitor_ram_ecp2_0_0_1.DATA_WIDTH_A = 18 ;
   9.705 -    // synopsys translate_on
   9.706 -    DP16KB lm32_monitor_ram_ecp2_0_0_1 (.DIA0(DataInA[0]), .DIA1(DataInA[1]), 
   9.707 -        .DIA2(DataInA[2]), .DIA3(DataInA[3]), .DIA4(DataInA[4]), .DIA5(DataInA[5]), 
   9.708 -        .DIA6(DataInA[6]), .DIA7(DataInA[7]), .DIA8(DataInA[8]), .DIA9(DataInA[9]), 
   9.709 -        .DIA10(DataInA[10]), .DIA11(DataInA[11]), .DIA12(DataInA[12]), .DIA13(DataInA[13]), 
   9.710 -        .DIA14(DataInA[14]), .DIA15(DataInA[15]), .DIA16(DataInA[16]), .DIA17(DataInA[17]), 
   9.711 -        .ADA0(scuba_vhi), .ADA1(scuba_vhi), .ADA2(scuba_vlo), .ADA3(scuba_vlo), 
   9.712 -        .ADA4(AddressA[0]), .ADA5(AddressA[1]), .ADA6(AddressA[2]), .ADA7(AddressA[3]), 
   9.713 -        .ADA8(AddressA[4]), .ADA9(AddressA[5]), .ADA10(AddressA[6]), .ADA11(AddressA[7]), 
   9.714 -        .ADA12(AddressA[8]), .ADA13(scuba_vlo), .CEA(ClockEnA), .CLKA(ClockA), 
   9.715 -        .WEA(WrA), .CSA0(scuba_vlo), .CSA1(scuba_vlo), .CSA2(scuba_vlo), 
   9.716 -        .RSTA(ResetA), .DIB0(DataInB[0]), .DIB1(DataInB[1]), .DIB2(DataInB[2]), 
   9.717 -        .DIB3(DataInB[3]), .DIB4(DataInB[4]), .DIB5(DataInB[5]), .DIB6(DataInB[6]), 
   9.718 -        .DIB7(DataInB[7]), .DIB8(DataInB[8]), .DIB9(DataInB[9]), .DIB10(DataInB[10]), 
   9.719 -        .DIB11(DataInB[11]), .DIB12(DataInB[12]), .DIB13(DataInB[13]), .DIB14(DataInB[14]), 
   9.720 -        .DIB15(DataInB[15]), .DIB16(DataInB[16]), .DIB17(DataInB[17]), .ADB0(scuba_vhi), 
   9.721 -        .ADB1(scuba_vhi), .ADB2(scuba_vlo), .ADB3(scuba_vlo), .ADB4(AddressB[0]), 
   9.722 -        .ADB5(AddressB[1]), .ADB6(AddressB[2]), .ADB7(AddressB[3]), .ADB8(AddressB[4]), 
   9.723 -        .ADB9(AddressB[5]), .ADB10(AddressB[6]), .ADB11(AddressB[7]), .ADB12(AddressB[8]), 
   9.724 -        .ADB13(scuba_vlo), .CEB(ClockEnB), .CLKB(ClockB), .WEB(WrB), .CSB0(scuba_vlo), 
   9.725 -        .CSB1(scuba_vlo), .CSB2(scuba_vlo), .RSTB(ResetB), .DOA0(QA[0]), 
   9.726 -        .DOA1(QA[1]), .DOA2(QA[2]), .DOA3(QA[3]), .DOA4(QA[4]), .DOA5(QA[5]), 
   9.727 -        .DOA6(QA[6]), .DOA7(QA[7]), .DOA8(QA[8]), .DOA9(QA[9]), .DOA10(QA[10]), 
   9.728 -        .DOA11(QA[11]), .DOA12(QA[12]), .DOA13(QA[13]), .DOA14(QA[14]), 
   9.729 -        .DOA15(QA[15]), .DOA16(QA[16]), .DOA17(QA[17]), .DOB0(QB[0]), .DOB1(QB[1]), 
   9.730 -        .DOB2(QB[2]), .DOB3(QB[3]), .DOB4(QB[4]), .DOB5(QB[5]), .DOB6(QB[6]), 
   9.731 -        .DOB7(QB[7]), .DOB8(QB[8]), .DOB9(QB[9]), .DOB10(QB[10]), .DOB11(QB[11]), 
   9.732 -        .DOB12(QB[12]), .DOB13(QB[13]), .DOB14(QB[14]), .DOB15(QB[15]), 
   9.733 -        .DOB16(QB[16]), .DOB17(QB[17]))
   9.734 -             /* synthesis MEM_LPC_FILE="lm32_monitor_ram_ecp2.lpc" */
   9.735 -             /* synthesis MEM_INIT_FILE="lm32_monitor.mem" */
   9.736 -             /* synthesis INITVAL_3F="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.737 -             /* synthesis INITVAL_3E="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.738 -             /* synthesis INITVAL_3D="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.739 -             /* synthesis INITVAL_3C="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.740 -             /* synthesis INITVAL_3B="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.741 -             /* synthesis INITVAL_3A="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.742 -             /* synthesis INITVAL_39="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.743 -             /* synthesis INITVAL_38="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.744 -             /* synthesis INITVAL_37="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.745 -             /* synthesis INITVAL_36="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.746 -             /* synthesis INITVAL_35="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.747 -             /* synthesis INITVAL_34="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.748 -             /* synthesis INITVAL_33="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.749 -             /* synthesis INITVAL_32="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.750 -             /* synthesis INITVAL_31="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.751 -             /* synthesis INITVAL_30="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.752 -             /* synthesis INITVAL_2F="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.753 -             /* synthesis INITVAL_2E="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.754 -             /* synthesis INITVAL_2D="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.755 -             /* synthesis INITVAL_2C="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.756 -             /* synthesis INITVAL_2B="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.757 -             /* synthesis INITVAL_2A="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.758 -             /* synthesis INITVAL_29="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.759 -             /* synthesis INITVAL_28="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.760 -             /* synthesis INITVAL_27="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.761 -             /* synthesis INITVAL_26="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.762 -             /* synthesis INITVAL_25="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.763 -             /* synthesis INITVAL_24="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.764 -             /* synthesis INITVAL_23="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.765 -             /* synthesis INITVAL_22="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.766 -             /* synthesis INITVAL_21="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.767 -             /* synthesis INITVAL_20="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.768 -             /* synthesis INITVAL_1F="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.769 -             /* synthesis INITVAL_1E="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.770 -             /* synthesis INITVAL_1D="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.771 -             /* synthesis INITVAL_1C="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.772 -             /* synthesis INITVAL_1B="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.773 -             /* synthesis INITVAL_1A="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.774 -             /* synthesis INITVAL_19="0x0000000000000000000000000000000000000000000000000000000000000000000000000003FF81" */
   9.775 -             /* synthesis INITVAL_18="0x300003FF83300003FF85300003FF873FF4A1004F3FF8A300003FF8C300003FF8E300003FF9030000" */
   9.776 -             /* synthesis INITVAL_17="0x3FF92300003FF94300003FF96300003FFC100800070003FFFB0000130001100003FF5B1001700000" */
   9.777 -             /* synthesis INITVAL_16="0x068003FF70058003FF723FFFB300013FF6A00001100001FFAB00000068003FF7B058003FF7D3FFB1" */
   9.778 -             /* synthesis INITVAL_15="0x3FF8D008003FFB4300000FFB61001B000361001A0002F10019000381001800038100130003310012" */
   9.779 -             /* synthesis INITVAL_14="0x00033100110003310010000331000900033100080003310007010003FF89058003FF9C3FFF900800" */
   9.780 -             /* synthesis INITVAL_13="0x070000FFFB30800070003FFD63FFB200800000041000A0004110006010003FF9A000000002410004" */
   9.781 -             /* synthesis INITVAL_12="0x200081000C0001030014200181001C00020300240000000000000001000000000000000000010000" */
   9.782 -             /* synthesis INITVAL_11="0x100010FFF310063000501004D000471006D00046100720002C100570001F10077010003FFBC00000" */
   9.783 -             /* synthesis INITVAL_10="0x30000044003FC0010000100540FFFF0080010000100540FFFF008000880010004200081000C00010" */
   9.784 -             /* synthesis INITVAL_0F="0x30014200181001C00020300240FFDC0000000008100043FFDD100083FFDF100093FFE11000A3FFE3" */
   9.785 -             /* synthesis INITVAL_0E="0x1000B10008100040FFF8000000000C1000410008100083FFE7100093FFE91000A3FFEB1000B3FFED" */
   9.786 -             /* synthesis INITVAL_0D="0x100040FFF400000200000FFFF01000000000000210054100000FFFF01000100FF00000100FF00000" */
   9.787 -             /* synthesis INITVAL_0C="0x0FFFE1010001000000000007430084200002009830000300943000030090300003008C2007C10078" */
   9.788 -             /* synthesis INITVAL_0B="0x300702006C1006800064300602005C1005800054300502004C1004800044300402003C1003800034" */
   9.789 -             /* synthesis INITVAL_0A="0x300302002C1002800024300202001C1001800014300102000C100080000000074200842000020098" */
   9.790 -             /* synthesis INITVAL_09="0x20000200942000020090200002008C3008010078300702006C1006800064300602005C1005800054" */
   9.791 -             /* synthesis INITVAL_08="0x300502004C1004800044300402003C1003800034300302002C1002800024300202001C1001800014" */
   9.792 -             /* synthesis INITVAL_07="0x300102000C10008000001F9A00E000000041007810000100881000110001100011000110001100FF" */
   9.793 -             /* synthesis INITVAL_06="0x1F9A0100940080010090008001008C008001009C008001009800800300802007C00074300702006C" */
   9.794 -             /* synthesis INITVAL_05="0x1006800064300602005C1005800054300502004C1004800044300402003C1003800034300302002C" */
   9.795 -             /* synthesis INITVAL_04="0x1002800024300202001C1001800014300102000C100080000000000106603FFC530000007F40E000" */
   9.796 -             /* synthesis INITVAL_03="0x0003E000BC1000400800200840000A000000000000046000C4100040080020084000120000000000" */
   9.797 -             /* synthesis INITVAL_02="0x0004E000CC1000400800200840001A000000000000056000D4100040080020084000220000000000" */
   9.798 -             /* synthesis INITVAL_01="0x00086000DC1000400800300840002A000000000000066000E4100040080020084000320000000000" */
   9.799 -             /* synthesis INITVAL_00="0x00096000EC1000400800300840003A000000000000000000000000000000000000003E0000000000" */
   9.800 -             /* synthesis CSDECODE_B="0b000" */
   9.801 -             /* synthesis CSDECODE_A="0b000" */
   9.802 -             /* synthesis WRITEMODE_B="NORMAL" */
   9.803 -             /* synthesis WRITEMODE_A="NORMAL" */
   9.804 -             /* synthesis GSR="DISABLED" */
   9.805 -             /* synthesis RESETMODE="SYNC" */
   9.806 -             /* synthesis REGMODE_B="NOREG" */
   9.807 -             /* synthesis REGMODE_A="NOREG" */
   9.808 -             /* synthesis DATA_WIDTH_B="18" */
   9.809 -             /* synthesis DATA_WIDTH_A="18" */;
   9.810 -
   9.811 -    VHI scuba_vhi_inst (.Z(scuba_vhi));
   9.812 -
   9.813 -    VLO scuba_vlo_inst (.Z(scuba_vlo));
   9.814 -
   9.815 -    // synopsys translate_off
   9.816 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.817 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.818 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.819 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.820 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.821 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.822 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.823 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.824 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.825 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.826 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.827 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.828 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.829 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.830 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.831 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.832 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.833 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.834 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.835 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.836 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.837 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.838 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.839 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.840 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.841 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.842 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.843 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.844 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.845 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.846 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.847 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.848 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.849 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.850 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.851 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.852 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.853 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
   9.854 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_19 = 320'h000000000000000000000000000000000000000000000000000000000000000000000000000038FF ;
   9.855 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_18 = 320'h034D2038FF034C2038FF0349A038FF03EFF00D00038FF034CA038FF03492038FF0348A038FF03482 ;
   9.856 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_17 = 320'h038FF0344A038FF03442038FF0343A038FF02E7002430038FF00D6300D5A00C5803EFF0136300D03 ;
   9.857 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_16 = 320'h02E0803EFF02E0803EFF038FF00D5A03EFF00D63010580136300D0302E0803EFF02E0803EFF038FF ;
   9.858 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_15 = 320'h03EFF02E88038FF034DA0170801F100110801F100110801F100110801F100110801F100110801F10 ;
   9.859 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_14 = 320'h0110801F100110801F100110801F100110801F100110801F0802E0803EFF02E0803EFF038FF02E70 ;
   9.860 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_13 = 320'h024500110C0287302430038FF03EFF02E700110801F100110801F0802E0803EFF030E800DE700AE7 ;
   9.861 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_12 = 320'h00AE400AE400AE400AE300AE300AE300AE300AE200D0000D0000D000342000D0000D0000D0003418 ;
   9.862 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_11 = 320'h00D000170801F100110801F100110801F100110801F100110801F100110801F0802E0803EFF00E84 ;
   9.863 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_10 = 320'h00E7B01E0401E030347000D0001708024700347000D00017080247002E08016E7016E4016E4016E4 ;
   9.864 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_0F = 320'h016E3016E3016E3016E3016E200DE7030E800DE700AE703EFF010E003EFF010E003EFF010E003EFF ;
   9.865 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_0E = 320'h010E0016E0016E700DE7030E800DE700AE700AE000CE003EFF00CE003EFF00CE003EFF00CE003EFF ;
   9.866 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_0D = 320'h016E700DE7030E8034700171002470030E80110801F0803470017100247000808030E80081003478 ;
   9.867 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_0C = 320'h011080081002478030F800AE700AE70340F00AE70340700AE70344F00AE70343F00AE700AE700AE7 ;
   9.868 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_0B = 320'h00AE600AE600AE600AE600AE500AE500AE500AE500AE400AE400AE400AE400AE300AE300AE300AE3 ;
   9.869 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_0A = 320'h00AE200AE200AE200AE200AE100AE100AE100AE100AE000AE000AE0030F000AE700AE70340F00AE7 ;
   9.870 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_09 = 320'h0340700AE70344F00AE70343F00AE700AE700AE700AE600AE600AE600AE600AE500AE500AE500AE5 ;
   9.871 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_08 = 320'h00AE400AE400AE400AE400AE300AE300AE300AE300AE200AE200AE200AE200AE100AE100AE100AE1 ;
   9.872 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_07 = 320'h00AE000AE000AE0030E800DEF02EE8016E8016E800AE8016E8000080000800008000080000800808 ;
   9.873 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_06 = 320'h00DE8016E802400016E802448016E802438016E802410016E802408016EF016EF016EF016EE016EE ;
   9.874 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_05 = 320'h016EE016EE016ED016ED016ED016ED016EC016EC016EC016EC016EB016EB016EB016EB016EA016EA ;
   9.875 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_04 = 320'h016EA016EA016E9016E9016E9016E9016E8016E8016E802600016E800DEF038FF00D0700DE702EE8 ;
   9.876 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_03 = 320'h0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600 ;
   9.877 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_02 = 320'h0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600 ;
   9.878 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_01 = 320'h0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600 ;
   9.879 -    defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_00 = 320'h0380003E0000D0802EE0016E703E0002EE80260000D0000D0000D0000D0000D0003E000340802600 ;
   9.880 -    defparam lm32_monitor_ram_ecp2_0_1_0.CSDECODE_B =  3'b000 ;
   9.881 -    defparam lm32_monitor_ram_ecp2_0_1_0.CSDECODE_A =  3'b000 ;
   9.882 -    defparam lm32_monitor_ram_ecp2_0_1_0.WRITEMODE_B = "NORMAL" ;
   9.883 -    defparam lm32_monitor_ram_ecp2_0_1_0.WRITEMODE_A = "NORMAL" ;
   9.884 -    defparam lm32_monitor_ram_ecp2_0_1_0.GSR = "DISABLED" ;
   9.885 -    defparam lm32_monitor_ram_ecp2_0_1_0.RESETMODE = "SYNC" ;
   9.886 -    defparam lm32_monitor_ram_ecp2_0_1_0.REGMODE_B = "NOREG" ;
   9.887 -    defparam lm32_monitor_ram_ecp2_0_1_0.REGMODE_A = "NOREG" ;
   9.888 -    defparam lm32_monitor_ram_ecp2_0_1_0.DATA_WIDTH_B = 18 ;
   9.889 -    defparam lm32_monitor_ram_ecp2_0_1_0.DATA_WIDTH_A = 18 ;
   9.890 -    // synopsys translate_on
   9.891 -    DP16KB lm32_monitor_ram_ecp2_0_1_0 (.DIA0(DataInA[18]), .DIA1(DataInA[19]), 
   9.892 -        .DIA2(DataInA[20]), .DIA3(DataInA[21]), .DIA4(DataInA[22]), .DIA5(DataInA[23]), 
   9.893 -        .DIA6(DataInA[24]), .DIA7(DataInA[25]), .DIA8(DataInA[26]), .DIA9(DataInA[27]), 
   9.894 -        .DIA10(DataInA[28]), .DIA11(DataInA[29]), .DIA12(DataInA[30]), .DIA13(DataInA[31]), 
   9.895 -        .DIA14(scuba_vlo), .DIA15(scuba_vlo), .DIA16(scuba_vlo), .DIA17(scuba_vlo), 
   9.896 -        .ADA0(scuba_vhi), .ADA1(scuba_vhi), .ADA2(scuba_vlo), .ADA3(scuba_vlo), 
   9.897 -        .ADA4(AddressA[0]), .ADA5(AddressA[1]), .ADA6(AddressA[2]), .ADA7(AddressA[3]), 
   9.898 -        .ADA8(AddressA[4]), .ADA9(AddressA[5]), .ADA10(AddressA[6]), .ADA11(AddressA[7]), 
   9.899 -        .ADA12(AddressA[8]), .ADA13(scuba_vlo), .CEA(ClockEnA), .CLKA(ClockA), 
   9.900 -        .WEA(WrA), .CSA0(scuba_vlo), .CSA1(scuba_vlo), .CSA2(scuba_vlo), 
   9.901 -        .RSTA(ResetA), .DIB0(DataInB[18]), .DIB1(DataInB[19]), .DIB2(DataInB[20]), 
   9.902 -        .DIB3(DataInB[21]), .DIB4(DataInB[22]), .DIB5(DataInB[23]), .DIB6(DataInB[24]), 
   9.903 -        .DIB7(DataInB[25]), .DIB8(DataInB[26]), .DIB9(DataInB[27]), .DIB10(DataInB[28]), 
   9.904 -        .DIB11(DataInB[29]), .DIB12(DataInB[30]), .DIB13(DataInB[31]), .DIB14(scuba_vlo), 
   9.905 -        .DIB15(scuba_vlo), .DIB16(scuba_vlo), .DIB17(scuba_vlo), .ADB0(scuba_vhi), 
   9.906 -        .ADB1(scuba_vhi), .ADB2(scuba_vlo), .ADB3(scuba_vlo), .ADB4(AddressB[0]), 
   9.907 -        .ADB5(AddressB[1]), .ADB6(AddressB[2]), .ADB7(AddressB[3]), .ADB8(AddressB[4]), 
   9.908 -        .ADB9(AddressB[5]), .ADB10(AddressB[6]), .ADB11(AddressB[7]), .ADB12(AddressB[8]), 
   9.909 -        .ADB13(scuba_vlo), .CEB(ClockEnB), .CLKB(ClockB), .WEB(WrB), .CSB0(scuba_vlo), 
   9.910 -        .CSB1(scuba_vlo), .CSB2(scuba_vlo), .RSTB(ResetB), .DOA0(QA[18]), 
   9.911 -        .DOA1(QA[19]), .DOA2(QA[20]), .DOA3(QA[21]), .DOA4(QA[22]), .DOA5(QA[23]), 
   9.912 -        .DOA6(QA[24]), .DOA7(QA[25]), .DOA8(QA[26]), .DOA9(QA[27]), .DOA10(QA[28]), 
   9.913 -        .DOA11(QA[29]), .DOA12(QA[30]), .DOA13(QA[31]), .DOA14(), .DOA15(), 
   9.914 -        .DOA16(), .DOA17(), .DOB0(QB[18]), .DOB1(QB[19]), .DOB2(QB[20]), 
   9.915 -        .DOB3(QB[21]), .DOB4(QB[22]), .DOB5(QB[23]), .DOB6(QB[24]), .DOB7(QB[25]), 
   9.916 -        .DOB8(QB[26]), .DOB9(QB[27]), .DOB10(QB[28]), .DOB11(QB[29]), .DOB12(QB[30]), 
   9.917 -        .DOB13(QB[31]), .DOB14(), .DOB15(), .DOB16(), .DOB17())
   9.918 -             /* synthesis MEM_LPC_FILE="lm32_monitor_ram_ecp2.lpc" */
   9.919 -             /* synthesis MEM_INIT_FILE="lm32_monitor.mem" */
   9.920 -             /* synthesis INITVAL_3F="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.921 -             /* synthesis INITVAL_3E="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.922 -             /* synthesis INITVAL_3D="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.923 -             /* synthesis INITVAL_3C="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.924 -             /* synthesis INITVAL_3B="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.925 -             /* synthesis INITVAL_3A="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.926 -             /* synthesis INITVAL_39="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.927 -             /* synthesis INITVAL_38="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.928 -             /* synthesis INITVAL_37="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.929 -             /* synthesis INITVAL_36="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.930 -             /* synthesis INITVAL_35="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.931 -             /* synthesis INITVAL_34="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.932 -             /* synthesis INITVAL_33="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.933 -             /* synthesis INITVAL_32="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.934 -             /* synthesis INITVAL_31="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.935 -             /* synthesis INITVAL_30="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.936 -             /* synthesis INITVAL_2F="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.937 -             /* synthesis INITVAL_2E="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.938 -             /* synthesis INITVAL_2D="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.939 -             /* synthesis INITVAL_2C="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.940 -             /* synthesis INITVAL_2B="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.941 -             /* synthesis INITVAL_2A="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.942 -             /* synthesis INITVAL_29="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.943 -             /* synthesis INITVAL_28="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.944 -             /* synthesis INITVAL_27="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.945 -             /* synthesis INITVAL_26="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.946 -             /* synthesis INITVAL_25="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.947 -             /* synthesis INITVAL_24="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.948 -             /* synthesis INITVAL_23="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.949 -             /* synthesis INITVAL_22="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.950 -             /* synthesis INITVAL_21="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.951 -             /* synthesis INITVAL_20="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.952 -             /* synthesis INITVAL_1F="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.953 -             /* synthesis INITVAL_1E="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.954 -             /* synthesis INITVAL_1D="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.955 -             /* synthesis INITVAL_1C="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.956 -             /* synthesis INITVAL_1B="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.957 -             /* synthesis INITVAL_1A="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
   9.958 -             /* synthesis INITVAL_19="0x000000000000000000000000000000000000000000000000000000000000000000000000000038FF" */
   9.959 -             /* synthesis INITVAL_18="0x034D2038FF034C2038FF0349A038FF03EFF00D00038FF034CA038FF03492038FF0348A038FF03482" */
   9.960 -             /* synthesis INITVAL_17="0x038FF0344A038FF03442038FF0343A038FF02E7002430038FF00D6300D5A00C5803EFF0136300D03" */
   9.961 -             /* synthesis INITVAL_16="0x02E0803EFF02E0803EFF038FF00D5A03EFF00D63010580136300D0302E0803EFF02E0803EFF038FF" */
   9.962 -             /* synthesis INITVAL_15="0x03EFF02E88038FF034DA0170801F100110801F100110801F100110801F100110801F100110801F10" */
   9.963 -             /* synthesis INITVAL_14="0x0110801F100110801F100110801F100110801F100110801F0802E0803EFF02E0803EFF038FF02E70" */
   9.964 -             /* synthesis INITVAL_13="0x024500110C0287302430038FF03EFF02E700110801F100110801F0802E0803EFF030E800DE700AE7" */
   9.965 -             /* synthesis INITVAL_12="0x00AE400AE400AE400AE300AE300AE300AE300AE200D0000D0000D000342000D0000D0000D0003418" */
   9.966 -             /* synthesis INITVAL_11="0x00D000170801F100110801F100110801F100110801F100110801F100110801F0802E0803EFF00E84" */
   9.967 -             /* synthesis INITVAL_10="0x00E7B01E0401E030347000D0001708024700347000D00017080247002E08016E7016E4016E4016E4" */
   9.968 -             /* synthesis INITVAL_0F="0x016E3016E3016E3016E3016E200DE7030E800DE700AE703EFF010E003EFF010E003EFF010E003EFF" */
   9.969 -             /* synthesis INITVAL_0E="0x010E0016E0016E700DE7030E800DE700AE700AE000CE003EFF00CE003EFF00CE003EFF00CE003EFF" */
   9.970 -             /* synthesis INITVAL_0D="0x016E700DE7030E8034700171002470030E80110801F0803470017100247000808030E80081003478" */
   9.971 -             /* synthesis INITVAL_0C="0x011080081002478030F800AE700AE70340F00AE70340700AE70344F00AE70343F00AE700AE700AE7" */
   9.972 -             /* synthesis INITVAL_0B="0x00AE600AE600AE600AE600AE500AE500AE500AE500AE400AE400AE400AE400AE300AE300AE300AE3" */
   9.973 -             /* synthesis INITVAL_0A="0x00AE200AE200AE200AE200AE100AE100AE100AE100AE000AE000AE0030F000AE700AE70340F00AE7" */
   9.974 -             /* synthesis INITVAL_09="0x0340700AE70344F00AE70343F00AE700AE700AE700AE600AE600AE600AE600AE500AE500AE500AE5" */
   9.975 -             /* synthesis INITVAL_08="0x00AE400AE400AE400AE400AE300AE300AE300AE300AE200AE200AE200AE200AE100AE100AE100AE1" */
   9.976 -             /* synthesis INITVAL_07="0x00AE000AE000AE0030E800DEF02EE8016E8016E800AE8016E8000080000800008000080000800808" */
   9.977 -             /* synthesis INITVAL_06="0x00DE8016E802400016E802448016E802438016E802410016E802408016EF016EF016EF016EE016EE" */
   9.978 -             /* synthesis INITVAL_05="0x016EE016EE016ED016ED016ED016ED016EC016EC016EC016EC016EB016EB016EB016EB016EA016EA" */
   9.979 -             /* synthesis INITVAL_04="0x016EA016EA016E9016E9016E9016E9016E8016E8016E802600016E800DEF038FF00D0700DE702EE8" */
   9.980 -             /* synthesis INITVAL_03="0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600" */
   9.981 -             /* synthesis INITVAL_02="0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600" */
   9.982 -             /* synthesis INITVAL_01="0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600" */
   9.983 -             /* synthesis INITVAL_00="0x0380003E0000D0802EE0016E703E0002EE80260000D0000D0000D0000D0000D0003E000340802600" */
   9.984 -             /* synthesis CSDECODE_B="0b000" */
   9.985 -             /* synthesis CSDECODE_A="0b000" */
   9.986 -             /* synthesis WRITEMODE_B="NORMAL" */
   9.987 -             /* synthesis WRITEMODE_A="NORMAL" */
   9.988 -             /* synthesis GSR="DISABLED" */
   9.989 -             /* synthesis RESETMODE="SYNC" */
   9.990 -             /* synthesis REGMODE_B="NOREG" */
   9.991 -             /* synthesis REGMODE_A="NOREG" */
   9.992 -             /* synthesis DATA_WIDTH_B="18" */
   9.993 -             /* synthesis DATA_WIDTH_A="18" */;
   9.994 -
   9.995 -
   9.996 -
   9.997 -    // exemplar begin
   9.998 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 MEM_LPC_FILE lm32_monitor_ram_ecp2.lpc
   9.999 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 MEM_INIT_FILE lm32_monitor.mem
  9.1000 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_3F 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1001 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_3E 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1002 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_3D 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1003 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_3C 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1004 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_3B 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1005 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_3A 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1006 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_39 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1007 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_38 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1008 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_37 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1009 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_36 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1010 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_35 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1011 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_34 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1012 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_33 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1013 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_32 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1014 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_31 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1015 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_30 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1016 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_2F 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1017 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_2E 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1018 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_2D 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1019 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_2C 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1020 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_2B 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1021 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_2A 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1022 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_29 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1023 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_28 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1024 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_27 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1025 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_26 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1026 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_25 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1027 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_24 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1028 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_23 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1029 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_22 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1030 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_21 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1031 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_20 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1032 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_1F 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1033 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_1E 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1034 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_1D 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1035 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_1C 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1036 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_1B 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1037 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_1A 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1038 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_19 0x0000000000000000000000000000000000000000000000000000000000000000000000000003FF81
  9.1039 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_18 0x300003FF83300003FF85300003FF873FF4A1004F3FF8A300003FF8C300003FF8E300003FF9030000
  9.1040 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_17 0x3FF92300003FF94300003FF96300003FFC100800070003FFFB0000130001100003FF5B1001700000
  9.1041 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_16 0x068003FF70058003FF723FFFB300013FF6A00001100001FFAB00000068003FF7B058003FF7D3FFB1
  9.1042 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_15 0x3FF8D008003FFB4300000FFB61001B000361001A0002F10019000381001800038100130003310012
  9.1043 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_14 0x00033100110003310010000331000900033100080003310007010003FF89058003FF9C3FFF900800
  9.1044 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_13 0x070000FFFB30800070003FFD63FFB200800000041000A0004110006010003FF9A000000002410004
  9.1045 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_12 0x200081000C0001030014200181001C00020300240000000000000001000000000000000000010000
  9.1046 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_11 0x100010FFF310063000501004D000471006D00046100720002C100570001F10077010003FFBC00000
  9.1047 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_10 0x30000044003FC0010000100540FFFF0080010000100540FFFF008000880010004200081000C00010
  9.1048 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_0F 0x30014200181001C00020300240FFDC0000000008100043FFDD100083FFDF100093FFE11000A3FFE3
  9.1049 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_0E 0x1000B10008100040FFF8000000000C1000410008100083FFE7100093FFE91000A3FFEB1000B3FFED
  9.1050 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_0D 0x100040FFF400000200000FFFF01000000000000210054100000FFFF01000100FF00000100FF00000
  9.1051 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_0C 0x0FFFE1010001000000000007430084200002009830000300943000030090300003008C2007C10078
  9.1052 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_0B 0x300702006C1006800064300602005C1005800054300502004C1004800044300402003C1003800034
  9.1053 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_0A 0x300302002C1002800024300202001C1001800014300102000C100080000000074200842000020098
  9.1054 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_09 0x20000200942000020090200002008C3008010078300702006C1006800064300602005C1005800054
  9.1055 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_08 0x300502004C1004800044300402003C1003800034300302002C1002800024300202001C1001800014
  9.1056 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_07 0x300102000C10008000001F9A00E000000041007810000100881000110001100011000110001100FF
  9.1057 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_06 0x1F9A0100940080010090008001008C008001009C008001009800800300802007C00074300702006C
  9.1058 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_05 0x1006800064300602005C1005800054300502004C1004800044300402003C1003800034300302002C
  9.1059 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_04 0x1002800024300202001C1001800014300102000C100080000000000106603FFC530000007F40E000
  9.1060 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_03 0x0003E000BC1000400800200840000A000000000000046000C4100040080020084000120000000000
  9.1061 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_02 0x0004E000CC1000400800200840001A000000000000056000D4100040080020084000220000000000
  9.1062 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_01 0x00086000DC1000400800300840002A000000000000066000E4100040080020084000320000000000
  9.1063 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_00 0x00096000EC1000400800300840003A000000000000000000000000000000000000003E0000000000
  9.1064 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 CSDECODE_B 0b000
  9.1065 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 CSDECODE_A 0b000
  9.1066 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 WRITEMODE_B NORMAL
  9.1067 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 WRITEMODE_A NORMAL
  9.1068 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 GSR DISABLED
  9.1069 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 RESETMODE SYNC
  9.1070 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 REGMODE_B NOREG
  9.1071 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 REGMODE_A NOREG
  9.1072 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 DATA_WIDTH_B 18
  9.1073 -    // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 DATA_WIDTH_A 18
  9.1074 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 MEM_LPC_FILE lm32_monitor_ram_ecp2.lpc
  9.1075 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 MEM_INIT_FILE lm32_monitor.mem
  9.1076 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_3F 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1077 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_3E 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1078 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_3D 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1079 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_3C 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1080 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_3B 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1081 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_3A 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1082 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_39 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1083 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_38 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1084 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_37 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1085 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_36 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1086 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_35 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1087 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_34 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1088 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_33 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1089 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_32 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1090 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_31 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1091 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_30 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1092 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_2F 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1093 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_2E 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1094 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_2D 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1095 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_2C 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1096 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_2B 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1097 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_2A 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1098 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_29 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1099 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_28 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1100 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_27 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1101 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_26 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1102 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_25 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1103 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_24 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1104 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_23 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1105 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_22 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1106 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_21 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1107 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_20 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1108 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_1F 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1109 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_1E 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1110 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_1D 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1111 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_1C 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1112 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_1B 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1113 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_1A 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1114 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_19 0x000000000000000000000000000000000000000000000000000000000000000000000000000038FF
  9.1115 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_18 0x034D2038FF034C2038FF0349A038FF03EFF00D00038FF034CA038FF03492038FF0348A038FF03482
  9.1116 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_17 0x038FF0344A038FF03442038FF0343A038FF02E7002430038FF00D6300D5A00C5803EFF0136300D03
  9.1117 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_16 0x02E0803EFF02E0803EFF038FF00D5A03EFF00D63010580136300D0302E0803EFF02E0803EFF038FF
  9.1118 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_15 0x03EFF02E88038FF034DA0170801F100110801F100110801F100110801F100110801F100110801F10
  9.1119 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_14 0x0110801F100110801F100110801F100110801F100110801F0802E0803EFF02E0803EFF038FF02E70
  9.1120 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_13 0x024500110C0287302430038FF03EFF02E700110801F100110801F0802E0803EFF030E800DE700AE7
  9.1121 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_12 0x00AE400AE400AE400AE300AE300AE300AE300AE200D0000D0000D000342000D0000D0000D0003418
  9.1122 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_11 0x00D000170801F100110801F100110801F100110801F100110801F100110801F0802E0803EFF00E84
  9.1123 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_10 0x00E7B01E0401E030347000D0001708024700347000D00017080247002E08016E7016E4016E4016E4
  9.1124 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_0F 0x016E3016E3016E3016E3016E200DE7030E800DE700AE703EFF010E003EFF010E003EFF010E003EFF
  9.1125 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_0E 0x010E0016E0016E700DE7030E800DE700AE700AE000CE003EFF00CE003EFF00CE003EFF00CE003EFF
  9.1126 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_0D 0x016E700DE7030E8034700171002470030E80110801F0803470017100247000808030E80081003478
  9.1127 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_0C 0x011080081002478030F800AE700AE70340F00AE70340700AE70344F00AE70343F00AE700AE700AE7
  9.1128 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_0B 0x00AE600AE600AE600AE600AE500AE500AE500AE500AE400AE400AE400AE400AE300AE300AE300AE3
  9.1129 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_0A 0x00AE200AE200AE200AE200AE100AE100AE100AE100AE000AE000AE0030F000AE700AE70340F00AE7
  9.1130 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_09 0x0340700AE70344F00AE70343F00AE700AE700AE700AE600AE600AE600AE600AE500AE500AE500AE5
  9.1131 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_08 0x00AE400AE400AE400AE400AE300AE300AE300AE300AE200AE200AE200AE200AE100AE100AE100AE1
  9.1132 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_07 0x00AE000AE000AE0030E800DEF02EE8016E8016E800AE8016E8000080000800008000080000800808
  9.1133 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_06 0x00DE8016E802400016E802448016E802438016E802410016E802408016EF016EF016EF016EE016EE
  9.1134 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_05 0x016EE016EE016ED016ED016ED016ED016EC016EC016EC016EC016EB016EB016EB016EB016EA016EA
  9.1135 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_04 0x016EA016EA016E9016E9016E9016E9016E8016E8016E802600016E800DEF038FF00D0700DE702EE8
  9.1136 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_03 0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600
  9.1137 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_02 0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600
  9.1138 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_01 0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600
  9.1139 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_00 0x0380003E0000D0802EE0016E703E0002EE80260000D0000D0000D0000D0000D0003E000340802600
  9.1140 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 CSDECODE_B 0b000
  9.1141 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 CSDECODE_A 0b000
  9.1142 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 WRITEMODE_B NORMAL
  9.1143 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 WRITEMODE_A NORMAL
  9.1144 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 GSR DISABLED
  9.1145 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 RESETMODE SYNC
  9.1146 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 REGMODE_B NOREG
  9.1147 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 REGMODE_A NOREG
  9.1148 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 DATA_WIDTH_B 18
  9.1149 -    // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 DATA_WIDTH_A 18
  9.1150 -    // exemplar end
  9.1151 -
  9.1152 -      end   else if (lat_family == "SC" || lat_family == "SCM") begin 
  9.1153 -
  9.1154 -/* Verilog netlist generated by SCUBA ispLever_v8.0_ALPHA (69) */
  9.1155 -/* Module Version: 7.0 */
  9.1156 -/* c:\ispTOOLS8_0\ispFPGA\bin\nt\scuba.exe -w -lang verilog -synth synplify -bus_exp 7 -bb -arch or5s00 -type bram -wp 11 -rp 1010 -addr_width 9 -data_width 32 -num_rows 512 -gsr DISABLED -sync_reset -memfile ../../lm32_monitor.mem -memformat hex -e -n sc_rom_monitor  */
  9.1157 -/* Tue Jun 16 18:01:58 2009 */
  9.1158 -
  9.1159 -    // synopsys translate_off
  9.1160 -    defparam sc_rom_monitor_0_0_1.INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1161 -    defparam sc_rom_monitor_0_0_1.INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1162 -    defparam sc_rom_monitor_0_0_1.INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1163 -    defparam sc_rom_monitor_0_0_1.INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1164 -    defparam sc_rom_monitor_0_0_1.INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1165 -    defparam sc_rom_monitor_0_0_1.INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1166 -    defparam sc_rom_monitor_0_0_1.INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1167 -    defparam sc_rom_monitor_0_0_1.INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1168 -    defparam sc_rom_monitor_0_0_1.INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1169 -    defparam sc_rom_monitor_0_0_1.INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1170 -    defparam sc_rom_monitor_0_0_1.INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1171 -    defparam sc_rom_monitor_0_0_1.INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1172 -    defparam sc_rom_monitor_0_0_1.INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1173 -    defparam sc_rom_monitor_0_0_1.INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1174 -    defparam sc_rom_monitor_0_0_1.INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1175 -    defparam sc_rom_monitor_0_0_1.INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1176 -    defparam sc_rom_monitor_0_0_1.INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1177 -    defparam sc_rom_monitor_0_0_1.INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1178 -    defparam sc_rom_monitor_0_0_1.INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1179 -    defparam sc_rom_monitor_0_0_1.INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1180 -    defparam sc_rom_monitor_0_0_1.INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1181 -    defparam sc_rom_monitor_0_0_1.INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1182 -    defparam sc_rom_monitor_0_0_1.INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1183 -    defparam sc_rom_monitor_0_0_1.INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1184 -    defparam sc_rom_monitor_0_0_1.INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1185 -    defparam sc_rom_monitor_0_0_1.INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1186 -    defparam sc_rom_monitor_0_0_1.INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1187 -    defparam sc_rom_monitor_0_0_1.INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1188 -    defparam sc_rom_monitor_0_0_1.INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1189 -    defparam sc_rom_monitor_0_0_1.INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1190 -    defparam sc_rom_monitor_0_0_1.INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1191 -    defparam sc_rom_monitor_0_0_1.INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1192 -    defparam sc_rom_monitor_0_0_1.INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1193 -    defparam sc_rom_monitor_0_0_1.INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1194 -    defparam sc_rom_monitor_0_0_1.INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1195 -    defparam sc_rom_monitor_0_0_1.INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1196 -    defparam sc_rom_monitor_0_0_1.INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1197 -    defparam sc_rom_monitor_0_0_1.INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1198 -    defparam sc_rom_monitor_0_0_1.INITVAL_19 = 320'h0000000000000000000000000000000000000000000000000000000000000000000000000003FF81 ;
  9.1199 -    defparam sc_rom_monitor_0_0_1.INITVAL_18 = 320'h300003FF83300003FF85300003FF873FF4A1004F3FF8A300003FF8C300003FF8E300003FF9030000 ;
  9.1200 -    defparam sc_rom_monitor_0_0_1.INITVAL_17 = 320'h3FF92300003FF94300003FF96300003FFC100800070003FFFB0000130001100003FF5B1001700000 ;
  9.1201 -    defparam sc_rom_monitor_0_0_1.INITVAL_16 = 320'h068003FF70058003FF723FFFB300013FF6A00001100001FFAB00000068003FF7B058003FF7D3FFB1 ;
  9.1202 -    defparam sc_rom_monitor_0_0_1.INITVAL_15 = 320'h3FF8D008003FFB4300000FFB61001B000361001A0002F10019000381001800038100130003310012 ;
  9.1203 -    defparam sc_rom_monitor_0_0_1.INITVAL_14 = 320'h00033100110003310010000331000900033100080003310007010003FF89058003FF9C3FFF900800 ;
  9.1204 -    defparam sc_rom_monitor_0_0_1.INITVAL_13 = 320'h070000FFFB30800070003FFD63FFB200800000041000A0004110006010003FF9A000000002410004 ;
  9.1205 -    defparam sc_rom_monitor_0_0_1.INITVAL_12 = 320'h200081000C0001030014200181001C00020300240000000000000001000000000000000000010000 ;
  9.1206 -    defparam sc_rom_monitor_0_0_1.INITVAL_11 = 320'h100010FFF310063000501004D000471006D00046100720002C100570001F10077010003FFBC00000 ;
  9.1207 -    defparam sc_rom_monitor_0_0_1.INITVAL_10 = 320'h30000044003FC0010000100540FFFF0080010000100540FFFF008000880010004200081000C00010 ;
  9.1208 -    defparam sc_rom_monitor_0_0_1.INITVAL_0F = 320'h30014200181001C00020300240FFDC0000000008100043FFDD100083FFDF100093FFE11000A3FFE3 ;
  9.1209 -    defparam sc_rom_monitor_0_0_1.INITVAL_0E = 320'h1000B10008100040FFF8000000000C1000410008100083FFE7100093FFE91000A3FFEB1000B3FFED ;
  9.1210 -    defparam sc_rom_monitor_0_0_1.INITVAL_0D = 320'h100040FFF400000200000FFFF01000000000000210054100000FFFF01000100FF00000100FF00000 ;
  9.1211 -    defparam sc_rom_monitor_0_0_1.INITVAL_0C = 320'h0FFFE1010001000000000007430084200002009830000300943000030090300003008C2007C10078 ;
  9.1212 -    defparam sc_rom_monitor_0_0_1.INITVAL_0B = 320'h300702006C1006800064300602005C1005800054300502004C1004800044300402003C1003800034 ;
  9.1213 -    defparam sc_rom_monitor_0_0_1.INITVAL_0A = 320'h300302002C1002800024300202001C1001800014300102000C100080000000074200842000020098 ;
  9.1214 -    defparam sc_rom_monitor_0_0_1.INITVAL_09 = 320'h20000200942000020090200002008C3008010078300702006C1006800064300602005C1005800054 ;
  9.1215 -    defparam sc_rom_monitor_0_0_1.INITVAL_08 = 320'h300502004C1004800044300402003C1003800034300302002C1002800024300202001C1001800014 ;
  9.1216 -    defparam sc_rom_monitor_0_0_1.INITVAL_07 = 320'h300102000C10008000001F9A00E000000041007810000100881000110001100011000110001100FF ;
  9.1217 -    defparam sc_rom_monitor_0_0_1.INITVAL_06 = 320'h1F9A0100940080010090008001008C008001009C008001009800800300802007C00074300702006C ;
  9.1218 -    defparam sc_rom_monitor_0_0_1.INITVAL_05 = 320'h1006800064300602005C1005800054300502004C1004800044300402003C1003800034300302002C ;
  9.1219 -    defparam sc_rom_monitor_0_0_1.INITVAL_04 = 320'h1002800024300202001C1001800014300102000C100080000000000106603FFC530000007F40E000 ;
  9.1220 -    defparam sc_rom_monitor_0_0_1.INITVAL_03 = 320'h0003E000BC1000400800200840000A000000000000046000C4100040080020084000120000000000 ;
  9.1221 -    defparam sc_rom_monitor_0_0_1.INITVAL_02 = 320'h0004E000CC1000400800200840001A000000000000056000D4100040080020084000220000000000 ;
  9.1222 -    defparam sc_rom_monitor_0_0_1.INITVAL_01 = 320'h00086000DC1000400800300840002A000000000000066000E4100040080020084000320000000000 ;
  9.1223 -    defparam sc_rom_monitor_0_0_1.INITVAL_00 = 320'h00096000EC1000400800300840003A000000000000000000000000000000000000003E0000000000 ;
  9.1224 -    defparam sc_rom_monitor_0_0_1.CSDECODE_B =  3'b000 ;
  9.1225 -    defparam sc_rom_monitor_0_0_1.CSDECODE_A =  3'b000 ;
  9.1226 -    defparam sc_rom_monitor_0_0_1.WRITEMODE_B = "NORMAL" ;
  9.1227 -    defparam sc_rom_monitor_0_0_1.WRITEMODE_A = "NORMAL" ;
  9.1228 -    defparam sc_rom_monitor_0_0_1.GSR = "DISABLED" ;
  9.1229 -    defparam sc_rom_monitor_0_0_1.RESETMODE = "SYNC" ;
  9.1230 -    defparam sc_rom_monitor_0_0_1.REGMODE_B = "NOREG" ;
  9.1231 -    defparam sc_rom_monitor_0_0_1.REGMODE_A = "NOREG" ;
  9.1232 -    defparam sc_rom_monitor_0_0_1.DATA_WIDTH_B = 18 ;
  9.1233 -    defparam sc_rom_monitor_0_0_1.DATA_WIDTH_A = 18 ;
  9.1234 -    // synopsys translate_on
  9.1235 -    DP16KA sc_rom_monitor_0_0_1 (.DIA0(DataInA[0]), .DIA1(DataInA[1]), .DIA2(DataInA[2]), 
  9.1236 -        .DIA3(DataInA[3]), .DIA4(DataInA[4]), .DIA5(DataInA[5]), .DIA6(DataInA[6]), 
  9.1237 -        .DIA7(DataInA[7]), .DIA8(DataInA[8]), .DIA9(DataInA[9]), .DIA10(DataInA[10]), 
  9.1238 -        .DIA11(DataInA[11]), .DIA12(DataInA[12]), .DIA13(DataInA[13]), .DIA14(DataInA[14]), 
  9.1239 -        .DIA15(DataInA[15]), .DIA16(DataInA[16]), .DIA17(DataInA[17]), .ADA0(scuba_vhi), 
  9.1240 -        .ADA1(scuba_vhi), .ADA2(scuba_vlo), .ADA3(scuba_vlo), .ADA4(AddressA[0]), 
  9.1241 -        .ADA5(AddressA[1]), .ADA6(AddressA[2]), .ADA7(AddressA[3]), .ADA8(AddressA[4]), 
  9.1242 -        .ADA9(AddressA[5]), .ADA10(AddressA[6]), .ADA11(AddressA[7]), .ADA12(AddressA[8]), 
  9.1243 -        .ADA13(scuba_vlo), .CEA(ClockEnA), .CLKA(ClockA), .WEA(WrA), .CSA0(scuba_vlo), 
  9.1244 -        .CSA1(scuba_vlo), .CSA2(scuba_vlo), .RSTA(ResetA), .DIB0(DataInB[0]), 
  9.1245 -        .DIB1(DataInB[1]), .DIB2(DataInB[2]), .DIB3(DataInB[3]), .DIB4(DataInB[4]), 
  9.1246 -        .DIB5(DataInB[5]), .DIB6(DataInB[6]), .DIB7(DataInB[7]), .DIB8(DataInB[8]), 
  9.1247 -        .DIB9(DataInB[9]), .DIB10(DataInB[10]), .DIB11(DataInB[11]), .DIB12(DataInB[12]), 
  9.1248 -        .DIB13(DataInB[13]), .DIB14(DataInB[14]), .DIB15(DataInB[15]), .DIB16(DataInB[16]), 
  9.1249 -        .DIB17(DataInB[17]), .ADB0(scuba_vhi), .ADB1(scuba_vhi), .ADB2(scuba_vlo), 
  9.1250 -        .ADB3(scuba_vlo), .ADB4(AddressB[0]), .ADB5(AddressB[1]), .ADB6(AddressB[2]), 
  9.1251 -        .ADB7(AddressB[3]), .ADB8(AddressB[4]), .ADB9(AddressB[5]), .ADB10(AddressB[6]), 
  9.1252 -        .ADB11(AddressB[7]), .ADB12(AddressB[8]), .ADB13(scuba_vlo), .CEB(ClockEnB), 
  9.1253 -        .CLKB(ClockB), .WEB(WrB), .CSB0(scuba_vlo), .CSB1(scuba_vlo), .CSB2(scuba_vlo), 
  9.1254 -        .RSTB(ResetB), .DOA0(QA[0]), .DOA1(QA[1]), .DOA2(QA[2]), .DOA3(QA[3]), 
  9.1255 -        .DOA4(QA[4]), .DOA5(QA[5]), .DOA6(QA[6]), .DOA7(QA[7]), .DOA8(QA[8]), 
  9.1256 -        .DOA9(QA[9]), .DOA10(QA[10]), .DOA11(QA[11]), .DOA12(QA[12]), .DOA13(QA[13]), 
  9.1257 -        .DOA14(QA[14]), .DOA15(QA[15]), .DOA16(QA[16]), .DOA17(QA[17]), 
  9.1258 -        .DOB0(QB[0]), .DOB1(QB[1]), .DOB2(QB[2]), .DOB3(QB[3]), .DOB4(QB[4]), 
  9.1259 -        .DOB5(QB[5]), .DOB6(QB[6]), .DOB7(QB[7]), .DOB8(QB[8]), .DOB9(QB[9]), 
  9.1260 -        .DOB10(QB[10]), .DOB11(QB[11]), .DOB12(QB[12]), .DOB13(QB[13]), 
  9.1261 -        .DOB14(QB[14]), .DOB15(QB[15]), .DOB16(QB[16]), .DOB17(QB[17]))
  9.1262 -             /* synthesis MEM_LPC_FILE="sc_rom_monitor.lpc" */
  9.1263 -             /* synthesis MEM_INIT_FILE="lm32_monitor.mem" */
  9.1264 -             /* synthesis INITVAL_3F="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1265 -             /* synthesis INITVAL_3E="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1266 -             /* synthesis INITVAL_3D="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1267 -             /* synthesis INITVAL_3C="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1268 -             /* synthesis INITVAL_3B="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1269 -             /* synthesis INITVAL_3A="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1270 -             /* synthesis INITVAL_39="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1271 -             /* synthesis INITVAL_38="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1272 -             /* synthesis INITVAL_37="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1273 -             /* synthesis INITVAL_36="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1274 -             /* synthesis INITVAL_35="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1275 -             /* synthesis INITVAL_34="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1276 -             /* synthesis INITVAL_33="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1277 -             /* synthesis INITVAL_32="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1278 -             /* synthesis INITVAL_31="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1279 -             /* synthesis INITVAL_30="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1280 -             /* synthesis INITVAL_2F="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1281 -             /* synthesis INITVAL_2E="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1282 -             /* synthesis INITVAL_2D="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1283 -             /* synthesis INITVAL_2C="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1284 -             /* synthesis INITVAL_2B="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1285 -             /* synthesis INITVAL_2A="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1286 -             /* synthesis INITVAL_29="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1287 -             /* synthesis INITVAL_28="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1288 -             /* synthesis INITVAL_27="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1289 -             /* synthesis INITVAL_26="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1290 -             /* synthesis INITVAL_25="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1291 -             /* synthesis INITVAL_24="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1292 -             /* synthesis INITVAL_23="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1293 -             /* synthesis INITVAL_22="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1294 -             /* synthesis INITVAL_21="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1295 -             /* synthesis INITVAL_20="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1296 -             /* synthesis INITVAL_1F="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1297 -             /* synthesis INITVAL_1E="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1298 -             /* synthesis INITVAL_1D="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1299 -             /* synthesis INITVAL_1C="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1300 -             /* synthesis INITVAL_1B="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1301 -             /* synthesis INITVAL_1A="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1302 -             /* synthesis INITVAL_19="0x0000000000000000000000000000000000000000000000000000000000000000000000000003FF81" */
  9.1303 -             /* synthesis INITVAL_18="0x300003FF83300003FF85300003FF873FF4A1004F3FF8A300003FF8C300003FF8E300003FF9030000" */
  9.1304 -             /* synthesis INITVAL_17="0x3FF92300003FF94300003FF96300003FFC100800070003FFFB0000130001100003FF5B1001700000" */
  9.1305 -             /* synthesis INITVAL_16="0x068003FF70058003FF723FFFB300013FF6A00001100001FFAB00000068003FF7B058003FF7D3FFB1" */
  9.1306 -             /* synthesis INITVAL_15="0x3FF8D008003FFB4300000FFB61001B000361001A0002F10019000381001800038100130003310012" */
  9.1307 -             /* synthesis INITVAL_14="0x00033100110003310010000331000900033100080003310007010003FF89058003FF9C3FFF900800" */
  9.1308 -             /* synthesis INITVAL_13="0x070000FFFB30800070003FFD63FFB200800000041000A0004110006010003FF9A000000002410004" */
  9.1309 -             /* synthesis INITVAL_12="0x200081000C0001030014200181001C00020300240000000000000001000000000000000000010000" */
  9.1310 -             /* synthesis INITVAL_11="0x100010FFF310063000501004D000471006D00046100720002C100570001F10077010003FFBC00000" */
  9.1311 -             /* synthesis INITVAL_10="0x30000044003FC0010000100540FFFF0080010000100540FFFF008000880010004200081000C00010" */
  9.1312 -             /* synthesis INITVAL_0F="0x30014200181001C00020300240FFDC0000000008100043FFDD100083FFDF100093FFE11000A3FFE3" */
  9.1313 -             /* synthesis INITVAL_0E="0x1000B10008100040FFF8000000000C1000410008100083FFE7100093FFE91000A3FFEB1000B3FFED" */
  9.1314 -             /* synthesis INITVAL_0D="0x100040FFF400000200000FFFF01000000000000210054100000FFFF01000100FF00000100FF00000" */
  9.1315 -             /* synthesis INITVAL_0C="0x0FFFE1010001000000000007430084200002009830000300943000030090300003008C2007C10078" */
  9.1316 -             /* synthesis INITVAL_0B="0x300702006C1006800064300602005C1005800054300502004C1004800044300402003C1003800034" */
  9.1317 -             /* synthesis INITVAL_0A="0x300302002C1002800024300202001C1001800014300102000C100080000000074200842000020098" */
  9.1318 -             /* synthesis INITVAL_09="0x20000200942000020090200002008C3008010078300702006C1006800064300602005C1005800054" */
  9.1319 -             /* synthesis INITVAL_08="0x300502004C1004800044300402003C1003800034300302002C1002800024300202001C1001800014" */
  9.1320 -             /* synthesis INITVAL_07="0x300102000C10008000001F9A00E000000041007810000100881000110001100011000110001100FF" */
  9.1321 -             /* synthesis INITVAL_06="0x1F9A0100940080010090008001008C008001009C008001009800800300802007C00074300702006C" */
  9.1322 -             /* synthesis INITVAL_05="0x1006800064300602005C1005800054300502004C1004800044300402003C1003800034300302002C" */
  9.1323 -             /* synthesis INITVAL_04="0x1002800024300202001C1001800014300102000C100080000000000106603FFC530000007F40E000" */
  9.1324 -             /* synthesis INITVAL_03="0x0003E000BC1000400800200840000A000000000000046000C4100040080020084000120000000000" */
  9.1325 -             /* synthesis INITVAL_02="0x0004E000CC1000400800200840001A000000000000056000D4100040080020084000220000000000" */
  9.1326 -             /* synthesis INITVAL_01="0x00086000DC1000400800300840002A000000000000066000E4100040080020084000320000000000" */
  9.1327 -             /* synthesis INITVAL_00="0x00096000EC1000400800300840003A000000000000000000000000000000000000003E0000000000" */
  9.1328 -             /* synthesis CSDECODE_B="0b000" */
  9.1329 -             /* synthesis CSDECODE_A="0b000" */
  9.1330 -             /* synthesis WRITEMODE_B="NORMAL" */
  9.1331 -             /* synthesis WRITEMODE_A="NORMAL" */
  9.1332 -             /* synthesis GSR="DISABLED" */
  9.1333 -             /* synthesis RESETMODE="SYNC" */
  9.1334 -             /* synthesis REGMODE_B="NOREG" */
  9.1335 -             /* synthesis REGMODE_A="NOREG" */
  9.1336 -             /* synthesis DATA_WIDTH_B="18" */
  9.1337 -             /* synthesis DATA_WIDTH_A="18" */;
  9.1338 -
  9.1339 -    VHI scuba_vhi_inst (.Z(scuba_vhi));
  9.1340 -
  9.1341 -    VLO scuba_vlo_inst (.Z(scuba_vlo));
  9.1342 -
  9.1343 -    // synopsys translate_off
  9.1344 -    defparam sc_rom_monitor_0_1_0.INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1345 -    defparam sc_rom_monitor_0_1_0.INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1346 -    defparam sc_rom_monitor_0_1_0.INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1347 -    defparam sc_rom_monitor_0_1_0.INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1348 -    defparam sc_rom_monitor_0_1_0.INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1349 -    defparam sc_rom_monitor_0_1_0.INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1350 -    defparam sc_rom_monitor_0_1_0.INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1351 -    defparam sc_rom_monitor_0_1_0.INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1352 -    defparam sc_rom_monitor_0_1_0.INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1353 -    defparam sc_rom_monitor_0_1_0.INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1354 -    defparam sc_rom_monitor_0_1_0.INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1355 -    defparam sc_rom_monitor_0_1_0.INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1356 -    defparam sc_rom_monitor_0_1_0.INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1357 -    defparam sc_rom_monitor_0_1_0.INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1358 -    defparam sc_rom_monitor_0_1_0.INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1359 -    defparam sc_rom_monitor_0_1_0.INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1360 -    defparam sc_rom_monitor_0_1_0.INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1361 -    defparam sc_rom_monitor_0_1_0.INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1362 -    defparam sc_rom_monitor_0_1_0.INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1363 -    defparam sc_rom_monitor_0_1_0.INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1364 -    defparam sc_rom_monitor_0_1_0.INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1365 -    defparam sc_rom_monitor_0_1_0.INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1366 -    defparam sc_rom_monitor_0_1_0.INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1367 -    defparam sc_rom_monitor_0_1_0.INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1368 -    defparam sc_rom_monitor_0_1_0.INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1369 -    defparam sc_rom_monitor_0_1_0.INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1370 -    defparam sc_rom_monitor_0_1_0.INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1371 -    defparam sc_rom_monitor_0_1_0.INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1372 -    defparam sc_rom_monitor_0_1_0.INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1373 -    defparam sc_rom_monitor_0_1_0.INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1374 -    defparam sc_rom_monitor_0_1_0.INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1375 -    defparam sc_rom_monitor_0_1_0.INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1376 -    defparam sc_rom_monitor_0_1_0.INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1377 -    defparam sc_rom_monitor_0_1_0.INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1378 -    defparam sc_rom_monitor_0_1_0.INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1379 -    defparam sc_rom_monitor_0_1_0.INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1380 -    defparam sc_rom_monitor_0_1_0.INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1381 -    defparam sc_rom_monitor_0_1_0.INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
  9.1382 -    defparam sc_rom_monitor_0_1_0.INITVAL_19 = 320'h000000000000000000000000000000000000000000000000000000000000000000000000000038FF ;
  9.1383 -    defparam sc_rom_monitor_0_1_0.INITVAL_18 = 320'h034D2038FF034C2038FF0349A038FF03EFF00D00038FF034CA038FF03492038FF0348A038FF03482 ;
  9.1384 -    defparam sc_rom_monitor_0_1_0.INITVAL_17 = 320'h038FF0344A038FF03442038FF0343A038FF02E7002430038FF00D6300D5A00C5803EFF0136300D03 ;
  9.1385 -    defparam sc_rom_monitor_0_1_0.INITVAL_16 = 320'h02E0803EFF02E0803EFF038FF00D5A03EFF00D63010580136300D0302E0803EFF02E0803EFF038FF ;
  9.1386 -    defparam sc_rom_monitor_0_1_0.INITVAL_15 = 320'h03EFF02E88038FF034DA0170801F100110801F100110801F100110801F100110801F100110801F10 ;
  9.1387 -    defparam sc_rom_monitor_0_1_0.INITVAL_14 = 320'h0110801F100110801F100110801F100110801F100110801F0802E0803EFF02E0803EFF038FF02E70 ;
  9.1388 -    defparam sc_rom_monitor_0_1_0.INITVAL_13 = 320'h024500110C0287302430038FF03EFF02E700110801F100110801F0802E0803EFF030E800DE700AE7 ;
  9.1389 -    defparam sc_rom_monitor_0_1_0.INITVAL_12 = 320'h00AE400AE400AE400AE300AE300AE300AE300AE200D0000D0000D000342000D0000D0000D0003418 ;
  9.1390 -    defparam sc_rom_monitor_0_1_0.INITVAL_11 = 320'h00D000170801F100110801F100110801F100110801F100110801F100110801F0802E0803EFF00E84 ;
  9.1391 -    defparam sc_rom_monitor_0_1_0.INITVAL_10 = 320'h00E7B01E0401E030347000D0001708024700347000D00017080247002E08016E7016E4016E4016E4 ;
  9.1392 -    defparam sc_rom_monitor_0_1_0.INITVAL_0F = 320'h016E3016E3016E3016E3016E200DE7030E800DE700AE703EFF010E003EFF010E003EFF010E003EFF ;
  9.1393 -    defparam sc_rom_monitor_0_1_0.INITVAL_0E = 320'h010E0016E0016E700DE7030E800DE700AE700AE000CE003EFF00CE003EFF00CE003EFF00CE003EFF ;
  9.1394 -    defparam sc_rom_monitor_0_1_0.INITVAL_0D = 320'h016E700DE7030E8034700171002470030E80110801F0803470017100247000808030E80081003478 ;
  9.1395 -    defparam sc_rom_monitor_0_1_0.INITVAL_0C = 320'h011080081002478030F800AE700AE70340F00AE70340700AE70344F00AE70343F00AE700AE700AE7 ;
  9.1396 -    defparam sc_rom_monitor_0_1_0.INITVAL_0B = 320'h00AE600AE600AE600AE600AE500AE500AE500AE500AE400AE400AE400AE400AE300AE300AE300AE3 ;
  9.1397 -    defparam sc_rom_monitor_0_1_0.INITVAL_0A = 320'h00AE200AE200AE200AE200AE100AE100AE100AE100AE000AE000AE0030F000AE700AE70340F00AE7 ;
  9.1398 -    defparam sc_rom_monitor_0_1_0.INITVAL_09 = 320'h0340700AE70344F00AE70343F00AE700AE700AE700AE600AE600AE600AE600AE500AE500AE500AE5 ;
  9.1399 -    defparam sc_rom_monitor_0_1_0.INITVAL_08 = 320'h00AE400AE400AE400AE400AE300AE300AE300AE300AE200AE200AE200AE200AE100AE100AE100AE1 ;
  9.1400 -    defparam sc_rom_monitor_0_1_0.INITVAL_07 = 320'h00AE000AE000AE0030E800DEF02EE8016E8016E800AE8016E8000080000800008000080000800808 ;
  9.1401 -    defparam sc_rom_monitor_0_1_0.INITVAL_06 = 320'h00DE8016E802400016E802448016E802438016E802410016E802408016EF016EF016EF016EE016EE ;
  9.1402 -    defparam sc_rom_monitor_0_1_0.INITVAL_05 = 320'h016EE016EE016ED016ED016ED016ED016EC016EC016EC016EC016EB016EB016EB016EB016EA016EA ;
  9.1403 -    defparam sc_rom_monitor_0_1_0.INITVAL_04 = 320'h016EA016EA016E9016E9016E9016E9016E8016E8016E802600016E800DEF038FF00D0700DE702EE8 ;
  9.1404 -    defparam sc_rom_monitor_0_1_0.INITVAL_03 = 320'h0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600 ;
  9.1405 -    defparam sc_rom_monitor_0_1_0.INITVAL_02 = 320'h0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600 ;
  9.1406 -    defparam sc_rom_monitor_0_1_0.INITVAL_01 = 320'h0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600 ;
  9.1407 -    defparam sc_rom_monitor_0_1_0.INITVAL_00 = 320'h0380003E0000D0802EE0016E703E0002EE80260000D0000D0000D0000D0000D0003E000340802600 ;
  9.1408 -    defparam sc_rom_monitor_0_1_0.CSDECODE_B =  3'b000 ;
  9.1409 -    defparam sc_rom_monitor_0_1_0.CSDECODE_A =  3'b000 ;
  9.1410 -    defparam sc_rom_monitor_0_1_0.WRITEMODE_B = "NORMAL" ;
  9.1411 -    defparam sc_rom_monitor_0_1_0.WRITEMODE_A = "NORMAL" ;
  9.1412 -    defparam sc_rom_monitor_0_1_0.GSR = "DISABLED" ;
  9.1413 -    defparam sc_rom_monitor_0_1_0.RESETMODE = "SYNC" ;
  9.1414 -    defparam sc_rom_monitor_0_1_0.REGMODE_B = "NOREG" ;
  9.1415 -    defparam sc_rom_monitor_0_1_0.REGMODE_A = "NOREG" ;
  9.1416 -    defparam sc_rom_monitor_0_1_0.DATA_WIDTH_B = 18 ;
  9.1417 -    defparam sc_rom_monitor_0_1_0.DATA_WIDTH_A = 18 ;
  9.1418 -    // synopsys translate_on
  9.1419 -    DP16KA sc_rom_monitor_0_1_0 (.DIA0(DataInA[18]), .DIA1(DataInA[19]), 
  9.1420 -        .DIA2(DataInA[20]), .DIA3(DataInA[21]), .DIA4(DataInA[22]), .DIA5(DataInA[23]), 
  9.1421 -        .DIA6(DataInA[24]), .DIA7(DataInA[25]), .DIA8(DataInA[26]), .DIA9(DataInA[27]), 
  9.1422 -        .DIA10(DataInA[28]), .DIA11(DataInA[29]), .DIA12(DataInA[30]), .DIA13(DataInA[31]), 
  9.1423 -        .DIA14(scuba_vlo), .DIA15(scuba_vlo), .DIA16(scuba_vlo), .DIA17(scuba_vlo), 
  9.1424 -        .ADA0(scuba_vhi), .ADA1(scuba_vhi), .ADA2(scuba_vlo), .ADA3(scuba_vlo), 
  9.1425 -        .ADA4(AddressA[0]), .ADA5(AddressA[1]), .ADA6(AddressA[2]), .ADA7(AddressA[3]), 
  9.1426 -        .ADA8(AddressA[4]), .ADA9(AddressA[5]), .ADA10(AddressA[6]), .ADA11(AddressA[7]), 
  9.1427 -        .ADA12(AddressA[8]), .ADA13(scuba_vlo), .CEA(ClockEnA), .CLKA(ClockA), 
  9.1428 -        .WEA(WrA), .CSA0(scuba_vlo), .CSA1(scuba_vlo), .CSA2(scuba_vlo), 
  9.1429 -        .RSTA(ResetA), .DIB0(DataInB[18]), .DIB1(DataInB[19]), .DIB2(DataInB[20]), 
  9.1430 -        .DIB3(DataInB[21]), .DIB4(DataInB[22]), .DIB5(DataInB[23]), .DIB6(DataInB[24]), 
  9.1431 -        .DIB7(DataInB[25]), .DIB8(DataInB[26]), .DIB9(DataInB[27]), .DIB10(DataInB[28]), 
  9.1432 -        .DIB11(DataInB[29]), .DIB12(DataInB[30]), .DIB13(DataInB[31]), .DIB14(scuba_vlo), 
  9.1433 -        .DIB15(scuba_vlo), .DIB16(scuba_vlo), .DIB17(scuba_vlo), .ADB0(scuba_vhi), 
  9.1434 -        .ADB1(scuba_vhi), .ADB2(scuba_vlo), .ADB3(scuba_vlo), .ADB4(AddressB[0]), 
  9.1435 -        .ADB5(AddressB[1]), .ADB6(AddressB[2]), .ADB7(AddressB[3]), .ADB8(AddressB[4]), 
  9.1436 -        .ADB9(AddressB[5]), .ADB10(AddressB[6]), .ADB11(AddressB[7]), .ADB12(AddressB[8]), 
  9.1437 -        .ADB13(scuba_vlo), .CEB(ClockEnB), .CLKB(ClockB), .WEB(WrB), .CSB0(scuba_vlo), 
  9.1438 -        .CSB1(scuba_vlo), .CSB2(scuba_vlo), .RSTB(ResetB), .DOA0(QA[18]), 
  9.1439 -        .DOA1(QA[19]), .DOA2(QA[20]), .DOA3(QA[21]), .DOA4(QA[22]), .DOA5(QA[23]), 
  9.1440 -        .DOA6(QA[24]), .DOA7(QA[25]), .DOA8(QA[26]), .DOA9(QA[27]), .DOA10(QA[28]), 
  9.1441 -        .DOA11(QA[29]), .DOA12(QA[30]), .DOA13(QA[31]), .DOA14(), .DOA15(), 
  9.1442 -        .DOA16(), .DOA17(), .DOB0(QB[18]), .DOB1(QB[19]), .DOB2(QB[20]), 
  9.1443 -        .DOB3(QB[21]), .DOB4(QB[22]), .DOB5(QB[23]), .DOB6(QB[24]), .DOB7(QB[25]), 
  9.1444 -        .DOB8(QB[26]), .DOB9(QB[27]), .DOB10(QB[28]), .DOB11(QB[29]), .DOB12(QB[30]), 
  9.1445 -        .DOB13(QB[31]), .DOB14(), .DOB15(), .DOB16(), .DOB17())
  9.1446 -             /* synthesis MEM_LPC_FILE="sc_rom_monitor.lpc" */
  9.1447 -             /* synthesis MEM_INIT_FILE="lm32_monitor.mem" */
  9.1448 -             /* synthesis INITVAL_3F="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1449 -             /* synthesis INITVAL_3E="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1450 -             /* synthesis INITVAL_3D="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1451 -             /* synthesis INITVAL_3C="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1452 -             /* synthesis INITVAL_3B="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1453 -             /* synthesis INITVAL_3A="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1454 -             /* synthesis INITVAL_39="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1455 -             /* synthesis INITVAL_38="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1456 -             /* synthesis INITVAL_37="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1457 -             /* synthesis INITVAL_36="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1458 -             /* synthesis INITVAL_35="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1459 -             /* synthesis INITVAL_34="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1460 -             /* synthesis INITVAL_33="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1461 -             /* synthesis INITVAL_32="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1462 -             /* synthesis INITVAL_31="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1463 -             /* synthesis INITVAL_30="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1464 -             /* synthesis INITVAL_2F="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1465 -             /* synthesis INITVAL_2E="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1466 -             /* synthesis INITVAL_2D="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1467 -             /* synthesis INITVAL_2C="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1468 -             /* synthesis INITVAL_2B="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1469 -             /* synthesis INITVAL_2A="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1470 -             /* synthesis INITVAL_29="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1471 -             /* synthesis INITVAL_28="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1472 -             /* synthesis INITVAL_27="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1473 -             /* synthesis INITVAL_26="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1474 -             /* synthesis INITVAL_25="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1475 -             /* synthesis INITVAL_24="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1476 -             /* synthesis INITVAL_23="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1477 -             /* synthesis INITVAL_22="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1478 -             /* synthesis INITVAL_21="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1479 -             /* synthesis INITVAL_20="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1480 -             /* synthesis INITVAL_1F="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1481 -             /* synthesis INITVAL_1E="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1482 -             /* synthesis INITVAL_1D="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1483 -             /* synthesis INITVAL_1C="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1484 -             /* synthesis INITVAL_1B="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1485 -             /* synthesis INITVAL_1A="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
  9.1486 -             /* synthesis INITVAL_19="0x000000000000000000000000000000000000000000000000000000000000000000000000000038FF" */
  9.1487 -             /* synthesis INITVAL_18="0x034D2038FF034C2038FF0349A038FF03EFF00D00038FF034CA038FF03492038FF0348A038FF03482" */
  9.1488 -             /* synthesis INITVAL_17="0x038FF0344A038FF03442038FF0343A038FF02E7002430038FF00D6300D5A00C5803EFF0136300D03" */
  9.1489 -             /* synthesis INITVAL_16="0x02E0803EFF02E0803EFF038FF00D5A03EFF00D63010580136300D0302E0803EFF02E0803EFF038FF" */
  9.1490 -             /* synthesis INITVAL_15="0x03EFF02E88038FF034DA0170801F100110801F100110801F100110801F100110801F100110801F10" */
  9.1491 -             /* synthesis INITVAL_14="0x0110801F100110801F100110801F100110801F100110801F0802E0803EFF02E0803EFF038FF02E70" */
  9.1492 -             /* synthesis INITVAL_13="0x024500110C0287302430038FF03EFF02E700110801F100110801F0802E0803EFF030E800DE700AE7" */
  9.1493 -             /* synthesis INITVAL_12="0x00AE400AE400AE400AE300AE300AE300AE300AE200D0000D0000D000342000D0000D0000D0003418" */
  9.1494 -             /* synthesis INITVAL_11="0x00D000170801F100110801F100110801F100110801F100110801F100110801F0802E0803EFF00E84" */
  9.1495 -             /* synthesis INITVAL_10="0x00E7B01E0401E030347000D0001708024700347000D00017080247002E08016E7016E4016E4016E4" */
  9.1496 -             /* synthesis INITVAL_0F="0x016E3016E3016E3016E3016E200DE7030E800DE700AE703EFF010E003EFF010E003EFF010E003EFF" */
  9.1497 -             /* synthesis INITVAL_0E="0x010E0016E0016E700DE7030E800DE700AE700AE000CE003EFF00CE003EFF00CE003EFF00CE003EFF" */
  9.1498 -             /* synthesis INITVAL_0D="0x016E700DE7030E8034700171002470030E80110801F0803470017100247000808030E80081003478" */
  9.1499 -             /* synthesis INITVAL_0C="0x011080081002478030F800AE700AE70340F00AE70340700AE70344F00AE70343F00AE700AE700AE7" */
  9.1500 -             /* synthesis INITVAL_0B="0x00AE600AE600AE600AE600AE500AE500AE500AE500AE400AE400AE400AE400AE300AE300AE300AE3" */
  9.1501 -             /* synthesis INITVAL_0A="0x00AE200AE200AE200AE200AE100AE100AE100AE100AE000AE000AE0030F000AE700AE70340F00AE7" */
  9.1502 -             /* synthesis INITVAL_09="0x0340700AE70344F00AE70343F00AE700AE700AE700AE600AE600AE600AE600AE500AE500AE500AE5" */
  9.1503 -             /* synthesis INITVAL_08="0x00AE400AE400AE400AE400AE300AE300AE300AE300AE200AE200AE200AE200AE100AE100AE100AE1" */
  9.1504 -             /* synthesis INITVAL_07="0x00AE000AE000AE0030E800DEF02EE8016E8016E800AE8016E8000080000800008000080000800808" */
  9.1505 -             /* synthesis INITVAL_06="0x00DE8016E802400016E802448016E802438016E802410016E802408016EF016EF016EF016EE016EE" */
  9.1506 -             /* synthesis INITVAL_05="0x016EE016EE016ED016ED016ED016ED016EC016EC016EC016EC016EB016EB016EB016EB016EA016EA" */
  9.1507 -             /* synthesis INITVAL_04="0x016EA016EA016E9016E9016E9016E9016E8016E8016E802600016E800DEF038FF00D0700DE702EE8" */
  9.1508 -             /* synthesis INITVAL_03="0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600" */
  9.1509 -             /* synthesis INITVAL_02="0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600" */
  9.1510 -             /* synthesis INITVAL_01="0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600" */
  9.1511 -             /* synthesis INITVAL_00="0x0380003E0000D0802EE0016E703E0002EE80260000D0000D0000D0000D0000D0003E000340802600" */
  9.1512 -             /* synthesis CSDECODE_B="0b000" */
  9.1513 -             /* synthesis CSDECODE_A="0b000" */
  9.1514 -             /* synthesis WRITEMODE_B="NORMAL" */
  9.1515 -             /* synthesis WRITEMODE_A="NORMAL" */
  9.1516 -             /* synthesis GSR="DISABLED" */
  9.1517 -             /* synthesis RESETMODE="SYNC" */
  9.1518 -             /* synthesis REGMODE_B="NOREG" */
  9.1519 -             /* synthesis REGMODE_A="NOREG" */
  9.1520 -             /* synthesis DATA_WIDTH_B="18" */
  9.1521 -             /* synthesis DATA_WIDTH_A="18" */;
  9.1522 -
  9.1523 -
  9.1524 -
  9.1525 -    // exemplar begin
  9.1526 -    // exemplar attribute sc_rom_monitor_0_0_1 MEM_LPC_FILE sc_rom_monitor.lpc
  9.1527 -    // exemplar attribute sc_rom_monitor_0_0_1 MEM_INIT_FILE lm32_monitor.mem
  9.1528 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_3F 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1529 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_3E 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1530 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_3D 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1531 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_3C 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1532 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_3B 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1533 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_3A 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1534 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_39 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1535 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_38 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1536 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_37 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1537 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_36 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1538 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_35 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1539 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_34 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1540 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_33 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1541 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_32 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1542 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_31 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1543 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_30 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1544 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_2F 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1545 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_2E 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1546 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_2D 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1547 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_2C 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1548 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_2B 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1549 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_2A 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1550 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_29 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1551 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_28 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1552 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_27 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1553 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_26 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1554 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_25 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1555 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_24 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1556 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_23 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1557 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_22 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1558 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_21 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1559 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_20 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1560 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_1F 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1561 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_1E 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1562 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_1D 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1563 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_1C 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1564 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_1B 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1565 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_1A 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1566 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_19 0x0000000000000000000000000000000000000000000000000000000000000000000000000003FF81
  9.1567 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_18 0x300003FF83300003FF85300003FF873FF4A1004F3FF8A300003FF8C300003FF8E300003FF9030000
  9.1568 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_17 0x3FF92300003FF94300003FF96300003FFC100800070003FFFB0000130001100003FF5B1001700000
  9.1569 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_16 0x068003FF70058003FF723FFFB300013FF6A00001100001FFAB00000068003FF7B058003FF7D3FFB1
  9.1570 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_15 0x3FF8D008003FFB4300000FFB61001B000361001A0002F10019000381001800038100130003310012
  9.1571 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_14 0x00033100110003310010000331000900033100080003310007010003FF89058003FF9C3FFF900800
  9.1572 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_13 0x070000FFFB30800070003FFD63FFB200800000041000A0004110006010003FF9A000000002410004
  9.1573 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_12 0x200081000C0001030014200181001C00020300240000000000000001000000000000000000010000
  9.1574 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_11 0x100010FFF310063000501004D000471006D00046100720002C100570001F10077010003FFBC00000
  9.1575 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_10 0x30000044003FC0010000100540FFFF0080010000100540FFFF008000880010004200081000C00010
  9.1576 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_0F 0x30014200181001C00020300240FFDC0000000008100043FFDD100083FFDF100093FFE11000A3FFE3
  9.1577 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_0E 0x1000B10008100040FFF8000000000C1000410008100083FFE7100093FFE91000A3FFEB1000B3FFED
  9.1578 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_0D 0x100040FFF400000200000FFFF01000000000000210054100000FFFF01000100FF00000100FF00000
  9.1579 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_0C 0x0FFFE1010001000000000007430084200002009830000300943000030090300003008C2007C10078
  9.1580 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_0B 0x300702006C1006800064300602005C1005800054300502004C1004800044300402003C1003800034
  9.1581 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_0A 0x300302002C1002800024300202001C1001800014300102000C100080000000074200842000020098
  9.1582 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_09 0x20000200942000020090200002008C3008010078300702006C1006800064300602005C1005800054
  9.1583 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_08 0x300502004C1004800044300402003C1003800034300302002C1002800024300202001C1001800014
  9.1584 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_07 0x300102000C10008000001F9A00E000000041007810000100881000110001100011000110001100FF
  9.1585 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_06 0x1F9A0100940080010090008001008C008001009C008001009800800300802007C00074300702006C
  9.1586 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_05 0x1006800064300602005C1005800054300502004C1004800044300402003C1003800034300302002C
  9.1587 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_04 0x1002800024300202001C1001800014300102000C100080000000000106603FFC530000007F40E000
  9.1588 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_03 0x0003E000BC1000400800200840000A000000000000046000C4100040080020084000120000000000
  9.1589 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_02 0x0004E000CC1000400800200840001A000000000000056000D4100040080020084000220000000000
  9.1590 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_01 0x00086000DC1000400800300840002A000000000000066000E4100040080020084000320000000000
  9.1591 -    // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_00 0x00096000EC1000400800300840003A000000000000000000000000000000000000003E0000000000
  9.1592 -    // exemplar attribute sc_rom_monitor_0_0_1 CSDECODE_B 0b000
  9.1593 -    // exemplar attribute sc_rom_monitor_0_0_1 CSDECODE_A 0b000
  9.1594 -    // exemplar attribute sc_rom_monitor_0_0_1 WRITEMODE_B NORMAL
  9.1595 -    // exemplar attribute sc_rom_monitor_0_0_1 WRITEMODE_A NORMAL
  9.1596 -    // exemplar attribute sc_rom_monitor_0_0_1 GSR DISABLED
  9.1597 -    // exemplar attribute sc_rom_monitor_0_0_1 RESETMODE SYNC
  9.1598 -    // exemplar attribute sc_rom_monitor_0_0_1 REGMODE_B NOREG
  9.1599 -    // exemplar attribute sc_rom_monitor_0_0_1 REGMODE_A NOREG
  9.1600 -    // exemplar attribute sc_rom_monitor_0_0_1 DATA_WIDTH_B 18
  9.1601 -    // exemplar attribute sc_rom_monitor_0_0_1 DATA_WIDTH_A 18
  9.1602 -    // exemplar attribute sc_rom_monitor_0_1_0 MEM_LPC_FILE sc_rom_monitor.lpc
  9.1603 -    // exemplar attribute sc_rom_monitor_0_1_0 MEM_INIT_FILE lm32_monitor.mem
  9.1604 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_3F 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1605 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_3E 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1606 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_3D 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1607 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_3C 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1608 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_3B 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1609 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_3A 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1610 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_39 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1611 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_38 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1612 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_37 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1613 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_36 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1614 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_35 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1615 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_34 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1616 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_33 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1617 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_32 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1618 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_31 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1619 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_30 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1620 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_2F 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1621 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_2E 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1622 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_2D 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1623 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_2C 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1624 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_2B 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1625 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_2A 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1626 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_29 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1627 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_28 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1628 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_27 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1629 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_26 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1630 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_25 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1631 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_24 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1632 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_23 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1633 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_22 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1634 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_21 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1635 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_20 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1636 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_1F 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1637 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_1E 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1638 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_1D 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1639 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_1C 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1640 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_1B 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1641 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_1A 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
  9.1642 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_19 0x000000000000000000000000000000000000000000000000000000000000000000000000000038FF
  9.1643 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_18 0x034D2038FF034C2038FF0349A038FF03EFF00D00038FF034CA038FF03492038FF0348A038FF03482
  9.1644 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_17 0x038FF0344A038FF03442038FF0343A038FF02E7002430038FF00D6300D5A00C5803EFF0136300D03
  9.1645 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_16 0x02E0803EFF02E0803EFF038FF00D5A03EFF00D63010580136300D0302E0803EFF02E0803EFF038FF
  9.1646 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_15 0x03EFF02E88038FF034DA0170801F100110801F100110801F100110801F100110801F100110801F10
  9.1647 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_14 0x0110801F100110801F100110801F100110801F100110801F0802E0803EFF02E0803EFF038FF02E70
  9.1648 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_13 0x024500110C0287302430038FF03EFF02E700110801F100110801F0802E0803EFF030E800DE700AE7
  9.1649 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_12 0x00AE400AE400AE400AE300AE300AE300AE300AE200D0000D0000D000342000D0000D0000D0003418
  9.1650 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_11 0x00D000170801F100110801F100110801F100110801F100110801F100110801F0802E0803EFF00E84
  9.1651 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_10 0x00E7B01E0401E030347000D0001708024700347000D00017080247002E08016E7016E4016E4016E4
  9.1652 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_0F 0x016E3016E3016E3016E3016E200DE7030E800DE700AE703EFF010E003EFF010E003EFF010E003EFF
  9.1653 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_0E 0x010E0016E0016E700DE7030E800DE700AE700AE000CE003EFF00CE003EFF00CE003EFF00CE003EFF
  9.1654 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_0D 0x016E700DE7030E8034700171002470030E80110801F0803470017100247000808030E80081003478
  9.1655 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_0C 0x011080081002478030F800AE700AE70340F00AE70340700AE70344F00AE70343F00AE700AE700AE7
  9.1656 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_0B 0x00AE600AE600AE600AE600AE500AE500AE500AE500AE400AE400AE400AE400AE300AE300AE300AE3
  9.1657 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_0A 0x00AE200AE200AE200AE200AE100AE100AE100AE100AE000AE000AE0030F000AE700AE70340F00AE7
  9.1658 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_09 0x0340700AE70344F00AE70343F00AE700AE700AE700AE600AE600AE600AE600AE500AE500AE500AE5
  9.1659 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_08 0x00AE400AE400AE400AE400AE300AE300AE300AE300AE200AE200AE200AE200AE100AE100AE100AE1
  9.1660 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_07 0x00AE000AE000AE0030E800DEF02EE8016E8016E800AE8016E8000080000800008000080000800808
  9.1661 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_06 0x00DE8016E802400016E802448016E802438016E802410016E802408016EF016EF016EF016EE016EE
  9.1662 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_05 0x016EE016EE016ED016ED016ED016ED016EC016EC016EC016EC016EB016EB016EB016EB016EA016EA
  9.1663 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_04 0x016EA016EA016E9016E9016E9016E9016E8016E8016E802600016E800DEF038FF00D0700DE702EE8
  9.1664 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_03 0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600
  9.1665 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_02 0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600
  9.1666 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_01 0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600
  9.1667 -    // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_00 0x0380003E0000D0802EE0016E703E0002EE80260000D0000D0000D0000D0000D0003E000340802600
  9.1668 -    // exemplar attribute sc_rom_monitor_0_1_0 CSDECODE_B 0b000
  9.1669 -    // exemplar attribute sc_rom_monitor_0_1_0 CSDECODE_A 0b000
  9.1670 -    // exemplar attribute sc_rom_monitor_0_1_0 WRITEMODE_B NORMAL
  9.1671 -    // exemplar attribute sc_rom_monitor_0_1_0 WRITEMODE_A NORMAL
  9.1672 -    // exemplar attribute sc_rom_monitor_0_1_0 GSR DISABLED
  9.1673 -    // exemplar attribute sc_rom_monitor_0_1_0 RESETMODE SYNC
  9.1674 -    // exemplar attribute sc_rom_monitor_0_1_0 REGMODE_B NOREG
  9.1675 -    // exemplar attribute sc_rom_monitor_0_1_0 REGMODE_A NOREG
  9.1676 -    // exemplar attribute sc_rom_monitor_0_1_0 DATA_WIDTH_B 18
  9.1677 -    // exemplar attribute sc_rom_monitor_0_1_0 DATA_WIDTH_A 18
  9.1678 -    // exemplar end
  9.1679 -
  9.1680 -
  9.1681 -      end
  9.1682 -   endgenerate
  9.1683 -   
  9.1684 -endmodule
  9.1685 -

    10.1 --- a/lm32_top.v	Sun Mar 06 19:23:51 2011 +0000
    10.2 +++ b/lm32_top.v	Sun Mar 06 19:31:09 2011 +0000
    10.3 @@ -57,16 +57,6 @@
    10.4      D_ACK_I,
    10.5      D_ERR_I,
    10.6      D_RTY_I,
    10.7 -    // Debug Slave port WishboneInterface
    10.8 -    DEBUG_ADR_I,
    10.9 -    DEBUG_DAT_I,
   10.10 -    DEBUG_SEL_I,
   10.11 -    DEBUG_WE_I,
   10.12 -    DEBUG_CTI_I,
   10.13 -    DEBUG_BTE_I,
   10.14 -    DEBUG_LOCK_I,
   10.15 -    DEBUG_CYC_I,
   10.16 -    DEBUG_STB_I,
   10.17      // ----- Outputs -------
   10.18  `ifdef CFG_USER_ENABLED    
   10.19      user_valid,
   10.20 @@ -95,12 +85,7 @@
   10.21      D_WE_O,
   10.22      D_CTI_O,
   10.23      D_LOCK_O,
   10.24 -    D_BTE_O,
   10.25 -    // Debug Slave port WishboneInterface
   10.26 -    DEBUG_ACK_O,
   10.27 -    DEBUG_ERR_O,
   10.28 -    DEBUG_RTY_O,
   10.29 -    DEBUG_DAT_O
   10.30 +    D_BTE_O
   10.31      );
   10.32  
   10.33  /////////////////////////////////////////////////////
   10.34 @@ -131,16 +116,6 @@
   10.35  input D_ERR_I;                                  // Data Wishbone interface error
   10.36  input D_RTY_I;                                  // Data Wishbone interface retry
   10.37  
   10.38 -input [`LM32_WORD_RNG] DEBUG_ADR_I;             // Debug monitor Wishbone interface address
   10.39 -input [`LM32_WORD_RNG] DEBUG_DAT_I;             // Debug monitor Wishbone interface write data
   10.40 -input [`LM32_BYTE_SELECT_RNG] DEBUG_SEL_I;      // Debug monitor Wishbone interface byte select
   10.41 -input DEBUG_WE_I;                               // Debug monitor Wishbone interface write enable
   10.42 -input [`LM32_CTYPE_RNG] DEBUG_CTI_I;            // Debug monitor Wishbone interface cycle type
   10.43 -input [`LM32_BTYPE_RNG] DEBUG_BTE_I;            // Debug monitor Wishbone interface burst type
   10.44 -input DEBUG_LOCK_I;                             // Debug monitor Wishbone interface locked transfer
   10.45 -input DEBUG_CYC_I;                              // Debug monitor Wishbone interface cycle
   10.46 -input DEBUG_STB_I;                              // Debug monitor Wishbone interface strobe
   10.47 -
   10.48  /////////////////////////////////////////////////////
   10.49  // Outputs
   10.50  /////////////////////////////////////////////////////
   10.51 @@ -195,15 +170,6 @@
   10.52  wire   D_LOCK_O;
   10.53  output [`LM32_BTYPE_RNG] D_BTE_O;               // Data Wishbone interface burst type 
   10.54  wire   [`LM32_BTYPE_RNG] D_BTE_O;
   10.55 -
   10.56 -output DEBUG_ACK_O;                             // Debug monitor Wishbone ack
   10.57 -wire   DEBUG_ACK_O;             
   10.58 -output DEBUG_ERR_O;                             // Debug monitor Wishbone error
   10.59 -wire   DEBUG_ERR_O;
   10.60 -output DEBUG_RTY_O;                             // Debug monitor Wishbone retry
   10.61 -wire   DEBUG_RTY_O;
   10.62 -output [`LM32_WORD_RNG] DEBUG_DAT_O;            // Debug monitor Wishbone read data
   10.63 -wire   [`LM32_WORD_RNG] DEBUG_DAT_O;
   10.64    
   10.65  /////////////////////////////////////////////////////
   10.66  // Internal nets and registers 
   10.67 @@ -220,6 +186,7 @@
   10.68  wire jrstn;
   10.69  `endif
   10.70  
   10.71 +// TODO: get the trace signals out
   10.72  `ifdef CFG_TRACE_ENABLED
   10.73  // PC trace signals
   10.74  wire [`LM32_PC_RNG] trace_pc;                   // PC to trace (address of next non-sequential instruction)

    11.1 --- a/lm32_trace.v	Sun Mar 06 19:23:51 2011 +0000
    11.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    11.3 @@ -1,298 +0,0 @@
    11.4 -// =============================================================================
    11.5 -//                           COPYRIGHT NOTICE
    11.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation
    11.7 -// ALL RIGHTS RESERVED
    11.8 -// This confidential and proprietary software may be used only as authorised by
    11.9 -// a licensing agreement from Lattice Semiconductor Corporation.
   11.10 -// The entire notice above must be reproduced on all authorized copies and
   11.11 -// copies may only be made to the extent permitted by a licensing agreement from
   11.12 -// Lattice Semiconductor Corporation.
   11.13 -//
   11.14 -// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
   11.15 -// 5555 NE Moore Court                            408-826-6000 (other locations)
   11.16 -// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
   11.17 -// U.S.A                                   email: techsupport@latticesemi.com
   11.18 -// =============================================================================/
   11.19 -//                         FILE DETAILS
   11.20 -// Project          : LatticeMico32
   11.21 -// File             : lm32_trace.v
   11.22 -// Title            : PC Trace and associated logic.
   11.23 -// Dependencies     : lm32_include.v, lm32_functions.v
   11.24 -// Version          : 6.1.17
   11.25 -//                  : Initial Release
   11.26 -// Version          : 7.0SP2, 3.0
   11.27 -//                  : No Change
   11.28 -// Version          : 3.1
   11.29 -//                  : No Change
   11.30 -// =============================================================================
   11.31 -
   11.32 -`include "lm32_include.v"
   11.33 -`include "system_conf.v"
   11.34 -
   11.35 -`ifdef CFG_TRACE_ENABLED
   11.36 -module lm32_trace(
   11.37 -		  // ----- Inputs -------
   11.38 -		  clk_i,
   11.39 -		  rst_i,
   11.40 -		  stb_i,
   11.41 -		  we_i,
   11.42 -		  sel_i,
   11.43 -		  dat_i,
   11.44 -		  adr_i,
   11.45 -		  
   11.46 -		  trace_pc,
   11.47 -		  trace_eid,
   11.48 -		  trace_eret,
   11.49 -		  trace_bret,
   11.50 -		  trace_pc_valid,
   11.51 -		  trace_exception,
   11.52 -		  
   11.53 -		  // -- outputs
   11.54 -		  ack_o,
   11.55 -		  dat_o);
   11.56 -
   11.57 -   input clk_i;   
   11.58 -   input rst_i;   
   11.59 -   input stb_i;
   11.60 -   input we_i;   
   11.61 -   input [3:0] sel_i;
   11.62 -   input [`LM32_WORD_RNG] dat_i;
   11.63 -   input [`LM32_WORD_RNG] adr_i;
   11.64 -   input [`LM32_PC_RNG]   trace_pc;
   11.65 -   input [`LM32_EID_RNG]  trace_eid;
   11.66 -   input 		  trace_eret;
   11.67 -   input 		  trace_bret;
   11.68 -   input 		  trace_pc_valid;
   11.69 -   input 		  trace_exception;
   11.70 -   // -- outputs
   11.71 -   output 		  ack_o;
   11.72 -   output [`LM32_WORD_RNG] dat_o;
   11.73 -   reg 			   ovrflw;
   11.74 -   
   11.75 -   function integer clogb2;
   11.76 -      input [31:0] value;
   11.77 -      begin
   11.78 -	 for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
   11.79 -           value = value >> 1;
   11.80 -      end
   11.81 -   endfunction 
   11.82 -  
   11.83 -  // instantiate the trace memory
   11.84 -  parameter mem_data_width = `LM32_PC_WIDTH;
   11.85 -  parameter mem_addr_width = clogb2(`CFG_TRACE_DEPTH-1);
   11.86 -   
   11.87 -   wire [`LM32_PC_RNG] 	     trace_dat_o;
   11.88 -   wire [mem_addr_width-1:0] trace_raddr;
   11.89 -   wire [mem_addr_width-1:0] trace_waddr;
   11.90 -   reg  		     trace_we;
   11.91 -   wire 		     trace_be, trace_last;   
   11.92 -   wire 		     rw_creg = adr_i[12]; 
   11.93 -   
   11.94 -   lm32_ram #(.data_width    (mem_data_width),
   11.95 -	      .address_width (mem_addr_width)) 
   11.96 -     trace_mem (.read_clk  	(clk_i),
   11.97 -		.write_clk 	(clk_i),
   11.98 -		.reset     	(rst_i),
   11.99 -		.read_address 	(adr_i[mem_addr_width+1:2]),
  11.100 -		.write_address  (trace_waddr),
  11.101 -		.enable_read 	(`TRUE),
  11.102 -		.enable_write 	((trace_we | trace_be) & trace_pc_valid & !trace_last),
  11.103 -		.write_enable 	(`TRUE),
  11.104 -		.write_data   	(trace_pc),
  11.105 -		.read_data    	(trace_dat_o));
  11.106 -
  11.107 -   // trigger type & stop type
  11.108 -   //  trig_type [0] = start capture when bret
  11.109 -   //  trig_type [1] = start capture when eret
  11.110 -   //  trig_type [2] = start capture when PC within a range
  11.111 -   //  trig_type [3] = start when an exception happens (other than breakpoint)
  11.112 -   //  trig_type [4] = start when a breakpoint exception happens
  11.113 -
  11.114 -   
  11.115 -   reg [4:0]	        trig_type;	   // at address  0
  11.116 -   reg [4:0] 	        stop_type;         // at address 16   
  11.117 -   reg [`LM32_WORD_RNG] trace_len;   	   // at address  4
  11.118 -   reg [`LM32_WORD_RNG]   pc_low;	   // at address  8
  11.119 -   reg [`LM32_WORD_RNG]   pc_high;	   // at address 12
  11.120 -   reg 		        trace_start,trace_stop;
  11.121 -   reg 		        ack_o;
  11.122 -   reg 			mem_valid;   
  11.123 -   reg [`LM32_WORD_RNG] reg_dat_o;
  11.124 -   reg started;
  11.125 -   reg capturing;
  11.126 -   assign 		dat_o = (rw_creg ? reg_dat_o : trace_dat_o);
  11.127 -   
  11.128 -   initial begin
  11.129 -      trig_type <= 0;
  11.130 -      stop_type <= 0;
  11.131 -      trace_len <= 0;
  11.132 -      pc_low    <= 0;
  11.133 -      pc_high   <= 0;
  11.134 -      trace_start <= 0;
  11.135 -      trace_stop  <= 0;
  11.136 -      ack_o 	<= 0;
  11.137 -      reg_dat_o <= 0;
  11.138 -      mem_valid <= 0;
  11.139 -      started   <= 0;
  11.140 -      capturing <= 0;
  11.141 -   end
  11.142 -   
  11.143 -   // the host side control
  11.144 -   always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  11.145 -     begin
  11.146 -	if (rst_i == `TRUE) begin
  11.147 -	   trig_type   <= 0;
  11.148 -	   trace_stop  <= 0;
  11.149 -	   trace_start <= 0;
  11.150 -	   pc_low      <= 0;
  11.151 -	   pc_high     <= 0;
  11.152 -	   ack_o       <= 0;
  11.153 -	end else begin
  11.154 -	   if (stb_i == `TRUE && ack_o == `FALSE) begin
  11.155 -	      if (rw_creg) begin // control register access
  11.156 -		 ack_o <= `TRUE;		    
  11.157 -		 if (we_i == `TRUE) begin
  11.158 -		    case ({adr_i[11:2],2'b0})
  11.159 -		      // write to trig type
  11.160 -		      12'd0:
  11.161 -			begin
  11.162 -			   if (sel_i[0]) begin
  11.163 -			      trig_type[4:0] <= dat_i[4:0];
  11.164 -                           end
  11.165 -                           if (sel_i[3]) begin
  11.166 -                              trace_start <= dat_i[31];
  11.167 -                              trace_stop  <= dat_i[30];
  11.168 -                           end
  11.169 -			end
  11.170 -		      12'd8:
  11.171 -			begin
  11.172 -			   if (sel_i[3]) pc_low[31:24] <= dat_i[31:24];
  11.173 -			   if (sel_i[2]) pc_low[23:16] <= dat_i[23:16];
  11.174 -			   if (sel_i[1]) pc_low[15:8]  <= dat_i[15:8];
  11.175 -			   if (sel_i[0]) pc_low[7:0]   <= dat_i[7:0];			 
  11.176 -			end
  11.177 -		      12'd12:
  11.178 -			begin
  11.179 -			   if (sel_i[3]) pc_high[31:24] <= dat_i[31:24];
  11.180 -			   if (sel_i[2]) pc_high[23:16] <= dat_i[23:16];
  11.181 -			   if (sel_i[1]) pc_high[15:8]  <= dat_i[15:8];
  11.182 -			   if (sel_i[0]) pc_high[7:0]   <= dat_i[7:0];			 
  11.183 -			end
  11.184 -		      12'd16:
  11.185 -                        begin
  11.186 -			   if (sel_i[0])begin
  11.187 -                               stop_type[4:0] <= dat_i[4:0];
  11.188 -                           end
  11.189 -                        end
  11.190 -		    endcase
  11.191 -		 end else begin // read control registers
  11.192 -		    case ({adr_i[11:2],2'b0})
  11.193 -		      // read the trig type
  11.194 -		      12'd0:
  11.195 -                        reg_dat_o <= {22'b1,capturing,mem_valid,ovrflw,trace_we,started,trig_type};
  11.196 -		      12'd4:
  11.197 -                        reg_dat_o <= trace_len;			 
  11.198 -		      12'd8:
  11.199 -			reg_dat_o <= pc_low;
  11.200 -		      12'd12:
  11.201 -			reg_dat_o <= pc_high;		      
  11.202 -		      default:
  11.203 -			reg_dat_o <= {27'b0,stop_type};
  11.204 -		    endcase
  11.205 -		 end // else: !if(we_i == `TRUE)		 
  11.206 -	      end else // read / write memory
  11.207 -		if (we_i == `FALSE) begin
  11.208 -		   ack_o <= `TRUE;
  11.209 -		end else
  11.210 -		  ack_o <= `FALSE;	      
  11.211 -	      // not allowed to write to trace memory
  11.212 -	   end else begin // if (stb_i == `TRUE)
  11.213 -	      trace_start  <= `FALSE;
  11.214 -	      trace_stop   <= `FALSE;
  11.215 -	      ack_o        <= `FALSE;	      
  11.216 -	   end // else: !if(stb_i == `TRUE)	   
  11.217 -	end // else: !if(rst_i == `TRUE)
  11.218 -     end 
  11.219 -   
  11.220 -   wire [`LM32_WORD_RNG] trace_pc_tmp = {trace_pc,2'b0};
  11.221 -   
  11.222 -   // trace state machine
  11.223 -   reg [2:0] tstate;
  11.224 -   wire      pc_in_range = {trace_pc,2'b0} >= pc_low &&
  11.225 -	                   {trace_pc,2'b0} <= pc_high;
  11.226 -   
  11.227 -   assign    trace_waddr = trace_len[mem_addr_width-1:0];
  11.228 -
  11.229 -   wire trace_begin = ((trig_type[0] & trace_bret) ||
  11.230 -		       (trig_type[1] & trace_eret) ||
  11.231 -		       (trig_type[2] & pc_in_range & trace_pc_valid) ||
  11.232 -		       (trig_type[3] & trace_exception & (trace_eid != `LM32_EID_BREAKPOINT)) ||
  11.233 -                       (trig_type[4] & trace_exception & (trace_eid == `LM32_EID_BREAKPOINT))
  11.234 -                      );
  11.235 -   
  11.236 -
  11.237 -   wire trace_end = (trace_stop  ||
  11.238 -		      (stop_type[0] & trace_bret) ||
  11.239 -		      (stop_type[1] & trace_eret) ||
  11.240 -		      (stop_type[2] & !pc_in_range & trace_pc_valid) ||
  11.241 -		      (stop_type[3] & trace_exception & (trace_eid != `LM32_EID_BREAKPOINT)) ||
  11.242 -                      (stop_type[4] & trace_exception & (trace_eid == `LM32_EID_BREAKPOINT))
  11.243 -                    );
  11.244 -
  11.245 -   assign trace_be = (trace_begin & (tstate == 3'd1));
  11.246 -   assign trace_last = (trace_stop & (tstate == 3'd2));
  11.247 -   
  11.248 -   always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  11.249 -     begin
  11.250 -	if (rst_i == `TRUE) begin
  11.251 -	   tstate    <= 0;
  11.252 -	   trace_we  <= 0;
  11.253 -	   trace_len <= 0;	   
  11.254 -	   ovrflw    <= `FALSE;
  11.255 -	   mem_valid <= 0;
  11.256 -           started   <= 0;
  11.257 -           capturing <= 0;
  11.258 -	end else begin
  11.259 -	   case (tstate)
  11.260 -	   3'd0:
  11.261 -	     // start capture	     
  11.262 -	     if (trace_start) begin
  11.263 -		tstate <= 3'd1;
  11.264 -		mem_valid <= 0;
  11.265 -                started   <= 1;
  11.266 -	     end
  11.267 -	   3'd1:
  11.268 -	     begin
  11.269 -		// wait for trigger
  11.270 -		if (trace_begin) begin
  11.271 -                   capturing <= 1;
  11.272 -		   tstate    <= 3'd2;
  11.273 -		   trace_we  <= `TRUE;
  11.274 -		   trace_len <= 0;		
  11.275 -		   ovrflw    <= `FALSE;			      
  11.276 -		end
  11.277 -	     end // case: 3'd1	     
  11.278 -
  11.279 -	   3'd2:
  11.280 -	     begin
  11.281 -		if (trace_pc_valid) begin
  11.282 -		   if (trace_len[mem_addr_width])
  11.283 -		     trace_len <= 0;
  11.284 -		   else
  11.285 -		     trace_len <= trace_len + 1;
  11.286 -		end
  11.287 -		if (!ovrflw) ovrflw <= trace_len[mem_addr_width];		
  11.288 -		// wait for stop condition
  11.289 -		if (trace_end) begin
  11.290 -		   tstate    <= 3'd0;
  11.291 -		   trace_we  <= 0;
  11.292 -		   mem_valid <= 1;
  11.293 -                   started   <= 0;
  11.294 -                   capturing <= 0;
  11.295 -		end
  11.296 -	     end // case: 3'd2
  11.297 -	   endcase
  11.298 -	end // else: !if(rst_i == `TRUE)
  11.299 -     end
  11.300 -endmodule
  11.301 -`endif

    12.1 --- a/spiprog.v	Sun Mar 06 19:23:51 2011 +0000
    12.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    12.3 @@ -1,193 +0,0 @@
    12.4 -// =============================================================================
    12.5 -//                           COPYRIGHT NOTICE
    12.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation
    12.7 -// ALL RIGHTS RESERVED
    12.8 -// This confidential and proprietary software may be used only as authorised by
    12.9 -// a licensing agreement from Lattice Semiconductor Corporation.
   12.10 -// The entire notice above must be reproduced on all authorized copies and
   12.11 -// copies may only be made to the extent permitted by a licensing agreement from
   12.12 -// Lattice Semiconductor Corporation.
   12.13 -//
   12.14 -// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
   12.15 -// 5555 NE Moore Court                            408-826-6000 (other locations)
   12.16 -// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
   12.17 -// U.S.A                                   email: techsupport@latticesemi.com
   12.18 -// =============================================================================/
   12.19 -//                         FILE DETAILS
   12.20 -// Project          : LatticeMico32
   12.21 -// File             : SPIPROG.v
   12.22 -//   This module contains the ER2 regsiters of SPI Serial FLASH programmer IP
   12.23 -//   core.  There are only three ER2 registers, one control register and two
   12.24 -//   data registers, in this IP core.  The control register is a 8-bit wide
   12.25 -//   register for selecting which data register will be accessed when the
   12.26 -//   Control/Data# bit in ER1 register is low.  Data register 0 is a readonly
   12.27 -//   ID register.  It is composed of three register fields -- an 8-bit
   12.28 -//   "implementer", a 16-bit "IP_functionality", and a 12-bit "revision".
   12.29 -//   Data register 1 is a variable length register for sending commands to or
   12.30 -//   receiving readback data from the SPI Serial FLASH device.
   12.31 -// Dependencies     : None
   12.32 -// Version          : 6.1.17
   12.33 -//        1. Reduced the the ID register (DR0) length from 36 bits to 8 bits.
   12.34 -//        2. Same as TYPEA and TYPEB modules, use falling edge clock
   12.35 -//           for all TCK Flip-Flops.
   12.36 -//        3. Added 7 delay Flip-Flops so that the DR1 readback data from 
   12.37 -//           SPI Serial FLASH is in the byte boundary.
   12.38 -// Version          : 7.0SP2, 3.0
   12.39 -//                  : No Change
   12.40 -// Version          : 3.1
   12.41 -//                  : No Change
   12.42 -// =============================================================================
   12.43 -//---------------------------------------------------------------------------
   12.44 -//
   12.45 -//Name : SPIPROG.v
   12.46 -//
   12.47 -//Description:
   12.48 -//
   12.49 -//   This module contains the ER2 regsiters of SPI Serial FLASH programmer IP
   12.50 -//   core.  There are only three ER2 registers, one control register and two
   12.51 -//   data registers, in this IP core.  The control register is a 8-bit wide
   12.52 -//   register for selecting which data register will be accessed when the
   12.53 -//   Control/Data# bit in ER1 register is low.  Data register 0 is a readonly
   12.54 -//   ID register.  It is composed of three register fields -- an 8-bit
   12.55 -//   "implementer", a 16-bit "IP_functionality", and a 12-bit "revision".
   12.56 -//   Data register 1 is a variable length register for sending commands to or
   12.57 -//   receiving readback data from the SPI Serial FLASH device.
   12.58 -//
   12.59 -//$Log: spiprog.vhd,v $
   12.60 -//Revision 1.2  2004-09-09 11:43:26-07  jhsin
   12.61 -//1. Reduced the the ID register (DR0) length from 36 bits to 8 bits.
   12.62 -//2. Same as TYPEA and TYPEB modules, use falling edge clock
   12.63 -//   for all TCK Flip-Flops.
   12.64 -//
   12.65 -//Revision 1.1  2004-08-12 13:22:05-07  jhsin
   12.66 -//Added 7 delay Flip-Flops so that the DR1 readback data from SPI Serial FLASH is in the byte boundary.
   12.67 -//
   12.68 -//Revision 1.0  2004-08-03 18:35:56-07  jhsin
   12.69 -//Initial revision
   12.70 -//
   12.71 -//
   12.72 -
   12.73 -module SPIPROG (input 	JTCK           ,
   12.74 -		input 	JTDI           ,
   12.75 -		output 	JTDO2          ,
   12.76 -		input 	JSHIFT         ,
   12.77 -		input 	JUPDATE        ,
   12.78 -		input 	JRSTN          ,
   12.79 -		input 	JCE2           ,
   12.80 -		input 	SPIPROG_ENABLE ,
   12.81 -		input 	CONTROL_DATAN  ,
   12.82 -		output 	SPI_C          ,
   12.83 -		output 	SPI_D          ,
   12.84 -		output 	SPI_SN         ,
   12.85 -		input 	SPI_Q);
   12.86 -
   12.87 -   wire 		er2Cr_enable ;
   12.88 -   wire 		er2Dr0_enable;
   12.89 -   wire 		er2Dr1_enable;
   12.90 -   
   12.91 -   wire 		tdo_er2Cr ;
   12.92 -   wire 		tdo_er2Dr0;
   12.93 -   wire 		tdo_er2Dr1;
   12.94 -   
   12.95 -   wire [7:0] 		encodedDrSelBits ;
   12.96 -   wire [8:0] 		er2CrTdiBit      ;
   12.97 -   wire [8:0] 		er2Dr0TdiBit     ;
   12.98 -   
   12.99 -   wire 		captureDrER2;
  12.100 -   reg 			spi_s       ;
  12.101 -   reg [6:0] 		spi_q_dly;
  12.102 -   
  12.103 -   wire [7:0] 		ip_functionality_id;
  12.104 -   
  12.105 -   genvar 		i;
  12.106 -   
  12.107 -   //   ------ Control Register 0 ------
  12.108 -   
  12.109 -   assign 		er2Cr_enable = JCE2 & SPIPROG_ENABLE & CONTROL_DATAN;
  12.110 -   
  12.111 -   assign 		tdo_er2Cr = er2CrTdiBit[0];
  12.112 -   
  12.113 -   //   CR_BIT0_BIT7 
  12.114 -   generate
  12.115 -      for(i=0; i<=7; i=i+1)
  12.116 -	begin:CR_BIT0_BIT7
  12.117 -	   TYPEA BIT_N (.CLK        (JTCK),
  12.118 -			.RESET_N    (JRSTN),
  12.119 -			.CLKEN      (er2Cr_enable),
  12.120 -			.TDI        (er2CrTdiBit[i + 1]),
  12.121 -			.TDO        (er2CrTdiBit[i]),
  12.122 -			.DATA_OUT   (encodedDrSelBits[i]),
  12.123 -			.DATA_IN    (encodedDrSelBits[i]),
  12.124 -			.CAPTURE_DR (captureDrER2),
  12.125 -			.UPDATE_DR  (JUPDATE));
  12.126 -	end
  12.127 -   endgenerate // CR_BIT0_BIT7
  12.128 -
  12.129 -   assign er2CrTdiBit[8] = JTDI;
  12.130 -
  12.131 -//   ------ Data Register 0 ------
  12.132 -   assign er2Dr0_enable = (JCE2 & SPIPROG_ENABLE & ~CONTROL_DATAN & (encodedDrSelBits == 8'b00000000)) ? 1'b1 : 1'b0;
  12.133 -
  12.134 -   assign tdo_er2Dr0 = er2Dr0TdiBit[0];
  12.135 -
  12.136 -   assign ip_functionality_id = 8'b00000001;  //-- SPI Serial FLASH Programmer (0x01)
  12.137 -
  12.138 -//   DR0_BIT0_BIT7 
  12.139 -   generate
  12.140 -      for(i=0; i<=7; i=i+1)
  12.141 -	begin:DR0_BIT0_BIT7
  12.142 -	   TYPEB BIT_N (.CLK        (JTCK),
  12.143 -			.RESET_N    (JRSTN),
  12.144 -			.CLKEN      (er2Dr0_enable),
  12.145 -			.TDI        (er2Dr0TdiBit[i + 1]),
  12.146 -			.TDO        (er2Dr0TdiBit[i]),
  12.147 -			.DATA_IN    (ip_functionality_id[i]),
  12.148 -			.CAPTURE_DR (captureDrER2));
  12.149 -	end
  12.150 -   endgenerate // DR0_BIT0_BIT7
  12.151 -
  12.152 -   assign er2Dr0TdiBit[8] = JTDI;
  12.153 -
  12.154 -//   ------ Data Register 1 ------
  12.155 -
  12.156 -   assign er2Dr1_enable = (JCE2 & JSHIFT & SPIPROG_ENABLE & ~CONTROL_DATAN & (encodedDrSelBits == 8'b00000001)) ?  1'b1 : 1'b0;
  12.157 -   
  12.158 -   assign SPI_C = ~ (JTCK & er2Dr1_enable & spi_s);
  12.159 -
  12.160 -   assign SPI_D = JTDI & er2Dr1_enable;
  12.161 -
  12.162 -   //   SPI_S_Proc
  12.163 -   always @(negedge JTCK or negedge JRSTN)
  12.164 -     begin
  12.165 -	if (~JRSTN)
  12.166 -          spi_s <= 1'b0;
  12.167 -	else
  12.168 -          if (JUPDATE)
  12.169 -            spi_s <= 1'b0;
  12.170 -          else
  12.171 -            spi_s <= er2Dr1_enable;
  12.172 -     end
  12.173 -   
  12.174 -   assign SPI_SN = ~spi_s;
  12.175 -   
  12.176 -   //   SPI_Q_Proc
  12.177 -   always @(negedge JTCK or negedge JRSTN)
  12.178 -     begin
  12.179 -	if (~JRSTN)
  12.180 -          spi_q_dly <= 'b0;
  12.181 -	else
  12.182 -          if (er2Dr1_enable)
  12.183 -            spi_q_dly  <= {spi_q_dly[5:0],SPI_Q};
  12.184 -     end
  12.185 -   
  12.186 -   assign tdo_er2Dr1 = spi_q_dly[6];
  12.187 -   
  12.188 -   //   ------ JTDO2 MUX ------
  12.189 -   
  12.190 -   assign JTDO2 = CONTROL_DATAN ? tdo_er2Cr :
  12.191 -	  (encodedDrSelBits == 8'b00000000) ? tdo_er2Dr0 :
  12.192 -	  (encodedDrSelBits == 8'b00000001) ? tdo_er2Dr1 : 1'b0;
  12.193 -   
  12.194 -   assign captureDrER2  = ~JSHIFT & JCE2;
  12.195 -   
  12.196 -endmodule

    13.1 --- a/typea.v	Sun Mar 06 19:23:51 2011 +0000
    13.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    13.3 @@ -1,81 +0,0 @@
    13.4 -// =============================================================================
    13.5 -//                           COPYRIGHT NOTICE
    13.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation
    13.7 -// ALL RIGHTS RESERVED
    13.8 -// This confidential and proprietary software may be used only as authorised by
    13.9 -// a licensing agreement from Lattice Semiconductor Corporation.
   13.10 -// The entire notice above must be reproduced on all authorized copies and
   13.11 -// copies may only be made to the extent permitted by a licensing agreement from
   13.12 -// Lattice Semiconductor Corporation.
   13.13 -//
   13.14 -// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
   13.15 -// 5555 NE Moore Court                            408-826-6000 (other locations)
   13.16 -// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
   13.17 -// U.S.A                                   email: techsupport@latticesemi.com
   13.18 -// =============================================================================/
   13.19 -//                         FILE DETAILS
   13.20 -// Project          : LatticeMico32
   13.21 -// File             : TYPEA.v
   13.22 -// Description:
   13.23 -//    This is one of the two types of cells that are used to create ER1/ER2
   13.24 -//    register bits.
   13.25 -// Dependencies     : None
   13.26 -// Version          : 6.1.17
   13.27 -//   The SHIFT_DR_CAPTURE_DR and ENABLE_ER1/2 signals of the
   13.28 -//   dedicate logic JTAG_PORT didn't act as what their names implied.
   13.29 -//   The SHIFT_DR_CAPTURE_DR actually acts as SHIFT_DR.
   13.30 -//   The ENABLE_ER1/2 actually acts as SHIFT_DR_CAPTURE_DR.
   13.31 -//   These had caused a lot of headaches for a long time and now they are
   13.32 -//   fixed by:
   13.33 -//   (1) Use SHIFT_DR_CAPTURE_DR and ENABLE_ER1/2 to create
   13.34 -//       CAPTURE_DR for all typeA, typeB bits in the ER1, ER2 registers.
   13.35 -//   (2) Use ENABLE_ER1 or the enESR, enCSR, enBAR (these 3 signals
   13.36 -//       have the same waveform of ENABLE_ER2) directly to be the CLKEN
   13.37 -//       of all typeA, typeB bits in the ER1, ER2 registers.
   13.38 -//   (3) Modify typea.vhd to use only UPDATE_DR signal for the clock enable
   13.39 -//       of the holding flip-flop.
   13.40 -//   These changes caused ispTracy.vhd and cge.dat changes and the new
   13.41 -//   CGE.exe version will be 1.3.5.
   13.42 -// Version          : 7.0SP2, 3.0
   13.43 -//                  : No Change
   13.44 -// Version          : 3.1
   13.45 -//                  : No Change
   13.46 -// =============================================================================
   13.47 -module TYPEA(
   13.48 -      input CLK,
   13.49 -      input RESET_N,
   13.50 -      input CLKEN,
   13.51 -      input TDI,
   13.52 -      output TDO,
   13.53 -      output reg DATA_OUT,
   13.54 -      input DATA_IN,
   13.55 -      input CAPTURE_DR,
   13.56 -      input UPDATE_DR
   13.57 -   );
   13.58 -  
   13.59 -  reg tdoInt;
   13.60 -
   13.61 -
   13.62 -  always @ (negedge CLK or negedge RESET_N)
   13.63 -  begin
   13.64 -      if (RESET_N == 1'b0)
   13.65 -         tdoInt <= 1'b0;
   13.66 -      else if (CLK == 1'b0)
   13.67 -         if (CLKEN == 1'b1)
   13.68 -            if (CAPTURE_DR == 1'b0)
   13.69 -               tdoInt <= TDI;
   13.70 -            else
   13.71 -               tdoInt <= DATA_IN;
   13.72 -  end
   13.73 -
   13.74 -   assign TDO = tdoInt;
   13.75 -
   13.76 -  always @ (negedge CLK or negedge RESET_N)
   13.77 -   begin
   13.78 -      if (RESET_N == 1'b0)
   13.79 -         DATA_OUT <= 1'b0;
   13.80 -      else if (CLK == 1'b0)
   13.81 -         if (UPDATE_DR == 1'b1)
   13.82 -            DATA_OUT <= tdoInt;
   13.83 -   end
   13.84 -endmodule

    14.1 --- a/typeb.v	Sun Mar 06 19:23:51 2011 +0000
    14.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    14.3 @@ -1,58 +0,0 @@
    14.4 -// =============================================================================
    14.5 -//                           COPYRIGHT NOTICE
    14.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation
    14.7 -// ALL RIGHTS RESERVED
    14.8 -// This confidential and proprietary software may be used only as authorised by
    14.9 -// a licensing agreement from Lattice Semiconductor Corporation.
   14.10 -// The entire notice above must be reproduced on all authorized copies and
   14.11 -// copies may only be made to the extent permitted by a licensing agreement from
   14.12 -// Lattice Semiconductor Corporation.
   14.13 -//
   14.14 -// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
   14.15 -// 5555 NE Moore Court                            408-826-6000 (other locations)
   14.16 -// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
   14.17 -// U.S.A                                   email: techsupport@latticesemi.com
   14.18 -// =============================================================================/
   14.19 -//                         FILE DETAILS
   14.20 -// Project          : LatticeMico32
   14.21 -// File             : TYPEB.v
   14.22 -// Description:
   14.23 -//    This is one of the two types of cells that are used to create ER1/ER2
   14.24 -//    register bits.
   14.25 -// Dependencies     : None
   14.26 -// Version          : 6.1.17
   14.27 -//   Modified typeb module to remove redundant DATA_OUT port.
   14.28 -// Version          : 7.0SP2, 3.0
   14.29 -//                  : No Change
   14.30 -// Version          : 3.1
   14.31 -//                  : No Change
   14.32 -// =============================================================================
   14.33 -module TYPEB
   14.34 -   (
   14.35 -      input CLK,
   14.36 -      input RESET_N,
   14.37 -      input CLKEN,
   14.38 -      input TDI,
   14.39 -      output TDO,
   14.40 -      input DATA_IN,
   14.41 -      input CAPTURE_DR
   14.42 -   );
   14.43 -
   14.44 -   reg tdoInt;
   14.45 -
   14.46 -   always @ (negedge CLK or negedge RESET_N)
   14.47 -   begin
   14.48 -      if (RESET_N== 1'b0)
   14.49 -         tdoInt <= 1'b0;
   14.50 -      else if (CLK == 1'b0)
   14.51 -         if (CLKEN==1'b1)
   14.52 -            if (CAPTURE_DR==1'b0)
   14.53 -               tdoInt <= TDI;
   14.54 -            else
   14.55 -               tdoInt <= DATA_IN;
   14.56 -   end
   14.57 -
   14.58 -   assign TDO = tdoInt;
   14.59 -
   14.60 -endmodule
   14.61 -