1.1 --- a/lm32_monitor.v Sun Mar 06 19:23:51 2011 +0000 1.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 1.3 @@ -1,167 +0,0 @@ 1.4 -// ============================================================================= 1.5 -// COPYRIGHT NOTICE 1.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation 1.7 -// ALL RIGHTS RESERVED 1.8 -// This confidential and proprietary software may be used only as authorised by 1.9 -// a licensing agreement from Lattice Semiconductor Corporation. 1.10 -// The entire notice above must be reproduced on all authorized copies and 1.11 -// copies may only be made to the extent permitted by a licensing agreement from 1.12 -// Lattice Semiconductor Corporation. 1.13 -// 1.14 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 1.15 -// 5555 NE Moore Court 408-826-6000 (other locations) 1.16 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 1.17 -// U.S.A email: techsupport@latticesemi.com 1.18 -// =============================================================================/ 1.19 -// FILE DETAILS 1.20 -// Project : LatticeMico32 1.21 -// File : lm32_monitor.v 1.22 -// Title : Debug monitor memory Wishbone interface 1.23 -// Version : 6.1.17 1.24 -// : Initial Release 1.25 -// Version : 7.0SP2, 3.0 1.26 -// : No Change 1.27 -// Version : 3.3 1.28 -// : Removed port mismatch in instantiation of module 1.29 -// : lm32_monitor_ram. 1.30 -// ============================================================================= 1.31 - 1.32 -`include "system_conf.v" 1.33 -`include "lm32_include.v" 1.34 - 1.35 -///////////////////////////////////////////////////// 1.36 -// Module interface 1.37 -///////////////////////////////////////////////////// 1.38 - 1.39 -module lm32_monitor ( 1.40 - // ----- Inputs ------- 1.41 - clk_i, 1.42 - rst_i, 1.43 - MON_ADR_I, 1.44 - MON_CYC_I, 1.45 - MON_DAT_I, 1.46 - MON_SEL_I, 1.47 - MON_STB_I, 1.48 - MON_WE_I, 1.49 - // ----- Outputs ------- 1.50 - MON_ACK_O, 1.51 - MON_RTY_O, 1.52 - MON_DAT_O, 1.53 - MON_ERR_O 1.54 - ); 1.55 - 1.56 -///////////////////////////////////////////////////// 1.57 -// Inputs 1.58 -///////////////////////////////////////////////////// 1.59 - 1.60 -input clk_i; // Wishbone clock 1.61 -input rst_i; // Wishbone reset 1.62 -input [10:2] MON_ADR_I; // Wishbone address 1.63 -input MON_STB_I; // Wishbone strobe 1.64 -input MON_CYC_I; // Wishbone cycle 1.65 -input [`LM32_WORD_RNG] MON_DAT_I; // Wishbone write data 1.66 -input [`LM32_BYTE_SELECT_RNG] MON_SEL_I; // Wishbone byte select 1.67 -input MON_WE_I; // Wishbone write enable 1.68 - 1.69 -///////////////////////////////////////////////////// 1.70 -// Outputs 1.71 -///////////////////////////////////////////////////// 1.72 - 1.73 -output MON_ACK_O; // Wishbone acknowlege 1.74 -reg MON_ACK_O; 1.75 -output [`LM32_WORD_RNG] MON_DAT_O; // Wishbone data output 1.76 -reg [`LM32_WORD_RNG] MON_DAT_O; 1.77 -output MON_RTY_O; // Wishbone retry 1.78 -wire MON_RTY_O; 1.79 -output MON_ERR_O; // Wishbone error 1.80 -wire MON_ERR_O; 1.81 - 1.82 -///////////////////////////////////////////////////// 1.83 -// Internal nets and registers 1.84 -///////////////////////////////////////////////////// 1.85 - 1.86 -reg [1:0] state; // Current state of FSM 1.87 -wire [`LM32_WORD_RNG] data, dataB; // Data read from RAM 1.88 -reg write_enable; // RAM write enable 1.89 -reg [`LM32_WORD_RNG] write_data; // RAM write data 1.90 - 1.91 -///////////////////////////////////////////////////// 1.92 -// Instantiations 1.93 -///////////////////////////////////////////////////// 1.94 - 1.95 -lm32_monitor_ram ram ( 1.96 - // ----- Inputs ------- 1.97 - .ClockA (clk_i), 1.98 - .ClockB (clk_i), 1.99 - .ResetA (rst_i), 1.100 - .ResetB (rst_i), 1.101 - .ClockEnA (`TRUE), 1.102 - .ClockEnB (`FALSE), 1.103 - .AddressA (MON_ADR_I[10:2]), 1.104 - .AddressB (9'b0), 1.105 - .DataInA (write_data), 1.106 - .DataInB (32'b0), 1.107 - .WrA (write_enable), 1.108 - .WrB (`FALSE), 1.109 - // ----- Outputs ------- 1.110 - .QA (data), 1.111 - .QB (dataB) 1.112 - ); 1.113 - 1.114 -///////////////////////////////////////////////////// 1.115 -// Combinational Logic 1.116 -///////////////////////////////////////////////////// 1.117 - 1.118 -assign MON_RTY_O = `FALSE; 1.119 -assign MON_ERR_O = `FALSE; 1.120 - 1.121 -///////////////////////////////////////////////////// 1.122 -// Sequential Logic 1.123 -///////////////////////////////////////////////////// 1.124 - 1.125 -always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.126 -begin 1.127 - if (rst_i == `TRUE) 1.128 - begin 1.129 - write_enable <= `FALSE; 1.130 - MON_ACK_O <= `FALSE; 1.131 - MON_DAT_O <= {`LM32_WORD_WIDTH{1'bx}}; 1.132 - state <= 2'b00; 1.133 - end 1.134 - else 1.135 - begin 1.136 - case (state) 1.137 - 2'b00: 1.138 - begin 1.139 - // Wait for a Wishbone access 1.140 - if ((MON_STB_I == `TRUE) && (MON_CYC_I == `TRUE)) 1.141 - state <= 2'b01; 1.142 - end 1.143 - 2'b01: 1.144 - begin 1.145 - // Output read data to Wishbone 1.146 - MON_ACK_O <= `TRUE; 1.147 - MON_DAT_O <= data; 1.148 - // Sub-word writes are performed using read-modify-write 1.149 - // as the Lattice EBRs don't support byte enables 1.150 - if (MON_WE_I == `TRUE) 1.151 - write_enable <= `TRUE; 1.152 - write_data[7:0] <= MON_SEL_I[0] ? MON_DAT_I[7:0] : data[7:0]; 1.153 - write_data[15:8] <= MON_SEL_I[1] ? MON_DAT_I[15:8] : data[15:8]; 1.154 - write_data[23:16] <= MON_SEL_I[2] ? MON_DAT_I[23:16] : data[23:16]; 1.155 - write_data[31:24] <= MON_SEL_I[3] ? MON_DAT_I[31:24] : data[31:24]; 1.156 - state <= 2'b10; 1.157 - end 1.158 - 2'b10: 1.159 - begin 1.160 - // Wishbone access occurs in this cycle 1.161 - write_enable <= `FALSE; 1.162 - MON_ACK_O <= `FALSE; 1.163 - MON_DAT_O <= {`LM32_WORD_WIDTH{1'bx}}; 1.164 - state <= 2'b00; 1.165 - end 1.166 - endcase 1.167 - end 1.168 -end 1.169 - 1.170 -endmodule