1.1 diff -r e66ed0e9e2f8 -r 54dd95f89113 lm32_monitor.v 1.2 --- a/lm32_monitor.v Sun Mar 06 19:23:51 2011 +0000 1.3 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 1.4 @@ -1,167 +0,0 @@ 1.5 -// ============================================================================= 1.6 -// COPYRIGHT NOTICE 1.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 1.8 -// ALL RIGHTS RESERVED 1.9 -// This confidential and proprietary software may be used only as authorised by 1.10 -// a licensing agreement from Lattice Semiconductor Corporation. 1.11 -// The entire notice above must be reproduced on all authorized copies and 1.12 -// copies may only be made to the extent permitted by a licensing agreement from 1.13 -// Lattice Semiconductor Corporation. 1.14 -// 1.15 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 1.16 -// 5555 NE Moore Court 408-826-6000 (other locations) 1.17 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 1.18 -// U.S.A email: techsupport@latticesemi.com 1.19 -// =============================================================================/ 1.20 -// FILE DETAILS 1.21 -// Project : LatticeMico32 1.22 -// File : lm32_monitor.v 1.23 -// Title : Debug monitor memory Wishbone interface 1.24 -// Version : 6.1.17 1.25 -// : Initial Release 1.26 -// Version : 7.0SP2, 3.0 1.27 -// : No Change 1.28 -// Version : 3.3 1.29 -// : Removed port mismatch in instantiation of module 1.30 -// : lm32_monitor_ram. 1.31 -// ============================================================================= 1.32 - 1.33 -`include "system_conf.v" 1.34 -`include "lm32_include.v" 1.35 - 1.36 -///////////////////////////////////////////////////// 1.37 -// Module interface 1.38 -///////////////////////////////////////////////////// 1.39 - 1.40 -module lm32_monitor ( 1.41 - // ----- Inputs ------- 1.42 - clk_i, 1.43 - rst_i, 1.44 - MON_ADR_I, 1.45 - MON_CYC_I, 1.46 - MON_DAT_I, 1.47 - MON_SEL_I, 1.48 - MON_STB_I, 1.49 - MON_WE_I, 1.50 - // ----- Outputs ------- 1.51 - MON_ACK_O, 1.52 - MON_RTY_O, 1.53 - MON_DAT_O, 1.54 - MON_ERR_O 1.55 - ); 1.56 - 1.57 -///////////////////////////////////////////////////// 1.58 -// Inputs 1.59 -///////////////////////////////////////////////////// 1.60 - 1.61 -input clk_i; // Wishbone clock 1.62 -input rst_i; // Wishbone reset 1.63 -input [10:2] MON_ADR_I; // Wishbone address 1.64 -input MON_STB_I; // Wishbone strobe 1.65 -input MON_CYC_I; // Wishbone cycle 1.66 -input [`LM32_WORD_RNG] MON_DAT_I; // Wishbone write data 1.67 -input [`LM32_BYTE_SELECT_RNG] MON_SEL_I; // Wishbone byte select 1.68 -input MON_WE_I; // Wishbone write enable 1.69 - 1.70 -///////////////////////////////////////////////////// 1.71 -// Outputs 1.72 -///////////////////////////////////////////////////// 1.73 - 1.74 -output MON_ACK_O; // Wishbone acknowlege 1.75 -reg MON_ACK_O; 1.76 -output [`LM32_WORD_RNG] MON_DAT_O; // Wishbone data output 1.77 -reg [`LM32_WORD_RNG] MON_DAT_O; 1.78 -output MON_RTY_O; // Wishbone retry 1.79 -wire MON_RTY_O; 1.80 -output MON_ERR_O; // Wishbone error 1.81 -wire MON_ERR_O; 1.82 - 1.83 -///////////////////////////////////////////////////// 1.84 -// Internal nets and registers 1.85 -///////////////////////////////////////////////////// 1.86 - 1.87 -reg [1:0] state; // Current state of FSM 1.88 -wire [`LM32_WORD_RNG] data, dataB; // Data read from RAM 1.89 -reg write_enable; // RAM write enable 1.90 -reg [`LM32_WORD_RNG] write_data; // RAM write data 1.91 - 1.92 -///////////////////////////////////////////////////// 1.93 -// Instantiations 1.94 -///////////////////////////////////////////////////// 1.95 - 1.96 -lm32_monitor_ram ram ( 1.97 - // ----- Inputs ------- 1.98 - .ClockA (clk_i), 1.99 - .ClockB (clk_i), 1.100 - .ResetA (rst_i), 1.101 - .ResetB (rst_i), 1.102 - .ClockEnA (`TRUE), 1.103 - .ClockEnB (`FALSE), 1.104 - .AddressA (MON_ADR_I[10:2]), 1.105 - .AddressB (9'b0), 1.106 - .DataInA (write_data), 1.107 - .DataInB (32'b0), 1.108 - .WrA (write_enable), 1.109 - .WrB (`FALSE), 1.110 - // ----- Outputs ------- 1.111 - .QA (data), 1.112 - .QB (dataB) 1.113 - ); 1.114 - 1.115 -///////////////////////////////////////////////////// 1.116 -// Combinational Logic 1.117 -///////////////////////////////////////////////////// 1.118 - 1.119 -assign MON_RTY_O = `FALSE; 1.120 -assign MON_ERR_O = `FALSE; 1.121 - 1.122 -///////////////////////////////////////////////////// 1.123 -// Sequential Logic 1.124 -///////////////////////////////////////////////////// 1.125 - 1.126 -always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.127 -begin 1.128 - if (rst_i == `TRUE) 1.129 - begin 1.130 - write_enable <= `FALSE; 1.131 - MON_ACK_O <= `FALSE; 1.132 - MON_DAT_O <= {`LM32_WORD_WIDTH{1'bx}}; 1.133 - state <= 2'b00; 1.134 - end 1.135 - else 1.136 - begin 1.137 - case (state) 1.138 - 2'b00: 1.139 - begin 1.140 - // Wait for a Wishbone access 1.141 - if ((MON_STB_I == `TRUE) && (MON_CYC_I == `TRUE)) 1.142 - state <= 2'b01; 1.143 - end 1.144 - 2'b01: 1.145 - begin 1.146 - // Output read data to Wishbone 1.147 - MON_ACK_O <= `TRUE; 1.148 - MON_DAT_O <= data; 1.149 - // Sub-word writes are performed using read-modify-write 1.150 - // as the Lattice EBRs don't support byte enables 1.151 - if (MON_WE_I == `TRUE) 1.152 - write_enable <= `TRUE; 1.153 - write_data[7:0] <= MON_SEL_I[0] ? MON_DAT_I[7:0] : data[7:0]; 1.154 - write_data[15:8] <= MON_SEL_I[1] ? MON_DAT_I[15:8] : data[15:8]; 1.155 - write_data[23:16] <= MON_SEL_I[2] ? MON_DAT_I[23:16] : data[23:16]; 1.156 - write_data[31:24] <= MON_SEL_I[3] ? MON_DAT_I[31:24] : data[31:24]; 1.157 - state <= 2'b10; 1.158 - end 1.159 - 2'b10: 1.160 - begin 1.161 - // Wishbone access occurs in this cycle 1.162 - write_enable <= `FALSE; 1.163 - MON_ACK_O <= `FALSE; 1.164 - MON_DAT_O <= {`LM32_WORD_WIDTH{1'bx}}; 1.165 - state <= 2'b00; 1.166 - end 1.167 - endcase 1.168 - end 1.169 -end 1.170 - 1.171 -endmodule