1.1 --- a/lm32_instruction_unit.v Sun Mar 06 21:14:43 2011 +0000 1.2 +++ b/lm32_instruction_unit.v Sat Aug 06 00:02:46 2011 +0100 1.3 @@ -1,18 +1,39 @@ 1.4 -// ============================================================================= 1.5 -// COPYRIGHT NOTICE 1.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation 1.7 -// ALL RIGHTS RESERVED 1.8 -// This confidential and proprietary software may be used only as authorised by 1.9 -// a licensing agreement from Lattice Semiconductor Corporation. 1.10 -// The entire notice above must be reproduced on all authorized copies and 1.11 -// copies may only be made to the extent permitted by a licensing agreement from 1.12 -// Lattice Semiconductor Corporation. 1.13 +// ================================================================== 1.14 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 1.15 +// ------------------------------------------------------------------ 1.16 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 1.17 +// ALL RIGHTS RESERVED 1.18 +// ------------------------------------------------------------------ 1.19 +// 1.20 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 1.21 +// 1.22 +// Permission: 1.23 +// 1.24 +// Lattice Semiconductor grants permission to use this code 1.25 +// pursuant to the terms of the Lattice Semiconductor Corporation 1.26 +// Open Source License Agreement. 1.27 +// 1.28 +// Disclaimer: 1.29 // 1.30 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 1.31 -// 5555 NE Moore Court 408-826-6000 (other locations) 1.32 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 1.33 -// U.S.A email: techsupport@latticesemi.com 1.34 -// =============================================================================/ 1.35 +// Lattice Semiconductor provides no warranty regarding the use or 1.36 +// functionality of this code. It is the user's responsibility to 1.37 +// verify the user’s design for consistency and functionality through 1.38 +// the use of formal verification methods. 1.39 +// 1.40 +// -------------------------------------------------------------------- 1.41 +// 1.42 +// Lattice Semiconductor Corporation 1.43 +// 5555 NE Moore Court 1.44 +// Hillsboro, OR 97214 1.45 +// U.S.A 1.46 +// 1.47 +// TEL: 1-800-Lattice (USA and Canada) 1.48 +// 503-286-8001 (other locations) 1.49 +// 1.50 +// web: http://www.latticesemi.com/ 1.51 +// email: techsupport@latticesemi.com 1.52 +// 1.53 +// -------------------------------------------------------------------- 1.54 // FILE DETAILS 1.55 // Project : LatticeMico32 1.56 // File : lm32_instruction_unit.v 1.57 @@ -42,6 +63,9 @@ 1.58 // : instruction cache) to lock up in to an infinite loop due to a 1.59 // : instruction bus error when EBA was set to instruction inline 1.60 // : memory. 1.61 +// Version : 3.8 1.62 +// : Feature: Support for dynamically switching EBA to DEBA via a 1.63 +// : GPIO. 1.64 // ============================================================================= 1.65 1.66 `include "lm32_include.v" 1.67 @@ -54,6 +78,11 @@ 1.68 // ----- Inputs ------- 1.69 clk_i, 1.70 rst_i, 1.71 +`ifdef CFG_DEBUG_ENABLED 1.72 + `ifdef CFG_ALTERNATE_EBA 1.73 + at_debug, 1.74 + `endif 1.75 +`endif 1.76 // From pipeline 1.77 stall_a, 1.78 stall_f, 1.79 @@ -161,6 +190,12 @@ 1.80 input clk_i; // Clock 1.81 input rst_i; // Reset 1.82 1.83 +`ifdef CFG_DEBUG_ENABLED 1.84 + `ifdef CFG_ALTERNATE_EBA 1.85 + input at_debug; // GPIO input that maps EBA to DEBA 1.86 + `endif 1.87 +`endif 1.88 + 1.89 input stall_a; // Stall A stage instruction 1.90 input stall_f; // Stall F stage instruction 1.91 input stall_d; // Stall D stage instruction 1.92 @@ -334,6 +369,10 @@ 1.93 reg jtag_access; // Indicates if a JTAG WB access is in progress 1.94 `endif 1.95 1.96 +`ifdef CFG_ALTERNATE_EBA 1.97 + reg alternate_eba_taken; 1.98 +`endif 1.99 + 1.100 ///////////////////////////////////////////////////// 1.101 // Functions 1.102 ///////////////////////////////////////////////////// 1.103 @@ -381,8 +420,8 @@ 1.104 .ResetB (rst_i), 1.105 .DataInA ({32{1'b0}}), 1.106 .DataInB (irom_store_data_m), 1.107 - .AddressA (pc_a[(clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)+2-1:2]), 1.108 - .AddressB (irom_address_xm[(clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)+2-1:2]), 1.109 + .AddressA (pc_a[clogb2_v1(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)+2-1:2]), 1.110 + .AddressB (irom_address_xm[clogb2_v1(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)+2-1:2]), 1.111 .ClockEnA (!stall_a), 1.112 .ClockEnB (!stall_x || !stall_m), 1.113 .WrA (`FALSE), 1.114 @@ -469,7 +508,7 @@ 1.115 pc_a = restart_address; 1.116 else 1.117 `endif 1.118 - pc_a = pc_f + 1'b1; 1.119 + pc_a = pc_f + 1'b1; 1.120 end 1.121 1.122 // Select where instruction should be fetched from 1.123 @@ -542,52 +581,63 @@ 1.124 1.125 // PC 1.126 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.127 -begin 1.128 - if (rst_i == `TRUE) 1.129 - begin 1.130 - pc_f <= (`CFG_EBA_RESET-4)/4; 1.131 - pc_d <= {`LM32_PC_WIDTH{1'b0}}; 1.132 - pc_x <= {`LM32_PC_WIDTH{1'b0}}; 1.133 - pc_m <= {`LM32_PC_WIDTH{1'b0}}; 1.134 - pc_w <= {`LM32_PC_WIDTH{1'b0}}; 1.135 - end 1.136 - else 1.137 - begin 1.138 - if (stall_f == `FALSE) 1.139 - pc_f <= pc_a; 1.140 - if (stall_d == `FALSE) 1.141 - pc_d <= pc_f; 1.142 - if (stall_x == `FALSE) 1.143 - pc_x <= pc_d; 1.144 - if (stall_m == `FALSE) 1.145 - pc_m <= pc_x; 1.146 - pc_w <= pc_m; 1.147 - end 1.148 -end 1.149 + begin 1.150 + if (rst_i == `TRUE) 1.151 + begin 1.152 +`ifdef CFG_DEBUG_ENABLED 1.153 + `ifdef CFG_ALTERNATE_EBA 1.154 + if (at_debug == `TRUE) 1.155 + pc_f <= #1 (`CFG_DEBA_RESET-4)/4; 1.156 + else 1.157 + pc_f <= #1 (`CFG_EBA_RESET-4)/4; 1.158 + `else 1.159 + pc_f <= #1 (`CFG_EBA_RESET-4)/4; 1.160 + `endif 1.161 +`else 1.162 + pc_f <= #1 (`CFG_EBA_RESET-4)/4; 1.163 +`endif 1.164 + pc_d <= #1 {`LM32_PC_WIDTH{1'b0}}; 1.165 + pc_x <= #1 {`LM32_PC_WIDTH{1'b0}}; 1.166 + pc_m <= #1 {`LM32_PC_WIDTH{1'b0}}; 1.167 + pc_w <= #1 {`LM32_PC_WIDTH{1'b0}}; 1.168 + end 1.169 + else 1.170 + begin 1.171 + if (stall_f == `FALSE) 1.172 + pc_f <= #1 pc_a; 1.173 + if (stall_d == `FALSE) 1.174 + pc_d <= #1 pc_f; 1.175 + if (stall_x == `FALSE) 1.176 + pc_x <= #1 pc_d; 1.177 + if (stall_m == `FALSE) 1.178 + pc_m <= #1 pc_x; 1.179 + pc_w <= #1 pc_m; 1.180 + end 1.181 + end 1.182 1.183 `ifdef LM32_CACHE_ENABLED 1.184 // Address to restart from after a cache miss has been handled 1.185 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.186 begin 1.187 if (rst_i == `TRUE) 1.188 - restart_address <= {`LM32_PC_WIDTH{1'b0}}; 1.189 + restart_address <= #1 {`LM32_PC_WIDTH{1'b0}}; 1.190 else 1.191 begin 1.192 `ifdef CFG_DCACHE_ENABLED 1.193 `ifdef CFG_ICACHE_ENABLED 1.194 // D-cache restart address must take priority, otherwise instructions will be lost 1.195 if (dcache_refill_request == `TRUE) 1.196 - restart_address <= pc_w; 1.197 + restart_address <= #1 pc_w; 1.198 else if ((icache_refill_request == `TRUE) && (!dcache_refilling) && (!dcache_restart_request)) 1.199 - restart_address <= icache_refill_address; 1.200 + restart_address <= #1 icache_refill_address; 1.201 `else 1.202 if (dcache_refill_request == `TRUE) 1.203 - restart_address <= pc_w; 1.204 + restart_address <= #1 pc_w; 1.205 `endif 1.206 `else 1.207 `ifdef CFG_ICACHE_ENABLED 1.208 if (icache_refill_request == `TRUE) 1.209 - restart_address <= icache_refill_address; 1.210 + restart_address <= #1 icache_refill_address; 1.211 `endif 1.212 `endif 1.213 end 1.214 @@ -599,11 +649,11 @@ 1.215 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.216 begin 1.217 if (rst_i == `TRUE) 1.218 - irom_select_f <= `FALSE; 1.219 + irom_select_f <= #1 `FALSE; 1.220 else 1.221 begin 1.222 if (stall_f == `FALSE) 1.223 - irom_select_f <= irom_select_a; 1.224 + irom_select_f <= #1 irom_select_a; 1.225 end 1.226 end 1.227 `endif 1.228 @@ -628,25 +678,25 @@ 1.229 begin 1.230 if (rst_i == `TRUE) 1.231 begin 1.232 - i_cyc_o <= `FALSE; 1.233 - i_stb_o <= `FALSE; 1.234 - i_adr_o <= {`LM32_WORD_WIDTH{1'b0}}; 1.235 - i_cti_o <= `LM32_CTYPE_END; 1.236 - i_lock_o <= `FALSE; 1.237 - icache_refill_data <= {`LM32_INSTRUCTION_WIDTH{1'b0}}; 1.238 - icache_refill_ready <= `FALSE; 1.239 + i_cyc_o <= #1 `FALSE; 1.240 + i_stb_o <= #1 `FALSE; 1.241 + i_adr_o <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.242 + i_cti_o <= #1 `LM32_CTYPE_END; 1.243 + i_lock_o <= #1 `FALSE; 1.244 + icache_refill_data <= #1 {`LM32_INSTRUCTION_WIDTH{1'b0}}; 1.245 + icache_refill_ready <= #1 `FALSE; 1.246 `ifdef CFG_BUS_ERRORS_ENABLED 1.247 - bus_error_f <= `FALSE; 1.248 + bus_error_f <= #1 `FALSE; 1.249 `endif 1.250 `ifdef CFG_HW_DEBUG_ENABLED 1.251 - i_we_o <= `FALSE; 1.252 - i_sel_o <= 4'b1111; 1.253 - jtag_access <= `FALSE; 1.254 + i_we_o <= #1 `FALSE; 1.255 + i_sel_o <= #1 4'b1111; 1.256 + jtag_access <= #1 `FALSE; 1.257 `endif 1.258 end 1.259 else 1.260 begin 1.261 - icache_refill_ready <= `FALSE; 1.262 + icache_refill_ready <= #1 `FALSE; 1.263 // Is a cycle in progress? 1.264 if (i_cyc_o == `TRUE) 1.265 begin 1.266 @@ -656,10 +706,10 @@ 1.267 `ifdef CFG_HW_DEBUG_ENABLED 1.268 if (jtag_access == `TRUE) 1.269 begin 1.270 - i_cyc_o <= `FALSE; 1.271 - i_stb_o <= `FALSE; 1.272 - i_we_o <= `FALSE; 1.273 - jtag_access <= `FALSE; 1.274 + i_cyc_o <= #1 `FALSE; 1.275 + i_stb_o <= #1 `FALSE; 1.276 + i_we_o <= #1 `FALSE; 1.277 + jtag_access <= #1 `FALSE; 1.278 end 1.279 else 1.280 `endif 1.281 @@ -667,22 +717,22 @@ 1.282 if (last_word == `TRUE) 1.283 begin 1.284 // Cache line fill complete 1.285 - i_cyc_o <= `FALSE; 1.286 - i_stb_o <= `FALSE; 1.287 - i_lock_o <= `FALSE; 1.288 + i_cyc_o <= #1 `FALSE; 1.289 + i_stb_o <= #1 `FALSE; 1.290 + i_lock_o <= #1 `FALSE; 1.291 end 1.292 // Fetch next word in cache line 1.293 - i_adr_o[addr_offset_msb:addr_offset_lsb] <= i_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1; 1.294 - i_cti_o <= next_cycle_type; 1.295 + i_adr_o[addr_offset_msb:addr_offset_lsb] <= #1 i_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1; 1.296 + i_cti_o <= #1 next_cycle_type; 1.297 // Write fetched data into instruction cache 1.298 - icache_refill_ready <= `TRUE; 1.299 - icache_refill_data <= i_dat_i; 1.300 + icache_refill_ready <= #1 `TRUE; 1.301 + icache_refill_data <= #1 i_dat_i; 1.302 end 1.303 end 1.304 `ifdef CFG_BUS_ERRORS_ENABLED 1.305 if (i_err_i == `TRUE) 1.306 begin 1.307 - bus_error_f <= `TRUE; 1.308 + bus_error_f <= #1 `TRUE; 1.309 $display ("Instruction bus error. Address: %x", i_adr_o); 1.310 end 1.311 `endif 1.312 @@ -693,15 +743,15 @@ 1.313 begin 1.314 // Read first word of cache line 1.315 `ifdef CFG_HW_DEBUG_ENABLED 1.316 - i_sel_o <= 4'b1111; 1.317 + i_sel_o <= #1 4'b1111; 1.318 `endif 1.319 - i_adr_o <= {first_address, 2'b00}; 1.320 - i_cyc_o <= `TRUE; 1.321 - i_stb_o <= `TRUE; 1.322 - i_cti_o <= first_cycle_type; 1.323 - //i_lock_o <= `TRUE; 1.324 + i_adr_o <= #1 {first_address, 2'b00}; 1.325 + i_cyc_o <= #1 `TRUE; 1.326 + i_stb_o <= #1 `TRUE; 1.327 + i_cti_o <= #1 first_cycle_type; 1.328 + //i_lock_o <= #1 `TRUE; 1.329 `ifdef CFG_BUS_ERRORS_ENABLED 1.330 - bus_error_f <= `FALSE; 1.331 + bus_error_f <= #1 `FALSE; 1.332 `endif 1.333 end 1.334 `ifdef CFG_HW_DEBUG_ENABLED 1.335 @@ -710,18 +760,18 @@ 1.336 if ((jtag_read_enable == `TRUE) || (jtag_write_enable == `TRUE)) 1.337 begin 1.338 case (jtag_address[1:0]) 1.339 - 2'b00: i_sel_o <= 4'b1000; 1.340 - 2'b01: i_sel_o <= 4'b0100; 1.341 - 2'b10: i_sel_o <= 4'b0010; 1.342 - 2'b11: i_sel_o <= 4'b0001; 1.343 + 2'b00: i_sel_o <= #1 4'b1000; 1.344 + 2'b01: i_sel_o <= #1 4'b0100; 1.345 + 2'b10: i_sel_o <= #1 4'b0010; 1.346 + 2'b11: i_sel_o <= #1 4'b0001; 1.347 endcase 1.348 - i_adr_o <= jtag_address; 1.349 - i_dat_o <= {4{jtag_write_data}}; 1.350 - i_cyc_o <= `TRUE; 1.351 - i_stb_o <= `TRUE; 1.352 - i_we_o <= jtag_write_enable; 1.353 - i_cti_o <= `LM32_CTYPE_END; 1.354 - jtag_access <= `TRUE; 1.355 + i_adr_o <= #1 jtag_address; 1.356 + i_dat_o <= #1 {4{jtag_write_data}}; 1.357 + i_cyc_o <= #1 `TRUE; 1.358 + i_stb_o <= #1 `TRUE; 1.359 + i_we_o <= #1 jtag_write_enable; 1.360 + i_cti_o <= #1 `LM32_CTYPE_END; 1.361 + jtag_access <= #1 `TRUE; 1.362 end 1.363 end 1.364 `endif 1.365 @@ -730,10 +780,10 @@ 1.366 // continually generated if exception handler is cached 1.367 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH 1.368 if (branch_taken_x == `TRUE) 1.369 - bus_error_f <= `FALSE; 1.370 + bus_error_f <= #1 `FALSE; 1.371 `endif 1.372 if (branch_taken_m == `TRUE) 1.373 - bus_error_f <= `FALSE; 1.374 + bus_error_f <= #1 `FALSE; 1.375 `endif 1.376 end 1.377 end 1.378 @@ -743,14 +793,14 @@ 1.379 begin 1.380 if (rst_i == `TRUE) 1.381 begin 1.382 - i_cyc_o <= `FALSE; 1.383 - i_stb_o <= `FALSE; 1.384 - i_adr_o <= {`LM32_WORD_WIDTH{1'b0}}; 1.385 - i_cti_o <= `LM32_CTYPE_END; 1.386 - i_lock_o <= `FALSE; 1.387 - wb_data_f <= {`LM32_INSTRUCTION_WIDTH{1'b0}}; 1.388 + i_cyc_o <= #1 `FALSE; 1.389 + i_stb_o <= #1 `FALSE; 1.390 + i_adr_o <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.391 + i_cti_o <= #1 `LM32_CTYPE_END; 1.392 + i_lock_o <= #1 `FALSE; 1.393 + wb_data_f <= #1 {`LM32_INSTRUCTION_WIDTH{1'b0}}; 1.394 `ifdef CFG_BUS_ERRORS_ENABLED 1.395 - bus_error_f <= `FALSE; 1.396 + bus_error_f <= #1 `FALSE; 1.397 `endif 1.398 end 1.399 else 1.400 @@ -762,15 +812,15 @@ 1.401 if((i_ack_i == `TRUE) || (i_err_i == `TRUE)) 1.402 begin 1.403 // Cycle complete 1.404 - i_cyc_o <= `FALSE; 1.405 - i_stb_o <= `FALSE; 1.406 + i_cyc_o <= #1 `FALSE; 1.407 + i_stb_o <= #1 `FALSE; 1.408 // Register fetched instruction 1.409 - wb_data_f <= i_dat_i; 1.410 + wb_data_f <= #1 i_dat_i; 1.411 end 1.412 `ifdef CFG_BUS_ERRORS_ENABLED 1.413 if (i_err_i == `TRUE) 1.414 begin 1.415 - bus_error_f <= `TRUE; 1.416 + bus_error_f <= #1 `TRUE; 1.417 $display ("Instruction bus error. Address: %x", i_adr_o); 1.418 end 1.419 `endif 1.420 @@ -786,13 +836,13 @@ 1.421 begin 1.422 // Fetch instruction 1.423 `ifdef CFG_HW_DEBUG_ENABLED 1.424 - i_sel_o <= 4'b1111; 1.425 + i_sel_o <= #1 4'b1111; 1.426 `endif 1.427 - i_adr_o <= {pc_a, 2'b00}; 1.428 - i_cyc_o <= `TRUE; 1.429 - i_stb_o <= `TRUE; 1.430 + i_adr_o <= #1 {pc_a, 2'b00}; 1.431 + i_cyc_o <= #1 `TRUE; 1.432 + i_stb_o <= #1 `TRUE; 1.433 `ifdef CFG_BUS_ERRORS_ENABLED 1.434 - bus_error_f <= `FALSE; 1.435 + bus_error_f <= #1 `FALSE; 1.436 `endif 1.437 end 1.438 else 1.439 @@ -804,7 +854,7 @@ 1.440 ) 1.441 begin 1.442 `ifdef CFG_BUS_ERRORS_ENABLED 1.443 - bus_error_f <= `FALSE; 1.444 + bus_error_f <= #1 `FALSE; 1.445 `endif 1.446 end 1.447 end 1.448 @@ -819,18 +869,18 @@ 1.449 begin 1.450 if (rst_i == `TRUE) 1.451 begin 1.452 - instruction_d <= {`LM32_INSTRUCTION_WIDTH{1'b0}}; 1.453 + instruction_d <= #1 {`LM32_INSTRUCTION_WIDTH{1'b0}}; 1.454 `ifdef CFG_BUS_ERRORS_ENABLED 1.455 - bus_error_d <= `FALSE; 1.456 + bus_error_d <= #1 `FALSE; 1.457 `endif 1.458 end 1.459 else 1.460 begin 1.461 if (stall_d == `FALSE) 1.462 begin 1.463 - instruction_d <= instruction_f; 1.464 + instruction_d <= #1 instruction_f; 1.465 `ifdef CFG_BUS_ERRORS_ENABLED 1.466 - bus_error_d <= bus_error_f; 1.467 + bus_error_d <= #1 bus_error_f; 1.468 `endif 1.469 end 1.470 end