1.1 diff -r 35dc7ba83714 -r 73de224304c1 lm32_instruction_unit.v 1.2 --- a/lm32_instruction_unit.v Sun Mar 06 21:14:43 2011 +0000 1.3 +++ b/lm32_instruction_unit.v Sat Aug 06 00:02:46 2011 +0100 1.4 @@ -1,18 +1,39 @@ 1.5 -// ============================================================================= 1.6 -// COPYRIGHT NOTICE 1.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 1.8 -// ALL RIGHTS RESERVED 1.9 -// This confidential and proprietary software may be used only as authorised by 1.10 -// a licensing agreement from Lattice Semiconductor Corporation. 1.11 -// The entire notice above must be reproduced on all authorized copies and 1.12 -// copies may only be made to the extent permitted by a licensing agreement from 1.13 -// Lattice Semiconductor Corporation. 1.14 +// ================================================================== 1.15 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 1.16 +// ------------------------------------------------------------------ 1.17 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 1.18 +// ALL RIGHTS RESERVED 1.19 +// ------------------------------------------------------------------ 1.20 +// 1.21 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 1.22 +// 1.23 +// Permission: 1.24 +// 1.25 +// Lattice Semiconductor grants permission to use this code 1.26 +// pursuant to the terms of the Lattice Semiconductor Corporation 1.27 +// Open Source License Agreement. 1.28 +// 1.29 +// Disclaimer: 1.30 // 1.31 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 1.32 -// 5555 NE Moore Court 408-826-6000 (other locations) 1.33 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 1.34 -// U.S.A email: techsupport@latticesemi.com 1.35 -// =============================================================================/ 1.36 +// Lattice Semiconductor provides no warranty regarding the use or 1.37 +// functionality of this code. It is the user's responsibility to 1.38 +// verify the user’s design for consistency and functionality through 1.39 +// the use of formal verification methods. 1.40 +// 1.41 +// -------------------------------------------------------------------- 1.42 +// 1.43 +// Lattice Semiconductor Corporation 1.44 +// 5555 NE Moore Court 1.45 +// Hillsboro, OR 97214 1.46 +// U.S.A 1.47 +// 1.48 +// TEL: 1-800-Lattice (USA and Canada) 1.49 +// 503-286-8001 (other locations) 1.50 +// 1.51 +// web: http://www.latticesemi.com/ 1.52 +// email: techsupport@latticesemi.com 1.53 +// 1.54 +// -------------------------------------------------------------------- 1.55 // FILE DETAILS 1.56 // Project : LatticeMico32 1.57 // File : lm32_instruction_unit.v 1.58 @@ -42,6 +63,9 @@ 1.59 // : instruction cache) to lock up in to an infinite loop due to a 1.60 // : instruction bus error when EBA was set to instruction inline 1.61 // : memory. 1.62 +// Version : 3.8 1.63 +// : Feature: Support for dynamically switching EBA to DEBA via a 1.64 +// : GPIO. 1.65 // ============================================================================= 1.66 1.67 `include "lm32_include.v" 1.68 @@ -54,6 +78,11 @@ 1.69 // ----- Inputs ------- 1.70 clk_i, 1.71 rst_i, 1.72 +`ifdef CFG_DEBUG_ENABLED 1.73 + `ifdef CFG_ALTERNATE_EBA 1.74 + at_debug, 1.75 + `endif 1.76 +`endif 1.77 // From pipeline 1.78 stall_a, 1.79 stall_f, 1.80 @@ -161,6 +190,12 @@ 1.81 input clk_i; // Clock 1.82 input rst_i; // Reset 1.83 1.84 +`ifdef CFG_DEBUG_ENABLED 1.85 + `ifdef CFG_ALTERNATE_EBA 1.86 + input at_debug; // GPIO input that maps EBA to DEBA 1.87 + `endif 1.88 +`endif 1.89 + 1.90 input stall_a; // Stall A stage instruction 1.91 input stall_f; // Stall F stage instruction 1.92 input stall_d; // Stall D stage instruction 1.93 @@ -334,6 +369,10 @@ 1.94 reg jtag_access; // Indicates if a JTAG WB access is in progress 1.95 `endif 1.96 1.97 +`ifdef CFG_ALTERNATE_EBA 1.98 + reg alternate_eba_taken; 1.99 +`endif 1.100 + 1.101 ///////////////////////////////////////////////////// 1.102 // Functions 1.103 ///////////////////////////////////////////////////// 1.104 @@ -381,8 +420,8 @@ 1.105 .ResetB (rst_i), 1.106 .DataInA ({32{1'b0}}), 1.107 .DataInB (irom_store_data_m), 1.108 - .AddressA (pc_a[(clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)+2-1:2]), 1.109 - .AddressB (irom_address_xm[(clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)+2-1:2]), 1.110 + .AddressA (pc_a[clogb2_v1(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)+2-1:2]), 1.111 + .AddressB (irom_address_xm[clogb2_v1(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)+2-1:2]), 1.112 .ClockEnA (!stall_a), 1.113 .ClockEnB (!stall_x || !stall_m), 1.114 .WrA (`FALSE), 1.115 @@ -469,7 +508,7 @@ 1.116 pc_a = restart_address; 1.117 else 1.118 `endif 1.119 - pc_a = pc_f + 1'b1; 1.120 + pc_a = pc_f + 1'b1; 1.121 end 1.122 1.123 // Select where instruction should be fetched from 1.124 @@ -542,52 +581,63 @@ 1.125 1.126 // PC 1.127 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.128 -begin 1.129 - if (rst_i == `TRUE) 1.130 - begin 1.131 - pc_f <= (`CFG_EBA_RESET-4)/4; 1.132 - pc_d <= {`LM32_PC_WIDTH{1'b0}}; 1.133 - pc_x <= {`LM32_PC_WIDTH{1'b0}}; 1.134 - pc_m <= {`LM32_PC_WIDTH{1'b0}}; 1.135 - pc_w <= {`LM32_PC_WIDTH{1'b0}}; 1.136 - end 1.137 - else 1.138 - begin 1.139 - if (stall_f == `FALSE) 1.140 - pc_f <= pc_a; 1.141 - if (stall_d == `FALSE) 1.142 - pc_d <= pc_f; 1.143 - if (stall_x == `FALSE) 1.144 - pc_x <= pc_d; 1.145 - if (stall_m == `FALSE) 1.146 - pc_m <= pc_x; 1.147 - pc_w <= pc_m; 1.148 - end 1.149 -end 1.150 + begin 1.151 + if (rst_i == `TRUE) 1.152 + begin 1.153 +`ifdef CFG_DEBUG_ENABLED 1.154 + `ifdef CFG_ALTERNATE_EBA 1.155 + if (at_debug == `TRUE) 1.156 + pc_f <= #1 (`CFG_DEBA_RESET-4)/4; 1.157 + else 1.158 + pc_f <= #1 (`CFG_EBA_RESET-4)/4; 1.159 + `else 1.160 + pc_f <= #1 (`CFG_EBA_RESET-4)/4; 1.161 + `endif 1.162 +`else 1.163 + pc_f <= #1 (`CFG_EBA_RESET-4)/4; 1.164 +`endif 1.165 + pc_d <= #1 {`LM32_PC_WIDTH{1'b0}}; 1.166 + pc_x <= #1 {`LM32_PC_WIDTH{1'b0}}; 1.167 + pc_m <= #1 {`LM32_PC_WIDTH{1'b0}}; 1.168 + pc_w <= #1 {`LM32_PC_WIDTH{1'b0}}; 1.169 + end 1.170 + else 1.171 + begin 1.172 + if (stall_f == `FALSE) 1.173 + pc_f <= #1 pc_a; 1.174 + if (stall_d == `FALSE) 1.175 + pc_d <= #1 pc_f; 1.176 + if (stall_x == `FALSE) 1.177 + pc_x <= #1 pc_d; 1.178 + if (stall_m == `FALSE) 1.179 + pc_m <= #1 pc_x; 1.180 + pc_w <= #1 pc_m; 1.181 + end 1.182 + end 1.183 1.184 `ifdef LM32_CACHE_ENABLED 1.185 // Address to restart from after a cache miss has been handled 1.186 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.187 begin 1.188 if (rst_i == `TRUE) 1.189 - restart_address <= {`LM32_PC_WIDTH{1'b0}}; 1.190 + restart_address <= #1 {`LM32_PC_WIDTH{1'b0}}; 1.191 else 1.192 begin 1.193 `ifdef CFG_DCACHE_ENABLED 1.194 `ifdef CFG_ICACHE_ENABLED 1.195 // D-cache restart address must take priority, otherwise instructions will be lost 1.196 if (dcache_refill_request == `TRUE) 1.197 - restart_address <= pc_w; 1.198 + restart_address <= #1 pc_w; 1.199 else if ((icache_refill_request == `TRUE) && (!dcache_refilling) && (!dcache_restart_request)) 1.200 - restart_address <= icache_refill_address; 1.201 + restart_address <= #1 icache_refill_address; 1.202 `else 1.203 if (dcache_refill_request == `TRUE) 1.204 - restart_address <= pc_w; 1.205 + restart_address <= #1 pc_w; 1.206 `endif 1.207 `else 1.208 `ifdef CFG_ICACHE_ENABLED 1.209 if (icache_refill_request == `TRUE) 1.210 - restart_address <= icache_refill_address; 1.211 + restart_address <= #1 icache_refill_address; 1.212 `endif 1.213 `endif 1.214 end 1.215 @@ -599,11 +649,11 @@ 1.216 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.217 begin 1.218 if (rst_i == `TRUE) 1.219 - irom_select_f <= `FALSE; 1.220 + irom_select_f <= #1 `FALSE; 1.221 else 1.222 begin 1.223 if (stall_f == `FALSE) 1.224 - irom_select_f <= irom_select_a; 1.225 + irom_select_f <= #1 irom_select_a; 1.226 end 1.227 end 1.228 `endif 1.229 @@ -628,25 +678,25 @@ 1.230 begin 1.231 if (rst_i == `TRUE) 1.232 begin 1.233 - i_cyc_o <= `FALSE; 1.234 - i_stb_o <= `FALSE; 1.235 - i_adr_o <= {`LM32_WORD_WIDTH{1'b0}}; 1.236 - i_cti_o <= `LM32_CTYPE_END; 1.237 - i_lock_o <= `FALSE; 1.238 - icache_refill_data <= {`LM32_INSTRUCTION_WIDTH{1'b0}}; 1.239 - icache_refill_ready <= `FALSE; 1.240 + i_cyc_o <= #1 `FALSE; 1.241 + i_stb_o <= #1 `FALSE; 1.242 + i_adr_o <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.243 + i_cti_o <= #1 `LM32_CTYPE_END; 1.244 + i_lock_o <= #1 `FALSE; 1.245 + icache_refill_data <= #1 {`LM32_INSTRUCTION_WIDTH{1'b0}}; 1.246 + icache_refill_ready <= #1 `FALSE; 1.247 `ifdef CFG_BUS_ERRORS_ENABLED 1.248 - bus_error_f <= `FALSE; 1.249 + bus_error_f <= #1 `FALSE; 1.250 `endif 1.251 `ifdef CFG_HW_DEBUG_ENABLED 1.252 - i_we_o <= `FALSE; 1.253 - i_sel_o <= 4'b1111; 1.254 - jtag_access <= `FALSE; 1.255 + i_we_o <= #1 `FALSE; 1.256 + i_sel_o <= #1 4'b1111; 1.257 + jtag_access <= #1 `FALSE; 1.258 `endif 1.259 end 1.260 else 1.261 begin 1.262 - icache_refill_ready <= `FALSE; 1.263 + icache_refill_ready <= #1 `FALSE; 1.264 // Is a cycle in progress? 1.265 if (i_cyc_o == `TRUE) 1.266 begin 1.267 @@ -656,10 +706,10 @@ 1.268 `ifdef CFG_HW_DEBUG_ENABLED 1.269 if (jtag_access == `TRUE) 1.270 begin 1.271 - i_cyc_o <= `FALSE; 1.272 - i_stb_o <= `FALSE; 1.273 - i_we_o <= `FALSE; 1.274 - jtag_access <= `FALSE; 1.275 + i_cyc_o <= #1 `FALSE; 1.276 + i_stb_o <= #1 `FALSE; 1.277 + i_we_o <= #1 `FALSE; 1.278 + jtag_access <= #1 `FALSE; 1.279 end 1.280 else 1.281 `endif 1.282 @@ -667,22 +717,22 @@ 1.283 if (last_word == `TRUE) 1.284 begin 1.285 // Cache line fill complete 1.286 - i_cyc_o <= `FALSE; 1.287 - i_stb_o <= `FALSE; 1.288 - i_lock_o <= `FALSE; 1.289 + i_cyc_o <= #1 `FALSE; 1.290 + i_stb_o <= #1 `FALSE; 1.291 + i_lock_o <= #1 `FALSE; 1.292 end 1.293 // Fetch next word in cache line 1.294 - i_adr_o[addr_offset_msb:addr_offset_lsb] <= i_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1; 1.295 - i_cti_o <= next_cycle_type; 1.296 + i_adr_o[addr_offset_msb:addr_offset_lsb] <= #1 i_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1; 1.297 + i_cti_o <= #1 next_cycle_type; 1.298 // Write fetched data into instruction cache 1.299 - icache_refill_ready <= `TRUE; 1.300 - icache_refill_data <= i_dat_i; 1.301 + icache_refill_ready <= #1 `TRUE; 1.302 + icache_refill_data <= #1 i_dat_i; 1.303 end 1.304 end 1.305 `ifdef CFG_BUS_ERRORS_ENABLED 1.306 if (i_err_i == `TRUE) 1.307 begin 1.308 - bus_error_f <= `TRUE; 1.309 + bus_error_f <= #1 `TRUE; 1.310 $display ("Instruction bus error. Address: %x", i_adr_o); 1.311 end 1.312 `endif 1.313 @@ -693,15 +743,15 @@ 1.314 begin 1.315 // Read first word of cache line 1.316 `ifdef CFG_HW_DEBUG_ENABLED 1.317 - i_sel_o <= 4'b1111; 1.318 + i_sel_o <= #1 4'b1111; 1.319 `endif 1.320 - i_adr_o <= {first_address, 2'b00}; 1.321 - i_cyc_o <= `TRUE; 1.322 - i_stb_o <= `TRUE; 1.323 - i_cti_o <= first_cycle_type; 1.324 - //i_lock_o <= `TRUE; 1.325 + i_adr_o <= #1 {first_address, 2'b00}; 1.326 + i_cyc_o <= #1 `TRUE; 1.327 + i_stb_o <= #1 `TRUE; 1.328 + i_cti_o <= #1 first_cycle_type; 1.329 + //i_lock_o <= #1 `TRUE; 1.330 `ifdef CFG_BUS_ERRORS_ENABLED 1.331 - bus_error_f <= `FALSE; 1.332 + bus_error_f <= #1 `FALSE; 1.333 `endif 1.334 end 1.335 `ifdef CFG_HW_DEBUG_ENABLED 1.336 @@ -710,18 +760,18 @@ 1.337 if ((jtag_read_enable == `TRUE) || (jtag_write_enable == `TRUE)) 1.338 begin 1.339 case (jtag_address[1:0]) 1.340 - 2'b00: i_sel_o <= 4'b1000; 1.341 - 2'b01: i_sel_o <= 4'b0100; 1.342 - 2'b10: i_sel_o <= 4'b0010; 1.343 - 2'b11: i_sel_o <= 4'b0001; 1.344 + 2'b00: i_sel_o <= #1 4'b1000; 1.345 + 2'b01: i_sel_o <= #1 4'b0100; 1.346 + 2'b10: i_sel_o <= #1 4'b0010; 1.347 + 2'b11: i_sel_o <= #1 4'b0001; 1.348 endcase 1.349 - i_adr_o <= jtag_address; 1.350 - i_dat_o <= {4{jtag_write_data}}; 1.351 - i_cyc_o <= `TRUE; 1.352 - i_stb_o <= `TRUE; 1.353 - i_we_o <= jtag_write_enable; 1.354 - i_cti_o <= `LM32_CTYPE_END; 1.355 - jtag_access <= `TRUE; 1.356 + i_adr_o <= #1 jtag_address; 1.357 + i_dat_o <= #1 {4{jtag_write_data}}; 1.358 + i_cyc_o <= #1 `TRUE; 1.359 + i_stb_o <= #1 `TRUE; 1.360 + i_we_o <= #1 jtag_write_enable; 1.361 + i_cti_o <= #1 `LM32_CTYPE_END; 1.362 + jtag_access <= #1 `TRUE; 1.363 end 1.364 end 1.365 `endif 1.366 @@ -730,10 +780,10 @@ 1.367 // continually generated if exception handler is cached 1.368 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH 1.369 if (branch_taken_x == `TRUE) 1.370 - bus_error_f <= `FALSE; 1.371 + bus_error_f <= #1 `FALSE; 1.372 `endif 1.373 if (branch_taken_m == `TRUE) 1.374 - bus_error_f <= `FALSE; 1.375 + bus_error_f <= #1 `FALSE; 1.376 `endif 1.377 end 1.378 end 1.379 @@ -743,14 +793,14 @@ 1.380 begin 1.381 if (rst_i == `TRUE) 1.382 begin 1.383 - i_cyc_o <= `FALSE; 1.384 - i_stb_o <= `FALSE; 1.385 - i_adr_o <= {`LM32_WORD_WIDTH{1'b0}}; 1.386 - i_cti_o <= `LM32_CTYPE_END; 1.387 - i_lock_o <= `FALSE; 1.388 - wb_data_f <= {`LM32_INSTRUCTION_WIDTH{1'b0}}; 1.389 + i_cyc_o <= #1 `FALSE; 1.390 + i_stb_o <= #1 `FALSE; 1.391 + i_adr_o <= #1 {`LM32_WORD_WIDTH{1'b0}}; 1.392 + i_cti_o <= #1 `LM32_CTYPE_END; 1.393 + i_lock_o <= #1 `FALSE; 1.394 + wb_data_f <= #1 {`LM32_INSTRUCTION_WIDTH{1'b0}}; 1.395 `ifdef CFG_BUS_ERRORS_ENABLED 1.396 - bus_error_f <= `FALSE; 1.397 + bus_error_f <= #1 `FALSE; 1.398 `endif 1.399 end 1.400 else 1.401 @@ -762,15 +812,15 @@ 1.402 if((i_ack_i == `TRUE) || (i_err_i == `TRUE)) 1.403 begin 1.404 // Cycle complete 1.405 - i_cyc_o <= `FALSE; 1.406 - i_stb_o <= `FALSE; 1.407 + i_cyc_o <= #1 `FALSE; 1.408 + i_stb_o <= #1 `FALSE; 1.409 // Register fetched instruction 1.410 - wb_data_f <= i_dat_i; 1.411 + wb_data_f <= #1 i_dat_i; 1.412 end 1.413 `ifdef CFG_BUS_ERRORS_ENABLED 1.414 if (i_err_i == `TRUE) 1.415 begin 1.416 - bus_error_f <= `TRUE; 1.417 + bus_error_f <= #1 `TRUE; 1.418 $display ("Instruction bus error. Address: %x", i_adr_o); 1.419 end 1.420 `endif 1.421 @@ -786,13 +836,13 @@ 1.422 begin 1.423 // Fetch instruction 1.424 `ifdef CFG_HW_DEBUG_ENABLED 1.425 - i_sel_o <= 4'b1111; 1.426 + i_sel_o <= #1 4'b1111; 1.427 `endif 1.428 - i_adr_o <= {pc_a, 2'b00}; 1.429 - i_cyc_o <= `TRUE; 1.430 - i_stb_o <= `TRUE; 1.431 + i_adr_o <= #1 {pc_a, 2'b00}; 1.432 + i_cyc_o <= #1 `TRUE; 1.433 + i_stb_o <= #1 `TRUE; 1.434 `ifdef CFG_BUS_ERRORS_ENABLED 1.435 - bus_error_f <= `FALSE; 1.436 + bus_error_f <= #1 `FALSE; 1.437 `endif 1.438 end 1.439 else 1.440 @@ -804,7 +854,7 @@ 1.441 ) 1.442 begin 1.443 `ifdef CFG_BUS_ERRORS_ENABLED 1.444 - bus_error_f <= `FALSE; 1.445 + bus_error_f <= #1 `FALSE; 1.446 `endif 1.447 end 1.448 end 1.449 @@ -819,18 +869,18 @@ 1.450 begin 1.451 if (rst_i == `TRUE) 1.452 begin 1.453 - instruction_d <= {`LM32_INSTRUCTION_WIDTH{1'b0}}; 1.454 + instruction_d <= #1 {`LM32_INSTRUCTION_WIDTH{1'b0}}; 1.455 `ifdef CFG_BUS_ERRORS_ENABLED 1.456 - bus_error_d <= `FALSE; 1.457 + bus_error_d <= #1 `FALSE; 1.458 `endif 1.459 end 1.460 else 1.461 begin 1.462 if (stall_d == `FALSE) 1.463 begin 1.464 - instruction_d <= instruction_f; 1.465 + instruction_d <= #1 instruction_f; 1.466 `ifdef CFG_BUS_ERRORS_ENABLED 1.467 - bus_error_d <= bus_error_f; 1.468 + bus_error_d <= #1 bus_error_f; 1.469 `endif 1.470 end 1.471 end