1.1 --- a/lm32_top.v Sun Mar 06 21:17:31 2011 +0000 1.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 1.3 @@ -1,355 +0,0 @@ 1.4 -// ============================================================================= 1.5 -// COPYRIGHT NOTICE 1.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation 1.7 -// ALL RIGHTS RESERVED 1.8 -// This confidential and proprietary software may be used only as authorised by 1.9 -// a licensing agreement from Lattice Semiconductor Corporation. 1.10 -// The entire notice above must be reproduced on all authorized copies and 1.11 -// copies may only be made to the extent permitted by a licensing agreement from 1.12 -// Lattice Semiconductor Corporation. 1.13 -// 1.14 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 1.15 -// 5555 NE Moore Court 408-826-6000 (other locations) 1.16 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 1.17 -// U.S.A email: techsupport@latticesemi.com 1.18 -// =============================================================================/ 1.19 -// FILE DETAILS 1.20 -// Project : LatticeMico32 1.21 -// File : lm32_top.v 1.22 -// Title : Top-level of CPU. 1.23 -// Dependencies : lm32_include.v 1.24 -// Version : 6.1.17 1.25 -// : removed SPI - 04/12/07 1.26 -// Version : 7.0SP2, 3.0 1.27 -// : No Change 1.28 -// Version : 3.1 1.29 -// : No Change 1.30 -// ============================================================================= 1.31 - 1.32 -`include "lm32_include.v" 1.33 - 1.34 -///////////////////////////////////////////////////// 1.35 -// Module interface 1.36 -///////////////////////////////////////////////////// 1.37 - 1.38 -module lm32_top ( 1.39 - // ----- Inputs ------- 1.40 - clk_i, 1.41 - rst_i, 1.42 - // From external devices 1.43 -`ifdef CFG_INTERRUPTS_ENABLED 1.44 - interrupt, 1.45 -`endif 1.46 - // From user logic 1.47 -`ifdef CFG_USER_ENABLED 1.48 - user_result, 1.49 - user_complete, 1.50 -`endif 1.51 -`ifdef CFG_IWB_ENABLED 1.52 - // Instruction Wishbone master 1.53 - I_DAT_I, 1.54 - I_ACK_I, 1.55 - I_ERR_I, 1.56 - I_RTY_I, 1.57 -`endif 1.58 - // Data Wishbone master 1.59 - D_DAT_I, 1.60 - D_ACK_I, 1.61 - D_ERR_I, 1.62 - D_RTY_I, 1.63 - // ----- Outputs ------- 1.64 -`ifdef CFG_USER_ENABLED 1.65 - user_valid, 1.66 - user_opcode, 1.67 - user_operand_0, 1.68 - user_operand_1, 1.69 -`endif 1.70 -`ifdef CFG_IWB_ENABLED 1.71 - // Instruction Wishbone master 1.72 - I_DAT_O, 1.73 - I_ADR_O, 1.74 - I_CYC_O, 1.75 - I_SEL_O, 1.76 - I_STB_O, 1.77 - I_WE_O, 1.78 - I_CTI_O, 1.79 - I_LOCK_O, 1.80 - I_BTE_O, 1.81 -`endif 1.82 - // Data Wishbone master 1.83 - D_DAT_O, 1.84 - D_ADR_O, 1.85 - D_CYC_O, 1.86 - D_SEL_O, 1.87 - D_STB_O, 1.88 - D_WE_O, 1.89 - D_CTI_O, 1.90 - D_LOCK_O, 1.91 - D_BTE_O 1.92 - ); 1.93 - 1.94 -///////////////////////////////////////////////////// 1.95 -// Inputs 1.96 -///////////////////////////////////////////////////// 1.97 - 1.98 -input clk_i; // Clock 1.99 -input rst_i; // Reset 1.100 - 1.101 -`ifdef CFG_INTERRUPTS_ENABLED 1.102 -input [`LM32_INTERRUPT_RNG] interrupt; // Interrupt pins 1.103 -`endif 1.104 - 1.105 -`ifdef CFG_USER_ENABLED 1.106 -input [`LM32_WORD_RNG] user_result; // User-defined instruction result 1.107 -input user_complete; // Indicates the user-defined instruction result is valid 1.108 -`endif 1.109 - 1.110 -`ifdef CFG_IWB_ENABLED 1.111 -input [`LM32_WORD_RNG] I_DAT_I; // Instruction Wishbone interface read data 1.112 -input I_ACK_I; // Instruction Wishbone interface acknowledgement 1.113 -input I_ERR_I; // Instruction Wishbone interface error 1.114 -input I_RTY_I; // Instruction Wishbone interface retry 1.115 -`endif 1.116 - 1.117 -input [`LM32_WORD_RNG] D_DAT_I; // Data Wishbone interface read data 1.118 -input D_ACK_I; // Data Wishbone interface acknowledgement 1.119 -input D_ERR_I; // Data Wishbone interface error 1.120 -input D_RTY_I; // Data Wishbone interface retry 1.121 - 1.122 -///////////////////////////////////////////////////// 1.123 -// Outputs 1.124 -///////////////////////////////////////////////////// 1.125 - 1.126 -`ifdef CFG_USER_ENABLED 1.127 -output user_valid; // Indicates that user_opcode and user_operand_* are valid 1.128 -wire user_valid; 1.129 -output [`LM32_USER_OPCODE_RNG] user_opcode; // User-defined instruction opcode 1.130 -reg [`LM32_USER_OPCODE_RNG] user_opcode; 1.131 -output [`LM32_WORD_RNG] user_operand_0; // First operand for user-defined instruction 1.132 -wire [`LM32_WORD_RNG] user_operand_0; 1.133 -output [`LM32_WORD_RNG] user_operand_1; // Second operand for user-defined instruction 1.134 -wire [`LM32_WORD_RNG] user_operand_1; 1.135 -`endif 1.136 - 1.137 -`ifdef CFG_IWB_ENABLED 1.138 -output [`LM32_WORD_RNG] I_DAT_O; // Instruction Wishbone interface write data 1.139 -wire [`LM32_WORD_RNG] I_DAT_O; 1.140 -output [`LM32_WORD_RNG] I_ADR_O; // Instruction Wishbone interface address 1.141 -wire [`LM32_WORD_RNG] I_ADR_O; 1.142 -output I_CYC_O; // Instruction Wishbone interface cycle 1.143 -wire I_CYC_O; 1.144 -output [`LM32_BYTE_SELECT_RNG] I_SEL_O; // Instruction Wishbone interface byte select 1.145 -wire [`LM32_BYTE_SELECT_RNG] I_SEL_O; 1.146 -output I_STB_O; // Instruction Wishbone interface strobe 1.147 -wire I_STB_O; 1.148 -output I_WE_O; // Instruction Wishbone interface write enable 1.149 -wire I_WE_O; 1.150 -output [`LM32_CTYPE_RNG] I_CTI_O; // Instruction Wishbone interface cycle type 1.151 -wire [`LM32_CTYPE_RNG] I_CTI_O; 1.152 -output I_LOCK_O; // Instruction Wishbone interface lock bus 1.153 -wire I_LOCK_O; 1.154 -output [`LM32_BTYPE_RNG] I_BTE_O; // Instruction Wishbone interface burst type 1.155 -wire [`LM32_BTYPE_RNG] I_BTE_O; 1.156 -`endif 1.157 - 1.158 -output [`LM32_WORD_RNG] D_DAT_O; // Data Wishbone interface write data 1.159 -wire [`LM32_WORD_RNG] D_DAT_O; 1.160 -output [`LM32_WORD_RNG] D_ADR_O; // Data Wishbone interface address 1.161 -wire [`LM32_WORD_RNG] D_ADR_O; 1.162 -output D_CYC_O; // Data Wishbone interface cycle 1.163 -wire D_CYC_O; 1.164 -output [`LM32_BYTE_SELECT_RNG] D_SEL_O; // Data Wishbone interface byte select 1.165 -wire [`LM32_BYTE_SELECT_RNG] D_SEL_O; 1.166 -output D_STB_O; // Data Wishbone interface strobe 1.167 -wire D_STB_O; 1.168 -output D_WE_O; // Data Wishbone interface write enable 1.169 -wire D_WE_O; 1.170 -output [`LM32_CTYPE_RNG] D_CTI_O; // Data Wishbone interface cycle type 1.171 -wire [`LM32_CTYPE_RNG] D_CTI_O; 1.172 -output D_LOCK_O; // Date Wishbone interface lock bus 1.173 -wire D_LOCK_O; 1.174 -output [`LM32_BTYPE_RNG] D_BTE_O; // Data Wishbone interface burst type 1.175 -wire [`LM32_BTYPE_RNG] D_BTE_O; 1.176 - 1.177 -///////////////////////////////////////////////////// 1.178 -// Internal nets and registers 1.179 -///////////////////////////////////////////////////// 1.180 - 1.181 -`ifdef CFG_JTAG_ENABLED 1.182 -// Signals between JTAG interface and CPU 1.183 -wire [`LM32_BYTE_RNG] jtag_reg_d; 1.184 -wire [`LM32_BYTE_RNG] jtag_reg_q; 1.185 -wire jtag_update; 1.186 -wire [2:0] jtag_reg_addr_d; 1.187 -wire [2:0] jtag_reg_addr_q; 1.188 -wire jtck; 1.189 -wire jrstn; 1.190 -`endif 1.191 - 1.192 -// TODO: get the trace signals out 1.193 -`ifdef CFG_TRACE_ENABLED 1.194 -// PC trace signals 1.195 -wire [`LM32_PC_RNG] trace_pc; // PC to trace (address of next non-sequential instruction) 1.196 -wire trace_pc_valid; // Indicates that a new trace PC is valid 1.197 -wire trace_exception; // Indicates an exception has occured 1.198 -wire [`LM32_EID_RNG] trace_eid; // Indicates what type of exception has occured 1.199 -wire trace_eret; // Indicates an eret instruction has been executed 1.200 -`ifdef CFG_DEBUG_ENABLED 1.201 -wire trace_bret; // Indicates a bret instruction has been executed 1.202 -`endif 1.203 -`endif 1.204 - 1.205 -///////////////////////////////////////////////////// 1.206 -// Functions 1.207 -///////////////////////////////////////////////////// 1.208 - 1.209 -`include "lm32_functions.v" 1.210 -///////////////////////////////////////////////////// 1.211 -// Instantiations 1.212 -///////////////////////////////////////////////////// 1.213 - 1.214 -// LM32 CPU 1.215 -lm32_cpu cpu ( 1.216 - // ----- Inputs ------- 1.217 - .clk_i (clk_i), 1.218 -`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE 1.219 - .clk_n_i (clk_n), 1.220 -`endif 1.221 - .rst_i (rst_i), 1.222 - // From external devices 1.223 -`ifdef CFG_INTERRUPTS_ENABLED 1.224 - .interrupt (interrupt), 1.225 -`endif 1.226 - // From user logic 1.227 -`ifdef CFG_USER_ENABLED 1.228 - .user_result (user_result), 1.229 - .user_complete (user_complete), 1.230 -`endif 1.231 -`ifdef CFG_JTAG_ENABLED 1.232 - // From JTAG 1.233 - .jtag_clk (jtck), 1.234 - .jtag_update (jtag_update), 1.235 - .jtag_reg_q (jtag_reg_q), 1.236 - .jtag_reg_addr_q (jtag_reg_addr_q), 1.237 -`endif 1.238 -`ifdef CFG_IWB_ENABLED 1.239 - // Instruction Wishbone master 1.240 - .I_DAT_I (I_DAT_I), 1.241 - .I_ACK_I (I_ACK_I), 1.242 - .I_ERR_I (I_ERR_I), 1.243 - .I_RTY_I (I_RTY_I), 1.244 -`endif 1.245 - // Data Wishbone master 1.246 - .D_DAT_I (D_DAT_I), 1.247 - .D_ACK_I (D_ACK_I), 1.248 - .D_ERR_I (D_ERR_I), 1.249 - .D_RTY_I (D_RTY_I), 1.250 - // ----- Outputs ------- 1.251 -`ifdef CFG_TRACE_ENABLED 1.252 - .trace_pc (trace_pc), 1.253 - .trace_pc_valid (trace_pc_valid), 1.254 - .trace_exception (trace_exception), 1.255 - .trace_eid (trace_eid), 1.256 - .trace_eret (trace_eret), 1.257 -`ifdef CFG_DEBUG_ENABLED 1.258 - .trace_bret (trace_bret), 1.259 -`endif 1.260 -`endif 1.261 -`ifdef CFG_JTAG_ENABLED 1.262 - .jtag_reg_d (jtag_reg_d), 1.263 - .jtag_reg_addr_d (jtag_reg_addr_d), 1.264 -`endif 1.265 -`ifdef CFG_USER_ENABLED 1.266 - .user_valid (user_valid), 1.267 - .user_opcode (user_opcode), 1.268 - .user_operand_0 (user_operand_0), 1.269 - .user_operand_1 (user_operand_1), 1.270 -`endif 1.271 -`ifdef CFG_IWB_ENABLED 1.272 - // Instruction Wishbone master 1.273 - .I_DAT_O (I_DAT_O), 1.274 - .I_ADR_O (I_ADR_O), 1.275 - .I_CYC_O (I_CYC_O), 1.276 - .I_SEL_O (I_SEL_O), 1.277 - .I_STB_O (I_STB_O), 1.278 - .I_WE_O (I_WE_O), 1.279 - .I_CTI_O (I_CTI_O), 1.280 - .I_LOCK_O (I_LOCK_O), 1.281 - .I_BTE_O (I_BTE_O), 1.282 - `endif 1.283 - // Data Wishbone master 1.284 - .D_DAT_O (D_DAT_O), 1.285 - .D_ADR_O (D_ADR_O), 1.286 - .D_CYC_O (D_CYC_O), 1.287 - .D_SEL_O (D_SEL_O), 1.288 - .D_STB_O (D_STB_O), 1.289 - .D_WE_O (D_WE_O), 1.290 - .D_CTI_O (D_CTI_O), 1.291 - .D_LOCK_O (D_LOCK_O), 1.292 - .D_BTE_O (D_BTE_O) 1.293 - ); 1.294 - 1.295 - wire TRACE_ACK_O; 1.296 - wire [`LM32_WORD_RNG] TRACE_DAT_O; 1.297 -`ifdef CFG_TRACE_ENABLED 1.298 - lm32_trace trace_module (.clk_i (clk_i), 1.299 - .rst_i (rst_i), 1.300 - .stb_i (DEBUG_STB_I & DEBUG_ADR_I[13]), 1.301 - .we_i (DEBUG_WE_I), 1.302 - .sel_i (DEBUG_SEL_I), 1.303 - .dat_i (DEBUG_DAT_I), 1.304 - .adr_i (DEBUG_ADR_I), 1.305 - .trace_pc (trace_pc), 1.306 - .trace_eid (trace_eid), 1.307 - .trace_eret (trace_eret), 1.308 - .trace_bret (trace_bret), 1.309 - .trace_pc_valid (trace_pc_valid), 1.310 - .trace_exception (trace_exception), 1.311 - .ack_o (TRACE_ACK_O), 1.312 - .dat_o (TRACE_DAT_O)); 1.313 -`else 1.314 - assign TRACE_ACK_O = 0; 1.315 - assign TRACE_DAT_O = 0; 1.316 -`endif 1.317 -`ifdef DEBUG_ROM 1.318 - wire ROM_ACK_O; 1.319 - wire [`LM32_WORD_RNG] ROM_DAT_O; 1.320 - 1.321 - assign DEBUG_ACK_O = DEBUG_ADR_I[13] ? TRACE_ACK_O : ROM_ACK_O; 1.322 - assign DEBUG_DAT_O = DEBUG_ADR_I[13] ? TRACE_DAT_O : ROM_DAT_O; 1.323 - 1.324 - // ROM monitor 1.325 - lm32_monitor debug_rom ( 1.326 - // ----- Inputs ------- 1.327 - .clk_i (clk_i), 1.328 - .rst_i (rst_i), 1.329 - .MON_ADR_I (DEBUG_ADR_I[10:2]), 1.330 - .MON_STB_I (DEBUG_STB_I & ~DEBUG_ADR_I[13]), 1.331 - .MON_CYC_I (DEBUG_CYC_I & ~DEBUG_ADR_I[13]), 1.332 - .MON_WE_I (DEBUG_WE_I), 1.333 - .MON_SEL_I (DEBUG_SEL_I), 1.334 - .MON_DAT_I (DEBUG_DAT_I), 1.335 - // ----- Outputs ------ 1.336 - .MON_RTY_O (DEBUG_RTY_O), 1.337 - .MON_ERR_O (DEBUG_ERR_O), 1.338 - .MON_ACK_O (ROM_ACK_O), 1.339 - .MON_DAT_O (ROM_DAT_O) 1.340 - ); 1.341 -`endif 1.342 - 1.343 -`ifdef CFG_JTAG_ENABLED 1.344 -// JTAG cores 1.345 -jtag_cores jtag_cores ( 1.346 - // ----- Inputs ----- 1.347 - .reg_d (jtag_reg_d), 1.348 - .reg_addr_d (jtag_reg_addr_d), 1.349 - // ----- Outputs ----- 1.350 - .reg_update (jtag_update), 1.351 - .reg_q (jtag_reg_q), 1.352 - .reg_addr_q (jtag_reg_addr_q), 1.353 - .jtck (jtck), 1.354 - .jrstn (jrstn) 1.355 - ); 1.356 -`endif 1.357 - 1.358 -endmodule