Fix project layout to follow standards

     4.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     4.2 +++ b/doc/lever40.css	Tue Mar 08 09:40:42 2011 +0000
     4.3 @@ -0,0 +1,245 @@
     4.4 +H1 { 
     4.5 +    font-weight:bold; 
     4.6 +    border-top-style:none; 
     4.7 +    font-family:Arial, helvetica, sans-serif; 
     4.8 +    color:#ea6d23; 
     4.9 +    margin-left:15px; 
    4.10 +    margin-top:3px; 
    4.11 +    margin-bottom:10px; 
    4.12 +    border-bottom-style:Solid; 
    4.13 +    border-bottom-width:2px; 
    4.14 +    border-bottom-color:#dbdbdb; 
    4.15 +    margin-right:0px; 
    4.16 +    line-height:Normal; 
    4.17 +    font-size:1em;  }
    4.18 +LI.kadov-H1 { 
    4.19 +             font-weight:bold; 
    4.20 +             font-family:Arial, helvetica, sans-serif; 
    4.21 +             color:#ea6d23; 
    4.22 +             line-height:Normal; 
    4.23 +             font-size:1em;  }
    4.24 +H2 { 
    4.25 +    font-weight:bold; 
    4.26 +    x-text-underline:Off; 
    4.27 +    border-top-style:none; 
    4.28 +    border-bottom-style:none; 
    4.29 +    font-family:Arial, helvetica, sans-serif; 
    4.30 +    color:#ea6d23; 
    4.31 +    margin-left:15px; 
    4.32 +    margin-top:12px; 
    4.33 +    margin-bottom:5px; 
    4.34 +    font-size:0.84em; 
    4.35 +    margin-right:0px; 
    4.36 +    text-decoration:none;  }
    4.37 +LI.kadov-H2 { 
    4.38 +             font-weight:bold; 
    4.39 +             x-text-underline:Off; 
    4.40 +             font-family:Arial, helvetica, sans-serif; 
    4.41 +             color:#ea6d23; 
    4.42 +             font-size:0.84em; 
    4.43 +             text-decoration:none;  }
    4.44 +P { 
    4.45 +   margin-top:0pt; 
    4.46 +   font-family:Verdana, Arial, helvetica, sans-serif; 
    4.47 +   color:#323232; 
    4.48 +   font-size:71%; 
    4.49 +   margin-bottom:8px; 
    4.50 +   line-height:1.4em; 
    4.51 +   margin-right:0px; 
    4.52 +   margin-left:15px;  }
    4.53 +LI.kadov-P { 
    4.54 +            font-family:Verdana, Arial, helvetica, sans-serif; 
    4.55 +            color:#323232; 
    4.56 +            font-size:71%; 
    4.57 +            line-height:1.4em;  }
    4.58 +p.Step { 
    4.59 +        list-style:decimal; 
    4.60 +        margin-left:0px; 
    4.61 +        font-size:100%; 
    4.62 +        margin-bottom:7px; 
    4.63 +        margin-top:0px;  }
    4.64 +LI.kadov-p-CStep { 
    4.65 +                  list-style:decimal; 
    4.66 +                  font-size:100%;  }
    4.67 +P.Bullet { 
    4.68 +          font-size:100%; 
    4.69 +          list-style:url("image/top-bullet.gif"); 
    4.70 +          margin-bottom:7px; 
    4.71 +          margin-left:0px; 
    4.72 +          margin-top:0px;  }
    4.73 +LI.kadov-P-CBullet { 
    4.74 +                    font-size:100%; 
    4.75 +                    list-style:url("image/top-bullet.gif");  }
    4.76 +P.NormalIndent { 
    4.77 +                margin-left:40px;  }
    4.78 +LI.kadov-P-CNormalIndent {  }
    4.79 +P.BulletIndent { 
    4.80 +                margin-bottom:2px; 
    4.81 +                font-size:100%; 
    4.82 +                margin-left:15pt; 
    4.83 +                list-style:url("image/secondary-bullet.gif");  }
    4.84 +LI.kadov-P-CBulletIndent { 
    4.85 +                          font-size:100%; 
    4.86 +                          list-style:url("image/secondary-bullet.gif");  }
    4.87 +P.Procedure { 
    4.88 +             font-style:italic; 
    4.89 +             font-weight:normal; 
    4.90 +             x-next-class:Step; 
    4.91 +             x-next-type:p; 
    4.92 +             margin-top:12pt; 
    4.93 +             margin-bottom:5px;  }
    4.94 +LI.kadov-P-CProcedure { 
    4.95 +                       font-style:italic; 
    4.96 +                       font-weight:normal;  }
    4.97 +P.Note { 
    4.98 +        margin-top:8pt; 
    4.99 +        margin-bottom:8pt; 
   4.100 +        border-top-style:Solid; 
   4.101 +        border-bottom-style:Solid; 
   4.102 +        padding-top:4px; 
   4.103 +        padding-bottom:4px; 
   4.104 +        border-top-width:1px; 
   4.105 +        border-bottom-width:1px; 
   4.106 +        background-color:#ffffff;  }
   4.107 +LI.kadov-P-CNote {  }
   4.108 +P.NoteIndent { 
   4.109 +              margin-top:8pt; 
   4.110 +              margin-bottom:8pt; 
   4.111 +              border-top-style:Solid; 
   4.112 +              border-bottom-style:Solid; 
   4.113 +              padding-top:4px; 
   4.114 +              padding-bottom:4px; 
   4.115 +              border-top-width:1px; 
   4.116 +              border-bottom-width:1px; 
   4.117 +              background-color:#ffffff; 
   4.118 +              margin-left:40px;  }
   4.119 +LI.kadov-P-CNoteIndent {  }
   4.120 +P.Table { 
   4.121 +         margin-top:4px; 
   4.122 +         margin-bottom:4px; 
   4.123 +         margin-right:4px; 
   4.124 +         margin-left:4px;  }
   4.125 +LI.kadov-P-CTable {  }
   4.126 +P.Code { 
   4.127 +        margin-bottom:0px; 
   4.128 +        line-height:Normal; 
   4.129 +        font-family:"Courier New"  , Courier, monospace;  }
   4.130 +LI.kadov-P-CCode { 
   4.131 +                  line-height:Normal; 
   4.132 +                  font-family:"Courier New"  , Courier, monospace;  }
   4.133 +P.StepBulletFirst { 
   4.134 +                   font-size:100%; 
   4.135 +                   margin-left:15px; 
   4.136 +                   margin-bottom:2px; 
   4.137 +                   list-style:url("image/secondary-bullet.gif");  }
   4.138 +LI.kadov-P-CStepBulletFirst { 
   4.139 +                             font-size:100%; 
   4.140 +                             list-style:url("image/secondary-bullet.gif");  }
   4.141 +BODY { 
   4.142 +      background-color:#ffffff; 
   4.143 +      color:#000080; 
   4.144 +      font-family:Arial, sans-serif;  }
   4.145 +P.SeeAlso { 
   4.146 +           font-weight:bold; 
   4.147 +           font-style:normal; 
   4.148 +           x-next-type:P; 
   4.149 +           color:#ea6d23; 
   4.150 +           font-family:Arial, helvetica, sans-serif; 
   4.151 +           margin-left:15px; 
   4.152 +           margin-top:12px; 
   4.153 +           margin-bottom:5px; 
   4.154 +           font-size:0.84em;  }
   4.155 +LI.kadov-P-CSeeAlso { 
   4.156 +                     font-weight:bold; 
   4.157 +                     font-style:normal; 
   4.158 +                     color:#ea6d23; 
   4.159 +                     font-family:Arial, helvetica, sans-serif; 
   4.160 +                     font-size:0.84em;  }
   4.161 +A:link { 
   4.162 +        font-weight:bold; 
   4.163 +        font-style:normal; 
   4.164 +        color:#003a98; 
   4.165 +        x-text-underline:Off; 
   4.166 +        text-decoration:none;  }
   4.167 +A:hover { 
   4.168 +         x-text-underline:Normal; 
   4.169 +         color:#59add3; 
   4.170 +         text-decoration:underline;  }
   4.171 +A:active { 
   4.172 +          color:#59add3;  }
   4.173 +A:visited { 
   4.174 +           x-text-underline:Off; 
   4.175 +           color:#385689; 
   4.176 +           font-weight:bold; 
   4.177 +           font-style:normal; 
   4.178 +           text-decoration:none;  }
   4.179 +H1.Home { 
   4.180 +         x-next-type:P; 
   4.181 +         border-top-style:none; 
   4.182 +         border-bottom-style:none; 
   4.183 +         x-text-underline:Off; 
   4.184 +         font-size:15pt; 
   4.185 +         color:#ea6d23; 
   4.186 +         text-decoration:none;  }
   4.187 +LI.kadov-H1-CHome { 
   4.188 +                   x-text-underline:Off; 
   4.189 +                   font-size:15pt; 
   4.190 +                   color:#ea6d23; 
   4.191 +                   text-decoration:none;  }
   4.192 +H3 { 
   4.193 +    margin-left:15px; 
   4.194 +    margin-top:12px; 
   4.195 +    margin-bottom:5px; 
   4.196 +    color:#323232; 
   4.197 +    font-size:71%; 
   4.198 +    font-family:Verdana, Arial, helvetica, sans-serif; 
   4.199 +    margin-right:0px;  }
   4.200 +LI.kadov-H3 { 
   4.201 +             color:#323232; 
   4.202 +             font-size:71%; 
   4.203 +             font-family:Verdana, Arial, helvetica, sans-serif;  }
   4.204 +P.Title { 
   4.205 +         font-weight:bold; 
   4.206 +         font-style:normal; 
   4.207 +         x-next-type:P; 
   4.208 +         font-family:Arial, helvetica, sans-serif; 
   4.209 +         color:#ea6d23; 
   4.210 +         margin-bottom:10px; 
   4.211 +         font-size:1.4em; 
   4.212 +         line-height:Normal; 
   4.213 +         border-bottom-style:Solid; 
   4.214 +         border-bottom-width:2px; 
   4.215 +         border-bottom-color:#dbdbdb; 
   4.216 +         margin-top:0px;  }
   4.217 +LI.kadov-P-CTitle { 
   4.218 +                   font-weight:bold; 
   4.219 +                   font-style:normal; 
   4.220 +                   font-family:Arial, helvetica, sans-serif; 
   4.221 +                   color:#ea6d23; 
   4.222 +                   font-size:1.4em; 
   4.223 +                   line-height:Normal;  }
   4.224 +P.Supra { 
   4.225 +         font-weight:bold; 
   4.226 +         font-style:normal; 
   4.227 +         margin-bottom:6pt; 
   4.228 +         font-family:Arial, helvetica, sans-serif;  }
   4.229 +LI.kadov-P-CSupra { 
   4.230 +                   font-weight:bold; 
   4.231 +                   font-style:normal; 
   4.232 +                   font-family:Arial, helvetica, sans-serif;  }
   4.233 +OL { 
   4.234 +    font-size:71%; 
   4.235 +    font-family:Verdana, Arial, helvetica, sans-serif; 
   4.236 +    color:#323232;  }
   4.237 +UL { 
   4.238 +    font-size:71%; 
   4.239 +    font-family:Verdana, Arial, helvetica, sans-serif; 
   4.240 +    color:#323232;  }
   4.241 +P.CodeIndent { 
   4.242 +              font-family:"Courier New"  , Courier, monospace; 
   4.243 +              margin-left:40px; 
   4.244 +              margin-bottom:0px; 
   4.245 +              line-height:Normal;  }
   4.246 +LI.kadov-P-CCodeIndent { 
   4.247 +                        font-family:"Courier New"  , Courier, monospace; 
   4.248 +                        line-height:Normal;  }

     5.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     5.2 +++ b/doc/lever40_ns.css	Tue Mar 08 09:40:42 2011 +0000
     5.3 @@ -0,0 +1,248 @@
     5.4 +H1 { 
     5.5 +    font-weight:bold; 
     5.6 +    border-top-style:none; 
     5.7 +    font-family:Arial, helvetica, sans-serif; 
     5.8 +    color:#ea6d23; 
     5.9 +    margin-left:15px; 
    5.10 +    margin-top:3px; 
    5.11 +    margin-bottom:10px; 
    5.12 +    border-bottom-style:Solid; 
    5.13 +    border-bottom-width:2px; 
    5.14 +    border-bottom-color:#dbdbdb; 
    5.15 +    margin-right:1pt; 
    5.16 +    line-height:Normal; 
    5.17 +    font-size:1em;  }
    5.18 +LI.kadov-H1 { 
    5.19 +             font-weight:bold; 
    5.20 +             font-family:Arial, helvetica, sans-serif; 
    5.21 +             color:#ea6d23; 
    5.22 +             line-height:Normal; 
    5.23 +             font-size:1em;  }
    5.24 +H2 { 
    5.25 +    font-weight:bold; 
    5.26 +    x-text-underline:Off; 
    5.27 +    border-top-style:none; 
    5.28 +    border-bottom-style:none; 
    5.29 +    font-family:Arial, helvetica, sans-serif; 
    5.30 +    color:#ea6d23; 
    5.31 +    margin-left:15px; 
    5.32 +    margin-top:12px; 
    5.33 +    margin-bottom:5px; 
    5.34 +    font-size:0.84em; 
    5.35 +    margin-right:1pt; 
    5.36 +    text-decoration:none;  }
    5.37 +LI.kadov-H2 { 
    5.38 +             font-weight:bold; 
    5.39 +             x-text-underline:Off; 
    5.40 +             font-family:Arial, helvetica, sans-serif; 
    5.41 +             color:#ea6d23; 
    5.42 +             font-size:0.84em; 
    5.43 +             text-decoration:none;  }
    5.44 +P { 
    5.45 +   margin-top:1pt; 
    5.46 +   font-family:Verdana, Arial, helvetica, sans-serif; 
    5.47 +   color:#323232; 
    5.48 +   font-size:71%; 
    5.49 +   margin-bottom:8px; 
    5.50 +   line-height:1.4em; 
    5.51 +   margin-right:1pt; 
    5.52 +   margin-left:15px;  }
    5.53 +LI.kadov-P { 
    5.54 +            font-family:Verdana, Arial, helvetica, sans-serif; 
    5.55 +            color:#323232; 
    5.56 +            font-size:71%; 
    5.57 +            line-height:1.4em;  }
    5.58 +p.Step { 
    5.59 +        list-style:decimal; 
    5.60 +        margin-left:1pt; 
    5.61 +        font-size:100%; 
    5.62 +        margin-bottom:7px; 
    5.63 +        margin-top:1pt;  }
    5.64 +LI.kadov-p-CStep { 
    5.65 +                  list-style:decimal; 
    5.66 +                  font-size:100%;  }
    5.67 +P.Bullet { 
    5.68 +          font-size:100%; 
    5.69 +          margin-bottom:7px; 
    5.70 +          margin-left:1pt; 
    5.71 +          margin-top:1pt;  }
    5.72 +LI.kadov-P-CBullet { 
    5.73 +                    font-size:100%;  }
    5.74 +P.NormalIndent { 
    5.75 +                margin-left:40px;  }
    5.76 +LI.kadov-P-CNormalIndent {  }
    5.77 +P.BulletIndent { 
    5.78 +                margin-bottom:2px; 
    5.79 +                font-size:100%; 
    5.80 +                margin-left:15pt;  }
    5.81 +LI.kadov-P-CBulletIndent { 
    5.82 +                          font-size:100%;  }
    5.83 +P.Procedure { 
    5.84 +             font-style:italic; 
    5.85 +             font-weight:normal; 
    5.86 +             x-next-class:Step; 
    5.87 +             x-next-type:p; 
    5.88 +             margin-top:12pt; 
    5.89 +             margin-bottom:5px;  }
    5.90 +LI.kadov-P-CProcedure { 
    5.91 +                       font-style:italic; 
    5.92 +                       font-weight:normal;  }
    5.93 +P.Note { 
    5.94 +        margin-top:8pt; 
    5.95 +        margin-bottom:8pt; 
    5.96 +        border-top-style:Solid; 
    5.97 +        border-bottom-style:Solid; 
    5.98 +        padding-top:4px; 
    5.99 +        padding-bottom:4px; 
   5.100 +        border-top-width:1px; 
   5.101 +        border-bottom-width:1px; 
   5.102 +        background-color:#ffffff;  }
   5.103 +LI.kadov-P-CNote {  }
   5.104 +P.NoteIndent { 
   5.105 +              margin-top:8pt; 
   5.106 +              margin-bottom:8pt; 
   5.107 +              border-top-style:Solid; 
   5.108 +              border-bottom-style:Solid; 
   5.109 +              padding-top:4px; 
   5.110 +              padding-bottom:4px; 
   5.111 +              border-top-width:1px; 
   5.112 +              border-bottom-width:1px; 
   5.113 +              background-color:#ffffff; 
   5.114 +              margin-left:40px;  }
   5.115 +LI.kadov-P-CNoteIndent {  }
   5.116 +P.Table { 
   5.117 +         margin-top:4px; 
   5.118 +         margin-bottom:4px; 
   5.119 +         margin-right:4px; 
   5.120 +         margin-left:4px;  }
   5.121 +LI.kadov-P-CTable {  }
   5.122 +P.Code { 
   5.123 +        margin-bottom:1pt; 
   5.124 +        line-height:Normal; 
   5.125 +        font-family:"Courier New"     , Courier, monospace;  }
   5.126 +LI.kadov-P-CCode { 
   5.127 +                  line-height:Normal; 
   5.128 +                  font-family:"Courier New"     , Courier, monospace;  }
   5.129 +P.StepBulletFirst { 
   5.130 +                   font-size:100%; 
   5.131 +                   margin-left:15px; 
   5.132 +                   margin-bottom:2px;  }
   5.133 +LI.kadov-P-CStepBulletFirst { 
   5.134 +                             font-size:100%;  }
   5.135 +BODY { 
   5.136 +      background-color:#ffffff; 
   5.137 +      color:#000080; 
   5.138 +      font-family:Arial, sans-serif;  }
   5.139 +P.SeeAlso { 
   5.140 +           font-weight:bold; 
   5.141 +           font-style:normal; 
   5.142 +           x-next-type:P; 
   5.143 +           color:#ea6d23; 
   5.144 +           font-family:Arial, helvetica, sans-serif; 
   5.145 +           margin-left:15px; 
   5.146 +           margin-top:12px; 
   5.147 +           margin-bottom:5px; 
   5.148 +           font-size:0.84em;  }
   5.149 +LI.kadov-P-CSeeAlso { 
   5.150 +                     font-weight:bold; 
   5.151 +                     font-style:normal; 
   5.152 +                     color:#ea6d23; 
   5.153 +                     font-family:Arial, helvetica, sans-serif; 
   5.154 +                     font-size:0.84em;  }
   5.155 +A:link { 
   5.156 +        font-weight:bold; 
   5.157 +        font-style:normal; 
   5.158 +        color:#003a98; 
   5.159 +        x-text-underline:Off; 
   5.160 +        text-decoration:none;  }
   5.161 +A:hover { 
   5.162 +         x-text-underline:Normal; 
   5.163 +         color:#59add3; 
   5.164 +         text-decoration:underline;  }
   5.165 +A:active { 
   5.166 +          color:#59add3;  }
   5.167 +A:visited { 
   5.168 +           x-text-underline:Off; 
   5.169 +           color:#385689; 
   5.170 +           font-weight:bold; 
   5.171 +           font-style:normal; 
   5.172 +           text-decoration:none;  }
   5.173 +H1.Home { 
   5.174 +         x-next-type:P; 
   5.175 +         border-top-style:none; 
   5.176 +         border-bottom-style:none; 
   5.177 +         x-text-underline:Off; 
   5.178 +         font-size:15pt; 
   5.179 +         color:#ea6d23; 
   5.180 +         text-decoration:none;  }
   5.181 +LI.kadov-H1-CHome { 
   5.182 +                   x-text-underline:Off; 
   5.183 +                   font-size:15pt; 
   5.184 +                   color:#ea6d23; 
   5.185 +                   text-decoration:none;  }
   5.186 +H3 { 
   5.187 +    margin-left:15px; 
   5.188 +    margin-top:12px; 
   5.189 +    margin-bottom:5px; 
   5.190 +    color:#323232; 
   5.191 +    font-size:71%; 
   5.192 +    font-family:Verdana, Arial, helvetica, sans-serif; 
   5.193 +    margin-right:1pt; 
   5.194 +    font-weight:bold;  }
   5.195 +LI.kadov-H3 { 
   5.196 +             color:#323232; 
   5.197 +             font-size:71%; 
   5.198 +             font-family:Verdana, Arial, helvetica, sans-serif;  }
   5.199 +P.Title { 
   5.200 +         font-weight:bold; 
   5.201 +         font-style:normal; 
   5.202 +         x-next-type:P; 
   5.203 +         font-family:Arial, helvetica, sans-serif; 
   5.204 +         color:#ea6d23; 
   5.205 +         margin-bottom:10px; 
   5.206 +         font-size:1.4em; 
   5.207 +         line-height:Normal; 
   5.208 +         border-bottom-style:Solid; 
   5.209 +         border-bottom-width:2px; 
   5.210 +         border-bottom-color:#dbdbdb; 
   5.211 +         margin-top:1pt;  }
   5.212 +LI.kadov-P-CTitle { 
   5.213 +                   font-weight:bold; 
   5.214 +                   font-style:normal; 
   5.215 +                   font-family:Arial, helvetica, sans-serif; 
   5.216 +                   color:#ea6d23; 
   5.217 +                   font-size:1.4em; 
   5.218 +                   line-height:Normal;  }
   5.219 +P.Supra { 
   5.220 +         font-weight:bold; 
   5.221 +         font-style:normal; 
   5.222 +         margin-bottom:6pt; 
   5.223 +         font-family:Arial, helvetica, sans-serif;  }
   5.224 +LI.kadov-P-CSupra { 
   5.225 +                   font-weight:bold; 
   5.226 +                   font-style:normal; 
   5.227 +                   font-family:Arial, helvetica, sans-serif;  }
   5.228 +OL { 
   5.229 +    font-size:71%; 
   5.230 +    font-family:Verdana, Arial, helvetica, sans-serif; 
   5.231 +    color:#323232;  }
   5.232 +UL { 
   5.233 +    font-size:71%; 
   5.234 +    font-family:Verdana, Arial, helvetica, sans-serif; 
   5.235 +    color:#323232;  }
   5.236 +P.CodeIndent { 
   5.237 +              font-family:"Courier New"     , Courier, monospace; 
   5.238 +              margin-left:40px; 
   5.239 +              margin-bottom:1pt; 
   5.240 +              line-height:Normal;  }
   5.241 +LI.kadov-P-CCodeIndent { 
   5.242 +                        font-family:"Courier New"     , Courier, monospace; 
   5.243 +                        line-height:Normal;  }
   5.244 +ol ol { 
   5.245 +       margin-top:1px;  }
   5.246 +ol ul { 
   5.247 +       margin-top:1px;  }
   5.248 +ul ul { 
   5.249 +       margin-top:1px;  }
   5.250 +ul ol { 
   5.251 +       margin-top:1px;  }

     6.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     6.2 +++ b/doc/lm32.htm	Tue Mar 08 09:40:42 2011 +0000
     6.3 @@ -0,0 +1,661 @@
     6.4 +<!doctype HTML public "-//W3C//DTD HTML 4.0 Frameset//EN">
     6.5 +
     6.6 +<html>
     6.7 +
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    6.12 +<link rel="stylesheet" href="lever40_ns.css"><script type="text/javascript" language="JavaScript" title="WebHelpSplitCss">
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    6.14 +if (navigator.appName !="Netscape")
    6.15 +{   document.write("<link rel='stylesheet' href='lever40.css'>");}
    6.16 +//-->
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    6.18 +<style>
    6.19 +<!--
    6.20 +body { border-left-style:None; border-right-style:None; border-top-style:None; border-bottom-style:None; }
    6.21 +-->
    6.22 +</style><style type="text/css">
    6.23 +<!--
    6.24 +img_whs1 { border:none; width:29px; height:31px; float:none; border-style:none; }
    6.25 +p.whs2 { font-style:italic; }
    6.26 +table.whs3 { x-cell-content-align:top; height:84px; left:0px; top:114px; width:738px; margin-left:15px; border-spacing:0px; }
    6.27 +col.whs4 { width:93px; }
    6.28 +col.whs5 { width:598px; }
    6.29 +tr.whs6 { x-cell-content-align:top; height:22px; }
    6.30 +td.whs7 { width:93px; padding-right:10px; padding-left:10px; border-left-style:Solid; border-left-color:#c0c0c0; border-top-style:Solid; border-top-color:#c0c0c0; border-right-color:#c0c0c0; border-right-style:Solid; border-bottom-color:#c0c0c0; border-bottom-style:Solid; border-right-width:1px; border-left-width:1px; border-top-width:1px; border-bottom-width:1px; background-color:#dee8f4; }
    6.31 +td.whs8 { width:598px; padding-right:10px; padding-left:10px; border-top-style:Solid; border-top-color:#c0c0c0; border-right-color:#c0c0c0; border-right-style:Solid; border-bottom-color:#c0c0c0; border-bottom-style:Solid; border-top-width:1px; border-bottom-width:1px; border-right-width:1px; background-color:#dee8f4; }
    6.32 +td.whs9 { width:93px; padding-right:10px; padding-left:10px; border-left-color:#c0c0c0; border-left-width:1px; border-left-style:Solid; border-right-color:#c0c0c0; border-right-style:Solid; border-right-width:1px; border-bottom-color:#c0c0c0; border-bottom-style:Solid; border-bottom-width:1px; }
    6.33 +td.whs10 { width:598px; padding-right:10px; padding-left:10px; border-right-color:#c0c0c0; border-right-style:Solid; border-right-width:1px; border-bottom-color:#c0c0c0; border-bottom-style:Solid; border-bottom-width:1px; }
    6.34 +p.whs11 { margin-left:4px; }
    6.35 +table.whs12 { x-cell-content-align:top; margin-left:15px; border-spacing:0px; }
    6.36 +col.whs13 { width:167px; }
    6.37 +col.whs14 { width:524px; }
    6.38 +tr.whs15 { x-cell-content-align:top; }
    6.39 +td.whs16 { width:167px; padding-right:10px; padding-left:10px; background-color:#dee8f4; border-left-color:#c0c0c0; border-top-color:#c0c0c0; border-top-style:Solid; border-bottom-color:#c0c0c0; border-bottom-width:1px; border-bottom-style:Solid; border-right-color:#c0c0c0; border-right-width:1px; border-right-style:Solid; border-left-width:1px; border-left-style:solid; border-top-width:1px; }
    6.40 +td.whs17 { width:524px; padding-right:10px; padding-left:10px; background-color:#dee8f4; border-top-style:Solid; border-top-color:#c0c0c0; border-right-style:Solid; border-right-color:#c0c0c0; border-bottom-color:#c0c0c0; border-bottom-width:1px; border-bottom-style:Solid; border-top-width:1px; border-right-width:1px; }
    6.41 +td.whs18 { width:167px; padding-right:10px; padding-left:10px; border-left-color:#c0c0c0; border-bottom-color:#c0c0c0; border-bottom-width:1px; border-bottom-style:Solid; border-right-color:#c0c0c0; border-right-width:1px; border-right-style:Solid; border-left-width:1px; border-left-style:solid; }
    6.42 +td.whs19 { width:524px; border-right-style:Solid; border-right-color:#c0c0c0; border-bottom-color:#c0c0c0; border-bottom-width:1px; border-bottom-style:Solid; border-right-width:1px; }
    6.43 +td.whs20 { width:691px; padding-right:10px; padding-left:10px; border-left-color:#c0c0c0; border-right-style:Solid; border-right-color:#c0c0c0; border-bottom-color:#c0c0c0; border-bottom-width:1px; border-bottom-style:Solid; border-left-width:1px; border-left-style:solid; border-right-width:1px; }
    6.44 +td.whs21 { width:524px; padding-right:10px; padding-left:10px; border-right-style:Solid; border-right-color:#c0c0c0; border-bottom-color:#c0c0c0; border-bottom-width:1px; border-bottom-style:Solid; border-right-width:1px; }
    6.45 +ul.whs22 { list-style:disc; }
    6.46 +td.whs23 { width:167px; padding-right:10px; padding-left:10px; border-left-color:#c0c0c0; border-bottom-color:#c0c0c0; border-bottom-style:Solid; border-right-color:#c0c0c0; border-right-width:1px; border-right-style:Solid; border-left-width:1px; border-left-style:solid; border-bottom-width:1px; }
    6.47 +td.whs24 { width:524px; padding-right:10px; padding-left:10px; border-right-style:Solid; border-right-color:#c0c0c0; border-bottom-style:Solid; border-bottom-color:#c0c0c0; border-bottom-width:1px; border-right-width:1px; }
    6.48 +td.whs25 { width:167px; padding-right:10px; padding-left:10px; background-color:#dee8f4; border-left-color:#c0c0c0; border-top-style:Solid; border-top-color:#c0c0c0; border-right-color:#c0c0c0; border-right-style:Solid; border-bottom-color:#c0c0c0; border-bottom-width:1px; border-bottom-style:Solid; border-right-width:1px; border-left-width:1px; border-left-style:Solid; border-top-width:1px; }
    6.49 +td.whs26 { width:524px; padding-right:10px; padding-left:10px; background-color:#dee8f4; border-top-style:Solid; border-top-color:#c0c0c0; border-bottom-color:#c0c0c0; border-bottom-width:1px; border-bottom-style:Solid; border-top-width:1px; border-right-color:#c0c0c0; border-right-width:1px; border-right-style:Solid; }
    6.50 +td.whs27 { width:691px; padding-right:10px; padding-left:10px; border-left-color:#c0c0c0; border-bottom-color:#c0c0c0; border-bottom-width:1px; border-bottom-style:Solid; border-left-width:1px; border-left-style:Solid; border-right-color:#c0c0c0; border-right-width:1px; border-right-style:Solid; }
    6.51 +td.whs28 { width:167px; padding-right:10px; padding-left:10px; border-left-color:#c0c0c0; border-right-color:#c0c0c0; border-right-style:Solid; border-bottom-color:#c0c0c0; border-bottom-width:1px; border-bottom-style:Solid; border-right-width:1px; border-left-width:1px; border-left-style:Solid; }
    6.52 +td.whs29 { width:524px; padding-right:10px; padding-left:10px; border-bottom-color:#c0c0c0; border-bottom-width:1px; border-bottom-style:Solid; border-right-color:#c0c0c0; border-right-width:1px; border-right-style:Solid; }
    6.53 +td.whs30 { width:167px; padding-right:10px; padding-left:10px; border-left-color:#c0c0c0; border-right-color:#c0c0c0; border-right-style:Solid; border-bottom-color:#c0c0c0; border-bottom-style:Solid; border-right-width:1px; border-left-width:1px; border-left-style:Solid; border-bottom-width:1px; }
    6.54 +td.whs31 { width:524px; padding-right:10px; padding-left:10px; border-bottom-color:#c0c0c0; border-bottom-style:Solid; border-bottom-width:1px; border-right-color:#c0c0c0; border-right-width:1px; border-right-style:Solid; }
    6.55 +img_whs32 { border:none; width:14px; height:16px; float:none; border-style:none; }
    6.56 +-->
    6.57 +</style><script type="text/javascript" language="JavaScript">
    6.58 +<!--
    6.59 +function ehlp_showtip(current,e,text)
    6.60 +{
    6.61 +  if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape'))
    6.62 +  {
    6.63 +    document.tooltip.document.write("<layer bgColor='yellow' style='border:1px solid black;font-size:12px;'>"+ text + "</layer>");
    6.64 +    document.tooltip.document.close();
    6.65 +    document.tooltip.left=e.pageX+5;
    6.66 +    document.tooltip.top=e.pageY+5;
    6.67 +    document.tooltip.visibility="show";
    6.68 +  }
    6.69 +}
    6.70 +function ehlp_hidetip()
    6.71 +{
    6.72 +  document.tooltip.visibility="hidden";
    6.73 +}
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    6.75 +</script>
    6.76 +<script type="text/javascript" language="JavaScript" title="WebHelpInlineScript">
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    6.78 +function reDo() {
    6.79 +  if (innerWidth != origWidth || innerHeight != origHeight)
    6.80 +     location.reload();
    6.81 +}
    6.82 +if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == "Netscape")) {
    6.83 +	origWidth = innerWidth;
    6.84 +	origHeight = innerHeight;
    6.85 +	onresize = reDo;
    6.86 +}
    6.87 +onerror = null; 
    6.88 +//-->
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    6.90 +<style type="text/css">
    6.91 +<!--
    6.92 +div.WebHelpPopupMenu { position:absolute; left:0px; top:0px; z-index:4; visibility:hidden; }
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    6.95 +</style><script type="text/javascript" language="javascript1.2" src="whmsg.js"></script>
    6.96 +<script type="text/javascript" language="javascript" src="whver.js"></script>
    6.97 +<script type="text/javascript" language="javascript1.2" src="whproxy.js"></script>
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    6.99 +<script type="text/javascript" language="javascript1.2" src="whtopic.js"></script>
   6.100 +<script type="text/javascript" language="javascript1.2">
   6.101 +<!--
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   6.103 +{
   6.104 +	if (window.setRelStartPage)
   6.105 +	{
   6.106 +	addTocInfo("LM32");
   6.107 +
   6.108 +	}
   6.109 +
   6.110 +
   6.111 +	if (window.setRelStartPage)
   6.112 +	{
   6.113 +	setRelStartPage("msb_peripherals.htm");
   6.114 +
   6.115 +		autoSync(0);
   6.116 +		sendSyncInfo();
   6.117 +		sendAveInfoOut();
   6.118 +	}
   6.119 +
   6.120 +}
   6.121 +else
   6.122 +	if (window.gbIE4)
   6.123 +		document.location.reload();
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   6.133 +<h1>LatticeMico32 Processor &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<a title="View Reference Manual" href="lm32_archman.pdf" target="_blank" onmouseover="if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) ehlp_showtip(this,event,'View Reference Manual');" onmouseout="if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) ehlp_hidetip();"><img src="ds_icon_ast.jpg" x-maintain-ratio="TRUE" width="29px" height="31px" border="0" class="img_whs1"></a></h1>
   6.134 +
   6.135 +<p>The LatticeMico32 processor is a high-performance 32-bit microprocessor 
   6.136 + optimized for Lattice Semiconductor field-programmable gate arrays. </p>
   6.137 +
   6.138 +<p class="whs2"><span style="font-style: italic;"><I>*If the 
   6.139 + processor manual fails to open, see the note at the bottom of this page.</I></span></p>
   6.140 +
   6.141 +<h2>Revision History</h2>
   6.142 +
   6.143 +<table x-use-null-cells cellspacing="0" width="738" height="84" class="whs3">
   6.144 +<script language='JavaScript'><!--
   6.145 +if ((navigator.appName == "Netscape") && (parseInt(navigator.appVersion) == 4)) document.write("</table><table x-use-null-cells cellspacing='0' width='738' height='84' border='1' bordercolor='silver' bordercolorlight='silver' bordercolordark='silver'>");
   6.146 +//--></script>
   6.147 +<col class="whs4">
   6.148 +<col class="whs5">
   6.149 +
   6.150 +<tr valign="top" class="whs6">
   6.151 +<td bgcolor="#DEE8F4" width="93px" class="whs7">
   6.152 +<p class=Table
   6.153 +	style="font-weight: bold;">Version</td>
   6.154 +<td bgcolor="#DEE8F4" width="598px" class="whs8">
   6.155 +<p class=Table
   6.156 +	style="font-weight: bold;">Description</td></tr>
   6.157 +
   6.158 +<tr valign="top" class="whs6">
   6.159 +<td colspan="1" rowspan="1" width="93px" class="whs9">
   6.160 +<p class=Table
   6.161 +	style="font-weight: normal;">3.6</td>
   6.162 +<td colspan="1" rowspan="1" width="598px" class="whs10">
   6.163 +<p class=whs10
   6.164 +	style="margin-left: 0px;">Fixed the issue of the processor locking 
   6.165 + up when Instruction Cache is not used.</td></tr>
   6.166 +
   6.167 +<tr valign="top" class="whs6">
   6.168 +<td colspan="1" rowspan="1" width="93px" class="whs9">
   6.169 +<p class=Table
   6.170 +	style="font-weight: normal;">3.5</td>
   6.171 +<td colspan="1" rowspan="1" width="598px" class="whs10">
   6.172 +<p class=whs10
   6.173 +	style="margin-left: 0px;">Support added to allow Inline Memories to 
   6.174 + be generated as non-power-of-two, as long as they are a multiple of 1024 
   6.175 + bytes</td></tr>
   6.176 +
   6.177 +<tr valign="top" class="whs6">
   6.178 +<td colspan="1" rowspan="1" width="93px" class="whs9">
   6.179 +<p class=Table
   6.180 +	style="font-weight: normal;">3.4</td>
   6.181 +<td colspan="1" rowspan="1" width="598px" class="whs10">
   6.182 +<p class=whs10
   6.183 +	style="margin-left: 0px;">Updated to support ispLEVER 7.2 SP1.</td></tr>
   6.184 +
   6.185 +<tr valign="top" class="whs6">
   6.186 +<td colspan="1" rowspan="1" width="93px" class="whs9">
   6.187 +<p class=Table
   6.188 +	style="font-weight: normal;">3.3</td>
   6.189 +<td colspan="1" rowspan="1" width="598px" class="whs10">
   6.190 +<p class=whs10
   6.191 +	style="margin-left: 0px;">Updated to support ispLEVER 7.2.</p>
   6.192 +<p class=whs10
   6.193 +	style="margin-left: 0px;">Added Inline Memory to support on-chip memory 
   6.194 + connected through a local bus.</td></tr>
   6.195 +
   6.196 +<tr valign="top" class="whs6">
   6.197 +<td colspan="1" rowspan="1" width="93px" class="whs9">
   6.198 +<p class=Table
   6.199 +	style="font-weight: normal;">3.2</td>
   6.200 +<td colspan="1" rowspan="1" width="598px" class="whs10">
   6.201 +<p class=whs10
   6.202 +	style="margin-left: 0px;">Updated to support ispLEVER 7.1 SP1</p>
   6.203 +<p class=whs10
   6.204 +	style="margin-left: 0px;">Added Memory Type to instruction cache and 
   6.205 + data cache.</td></tr>
   6.206 +
   6.207 +<tr valign="top" class="whs6">
   6.208 +<td colspan="1" rowspan="1" width="93px" class="whs9">
   6.209 +<p class=Table
   6.210 +	style="font-weight: normal;">3.1</td>
   6.211 +<td colspan="1" rowspan="1" width="598px" class="whs10">
   6.212 +<p class="whs11">Updated to support ispLEVER 7.1.</p>
   6.213 +<p class="whs11">Added static predictor to improve the behavior 
   6.214 + of branches.</p>
   6.215 +<p class="whs11">Added support for optionally mapping the register 
   6.216 + file to EBRs (on-chip memory).</p>
   6.217 +<p class="whs11">Added support for selecting between distributed 
   6.218 + RAM and EBRs (pseudo-dual port or true-dual port) for instruction and 
   6.219 + data caches.</td></tr>
   6.220 +
   6.221 +<tr valign="top" class="whs6">
   6.222 +<td colspan="1" rowspan="1" width="93px" class="whs9">
   6.223 +<p class=Table
   6.224 +	style="font-weight: normal;"><span style="font-weight: normal;">3.0 
   6.225 + (7.0 SP2)</span></td>
   6.226 +<td colspan="1" rowspan="1" width="598px" class="whs10">
   6.227 +<p class="whs11">Updated to support ispLEVER 7.0 SP2.</p>
   6.228 +<p class="whs11">Fixed incorrect handling of data cache miss 
   6.229 + in the presence of an instruction cache miss.</td></tr>
   6.230 +
   6.231 +<tr valign="top" class="whs6">
   6.232 +<td colspan="1" rowspan="1" width="93px" class="whs9">
   6.233 +<p class="whs11">1.0</td>
   6.234 +<td colspan="1" rowspan="1" width="598px" class="whs10">
   6.235 +<p class="whs11">Initial version.</td></tr>
   6.236 +<script language='JavaScript'><!--
   6.237 +if ((navigator.appName == "Netscape") && (parseInt(navigator.appVersion) == 4)) document.write("</table></table><table>");
   6.238 +//--></script>
   6.239 +</table>
   6.240 +
   6.241 +&nbsp; 
   6.242 +
   6.243 +<h2>Dialog Box Parameters &#8211; 
   6.244 + General Tab</h2>
   6.245 +
   6.246 +<table x-use-null-cells cellspacing="0" class="whs12">
   6.247 +<col class="whs13">
   6.248 +<col class="whs14">
   6.249 +
   6.250 +<tr valign="top" class="whs15">
   6.251 +<td bgcolor="#DEE8F4" width="167px" class="whs16">
   6.252 +<p class=Table
   6.253 +	style="font-weight: bold;">Parameter</td>
   6.254 +<td bgcolor="#DEE8F4" width="524px" class="whs17">
   6.255 +<p class=Table
   6.256 +	style="font-weight: bold;">Description</td></tr>
   6.257 +
   6.258 +<tr valign="top" class="whs15">
   6.259 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   6.260 +<p class=Table
   6.261 +	style="font-weight: normal;">Instance Name</td>
   6.262 +<td colspan="1" rowspan="1" width="524px" class="whs19">
   6.263 +<p class=Table
   6.264 +	style="margin-left: 14px;">Specifies the name of the LatticeMico32 
   6.265 + processor. Alphanumeric values and underscores are supported. The default 
   6.266 + is LM32.</td></tr>
   6.267 +
   6.268 +<tr valign="top" class="whs15">
   6.269 +<td colspan="2" rowspan="1" width="691px" class="whs20">
   6.270 +<p class=Table
   6.271 +	style="font-weight: bold;">Settings</td>
   6.272 +</tr>
   6.273 +
   6.274 +<tr valign="top" class="whs15">
   6.275 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   6.276 +<p class=Table>Use EBRs for Register File</td>
   6.277 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   6.278 +<p class=Table>Uses embedded block RAMS for the register file.</td></tr>
   6.279 +
   6.280 +<tr valign="top" class="whs15">
   6.281 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   6.282 +<p class=Table>Enable Divide</td>
   6.283 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   6.284 +<p class=Table>Enables the divide and modulus instructions (<span style="font-family: Verdana, sans-serif;">divu, 
   6.285 + modu</span>).</td></tr>
   6.286 +
   6.287 +<tr valign="top" class="whs15">
   6.288 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   6.289 +<p class=Table>Enable Sign Extend</td>
   6.290 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   6.291 +<p class=Table>Enables the sign-extension instructions (<span style="font-family: Verdana, sans-serif;">sextb, 
   6.292 + sexth</span><span style="font-family: Arial, sans-serif;">)</span>.</td></tr>
   6.293 +
   6.294 +<tr valign="top" class="whs15">
   6.295 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   6.296 +<p class=Table>Location of Exception Handlers</td>
   6.297 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   6.298 +<p class=Table>Specifies the default value for the vector table. This can 
   6.299 + be changed by updating the EBA control register or status register.</p>
   6.300 +<p class=Table>This address must be aligned to a 256-byte boundary, since 
   6.301 + the hardware ignores the least-significant byte. Unpredictable behavior 
   6.302 + occurs when the exception base address and the exception vectors are not 
   6.303 + aligned on a 256-byte boundary.</td></tr>
   6.304 +
   6.305 +<tr valign="top" class="whs15">
   6.306 +<td colspan="2" rowspan="1" width="691px" class="whs20">
   6.307 +<p class=Table
   6.308 +	style="font-weight: bold;">Multiplier Settings</td>
   6.309 +</tr>
   6.310 +
   6.311 +<tr valign="top" class="whs15">
   6.312 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   6.313 +<p class=Table>Enable Multiplier</td>
   6.314 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   6.315 +<p class=Table>Enables the multiply instructions (<span style="font-family: Verdana, sans-serif;">mul, 
   6.316 + muli)</span>.</td></tr>
   6.317 +
   6.318 +<tr valign="top" class="whs15">
   6.319 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   6.320 +<p class=Table>Enable Pipelined Multiplier (DSP Block if available)</td>
   6.321 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   6.322 +<p class=Table>Enables the multiplier using the DSP block, if available.</td></tr>
   6.323 +
   6.324 +<tr valign="top" class="whs15">
   6.325 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   6.326 +<p class=Table>Enable Multicycle (LUT-based, 32 cycles) Multiplier</td>
   6.327 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   6.328 +<p class=Table>Enables the multiplier using LUTs.</td></tr>
   6.329 +
   6.330 +<tr valign="top" class="whs15">
   6.331 +<td colspan="2" rowspan="1" width="691px" class="whs20">
   6.332 +<p class=Table
   6.333 +	style="font-weight: bold;">Instruction Cache</td>
   6.334 +</tr>
   6.335 +
   6.336 +<tr valign="top" class="whs15">
   6.337 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   6.338 +<p class=Table>Instruction Cache Enabled</td>
   6.339 +<td colspan="1" rowspan="1" width="524px" class="whs19">
   6.340 +<p class=Table
   6.341 +	style="margin-left: 14px;">Determines whether an instruction cache 
   6.342 + is implemented.</td></tr>
   6.343 +
   6.344 +<tr valign="top" class="whs15">
   6.345 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   6.346 +<p class=Table>Number of Sets</td>
   6.347 +<td colspan="1" rowspan="1" width="524px" class="whs19">
   6.348 +<p class=Table
   6.349 +	style="margin-left: 14px;">Specifies the number of sets in the instruction 
   6.350 + cache. Supported values are 128, 256, 512, 1024.</td></tr>
   6.351 +
   6.352 +<tr valign="top" class="whs15">
   6.353 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   6.354 +<p class=Table>Set Associativity</td>
   6.355 +<td colspan="1" rowspan="1" width="524px" class="whs19">
   6.356 +<p class=Table
   6.357 +	style="margin-left: 14px;">Specifies the associativity of the instruction 
   6.358 + cache. Supported values are 1, 2.</td></tr>
   6.359 +
   6.360 +<tr valign="top" class="whs15">
   6.361 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   6.362 +<p class=Table>Bytes/Cache Line</td>
   6.363 +<td colspan="1" rowspan="1" width="524px" class="whs19">
   6.364 +<p class=Table
   6.365 +	style="margin-left: 15px;">Specifies the number of bytes per instruction 
   6.366 + cache line. Supported values are 4, 8, 16.</td></tr>
   6.367 +
   6.368 +<tr valign="top" class="whs15">
   6.369 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   6.370 +<p class=Table>Memory Type</td>
   6.371 +<td colspan="1" rowspan="1" width="524px" class="whs19">
   6.372 +<p class=Table
   6.373 +	style="margin-left: 15px;">Determines the FPGA resource to be used 
   6.374 + to implement the instruction cache. The decision can be left to the synthesis 
   6.375 + tool (Auto), or you can select from the following options:</p>
   6.376 +<ul type="disc" class="whs22">
   6.377 +	
   6.378 +	<li class=kadov-p-CBullet><p class=Bullet>Auto &#8211; 
   6.379 + Leaves the implementation of the instruction cache to the synthesis tool.</p></li>
   6.380 +	
   6.381 +	<li class=kadov-p-CBullet><p class=Bullet>Distributed RAM &#8211; 
   6.382 + Implements the instruction cache as distributed RAM.</p></li>
   6.383 +	
   6.384 +	<li class=kadov-p-CBullet><p class=Bullet>Dual-Port EBR &#8211; 
   6.385 + Implements the instruction cache as dual-port EBR (two read/write ports).</p></li>
   6.386 +	
   6.387 +	<li class=kadov-p-CBullet><p class=Bullet>Pseudo Dual-Port EBR &#8211; Implements 
   6.388 + the instruction cache as pseudo-dual-port EBR (one read port and one write 
   6.389 + port). </p></li>
   6.390 +</ul></td></tr>
   6.391 +
   6.392 +<tr valign="top" class="whs15">
   6.393 +<td colspan="2" rowspan="1" width="691px" class="whs20">
   6.394 +<p class=Table
   6.395 +	style="font-weight: bold;">Debug Setting</td>
   6.396 +</tr>
   6.397 +
   6.398 +<tr valign="top" class="whs15">
   6.399 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   6.400 +<p class=Table>Enable Debug Interface</td>
   6.401 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   6.402 +<p class=Table>Includes the debugger stub in the CPU, which is required 
   6.403 + for debugging.</td></tr>
   6.404 +
   6.405 +<tr valign="top" class="whs15">
   6.406 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   6.407 +<p class=Table># of H/W Watchpoint Registers</td>
   6.408 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   6.409 +<p class=Table
   6.410 +	style="font-weight: normal;">Specifies the number of hardware watchpoint 
   6.411 + registers to be used in the debugging process.</td></tr>
   6.412 +
   6.413 +<tr valign="top" class="whs15">
   6.414 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   6.415 +<p class=Table>Enable Debugging Code in Flash or ROM</td>
   6.416 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   6.417 +<p class=Table
   6.418 +	style="font-weight: normal;">Enables you to set hardware breakpoints 
   6.419 + in read-only memory.</td></tr>
   6.420 +
   6.421 +<tr valign="top" class="whs15">
   6.422 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   6.423 +<p class=Table># of H/W Breakpoint Registers</td>
   6.424 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   6.425 +<p class=Table>Specifies the number of hardware breakpoint registers to 
   6.426 + be used in the debugging process.</td></tr>
   6.427 +
   6.428 +<tr valign="top" class="whs15">
   6.429 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   6.430 +<p class=Table>Enable PC Trace</td>
   6.431 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   6.432 +<p class=Table>Enables the Program Counter Trace feature, which enables 
   6.433 + you to run the program trace during debug to find items in your C or C++ 
   6.434 + Code during debug, such as breakpoints and exceptions. Refer to <span 
   6.435 + style="font-weight: bold;"><B>Help &gt; Help Contents &gt; C/C++ SPE</B></span> 
   6.436 + and <span style="font-weight: bold;"><B>Debug &gt; Concepts &gt; Program 
   6.437 + Counter Trace</B></span> for more information on Program Counter Trace.</td></tr>
   6.438 +
   6.439 +<tr valign="top" class="whs15">
   6.440 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   6.441 +<p class=Table>Trace Depth</td>
   6.442 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   6.443 +<p class=Table>Enables you to specify the depth of the Program Counter 
   6.444 + Trace buffer. Refer to <span style="font-weight: bold;"><B>Help &gt; Help 
   6.445 + Contents &gt; C/C++ SPE</B></span> and <span style="font-weight: bold;"><B>Debug 
   6.446 + &gt; Concepts &gt; Program Counter Trace</B></span> for more information on 
   6.447 + Program Counter Trace.</td></tr>
   6.448 +
   6.449 +<tr valign="top" class="whs15">
   6.450 +<td colspan="2" rowspan="1" width="691px" class="whs20">
   6.451 +<p class=Table
   6.452 +	style="font-weight: bold;">Shifter Settings</td>
   6.453 +</tr>
   6.454 +
   6.455 +<tr valign="top" class="whs15">
   6.456 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   6.457 +<p class=Table>Enable Piplined Barrel Shifter</td>
   6.458 +<td colspan="1" rowspan="1" width="524px" class="whs19">
   6.459 +<p>Enables the barrel shifter to be pipelined. The barrel shifter is implemented 
   6.460 + to perform a shift operation in three cycles.</td></tr>
   6.461 +
   6.462 +<tr valign="top" class="whs15">
   6.463 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   6.464 +<p class=Table>Enable Multicycle Barrel Shifter (up to 32 cycles)</td>
   6.465 +<td colspan="1" rowspan="1" width="524px" class="whs19">
   6.466 +<p>Enables multi-cycle shift operation for the barrel shifter. The barrel 
   6.467 + shifter is implemented to shift one bit per cycle and take thirty-two 
   6.468 + cycles to complete.</td></tr>
   6.469 +
   6.470 +<tr valign="top" class="whs15">
   6.471 +<td colspan="2" rowspan="1" width="691px" class="whs20">
   6.472 +<p class=Table><span style="font-weight: bold;"><B>Data Cache</B></span></td>
   6.473 +</tr>
   6.474 +
   6.475 +<tr valign="top" class="whs15">
   6.476 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   6.477 +<p class=Table>Data Cache Enabled</td>
   6.478 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   6.479 +<p class=Table>Determines whether a data cache is implemented.</td></tr>
   6.480 +
   6.481 +<tr valign="top" class="whs15">
   6.482 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   6.483 +<p class=Table>Number of Sets</td>
   6.484 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   6.485 +<p class=Table>Specifies the number of sets in the data cache. Supported 
   6.486 + values are 128, 256, 512, 1024.</td></tr>
   6.487 +
   6.488 +<tr valign="top" class="whs15">
   6.489 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   6.490 +<p class=Table>Set Associativity</td>
   6.491 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   6.492 +<p class=Table>Specifies the associativity of the data cache. Supported 
   6.493 + values are 1, 2.</td></tr>
   6.494 +
   6.495 +<tr valign="top" class="whs15">
   6.496 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   6.497 +<p class=Table>Bytes/Cache Line</td>
   6.498 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   6.499 +<p class=Table>Specifies the number of bytes per data cache line. Supported 
   6.500 + values are 4, 8, 16.</td></tr>
   6.501 +
   6.502 +<tr valign="top" class="whs15">
   6.503 +<td colspan="1" rowspan="1" width="167px" class="whs23">
   6.504 +<p class=Table>Memory Type</td>
   6.505 +<td colspan="1" rowspan="1" width="524px" class="whs24">
   6.506 +<p class=Table>Determines the FPGA resource to be used to implement the 
   6.507 + data cache. The decision can be left to the synthesis tool (Auto), or 
   6.508 + you can select from the following options:</p>
   6.509 +<ul>
   6.510 +	
   6.511 +	<li class=kadov-p-CBullet><p class=Bullet>Auto &#8211; 
   6.512 + Leaves the implementation of the data cache to the synthesis tool.</p></li>
   6.513 +	
   6.514 +	<li class=kadov-p-CBullet><p class=Bullet>Distributed RAM &#8211; 
   6.515 + Implements the data cache as distributed RAM.</p></li>
   6.516 +	
   6.517 +	<li class=kadov-p-CBullet><p class=Bullet>Dual-Port EBR &#8211; 
   6.518 + Implements the data cache as dual-port EBR (two read/write ports).</p></li>
   6.519 +</ul></td></tr>
   6.520 +</table>
   6.521 +
   6.522 +<p>&nbsp;</p>
   6.523 +
   6.524 +<h2>Dialog Box Parameters &#8211; 
   6.525 + Inline Memory Tab</h2>
   6.526 +
   6.527 +<table x-use-null-cells cellspacing="0" class="whs12">
   6.528 +<col class="whs13">
   6.529 +<col class="whs14">
   6.530 +
   6.531 +<tr valign="top" class="whs15">
   6.532 +<td bgcolor="#DEE8F4" width="167px" class="whs25">
   6.533 +<p class=Table
   6.534 +	style="font-weight: bold;">Parameter</td>
   6.535 +<td bgcolor="#DEE8F4" width="524px" class="whs26">
   6.536 +<p class=Table
   6.537 +	style="font-weight: bold;">Description</td></tr>
   6.538 +
   6.539 +<tr valign="top" class="whs15">
   6.540 +<td rowspan="1" colspan="2" width="691px" class="whs27">
   6.541 +<p class=Table
   6.542 +	style="font-weight: bold;">Instruction Inline Memory</td>
   6.543 +</tr>
   6.544 +
   6.545 +<tr valign="top" class="whs15">
   6.546 +<td width="167px" class="whs28">
   6.547 +<p class=Table>Enable</td>
   6.548 +<td width="524px" class="whs29">
   6.549 +<p class=Table>Enables the instruction inline memory</td></tr>
   6.550 +
   6.551 +<tr valign="top" class="whs15">
   6.552 +<td width="167px" class="whs28">
   6.553 +<p class=Table>Instance Name</td>
   6.554 +<td width="524px" class="whs29">
   6.555 +<p class=Table>Specifics the name of the instruction inline memory. Alphanumeric 
   6.556 + values and underscores are supported. The default is Instruction_IM.</td></tr>
   6.557 +
   6.558 +<tr valign="top" class="whs15">
   6.559 +<td width="167px" class="whs28">
   6.560 +<p class=Table>Base Address</td>
   6.561 +<td width="524px" class="whs29">
   6.562 +<p class=Table>Specifies the base address for the instruction inline memory. 
   6.563 + The default is 0x10000000.</td></tr>
   6.564 +
   6.565 +<tr valign="top" class="whs15">
   6.566 +<td width="167px" class="whs28">
   6.567 +<p class=Table>Size of Memory in Bytes</td>
   6.568 +<td width="524px" class="whs29">
   6.569 +<p class=Table>Specifies the size of the instruction inline memory.</td></tr>
   6.570 +
   6.571 +<tr valign="top" class="whs15">
   6.572 +<td rowspan="1" colspan="2" width="691px" class="whs27">
   6.573 +<p class=Table><span style="font-weight: bold;"><B>Memory File</B></span></td>
   6.574 +</tr>
   6.575 +
   6.576 +<tr valign="top" class="whs15">
   6.577 +<td width="167px" class="whs28">
   6.578 +<p class=Table>Initialization File Name</td>
   6.579 +<td width="524px" class="whs29">
   6.580 +<p class=Table>Specifies the name of the memory initialization file for 
   6.581 + instruction inline memory.</td></tr>
   6.582 +
   6.583 +<tr valign="top" class="whs15">
   6.584 +<td width="167px" class="whs28">
   6.585 +<p class=Table>File Format</td>
   6.586 +<td width="524px" class="whs29">
   6.587 +<p class=Table>Specifies the format of the memory initialization file: 
   6.588 + hex or binary.</td></tr>
   6.589 +
   6.590 +<tr valign="top" class="whs15">
   6.591 +<td rowspan="1" colspan="2" width="691px" class="whs27">
   6.592 +<p class=Table
   6.593 +	style="font-weight: bold;">Data Inline Memory</td>
   6.594 +</tr>
   6.595 +
   6.596 +<tr valign="top" class="whs15">
   6.597 +<td width="167px" class="whs28">
   6.598 +<p class=Table>Enabled</td>
   6.599 +<td width="524px" class="whs29">
   6.600 +<p class=Table>Enables the data inline memory.</td></tr>
   6.601 +
   6.602 +<tr valign="top" class="whs15">
   6.603 +<td width="167px" class="whs28">
   6.604 +<p class=Table>Instance Name</td>
   6.605 +<td width="524px" class="whs29">
   6.606 +<p class=Table>Specifies the name of the data inline memory. Alphanumeric 
   6.607 + values and underscores are supported. The default is Data_IM.</td></tr>
   6.608 +
   6.609 +<tr valign="top" class="whs15">
   6.610 +<td width="167px" class="whs28">
   6.611 +<p class=Table>Base Address</td>
   6.612 +<td width="524px" class="whs29">
   6.613 +<p class=Table>Specifies the base address for the data inline memory. The 
   6.614 + default is 0x20000000.</td></tr>
   6.615 +
   6.616 +<tr valign="top" class="whs15">
   6.617 +<td width="167px" class="whs28">
   6.618 +<p class=Table>Size of Memory in Bytes</td>
   6.619 +<td width="524px" class="whs29">
   6.620 +<p class=Table>Specifies the size of the data inline memory.</td></tr>
   6.621 +
   6.622 +<tr valign="top" class="whs15">
   6.623 +<td colspan="2" rowspan="1" width="691px" class="whs27">
   6.624 +<p class=Table
   6.625 +	style="font-weight: bold;">Memory File</td>
   6.626 +</tr>
   6.627 +
   6.628 +<tr valign="top" class="whs15">
   6.629 +<td colspan="1" rowspan="1" width="167px" class="whs28">
   6.630 +<p class=Table>Initialization File Name</td>
   6.631 +<td colspan="1" rowspan="1" width="524px" class="whs29">
   6.632 +<p class=Table>Specifies the name of the memory initialization file for 
   6.633 + data inline memory.</td></tr>
   6.634 +
   6.635 +<tr valign="top" class="whs15">
   6.636 +<td colspan="1" rowspan="1" width="167px" class="whs30">
   6.637 +<p class=Table>File Format</td>
   6.638 +<td colspan="1" rowspan="1" width="524px" class="whs31">
   6.639 +<p class=Table>Specifies the format of the memory initialization file: 
   6.640 + hex or binary.</td></tr>
   6.641 +</table>
   6.642 +
   6.643 +<p>&nbsp;</p>
   6.644 +
   6.645 +<p>For the revision history of the component RTL files, refer to the header 
   6.646 + of each component Verilog source file. </p>
   6.647 +
   6.648 +<p><span style="font-weight: bold;"><B>Note</B></span>: If the processor manual 
   6.649 + fails to open, click <img src="qm_icon.jpg" x-maintain-ratio="TRUE" width="14px" height="16px" border="0" class="img_whs32"> on the Available Components toolbar, 
   6.650 + and then click the note button.</p>
   6.651 +
   6.652 +<script type="text/javascript" language="JavaScript">
   6.653 +<!--
   6.654 + if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape'))
   6.655 +  document.write("<div id='tooltip' class='WebHelpPopupMenu'></div>");
   6.656 +//-->
   6.657 +</script><script type="text/javascript" language="javascript1.2">
   6.658 +<!--
   6.659 +if (window.writeIntopicBar)
   6.660 +	writeIntopicBar(0);
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   6.663 +</body>
   6.664 +</html>

    12.1 --- a/document/lever40.css	Sun Mar 06 21:17:31 2011 +0000
    12.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    12.3 @@ -1,245 +0,0 @@
    12.4 -H1 { 
    12.5 -    font-weight:bold; 
    12.6 -    border-top-style:none; 
    12.7 -    font-family:Arial, helvetica, sans-serif; 
    12.8 -    color:#ea6d23; 
    12.9 -    margin-left:15px; 
   12.10 -    margin-top:3px; 
   12.11 -    margin-bottom:10px; 
   12.12 -    border-bottom-style:Solid; 
   12.13 -    border-bottom-width:2px; 
   12.14 -    border-bottom-color:#dbdbdb; 
   12.15 -    margin-right:0px; 
   12.16 -    line-height:Normal; 
   12.17 -    font-size:1em;  }
   12.18 -LI.kadov-H1 { 
   12.19 -             font-weight:bold; 
   12.20 -             font-family:Arial, helvetica, sans-serif; 
   12.21 -             color:#ea6d23; 
   12.22 -             line-height:Normal; 
   12.23 -             font-size:1em;  }
   12.24 -H2 { 
   12.25 -    font-weight:bold; 
   12.26 -    x-text-underline:Off; 
   12.27 -    border-top-style:none; 
   12.28 -    border-bottom-style:none; 
   12.29 -    font-family:Arial, helvetica, sans-serif; 
   12.30 -    color:#ea6d23; 
   12.31 -    margin-left:15px; 
   12.32 -    margin-top:12px; 
   12.33 -    margin-bottom:5px; 
   12.34 -    font-size:0.84em; 
   12.35 -    margin-right:0px; 
   12.36 -    text-decoration:none;  }
   12.37 -LI.kadov-H2 { 
   12.38 -             font-weight:bold; 
   12.39 -             x-text-underline:Off; 
   12.40 -             font-family:Arial, helvetica, sans-serif; 
   12.41 -             color:#ea6d23; 
   12.42 -             font-size:0.84em; 
   12.43 -             text-decoration:none;  }
   12.44 -P { 
   12.45 -   margin-top:0pt; 
   12.46 -   font-family:Verdana, Arial, helvetica, sans-serif; 
   12.47 -   color:#323232; 
   12.48 -   font-size:71%; 
   12.49 -   margin-bottom:8px; 
   12.50 -   line-height:1.4em; 
   12.51 -   margin-right:0px; 
   12.52 -   margin-left:15px;  }
   12.53 -LI.kadov-P { 
   12.54 -            font-family:Verdana, Arial, helvetica, sans-serif; 
   12.55 -            color:#323232; 
   12.56 -            font-size:71%; 
   12.57 -            line-height:1.4em;  }
   12.58 -p.Step { 
   12.59 -        list-style:decimal; 
   12.60 -        margin-left:0px; 
   12.61 -        font-size:100%; 
   12.62 -        margin-bottom:7px; 
   12.63 -        margin-top:0px;  }
   12.64 -LI.kadov-p-CStep { 
   12.65 -                  list-style:decimal; 
   12.66 -                  font-size:100%;  }
   12.67 -P.Bullet { 
   12.68 -          font-size:100%; 
   12.69 -          list-style:url("image/top-bullet.gif"); 
   12.70 -          margin-bottom:7px; 
   12.71 -          margin-left:0px; 
   12.72 -          margin-top:0px;  }
   12.73 -LI.kadov-P-CBullet { 
   12.74 -                    font-size:100%; 
   12.75 -                    list-style:url("image/top-bullet.gif");  }
   12.76 -P.NormalIndent { 
   12.77 -                margin-left:40px;  }
   12.78 -LI.kadov-P-CNormalIndent {  }
   12.79 -P.BulletIndent { 
   12.80 -                margin-bottom:2px; 
   12.81 -                font-size:100%; 
   12.82 -                margin-left:15pt; 
   12.83 -                list-style:url("image/secondary-bullet.gif");  }
   12.84 -LI.kadov-P-CBulletIndent { 
   12.85 -                          font-size:100%; 
   12.86 -                          list-style:url("image/secondary-bullet.gif");  }
   12.87 -P.Procedure { 
   12.88 -             font-style:italic; 
   12.89 -             font-weight:normal; 
   12.90 -             x-next-class:Step; 
   12.91 -             x-next-type:p; 
   12.92 -             margin-top:12pt; 
   12.93 -             margin-bottom:5px;  }
   12.94 -LI.kadov-P-CProcedure { 
   12.95 -                       font-style:italic; 
   12.96 -                       font-weight:normal;  }
   12.97 -P.Note { 
   12.98 -        margin-top:8pt; 
   12.99 -        margin-bottom:8pt; 
  12.100 -        border-top-style:Solid; 
  12.101 -        border-bottom-style:Solid; 
  12.102 -        padding-top:4px; 
  12.103 -        padding-bottom:4px; 
  12.104 -        border-top-width:1px; 
  12.105 -        border-bottom-width:1px; 
  12.106 -        background-color:#ffffff;  }
  12.107 -LI.kadov-P-CNote {  }
  12.108 -P.NoteIndent { 
  12.109 -              margin-top:8pt; 
  12.110 -              margin-bottom:8pt; 
  12.111 -              border-top-style:Solid; 
  12.112 -              border-bottom-style:Solid; 
  12.113 -              padding-top:4px; 
  12.114 -              padding-bottom:4px; 
  12.115 -              border-top-width:1px; 
  12.116 -              border-bottom-width:1px; 
  12.117 -              background-color:#ffffff; 
  12.118 -              margin-left:40px;  }
  12.119 -LI.kadov-P-CNoteIndent {  }
  12.120 -P.Table { 
  12.121 -         margin-top:4px; 
  12.122 -         margin-bottom:4px; 
  12.123 -         margin-right:4px; 
  12.124 -         margin-left:4px;  }
  12.125 -LI.kadov-P-CTable {  }
  12.126 -P.Code { 
  12.127 -        margin-bottom:0px; 
  12.128 -        line-height:Normal; 
  12.129 -        font-family:"Courier New"  , Courier, monospace;  }
  12.130 -LI.kadov-P-CCode { 
  12.131 -                  line-height:Normal; 
  12.132 -                  font-family:"Courier New"  , Courier, monospace;  }
  12.133 -P.StepBulletFirst { 
  12.134 -                   font-size:100%; 
  12.135 -                   margin-left:15px; 
  12.136 -                   margin-bottom:2px; 
  12.137 -                   list-style:url("image/secondary-bullet.gif");  }
  12.138 -LI.kadov-P-CStepBulletFirst { 
  12.139 -                             font-size:100%; 
  12.140 -                             list-style:url("image/secondary-bullet.gif");  }
  12.141 -BODY { 
  12.142 -      background-color:#ffffff; 
  12.143 -      color:#000080; 
  12.144 -      font-family:Arial, sans-serif;  }
  12.145 -P.SeeAlso { 
  12.146 -           font-weight:bold; 
  12.147 -           font-style:normal; 
  12.148 -           x-next-type:P; 
  12.149 -           color:#ea6d23; 
  12.150 -           font-family:Arial, helvetica, sans-serif; 
  12.151 -           margin-left:15px; 
  12.152 -           margin-top:12px; 
  12.153 -           margin-bottom:5px; 
  12.154 -           font-size:0.84em;  }
  12.155 -LI.kadov-P-CSeeAlso { 
  12.156 -                     font-weight:bold; 
  12.157 -                     font-style:normal; 
  12.158 -                     color:#ea6d23; 
  12.159 -                     font-family:Arial, helvetica, sans-serif; 
  12.160 -                     font-size:0.84em;  }
  12.161 -A:link { 
  12.162 -        font-weight:bold; 
  12.163 -        font-style:normal; 
  12.164 -        color:#003a98; 
  12.165 -        x-text-underline:Off; 
  12.166 -        text-decoration:none;  }
  12.167 -A:hover { 
  12.168 -         x-text-underline:Normal; 
  12.169 -         color:#59add3; 
  12.170 -         text-decoration:underline;  }
  12.171 -A:active { 
  12.172 -          color:#59add3;  }
  12.173 -A:visited { 
  12.174 -           x-text-underline:Off; 
  12.175 -           color:#385689; 
  12.176 -           font-weight:bold; 
  12.177 -           font-style:normal; 
  12.178 -           text-decoration:none;  }
  12.179 -H1.Home { 
  12.180 -         x-next-type:P; 
  12.181 -         border-top-style:none; 
  12.182 -         border-bottom-style:none; 
  12.183 -         x-text-underline:Off; 
  12.184 -         font-size:15pt; 
  12.185 -         color:#ea6d23; 
  12.186 -         text-decoration:none;  }
  12.187 -LI.kadov-H1-CHome { 
  12.188 -                   x-text-underline:Off; 
  12.189 -                   font-size:15pt; 
  12.190 -                   color:#ea6d23; 
  12.191 -                   text-decoration:none;  }
  12.192 -H3 { 
  12.193 -    margin-left:15px; 
  12.194 -    margin-top:12px; 
  12.195 -    margin-bottom:5px; 
  12.196 -    color:#323232; 
  12.197 -    font-size:71%; 
  12.198 -    font-family:Verdana, Arial, helvetica, sans-serif; 
  12.199 -    margin-right:0px;  }
  12.200 -LI.kadov-H3 { 
  12.201 -             color:#323232; 
  12.202 -             font-size:71%; 
  12.203 -             font-family:Verdana, Arial, helvetica, sans-serif;  }
  12.204 -P.Title { 
  12.205 -         font-weight:bold; 
  12.206 -         font-style:normal; 
  12.207 -         x-next-type:P; 
  12.208 -         font-family:Arial, helvetica, sans-serif; 
  12.209 -         color:#ea6d23; 
  12.210 -         margin-bottom:10px; 
  12.211 -         font-size:1.4em; 
  12.212 -         line-height:Normal; 
  12.213 -         border-bottom-style:Solid; 
  12.214 -         border-bottom-width:2px; 
  12.215 -         border-bottom-color:#dbdbdb; 
  12.216 -         margin-top:0px;  }
  12.217 -LI.kadov-P-CTitle { 
  12.218 -                   font-weight:bold; 
  12.219 -                   font-style:normal; 
  12.220 -                   font-family:Arial, helvetica, sans-serif; 
  12.221 -                   color:#ea6d23; 
  12.222 -                   font-size:1.4em; 
  12.223 -                   line-height:Normal;  }
  12.224 -P.Supra { 
  12.225 -         font-weight:bold; 
  12.226 -         font-style:normal; 
  12.227 -         margin-bottom:6pt; 
  12.228 -         font-family:Arial, helvetica, sans-serif;  }
  12.229 -LI.kadov-P-CSupra { 
  12.230 -                   font-weight:bold; 
  12.231 -                   font-style:normal; 
  12.232 -                   font-family:Arial, helvetica, sans-serif;  }
  12.233 -OL { 
  12.234 -    font-size:71%; 
  12.235 -    font-family:Verdana, Arial, helvetica, sans-serif; 
  12.236 -    color:#323232;  }
  12.237 -UL { 
  12.238 -    font-size:71%; 
  12.239 -    font-family:Verdana, Arial, helvetica, sans-serif; 
  12.240 -    color:#323232;  }
  12.241 -P.CodeIndent { 
  12.242 -              font-family:"Courier New"  , Courier, monospace; 
  12.243 -              margin-left:40px; 
  12.244 -              margin-bottom:0px; 
  12.245 -              line-height:Normal;  }
  12.246 -LI.kadov-P-CCodeIndent { 
  12.247 -                        font-family:"Courier New"  , Courier, monospace; 
  12.248 -                        line-height:Normal;  }

    13.1 --- a/document/lever40_ns.css	Sun Mar 06 21:17:31 2011 +0000
    13.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    13.3 @@ -1,248 +0,0 @@
    13.4 -H1 { 
    13.5 -    font-weight:bold; 
    13.6 -    border-top-style:none; 
    13.7 -    font-family:Arial, helvetica, sans-serif; 
    13.8 -    color:#ea6d23; 
    13.9 -    margin-left:15px; 
   13.10 -    margin-top:3px; 
   13.11 -    margin-bottom:10px; 
   13.12 -    border-bottom-style:Solid; 
   13.13 -    border-bottom-width:2px; 
   13.14 -    border-bottom-color:#dbdbdb; 
   13.15 -    margin-right:1pt; 
   13.16 -    line-height:Normal; 
   13.17 -    font-size:1em;  }
   13.18 -LI.kadov-H1 { 
   13.19 -             font-weight:bold; 
   13.20 -             font-family:Arial, helvetica, sans-serif; 
   13.21 -             color:#ea6d23; 
   13.22 -             line-height:Normal; 
   13.23 -             font-size:1em;  }
   13.24 -H2 { 
   13.25 -    font-weight:bold; 
   13.26 -    x-text-underline:Off; 
   13.27 -    border-top-style:none; 
   13.28 -    border-bottom-style:none; 
   13.29 -    font-family:Arial, helvetica, sans-serif; 
   13.30 -    color:#ea6d23; 
   13.31 -    margin-left:15px; 
   13.32 -    margin-top:12px; 
   13.33 -    margin-bottom:5px; 
   13.34 -    font-size:0.84em; 
   13.35 -    margin-right:1pt; 
   13.36 -    text-decoration:none;  }
   13.37 -LI.kadov-H2 { 
   13.38 -             font-weight:bold; 
   13.39 -             x-text-underline:Off; 
   13.40 -             font-family:Arial, helvetica, sans-serif; 
   13.41 -             color:#ea6d23; 
   13.42 -             font-size:0.84em; 
   13.43 -             text-decoration:none;  }
   13.44 -P { 
   13.45 -   margin-top:1pt; 
   13.46 -   font-family:Verdana, Arial, helvetica, sans-serif; 
   13.47 -   color:#323232; 
   13.48 -   font-size:71%; 
   13.49 -   margin-bottom:8px; 
   13.50 -   line-height:1.4em; 
   13.51 -   margin-right:1pt; 
   13.52 -   margin-left:15px;  }
   13.53 -LI.kadov-P { 
   13.54 -            font-family:Verdana, Arial, helvetica, sans-serif; 
   13.55 -            color:#323232; 
   13.56 -            font-size:71%; 
   13.57 -            line-height:1.4em;  }
   13.58 -p.Step { 
   13.59 -        list-style:decimal; 
   13.60 -        margin-left:1pt; 
   13.61 -        font-size:100%; 
   13.62 -        margin-bottom:7px; 
   13.63 -        margin-top:1pt;  }
   13.64 -LI.kadov-p-CStep { 
   13.65 -                  list-style:decimal; 
   13.66 -                  font-size:100%;  }
   13.67 -P.Bullet { 
   13.68 -          font-size:100%; 
   13.69 -          margin-bottom:7px; 
   13.70 -          margin-left:1pt; 
   13.71 -          margin-top:1pt;  }
   13.72 -LI.kadov-P-CBullet { 
   13.73 -                    font-size:100%;  }
   13.74 -P.NormalIndent { 
   13.75 -                margin-left:40px;  }
   13.76 -LI.kadov-P-CNormalIndent {  }
   13.77 -P.BulletIndent { 
   13.78 -                margin-bottom:2px; 
   13.79 -                font-size:100%; 
   13.80 -                margin-left:15pt;  }
   13.81 -LI.kadov-P-CBulletIndent { 
   13.82 -                          font-size:100%;  }
   13.83 -P.Procedure { 
   13.84 -             font-style:italic; 
   13.85 -             font-weight:normal; 
   13.86 -             x-next-class:Step; 
   13.87 -             x-next-type:p; 
   13.88 -             margin-top:12pt; 
   13.89 -             margin-bottom:5px;  }
   13.90 -LI.kadov-P-CProcedure { 
   13.91 -                       font-style:italic; 
   13.92 -                       font-weight:normal;  }
   13.93 -P.Note { 
   13.94 -        margin-top:8pt; 
   13.95 -        margin-bottom:8pt; 
   13.96 -        border-top-style:Solid; 
   13.97 -        border-bottom-style:Solid; 
   13.98 -        padding-top:4px; 
   13.99 -        padding-bottom:4px; 
  13.100 -        border-top-width:1px; 
  13.101 -        border-bottom-width:1px; 
  13.102 -        background-color:#ffffff;  }
  13.103 -LI.kadov-P-CNote {  }
  13.104 -P.NoteIndent { 
  13.105 -              margin-top:8pt; 
  13.106 -              margin-bottom:8pt; 
  13.107 -              border-top-style:Solid; 
  13.108 -              border-bottom-style:Solid; 
  13.109 -              padding-top:4px; 
  13.110 -              padding-bottom:4px; 
  13.111 -              border-top-width:1px; 
  13.112 -              border-bottom-width:1px; 
  13.113 -              background-color:#ffffff; 
  13.114 -              margin-left:40px;  }
  13.115 -LI.kadov-P-CNoteIndent {  }
  13.116 -P.Table { 
  13.117 -         margin-top:4px; 
  13.118 -         margin-bottom:4px; 
  13.119 -         margin-right:4px; 
  13.120 -         margin-left:4px;  }
  13.121 -LI.kadov-P-CTable {  }
  13.122 -P.Code { 
  13.123 -        margin-bottom:1pt; 
  13.124 -        line-height:Normal; 
  13.125 -        font-family:"Courier New"     , Courier, monospace;  }
  13.126 -LI.kadov-P-CCode { 
  13.127 -                  line-height:Normal; 
  13.128 -                  font-family:"Courier New"     , Courier, monospace;  }
  13.129 -P.StepBulletFirst { 
  13.130 -                   font-size:100%; 
  13.131 -                   margin-left:15px; 
  13.132 -                   margin-bottom:2px;  }
  13.133 -LI.kadov-P-CStepBulletFirst { 
  13.134 -                             font-size:100%;  }
  13.135 -BODY { 
  13.136 -      background-color:#ffffff; 
  13.137 -      color:#000080; 
  13.138 -      font-family:Arial, sans-serif;  }
  13.139 -P.SeeAlso { 
  13.140 -           font-weight:bold; 
  13.141 -           font-style:normal; 
  13.142 -           x-next-type:P; 
  13.143 -           color:#ea6d23; 
  13.144 -           font-family:Arial, helvetica, sans-serif; 
  13.145 -           margin-left:15px; 
  13.146 -           margin-top:12px; 
  13.147 -           margin-bottom:5px; 
  13.148 -           font-size:0.84em;  }
  13.149 -LI.kadov-P-CSeeAlso { 
  13.150 -                     font-weight:bold; 
  13.151 -                     font-style:normal; 
  13.152 -                     color:#ea6d23; 
  13.153 -                     font-family:Arial, helvetica, sans-serif; 
  13.154 -                     font-size:0.84em;  }
  13.155 -A:link { 
  13.156 -        font-weight:bold; 
  13.157 -        font-style:normal; 
  13.158 -        color:#003a98; 
  13.159 -        x-text-underline:Off; 
  13.160 -        text-decoration:none;  }
  13.161 -A:hover { 
  13.162 -         x-text-underline:Normal; 
  13.163 -         color:#59add3; 
  13.164 -         text-decoration:underline;  }
  13.165 -A:active { 
  13.166 -          color:#59add3;  }
  13.167 -A:visited { 
  13.168 -           x-text-underline:Off; 
  13.169 -           color:#385689; 
  13.170 -           font-weight:bold; 
  13.171 -           font-style:normal; 
  13.172 -           text-decoration:none;  }
  13.173 -H1.Home { 
  13.174 -         x-next-type:P; 
  13.175 -         border-top-style:none; 
  13.176 -         border-bottom-style:none; 
  13.177 -         x-text-underline:Off; 
  13.178 -         font-size:15pt; 
  13.179 -         color:#ea6d23; 
  13.180 -         text-decoration:none;  }
  13.181 -LI.kadov-H1-CHome { 
  13.182 -                   x-text-underline:Off; 
  13.183 -                   font-size:15pt; 
  13.184 -                   color:#ea6d23; 
  13.185 -                   text-decoration:none;  }
  13.186 -H3 { 
  13.187 -    margin-left:15px; 
  13.188 -    margin-top:12px; 
  13.189 -    margin-bottom:5px; 
  13.190 -    color:#323232; 
  13.191 -    font-size:71%; 
  13.192 -    font-family:Verdana, Arial, helvetica, sans-serif; 
  13.193 -    margin-right:1pt; 
  13.194 -    font-weight:bold;  }
  13.195 -LI.kadov-H3 { 
  13.196 -             color:#323232; 
  13.197 -             font-size:71%; 
  13.198 -             font-family:Verdana, Arial, helvetica, sans-serif;  }
  13.199 -P.Title { 
  13.200 -         font-weight:bold; 
  13.201 -         font-style:normal; 
  13.202 -         x-next-type:P; 
  13.203 -         font-family:Arial, helvetica, sans-serif; 
  13.204 -         color:#ea6d23; 
  13.205 -         margin-bottom:10px; 
  13.206 -         font-size:1.4em; 
  13.207 -         line-height:Normal; 
  13.208 -         border-bottom-style:Solid; 
  13.209 -         border-bottom-width:2px; 
  13.210 -         border-bottom-color:#dbdbdb; 
  13.211 -         margin-top:1pt;  }
  13.212 -LI.kadov-P-CTitle { 
  13.213 -                   font-weight:bold; 
  13.214 -                   font-style:normal; 
  13.215 -                   font-family:Arial, helvetica, sans-serif; 
  13.216 -                   color:#ea6d23; 
  13.217 -                   font-size:1.4em; 
  13.218 -                   line-height:Normal;  }
  13.219 -P.Supra { 
  13.220 -         font-weight:bold; 
  13.221 -         font-style:normal; 
  13.222 -         margin-bottom:6pt; 
  13.223 -         font-family:Arial, helvetica, sans-serif;  }
  13.224 -LI.kadov-P-CSupra { 
  13.225 -                   font-weight:bold; 
  13.226 -                   font-style:normal; 
  13.227 -                   font-family:Arial, helvetica, sans-serif;  }
  13.228 -OL { 
  13.229 -    font-size:71%; 
  13.230 -    font-family:Verdana, Arial, helvetica, sans-serif; 
  13.231 -    color:#323232;  }
  13.232 -UL { 
  13.233 -    font-size:71%; 
  13.234 -    font-family:Verdana, Arial, helvetica, sans-serif; 
  13.235 -    color:#323232;  }
  13.236 -P.CodeIndent { 
  13.237 -              font-family:"Courier New"     , Courier, monospace; 
  13.238 -              margin-left:40px; 
  13.239 -              margin-bottom:1pt; 
  13.240 -              line-height:Normal;  }
  13.241 -LI.kadov-P-CCodeIndent { 
  13.242 -                        font-family:"Courier New"     , Courier, monospace; 
  13.243 -                        line-height:Normal;  }
  13.244 -ol ol { 
  13.245 -       margin-top:1px;  }
  13.246 -ol ul { 
  13.247 -       margin-top:1px;  }
  13.248 -ul ul { 
  13.249 -       margin-top:1px;  }
  13.250 -ul ol { 
  13.251 -       margin-top:1px;  }

    14.1 --- a/document/lm32.htm	Sun Mar 06 21:17:31 2011 +0000
    14.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    14.3 @@ -1,661 +0,0 @@
    14.4 -<!doctype HTML public "-//W3C//DTD HTML 4.0 Frameset//EN">
    14.5 -
    14.6 -<html>
    14.7 -
    14.8 -<head>
    14.9 -<title>LatticeMico32 processor</title>
   14.10 -<meta http-equiv="content-type" content="text/html; charset=windows-1252">
   14.11 -<meta name="generator" content="RoboHelp by eHelp Corporation www.ehelp.com">
   14.12 -<link rel="stylesheet" href="lever40_ns.css"><script type="text/javascript" language="JavaScript" title="WebHelpSplitCss">
   14.13 -<!--
   14.14 -if (navigator.appName !="Netscape")
   14.15 -{   document.write("<link rel='stylesheet' href='lever40.css'>");}
   14.16 -//-->
   14.17 -</script>
   14.18 -<style>
   14.19 -<!--
   14.20 -body { border-left-style:None; border-right-style:None; border-top-style:None; border-bottom-style:None; }
   14.21 --->
   14.22 -</style><style type="text/css">
   14.23 -<!--
   14.24 -img_whs1 { border:none; width:29px; height:31px; float:none; border-style:none; }
   14.25 -p.whs2 { font-style:italic; }
   14.26 -table.whs3 { x-cell-content-align:top; height:84px; left:0px; top:114px; width:738px; margin-left:15px; border-spacing:0px; }
   14.27 -col.whs4 { width:93px; }
   14.28 -col.whs5 { width:598px; }
   14.29 -tr.whs6 { x-cell-content-align:top; height:22px; }
   14.30 -td.whs7 { width:93px; padding-right:10px; padding-left:10px; border-left-style:Solid; border-left-color:#c0c0c0; border-top-style:Solid; border-top-color:#c0c0c0; border-right-color:#c0c0c0; border-right-style:Solid; border-bottom-color:#c0c0c0; border-bottom-style:Solid; border-right-width:1px; border-left-width:1px; border-top-width:1px; border-bottom-width:1px; background-color:#dee8f4; }
   14.31 -td.whs8 { width:598px; padding-right:10px; padding-left:10px; border-top-style:Solid; border-top-color:#c0c0c0; border-right-color:#c0c0c0; border-right-style:Solid; border-bottom-color:#c0c0c0; border-bottom-style:Solid; border-top-width:1px; border-bottom-width:1px; border-right-width:1px; background-color:#dee8f4; }
   14.32 -td.whs9 { width:93px; padding-right:10px; padding-left:10px; border-left-color:#c0c0c0; border-left-width:1px; border-left-style:Solid; border-right-color:#c0c0c0; border-right-style:Solid; border-right-width:1px; border-bottom-color:#c0c0c0; border-bottom-style:Solid; border-bottom-width:1px; }
   14.33 -td.whs10 { width:598px; padding-right:10px; padding-left:10px; border-right-color:#c0c0c0; border-right-style:Solid; border-right-width:1px; border-bottom-color:#c0c0c0; border-bottom-style:Solid; border-bottom-width:1px; }
   14.34 -p.whs11 { margin-left:4px; }
   14.35 -table.whs12 { x-cell-content-align:top; margin-left:15px; border-spacing:0px; }
   14.36 -col.whs13 { width:167px; }
   14.37 -col.whs14 { width:524px; }
   14.38 -tr.whs15 { x-cell-content-align:top; }
   14.39 -td.whs16 { width:167px; padding-right:10px; padding-left:10px; background-color:#dee8f4; border-left-color:#c0c0c0; border-top-color:#c0c0c0; border-top-style:Solid; border-bottom-color:#c0c0c0; border-bottom-width:1px; border-bottom-style:Solid; border-right-color:#c0c0c0; border-right-width:1px; border-right-style:Solid; border-left-width:1px; border-left-style:solid; border-top-width:1px; }
   14.40 -td.whs17 { width:524px; padding-right:10px; padding-left:10px; background-color:#dee8f4; border-top-style:Solid; border-top-color:#c0c0c0; border-right-style:Solid; border-right-color:#c0c0c0; border-bottom-color:#c0c0c0; border-bottom-width:1px; border-bottom-style:Solid; border-top-width:1px; border-right-width:1px; }
   14.41 -td.whs18 { width:167px; padding-right:10px; padding-left:10px; border-left-color:#c0c0c0; border-bottom-color:#c0c0c0; border-bottom-width:1px; border-bottom-style:Solid; border-right-color:#c0c0c0; border-right-width:1px; border-right-style:Solid; border-left-width:1px; border-left-style:solid; }
   14.42 -td.whs19 { width:524px; border-right-style:Solid; border-right-color:#c0c0c0; border-bottom-color:#c0c0c0; border-bottom-width:1px; border-bottom-style:Solid; border-right-width:1px; }
   14.43 -td.whs20 { width:691px; padding-right:10px; padding-left:10px; border-left-color:#c0c0c0; border-right-style:Solid; border-right-color:#c0c0c0; border-bottom-color:#c0c0c0; border-bottom-width:1px; border-bottom-style:Solid; border-left-width:1px; border-left-style:solid; border-right-width:1px; }
   14.44 -td.whs21 { width:524px; padding-right:10px; padding-left:10px; border-right-style:Solid; border-right-color:#c0c0c0; border-bottom-color:#c0c0c0; border-bottom-width:1px; border-bottom-style:Solid; border-right-width:1px; }
   14.45 -ul.whs22 { list-style:disc; }
   14.46 -td.whs23 { width:167px; padding-right:10px; padding-left:10px; border-left-color:#c0c0c0; border-bottom-color:#c0c0c0; border-bottom-style:Solid; border-right-color:#c0c0c0; border-right-width:1px; border-right-style:Solid; border-left-width:1px; border-left-style:solid; border-bottom-width:1px; }
   14.47 -td.whs24 { width:524px; padding-right:10px; padding-left:10px; border-right-style:Solid; border-right-color:#c0c0c0; border-bottom-style:Solid; border-bottom-color:#c0c0c0; border-bottom-width:1px; border-right-width:1px; }
   14.48 -td.whs25 { width:167px; padding-right:10px; padding-left:10px; background-color:#dee8f4; border-left-color:#c0c0c0; border-top-style:Solid; border-top-color:#c0c0c0; border-right-color:#c0c0c0; border-right-style:Solid; border-bottom-color:#c0c0c0; border-bottom-width:1px; border-bottom-style:Solid; border-right-width:1px; border-left-width:1px; border-left-style:Solid; border-top-width:1px; }
   14.49 -td.whs26 { width:524px; padding-right:10px; padding-left:10px; background-color:#dee8f4; border-top-style:Solid; border-top-color:#c0c0c0; border-bottom-color:#c0c0c0; border-bottom-width:1px; border-bottom-style:Solid; border-top-width:1px; border-right-color:#c0c0c0; border-right-width:1px; border-right-style:Solid; }
   14.50 -td.whs27 { width:691px; padding-right:10px; padding-left:10px; border-left-color:#c0c0c0; border-bottom-color:#c0c0c0; border-bottom-width:1px; border-bottom-style:Solid; border-left-width:1px; border-left-style:Solid; border-right-color:#c0c0c0; border-right-width:1px; border-right-style:Solid; }
   14.51 -td.whs28 { width:167px; padding-right:10px; padding-left:10px; border-left-color:#c0c0c0; border-right-color:#c0c0c0; border-right-style:Solid; border-bottom-color:#c0c0c0; border-bottom-width:1px; border-bottom-style:Solid; border-right-width:1px; border-left-width:1px; border-left-style:Solid; }
   14.52 -td.whs29 { width:524px; padding-right:10px; padding-left:10px; border-bottom-color:#c0c0c0; border-bottom-width:1px; border-bottom-style:Solid; border-right-color:#c0c0c0; border-right-width:1px; border-right-style:Solid; }
   14.53 -td.whs30 { width:167px; padding-right:10px; padding-left:10px; border-left-color:#c0c0c0; border-right-color:#c0c0c0; border-right-style:Solid; border-bottom-color:#c0c0c0; border-bottom-style:Solid; border-right-width:1px; border-left-width:1px; border-left-style:Solid; border-bottom-width:1px; }
   14.54 -td.whs31 { width:524px; padding-right:10px; padding-left:10px; border-bottom-color:#c0c0c0; border-bottom-style:Solid; border-bottom-width:1px; border-right-color:#c0c0c0; border-right-width:1px; border-right-style:Solid; }
   14.55 -img_whs32 { border:none; width:14px; height:16px; float:none; border-style:none; }
   14.56 --->
   14.57 -</style><script type="text/javascript" language="JavaScript">
   14.58 -<!--
   14.59 -function ehlp_showtip(current,e,text)
   14.60 -{
   14.61 -  if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape'))
   14.62 -  {
   14.63 -    document.tooltip.document.write("<layer bgColor='yellow' style='border:1px solid black;font-size:12px;'>"+ text + "</layer>");
   14.64 -    document.tooltip.document.close();
   14.65 -    document.tooltip.left=e.pageX+5;
   14.66 -    document.tooltip.top=e.pageY+5;
   14.67 -    document.tooltip.visibility="show";
   14.68 -  }
   14.69 -}
   14.70 -function ehlp_hidetip()
   14.71 -{
   14.72 -  document.tooltip.visibility="hidden";
   14.73 -}
   14.74 -//-->
   14.75 -</script>
   14.76 -<script type="text/javascript" language="JavaScript" title="WebHelpInlineScript">
   14.77 -<!--
   14.78 -function reDo() {
   14.79 -  if (innerWidth != origWidth || innerHeight != origHeight)
   14.80 -     location.reload();
   14.81 -}
   14.82 -if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == "Netscape")) {
   14.83 -	origWidth = innerWidth;
   14.84 -	origHeight = innerHeight;
   14.85 -	onresize = reDo;
   14.86 -}
   14.87 -onerror = null; 
   14.88 -//-->
   14.89 -</script>
   14.90 -<style type="text/css">
   14.91 -<!--
   14.92 -div.WebHelpPopupMenu { position:absolute; left:0px; top:0px; z-index:4; visibility:hidden; }
   14.93 -p.WebHelpNavBar { text-align:right; }
   14.94 --->
   14.95 -</style><script type="text/javascript" language="javascript1.2" src="whmsg.js"></script>
   14.96 -<script type="text/javascript" language="javascript" src="whver.js"></script>
   14.97 -<script type="text/javascript" language="javascript1.2" src="whproxy.js"></script>
   14.98 -<script type="text/javascript" language="javascript1.2" src="whutils.js"></script>
   14.99 -<script type="text/javascript" language="javascript1.2" src="whtopic.js"></script>
  14.100 -<script type="text/javascript" language="javascript1.2">
  14.101 -<!--
  14.102 -if (window.gbWhTopic)
  14.103 -{
  14.104 -	if (window.setRelStartPage)
  14.105 -	{
  14.106 -	addTocInfo("LM32");
  14.107 -
  14.108 -	}
  14.109 -
  14.110 -
  14.111 -	if (window.setRelStartPage)
  14.112 -	{
  14.113 -	setRelStartPage("msb_peripherals.htm");
  14.114 -
  14.115 -		autoSync(0);
  14.116 -		sendSyncInfo();
  14.117 -		sendAveInfoOut();
  14.118 -	}
  14.119 -
  14.120 -}
  14.121 -else
  14.122 -	if (window.gbIE4)
  14.123 -		document.location.reload();
  14.124 -//-->
  14.125 -</script>
  14.126 -</head>
  14.127 -<body><script type="text/javascript" language="javascript1.2">
  14.128 -<!--
  14.129 -if (window.writeIntopicBar)
  14.130 -	writeIntopicBar(4);
  14.131 -//-->
  14.132 -</script>
  14.133 -<h1>LatticeMico32 Processor &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<a title="View Reference Manual" href="lm32_archman.pdf" target="_blank" onmouseover="if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) ehlp_showtip(this,event,'View Reference Manual');" onmouseout="if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) ehlp_hidetip();"><img src="ds_icon_ast.jpg" x-maintain-ratio="TRUE" width="29px" height="31px" border="0" class="img_whs1"></a></h1>
  14.134 -
  14.135 -<p>The LatticeMico32 processor is a high-performance 32-bit microprocessor 
  14.136 - optimized for Lattice Semiconductor field-programmable gate arrays. </p>
  14.137 -
  14.138 -<p class="whs2"><span style="font-style: italic;"><I>*If the 
  14.139 - processor manual fails to open, see the note at the bottom of this page.</I></span></p>
  14.140 -
  14.141 -<h2>Revision History</h2>
  14.142 -
  14.143 -<table x-use-null-cells cellspacing="0" width="738" height="84" class="whs3">
  14.144 -<script language='JavaScript'><!--
  14.145 -if ((navigator.appName == "Netscape") && (parseInt(navigator.appVersion) == 4)) document.write("</table><table x-use-null-cells cellspacing='0' width='738' height='84' border='1' bordercolor='silver' bordercolorlight='silver' bordercolordark='silver'>");
  14.146 -//--></script>
  14.147 -<col class="whs4">
  14.148 -<col class="whs5">
  14.149 -
  14.150 -<tr valign="top" class="whs6">
  14.151 -<td bgcolor="#DEE8F4" width="93px" class="whs7">
  14.152 -<p class=Table
  14.153 -	style="font-weight: bold;">Version</td>
  14.154 -<td bgcolor="#DEE8F4" width="598px" class="whs8">
  14.155 -<p class=Table
  14.156 -	style="font-weight: bold;">Description</td></tr>
  14.157 -
  14.158 -<tr valign="top" class="whs6">
  14.159 -<td colspan="1" rowspan="1" width="93px" class="whs9">
  14.160 -<p class=Table
  14.161 -	style="font-weight: normal;">3.6</td>
  14.162 -<td colspan="1" rowspan="1" width="598px" class="whs10">
  14.163 -<p class=whs10
  14.164 -	style="margin-left: 0px;">Fixed the issue of the processor locking 
  14.165 - up when Instruction Cache is not used.</td></tr>
  14.166 -
  14.167 -<tr valign="top" class="whs6">
  14.168 -<td colspan="1" rowspan="1" width="93px" class="whs9">
  14.169 -<p class=Table
  14.170 -	style="font-weight: normal;">3.5</td>
  14.171 -<td colspan="1" rowspan="1" width="598px" class="whs10">
  14.172 -<p class=whs10
  14.173 -	style="margin-left: 0px;">Support added to allow Inline Memories to 
  14.174 - be generated as non-power-of-two, as long as they are a multiple of 1024 
  14.175 - bytes</td></tr>
  14.176 -
  14.177 -<tr valign="top" class="whs6">
  14.178 -<td colspan="1" rowspan="1" width="93px" class="whs9">
  14.179 -<p class=Table
  14.180 -	style="font-weight: normal;">3.4</td>
  14.181 -<td colspan="1" rowspan="1" width="598px" class="whs10">
  14.182 -<p class=whs10
  14.183 -	style="margin-left: 0px;">Updated to support ispLEVER 7.2 SP1.</td></tr>
  14.184 -
  14.185 -<tr valign="top" class="whs6">
  14.186 -<td colspan="1" rowspan="1" width="93px" class="whs9">
  14.187 -<p class=Table
  14.188 -	style="font-weight: normal;">3.3</td>
  14.189 -<td colspan="1" rowspan="1" width="598px" class="whs10">
  14.190 -<p class=whs10
  14.191 -	style="margin-left: 0px;">Updated to support ispLEVER 7.2.</p>
  14.192 -<p class=whs10
  14.193 -	style="margin-left: 0px;">Added Inline Memory to support on-chip memory 
  14.194 - connected through a local bus.</td></tr>
  14.195 -
  14.196 -<tr valign="top" class="whs6">
  14.197 -<td colspan="1" rowspan="1" width="93px" class="whs9">
  14.198 -<p class=Table
  14.199 -	style="font-weight: normal;">3.2</td>
  14.200 -<td colspan="1" rowspan="1" width="598px" class="whs10">
  14.201 -<p class=whs10
  14.202 -	style="margin-left: 0px;">Updated to support ispLEVER 7.1 SP1</p>
  14.203 -<p class=whs10
  14.204 -	style="margin-left: 0px;">Added Memory Type to instruction cache and 
  14.205 - data cache.</td></tr>
  14.206 -
  14.207 -<tr valign="top" class="whs6">
  14.208 -<td colspan="1" rowspan="1" width="93px" class="whs9">
  14.209 -<p class=Table
  14.210 -	style="font-weight: normal;">3.1</td>
  14.211 -<td colspan="1" rowspan="1" width="598px" class="whs10">
  14.212 -<p class="whs11">Updated to support ispLEVER 7.1.</p>
  14.213 -<p class="whs11">Added static predictor to improve the behavior 
  14.214 - of branches.</p>
  14.215 -<p class="whs11">Added support for optionally mapping the register 
  14.216 - file to EBRs (on-chip memory).</p>
  14.217 -<p class="whs11">Added support for selecting between distributed 
  14.218 - RAM and EBRs (pseudo-dual port or true-dual port) for instruction and 
  14.219 - data caches.</td></tr>
  14.220 -
  14.221 -<tr valign="top" class="whs6">
  14.222 -<td colspan="1" rowspan="1" width="93px" class="whs9">
  14.223 -<p class=Table
  14.224 -	style="font-weight: normal;"><span style="font-weight: normal;">3.0 
  14.225 - (7.0 SP2)</span></td>
  14.226 -<td colspan="1" rowspan="1" width="598px" class="whs10">
  14.227 -<p class="whs11">Updated to support ispLEVER 7.0 SP2.</p>
  14.228 -<p class="whs11">Fixed incorrect handling of data cache miss 
  14.229 - in the presence of an instruction cache miss.</td></tr>
  14.230 -
  14.231 -<tr valign="top" class="whs6">
  14.232 -<td colspan="1" rowspan="1" width="93px" class="whs9">
  14.233 -<p class="whs11">1.0</td>
  14.234 -<td colspan="1" rowspan="1" width="598px" class="whs10">
  14.235 -<p class="whs11">Initial version.</td></tr>
  14.236 -<script language='JavaScript'><!--
  14.237 -if ((navigator.appName == "Netscape") && (parseInt(navigator.appVersion) == 4)) document.write("</table></table><table>");
  14.238 -//--></script>
  14.239 -</table>
  14.240 -
  14.241 -&nbsp; 
  14.242 -
  14.243 -<h2>Dialog Box Parameters &#8211; 
  14.244 - General Tab</h2>
  14.245 -
  14.246 -<table x-use-null-cells cellspacing="0" class="whs12">
  14.247 -<col class="whs13">
  14.248 -<col class="whs14">
  14.249 -
  14.250 -<tr valign="top" class="whs15">
  14.251 -<td bgcolor="#DEE8F4" width="167px" class="whs16">
  14.252 -<p class=Table
  14.253 -	style="font-weight: bold;">Parameter</td>
  14.254 -<td bgcolor="#DEE8F4" width="524px" class="whs17">
  14.255 -<p class=Table
  14.256 -	style="font-weight: bold;">Description</td></tr>
  14.257 -
  14.258 -<tr valign="top" class="whs15">
  14.259 -<td colspan="1" rowspan="1" width="167px" class="whs18">
  14.260 -<p class=Table
  14.261 -	style="font-weight: normal;">Instance Name</td>
  14.262 -<td colspan="1" rowspan="1" width="524px" class="whs19">
  14.263 -<p class=Table
  14.264 -	style="margin-left: 14px;">Specifies the name of the LatticeMico32 
  14.265 - processor. Alphanumeric values and underscores are supported. The default 
  14.266 - is LM32.</td></tr>
  14.267 -
  14.268 -<tr valign="top" class="whs15">
  14.269 -<td colspan="2" rowspan="1" width="691px" class="whs20">
  14.270 -<p class=Table
  14.271 -	style="font-weight: bold;">Settings</td>
  14.272 -</tr>
  14.273 -
  14.274 -<tr valign="top" class="whs15">
  14.275 -<td colspan="1" rowspan="1" width="167px" class="whs18">
  14.276 -<p class=Table>Use EBRs for Register File</td>
  14.277 -<td colspan="1" rowspan="1" width="524px" class="whs21">
  14.278 -<p class=Table>Uses embedded block RAMS for the register file.</td></tr>
  14.279 -
  14.280 -<tr valign="top" class="whs15">
  14.281 -<td colspan="1" rowspan="1" width="167px" class="whs18">
  14.282 -<p class=Table>Enable Divide</td>
  14.283 -<td colspan="1" rowspan="1" width="524px" class="whs21">
  14.284 -<p class=Table>Enables the divide and modulus instructions (<span style="font-family: Verdana, sans-serif;">divu, 
  14.285 - modu</span>).</td></tr>
  14.286 -
  14.287 -<tr valign="top" class="whs15">
  14.288 -<td colspan="1" rowspan="1" width="167px" class="whs18">
  14.289 -<p class=Table>Enable Sign Extend</td>
  14.290 -<td colspan="1" rowspan="1" width="524px" class="whs21">
  14.291 -<p class=Table>Enables the sign-extension instructions (<span style="font-family: Verdana, sans-serif;">sextb, 
  14.292 - sexth</span><span style="font-family: Arial, sans-serif;">)</span>.</td></tr>
  14.293 -
  14.294 -<tr valign="top" class="whs15">
  14.295 -<td colspan="1" rowspan="1" width="167px" class="whs18">
  14.296 -<p class=Table>Location of Exception Handlers</td>
  14.297 -<td colspan="1" rowspan="1" width="524px" class="whs21">
  14.298 -<p class=Table>Specifies the default value for the vector table. This can 
  14.299 - be changed by updating the EBA control register or status register.</p>
  14.300 -<p class=Table>This address must be aligned to a 256-byte boundary, since 
  14.301 - the hardware ignores the least-significant byte. Unpredictable behavior 
  14.302 - occurs when the exception base address and the exception vectors are not 
  14.303 - aligned on a 256-byte boundary.</td></tr>
  14.304 -
  14.305 -<tr valign="top" class="whs15">
  14.306 -<td colspan="2" rowspan="1" width="691px" class="whs20">
  14.307 -<p class=Table
  14.308 -	style="font-weight: bold;">Multiplier Settings</td>
  14.309 -</tr>
  14.310 -
  14.311 -<tr valign="top" class="whs15">
  14.312 -<td colspan="1" rowspan="1" width="167px" class="whs18">
  14.313 -<p class=Table>Enable Multiplier</td>
  14.314 -<td colspan="1" rowspan="1" width="524px" class="whs21">
  14.315 -<p class=Table>Enables the multiply instructions (<span style="font-family: Verdana, sans-serif;">mul, 
  14.316 - muli)</span>.</td></tr>
  14.317 -
  14.318 -<tr valign="top" class="whs15">
  14.319 -<td colspan="1" rowspan="1" width="167px" class="whs18">
  14.320 -<p class=Table>Enable Pipelined Multiplier (DSP Block if available)</td>
  14.321 -<td colspan="1" rowspan="1" width="524px" class="whs21">
  14.322 -<p class=Table>Enables the multiplier using the DSP block, if available.</td></tr>
  14.323 -
  14.324 -<tr valign="top" class="whs15">
  14.325 -<td colspan="1" rowspan="1" width="167px" class="whs18">
  14.326 -<p class=Table>Enable Multicycle (LUT-based, 32 cycles) Multiplier</td>
  14.327 -<td colspan="1" rowspan="1" width="524px" class="whs21">
  14.328 -<p class=Table>Enables the multiplier using LUTs.</td></tr>
  14.329 -
  14.330 -<tr valign="top" class="whs15">
  14.331 -<td colspan="2" rowspan="1" width="691px" class="whs20">
  14.332 -<p class=Table
  14.333 -	style="font-weight: bold;">Instruction Cache</td>
  14.334 -</tr>
  14.335 -
  14.336 -<tr valign="top" class="whs15">
  14.337 -<td colspan="1" rowspan="1" width="167px" class="whs18">
  14.338 -<p class=Table>Instruction Cache Enabled</td>
  14.339 -<td colspan="1" rowspan="1" width="524px" class="whs19">
  14.340 -<p class=Table
  14.341 -	style="margin-left: 14px;">Determines whether an instruction cache 
  14.342 - is implemented.</td></tr>
  14.343 -
  14.344 -<tr valign="top" class="whs15">
  14.345 -<td colspan="1" rowspan="1" width="167px" class="whs18">
  14.346 -<p class=Table>Number of Sets</td>
  14.347 -<td colspan="1" rowspan="1" width="524px" class="whs19">
  14.348 -<p class=Table
  14.349 -	style="margin-left: 14px;">Specifies the number of sets in the instruction 
  14.350 - cache. Supported values are 128, 256, 512, 1024.</td></tr>
  14.351 -
  14.352 -<tr valign="top" class="whs15">
  14.353 -<td colspan="1" rowspan="1" width="167px" class="whs18">
  14.354 -<p class=Table>Set Associativity</td>
  14.355 -<td colspan="1" rowspan="1" width="524px" class="whs19">
  14.356 -<p class=Table
  14.357 -	style="margin-left: 14px;">Specifies the associativity of the instruction 
  14.358 - cache. Supported values are 1, 2.</td></tr>
  14.359 -
  14.360 -<tr valign="top" class="whs15">
  14.361 -<td colspan="1" rowspan="1" width="167px" class="whs18">
  14.362 -<p class=Table>Bytes/Cache Line</td>
  14.363 -<td colspan="1" rowspan="1" width="524px" class="whs19">
  14.364 -<p class=Table
  14.365 -	style="margin-left: 15px;">Specifies the number of bytes per instruction 
  14.366 - cache line. Supported values are 4, 8, 16.</td></tr>
  14.367 -
  14.368 -<tr valign="top" class="whs15">
  14.369 -<td colspan="1" rowspan="1" width="167px" class="whs18">
  14.370 -<p class=Table>Memory Type</td>
  14.371 -<td colspan="1" rowspan="1" width="524px" class="whs19">
  14.372 -<p class=Table
  14.373 -	style="margin-left: 15px;">Determines the FPGA resource to be used 
  14.374 - to implement the instruction cache. The decision can be left to the synthesis 
  14.375 - tool (Auto), or you can select from the following options:</p>
  14.376 -<ul type="disc" class="whs22">
  14.377 -	
  14.378 -	<li class=kadov-p-CBullet><p class=Bullet>Auto &#8211; 
  14.379 - Leaves the implementation of the instruction cache to the synthesis tool.</p></li>
  14.380 -	
  14.381 -	<li class=kadov-p-CBullet><p class=Bullet>Distributed RAM &#8211; 
  14.382 - Implements the instruction cache as distributed RAM.</p></li>
  14.383 -	
  14.384 -	<li class=kadov-p-CBullet><p class=Bullet>Dual-Port EBR &#8211; 
  14.385 - Implements the instruction cache as dual-port EBR (two read/write ports).</p></li>
  14.386 -	
  14.387 -	<li class=kadov-p-CBullet><p class=Bullet>Pseudo Dual-Port EBR &#8211; Implements 
  14.388 - the instruction cache as pseudo-dual-port EBR (one read port and one write 
  14.389 - port). </p></li>
  14.390 -</ul></td></tr>
  14.391 -
  14.392 -<tr valign="top" class="whs15">
  14.393 -<td colspan="2" rowspan="1" width="691px" class="whs20">
  14.394 -<p class=Table
  14.395 -	style="font-weight: bold;">Debug Setting</td>
  14.396 -</tr>
  14.397 -
  14.398 -<tr valign="top" class="whs15">
  14.399 -<td colspan="1" rowspan="1" width="167px" class="whs18">
  14.400 -<p class=Table>Enable Debug Interface</td>
  14.401 -<td colspan="1" rowspan="1" width="524px" class="whs21">
  14.402 -<p class=Table>Includes the debugger stub in the CPU, which is required 
  14.403 - for debugging.</td></tr>
  14.404 -
  14.405 -<tr valign="top" class="whs15">
  14.406 -<td colspan="1" rowspan="1" width="167px" class="whs18">
  14.407 -<p class=Table># of H/W Watchpoint Registers</td>
  14.408 -<td colspan="1" rowspan="1" width="524px" class="whs21">
  14.409 -<p class=Table
  14.410 -	style="font-weight: normal;">Specifies the number of hardware watchpoint 
  14.411 - registers to be used in the debugging process.</td></tr>
  14.412 -
  14.413 -<tr valign="top" class="whs15">
  14.414 -<td colspan="1" rowspan="1" width="167px" class="whs18">
  14.415 -<p class=Table>Enable Debugging Code in Flash or ROM</td>
  14.416 -<td colspan="1" rowspan="1" width="524px" class="whs21">
  14.417 -<p class=Table
  14.418 -	style="font-weight: normal;">Enables you to set hardware breakpoints 
  14.419 - in read-only memory.</td></tr>
  14.420 -
  14.421 -<tr valign="top" class="whs15">
  14.422 -<td colspan="1" rowspan="1" width="167px" class="whs18">
  14.423 -<p class=Table># of H/W Breakpoint Registers</td>
  14.424 -<td colspan="1" rowspan="1" width="524px" class="whs21">
  14.425 -<p class=Table>Specifies the number of hardware breakpoint registers to 
  14.426 - be used in the debugging process.</td></tr>
  14.427 -
  14.428 -<tr valign="top" class="whs15">
  14.429 -<td colspan="1" rowspan="1" width="167px" class="whs18">
  14.430 -<p class=Table>Enable PC Trace</td>
  14.431 -<td colspan="1" rowspan="1" width="524px" class="whs21">
  14.432 -<p class=Table>Enables the Program Counter Trace feature, which enables 
  14.433 - you to run the program trace during debug to find items in your C or C++ 
  14.434 - Code during debug, such as breakpoints and exceptions. Refer to <span 
  14.435 - style="font-weight: bold;"><B>Help &gt; Help Contents &gt; C/C++ SPE</B></span> 
  14.436 - and <span style="font-weight: bold;"><B>Debug &gt; Concepts &gt; Program 
  14.437 - Counter Trace</B></span> for more information on Program Counter Trace.</td></tr>
  14.438 -
  14.439 -<tr valign="top" class="whs15">
  14.440 -<td colspan="1" rowspan="1" width="167px" class="whs18">
  14.441 -<p class=Table>Trace Depth</td>
  14.442 -<td colspan="1" rowspan="1" width="524px" class="whs21">
  14.443 -<p class=Table>Enables you to specify the depth of the Program Counter 
  14.444 - Trace buffer. Refer to <span style="font-weight: bold;"><B>Help &gt; Help 
  14.445 - Contents &gt; C/C++ SPE</B></span> and <span style="font-weight: bold;"><B>Debug 
  14.446 - &gt; Concepts &gt; Program Counter Trace</B></span> for more information on 
  14.447 - Program Counter Trace.</td></tr>
  14.448 -
  14.449 -<tr valign="top" class="whs15">
  14.450 -<td colspan="2" rowspan="1" width="691px" class="whs20">
  14.451 -<p class=Table
  14.452 -	style="font-weight: bold;">Shifter Settings</td>
  14.453 -</tr>
  14.454 -
  14.455 -<tr valign="top" class="whs15">
  14.456 -<td colspan="1" rowspan="1" width="167px" class="whs18">
  14.457 -<p class=Table>Enable Piplined Barrel Shifter</td>
  14.458 -<td colspan="1" rowspan="1" width="524px" class="whs19">
  14.459 -<p>Enables the barrel shifter to be pipelined. The barrel shifter is implemented 
  14.460 - to perform a shift operation in three cycles.</td></tr>
  14.461 -
  14.462 -<tr valign="top" class="whs15">
  14.463 -<td colspan="1" rowspan="1" width="167px" class="whs18">
  14.464 -<p class=Table>Enable Multicycle Barrel Shifter (up to 32 cycles)</td>
  14.465 -<td colspan="1" rowspan="1" width="524px" class="whs19">
  14.466 -<p>Enables multi-cycle shift operation for the barrel shifter. The barrel 
  14.467 - shifter is implemented to shift one bit per cycle and take thirty-two 
  14.468 - cycles to complete.</td></tr>
  14.469 -
  14.470 -<tr valign="top" class="whs15">
  14.471 -<td colspan="2" rowspan="1" width="691px" class="whs20">
  14.472 -<p class=Table><span style="font-weight: bold;"><B>Data Cache</B></span></td>
  14.473 -</tr>
  14.474 -
  14.475 -<tr valign="top" class="whs15">
  14.476 -<td colspan="1" rowspan="1" width="167px" class="whs18">
  14.477 -<p class=Table>Data Cache Enabled</td>
  14.478 -<td colspan="1" rowspan="1" width="524px" class="whs21">
  14.479 -<p class=Table>Determines whether a data cache is implemented.</td></tr>
  14.480 -
  14.481 -<tr valign="top" class="whs15">
  14.482 -<td colspan="1" rowspan="1" width="167px" class="whs18">
  14.483 -<p class=Table>Number of Sets</td>
  14.484 -<td colspan="1" rowspan="1" width="524px" class="whs21">
  14.485 -<p class=Table>Specifies the number of sets in the data cache. Supported 
  14.486 - values are 128, 256, 512, 1024.</td></tr>
  14.487 -
  14.488 -<tr valign="top" class="whs15">
  14.489 -<td colspan="1" rowspan="1" width="167px" class="whs18">
  14.490 -<p class=Table>Set Associativity</td>
  14.491 -<td colspan="1" rowspan="1" width="524px" class="whs21">
  14.492 -<p class=Table>Specifies the associativity of the data cache. Supported 
  14.493 - values are 1, 2.</td></tr>
  14.494 -
  14.495 -<tr valign="top" class="whs15">
  14.496 -<td colspan="1" rowspan="1" width="167px" class="whs18">
  14.497 -<p class=Table>Bytes/Cache Line</td>
  14.498 -<td colspan="1" rowspan="1" width="524px" class="whs21">
  14.499 -<p class=Table>Specifies the number of bytes per data cache line. Supported 
  14.500 - values are 4, 8, 16.</td></tr>
  14.501 -
  14.502 -<tr valign="top" class="whs15">
  14.503 -<td colspan="1" rowspan="1" width="167px" class="whs23">
  14.504 -<p class=Table>Memory Type</td>
  14.505 -<td colspan="1" rowspan="1" width="524px" class="whs24">
  14.506 -<p class=Table>Determines the FPGA resource to be used to implement the 
  14.507 - data cache. The decision can be left to the synthesis tool (Auto), or 
  14.508 - you can select from the following options:</p>
  14.509 -<ul>
  14.510 -	
  14.511 -	<li class=kadov-p-CBullet><p class=Bullet>Auto &#8211; 
  14.512 - Leaves the implementation of the data cache to the synthesis tool.</p></li>
  14.513 -	
  14.514 -	<li class=kadov-p-CBullet><p class=Bullet>Distributed RAM &#8211; 
  14.515 - Implements the data cache as distributed RAM.</p></li>
  14.516 -	
  14.517 -	<li class=kadov-p-CBullet><p class=Bullet>Dual-Port EBR &#8211; 
  14.518 - Implements the data cache as dual-port EBR (two read/write ports).</p></li>
  14.519 -</ul></td></tr>
  14.520 -</table>
  14.521 -
  14.522 -<p>&nbsp;</p>
  14.523 -
  14.524 -<h2>Dialog Box Parameters &#8211; 
  14.525 - Inline Memory Tab</h2>
  14.526 -
  14.527 -<table x-use-null-cells cellspacing="0" class="whs12">
  14.528 -<col class="whs13">
  14.529 -<col class="whs14">
  14.530 -
  14.531 -<tr valign="top" class="whs15">
  14.532 -<td bgcolor="#DEE8F4" width="167px" class="whs25">
  14.533 -<p class=Table
  14.534 -	style="font-weight: bold;">Parameter</td>
  14.535 -<td bgcolor="#DEE8F4" width="524px" class="whs26">
  14.536 -<p class=Table
  14.537 -	style="font-weight: bold;">Description</td></tr>
  14.538 -
  14.539 -<tr valign="top" class="whs15">
  14.540 -<td rowspan="1" colspan="2" width="691px" class="whs27">
  14.541 -<p class=Table
  14.542 -	style="font-weight: bold;">Instruction Inline Memory</td>
  14.543 -</tr>
  14.544 -
  14.545 -<tr valign="top" class="whs15">
  14.546 -<td width="167px" class="whs28">
  14.547 -<p class=Table>Enable</td>
  14.548 -<td width="524px" class="whs29">
  14.549 -<p class=Table>Enables the instruction inline memory</td></tr>
  14.550 -
  14.551 -<tr valign="top" class="whs15">
  14.552 -<td width="167px" class="whs28">
  14.553 -<p class=Table>Instance Name</td>
  14.554 -<td width="524px" class="whs29">
  14.555 -<p class=Table>Specifics the name of the instruction inline memory. Alphanumeric 
  14.556 - values and underscores are supported. The default is Instruction_IM.</td></tr>
  14.557 -
  14.558 -<tr valign="top" class="whs15">
  14.559 -<td width="167px" class="whs28">
  14.560 -<p class=Table>Base Address</td>
  14.561 -<td width="524px" class="whs29">
  14.562 -<p class=Table>Specifies the base address for the instruction inline memory. 
  14.563 - The default is 0x10000000.</td></tr>
  14.564 -
  14.565 -<tr valign="top" class="whs15">
  14.566 -<td width="167px" class="whs28">
  14.567 -<p class=Table>Size of Memory in Bytes</td>
  14.568 -<td width="524px" class="whs29">
  14.569 -<p class=Table>Specifies the size of the instruction inline memory.</td></tr>
  14.570 -
  14.571 -<tr valign="top" class="whs15">
  14.572 -<td rowspan="1" colspan="2" width="691px" class="whs27">
  14.573 -<p class=Table><span style="font-weight: bold;"><B>Memory File</B></span></td>
  14.574 -</tr>
  14.575 -
  14.576 -<tr valign="top" class="whs15">
  14.577 -<td width="167px" class="whs28">
  14.578 -<p class=Table>Initialization File Name</td>
  14.579 -<td width="524px" class="whs29">
  14.580 -<p class=Table>Specifies the name of the memory initialization file for 
  14.581 - instruction inline memory.</td></tr>
  14.582 -
  14.583 -<tr valign="top" class="whs15">
  14.584 -<td width="167px" class="whs28">
  14.585 -<p class=Table>File Format</td>
  14.586 -<td width="524px" class="whs29">
  14.587 -<p class=Table>Specifies the format of the memory initialization file: 
  14.588 - hex or binary.</td></tr>
  14.589 -
  14.590 -<tr valign="top" class="whs15">
  14.591 -<td rowspan="1" colspan="2" width="691px" class="whs27">
  14.592 -<p class=Table
  14.593 -	style="font-weight: bold;">Data Inline Memory</td>
  14.594 -</tr>
  14.595 -
  14.596 -<tr valign="top" class="whs15">
  14.597 -<td width="167px" class="whs28">
  14.598 -<p class=Table>Enabled</td>
  14.599 -<td width="524px" class="whs29">
  14.600 -<p class=Table>Enables the data inline memory.</td></tr>
  14.601 -
  14.602 -<tr valign="top" class="whs15">
  14.603 -<td width="167px" class="whs28">
  14.604 -<p class=Table>Instance Name</td>
  14.605 -<td width="524px" class="whs29">
  14.606 -<p class=Table>Specifies the name of the data inline memory. Alphanumeric 
  14.607 - values and underscores are supported. The default is Data_IM.</td></tr>
  14.608 -
  14.609 -<tr valign="top" class="whs15">
  14.610 -<td width="167px" class="whs28">
  14.611 -<p class=Table>Base Address</td>
  14.612 -<td width="524px" class="whs29">
  14.613 -<p class=Table>Specifies the base address for the data inline memory. The 
  14.614 - default is 0x20000000.</td></tr>
  14.615 -
  14.616 -<tr valign="top" class="whs15">
  14.617 -<td width="167px" class="whs28">
  14.618 -<p class=Table>Size of Memory in Bytes</td>
  14.619 -<td width="524px" class="whs29">
  14.620 -<p class=Table>Specifies the size of the data inline memory.</td></tr>
  14.621 -
  14.622 -<tr valign="top" class="whs15">
  14.623 -<td colspan="2" rowspan="1" width="691px" class="whs27">
  14.624 -<p class=Table
  14.625 -	style="font-weight: bold;">Memory File</td>
  14.626 -</tr>
  14.627 -
  14.628 -<tr valign="top" class="whs15">
  14.629 -<td colspan="1" rowspan="1" width="167px" class="whs28">
  14.630 -<p class=Table>Initialization File Name</td>
  14.631 -<td colspan="1" rowspan="1" width="524px" class="whs29">
  14.632 -<p class=Table>Specifies the name of the memory initialization file for 
  14.633 - data inline memory.</td></tr>
  14.634 -
  14.635 -<tr valign="top" class="whs15">
  14.636 -<td colspan="1" rowspan="1" width="167px" class="whs30">
  14.637 -<p class=Table>File Format</td>
  14.638 -<td colspan="1" rowspan="1" width="524px" class="whs31">
  14.639 -<p class=Table>Specifies the format of the memory initialization file: 
  14.640 - hex or binary.</td></tr>
  14.641 -</table>
  14.642 -
  14.643 -<p>&nbsp;</p>
  14.644 -
  14.645 -<p>For the revision history of the component RTL files, refer to the header 
  14.646 - of each component Verilog source file. </p>
  14.647 -
  14.648 -<p><span style="font-weight: bold;"><B>Note</B></span>: If the processor manual 
  14.649 - fails to open, click <img src="qm_icon.jpg" x-maintain-ratio="TRUE" width="14px" height="16px" border="0" class="img_whs32"> on the Available Components toolbar, 
  14.650 - and then click the note button.</p>
  14.651 -
  14.652 -<script type="text/javascript" language="JavaScript">
  14.653 -<!--
  14.654 - if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape'))
  14.655 -  document.write("<div id='tooltip' class='WebHelpPopupMenu'></div>");
  14.656 -//-->
  14.657 -</script><script type="text/javascript" language="javascript1.2">
  14.658 -<!--
  14.659 -if (window.writeIntopicBar)
  14.660 -	writeIntopicBar(0);
  14.661 -//-->
  14.662 -</script>
  14.663 -</body>
  14.664 -</html>

    17.1 --- a/jtag_cores.v	Sun Mar 06 21:17:31 2011 +0000
    17.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    17.3 @@ -1,66 +0,0 @@
    17.4 -// Modified by GSI to use simple positive edge clocking and the JTAG capture state
    17.5 -
    17.6 -module jtag_cores (
    17.7 -    input [7:0] reg_d,
    17.8 -    input [2:0] reg_addr_d,
    17.9 -    output reg_update,
   17.10 -    output [7:0] reg_q,
   17.11 -    output [2:0] reg_addr_q,
   17.12 -    output jtck,
   17.13 -    output jrstn
   17.14 -);
   17.15 -
   17.16 -wire tck;
   17.17 -wire tdi;
   17.18 -wire tdo;
   17.19 -wire capture;
   17.20 -wire shift;
   17.21 -wire update;
   17.22 -wire e1dr;
   17.23 -wire reset;
   17.24 -
   17.25 -jtag_tap jtag_tap (
   17.26 -	.tck(tck),
   17.27 -	.tdi(tdi),
   17.28 -	.tdo(tdo),
   17.29 -	.capture(capture),
   17.30 -	.shift(shift),
   17.31 -	.e1dr(e1dr),
   17.32 -	.update(update),
   17.33 -	.reset(reset)
   17.34 -);
   17.35 -
   17.36 -reg [10:0] jtag_shift;
   17.37 -reg [10:0] jtag_latched;
   17.38 -
   17.39 -always @(posedge tck)
   17.40 -begin
   17.41 -	if(reset)
   17.42 -		jtag_shift <= 11'b0;
   17.43 -	else begin
   17.44 -		if (shift)
   17.45 -			jtag_shift <= {tdi, jtag_shift[10:1]};
   17.46 -		else if (capture)
   17.47 -			jtag_shift <= {reg_d, reg_addr_d};
   17.48 -	end
   17.49 -end
   17.50 -
   17.51 -assign tdo = jtag_shift[0];
   17.52 -
   17.53 -always @(posedge tck)
   17.54 -begin
   17.55 -	if(reset)
   17.56 -		jtag_latched <= 11'b0;
   17.57 -	else begin
   17.58 -	   if (e1dr)
   17.59 -		   jtag_latched <= jtag_shift;
   17.60 -	end
   17.61 -end
   17.62 -
   17.63 -assign reg_update = update;
   17.64 -assign reg_q = jtag_latched[10:3];
   17.65 -assign reg_addr_q = jtag_latched[2:0];
   17.66 -assign jtck = tck;
   17.67 -assign jrstn = ~reset;
   17.68 -
   17.69 -endmodule

    18.1 --- a/jtag_tap_altera.v	Sun Mar 06 21:17:31 2011 +0000
    18.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    18.3 @@ -1,59 +0,0 @@
    18.4 -module jtag_tap(
    18.5 -  output tck,
    18.6 -  output tdi,
    18.7 -  input tdo,
    18.8 -  output capture,
    18.9 -  output shift,
   18.10 -  output e1dr,
   18.11 -  output update,
   18.12 -  output reset
   18.13 -);
   18.14 -
   18.15 -assign reset = 0;
   18.16 -wire nil1, nil2, nil3, nil4;
   18.17 -
   18.18 -sld_virtual_jtag altera_jtag(
   18.19 -  .ir_in       		(),
   18.20 -  .ir_out		(),
   18.21 -  .tck			(tck),
   18.22 -  .tdo			(tdo),
   18.23 -  .tdi			(tdi),
   18.24 -  .virtual_state_cdr	(capture),
   18.25 -  .virtual_state_sdr	(shift),
   18.26 -  .virtual_state_e1dr	(e1dr),
   18.27 -  .virtual_state_pdr	(nil1),
   18.28 -  .virtual_state_e2dr	(nil2),
   18.29 -  .virtual_state_udr	(update),
   18.30 -  .virtual_state_cir	(nil3),
   18.31 -  .virtual_state_uir	(nil4)
   18.32 -  // synopsys translate_off
   18.33 -  ,
   18.34 -  .jtag_state_cdr	(),
   18.35 -  .jtag_state_cir	(),
   18.36 -  .jtag_state_e1dr	(),
   18.37 -  .jtag_state_e1ir	(),
   18.38 -  .jtag_state_e2dr	(),
   18.39 -  .jtag_state_e2ir	(),
   18.40 -  .jtag_state_pdr	(),
   18.41 -  .jtag_state_pir	(),
   18.42 -  .jtag_state_rti	(),
   18.43 -  .jtag_state_sdr	(),
   18.44 -  .jtag_state_sdrs	(),
   18.45 -  .jtag_state_sir	(),
   18.46 -  .jtag_state_sirs	(),
   18.47 -  .jtag_state_tlr	(),
   18.48 -  .jtag_state_udr	(),
   18.49 -  .jtag_state_uir	(),
   18.50 -  .tms			()
   18.51 -  // synopsys translate_on
   18.52 -  );
   18.53 -
   18.54 -defparam
   18.55 -   altera_jtag.sld_auto_instance_index = "YES",
   18.56 -   altera_jtag.sld_instance_index = 0,
   18.57 -   altera_jtag.sld_ir_width = 1,
   18.58 -   altera_jtag.sld_sim_action = "",
   18.59 -   altera_jtag.sld_sim_n_scan = 0,
   18.60 -   altera_jtag.sld_sim_total_length = 0;
   18.61 -
   18.62 -endmodule

    19.1 --- a/jtag_tap_xilinx_spartan6.v	Sun Mar 06 21:17:31 2011 +0000
    19.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    19.3 @@ -1,43 +0,0 @@
    19.4 -
    19.5 -module jtag_tap(
    19.6 -	output tck,
    19.7 -	output tdi,
    19.8 -	input tdo,
    19.9 -	output capture,
   19.10 -	output shift,
   19.11 -	output e1dr,
   19.12 -	output update,
   19.13 -	output reset
   19.14 -);
   19.15 -
   19.16 -// Unfortunately the exit1 state for DR (e1dr) is mising
   19.17 -// We can simulate it by interpretting 'update' as e1dr and delaying 'update'
   19.18 -wire g_capture;
   19.19 -wire g_shift;
   19.20 -wire g_update;
   19.21 -reg update_delay;
   19.22 -
   19.23 -assign capture = g_capture & sel;
   19.24 -assign shift = g_shift & sel;
   19.25 -assign e1dr = g_update & sel;
   19.26 -assign update = update_delay;
   19.27 -
   19.28 -BSCAN_SPARTAN6 #(
   19.29 -	.JTAG_CHAIN(1)
   19.30 -) bscan (
   19.31 -	.CAPTURE(g_capture),
   19.32 -	.DRCK(tck),
   19.33 -	.RESET(reset),
   19.34 -	.RUNTEST(),
   19.35 -	.SEL(sel),
   19.36 -	.SHIFT(g_shift),
   19.37 -	.TCK(),
   19.38 -	.TDI(tdi),
   19.39 -	.TMS(),
   19.40 -	.UPDATE(g_update),
   19.41 -	.TDO(tdo)
   19.42 -);
   19.43 -
   19.44 -update_delay <= g_update;
   19.45 -
   19.46 -endmodule

    20.1 --- a/lm32_adder.v	Sun Mar 06 21:17:31 2011 +0000
    20.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    20.3 @@ -1,115 +0,0 @@
    20.4 -// =============================================================================
    20.5 -//                           COPYRIGHT NOTICE
    20.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation
    20.7 -// ALL RIGHTS RESERVED
    20.8 -// This confidential and proprietary software may be used only as authorised by
    20.9 -// a licensing agreement from Lattice Semiconductor Corporation.
   20.10 -// The entire notice above must be reproduced on all authorized copies and
   20.11 -// copies may only be made to the extent permitted by a licensing agreement from
   20.12 -// Lattice Semiconductor Corporation.
   20.13 -//
   20.14 -// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
   20.15 -// 5555 NE Moore Court                            408-826-6000 (other locations)
   20.16 -// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
   20.17 -// U.S.A                                   email: techsupport@latticesemi.com
   20.18 -// ============================================================================/
   20.19 -//                         FILE DETAILS
   20.20 -// Project          : LatticeMico32
   20.21 -// File             : lm32_adder.v
   20.22 -// Title            : Integer adder / subtractor with comparison flag generation 
   20.23 -// Dependencies     : lm32_include.v
   20.24 -// Version          : 6.1.17
   20.25 -//                  : Initial Release
   20.26 -// Version          : 7.0SP2, 3.0
   20.27 -//                  : No Change
   20.28 -// Version          : 3.1
   20.29 -//                  : No Change
   20.30 -// =============================================================================
   20.31 -
   20.32 -`include "lm32_include.v"
   20.33 -
   20.34 -/////////////////////////////////////////////////////
   20.35 -// Module interface
   20.36 -/////////////////////////////////////////////////////
   20.37 -
   20.38 -module lm32_adder (
   20.39 -    // ----- Inputs -------
   20.40 -    adder_op_x,
   20.41 -    adder_op_x_n,
   20.42 -    operand_0_x,
   20.43 -    operand_1_x,
   20.44 -    // ----- Outputs -------
   20.45 -    adder_result_x,
   20.46 -    adder_carry_n_x,
   20.47 -    adder_overflow_x
   20.48 -    );
   20.49 -
   20.50 -/////////////////////////////////////////////////////
   20.51 -// Inputs
   20.52 -/////////////////////////////////////////////////////
   20.53 -
   20.54 -input adder_op_x;                                       // Operating to perform, 0 for addition, 1 for subtraction
   20.55 -input adder_op_x_n;                                     // Inverted version of adder_op_x
   20.56 -input [`LM32_WORD_RNG] operand_0_x;                     // Operand to add, or subtract from
   20.57 -input [`LM32_WORD_RNG] operand_1_x;                     // Opearnd to add, or subtract by
   20.58 -
   20.59 -/////////////////////////////////////////////////////
   20.60 -// Outputs
   20.61 -/////////////////////////////////////////////////////
   20.62 -
   20.63 -output [`LM32_WORD_RNG] adder_result_x;                 // Result of addition or subtraction
   20.64 -wire   [`LM32_WORD_RNG] adder_result_x;
   20.65 -output adder_carry_n_x;                                 // Inverted carry
   20.66 -wire   adder_carry_n_x;
   20.67 -output adder_overflow_x;                                // Indicates if overflow occured, only valid for subtractions
   20.68 -reg    adder_overflow_x;
   20.69 -    
   20.70 -/////////////////////////////////////////////////////
   20.71 -// Internal nets and registers 
   20.72 -/////////////////////////////////////////////////////
   20.73 -
   20.74 -wire a_sign;                                            // Sign (i.e. positive or negative) of operand 0
   20.75 -wire b_sign;                                            // Sign of operand 1
   20.76 -wire result_sign;                                       // Sign of result
   20.77 -
   20.78 -/////////////////////////////////////////////////////
   20.79 -// Instantiations 
   20.80 -/////////////////////////////////////////////////////
   20.81 -
   20.82 -lm32_addsub addsub (
   20.83 -    // ----- Inputs -----
   20.84 -    .DataA          (operand_0_x), 
   20.85 -    .DataB          (operand_1_x), 
   20.86 -    .Cin            (adder_op_x), 
   20.87 -    .Add_Sub        (adder_op_x_n), 
   20.88 -    // ----- Ouputs -----
   20.89 -    .Result         (adder_result_x), 
   20.90 -    .Cout           (adder_carry_n_x)
   20.91 -    );
   20.92 -
   20.93 -/////////////////////////////////////////////////////
   20.94 -// Combinational Logic
   20.95 -/////////////////////////////////////////////////////
   20.96 -
   20.97 -// Extract signs of operands and result
   20.98 -
   20.99 -assign a_sign = operand_0_x[`LM32_WORD_WIDTH-1];
  20.100 -assign b_sign = operand_1_x[`LM32_WORD_WIDTH-1];
  20.101 -assign result_sign = adder_result_x[`LM32_WORD_WIDTH-1];
  20.102 -
  20.103 -// Determine whether an overflow occured when performing a subtraction
  20.104 -
  20.105 -always @(*)
  20.106 -begin    
  20.107 -    //  +ve - -ve = -ve -> overflow
  20.108 -    //  -ve - +ve = +ve -> overflow
  20.109 -    if  (   (!a_sign & b_sign & result_sign)
  20.110 -         || (a_sign & !b_sign & !result_sign)
  20.111 -        )
  20.112 -        adder_overflow_x = `TRUE;
  20.113 -    else
  20.114 -        adder_overflow_x = `FALSE;
  20.115 -end
  20.116 -    
  20.117 -endmodule
  20.118 -

    21.1 --- a/lm32_addsub.v	Sun Mar 06 21:17:31 2011 +0000
    21.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    21.3 @@ -1,98 +0,0 @@
    21.4 -// =============================================================================
    21.5 -//                           COPYRIGHT NOTICE
    21.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation
    21.7 -// ALL RIGHTS RESERVED
    21.8 -// This confidential and proprietary software may be used only as authorised by
    21.9 -// a licensing agreement from Lattice Semiconductor Corporation.
   21.10 -// The entire notice above must be reproduced on all authorized copies and
   21.11 -// copies may only be made to the extent permitted by a licensing agreement from
   21.12 -// Lattice Semiconductor Corporation.
   21.13 -//
   21.14 -// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
   21.15 -// 5555 NE Moore Court                            408-826-6000 (other locations)
   21.16 -// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
   21.17 -// U.S.A                                   email: techsupport@latticesemi.com
   21.18 -// =============================================================================/
   21.19 -//                         FILE DETAILS
   21.20 -// Project          : LatticeMico32
   21.21 -// File             : lm32_addsub.v
   21.22 -// Title            : PMI adder/subtractor.
   21.23 -// Version          : 6.1.17
   21.24 -//                  : Initial Release
   21.25 -// Version          : 7.0SP2, 3.0
   21.26 -//                  : No Change
   21.27 -// Version          : 3.1
   21.28 -//                  : No Change
   21.29 -// =============================================================================
   21.30 -
   21.31 -`include "lm32_include.v"
   21.32 -
   21.33 -/////////////////////////////////////////////////////
   21.34 -// Module interface
   21.35 -/////////////////////////////////////////////////////
   21.36 -
   21.37 -module lm32_addsub (
   21.38 -    // ----- Inputs -------
   21.39 -    DataA, 
   21.40 -    DataB, 
   21.41 -    Cin, 
   21.42 -    Add_Sub, 
   21.43 -    // ----- Outputs -------
   21.44 -    Result, 
   21.45 -    Cout
   21.46 -    );
   21.47 -
   21.48 -/////////////////////////////////////////////////////
   21.49 -// Inputs
   21.50 -/////////////////////////////////////////////////////
   21.51 -
   21.52 -input [31:0] DataA;
   21.53 -input [31:0] DataB;
   21.54 -input Cin;
   21.55 -input Add_Sub;
   21.56 -
   21.57 -/////////////////////////////////////////////////////
   21.58 -// Outputs
   21.59 -/////////////////////////////////////////////////////
   21.60 -
   21.61 -output [31:0] Result;
   21.62 -wire   [31:0] Result;
   21.63 -output Cout;
   21.64 -wire   Cout;
   21.65 -
   21.66 -/////////////////////////////////////////////////////
   21.67 -// Instantiations
   21.68 -///////////////////////////////////////////////////// 
   21.69 -
   21.70 -// Only use Lattice specific constructs when compiling with ispLEVER
   21.71 -`ifdef PLATFORM_LATTICE
   21.72 -       generate
   21.73 -	  if (`LATTICE_FAMILY == "SC" || `LATTICE_FAMILY == "SCM") begin
   21.74 -`endif
   21.75 -	     wire [32:0] tmp_addResult = DataA + DataB + Cin;
   21.76 -	     wire [32:0] tmp_subResult = DataA - DataB - !Cin;   
   21.77 -   
   21.78 -	     assign  Result = (Add_Sub == 1) ? tmp_addResult[31:0] : tmp_subResult[31:0];
   21.79 -	     assign  Cout = (Add_Sub == 1) ? tmp_addResult[32] : !tmp_subResult[32];
   21.80 -`ifdef PLATFORM_LATTICE
   21.81 -	  end else begin
   21.82 -	    pmi_addsub #(// ----- Parameters -------
   21.83 -			 .pmi_data_width     (32),
   21.84 -			 .pmi_result_width   (32),
   21.85 -			 .pmi_sign           ("off"),
   21.86 -			 .pmi_family         (`LATTICE_FAMILY),
   21.87 -			 .module_type        ("pmi_addsub")) 
   21.88 -	      addsub    (// ----- Inputs -------
   21.89 -			 .DataA              (DataA),
   21.90 -			 .DataB              (DataB),
   21.91 -			 .Cin                (Cin),
   21.92 -			 .Add_Sub            (Add_Sub),
   21.93 -			 // ----- Outputs -------
   21.94 -			 .Result             (Result),
   21.95 -			 .Cout               (Cout),
   21.96 -			 .Overflow           ());
   21.97 -	  end
   21.98 -       endgenerate 
   21.99 -`endif
  21.100 -
  21.101 -endmodule

    22.1 --- a/lm32_cpu.v	Sun Mar 06 21:17:31 2011 +0000
    22.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    22.3 @@ -1,2717 +0,0 @@
    22.4 -// =============================================================================
    22.5 -//                           COPYRIGHT NOTICE
    22.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation
    22.7 -// ALL RIGHTS RESERVED
    22.8 -// This confidential and proprietary software may be used only as authorised by
    22.9 -// a licensing agreement from Lattice Semiconductor Corporation.
   22.10 -// The entire notice above must be reproduced on all authorized copies and
   22.11 -// copies may only be made to the extent permitted by a licensing agreement from
   22.12 -// Lattice Semiconductor Corporation.
   22.13 -//
   22.14 -// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
   22.15 -// 5555 NE Moore Court                            408-826-6000 (other locations)
   22.16 -// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
   22.17 -// U.S.A                                   email: techsupport@latticesemi.com
   22.18 -// =============================================================================/
   22.19 -//                         FILE DETAILS
   22.20 -// Project          : LatticeMico32
   22.21 -// File             : lm32_cpu.v
   22.22 -// Title            : Top-level of CPU.
   22.23 -// Dependencies     : lm32_include.v
   22.24 -//
   22.25 -// Version 3.4
   22.26 -// 1. Bug Fix: In a tight infinite loop (add, sw, bi) incoming interrupts were 
   22.27 -//    never serviced.
   22.28 -//    
   22.29 -// Version 3.3
   22.30 -// 1. Feature: Support for memory that is tightly coupled to processor core, and 
   22.31 -//    has a single-cycle access latency (same as caches). Instruction port has
   22.32 -//    access to a dedicated physically-mapped memory. Data port has access to
   22.33 -//    a dedicated physically-mapped memory. In order to be able to manipulate
   22.34 -//    values in both these memories via the debugger, these memories also
   22.35 -//    interface with the data port of LM32.
   22.36 -// 2. Feature: Extended Configuration Register
   22.37 -// 3. Bug Fix: Removed port names that conflict with keywords reserved in System-
   22.38 -//    Verilog.
   22.39 -//
   22.40 -// Version 3.2
   22.41 -// 1. Bug Fix: Single-stepping a load/store to invalid address causes debugger to
   22.42 -//    hang. At the same time CPU fails to register data bus error exception. Bug
   22.43 -//    is caused because (a) data bus error exception occurs after load/store has
   22.44 -//    passed X stage and next sequential instruction (e.g., brk) is already in X
   22.45 -//    stage, and (b) data bus error exception had lower priority than, say, brk
   22.46 -//    exception.
   22.47 -// 2. Bug Fix: If a brk (or scall/eret/bret) sequentially follows a load/store to
   22.48 -//    invalid location, CPU will fail to register data bus error exception. The
   22.49 -//    solution is to stall scall/eret/bret/brk instructions in D pipeline stage
   22.50 -//    until load/store has completed.
   22.51 -// 3. Feature: Enable precise identification of load/store that causes seg fault.
   22.52 -// 4. SYNC resets used for register file when implemented in EBRs.
   22.53 -//
   22.54 -// Version 3.1
   22.55 -// 1. Feature: LM32 Register File can now be mapped in to on-chip block RAM (EBR)
   22.56 -//    instead of distributed memory by enabling the option in LM32 GUI. 
   22.57 -// 2. Feature: LM32 also adds a static branch predictor to improve branch 
   22.58 -//    performance. All immediate-based forward-pointing branches are predicted 
   22.59 -//    not-taken. All immediate-based backward-pointing branches are predicted taken.
   22.60 -// 
   22.61 -// Version 7.0SP2, 3.0
   22.62 -// No Change
   22.63 -//
   22.64 -// Version 6.1.17
   22.65 -// Initial Release
   22.66 -// =============================================================================
   22.67 -
   22.68 -`include "lm32_include.v"
   22.69 -
   22.70 -/////////////////////////////////////////////////////
   22.71 -// Module interface
   22.72 -/////////////////////////////////////////////////////
   22.73 -
   22.74 -module lm32_cpu (
   22.75 -    // ----- Inputs -------
   22.76 -    clk_i,
   22.77 -`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
   22.78 -    clk_n_i,
   22.79 -`endif    
   22.80 -    rst_i,
   22.81 -    // From external devices
   22.82 -`ifdef CFG_INTERRUPTS_ENABLED
   22.83 -    interrupt,
   22.84 -`endif
   22.85 -    // From user logic
   22.86 -`ifdef CFG_USER_ENABLED
   22.87 -    user_result,
   22.88 -    user_complete,
   22.89 -`endif     
   22.90 -`ifdef CFG_JTAG_ENABLED
   22.91 -    // From JTAG
   22.92 -    jtag_clk,
   22.93 -    jtag_update, 
   22.94 -    jtag_reg_q,
   22.95 -    jtag_reg_addr_q,
   22.96 -`endif
   22.97 -`ifdef CFG_IWB_ENABLED
   22.98 -    // Instruction Wishbone master
   22.99 -    I_DAT_I,
  22.100 -    I_ACK_I,
  22.101 -    I_ERR_I,
  22.102 -    I_RTY_I,
  22.103 -`endif
  22.104 -    // Data Wishbone master
  22.105 -    D_DAT_I,
  22.106 -    D_ACK_I,
  22.107 -    D_ERR_I,
  22.108 -    D_RTY_I,
  22.109 -    // ----- Outputs -------
  22.110 -`ifdef CFG_TRACE_ENABLED
  22.111 -    trace_pc,
  22.112 -    trace_pc_valid,
  22.113 -    trace_exception,
  22.114 -    trace_eid,
  22.115 -    trace_eret,
  22.116 -`ifdef CFG_DEBUG_ENABLED
  22.117 -    trace_bret,
  22.118 -`endif
  22.119 -`endif
  22.120 -`ifdef CFG_JTAG_ENABLED
  22.121 -    jtag_reg_d,
  22.122 -    jtag_reg_addr_d,
  22.123 -`endif
  22.124 -`ifdef CFG_USER_ENABLED    
  22.125 -    user_valid,
  22.126 -    user_opcode,
  22.127 -    user_operand_0,
  22.128 -    user_operand_1,
  22.129 -`endif    
  22.130 -`ifdef CFG_IWB_ENABLED
  22.131 -    // Instruction Wishbone master
  22.132 -    I_DAT_O,
  22.133 -    I_ADR_O,
  22.134 -    I_CYC_O,
  22.135 -    I_SEL_O,
  22.136 -    I_STB_O,
  22.137 -    I_WE_O,
  22.138 -    I_CTI_O,
  22.139 -    I_LOCK_O,
  22.140 -    I_BTE_O,
  22.141 -`endif
  22.142 -    // Data Wishbone master
  22.143 -    D_DAT_O,
  22.144 -    D_ADR_O,
  22.145 -    D_CYC_O,
  22.146 -    D_SEL_O,
  22.147 -    D_STB_O,
  22.148 -    D_WE_O,
  22.149 -    D_CTI_O,
  22.150 -    D_LOCK_O,
  22.151 -    D_BTE_O
  22.152 -    );
  22.153 -
  22.154 -/////////////////////////////////////////////////////
  22.155 -// Parameters
  22.156 -/////////////////////////////////////////////////////
  22.157 -
  22.158 -parameter eba_reset = `CFG_EBA_RESET;                           // Reset value for EBA CSR
  22.159 -`ifdef CFG_DEBUG_ENABLED
  22.160 -parameter deba_reset = `CFG_DEBA_RESET;                         // Reset value for DEBA CSR
  22.161 -`endif
  22.162 -
  22.163 -`ifdef CFG_ICACHE_ENABLED
  22.164 -parameter icache_associativity = `CFG_ICACHE_ASSOCIATIVITY;     // Associativity of the cache (Number of ways)
  22.165 -parameter icache_sets = `CFG_ICACHE_SETS;                       // Number of sets
  22.166 -parameter icache_bytes_per_line = `CFG_ICACHE_BYTES_PER_LINE;   // Number of bytes per cache line
  22.167 -parameter icache_base_address = `CFG_ICACHE_BASE_ADDRESS;       // Base address of cachable memory
  22.168 -parameter icache_limit = `CFG_ICACHE_LIMIT;                     // Limit (highest address) of cachable memory
  22.169 -`else
  22.170 -parameter icache_associativity = 1;    
  22.171 -parameter icache_sets = 512;                      
  22.172 -parameter icache_bytes_per_line = 16;  
  22.173 -parameter icache_base_address = 0;      
  22.174 -parameter icache_limit = 0;                    
  22.175 -`endif
  22.176 -
  22.177 -`ifdef CFG_DCACHE_ENABLED
  22.178 -parameter dcache_associativity = `CFG_DCACHE_ASSOCIATIVITY;     // Associativity of the cache (Number of ways)
  22.179 -parameter dcache_sets = `CFG_DCACHE_SETS;                       // Number of sets
  22.180 -parameter dcache_bytes_per_line = `CFG_DCACHE_BYTES_PER_LINE;   // Number of bytes per cache line
  22.181 -parameter dcache_base_address = `CFG_DCACHE_BASE_ADDRESS;       // Base address of cachable memory
  22.182 -parameter dcache_limit = `CFG_DCACHE_LIMIT;                     // Limit (highest address) of cachable memory
  22.183 -`else
  22.184 -parameter dcache_associativity = 1;    
  22.185 -parameter dcache_sets = 512;                      
  22.186 -parameter dcache_bytes_per_line = 16;  
  22.187 -parameter dcache_base_address = 0;      
  22.188 -parameter dcache_limit = 0;                    
  22.189 -`endif
  22.190 -
  22.191 -`ifdef CFG_DEBUG_ENABLED
  22.192 -parameter watchpoints = `CFG_WATCHPOINTS;                       // Number of h/w watchpoint CSRs
  22.193 -`else
  22.194 -parameter watchpoints = 0;
  22.195 -`endif
  22.196 -`ifdef CFG_ROM_DEBUG_ENABLED
  22.197 -parameter breakpoints = `CFG_BREAKPOINTS;                       // Number of h/w breakpoint CSRs
  22.198 -`else
  22.199 -parameter breakpoints = 0;
  22.200 -`endif
  22.201 -
  22.202 -`ifdef CFG_INTERRUPTS_ENABLED
  22.203 -parameter interrupts = `CFG_INTERRUPTS;                         // Number of interrupts
  22.204 -`else
  22.205 -parameter interrupts = 0;
  22.206 -`endif
  22.207 -
  22.208 -/////////////////////////////////////////////////////
  22.209 -// Inputs
  22.210 -/////////////////////////////////////////////////////
  22.211 -
  22.212 -input clk_i;                                    // Clock
  22.213 -`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
  22.214 -input clk_n_i;                                  // Inverted clock
  22.215 -`endif    
  22.216 -input rst_i;                                    // Reset
  22.217 -
  22.218 -`ifdef CFG_INTERRUPTS_ENABLED
  22.219 -input [`LM32_INTERRUPT_RNG] interrupt;          // Interrupt pins
  22.220 -`endif
  22.221 -
  22.222 -`ifdef CFG_USER_ENABLED
  22.223 -input [`LM32_WORD_RNG] user_result;             // User-defined instruction result
  22.224 -input user_complete;                            // User-defined instruction execution is complete
  22.225 -`endif    
  22.226 -
  22.227 -`ifdef CFG_JTAG_ENABLED
  22.228 -input jtag_clk;                                 // JTAG clock
  22.229 -input jtag_update;                              // JTAG state machine is in data register update state
  22.230 -input [`LM32_BYTE_RNG] jtag_reg_q;              
  22.231 -input [2:0] jtag_reg_addr_q;
  22.232 -`endif
  22.233 -
  22.234 -`ifdef CFG_IWB_ENABLED
  22.235 -input [`LM32_WORD_RNG] I_DAT_I;                 // Instruction Wishbone interface read data
  22.236 -input I_ACK_I;                                  // Instruction Wishbone interface acknowledgement
  22.237 -input I_ERR_I;                                  // Instruction Wishbone interface error
  22.238 -input I_RTY_I;                                  // Instruction Wishbone interface retry
  22.239 -`endif
  22.240 -
  22.241 -input [`LM32_WORD_RNG] D_DAT_I;                 // Data Wishbone interface read data
  22.242 -input D_ACK_I;                                  // Data Wishbone interface acknowledgement
  22.243 -input D_ERR_I;                                  // Data Wishbone interface error
  22.244 -input D_RTY_I;                                  // Data Wishbone interface retry
  22.245 -
  22.246 -/////////////////////////////////////////////////////
  22.247 -// Outputs
  22.248 -/////////////////////////////////////////////////////
  22.249 -
  22.250 -`ifdef CFG_TRACE_ENABLED
  22.251 -output [`LM32_PC_RNG] trace_pc;                 // PC to trace
  22.252 -reg    [`LM32_PC_RNG] trace_pc;
  22.253 -output trace_pc_valid;                          // Indicates that a new trace PC is valid
  22.254 -reg    trace_pc_valid;
  22.255 -output trace_exception;                         // Indicates an exception has occured
  22.256 -reg    trace_exception;
  22.257 -output [`LM32_EID_RNG] trace_eid;               // Indicates what type of exception has occured
  22.258 -reg    [`LM32_EID_RNG] trace_eid;
  22.259 -output trace_eret;                              // Indicates an eret instruction has been executed
  22.260 -reg    trace_eret;
  22.261 -`ifdef CFG_DEBUG_ENABLED
  22.262 -output trace_bret;                              // Indicates a bret instruction has been executed
  22.263 -reg    trace_bret;
  22.264 -`endif
  22.265 -`endif
  22.266 -
  22.267 -`ifdef CFG_JTAG_ENABLED
  22.268 -output [`LM32_BYTE_RNG] jtag_reg_d;
  22.269 -wire   [`LM32_BYTE_RNG] jtag_reg_d;
  22.270 -output [2:0] jtag_reg_addr_d;
  22.271 -wire   [2:0] jtag_reg_addr_d;
  22.272 -`endif
  22.273 -
  22.274 -`ifdef CFG_USER_ENABLED
  22.275 -output user_valid;                              // Indicates if user_opcode is valid
  22.276 -wire   user_valid;
  22.277 -output [`LM32_USER_OPCODE_RNG] user_opcode;     // User-defined instruction opcode
  22.278 -reg    [`LM32_USER_OPCODE_RNG] user_opcode;
  22.279 -output [`LM32_WORD_RNG] user_operand_0;         // First operand for user-defined instruction
  22.280 -wire   [`LM32_WORD_RNG] user_operand_0;
  22.281 -output [`LM32_WORD_RNG] user_operand_1;         // Second operand for user-defined instruction
  22.282 -wire   [`LM32_WORD_RNG] user_operand_1;
  22.283 -`endif
  22.284 -
  22.285 -`ifdef CFG_IWB_ENABLED
  22.286 -output [`LM32_WORD_RNG] I_DAT_O;                // Instruction Wishbone interface write data
  22.287 -wire   [`LM32_WORD_RNG] I_DAT_O;
  22.288 -output [`LM32_WORD_RNG] I_ADR_O;                // Instruction Wishbone interface address
  22.289 -wire   [`LM32_WORD_RNG] I_ADR_O;
  22.290 -output I_CYC_O;                                 // Instruction Wishbone interface cycle
  22.291 -wire   I_CYC_O;
  22.292 -output [`LM32_BYTE_SELECT_RNG] I_SEL_O;         // Instruction Wishbone interface byte select
  22.293 -wire   [`LM32_BYTE_SELECT_RNG] I_SEL_O;
  22.294 -output I_STB_O;                                 // Instruction Wishbone interface strobe
  22.295 -wire   I_STB_O;
  22.296 -output I_WE_O;                                  // Instruction Wishbone interface write enable
  22.297 -wire   I_WE_O;
  22.298 -output [`LM32_CTYPE_RNG] I_CTI_O;               // Instruction Wishbone interface cycle type 
  22.299 -wire   [`LM32_CTYPE_RNG] I_CTI_O;
  22.300 -output I_LOCK_O;                                // Instruction Wishbone interface lock bus
  22.301 -wire   I_LOCK_O;
  22.302 -output [`LM32_BTYPE_RNG] I_BTE_O;               // Instruction Wishbone interface burst type 
  22.303 -wire   [`LM32_BTYPE_RNG] I_BTE_O;
  22.304 -`endif
  22.305 -
  22.306 -output [`LM32_WORD_RNG] D_DAT_O;                // Data Wishbone interface write data
  22.307 -wire   [`LM32_WORD_RNG] D_DAT_O;
  22.308 -output [`LM32_WORD_RNG] D_ADR_O;                // Data Wishbone interface address
  22.309 -wire   [`LM32_WORD_RNG] D_ADR_O;
  22.310 -output D_CYC_O;                                 // Data Wishbone interface cycle
  22.311 -wire   D_CYC_O;
  22.312 -output [`LM32_BYTE_SELECT_RNG] D_SEL_O;         // Data Wishbone interface byte select
  22.313 -wire   [`LM32_BYTE_SELECT_RNG] D_SEL_O;
  22.314 -output D_STB_O;                                 // Data Wishbone interface strobe
  22.315 -wire   D_STB_O;
  22.316 -output D_WE_O;                                  // Data Wishbone interface write enable
  22.317 -wire   D_WE_O;
  22.318 -output [`LM32_CTYPE_RNG] D_CTI_O;               // Data Wishbone interface cycle type 
  22.319 -wire   [`LM32_CTYPE_RNG] D_CTI_O;
  22.320 -output D_LOCK_O;                                // Date Wishbone interface lock bus
  22.321 -wire   D_LOCK_O;
  22.322 -output [`LM32_BTYPE_RNG] D_BTE_O;               // Data Wishbone interface burst type 
  22.323 -wire   [`LM32_BTYPE_RNG] D_BTE_O;
  22.324 -
  22.325 -/////////////////////////////////////////////////////
  22.326 -// Internal nets and registers 
  22.327 -/////////////////////////////////////////////////////
  22.328 -
  22.329 -// Pipeline registers
  22.330 -
  22.331 -`ifdef LM32_CACHE_ENABLED
  22.332 -reg valid_a;                                    // Instruction in A stage is valid
  22.333 -`endif
  22.334 -reg valid_f;                                    // Instruction in F stage is valid
  22.335 -reg valid_d;                                    // Instruction in D stage is valid
  22.336 -reg valid_x;                                    // Instruction in X stage is valid
  22.337 -reg valid_m;                                    // Instruction in M stage is valid
  22.338 -reg valid_w;                                    // Instruction in W stage is valid
  22.339 -   
  22.340 -wire q_x;
  22.341 -wire [`LM32_WORD_RNG] immediate_d;              // Immediate operand
  22.342 -wire load_d;                                    // Indicates a load instruction
  22.343 -reg load_x;                                     
  22.344 -reg load_m;
  22.345 -wire load_q_x;
  22.346 -wire store_q_x;
  22.347 -wire store_d;                                   // Indicates a store instruction
  22.348 -reg store_x;
  22.349 -reg store_m;
  22.350 -wire [`LM32_SIZE_RNG] size_d;                   // Size of load/store (byte, hword, word)
  22.351 -reg [`LM32_SIZE_RNG] size_x;
  22.352 -wire branch_d;                                  // Indicates a branch instruction
  22.353 -wire branch_predict_d;                          // Indicates a branch is predicted
  22.354 -wire branch_predict_taken_d;                    // Indicates a branch is predicted taken
  22.355 -wire [`LM32_PC_RNG] branch_predict_address_d;   // Address to which predicted branch jumps
  22.356 -wire [`LM32_PC_RNG] branch_target_d;
  22.357 -wire bi_unconditional;
  22.358 -wire bi_conditional;
  22.359 -reg branch_x;                                   
  22.360 -reg branch_predict_x;
  22.361 -reg branch_predict_taken_x;
  22.362 -reg branch_m;
  22.363 -reg branch_predict_m;
  22.364 -reg branch_predict_taken_m;
  22.365 -wire branch_mispredict_taken_m;                 // Indicates a branch was mispredicted as taken
  22.366 -wire branch_flushX_m;                           // Indicates that instruction in X stage must be squashed
  22.367 -wire branch_reg_d;                              // Branch to register or immediate
  22.368 -wire [`LM32_PC_RNG] branch_offset_d;            // Branch offset for immediate branches
  22.369 -reg [`LM32_PC_RNG] branch_target_x;             // Address to branch to
  22.370 -reg [`LM32_PC_RNG] branch_target_m;
  22.371 -wire [`LM32_D_RESULT_SEL_0_RNG] d_result_sel_0_d; // Which result should be selected in D stage for operand 0
  22.372 -wire [`LM32_D_RESULT_SEL_1_RNG] d_result_sel_1_d; // Which result should be selected in D stage for operand 1
  22.373 -
  22.374 -wire x_result_sel_csr_d;                        // Select X stage result from CSRs
  22.375 -reg x_result_sel_csr_x;
  22.376 -`ifdef LM32_MC_ARITHMETIC_ENABLED
  22.377 -wire x_result_sel_mc_arith_d;                   // Select X stage result from multi-cycle arithmetic unit
  22.378 -reg x_result_sel_mc_arith_x;
  22.379 -`endif
  22.380 -`ifdef LM32_NO_BARREL_SHIFT    
  22.381 -wire x_result_sel_shift_d;                      // Select X stage result from shifter
  22.382 -reg x_result_sel_shift_x;
  22.383 -`endif
  22.384 -`ifdef CFG_SIGN_EXTEND_ENABLED
  22.385 -wire x_result_sel_sext_d;                       // Select X stage result from sign-extend logic
  22.386 -reg x_result_sel_sext_x;
  22.387 -`endif
  22.388 -wire x_result_sel_logic_d;                      // Select X stage result from logic op unit
  22.389 -reg x_result_sel_logic_x;
  22.390 -`ifdef CFG_USER_ENABLED
  22.391 -wire x_result_sel_user_d;                       // Select X stage result from user-defined logic
  22.392 -reg x_result_sel_user_x;
  22.393 -`endif
  22.394 -wire x_result_sel_add_d;                        // Select X stage result from adder
  22.395 -reg x_result_sel_add_x;
  22.396 -wire m_result_sel_compare_d;                    // Select M stage result from comparison logic
  22.397 -reg m_result_sel_compare_x;
  22.398 -reg m_result_sel_compare_m;
  22.399 -`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  22.400 -wire m_result_sel_shift_d;                      // Select M stage result from shifter
  22.401 -reg m_result_sel_shift_x;
  22.402 -reg m_result_sel_shift_m;
  22.403 -`endif
  22.404 -wire w_result_sel_load_d;                       // Select W stage result from load/store unit
  22.405 -reg w_result_sel_load_x;
  22.406 -reg w_result_sel_load_m;
  22.407 -reg w_result_sel_load_w;
  22.408 -`ifdef CFG_PL_MULTIPLY_ENABLED
  22.409 -wire w_result_sel_mul_d;                        // Select W stage result from multiplier
  22.410 -reg w_result_sel_mul_x;
  22.411 -reg w_result_sel_mul_m;
  22.412 -reg w_result_sel_mul_w;
  22.413 -`endif
  22.414 -wire x_bypass_enable_d;                         // Whether result is bypassable in X stage
  22.415 -reg x_bypass_enable_x;                          
  22.416 -wire m_bypass_enable_d;                         // Whether result is bypassable in M stage
  22.417 -reg m_bypass_enable_x;                          
  22.418 -reg m_bypass_enable_m;
  22.419 -wire sign_extend_d;                             // Whether to sign-extend or zero-extend
  22.420 -reg sign_extend_x;
  22.421 -wire write_enable_d;                            // Register file write enable
  22.422 -reg write_enable_x;
  22.423 -wire write_enable_q_x;
  22.424 -reg write_enable_m;
  22.425 -wire write_enable_q_m;
  22.426 -reg write_enable_w;
  22.427 -wire write_enable_q_w;
  22.428 -wire read_enable_0_d;                           // Register file read enable 0
  22.429 -wire [`LM32_REG_IDX_RNG] read_idx_0_d;          // Register file read index 0
  22.430 -wire read_enable_1_d;                           // Register file read enable 1
  22.431 -wire [`LM32_REG_IDX_RNG] read_idx_1_d;          // Register file read index 1
  22.432 -wire [`LM32_REG_IDX_RNG] write_idx_d;           // Register file write index
  22.433 -reg [`LM32_REG_IDX_RNG] write_idx_x;            
  22.434 -reg [`LM32_REG_IDX_RNG] write_idx_m;
  22.435 -reg [`LM32_REG_IDX_RNG] write_idx_w;
  22.436 -wire [`LM32_CSR_RNG] csr_d;                     // CSR read/write index
  22.437 -reg  [`LM32_CSR_RNG] csr_x;                  
  22.438 -wire [`LM32_CONDITION_RNG] condition_d;         // Branch condition
  22.439 -reg [`LM32_CONDITION_RNG] condition_x;          
  22.440 -`ifdef CFG_DEBUG_ENABLED
  22.441 -wire break_d;                                   // Indicates a break instruction
  22.442 -reg break_x;                                    
  22.443 -`endif
  22.444 -wire scall_d;                                   // Indicates a scall instruction
  22.445 -reg scall_x;    
  22.446 -wire eret_d;                                    // Indicates an eret instruction
  22.447 -reg eret_x;
  22.448 -wire eret_q_x;
  22.449 -reg eret_m;
  22.450 -`ifdef CFG_TRACE_ENABLED
  22.451 -reg eret_w;
  22.452 -`endif
  22.453 -`ifdef CFG_DEBUG_ENABLED
  22.454 -wire bret_d;                                    // Indicates a bret instruction
  22.455 -reg bret_x;
  22.456 -wire bret_q_x;
  22.457 -reg bret_m;
  22.458 -`ifdef CFG_TRACE_ENABLED
  22.459 -reg bret_w;
  22.460 -`endif
  22.461 -`endif
  22.462 -wire csr_write_enable_d;                        // CSR write enable
  22.463 -reg csr_write_enable_x;
  22.464 -wire csr_write_enable_q_x;
  22.465 -`ifdef CFG_USER_ENABLED
  22.466 -wire [`LM32_USER_OPCODE_RNG] user_opcode_d;     // User-defined instruction opcode
  22.467 -`endif
  22.468 -
  22.469 -`ifdef CFG_BUS_ERRORS_ENABLED
  22.470 -wire bus_error_d;                               // Indicates an bus error occured while fetching the instruction in this pipeline stage
  22.471 -reg bus_error_x;
  22.472 -reg data_bus_error_exception_m;
  22.473 -reg [`LM32_PC_RNG] memop_pc_w;
  22.474 -`endif
  22.475 -
  22.476 -reg [`LM32_WORD_RNG] d_result_0;                // Result of instruction in D stage (operand 0)
  22.477 -reg [`LM32_WORD_RNG] d_result_1;                // Result of instruction in D stage (operand 1)
  22.478 -reg [`LM32_WORD_RNG] x_result;                  // Result of instruction in X stage
  22.479 -reg [`LM32_WORD_RNG] m_result;                  // Result of instruction in M stage
  22.480 -reg [`LM32_WORD_RNG] w_result;                  // Result of instruction in W stage
  22.481 -
  22.482 -reg [`LM32_WORD_RNG] operand_0_x;               // Operand 0 for X stage instruction
  22.483 -reg [`LM32_WORD_RNG] operand_1_x;               // Operand 1 for X stage instruction
  22.484 -reg [`LM32_WORD_RNG] store_operand_x;           // Data read from register to store
  22.485 -reg [`LM32_WORD_RNG] operand_m;                 // Operand for M stage instruction
  22.486 -reg [`LM32_WORD_RNG] operand_w;                 // Operand for W stage instruction
  22.487 -
  22.488 -// To/from register file
  22.489 -`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
  22.490 -reg [`LM32_WORD_RNG] reg_data_live_0;          
  22.491 -reg [`LM32_WORD_RNG] reg_data_live_1;  
  22.492 -reg use_buf;                                    // Whether to use reg_data_live or reg_data_buf
  22.493 -reg [`LM32_WORD_RNG] reg_data_buf_0;
  22.494 -reg [`LM32_WORD_RNG] reg_data_buf_1;
  22.495 -`endif
  22.496 -`ifdef LM32_EBR_REGISTER_FILE
  22.497 -`else
  22.498 -reg [`LM32_WORD_RNG] registers[0:(1<<`LM32_REG_IDX_WIDTH)-1];   // Register file
  22.499 -`endif
  22.500 -wire [`LM32_WORD_RNG] reg_data_0;               // Register file read port 0 data         
  22.501 -wire [`LM32_WORD_RNG] reg_data_1;               // Register file read port 1 data
  22.502 -reg [`LM32_WORD_RNG] bypass_data_0;             // Register value 0 after bypassing
  22.503 -reg [`LM32_WORD_RNG] bypass_data_1;             // Register value 1 after bypassing
  22.504 -wire reg_write_enable_q_w;
  22.505 -
  22.506 -reg interlock;                                  // Indicates pipeline should be stalled because of a read-after-write hazzard
  22.507 -
  22.508 -wire stall_a;                                   // Stall instruction in A pipeline stage
  22.509 -wire stall_f;                                   // Stall instruction in F pipeline stage
  22.510 -wire stall_d;                                   // Stall instruction in D pipeline stage
  22.511 -wire stall_x;                                   // Stall instruction in X pipeline stage
  22.512 -wire stall_m;                                   // Stall instruction in M pipeline stage
  22.513 -
  22.514 -// To/from adder
  22.515 -wire adder_op_d;                                // Whether to add or subtract
  22.516 -reg adder_op_x;                                 
  22.517 -reg adder_op_x_n;                               // Inverted version of adder_op_x
  22.518 -wire [`LM32_WORD_RNG] adder_result_x;           // Result from adder
  22.519 -wire adder_overflow_x;                          // Whether a signed overflow occured
  22.520 -wire adder_carry_n_x;                           // Whether a carry was generated
  22.521 -
  22.522 -// To/from logical operations unit
  22.523 -wire [`LM32_LOGIC_OP_RNG] logic_op_d;           // Which operation to perform
  22.524 -reg [`LM32_LOGIC_OP_RNG] logic_op_x;            
  22.525 -wire [`LM32_WORD_RNG] logic_result_x;           // Result of logical operation
  22.526 -
  22.527 -`ifdef CFG_SIGN_EXTEND_ENABLED
  22.528 -// From sign-extension unit
  22.529 -wire [`LM32_WORD_RNG] sextb_result_x;           // Result of byte sign-extension
  22.530 -wire [`LM32_WORD_RNG] sexth_result_x;           // Result of half-word sign-extenstion
  22.531 -wire [`LM32_WORD_RNG] sext_result_x;            // Result of sign-extension specified by instruction
  22.532 -`endif
  22.533 -
  22.534 -// To/from shifter
  22.535 -`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  22.536 -`ifdef CFG_ROTATE_ENABLED
  22.537 -wire rotate_d;                                  // Whether we should rotate or shift
  22.538 -reg rotate_x;                                    
  22.539 -`endif
  22.540 -wire direction_d;                               // Which direction to shift in
  22.541 -reg direction_x;                                        
  22.542 -wire [`LM32_WORD_RNG] shifter_result_m;         // Result of shifter
  22.543 -`endif
  22.544 -`ifdef CFG_MC_BARREL_SHIFT_ENABLED
  22.545 -wire shift_left_d;                              // Indicates whether to perform a left shift or not
  22.546 -wire shift_left_q_d;
  22.547 -wire shift_right_d;                             // Indicates whether to perform a right shift or not
  22.548 -wire shift_right_q_d;
  22.549 -`endif
  22.550 -`ifdef LM32_NO_BARREL_SHIFT
  22.551 -wire [`LM32_WORD_RNG] shifter_result_x;         // Result of single-bit right shifter
  22.552 -`endif
  22.553 -
  22.554 -// To/from multiplier
  22.555 -`ifdef LM32_MULTIPLY_ENABLED
  22.556 -wire [`LM32_WORD_RNG] multiplier_result_w;      // Result from multiplier
  22.557 -`endif
  22.558 -`ifdef CFG_MC_MULTIPLY_ENABLED
  22.559 -wire multiply_d;                                // Indicates whether to perform a multiply or not
  22.560 -wire multiply_q_d;
  22.561 -`endif
  22.562 -
  22.563 -// To/from divider
  22.564 -`ifdef CFG_MC_DIVIDE_ENABLED
  22.565 -wire divide_d;                                  // Indicates whether to perform a divider or not
  22.566 -wire divide_q_d;
  22.567 -wire modulus_d;
  22.568 -wire modulus_q_d;
  22.569 -wire divide_by_zero_x;                          // Indicates an attempt was made to divide by zero
  22.570 -`endif
  22.571 -
  22.572 -// To from multi-cycle arithmetic unit
  22.573 -`ifdef LM32_MC_ARITHMETIC_ENABLED
  22.574 -wire mc_stall_request_x;                        // Multi-cycle arithmetic unit stall request
  22.575 -wire [`LM32_WORD_RNG] mc_result_x;
  22.576 -`endif
  22.577 -
  22.578 -// From CSRs
  22.579 -`ifdef CFG_INTERRUPTS_ENABLED
  22.580 -wire [`LM32_WORD_RNG] interrupt_csr_read_data_x;// Data read from interrupt CSRs
  22.581 -`endif
  22.582 -wire [`LM32_WORD_RNG] cfg;                      // Configuration CSR
  22.583 -wire [`LM32_WORD_RNG] cfg2;                     // Extended Configuration CSR
  22.584 -`ifdef CFG_CYCLE_COUNTER_ENABLED
  22.585 -reg [`LM32_WORD_RNG] cc;                        // Cycle counter CSR
  22.586 -`endif
  22.587 -reg [`LM32_WORD_RNG] csr_read_data_x;           // Data read from CSRs
  22.588 -
  22.589 -// To/from instruction unit
  22.590 -wire [`LM32_PC_RNG] pc_f;                       // PC of instruction in F stage
  22.591 -wire [`LM32_PC_RNG] pc_d;                       // PC of instruction in D stage
  22.592 -wire [`LM32_PC_RNG] pc_x;                       // PC of instruction in X stage
  22.593 -wire [`LM32_PC_RNG] pc_m;                       // PC of instruction in M stage
  22.594 -wire [`LM32_PC_RNG] pc_w;                       // PC of instruction in W stage
  22.595 -`ifdef CFG_TRACE_ENABLED
  22.596 -reg [`LM32_PC_RNG] pc_c;                        // PC of last commited instruction
  22.597 -`endif
  22.598 -`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
  22.599 -wire [`LM32_INSTRUCTION_RNG] instruction_f;     // Instruction in F stage
  22.600 -`endif
  22.601 -//pragma attribute instruction_d preserve_signal true
  22.602 -//pragma attribute instruction_d preserve_driver true
  22.603 -wire [`LM32_INSTRUCTION_RNG] instruction_d;     // Instruction in D stage
  22.604 -`ifdef CFG_ICACHE_ENABLED
  22.605 -wire iflush;                                    // Flush instruction cache
  22.606 -wire icache_stall_request;                      // Stall pipeline because instruction cache is busy
  22.607 -wire icache_restart_request;                    // Restart instruction that caused an instruction cache miss
  22.608 -wire icache_refill_request;                     // Request to refill instruction cache
  22.609 -wire icache_refilling;                          // Indicates the instruction cache is being refilled
  22.610 -`endif
  22.611 -`ifdef CFG_IROM_ENABLED
  22.612 -wire [`LM32_WORD_RNG] irom_store_data_m;        // Store data to instruction ROM
  22.613 -wire [`LM32_WORD_RNG] irom_address_xm;          // Address to instruction ROM from load-store unit
  22.614 -wire [`LM32_WORD_RNG] irom_data_m;              // Load data from instruction ROM
  22.615 -wire irom_we_xm;                                // Indicates data needs to be written to instruction ROM
  22.616 -wire irom_stall_request_x;                      // Indicates D stage needs to be stalled on a store to instruction ROM
  22.617 -`endif
  22.618 -
  22.619 -// To/from load/store unit
  22.620 -`ifdef CFG_DCACHE_ENABLED
  22.621 -wire dflush_x;                                  // Flush data cache    
  22.622 -reg dflush_m;                                    
  22.623 -wire dcache_stall_request;                      // Stall pipeline because data cache is busy
  22.624 -wire dcache_restart_request;                    // Restart instruction that caused a data cache miss
  22.625 -wire dcache_refill_request;                     // Request to refill data cache
  22.626 -wire dcache_refilling;                          // Indicates the data cache is being refilled
  22.627 -`endif
  22.628 -wire [`LM32_WORD_RNG] load_data_w;              // Result of a load instruction
  22.629 -wire stall_wb_load;                             // Stall pipeline because of a load via the data Wishbone interface
  22.630 -
  22.631 -// To/from JTAG interface
  22.632 -`ifdef CFG_JTAG_ENABLED
  22.633 -`ifdef CFG_JTAG_UART_ENABLED
  22.634 -wire [`LM32_WORD_RNG] jtx_csr_read_data;        // Read data for JTX CSR
  22.635 -wire [`LM32_WORD_RNG] jrx_csr_read_data;        // Read data for JRX CSR
  22.636 -`endif
  22.637 -`ifdef CFG_HW_DEBUG_ENABLED
  22.638 -wire jtag_csr_write_enable;                     // Debugger CSR write enable
  22.639 -wire [`LM32_WORD_RNG] jtag_csr_write_data;      // Data to write to specified CSR
  22.640 -wire [`LM32_CSR_RNG] jtag_csr;                  // Which CSR to write
  22.641 -wire jtag_read_enable;                          
  22.642 -wire [`LM32_BYTE_RNG] jtag_read_data;
  22.643 -wire jtag_write_enable;
  22.644 -wire [`LM32_BYTE_RNG] jtag_write_data;
  22.645 -wire [`LM32_WORD_RNG] jtag_address;
  22.646 -wire jtag_access_complete;
  22.647 -`endif
  22.648 -`ifdef CFG_DEBUG_ENABLED
  22.649 -wire jtag_break;                                // Request from debugger to raise a breakpoint
  22.650 -`endif
  22.651 -`endif
  22.652 -
  22.653 -// Hazzard detection
  22.654 -wire raw_x_0;                                   // RAW hazzard between instruction in X stage and read port 0
  22.655 -wire raw_x_1;                                   // RAW hazzard between instruction in X stage and read port 1
  22.656 -wire raw_m_0;                                   // RAW hazzard between instruction in M stage and read port 0
  22.657 -wire raw_m_1;                                   // RAW hazzard between instruction in M stage and read port 1
  22.658 -wire raw_w_0;                                   // RAW hazzard between instruction in W stage and read port 0
  22.659 -wire raw_w_1;                                   // RAW hazzard between instruction in W stage and read port 1
  22.660 -
  22.661 -// Control flow
  22.662 -wire cmp_zero;                                  // Result of comparison is zero
  22.663 -wire cmp_negative;                              // Result of comparison is negative
  22.664 -wire cmp_overflow;                              // Comparison produced an overflow
  22.665 -wire cmp_carry_n;                               // Comparison produced a carry, inverted
  22.666 -reg condition_met_x;                            // Condition of branch instruction is met
  22.667 -reg condition_met_m;
  22.668 -`ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
  22.669 -wire branch_taken_x;                            // Branch is taken in X stage
  22.670 -`endif
  22.671 -wire branch_taken_m;                            // Branch is taken in M stage
  22.672 -
  22.673 -wire kill_f;                                    // Kill instruction in F stage
  22.674 -wire kill_d;                                    // Kill instruction in D stage
  22.675 -wire kill_x;                                    // Kill instruction in X stage
  22.676 -wire kill_m;                                    // Kill instruction in M stage
  22.677 -wire kill_w;                                    // Kill instruction in W stage
  22.678 -
  22.679 -reg [`LM32_PC_WIDTH+2-1:8] eba;                 // Exception Base Address (EBA) CSR
  22.680 -`ifdef CFG_DEBUG_ENABLED
  22.681 -reg [`LM32_PC_WIDTH+2-1:8] deba;                // Debug Exception Base Address (DEBA) CSR
  22.682 -`endif
  22.683 -reg [`LM32_EID_RNG] eid_x;                      // Exception ID in X stage
  22.684 -`ifdef CFG_TRACE_ENABLED
  22.685 -reg [`LM32_EID_RNG] eid_m;                      // Exception ID in M stage
  22.686 -reg [`LM32_EID_RNG] eid_w;                      // Exception ID in W stage
  22.687 -`endif
  22.688 -
  22.689 -`ifdef CFG_DEBUG_ENABLED
  22.690 -`ifdef LM32_SINGLE_STEP_ENABLED
  22.691 -wire dc_ss;                                     // Is single-step enabled
  22.692 -`endif
  22.693 -wire dc_re;                                     // Remap all exceptions
  22.694 -wire exception_x;                               // An exception occured in the X stage
  22.695 -reg exception_m;                                // An instruction that caused an exception is in the M stage
  22.696 -wire debug_exception_x;                         // Indicates if a debug exception has occured
  22.697 -reg debug_exception_m;
  22.698 -reg debug_exception_w;
  22.699 -wire debug_exception_q_w;
  22.700 -wire non_debug_exception_x;                     // Indicates if a non debug exception has occured
  22.701 -reg non_debug_exception_m;
  22.702 -reg non_debug_exception_w;
  22.703 -wire non_debug_exception_q_w;
  22.704 -`else
  22.705 -wire exception_x;                               // Indicates if a debug exception has occured
  22.706 -reg exception_m;
  22.707 -reg exception_w;
  22.708 -wire exception_q_w;
  22.709 -`endif
  22.710 -
  22.711 -`ifdef CFG_DEBUG_ENABLED
  22.712 -`ifdef CFG_JTAG_ENABLED
  22.713 -wire reset_exception;                           // Indicates if a reset exception has occured
  22.714 -`endif
  22.715 -`endif
  22.716 -`ifdef CFG_INTERRUPTS_ENABLED
  22.717 -wire interrupt_exception;                       // Indicates if an interrupt exception has occured
  22.718 -`endif
  22.719 -`ifdef CFG_DEBUG_ENABLED
  22.720 -wire breakpoint_exception;                      // Indicates if a breakpoint exception has occured
  22.721 -wire watchpoint_exception;                      // Indicates if a watchpoint exception has occured
  22.722 -`endif
  22.723 -`ifdef CFG_BUS_ERRORS_ENABLED
  22.724 -wire instruction_bus_error_exception;           // Indicates if an instruction bus error exception has occured
  22.725 -wire data_bus_error_exception;                  // Indicates if a data bus error exception has occured
  22.726 -`endif
  22.727 -`ifdef CFG_MC_DIVIDE_ENABLED
  22.728 -wire divide_by_zero_exception;                  // Indicates if a divide by zero exception has occured
  22.729 -`endif
  22.730 -wire system_call_exception;                     // Indicates if a system call exception has occured
  22.731 -
  22.732 -`ifdef CFG_BUS_ERRORS_ENABLED
  22.733 -reg data_bus_error_seen;                        // Indicates if a data bus error was seen
  22.734 -`endif
  22.735 -
  22.736 -/////////////////////////////////////////////////////
  22.737 -// Functions
  22.738 -/////////////////////////////////////////////////////
  22.739 -
  22.740 -`include "lm32_functions.v"
  22.741 -
  22.742 -/////////////////////////////////////////////////////
  22.743 -// Instantiations
  22.744 -///////////////////////////////////////////////////// 
  22.745 -
  22.746 -// Instruction unit
  22.747 -lm32_instruction_unit #(
  22.748 -    .associativity          (icache_associativity),
  22.749 -    .sets                   (icache_sets),
  22.750 -    .bytes_per_line         (icache_bytes_per_line),
  22.751 -    .base_address           (icache_base_address),
  22.752 -    .limit                  (icache_limit)
  22.753 -  ) instruction_unit (
  22.754 -    // ----- Inputs -------
  22.755 -    .clk_i                  (clk_i),
  22.756 -    .rst_i                  (rst_i),
  22.757 -    // From pipeline
  22.758 -    .stall_a                (stall_a),
  22.759 -    .stall_f                (stall_f),
  22.760 -    .stall_d                (stall_d),
  22.761 -    .stall_x                (stall_x),
  22.762 -    .stall_m                (stall_m),
  22.763 -    .valid_f                (valid_f),
  22.764 -    .valid_d                (valid_d),
  22.765 -    .kill_f                 (kill_f),
  22.766 -    .branch_predict_taken_d (branch_predict_taken_d),
  22.767 -    .branch_predict_address_d (branch_predict_address_d),
  22.768 -`ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
  22.769 -    .branch_taken_x         (branch_taken_x),
  22.770 -    .branch_target_x        (branch_target_x),
  22.771 -`endif
  22.772 -    .exception_m            (exception_m),
  22.773 -    .branch_taken_m         (branch_taken_m),
  22.774 -    .branch_mispredict_taken_m (branch_mispredict_taken_m),
  22.775 -    .branch_target_m        (branch_target_m),
  22.776 -`ifdef CFG_ICACHE_ENABLED
  22.777 -    .iflush                 (iflush),
  22.778 -`endif
  22.779 -`ifdef CFG_IROM_ENABLED
  22.780 -    .irom_store_data_m      (irom_store_data_m),
  22.781 -    .irom_address_xm        (irom_address_xm),
  22.782 -    .irom_we_xm             (irom_we_xm),
  22.783 -`endif
  22.784 -`ifdef CFG_DCACHE_ENABLED
  22.785 -    .dcache_restart_request (dcache_restart_request),
  22.786 -    .dcache_refill_request  (dcache_refill_request),
  22.787 -    .dcache_refilling       (dcache_refilling),
  22.788 -`endif        
  22.789 -`ifdef CFG_IWB_ENABLED
  22.790 -    // From Wishbone
  22.791 -    .i_dat_i                (I_DAT_I),
  22.792 -    .i_ack_i                (I_ACK_I),
  22.793 -    .i_err_i                (I_ERR_I),
  22.794 -`endif
  22.795 -`ifdef CFG_HW_DEBUG_ENABLED
  22.796 -    .jtag_read_enable       (jtag_read_enable),
  22.797 -    .jtag_write_enable      (jtag_write_enable),
  22.798 -    .jtag_write_data        (jtag_write_data),
  22.799 -    .jtag_address           (jtag_address),
  22.800 -`endif
  22.801 -    // ----- Outputs -------
  22.802 -    // To pipeline
  22.803 -    .pc_f                   (pc_f),
  22.804 -    .pc_d                   (pc_d),
  22.805 -    .pc_x                   (pc_x),
  22.806 -    .pc_m                   (pc_m),
  22.807 -    .pc_w                   (pc_w),
  22.808 -`ifdef CFG_ICACHE_ENABLED
  22.809 -    .icache_stall_request   (icache_stall_request),
  22.810 -    .icache_restart_request (icache_restart_request),
  22.811 -    .icache_refill_request  (icache_refill_request),
  22.812 -    .icache_refilling       (icache_refilling),
  22.813 -`endif
  22.814 -`ifdef CFG_IROM_ENABLED
  22.815 -    .irom_data_m            (irom_data_m),
  22.816 -`endif
  22.817 -`ifdef CFG_IWB_ENABLED
  22.818 -    // To Wishbone
  22.819 -    .i_dat_o                (I_DAT_O),
  22.820 -    .i_adr_o                (I_ADR_O),
  22.821 -    .i_cyc_o                (I_CYC_O),
  22.822 -    .i_sel_o                (I_SEL_O),
  22.823 -    .i_stb_o                (I_STB_O),
  22.824 -    .i_we_o                 (I_WE_O),
  22.825 -    .i_cti_o                (I_CTI_O),
  22.826 -    .i_lock_o               (I_LOCK_O),
  22.827 -    .i_bte_o                (I_BTE_O),
  22.828 -`endif
  22.829 -`ifdef CFG_HW_DEBUG_ENABLED
  22.830 -    .jtag_read_data         (jtag_read_data),
  22.831 -    .jtag_access_complete   (jtag_access_complete),
  22.832 -`endif
  22.833 -`ifdef CFG_BUS_ERRORS_ENABLED
  22.834 -    .bus_error_d            (bus_error_d),
  22.835 -`endif
  22.836 -`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
  22.837 -    .instruction_f          (instruction_f),
  22.838 -`endif
  22.839 -    .instruction_d          (instruction_d)
  22.840 -    );
  22.841 -
  22.842 -// Instruction decoder
  22.843 -lm32_decoder decoder (
  22.844 -    // ----- Inputs -------
  22.845 -    .instruction            (instruction_d),
  22.846 -    // ----- Outputs -------
  22.847 -    .d_result_sel_0         (d_result_sel_0_d),
  22.848 -    .d_result_sel_1         (d_result_sel_1_d),
  22.849 -    .x_result_sel_csr       (x_result_sel_csr_d),
  22.850 -`ifdef LM32_MC_ARITHMETIC_ENABLED
  22.851 -    .x_result_sel_mc_arith  (x_result_sel_mc_arith_d),
  22.852 -`endif
  22.853 -`ifdef LM32_NO_BARREL_SHIFT    
  22.854 -    .x_result_sel_shift     (x_result_sel_shift_d),
  22.855 -`endif
  22.856 -`ifdef CFG_SIGN_EXTEND_ENABLED
  22.857 -    .x_result_sel_sext      (x_result_sel_sext_d),
  22.858 -`endif    
  22.859 -    .x_result_sel_logic     (x_result_sel_logic_d),
  22.860 -`ifdef CFG_USER_ENABLED
  22.861 -    .x_result_sel_user      (x_result_sel_user_d),
  22.862 -`endif
  22.863 -    .x_result_sel_add       (x_result_sel_add_d),
  22.864 -    .m_result_sel_compare   (m_result_sel_compare_d),
  22.865 -`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  22.866 -    .m_result_sel_shift     (m_result_sel_shift_d),  
  22.867 -`endif    
  22.868 -    .w_result_sel_load      (w_result_sel_load_d),
  22.869 -`ifdef CFG_PL_MULTIPLY_ENABLED
  22.870 -    .w_result_sel_mul       (w_result_sel_mul_d),
  22.871 -`endif
  22.872 -    .x_bypass_enable        (x_bypass_enable_d),
  22.873 -    .m_bypass_enable        (m_bypass_enable_d),
  22.874 -    .read_enable_0          (read_enable_0_d),
  22.875 -    .read_idx_0             (read_idx_0_d),
  22.876 -    .read_enable_1          (read_enable_1_d),
  22.877 -    .read_idx_1             (read_idx_1_d),
  22.878 -    .write_enable           (write_enable_d),
  22.879 -    .write_idx              (write_idx_d),
  22.880 -    .immediate              (immediate_d),
  22.881 -    .branch_offset          (branch_offset_d),
  22.882 -    .load                   (load_d),
  22.883 -    .store                  (store_d),
  22.884 -    .size                   (size_d),
  22.885 -    .sign_extend            (sign_extend_d),
  22.886 -    .adder_op               (adder_op_d),
  22.887 -    .logic_op               (logic_op_d),
  22.888 -`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  22.889 -    .direction              (direction_d),
  22.890 -`endif
  22.891 -`ifdef CFG_MC_BARREL_SHIFT_ENABLED
  22.892 -    .shift_left             (shift_left_d),
  22.893 -    .shift_right            (shift_right_d),
  22.894 -`endif
  22.895 -`ifdef CFG_MC_MULTIPLY_ENABLED
  22.896 -    .multiply               (multiply_d),
  22.897 -`endif
  22.898 -`ifdef CFG_MC_DIVIDE_ENABLED
  22.899 -    .divide                 (divide_d),
  22.900 -    .modulus                (modulus_d),
  22.901 -`endif
  22.902 -    .branch                 (branch_d),
  22.903 -    .bi_unconditional       (bi_unconditional),
  22.904 -    .bi_conditional         (bi_conditional),
  22.905 -    .branch_reg             (branch_reg_d),
  22.906 -    .condition              (condition_d),
  22.907 -`ifdef CFG_DEBUG_ENABLED
  22.908 -    .break_opcode           (break_d),
  22.909 -`endif
  22.910 -    .scall                  (scall_d),
  22.911 -    .eret                   (eret_d),
  22.912 -`ifdef CFG_DEBUG_ENABLED
  22.913 -    .bret                   (bret_d),
  22.914 -`endif
  22.915 -`ifdef CFG_USER_ENABLED
  22.916 -    .user_opcode            (user_opcode_d),
  22.917 -`endif
  22.918 -    .csr_write_enable       (csr_write_enable_d)
  22.919 -    ); 
  22.920 -
  22.921 -// Load/store unit       
  22.922 -lm32_load_store_unit #(
  22.923 -    .associativity          (dcache_associativity),
  22.924 -    .sets                   (dcache_sets),
  22.925 -    .bytes_per_line         (dcache_bytes_per_line),
  22.926 -    .base_address           (dcache_base_address),
  22.927 -    .limit                  (dcache_limit)
  22.928 -  ) load_store_unit (
  22.929 -    // ----- Inputs -------
  22.930 -    .clk_i                  (clk_i),
  22.931 -    .rst_i                  (rst_i),
  22.932 -    // From pipeline
  22.933 -    .stall_a                (stall_a),
  22.934 -    .stall_x                (stall_x),
  22.935 -    .stall_m                (stall_m),
  22.936 -    .kill_m                 (kill_m),
  22.937 -    .exception_m            (exception_m),
  22.938 -    .store_operand_x        (store_operand_x),
  22.939 -    .load_store_address_x   (adder_result_x),
  22.940 -    .load_store_address_m   (operand_m),
  22.941 -    .load_store_address_w   (operand_w[1:0]),
  22.942 -    .load_x                 (load_x),
  22.943 -    .store_x                (store_x),
  22.944 -    .load_q_x               (load_q_x),
  22.945 -    .store_q_x              (store_q_x),
  22.946 -    .load_q_m               (load_q_m),
  22.947 -    .store_q_m              (store_q_m),
  22.948 -    .sign_extend_x          (sign_extend_x),
  22.949 -    .size_x                 (size_x),
  22.950 -`ifdef CFG_DCACHE_ENABLED
  22.951 -    .dflush                 (dflush_m),
  22.952 -`endif
  22.953 -`ifdef CFG_IROM_ENABLED
  22.954 -    .irom_data_m            (irom_data_m),
  22.955 -`endif
  22.956 -    // From Wishbone
  22.957 -    .d_dat_i                (D_DAT_I),
  22.958 -    .d_ack_i                (D_ACK_I),
  22.959 -    .d_err_i                (D_ERR_I),
  22.960 -    .d_rty_i                (D_RTY_I),
  22.961 -    // ----- Outputs -------
  22.962 -    // To pipeline
  22.963 -`ifdef CFG_DCACHE_ENABLED
  22.964 -    .dcache_refill_request  (dcache_refill_request),
  22.965 -    .dcache_restart_request (dcache_restart_request),
  22.966 -    .dcache_stall_request   (dcache_stall_request),
  22.967 -    .dcache_refilling       (dcache_refilling),
  22.968 -`endif    
  22.969 -`ifdef CFG_IROM_ENABLED
  22.970 -    .irom_store_data_m      (irom_store_data_m),
  22.971 -    .irom_address_xm        (irom_address_xm),
  22.972 -    .irom_we_xm             (irom_we_xm),
  22.973 -    .irom_stall_request_x   (irom_stall_request_x),
  22.974 -`endif
  22.975 -    .load_data_w            (load_data_w),
  22.976 -    .stall_wb_load          (stall_wb_load),
  22.977 -    // To Wishbone
  22.978 -    .d_dat_o                (D_DAT_O),
  22.979 -    .d_adr_o                (D_ADR_O),
  22.980 -    .d_cyc_o                (D_CYC_O),
  22.981 -    .d_sel_o                (D_SEL_O),
  22.982 -    .d_stb_o                (D_STB_O),
  22.983 -    .d_we_o                 (D_WE_O),
  22.984 -    .d_cti_o                (D_CTI_O),
  22.985 -    .d_lock_o               (D_LOCK_O),
  22.986 -    .d_bte_o                (D_BTE_O)
  22.987 -    );      
  22.988 -       
  22.989 -// Adder       
  22.990 -lm32_adder adder (
  22.991 -    // ----- Inputs -------
  22.992 -    .adder_op_x             (adder_op_x),
  22.993 -    .adder_op_x_n           (adder_op_x_n),
  22.994 -    .operand_0_x            (operand_0_x),
  22.995 -    .operand_1_x            (operand_1_x),
  22.996 -    // ----- Outputs -------
  22.997 -    .adder_result_x         (adder_result_x),
  22.998 -    .adder_carry_n_x        (adder_carry_n_x),
  22.999 -    .adder_overflow_x       (adder_overflow_x)
 22.1000 -    );
 22.1001 -
 22.1002 -// Logic operations
 22.1003 -lm32_logic_op logic_op (
 22.1004 -    // ----- Inputs -------
 22.1005 -    .logic_op_x             (logic_op_x),
 22.1006 -    .operand_0_x            (operand_0_x),
 22.1007 -
 22.1008 -    .operand_1_x            (operand_1_x),
 22.1009 -    // ----- Outputs -------
 22.1010 -    .logic_result_x         (logic_result_x)
 22.1011 -    );
 22.1012 -              
 22.1013 -`ifdef CFG_PL_BARREL_SHIFT_ENABLED
 22.1014 -// Pipelined barrel-shifter
 22.1015 -lm32_shifter shifter (
 22.1016 -    // ----- Inputs -------
 22.1017 -    .clk_i                  (clk_i),
 22.1018 -    .rst_i                  (rst_i),
 22.1019 -    .stall_x                (stall_x),
 22.1020 -    .direction_x            (direction_x),
 22.1021 -    .sign_extend_x          (sign_extend_x),
 22.1022 -    .operand_0_x            (operand_0_x),
 22.1023 -    .operand_1_x            (operand_1_x),
 22.1024 -    // ----- Outputs -------
 22.1025 -    .shifter_result_m       (shifter_result_m)
 22.1026 -    );
 22.1027 -`endif
 22.1028 -
 22.1029 -`ifdef CFG_PL_MULTIPLY_ENABLED
 22.1030 -// Pipeline fixed-point multiplier
 22.1031 -lm32_multiplier multiplier (
 22.1032 -    // ----- Inputs -------
 22.1033 -    .clk_i                  (clk_i),
 22.1034 -    .rst_i                  (rst_i),
 22.1035 -    .stall_x                (stall_x),
 22.1036 -    .stall_m                (stall_m),
 22.1037 -    .operand_0              (d_result_0),
 22.1038 -    .operand_1              (d_result_1),
 22.1039 -    // ----- Outputs -------
 22.1040 -    .result                 (multiplier_result_w)    
 22.1041 -    );
 22.1042 -`endif
 22.1043 -
 22.1044 -`ifdef LM32_MC_ARITHMETIC_ENABLED
 22.1045 -// Multi-cycle arithmetic
 22.1046 -lm32_mc_arithmetic mc_arithmetic (
 22.1047 -    // ----- Inputs -------
 22.1048 -    .clk_i                  (clk_i),
 22.1049 -    .rst_i                  (rst_i),
 22.1050 -    .stall_d                (stall_d),
 22.1051 -    .kill_x                 (kill_x),
 22.1052 -`ifdef CFG_MC_DIVIDE_ENABLED                  
 22.1053 -    .divide_d               (divide_q_d),
 22.1054 -    .modulus_d              (modulus_q_d),
 22.1055 -`endif
 22.1056 -`ifdef CFG_MC_MULTIPLY_ENABLED        
 22.1057 -    .multiply_d             (multiply_q_d),
 22.1058 -`endif
 22.1059 -`ifdef CFG_MC_BARREL_SHIFT_ENABLED
 22.1060 -    .shift_left_d           (shift_left_q_d),
 22.1061 -    .shift_right_d          (shift_right_q_d),
 22.1062 -    .sign_extend_d          (sign_extend_d),
 22.1063 -`endif    
 22.1064 -    .operand_0_d            (d_result_0),
 22.1065 -    .operand_1_d            (d_result_1),
 22.1066 -    // ----- Outputs -------
 22.1067 -    .result_x               (mc_result_x),
 22.1068 -`ifdef CFG_MC_DIVIDE_ENABLED                  
 22.1069 -    .divide_by_zero_x       (divide_by_zero_x),
 22.1070 -`endif
 22.1071 -    .stall_request_x        (mc_stall_request_x)
 22.1072 -    );
 22.1073 -`endif
 22.1074 -              
 22.1075 -`ifdef CFG_INTERRUPTS_ENABLED
 22.1076 -// Interrupt unit
 22.1077 -lm32_interrupt interrupt_unit (
 22.1078 -    // ----- Inputs -------
 22.1079 -    .clk_i                  (clk_i),
 22.1080 -    .rst_i                  (rst_i),
 22.1081 -    // From external devices
 22.1082 -    .interrupt              (interrupt),
 22.1083 -    // From pipeline
 22.1084 -    .stall_x                (stall_x),
 22.1085 -`ifdef CFG_DEBUG_ENABLED
 22.1086 -    .non_debug_exception    (non_debug_exception_q_w),
 22.1087 -    .debug_exception        (debug_exception_q_w),
 22.1088 -`else
 22.1089 -    .exception              (exception_q_w),
 22.1090 -`endif
 22.1091 -    .eret_q_x               (eret_q_x),
 22.1092 -`ifdef CFG_DEBUG_ENABLED
 22.1093 -    .bret_q_x               (bret_q_x),
 22.1094 -`endif
 22.1095 -    .csr                    (csr_x),
 22.1096 -    .csr_write_data         (operand_1_x),
 22.1097 -    .csr_write_enable       (csr_write_enable_q_x),
 22.1098 -    // ----- Outputs -------
 22.1099 -    .interrupt_exception    (interrupt_exception),
 22.1100 -    // To pipeline
 22.1101 -    .csr_read_data          (interrupt_csr_read_data_x)
 22.1102 -    );
 22.1103 -`endif
 22.1104 -
 22.1105 -`ifdef CFG_JTAG_ENABLED
 22.1106 -// JTAG interface
 22.1107 -lm32_jtag jtag (
 22.1108 -    // ----- Inputs -------
 22.1109 -    .clk_i                  (clk_i),
 22.1110 -    .rst_i                  (rst_i),
 22.1111 -    // From JTAG
 22.1112 -    .jtag_clk               (jtag_clk),
 22.1113 -    .jtag_update            (jtag_update),
 22.1114 -    .jtag_reg_q             (jtag_reg_q),
 22.1115 -    .jtag_reg_addr_q        (jtag_reg_addr_q),
 22.1116 -    // From pipeline
 22.1117 -`ifdef CFG_JTAG_UART_ENABLED
 22.1118 -    .csr                    (csr_x),
 22.1119 -    .csr_write_data         (operand_1_x),
 22.1120 -    .csr_write_enable       (csr_write_enable_q_x),
 22.1121 -    .stall_x                (stall_x),
 22.1122 -`endif
 22.1123 -`ifdef CFG_HW_DEBUG_ENABLED
 22.1124 -    .jtag_read_data         (jtag_read_data),
 22.1125 -    .jtag_access_complete   (jtag_access_complete),
 22.1126 -`endif
 22.1127 -`ifdef CFG_DEBUG_ENABLED
 22.1128 -    .exception_q_w          (debug_exception_q_w || non_debug_exception_q_w),
 22.1129 -`endif    
 22.1130 -    // ----- Outputs -------
 22.1131 -    // To pipeline
 22.1132 -`ifdef CFG_JTAG_UART_ENABLED
 22.1133 -    .jtx_csr_read_data      (jtx_csr_read_data),
 22.1134 -    .jrx_csr_read_data      (jrx_csr_read_data),
 22.1135 -`endif
 22.1136 -`ifdef CFG_HW_DEBUG_ENABLED
 22.1137 -    .jtag_csr_write_enable  (jtag_csr_write_enable),
 22.1138 -    .jtag_csr_write_data    (jtag_csr_write_data),
 22.1139 -    .jtag_csr               (jtag_csr),
 22.1140 -    .jtag_read_enable       (jtag_read_enable),
 22.1141 -    .jtag_write_enable      (jtag_write_enable),
 22.1142 -    .jtag_write_data        (jtag_write_data),
 22.1143 -    .jtag_address           (jtag_address),
 22.1144 -`endif
 22.1145 -`ifdef CFG_DEBUG_ENABLED
 22.1146 -    .jtag_break             (jtag_break),
 22.1147 -    .jtag_reset             (reset_exception),
 22.1148 -`endif
 22.1149 -    // To JTAG 
 22.1150 -    .jtag_reg_d             (jtag_reg_d),
 22.1151 -    .jtag_reg_addr_d        (jtag_reg_addr_d)
 22.1152 -    );
 22.1153 -`endif
 22.1154 -
 22.1155 -`ifdef CFG_DEBUG_ENABLED
 22.1156 -// Debug unit
 22.1157 -lm32_debug #(
 22.1158 -    .breakpoints            (breakpoints),
 22.1159 -    .watchpoints            (watchpoints)
 22.1160 -  ) hw_debug (
 22.1161 -    // ----- Inputs -------
 22.1162 -    .clk_i                  (clk_i), 
 22.1163 -    .rst_i                  (rst_i),
 22.1164 -    .pc_x                   (pc_x),
 22.1165 -    .load_x                 (load_x),
 22.1166 -    .store_x                (store_x),
 22.1167 -    .load_store_address_x   (adder_result_x),
 22.1168 -    .csr_write_enable_x     (csr_write_enable_q_x),
 22.1169 -    .csr_write_data         (operand_1_x),
 22.1170 -    .csr_x                  (csr_x),
 22.1171 -`ifdef CFG_HW_DEBUG_ENABLED
 22.1172 -    .jtag_csr_write_enable  (jtag_csr_write_enable),
 22.1173 -    .jtag_csr_write_data    (jtag_csr_write_data),
 22.1174 -    .jtag_csr               (jtag_csr),
 22.1175 -`endif
 22.1176 -`ifdef LM32_SINGLE_STEP_ENABLED
 22.1177 -    .eret_q_x               (eret_q_x),
 22.1178 -    .bret_q_x               (bret_q_x),
 22.1179 -    .stall_x                (stall_x),
 22.1180 -    .exception_x            (exception_x),
 22.1181 -    .q_x                    (q_x),
 22.1182 -`ifdef CFG_DCACHE_ENABLED
 22.1183 -    .dcache_refill_request  (dcache_refill_request),
 22.1184 -`endif
 22.1185 -`endif
 22.1186 -    // ----- Outputs -------
 22.1187 -`ifdef LM32_SINGLE_STEP_ENABLED
 22.1188 -    .dc_ss                  (dc_ss),
 22.1189 -`endif
 22.1190 -    .dc_re                  (dc_re),
 22.1191 -    .bp_match               (bp_match),
 22.1192 -    .wp_match               (wp_match)
 22.1193 -    );
 22.1194 -`endif
 22.1195 -
 22.1196 -// Register file
 22.1197 -
 22.1198 -`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
 22.1199 -   /*----------------------------------------------------------------------
 22.1200 -    Register File is implemented using EBRs. There can be three accesses to
 22.1201 -    the register file in each cycle: two reads and one write. On-chip block
 22.1202 -    RAM has two read/write ports. To accomodate three accesses, two on-chip
 22.1203 -    block RAMs are used (each register file "write" is made to both block
 22.1204 -    RAMs).
 22.1205 -    
 22.1206 -    One limitation of the on-chip block RAMs is that one cannot perform a 
 22.1207 -    read and write to same location in a cycle (if this is done, then the
 22.1208 -    data read out is indeterminate).
 22.1209 -    ----------------------------------------------------------------------*/
 22.1210 -   wire [31:0] regfile_data_0, regfile_data_1;
 22.1211 -   reg [31:0]  w_result_d;
 22.1212 -   reg 	       regfile_raw_0, regfile_raw_0_nxt;
 22.1213 -   reg 	       regfile_raw_1, regfile_raw_1_nxt;
 22.1214 -   
 22.1215 -   /*----------------------------------------------------------------------
 22.1216 -    Check if read and write is being performed to same register in current 
 22.1217 -    cycle? This is done by comparing the read and write IDXs.
 22.1218 -    ----------------------------------------------------------------------*/
 22.1219 -   always @(reg_write_enable_q_w or write_idx_w or instruction_f)
 22.1220 -     begin
 22.1221 -	if (reg_write_enable_q_w
 22.1222 -	    && (write_idx_w == instruction_f[25:21]))
 22.1223 -	  regfile_raw_0_nxt = 1'b1;
 22.1224 -	else
 22.1225 -	  regfile_raw_0_nxt = 1'b0;
 22.1226 -	
 22.1227 -	if (reg_write_enable_q_w
 22.1228 -	    && (write_idx_w == instruction_f[20:16]))
 22.1229 -	  regfile_raw_1_nxt = 1'b1;
 22.1230 -	else
 22.1231 -	  regfile_raw_1_nxt = 1'b0;
 22.1232 -     end
 22.1233 -   
 22.1234 -   /*----------------------------------------------------------------------
 22.1235 -    Select latched (delayed) write value or data from register file. If 
 22.1236 -    read in previous cycle was performed to register written to in same
 22.1237 -    cycle, then latched (delayed) write value is selected.
 22.1238 -    ----------------------------------------------------------------------*/
 22.1239 -   always @(regfile_raw_0 or w_result_d or regfile_data_0)
 22.1240 -     if (regfile_raw_0)
 22.1241 -       reg_data_live_0 = w_result_d;
 22.1242 -     else
 22.1243 -       reg_data_live_0 = regfile_data_0;
 22.1244 -   
 22.1245 -   /*----------------------------------------------------------------------
 22.1246 -    Select latched (delayed) write value or data from register file. If 
 22.1247 -    read in previous cycle was performed to register written to in same
 22.1248 -    cycle, then latched (delayed) write value is selected.
 22.1249 -    ----------------------------------------------------------------------*/
 22.1250 -   always @(regfile_raw_1 or w_result_d or regfile_data_1)
 22.1251 -     if (regfile_raw_1)
 22.1252 -       reg_data_live_1 = w_result_d;
 22.1253 -     else
 22.1254 -       reg_data_live_1 = regfile_data_1;
 22.1255 -   
 22.1256 -   /*----------------------------------------------------------------------
 22.1257 -    Latch value written to register file
 22.1258 -    ----------------------------------------------------------------------*/
 22.1259 -   always @(posedge clk_i `CFG_RESET_SENSITIVITY)
 22.1260 -     if (rst_i == `TRUE)
 22.1261 -       begin
 22.1262 -	  regfile_raw_0 <= 1'b0;
 22.1263 -	  regfile_raw_1 <= 1'b0;
 22.1264 -	  w_result_d <= 32'b0;
 22.1265 -       end
 22.1266 -     else
 22.1267 -       begin
 22.1268 -	  regfile_raw_0 <= regfile_raw_0_nxt;
 22.1269 -	  regfile_raw_1 <= regfile_raw_1_nxt;
 22.1270 -	  w_result_d <= w_result;
 22.1271 -       end
 22.1272 -   
 22.1273 -   /*----------------------------------------------------------------------
 22.1274 -    Register file instantiation as Pseudo-Dual Port EBRs.
 22.1275 -    ----------------------------------------------------------------------*/
 22.1276 -   // Modified by GSI: removed non-portable RAM instantiation
 22.1277 -   lm32_dp_ram
 22.1278 -     #(
 22.1279 -       // ----- Parameters -----
 22.1280 -       .addr_depth(1<<5),
 22.1281 -       .addr_width(5),
 22.1282 -       .data_width(32)
 22.1283 -       )
 22.1284 -   reg_0
 22.1285 -     (
 22.1286 -      // ----- Inputs -----
 22.1287 -      .clk_i	(clk_i),
 22.1288 -      .rst_i	(rst_i), 
 22.1289 -      .we_i	(reg_write_enable_q_w),
 22.1290 -      .wdata_i	(w_result),
 22.1291 -      .waddr_i	(write_idx_w),
 22.1292 -      .raddr_i	(instruction_f[25:21]),
 22.1293 -      // ----- Outputs -----
 22.1294 -      .rdata_o	(regfile_data_0)
 22.1295 -      );
 22.1296 -
 22.1297 -   lm32_dp_ram
 22.1298 -     #(
 22.1299 -       .addr_depth(1<<5),
 22.1300 -       .addr_width(5),
 22.1301 -       .data_width(32)
 22.1302 -       )
 22.1303 -   reg_1
 22.1304 -     (
 22.1305 -      // ----- Inputs -----
 22.1306 -      .clk_i	(clk_i),
 22.1307 -      .rst_i	(rst_i), 
 22.1308 -      .we_i	(reg_write_enable_q_w),
 22.1309 -      .wdata_i	(w_result),
 22.1310 -      .waddr_i	(write_idx_w),
 22.1311 -      .raddr_i	(instruction_f[20:16]),
 22.1312 -      // ----- Outputs -----
 22.1313 -      .rdata_o	(regfile_data_1)
 22.1314 -      );
 22.1315 -`endif
 22.1316 -
 22.1317 -`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
 22.1318 -   pmi_ram_dp
 22.1319 -     #(
 22.1320 -       // ----- Parameters -----
 22.1321 -       .pmi_wr_addr_depth(1<<5),
 22.1322 -       .pmi_wr_addr_width(5),
 22.1323 -       .pmi_wr_data_width(32),
 22.1324 -       .pmi_rd_addr_depth(1<<5),
 22.1325 -       .pmi_rd_addr_width(5),
 22.1326 -       .pmi_rd_data_width(32),
 22.1327 -       .pmi_regmode("noreg"),
 22.1328 -       .pmi_gsr("enable"),
 22.1329 -       .pmi_resetmode("sync"),
 22.1330 -       .pmi_init_file("none"),
 22.1331 -       .pmi_init_file_format("binary"),
 22.1332 -       .pmi_family(`LATTICE_FAMILY),
 22.1333 -       .module_type("pmi_ram_dp")
 22.1334 -       )
 22.1335 -   reg_0
 22.1336 -     (
 22.1337 -      // ----- Inputs -----
 22.1338 -      .Data(w_result),
 22.1339 -      .WrAddress(write_idx_w),
 22.1340 -      .RdAddress(read_idx_0_d),
 22.1341 -      .WrClock(clk_i),
 22.1342 -      .RdClock(clk_n_i),
 22.1343 -      .WrClockEn(`TRUE),
 22.1344 -      .RdClockEn(stall_f == `FALSE),
 22.1345 -      .WE(reg_write_enable_q_w),
 22.1346 -      .Reset(rst_i), 
 22.1347 -      // ----- Outputs -----
 22.1348 -      .Q(reg_data_0)
 22.1349 -      );
 22.1350 -   
 22.1351 -   pmi_ram_dp
 22.1352 -     #(
 22.1353 -       // ----- Parameters -----
 22.1354 -       .pmi_wr_addr_depth(1<<5),
 22.1355 -       .pmi_wr_addr_width(5),
 22.1356 -       .pmi_wr_data_width(32),
 22.1357 -       .pmi_rd_addr_depth(1<<5),
 22.1358 -       .pmi_rd_addr_width(5),
 22.1359 -       .pmi_rd_data_width(32),
 22.1360 -       .pmi_regmode("noreg"),
 22.1361 -       .pmi_gsr("enable"),
 22.1362 -       .pmi_resetmode("sync"),
 22.1363 -       .pmi_init_file("none"),
 22.1364 -       .pmi_init_file_format("binary"),
 22.1365 -       .pmi_family(`LATTICE_FAMILY),
 22.1366 -       .module_type("pmi_ram_dp")
 22.1367 -       )
 22.1368 -   reg_1
 22.1369 -     (
 22.1370 -      // ----- Inputs -----
 22.1371 -      .Data(w_result),
 22.1372 -      .WrAddress(write_idx_w),
 22.1373 -      .RdAddress(read_idx_1_d),
 22.1374 -      .WrClock(clk_i),
 22.1375 -      .RdClock(clk_n_i),
 22.1376 -      .WrClockEn(`TRUE),
 22.1377 -      .RdClockEn(stall_f == `FALSE),
 22.1378 -      .WE(reg_write_enable_q_w),
 22.1379 -      .Reset(rst_i), 
 22.1380 -      // ----- Outputs -----
 22.1381 -      .Q(reg_data_1)
 22.1382 -      );
 22.1383 -`endif
 22.1384 -
 22.1385 -
 22.1386 -/////////////////////////////////////////////////////
 22.1387 -// Combinational Logic
 22.1388 -/////////////////////////////////////////////////////
 22.1389 -
 22.1390 -`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
 22.1391 -// Select between buffered and live data from register file
 22.1392 -assign reg_data_0 = use_buf ? reg_data_buf_0 : reg_data_live_0;
 22.1393 -assign reg_data_1 = use_buf ? reg_data_buf_1 : reg_data_live_1;
 22.1394 -`endif
 22.1395 -`ifdef LM32_EBR_REGISTER_FILE
 22.1396 -`else
 22.1397 -// Register file read ports
 22.1398 -assign reg_data_0 = registers[read_idx_0_d];
 22.1399 -assign reg_data_1 = registers[read_idx_1_d];
 22.1400 -`endif
 22.1401 -
 22.1402 -// Detect read-after-write hazzards
 22.1403 -assign raw_x_0 = (write_idx_x == read_idx_0_d) && (write_enable_q_x == `TRUE);
 22.1404 -assign raw_m_0 = (write_idx_m == read_idx_0_d) && (write_enable_q_m == `TRUE);
 22.1405 -assign raw_w_0 = (write_idx_w == read_idx_0_d) && (write_enable_q_w == `TRUE);
 22.1406 -assign raw_x_1 = (write_idx_x == read_idx_1_d) && (write_enable_q_x == `TRUE);
 22.1407 -assign raw_m_1 = (write_idx_m == read_idx_1_d) && (write_enable_q_m == `TRUE);
 22.1408 -assign raw_w_1 = (write_idx_w == read_idx_1_d) && (write_enable_q_w == `TRUE);
 22.1409 -
 22.1410 -// Interlock detection - Raise an interlock for RAW hazzards 
 22.1411 -always @(*)
 22.1412 -begin
 22.1413 -    if (   (   (x_bypass_enable_x == `FALSE)
 22.1414 -            && (   ((read_enable_0_d == `TRUE) && (raw_x_0 == `TRUE))
 22.1415 -                || ((read_enable_1_d == `TRUE) && (raw_x_1 == `TRUE))
 22.1416 -               )
 22.1417 -           )
 22.1418 -        || (   (m_bypass_enable_m == `FALSE)
 22.1419 -            && (   ((read_enable_0_d == `TRUE) && (raw_m_0 == `TRUE))
 22.1420 -                || ((read_enable_1_d == `TRUE) && (raw_m_1 == `TRUE))
 22.1421 -               )
 22.1422 -           )
 22.1423 -       )
 22.1424 -        interlock = `TRUE;
 22.1425 -    else
 22.1426 -        interlock = `FALSE;
 22.1427 -end
 22.1428 -
 22.1429 -// Bypass for reg port 0
 22.1430 -always @(*)
 22.1431 -begin
 22.1432 -    if (raw_x_0 == `TRUE)        
 22.1433 -        bypass_data_0 = x_result;
 22.1434 -    else if (raw_m_0 == `TRUE)
 22.1435 -        bypass_data_0 = m_result;
 22.1436 -    else if (raw_w_0 == `TRUE)
 22.1437 -        bypass_data_0 = w_result;
 22.1438 -    else
 22.1439 -        bypass_data_0 = reg_data_0;
 22.1440 -end
 22.1441 -
 22.1442 -// Bypass for reg port 1
 22.1443 -always @(*)
 22.1444 -begin
 22.1445 -    if (raw_x_1 == `TRUE)
 22.1446 -        bypass_data_1 = x_result;
 22.1447 -    else if (raw_m_1 == `TRUE)
 22.1448 -        bypass_data_1 = m_result;
 22.1449 -    else if (raw_w_1 == `TRUE)
 22.1450 -        bypass_data_1 = w_result;
 22.1451 -    else
 22.1452 -        bypass_data_1 = reg_data_1;
 22.1453 -end
 22.1454 -
 22.1455 -   /*----------------------------------------------------------------------
 22.1456 -    Branch prediction is performed in D stage of pipeline. Only PC-relative
 22.1457 -    branches are predicted: forward-pointing conditional branches are not-
 22.1458 -    taken, while backward-pointing conditional branches are taken. 
 22.1459 -    Unconditional branches are always predicted taken!
 22.1460 -    ----------------------------------------------------------------------*/
 22.1461 -   assign branch_predict_d = bi_unconditional | bi_conditional;
 22.1462 -   assign branch_predict_taken_d = bi_unconditional ? 1'b1 : (bi_conditional ? instruction_d[15] : 1'b0);
 22.1463 -   
 22.1464 -   // Compute branch target address: Branch PC PLUS Offset
 22.1465 -   assign branch_target_d = pc_d + branch_offset_d;
 22.1466 -
 22.1467 -   // Compute fetch address. Address of instruction sequentially after the
 22.1468 -   // branch if branch is not taken. Target address of branch is branch is
 22.1469 -   // taken
 22.1470 -   assign branch_predict_address_d = branch_predict_taken_d ? branch_target_d : pc_f;
 22.1471 -
 22.1472 -// D stage result selection
 22.1473 -always @(*)
 22.1474 -begin
 22.1475 -    d_result_0 = d_result_sel_0_d[0] ? {pc_f, 2'b00} : bypass_data_0; 
 22.1476 -    case (d_result_sel_1_d)
 22.1477 -    `LM32_D_RESULT_SEL_1_ZERO:      d_result_1 = {`LM32_WORD_WIDTH{1'b0}};
 22.1478 -    `LM32_D_RESULT_SEL_1_REG_1:     d_result_1 = bypass_data_1;
 22.1479 -    `LM32_D_RESULT_SEL_1_IMMEDIATE: d_result_1 = immediate_d;
 22.1480 -    default:                        d_result_1 = {`LM32_WORD_WIDTH{1'bx}};
 22.1481 -    endcase
 22.1482 -end
 22.1483 -
 22.1484 -`ifdef CFG_USER_ENABLED    
 22.1485 -// Operands for user-defined instructions
 22.1486 -assign user_operand_0 = operand_0_x;
 22.1487 -assign user_operand_1 = operand_1_x;
 22.1488 -`endif
 22.1489 -
 22.1490 -`ifdef CFG_SIGN_EXTEND_ENABLED
 22.1491 -// Sign-extension
 22.1492 -assign sextb_result_x = {{24{operand_0_x[7]}}, operand_0_x[7:0]};
 22.1493 -assign sexth_result_x = {{16{operand_0_x[15]}}, operand_0_x[15:0]};
 22.1494 -assign sext_result_x = size_x == `LM32_SIZE_BYTE ? sextb_result_x : sexth_result_x;
 22.1495 -`endif
 22.1496 -
 22.1497 -`ifdef LM32_NO_BARREL_SHIFT
 22.1498 -// Only single bit shift operations are supported when barrel-shifter isn't implemented
 22.1499 -assign shifter_result_x = {operand_0_x[`LM32_WORD_WIDTH-1] & sign_extend_x, operand_0_x[`LM32_WORD_WIDTH-1:1]};
 22.1500 -`endif
 22.1501 -
 22.1502 -// Condition evaluation
 22.1503 -assign cmp_zero = operand_0_x == operand_1_x;
 22.1504 -assign cmp_negative = adder_result_x[`LM32_WORD_WIDTH-1];
 22.1505 -assign cmp_overflow = adder_overflow_x;
 22.1506 -assign cmp_carry_n = adder_carry_n_x;
 22.1507 -always @(*)
 22.1508 -begin
 22.1509 -    case (condition_x)
 22.1510 -    `LM32_CONDITION_U1:   condition_met_x = `TRUE;
 22.1511 -    `LM32_CONDITION_U2:   condition_met_x = `TRUE;
 22.1512 -    `LM32_CONDITION_E:    condition_met_x = cmp_zero;
 22.1513 -    `LM32_CONDITION_NE:   condition_met_x = !cmp_zero;
 22.1514 -    `LM32_CONDITION_G:    condition_met_x = !cmp_zero && (cmp_negative == cmp_overflow);
 22.1515 -    `LM32_CONDITION_GU:   condition_met_x = cmp_carry_n && !cmp_zero;
 22.1516 -    `LM32_CONDITION_GE:   condition_met_x = cmp_negative == cmp_overflow;
 22.1517 -    `LM32_CONDITION_GEU:  condition_met_x = cmp_carry_n;
 22.1518 -    default:              condition_met_x = 1'bx;
 22.1519 -    endcase 
 22.1520 -end
 22.1521 -
 22.1522 -// X stage result selection
 22.1523 -always @(*)
 22.1524 -begin
 22.1525 -    x_result =   x_result_sel_add_x ? adder_result_x 
 22.1526 -               : x_result_sel_csr_x ? csr_read_data_x
 22.1527 -`ifdef CFG_SIGN_EXTEND_ENABLED
 22.1528 -               : x_result_sel_sext_x ? sext_result_x
 22.1529 -`endif
 22.1530 -`ifdef CFG_USER_ENABLED
 22.1531 -               : x_result_sel_user_x ? user_result
 22.1532 -`endif
 22.1533 -`ifdef LM32_NO_BARREL_SHIFT
 22.1534 -               : x_result_sel_shift_x ? shifter_result_x
 22.1535 -`endif
 22.1536 -`ifdef LM32_MC_ARITHMETIC_ENABLED
 22.1537 -               : x_result_sel_mc_arith_x ? mc_result_x
 22.1538 -`endif
 22.1539 -               : logic_result_x;
 22.1540 -end
 22.1541 -
 22.1542 -// M stage result selection
 22.1543 -always @(*)
 22.1544 -begin
 22.1545 -    m_result =   m_result_sel_compare_m ? {{`LM32_WORD_WIDTH-1{1'b0}}, condition_met_m}
 22.1546 -`ifdef CFG_PL_BARREL_SHIFT_ENABLED
 22.1547 -               : m_result_sel_shift_m ? shifter_result_m
 22.1548 -`endif
 22.1549 -               : operand_m; 
 22.1550 -end
 22.1551 -
 22.1552 -// W stage result selection
 22.1553 -always @(*)
 22.1554 -begin
 22.1555 -    w_result =    w_result_sel_load_w ? load_data_w
 22.1556 -`ifdef CFG_PL_MULTIPLY_ENABLED
 22.1557 -                : w_result_sel_mul_w ? multiplier_result_w
 22.1558 -`endif
 22.1559 -                : operand_w;
 22.1560 -end
 22.1561 -
 22.1562 -`ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
 22.1563 -// Indicate when a branch should be taken in X stage
 22.1564 -assign branch_taken_x =      (stall_x == `FALSE)
 22.1565 -                          && (   (branch_x == `TRUE)
 22.1566 -                              && ((condition_x == `LM32_CONDITION_U1) || (condition_x == `LM32_CONDITION_U2))
 22.1567 -                              && (valid_x == `TRUE)
 22.1568 -                              && (branch_predict_x == `FALSE)
 22.1569 -                             ); 
 22.1570 -`endif
 22.1571 -
 22.1572 -// Indicate when a branch should be taken in M stage (exceptions are a type of branch)
 22.1573 -assign branch_taken_m =      (stall_m == `FALSE) 
 22.1574 -                          && (   (   (branch_m == `TRUE) 
 22.1575 -                                  && (valid_m == `TRUE)
 22.1576 -                                  && (   (   (condition_met_m == `TRUE)
 22.1577 -					  && (branch_predict_taken_m == `FALSE)
 22.1578 -					 )
 22.1579 -				      || (   (condition_met_m == `FALSE)
 22.1580 -					  && (branch_predict_m == `TRUE)
 22.1581 -					  && (branch_predict_taken_m == `TRUE)
 22.1582 -					 )
 22.1583 -				     )
 22.1584 -                                 ) 
 22.1585 -                              || (exception_m == `TRUE)
 22.1586 -                             );
 22.1587 -
 22.1588 -// Indicate when a branch in M stage is mispredicted as being taken
 22.1589 -assign branch_mispredict_taken_m =    (condition_met_m == `FALSE)
 22.1590 -                                   && (branch_predict_m == `TRUE)
 22.1591 -	   			   && (branch_predict_taken_m == `TRUE);
 22.1592 -   
 22.1593 -// Indicate when a branch in M stage will cause flush in X stage
 22.1594 -assign branch_flushX_m =    (stall_m == `FALSE)
 22.1595 -                         && (   (   (branch_m == `TRUE) 
 22.1596 -                                 && (valid_m == `TRUE)
 22.1597 -			         && (   (condition_met_m == `TRUE)
 22.1598 -				     || (   (condition_met_m == `FALSE)
 22.1599 -					 && (branch_predict_m == `TRUE)
 22.1600 -					 && (branch_predict_taken_m == `TRUE)
 22.1601 -					)
 22.1602 -				    )
 22.1603 -			        )
 22.1604 -			     || (exception_m == `TRUE)
 22.1605 -			    );
 22.1606 -
 22.1607 -// Generate signal that will kill instructions in each pipeline stage when necessary
 22.1608 -assign kill_f =    (   (valid_d == `TRUE)
 22.1609 -                    && (branch_predict_taken_d == `TRUE)
 22.1610 -		   )
 22.1611 -                || (branch_taken_m == `TRUE) 
 22.1612 -`ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
 22.1613 -                || (branch_taken_x == `TRUE)
 22.1614 -`endif
 22.1615 -`ifdef CFG_ICACHE_ENABLED
 22.1616 -                || (icache_refill_request == `TRUE) 
 22.1617 -`endif
 22.1618 -`ifdef CFG_DCACHE_ENABLED                
 22.1619 -                || (dcache_refill_request == `TRUE)
 22.1620 -`endif
 22.1621 -                ;
 22.1622 -assign kill_d =    (branch_taken_m == `TRUE) 
 22.1623 -`ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
 22.1624 -                || (branch_taken_x == `TRUE)
 22.1625 -`endif
 22.1626 -`ifdef CFG_ICACHE_ENABLED
 22.1627 -                || (icache_refill_request == `TRUE)     
 22.1628 -`endif                
 22.1629 -`ifdef CFG_DCACHE_ENABLED                
 22.1630 -                || (dcache_refill_request == `TRUE)
 22.1631 -`endif
 22.1632 -                ;
 22.1633 -assign kill_x =    (branch_flushX_m == `TRUE) 
 22.1634 -`ifdef CFG_DCACHE_ENABLED                
 22.1635 -                || (dcache_refill_request == `TRUE)
 22.1636 -`endif
 22.1637 -                ;
 22.1638 -assign kill_m =    `FALSE
 22.1639 -`ifdef CFG_DCACHE_ENABLED                
 22.1640 -                || (dcache_refill_request == `TRUE)
 22.1641 -`endif
 22.1642 -                ;                
 22.1643 -assign kill_w =    `FALSE
 22.1644 -`ifdef CFG_DCACHE_ENABLED                
 22.1645 -                || (dcache_refill_request == `TRUE)
 22.1646 -`endif                
 22.1647 -                ;
 22.1648 -
 22.1649 -// Exceptions
 22.1650 -
 22.1651 -`ifdef CFG_DEBUG_ENABLED
 22.1652 -assign breakpoint_exception =    (   (   (break_x == `TRUE)
 22.1653 -				      || (bp_match == `TRUE)
 22.1654 -				     )
 22.1655 -				  && (valid_x == `TRUE)
 22.1656 -				 )
 22.1657 -`ifdef CFG_JTAG_ENABLED
 22.1658 -                              || (jtag_break == `TRUE)
 22.1659 -`endif
 22.1660 -                              ;
 22.1661 -`endif
 22.1662 -
 22.1663 -`ifdef CFG_DEBUG_ENABLED
 22.1664 -assign watchpoint_exception = wp_match == `TRUE;
 22.1665 -`endif
 22.1666 -
 22.1667 -`ifdef CFG_BUS_ERRORS_ENABLED
 22.1668 -assign instruction_bus_error_exception = (   (bus_error_x == `TRUE)
 22.1669 -                                          && (valid_x == `TRUE)
 22.1670 -                                         );
 22.1671 -assign data_bus_error_exception = data_bus_error_seen == `TRUE;
 22.1672 -`endif
 22.1673 -
 22.1674 -`ifdef CFG_MC_DIVIDE_ENABLED
 22.1675 -assign divide_by_zero_exception = divide_by_zero_x == `TRUE;
 22.1676 -`endif
 22.1677 -
 22.1678 -assign system_call_exception = (   (scall_x == `TRUE)
 22.1679 -`ifdef CFG_BUS_ERRORS_ENABLED
 22.1680 -                                && (valid_x == `TRUE)
 22.1681 -`endif
 22.1682 -			       );
 22.1683 -
 22.1684 -`ifdef CFG_DEBUG_ENABLED
 22.1685 -assign debug_exception_x =  (breakpoint_exception == `TRUE)
 22.1686 -                         || (watchpoint_exception == `TRUE)
 22.1687 -                         ;
 22.1688 -
 22.1689 -assign non_debug_exception_x = (system_call_exception == `TRUE)
 22.1690 -`ifdef CFG_JTAG_ENABLED
 22.1691 -                            || (reset_exception == `TRUE)
 22.1692 -`endif
 22.1693 -`ifdef CFG_BUS_ERRORS_ENABLED
 22.1694 -                            || (instruction_bus_error_exception == `TRUE)
 22.1695 -                            || (data_bus_error_exception == `TRUE)
 22.1696 -`endif
 22.1697 -`ifdef CFG_MC_DIVIDE_ENABLED
 22.1698 -                            || (divide_by_zero_exception == `TRUE)
 22.1699 -`endif
 22.1700 -`ifdef CFG_INTERRUPTS_ENABLED
 22.1701 -                            || (   (interrupt_exception == `TRUE)
 22.1702 -`ifdef LM32_SINGLE_STEP_ENABLED
 22.1703 -                                && (dc_ss == `FALSE)
 22.1704 -`endif                            
 22.1705 -`ifdef CFG_BUS_ERRORS_ENABLED
 22.1706 - 				&& (store_q_m == `FALSE)
 22.1707 -				&& (D_CYC_O == `FALSE)
 22.1708 -`endif
 22.1709 -                               )
 22.1710 -`endif
 22.1711 -                            ;
 22.1712 -
 22.1713 -assign exception_x = (debug_exception_x == `TRUE) || (non_debug_exception_x == `TRUE);
 22.1714 -`else
 22.1715 -assign exception_x =           (system_call_exception == `TRUE)
 22.1716 -`ifdef CFG_BUS_ERRORS_ENABLED
 22.1717 -                            || (instruction_bus_error_exception == `TRUE)
 22.1718 -                            || (data_bus_error_exception == `TRUE)
 22.1719 -`endif
 22.1720 -`ifdef CFG_MC_DIVIDE_ENABLED
 22.1721 -                            || (divide_by_zero_exception == `TRUE)
 22.1722 -`endif
 22.1723 -`ifdef CFG_INTERRUPTS_ENABLED
 22.1724 -                            || (   (interrupt_exception == `TRUE)
 22.1725 -`ifdef LM32_SINGLE_STEP_ENABLED
 22.1726 -                                && (dc_ss == `FALSE)
 22.1727 -`endif                            
 22.1728 -`ifdef CFG_BUS_ERRORS_ENABLED
 22.1729 - 				&& (store_q_m == `FALSE)
 22.1730 -				&& (D_CYC_O == `FALSE)
 22.1731 -`endif
 22.1732 -                               )
 22.1733 -`endif
 22.1734 -                            ;
 22.1735 -`endif
 22.1736 -
 22.1737 -// Exception ID
 22.1738 -always @(*)
 22.1739 -begin
 22.1740 -`ifdef CFG_DEBUG_ENABLED
 22.1741 -`ifdef CFG_JTAG_ENABLED
 22.1742 -    if (reset_exception == `TRUE)
 22.1743 -        eid_x = `LM32_EID_RESET;
 22.1744 -    else
 22.1745 -`endif     
 22.1746 -`ifdef CFG_BUS_ERRORS_ENABLED
 22.1747 -         if (data_bus_error_exception == `TRUE)
 22.1748 -        eid_x = `LM32_EID_DATA_BUS_ERROR;
 22.1749 -    else
 22.1750 -`endif
 22.1751 -         if (breakpoint_exception == `TRUE)
 22.1752 -        eid_x = `LM32_EID_BREAKPOINT;
 22.1753 -    else
 22.1754 -`endif
 22.1755 -`ifdef CFG_BUS_ERRORS_ENABLED
 22.1756 -         if (data_bus_error_exception == `TRUE)
 22.1757 -        eid_x = `LM32_EID_DATA_BUS_ERROR;
 22.1758 -    else
 22.1759 -         if (instruction_bus_error_exception == `TRUE)
 22.1760 -        eid_x = `LM32_EID_INST_BUS_ERROR;
 22.1761 -    else
 22.1762 -`endif
 22.1763 -`ifdef CFG_DEBUG_ENABLED
 22.1764 -         if (watchpoint_exception == `TRUE)
 22.1765 -        eid_x = `LM32_EID_WATCHPOINT;
 22.1766 -    else 
 22.1767 -`endif
 22.1768 -`ifdef CFG_MC_DIVIDE_ENABLED
 22.1769 -         if (divide_by_zero_exception == `TRUE)
 22.1770 -        eid_x = `LM32_EID_DIVIDE_BY_ZERO;
 22.1771 -    else
 22.1772 -`endif
 22.1773 -`ifdef CFG_INTERRUPTS_ENABLED
 22.1774 -         if (   (interrupt_exception == `TRUE)
 22.1775 -`ifdef LM32_SINGLE_STEP_ENABLED
 22.1776 -             && (dc_ss == `FALSE)
 22.1777 -`endif                            
 22.1778 -            )
 22.1779 -        eid_x = `LM32_EID_INTERRUPT;
 22.1780 -    else
 22.1781 -`endif
 22.1782 -        eid_x = `LM32_EID_SCALL;
 22.1783 -end
 22.1784 -
 22.1785 -// Stall generation
 22.1786 -
 22.1787 -assign stall_a = (stall_f == `TRUE);
 22.1788 -                
 22.1789 -assign stall_f = (stall_d == `TRUE);
 22.1790 -                
 22.1791 -assign stall_d =   (stall_x == `TRUE) 
 22.1792 -                || (   (interlock == `TRUE)
 22.1793 -                    && (kill_d == `FALSE)
 22.1794 -                   ) 
 22.1795 -		|| (   (   (eret_d == `TRUE)
 22.1796 -			|| (scall_d == `TRUE)
 22.1797 -`ifdef CFG_BUS_ERRORS_ENABLED
 22.1798 -			|| (bus_error_d == `TRUE)
 22.1799 -`endif
 22.1800 -		       )
 22.1801 -		    && (   (load_q_x == `TRUE)
 22.1802 -			|| (load_q_m == `TRUE)
 22.1803 -			|| (store_q_x == `TRUE)
 22.1804 -			|| (store_q_m == `TRUE)
 22.1805 -			|| (D_CYC_O == `TRUE)
 22.1806 -		       )
 22.1807 -                    && (kill_d == `FALSE)
 22.1808 -		   )
 22.1809 -`ifdef CFG_DEBUG_ENABLED
 22.1810 -		|| (   (   (break_d == `TRUE)
 22.1811 -			|| (bret_d == `TRUE)
 22.1812 -		       )
 22.1813 -		    && (   (load_q_x == `TRUE)
 22.1814 -			|| (store_q_x == `TRUE)
 22.1815 -			|| (load_q_m == `TRUE)
 22.1816 -			|| (store_q_m == `TRUE)
 22.1817 -			|| (D_CYC_O == `TRUE)
 22.1818 -		       )
 22.1819 -                    && (kill_d == `FALSE)
 22.1820 -		   )
 22.1821 -`endif                   
 22.1822 -                || (   (csr_write_enable_d == `TRUE)
 22.1823 -                    && (load_q_x == `TRUE)
 22.1824 -                   )                      
 22.1825 -                ;
 22.1826 -                
 22.1827 -assign stall_x =    (stall_m == `TRUE)
 22.1828 -`ifdef LM32_MC_ARITHMETIC_ENABLED
 22.1829 -                 || (   (mc_stall_request_x == `TRUE)
 22.1830 -                     && (kill_x == `FALSE)
 22.1831 -                    ) 
 22.1832 -`endif
 22.1833 -`ifdef CFG_IROM_ENABLED
 22.1834 -                 // Stall load/store instruction in D stage if there is an ongoing store
 22.1835 -                 // operation to instruction ROM in M stage
 22.1836 -                 || (   (irom_stall_request_x == `TRUE)
 22.1837 -		     && (   (load_d == `TRUE)
 22.1838 -			 || (store_d == `TRUE)
 22.1839 -			)
 22.1840 -		    )
 22.1841 -`endif
 22.1842 -                 ;
 22.1843 -
 22.1844 -assign stall_m =    (stall_wb_load == `TRUE)
 22.1845 -`ifdef CFG_SIZE_OVER_SPEED
 22.1846 -                 || (D_CYC_O == `TRUE)
 22.1847 -`else
 22.1848 -                 || (   (D_CYC_O == `TRUE)
 22.1849 -                     && (   (store_m == `TRUE)
 22.1850 -		         /*
 22.1851 -			  Bug: Following loop does not allow interrupts to be services since
 22.1852 -			  either D_CYC_O or store_m is always high during entire duration of
 22.1853 -			  loop.
 22.1854 -		          L1:	addi	r1, r1, 1
 22.1855 -			  	sw	(r2,0), r1
 22.1856 -			  	bi	L1
 22.1857 -			  
 22.1858 -			  Introduce a single-cycle stall when a wishbone cycle is in progress
 22.1859 -			  and a new store instruction is in Execute stage and a interrupt
 22.1860 -			  exception has occured. This stall will ensure that D_CYC_O and 
 22.1861 -			  store_m will both be low for one cycle.
 22.1862 -			  */
 22.1863 -`ifdef CFG_INTERRUPTS_ENABLED
 22.1864 -		         || ((store_x == `TRUE) && (interrupt_exception == `TRUE))
 22.1865 -`endif
 22.1866 -                         || (load_m == `TRUE)
 22.1867 -                         || (load_x == `TRUE)
 22.1868 -                        ) 
 22.1869 -                    ) 
 22.1870 -`endif                 
 22.1871 -`ifdef CFG_DCACHE_ENABLED
 22.1872 -                 || (dcache_stall_request == `TRUE)     // Need to stall in case a taken branch is in M stage and data cache is only being flush, so wont be restarted
 22.1873 -`endif                                    
 22.1874 -`ifdef CFG_ICACHE_ENABLED
 22.1875 -                 || (icache_stall_request == `TRUE)     // Pipeline needs to be stalled otherwise branches may be lost
 22.1876 -                 || ((I_CYC_O == `TRUE) && ((branch_m == `TRUE) || (exception_m == `TRUE))) 
 22.1877 -`else
 22.1878 -`ifdef CFG_IWB_ENABLED
 22.1879 -                 || (I_CYC_O == `TRUE)            
 22.1880 -`endif
 22.1881 -`endif                               
 22.1882 -`ifdef CFG_USER_ENABLED
 22.1883 -                 || (   (user_valid == `TRUE)           // Stall whole pipeline, rather than just X stage, where the instruction is, so we don't have to worry about exceptions (maybe)
 22.1884 -                     && (user_complete == `FALSE)
 22.1885 -                    )
 22.1886 -`endif
 22.1887 -                 ;      
 22.1888 -
 22.1889 -// Qualify state changing control signals
 22.1890 -`ifdef LM32_MC_ARITHMETIC_ENABLED
 22.1891 -assign q_d = (valid_d == `TRUE) && (kill_d == `FALSE);
 22.1892 -`endif
 22.1893 -`ifdef CFG_MC_BARREL_SHIFT_ENABLED
 22.1894 -assign shift_left_q_d = (shift_left_d == `TRUE) && (q_d == `TRUE);
 22.1895 -assign shift_right_q_d = (shift_right_d == `TRUE) && (q_d == `TRUE);
 22.1896 -`endif
 22.1897 -`ifdef CFG_MC_MULTIPLY_ENABLED
 22.1898 -assign multiply_q_d = (multiply_d == `TRUE) && (q_d == `TRUE);
 22.1899 -`endif
 22.1900 -`ifdef CFG_MC_DIVIDE_ENABLED
 22.1901 -assign divide_q_d = (divide_d == `TRUE) && (q_d == `TRUE);
 22.1902 -assign modulus_q_d = (modulus_d == `TRUE) && (q_d == `TRUE);
 22.1903 -`endif
 22.1904 -assign q_x = (valid_x == `TRUE) && (kill_x == `FALSE);
 22.1905 -assign csr_write_enable_q_x = (csr_write_enable_x == `TRUE) && (q_x == `TRUE);
 22.1906 -assign eret_q_x = (eret_x == `TRUE) && (q_x == `TRUE);
 22.1907 -`ifdef CFG_DEBUG_ENABLED
 22.1908 -assign bret_q_x = (bret_x == `TRUE) && (q_x == `TRUE);
 22.1909 -`endif
 22.1910 -assign load_q_x = (load_x == `TRUE) 
 22.1911 -               && (q_x == `TRUE)
 22.1912 -`ifdef CFG_DEBUG_ENABLED
 22.1913 -               && (bp_match == `FALSE)
 22.1914 -`endif
 22.1915 -                  ;
 22.1916 -assign store_q_x = (store_x == `TRUE) 
 22.1917 -               && (q_x == `TRUE)
 22.1918 -`ifdef CFG_DEBUG_ENABLED
 22.1919 -               && (bp_match == `FALSE)
 22.1920 -`endif
 22.1921 -                  ;
 22.1922 -`ifdef CFG_USER_ENABLED
 22.1923 -assign user_valid = (x_result_sel_user_x == `TRUE) && (q_x == `TRUE);
 22.1924 -`endif                              
 22.1925 -assign q_m = (valid_m == `TRUE) && (kill_m == `FALSE) && (exception_m == `FALSE);
 22.1926 -assign load_q_m = (load_m == `TRUE) && (q_m == `TRUE);
 22.1927 -assign store_q_m = (store_m == `TRUE) && (q_m == `TRUE);
 22.1928 -`ifdef CFG_DEBUG_ENABLED
 22.1929 -assign debug_exception_q_w = ((debug_exception_w == `TRUE) && (valid_w == `TRUE));
 22.1930 -assign non_debug_exception_q_w = ((non_debug_exception_w == `TRUE) && (valid_w == `TRUE));        
 22.1931 -`else
 22.1932 -assign exception_q_w = ((exception_w == `TRUE) && (valid_w == `TRUE));        
 22.1933 -`endif
 22.1934 -// Don't qualify register write enables with kill, as the signal is needed early, and it doesn't matter if the instruction is killed (except for the actual write - but that is handled separately)
 22.1935 -assign write_enable_q_x = (write_enable_x == `TRUE) && (valid_x == `TRUE) && (branch_flushX_m == `FALSE);
 22.1936 -assign write_enable_q_m = (write_enable_m == `TRUE) && (valid_m == `TRUE);
 22.1937 -assign write_enable_q_w = (write_enable_w == `TRUE) && (valid_w == `TRUE);
 22.1938 -// The enable that actually does write the registers needs to be qualified with kill
 22.1939 -assign reg_write_enable_q_w = (write_enable_w == `TRUE) && (kill_w == `FALSE) && (valid_w == `TRUE);
 22.1940 -
 22.1941 -// Configuration (CFG) CSR
 22.1942 -assign cfg = {
 22.1943 -              `LM32_REVISION,
 22.1944 -              watchpoints[3:0],
 22.1945 -              breakpoints[3:0],
 22.1946 -              interrupts[5:0],
 22.1947 -`ifdef CFG_JTAG_UART_ENABLED
 22.1948 -              `TRUE,
 22.1949 -`else
 22.1950 -              `FALSE,
 22.1951 -`endif
 22.1952 -`ifdef CFG_ROM_DEBUG_ENABLED
 22.1953 -              `TRUE,
 22.1954 -`else
 22.1955 -              `FALSE,
 22.1956 -`endif
 22.1957 -`ifdef CFG_HW_DEBUG_ENABLED
 22.1958 -              `TRUE,
 22.1959 -`else
 22.1960 -              `FALSE,
 22.1961 -`endif
 22.1962 -`ifdef CFG_DEBUG_ENABLED
 22.1963 -              `TRUE,
 22.1964 -`else
 22.1965 -              `FALSE,
 22.1966 -`endif
 22.1967 -`ifdef CFG_ICACHE_ENABLED
 22.1968 -              `TRUE,
 22.1969 -`else
 22.1970 -              `FALSE,
 22.1971 -`endif
 22.1972 -`ifdef CFG_DCACHE_ENABLED
 22.1973 -              `TRUE,
 22.1974 -`else
 22.1975 -              `FALSE,
 22.1976 -`endif
 22.1977 -`ifdef CFG_CYCLE_COUNTER_ENABLED
 22.1978 -              `TRUE,
 22.1979 -`else
 22.1980 -              `FALSE,
 22.1981 -`endif
 22.1982 -`ifdef CFG_USER_ENABLED
 22.1983 -              `TRUE,
 22.1984 -`else
 22.1985 -              `FALSE,
 22.1986 -`endif
 22.1987 -`ifdef CFG_SIGN_EXTEND_ENABLED
 22.1988 -              `TRUE,
 22.1989 -`else
 22.1990 -              `FALSE,
 22.1991 -`endif
 22.1992 -`ifdef LM32_BARREL_SHIFT_ENABLED
 22.1993 -              `TRUE,
 22.1994 -`else
 22.1995 -              `FALSE,
 22.1996 -`endif
 22.1997 -`ifdef CFG_MC_DIVIDE_ENABLED
 22.1998 -              `TRUE,
 22.1999 -`else
 22.2000 -              `FALSE,
 22.2001 -`endif
 22.2002 -`ifdef LM32_MULTIPLY_ENABLED 
 22.2003 -              `TRUE
 22.2004 -`else
 22.2005 -              `FALSE
 22.2006 -`endif
 22.2007 -              };
 22.2008 -
 22.2009 -assign cfg2 = {
 22.2010 -		     30'b0,
 22.2011 -`ifdef CFG_IROM_ENABLED
 22.2012 -		     `TRUE,
 22.2013 -`else
 22.2014 -		     `FALSE,
 22.2015 -`endif
 22.2016 -`ifdef CFG_DRAM_ENABLED
 22.2017 -		     `TRUE
 22.2018 -`else
 22.2019 -		     `FALSE
 22.2020 -`endif
 22.2021 -		     };
 22.2022 -   
 22.2023 -// Cache flush
 22.2024 -`ifdef CFG_ICACHE_ENABLED
 22.2025 -assign iflush = (   (csr_write_enable_d == `TRUE) 
 22.2026 -                 && (csr_d == `LM32_CSR_ICC)
 22.2027 -                 && (stall_d == `FALSE)
 22.2028 -                 && (kill_d == `FALSE)
 22.2029 -                 && (valid_d == `TRUE))
 22.2030 -// Added by GSI: needed to flush cache after loading firmware per JTAG
 22.2031 -`ifdef CFG_HW_DEBUG_ENABLED
 22.2032 -             ||
 22.2033 -                (   (jtag_csr_write_enable == `TRUE)
 22.2034 -		 && (jtag_csr == `LM32_CSR_ICC))
 22.2035 -`endif
 22.2036 -		 ;
 22.2037 -`endif 
 22.2038 -`ifdef CFG_DCACHE_ENABLED
 22.2039 -assign dflush_x = (   (csr_write_enable_q_x == `TRUE) 
 22.2040 -                   && (csr_x == `LM32_CSR_DCC))
 22.2041 -// Added by GSI: needed to flush cache after loading firmware per JTAG
 22.2042 -`ifdef CFG_HW_DEBUG_ENABLED
 22.2043 -               ||
 22.2044 -                  (   (jtag_csr_write_enable == `TRUE)
 22.2045 -		   && (jtag_csr == `LM32_CSR_DCC))
 22.2046 -`endif
 22.2047 -		   ;
 22.2048 -`endif 
 22.2049 -
 22.2050 -// Extract CSR index
 22.2051 -assign csr_d = read_idx_0_d[`LM32_CSR_RNG];
 22.2052 -
 22.2053 -// CSR reads
 22.2054 -always @(*)
 22.2055 -begin
 22.2056 -    case (csr_x)
 22.2057 -`ifdef CFG_INTERRUPTS_ENABLED
 22.2058 -    `LM32_CSR_IE,
 22.2059 -    `LM32_CSR_IM,
 22.2060 -    `LM32_CSR_IP:   csr_read_data_x = interrupt_csr_read_data_x;  
 22.2061 -`endif
 22.2062 -`ifdef CFG_CYCLE_COUNTER_ENABLED
 22.2063 -    `LM32_CSR_CC:   csr_read_data_x = cc;
 22.2064 -`endif
 22.2065 -    `LM32_CSR_CFG:  csr_read_data_x = cfg;
 22.2066 -    `LM32_CSR_EBA:  csr_read_data_x = {eba, 8'h00};
 22.2067 -`ifdef CFG_DEBUG_ENABLED
 22.2068 -    `LM32_CSR_DEBA: csr_read_data_x = {deba, 8'h00};
 22.2069 -`endif
 22.2070 -`ifdef CFG_JTAG_UART_ENABLED
 22.2071 -    `LM32_CSR_JTX:  csr_read_data_x = jtx_csr_read_data;  
 22.2072 -    `LM32_CSR_JRX:  csr_read_data_x = jrx_csr_read_data;
 22.2073 -`endif
 22.2074 -    `LM32_CSR_CFG2: csr_read_data_x = cfg2;
 22.2075 -      
 22.2076 -    default:        csr_read_data_x = {`LM32_WORD_WIDTH{1'bx}};
 22.2077 -    endcase
 22.2078 -end
 22.2079 -
 22.2080 -/////////////////////////////////////////////////////
 22.2081 -// Sequential Logic
 22.2082 -/////////////////////////////////////////////////////
 22.2083 -
 22.2084 -// Exception Base Address (EBA) CSR
 22.2085 -always @(posedge clk_i `CFG_RESET_SENSITIVITY)
 22.2086 -begin
 22.2087 -    if (rst_i == `TRUE)
 22.2088 -        eba <= eba_reset[`LM32_PC_WIDTH+2-1:8];
 22.2089 -    else
 22.2090 -    begin
 22.2091 -        if ((csr_write_enable_q_x == `TRUE) && (csr_x == `LM32_CSR_EBA) && (stall_x == `FALSE))
 22.2092 -            eba <= operand_1_x[`LM32_PC_WIDTH+2-1:8];
 22.2093 -`ifdef CFG_HW_DEBUG_ENABLED
 22.2094 -        if ((jtag_csr_write_enable == `TRUE) && (jtag_csr == `LM32_CSR_EBA))
 22.2095 -            eba <= jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8];
 22.2096 -`endif
 22.2097 -    end
 22.2098 -end
 22.2099 -
 22.2100 -`ifdef CFG_DEBUG_ENABLED
 22.2101 -// Debug Exception Base Address (DEBA) CSR
 22.2102 -always @(posedge clk_i `CFG_RESET_SENSITIVITY)
 22.2103 -begin
 22.2104 -    if (rst_i == `TRUE)
 22.2105 -        deba <= deba_reset[`LM32_PC_WIDTH+2-1:8];
 22.2106 -    else
 22.2107 -    begin
 22.2108 -        if ((csr_write_enable_q_x == `TRUE) && (csr_x == `LM32_CSR_DEBA) && (stall_x == `FALSE))
 22.2109 -            deba <= operand_1_x[`LM32_PC_WIDTH+2-1:8];
 22.2110 -`ifdef CFG_HW_DEBUG_ENABLED
 22.2111 -        if ((jtag_csr_write_enable == `TRUE) && (jtag_csr == `LM32_CSR_DEBA))
 22.2112 -            deba <= jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8];
 22.2113 -`endif
 22.2114 -    end
 22.2115 -end
 22.2116 -`endif
 22.2117 -
 22.2118 -// Cycle Counter (CC) CSR
 22.2119 -`ifdef CFG_CYCLE_COUNTER_ENABLED
 22.2120 -always @(posedge clk_i `CFG_RESET_SENSITIVITY)
 22.2121 -begin
 22.2122 -    if (rst_i == `TRUE)
 22.2123 -        cc <= {`LM32_WORD_WIDTH{1'b0}};
 22.2124 -    else
 22.2125 -        cc <= cc + 1'b1;
 22.2126 -end
 22.2127 -`endif
 22.2128 -
 22.2129 -`ifdef CFG_BUS_ERRORS_ENABLED
 22.2130 -// Watch for data bus errors
 22.2131 -always @(posedge clk_i `CFG_RESET_SENSITIVITY)
 22.2132 -begin
 22.2133 -    if (rst_i == `TRUE)
 22.2134 -        data_bus_error_seen <= `FALSE;
 22.2135 -    else
 22.2136 -    begin
 22.2137 -        // Set flag when bus error is detected
 22.2138 -        if ((D_ERR_I == `TRUE) && (D_CYC_O == `TRUE))
 22.2139 -            data_bus_error_seen <= `TRUE;
 22.2140 -        // Clear flag when exception is taken
 22.2141 -        if ((exception_m == `TRUE) && (kill_m == `FALSE))
 22.2142 -            data_bus_error_seen <= `FALSE;
 22.2143 -    end
 22.2144 -end
 22.2145 -`endif
 22.2146 - 
 22.2147 -// Valid bits to indicate whether an instruction in a partcular pipeline stage is valid or not  
 22.2148 -
 22.2149 -`ifdef CFG_ICACHE_ENABLED
 22.2150 -`ifdef CFG_DCACHE_ENABLED
 22.2151 -always @(*)
 22.2152 -begin
 22.2153 -    if (   (icache_refill_request == `TRUE) 
 22.2154 -        || (dcache_refill_request == `TRUE)
 22.2155 -       )
 22.2156 -        valid_a = `FALSE;
 22.2157 -    else if (   (icache_restart_request == `TRUE) 
 22.2158 -             || (dcache_restart_request == `TRUE) 
 22.2159 -            ) 
 22.2160 -        valid_a = `TRUE;
 22.2161 -    else 
 22.2162 -        valid_a = !icache_refilling && !dcache_refilling;
 22.2163 -end 
 22.2164 -`else
 22.2165 -always @(*)
 22.2166 -begin
 22.2167 -    if (icache_refill_request == `TRUE) 
 22.2168 -        valid_a = `FALSE;
 22.2169 -    else if (icache_restart_request == `TRUE) 
 22.2170 -        valid_a = `TRUE;
 22.2171 -    else 
 22.2172 -        valid_a = !icache_refilling;
 22.2173 -end 
 22.2174 -`endif
 22.2175 -`else
 22.2176 -`ifdef CFG_DCACHE_ENABLED
 22.2177 -always @(*)
 22.2178 -begin
 22.2179 -    if (dcache_refill_request == `TRUE) 
 22.2180 -        valid_a = `FALSE;
 22.2181 -    else if (dcache_restart_request == `TRUE) 
 22.2182 -        valid_a = `TRUE;
 22.2183 -    else 
 22.2184 -        valid_a = !dcache_refilling;
 22.2185 -end 
 22.2186 -`endif
 22.2187 -`endif
 22.2188 -
 22.2189 -always @(posedge clk_i `CFG_RESET_SENSITIVITY)
 22.2190 -begin
 22.2191 -    if (rst_i == `TRUE)
 22.2192 -    begin
 22.2193 -        valid_f <= `FALSE;
 22.2194 -        valid_d <= `FALSE;
 22.2195 -        valid_x <= `FALSE;
 22.2196 -        valid_m <= `FALSE;
 22.2197 -        valid_w <= `FALSE;
 22.2198 -    end
 22.2199 -    else
 22.2200 -    begin    
 22.2201 -        if ((kill_f == `TRUE) || (stall_a == `FALSE))
 22.2202 -`ifdef LM32_CACHE_ENABLED
 22.2203 -            valid_f <= valid_a;    
 22.2204 -`else
 22.2205 -            valid_f <= `TRUE;
 22.2206 -`endif            
 22.2207 -        else if (stall_f == `FALSE)
 22.2208 -            valid_f <= `FALSE;            
 22.2209 -
 22.2210 -        if (kill_d == `TRUE)
 22.2211 -            valid_d <= `FALSE;
 22.2212 -        else if (stall_f == `FALSE)
 22.2213 -            valid_d <= valid_f & !kill_f;
 22.2214 -        else if (stall_d == `FALSE)
 22.2215 -            valid_d <= `FALSE;
 22.2216 -       
 22.2217 -        if (stall_d == `FALSE)
 22.2218 -            valid_x <= valid_d & !kill_d;
 22.2219 -        else if (kill_x == `TRUE)
 22.2220 -            valid_x <= `FALSE;
 22.2221 -        else if (stall_x == `FALSE)
 22.2222 -            valid_x <= `FALSE;
 22.2223 -
 22.2224 -        if (kill_m == `TRUE)
 22.2225 -            valid_m <= `FALSE;
 22.2226 -        else if (stall_x == `FALSE)
 22.2227 -            valid_m <= valid_x & !kill_x;
 22.2228 -        else if (stall_m == `FALSE)
 22.2229 -            valid_m <= `FALSE;
 22.2230 -
 22.2231 -        if (stall_m == `FALSE)
 22.2232 -            valid_w <= valid_m & !kill_m;
 22.2233 -        else 
 22.2234 -            valid_w <= `FALSE;        
 22.2235 -    end
 22.2236 -end
 22.2237 -
 22.2238 -// Microcode pipeline registers
 22.2239 -always @(posedge clk_i `CFG_RESET_SENSITIVITY)
 22.2240 -begin
 22.2241 -    if (rst_i == `TRUE)
 22.2242 -    begin
 22.2243 -`ifdef CFG_USER_ENABLED
 22.2244 -        user_opcode <= {`LM32_USER_OPCODE_WIDTH{1'b0}};       
 22.2245 -`endif        
 22.2246 -        operand_0_x <= {`LM32_WORD_WIDTH{1'b0}};
 22.2247 -        operand_1_x <= {`LM32_WORD_WIDTH{1'b0}};
 22.2248 -        store_operand_x <= {`LM32_WORD_WIDTH{1'b0}};
 22.2249 -        branch_target_x <= {`LM32_PC_WIDTH{1'b0}};        
 22.2250 -        x_result_sel_csr_x <= `FALSE;
 22.2251 -`ifdef LM32_MC_ARITHMETIC_ENABLED
 22.2252 -        x_result_sel_mc_arith_x <= `FALSE;
 22.2253 -`endif
 22.2254 -`ifdef LM32_NO_BARREL_SHIFT    
 22.2255 -        x_result_sel_shift_x <= `FALSE;
 22.2256 -`endif
 22.2257 -`ifdef CFG_SIGN_EXTEND_ENABLED
 22.2258 -        x_result_sel_sext_x <= `FALSE;
 22.2259 -`endif  
 22.2260 -	x_result_sel_logic_x <= `FALSE;
 22.2261 -`ifdef CFG_USER_ENABLED
 22.2262 -        x_result_sel_user_x <= `FALSE;
 22.2263 -`endif
 22.2264 -        x_result_sel_add_x <= `FALSE;
 22.2265 -        m_result_sel_compare_x <= `FALSE;
 22.2266 -`ifdef CFG_PL_BARREL_SHIFT_ENABLED
 22.2267 -        m_result_sel_shift_x <= `FALSE;
 22.2268 -`endif    
 22.2269 -        w_result_sel_load_x <= `FALSE;
 22.2270 -`ifdef CFG_PL_MULTIPLY_ENABLED
 22.2271 -        w_result_sel_mul_x <= `FALSE;
 22.2272 -`endif
 22.2273 -        x_bypass_enable_x <= `FALSE;
 22.2274 -        m_bypass_enable_x <= `FALSE;
 22.2275 -        write_enable_x <= `FALSE;
 22.2276 -        write_idx_x <= {`LM32_REG_IDX_WIDTH{1'b0}};
 22.2277 -        csr_x <= {`LM32_CSR_WIDTH{1'b0}};
 22.2278 -        load_x <= `FALSE;
 22.2279 -        store_x <= `FALSE;
 22.2280 -        size_x <= {`LM32_SIZE_WIDTH{1'b0}};
 22.2281 -        sign_extend_x <= `FALSE;
 22.2282 -        adder_op_x <= `FALSE;
 22.2283 -        adder_op_x_n <= `FALSE;
 22.2284 -        logic_op_x <= 4'h0;
 22.2285 -`ifdef CFG_PL_BARREL_SHIFT_ENABLED
 22.2286 -        direction_x <= `FALSE;
 22.2287 -`endif
 22.2288 -`ifdef CFG_ROTATE_ENABLED
 22.2289 -        rotate_x <= `FALSE;
 22.2290 -
 22.2291 -`endif
 22.2292 -        branch_x <= `FALSE;
 22.2293 -        branch_predict_x <= `FALSE;
 22.2294 -        branch_predict_taken_x <= `FALSE;
 22.2295 -        condition_x <= `LM32_CONDITION_U1;
 22.2296 -`ifdef CFG_DEBUG_ENABLED
 22.2297 -        break_x <= `FALSE;
 22.2298 -`endif
 22.2299 -        scall_x <= `FALSE;
 22.2300 -        eret_x <= `FALSE;
 22.2301 -`ifdef CFG_DEBUG_ENABLED
 22.2302 -        bret_x <= `FALSE;
 22.2303 -`endif
 22.2304 -`ifdef CFG_BUS_ERRORS_ENABLED
 22.2305 -        bus_error_x <= `FALSE;
 22.2306 -        data_bus_error_exception_m <= `FALSE;
 22.2307 -`endif
 22.2308 -        csr_write_enable_x <= `FALSE;
 22.2309 -        operand_m <= {`LM32_WORD_WIDTH{1'b0}};
 22.2310 -        branch_target_m <= {`LM32_PC_WIDTH{1'b0}};
 22.2311 -        m_result_sel_compare_m <= `FALSE;
 22.2312 -`ifdef CFG_PL_BARREL_SHIFT_ENABLED
 22.2313 -        m_result_sel_shift_m <= `FALSE;
 22.2314 -`endif    
 22.2315 -        w_result_sel_load_m <= `FALSE;
 22.2316 -`ifdef CFG_PL_MULTIPLY_ENABLED
 22.2317 -        w_result_sel_mul_m <= `FALSE;
 22.2318 -`endif
 22.2319 -        m_bypass_enable_m <= `FALSE;
 22.2320 -        branch_m <= `FALSE;
 22.2321 -        branch_predict_m <= `FALSE;
 22.2322 -	branch_predict_taken_m <= `FALSE;
 22.2323 -        exception_m <= `FALSE;
 22.2324 -        load_m <= `FALSE;
 22.2325 -        store_m <= `FALSE;
 22.2326 -        write_enable_m <= `FALSE;            
 22.2327 -        write_idx_m <= {`LM32_REG_IDX_WIDTH{1'b0}};
 22.2328 -        condition_met_m <= `FALSE;
 22.2329 -`ifdef CFG_DCACHE_ENABLED
 22.2330 -        dflush_m <= `FALSE;
 22.2331 -`endif
 22.2332 -`ifdef CFG_DEBUG_ENABLED
 22.2333 -        debug_exception_m <= `FALSE;
 22.2334 -        non_debug_exception_m <= `FALSE;        
 22.2335 -`endif
 22.2336 -        operand_w <= {`LM32_WORD_WIDTH{1'b0}};        
 22.2337 -        w_result_sel_load_w <= `FALSE;
 22.2338 -`ifdef CFG_PL_MULTIPLY_ENABLED
 22.2339 -        w_result_sel_mul_w <= `FALSE;
 22.2340 -`endif
 22.2341 -        write_idx_w <= {`LM32_REG_IDX_WIDTH{1'b0}};        
 22.2342 -        write_enable_w <= `FALSE;
 22.2343 -`ifdef CFG_DEBUG_ENABLED
 22.2344 -        debug_exception_w <= `FALSE;
 22.2345 -        non_debug_exception_w <= `FALSE;        
 22.2346 -`else
 22.2347 -        exception_w <= `FALSE;
 22.2348 -`endif
 22.2349 -`ifdef CFG_BUS_ERRORS_ENABLED
 22.2350 -        memop_pc_w <= {`LM32_PC_WIDTH{1'b0}};
 22.2351 -`endif
 22.2352 -    end
 22.2353 -    else
 22.2354 -    begin
 22.2355 -        // D/X stage registers
 22.2356 -       
 22.2357 -        if (stall_x == `FALSE)
 22.2358 -        begin
 22.2359 -`ifdef CFG_USER_ENABLED
 22.2360 -            user_opcode <= user_opcode_d;       
 22.2361 -`endif        
 22.2362 -            operand_0_x <= d_result_0;
 22.2363 -            operand_1_x <= d_result_1;
 22.2364 -            store_operand_x <= bypass_data_1;
 22.2365 -            branch_target_x <= branch_reg_d == `TRUE ? bypass_data_0[`LM32_PC_RNG] : branch_target_d;            
 22.2366 -            x_result_sel_csr_x <= x_result_sel_csr_d;
 22.2367 -`ifdef LM32_MC_ARITHMETIC_ENABLED
 22.2368 -            x_result_sel_mc_arith_x <= x_result_sel_mc_arith_d;
 22.2369 -`endif
 22.2370 -`ifdef LM32_NO_BARREL_SHIFT    
 22.2371 -            x_result_sel_shift_x <= x_result_sel_shift_d;
 22.2372 -`endif
 22.2373 -`ifdef CFG_SIGN_EXTEND_ENABLED
 22.2374 -            x_result_sel_sext_x <= x_result_sel_sext_d;
 22.2375 -`endif    
 22.2376 -	    x_result_sel_logic_x <= x_result_sel_logic_d;
 22.2377 -`ifdef CFG_USER_ENABLED
 22.2378 -            x_result_sel_user_x <= x_result_sel_user_d;
 22.2379 -`endif
 22.2380 -            x_result_sel_add_x <= x_result_sel_add_d;
 22.2381 -            m_result_sel_compare_x <= m_result_sel_compare_d;
 22.2382 -`ifdef CFG_PL_BARREL_SHIFT_ENABLED
 22.2383 -            m_result_sel_shift_x <= m_result_sel_shift_d;
 22.2384 -`endif    
 22.2385 -            w_result_sel_load_x <= w_result_sel_load_d;
 22.2386 -`ifdef CFG_PL_MULTIPLY_ENABLED
 22.2387 -            w_result_sel_mul_x <= w_result_sel_mul_d;
 22.2388 -`endif
 22.2389 -            x_bypass_enable_x <= x_bypass_enable_d;
 22.2390 -            m_bypass_enable_x <= m_bypass_enable_d;
 22.2391 -            load_x <= load_d;
 22.2392 -            store_x <= store_d;
 22.2393 -            branch_x <= branch_d;
 22.2394 -	    branch_predict_x <= branch_predict_d;
 22.2395 -	    branch_predict_taken_x <= branch_predict_taken_d;
 22.2396 -	    write_idx_x <= write_idx_d;
 22.2397 -            csr_x <= csr_d;
 22.2398 -            size_x <= size_d;
 22.2399 -            sign_extend_x <= sign_extend_d;
 22.2400 -            adder_op_x <= adder_op_d;
 22.2401 -            adder_op_x_n <= ~adder_op_d;
 22.2402 -            logic_op_x <= logic_op_d;
 22.2403 -`ifdef CFG_PL_BARREL_SHIFT_ENABLED
 22.2404 -            direction_x <= direction_d;
 22.2405 -`endif
 22.2406 -`ifdef CFG_ROTATE_ENABLED
 22.2407 -            rotate_x <= rotate_d;
 22.2408 -`endif
 22.2409 -            condition_x <= condition_d;
 22.2410 -            csr_write_enable_x <= csr_write_enable_d;
 22.2411 -`ifdef CFG_DEBUG_ENABLED
 22.2412 -            break_x <= break_d;
 22.2413 -`endif
 22.2414 -            scall_x <= scall_d;
 22.2415 -`ifdef CFG_BUS_ERRORS_ENABLED
 22.2416 -            bus_error_x <= bus_error_d;
 22.2417 -`endif
 22.2418 -            eret_x <= eret_d;
 22.2419 -`ifdef CFG_DEBUG_ENABLED
 22.2420 -            bret_x <= bret_d; 
 22.2421 -`endif
 22.2422 -            write_enable_x <= write_enable_d;
 22.2423 -        end
 22.2424 -        
 22.2425 -        // X/M stage registers
 22.2426 -
 22.2427 -        if (stall_m == `FALSE)
 22.2428 -        begin
 22.2429 -            operand_m <= x_result;
 22.2430 -            m_result_sel_compare_m <= m_result_sel_compare_x;
 22.2431 -`ifdef CFG_PL_BARREL_SHIFT_ENABLED
 22.2432 -            m_result_sel_shift_m <= m_result_sel_shift_x;
 22.2433 -`endif    
 22.2434 -            if (exception_x == `TRUE)
 22.2435 -            begin
 22.2436 -                w_result_sel_load_m <= `FALSE;
 22.2437 -`ifdef CFG_PL_MULTIPLY_ENABLED
 22.2438 -                w_result_sel_mul_m <= `FALSE;
 22.2439 -`endif
 22.2440 -            end
 22.2441 -            else
 22.2442 -            begin
 22.2443 -                w_result_sel_load_m <= w_result_sel_load_x;
 22.2444 -`ifdef CFG_PL_MULTIPLY_ENABLED
 22.2445 -                w_result_sel_mul_m <= w_result_sel_mul_x;
 22.2446 -`endif
 22.2447 -            end
 22.2448 -            m_bypass_enable_m <= m_bypass_enable_x;
 22.2449 -`ifdef CFG_PL_BARREL_SHIFT_ENABLED
 22.2450 -`endif
 22.2451 -            load_m <= load_x;
 22.2452 -            store_m <= store_x;
 22.2453 -`ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
 22.2454 -            branch_m <= branch_x && !branch_taken_x;
 22.2455 -`else
 22.2456 -            branch_m <= branch_x;
 22.2457 -	    branch_predict_m <= branch_predict_x;
 22.2458 -	    branch_predict_taken_m <= branch_predict_taken_x;
 22.2459 -`endif
 22.2460 -`ifdef CFG_DEBUG_ENABLED
 22.2461 -	   // Data bus errors are generated by the wishbone and are
 22.2462 -	   // made known to the processor only in next cycle (as a
 22.2463 -	   // non-debug exception). A break instruction can be seen
 22.2464 -	   // in same cycle (causing a debug exception). Handle non
 22.2465 -	   // -debug exception first!
 22.2466 -            if (non_debug_exception_x == `TRUE) 
 22.2467 -                write_idx_m <= `LM32_EA_REG;
 22.2468 -            else if (debug_exception_x == `TRUE)
 22.2469 -                write_idx_m <= `LM32_BA_REG;
 22.2470 -            else 
 22.2471 -                write_idx_m <= write_idx_x;
 22.2472 -`else
 22.2473 -            if (exception_x == `TRUE)
 22.2474 -                write_idx_m <= `LM32_EA_REG;
 22.2475 -            else 
 22.2476 -                write_idx_m <= write_idx_x;
 22.2477 -`endif
 22.2478 -            condition_met_m <= condition_met_x;
 22.2479 -`ifdef CFG_DEBUG_ENABLED
 22.2480 -	   if (exception_x == `TRUE)
 22.2481 -	     if ((dc_re == `TRUE)
 22.2482 -		 || ((debug_exception_x == `TRUE) 
 22.2483 -		     && (non_debug_exception_x == `FALSE)))
 22.2484 -	       branch_target_m <= {deba, eid_x, {3{1'b0}}};
 22.2485 -	     else
 22.2486 -	       branch_target_m <= {eba, eid_x, {3{1'b0}}};
 22.2487 -	   else
 22.2488 -	     branch_target_m <= branch_target_x;
 22.2489 -`else
 22.2490 -            branch_target_m <= exception_x == `TRUE ? {eba, eid_x, {3{1'b0}}} : branch_target_x;
 22.2491 -`endif
 22.2492 -`ifdef CFG_TRACE_ENABLED
 22.2493 -            eid_m <= eid_x;
 22.2494 -`endif
 22.2495 -`ifdef CFG_DCACHE_ENABLED
 22.2496 -            dflush_m <= dflush_x;
 22.2497 -`endif
 22.2498 -            eret_m <= eret_q_x;
 22.2499 -`ifdef CFG_DEBUG_ENABLED
 22.2500 -            bret_m <= bret_q_x; 
 22.2501 -`endif
 22.2502 -            write_enable_m <= exception_x == `TRUE ? `TRUE : write_enable_x;            
 22.2503 -`ifdef CFG_DEBUG_ENABLED
 22.2504 -            debug_exception_m <= debug_exception_x;
 22.2505 -            non_debug_exception_m <= non_debug_exception_x;        
 22.2506 -`endif
 22.2507 -        end
 22.2508 -        
 22.2509 -        // State changing regs
 22.2510 -        if (stall_m == `FALSE)
 22.2511 -        begin
 22.2512 -            if ((exception_x == `TRUE) && (q_x == `TRUE) && (stall_x == `FALSE))
 22.2513 -                exception_m <= `TRUE;
 22.2514 -            else 
 22.2515 -                exception_m <= `FALSE;
 22.2516 -`ifdef CFG_BUS_ERRORS_ENABLED
 22.2517 -	   data_bus_error_exception_m <=    (data_bus_error_exception == `TRUE) 
 22.2518 -`ifdef CFG_DEBUG_ENABLED
 22.2519 -					 && (reset_exception == `FALSE)
 22.2520 -`endif
 22.2521 -					 ;
 22.2522 -`endif
 22.2523 -	end
 22.2524 -                
 22.2525 -        // M/W stage registers
 22.2526 -`ifdef CFG_BUS_ERRORS_ENABLED
 22.2527 -        operand_w <= exception_m == `TRUE ? (data_bus_error_exception_m ? {memop_pc_w, 2'b00} : {pc_m, 2'b00}) : m_result;
 22.2528 -`else
 22.2529 -        operand_w <= exception_m == `TRUE ? {pc_m, 2'b00} : m_result;
 22.2530 -`endif
 22.2531 -        w_result_sel_load_w <= w_result_sel_load_m;
 22.2532 -`ifdef CFG_PL_MULTIPLY_ENABLED
 22.2533 -        w_result_sel_mul_w <= w_result_sel_mul_m;
 22.2534 -`endif
 22.2535 -        write_idx_w <= write_idx_m;
 22.2536 -`ifdef CFG_TRACE_ENABLED
 22.2537 -        eid_w <= eid_m;
 22.2538 -        eret_w <= eret_m;
 22.2539 -`ifdef CFG_DEBUG_ENABLED
 22.2540 -        bret_w <= bret_m; 
 22.2541 -`endif
 22.2542 -`endif
 22.2543 -        write_enable_w <= write_enable_m;
 22.2544 -`ifdef CFG_DEBUG_ENABLED
 22.2545 -        debug_exception_w <= debug_exception_m;
 22.2546 -        non_debug_exception_w <= non_debug_exception_m;
 22.2547 -`else
 22.2548 -        exception_w <= exception_m;
 22.2549 -`endif
 22.2550 -`ifdef CFG_BUS_ERRORS_ENABLED
 22.2551 -        if (   (stall_m == `FALSE)
 22.2552 -            && (   (load_q_m == `TRUE) 
 22.2553 -                || (store_q_m == `TRUE)
 22.2554 -               )
 22.2555 -	   )
 22.2556 -          memop_pc_w <= pc_m;
 22.2557 -`endif
 22.2558 -    end
 22.2559 -end
 22.2560 -
 22.2561 -`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
 22.2562 -// Buffer data read from register file, in case a stall occurs, and watch for
 22.2563 -// any writes to the modified registers
 22.2564 -always @(posedge clk_i `CFG_RESET_SENSITIVITY)
 22.2565 -begin
 22.2566 -    if (rst_i == `TRUE)
 22.2567 -    begin
 22.2568 -        use_buf <= `FALSE;
 22.2569 -        reg_data_buf_0 <= {`LM32_WORD_WIDTH{1'b0}};
 22.2570 -        reg_data_buf_1 <= {`LM32_WORD_WIDTH{1'b0}};
 22.2571 -    end
 22.2572 -    else
 22.2573 -    begin
 22.2574 -        if (stall_d == `FALSE)
 22.2575 -            use_buf <= `FALSE;
 22.2576 -        else if (use_buf == `FALSE)
 22.2577 -        begin        
 22.2578 -            reg_data_buf_0 <= reg_data_live_0;
 22.2579 -            reg_data_buf_1 <= reg_data_live_1;
 22.2580 -            use_buf <= `TRUE;
 22.2581 -        end        
 22.2582 -        if (reg_write_enable_q_w == `TRUE)
 22.2583 -        begin
 22.2584 -            if (write_idx_w == read_idx_0_d)
 22.2585 -                reg_data_buf_0 <= w_result;
 22.2586 -            if (write_idx_w == read_idx_1_d)
 22.2587 -                reg_data_buf_1 <= w_result;
 22.2588 -        end
 22.2589 -    end
 22.2590 -end
 22.2591 -`endif
 22.2592 -
 22.2593 -`ifdef LM32_EBR_REGISTER_FILE
 22.2594 -`else
 22.2595 -// Register file write port
 22.2596 -always @(posedge clk_i `CFG_RESET_SENSITIVITY)
 22.2597 -begin
 22.2598 -    if (rst_i == `TRUE) begin
 22.2599 -        registers[0] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2600 -        registers[1] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2601 -        registers[2] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2602 -        registers[3] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2603 -        registers[4] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2604 -        registers[5] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2605 -        registers[6] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2606 -        registers[7] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2607 -        registers[8] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2608 -        registers[9] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2609 -        registers[10] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2610 -        registers[11] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2611 -        registers[12] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2612 -        registers[13] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2613 -        registers[14] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2614 -        registers[15] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2615 -        registers[16] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2616 -        registers[17] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2617 -        registers[18] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2618 -        registers[19] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2619 -        registers[20] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2620 -        registers[21] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2621 -        registers[22] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2622 -        registers[23] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2623 -        registers[24] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2624 -        registers[25] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2625 -        registers[26] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2626 -        registers[27] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2627 -        registers[28] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2628 -        registers[29] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2629 -        registers[30] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2630 -        registers[31] <= {`LM32_WORD_WIDTH{1'b0}}; 
 22.2631 -        end
 22.2632 -    else begin
 22.2633 -        if (reg_write_enable_q_w == `TRUE)
 22.2634 -          registers[write_idx_w] <= w_result;
 22.2635 -        end
 22.2636 -end
 22.2637 -`endif
 22.2638 -
 22.2639 -`ifdef CFG_TRACE_ENABLED
 22.2640 -// PC tracing logic
 22.2641 -always @(posedge clk_i `CFG_RESET_SENSITIVITY)
 22.2642 -begin
 22.2643 -    if (rst_i == `TRUE)
 22.2644 -    begin
 22.2645 -        trace_pc_valid <= `FALSE;
 22.2646 -        trace_pc <= {`LM32_PC_WIDTH{1'b0}};
 22.2647 -        trace_exception <= `FALSE;
 22.2648 -        trace_eid <= `LM32_EID_RESET;
 22.2649 -        trace_eret <= `FALSE;
 22.2650 -`ifdef CFG_DEBUG_ENABLED
 22.2651 -        trace_bret <= `FALSE;
 22.2652 -`endif
 22.2653 -        pc_c <= `CFG_EBA_RESET/4;
 22.2654 -    end
 22.2655 -    else
 22.2656 -    begin
 22.2657 -        trace_pc_valid <= `FALSE;
 22.2658 -        // Has an exception occured
 22.2659 -`ifdef CFG_DEBUG_ENABLED
 22.2660 -        if ((debug_exception_q_w == `TRUE) || (non_debug_exception_q_w == `TRUE))
 22.2661 -`else
 22.2662 -        if (exception_q_w == `TRUE)
 22.2663 -`endif
 22.2664 -        begin        
 22.2665 -            trace_exception <= `TRUE;
 22.2666 -            trace_pc_valid <= `TRUE;
 22.2667 -            trace_pc <= pc_w;
 22.2668 -            trace_eid <= eid_w;
 22.2669 -        end
 22.2670 -        else
 22.2671 -            trace_exception <= `FALSE;
 22.2672 -        
 22.2673 -        if ((valid_w == `TRUE) && (!kill_w))
 22.2674 -        begin
 22.2675 -            // An instruction is commiting. Determine if it is non-sequential
 22.2676 -            if (pc_c + 1'b1 != pc_w)
 22.2677 -            begin
 22.2678 -                // Non-sequential instruction
 22.2679 -                trace_pc_valid <= `TRUE;
 22.2680 -                trace_pc <= pc_w;
 22.2681 -            end
 22.2682 -            // Record PC so we can determine if next instruction is sequential or not
 22.2683 -            pc_c <= pc_w;
 22.2684 -            // Indicate if it was an eret/bret instruction
 22.2685 -            trace_eret <= eret_w;
 22.2686 -`ifdef CFG_DEBUG_ENABLED
 22.2687 -            trace_bret <= bret_w;
 22.2688 -`endif
 22.2689 -        end
 22.2690 -        else
 22.2691 -        begin
 22.2692 -            trace_eret <= `FALSE;
 22.2693 -`ifdef CFG_DEBUG_ENABLED
 22.2694 -            trace_bret <= `FALSE;
 22.2695 -`endif
 22.2696 -        end
 22.2697 -    end
 22.2698 -end
 22.2699 -`endif
 22.2700 -      
 22.2701 -/////////////////////////////////////////////////////
 22.2702 -// Behavioural Logic
 22.2703 -/////////////////////////////////////////////////////
 22.2704 -
 22.2705 -// synthesis translate_off            
 22.2706 -
 22.2707 -// Reset register 0. Only needed for simulation. 
 22.2708 -initial
 22.2709 -begin
 22.2710 -`ifdef LM32_EBR_REGISTER_FILE
 22.2711 -    reg_0.mem[0] = {`LM32_WORD_WIDTH{1'b0}};
 22.2712 -    reg_1.mem[0] = {`LM32_WORD_WIDTH{1'b0}};
 22.2713 -`else
 22.2714 -    registers[0] = {`LM32_WORD_WIDTH{1'b0}};
 22.2715 -`endif
 22.2716 -end
 22.2717 -
 22.2718 -// synthesis translate_on
 22.2719 -        
 22.2720 -endmodule 

    23.1 --- a/lm32_dcache.v	Sun Mar 06 21:17:31 2011 +0000
    23.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    23.3 @@ -1,542 +0,0 @@
    23.4 -// =============================================================================
    23.5 -//                           COPYRIGHT NOTICE
    23.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation
    23.7 -// ALL RIGHTS RESERVED
    23.8 -// This confidential and proprietary software may be used only as authorised by
    23.9 -// a licensing agreement from Lattice Semiconductor Corporation.
   23.10 -// The entire notice above must be reproduced on all authorized copies and
   23.11 -// copies may only be made to the extent permitted by a licensing agreement from
   23.12 -// Lattice Semiconductor Corporation.
   23.13 -//
   23.14 -// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
   23.15 -// 5555 NE Moore Court                            408-826-6000 (other locations)
   23.16 -// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
   23.17 -// U.S.A                                   email: techsupport@latticesemi.com
   23.18 -// =============================================================================/
   23.19 -//                         FILE DETAILS
   23.20 -// Project          : LatticeMico32
   23.21 -// File             : lm32_dcache.v
   23.22 -// Title            : Data cache
   23.23 -// Dependencies     : lm32_include.v
   23.24 -// Version          : 6.1.17
   23.25 -//                  : Initial Release
   23.26 -// Version          : 7.0SP2, 3.0
   23.27 -//                  : No Change
   23.28 -// Version	    : 3.1
   23.29 -//                  : Support for user-selected resource usage when implementing
   23.30 -//                  : cache memory. Additional parameters must be defined when
   23.31 -//                  : invoking lm32_ram.v
   23.32 -// =============================================================================
   23.33 -								 
   23.34 -`include "lm32_include.v"
   23.35 -
   23.36 -`ifdef CFG_DCACHE_ENABLED
   23.37 -
   23.38 -`define LM32_DC_ADDR_OFFSET_RNG          addr_offset_msb:addr_offset_lsb
   23.39 -`define LM32_DC_ADDR_SET_RNG             addr_set_msb:addr_set_lsb
   23.40 -`define LM32_DC_ADDR_TAG_RNG             addr_tag_msb:addr_tag_lsb
   23.41 -`define LM32_DC_ADDR_IDX_RNG             addr_set_msb:addr_offset_lsb
   23.42 -
   23.43 -`define LM32_DC_TMEM_ADDR_WIDTH          addr_set_width
   23.44 -`define LM32_DC_TMEM_ADDR_RNG            (`LM32_DC_TMEM_ADDR_WIDTH-1):0
   23.45 -`define LM32_DC_DMEM_ADDR_WIDTH          (addr_offset_width+addr_set_width)
   23.46 -`define LM32_DC_DMEM_ADDR_RNG            (`LM32_DC_DMEM_ADDR_WIDTH-1):0
   23.47 -
   23.48 -`define LM32_DC_TAGS_WIDTH               (addr_tag_width+1)
   23.49 -`define LM32_DC_TAGS_RNG                 (`LM32_DC_TAGS_WIDTH-1):0
   23.50 -`define LM32_DC_TAGS_TAG_RNG             (`LM32_DC_TAGS_WIDTH-1):1
   23.51 -`define LM32_DC_TAGS_VALID_RNG           0
   23.52 -
   23.53 -`define LM32_DC_STATE_RNG                2:0
   23.54 -`define LM32_DC_STATE_FLUSH              3'b001
   23.55 -`define LM32_DC_STATE_CHECK              3'b010
   23.56 -`define LM32_DC_STATE_REFILL             3'b100
   23.57 -
   23.58 -/////////////////////////////////////////////////////
   23.59 -// Module interface
   23.60 -/////////////////////////////////////////////////////
   23.61 -
   23.62 -module lm32_dcache ( 
   23.63 -    // ----- Inputs -----
   23.64 -    clk_i,
   23.65 -    rst_i,    
   23.66 -    stall_a,
   23.67 -    stall_x,
   23.68 -    stall_m,
   23.69 -    address_x,
   23.70 -    address_m,
   23.71 -    load_q_m,
   23.72 -    store_q_m,
   23.73 -    store_data,
   23.74 -    store_byte_select,
   23.75 -    refill_ready,
   23.76 -    refill_data,
   23.77 -    dflush,
   23.78 -    // ----- Outputs -----
   23.79 -    stall_request,
   23.80 -    restart_request,
   23.81 -    refill_request,
   23.82 -    refill_address,
   23.83 -    refilling,
   23.84 -    load_data
   23.85 -    );
   23.86 -
   23.87 -/////////////////////////////////////////////////////
   23.88 -// Parameters
   23.89 -/////////////////////////////////////////////////////
   23.90 -
   23.91 -parameter associativity = 1;                            // Associativity of the cache (Number of ways)
   23.92 -parameter sets = 512;                                   // Number of sets
   23.93 -parameter bytes_per_line = 16;                          // Number of bytes per cache line
   23.94 -parameter base_address = 0;                             // Base address of cachable memory
   23.95 -parameter limit = 0;                                    // Limit (highest address) of cachable memory
   23.96 -
   23.97 -localparam addr_offset_width = clogb2(bytes_per_line)-1-2;
   23.98 -localparam addr_set_width = clogb2(sets)-1;
   23.99 -localparam addr_offset_lsb = 2;
  23.100 -localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
  23.101 -localparam addr_set_lsb = (addr_offset_msb+1);
  23.102 -localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
  23.103 -localparam addr_tag_lsb = (addr_set_msb+1);
  23.104 -localparam addr_tag_msb = clogb2(`CFG_DCACHE_LIMIT-`CFG_DCACHE_BASE_ADDRESS)-1;
  23.105 -localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);
  23.106 -
  23.107 -/////////////////////////////////////////////////////
  23.108 -// Inputs
  23.109 -/////////////////////////////////////////////////////
  23.110 -
  23.111 -input clk_i;                                            // Clock
  23.112 -input rst_i;                                            // Reset
  23.113 -
  23.114 -input stall_a;                                          // Stall A stage
  23.115 -input stall_x;                                          // Stall X stage
  23.116 -input stall_m;                                          // Stall M stage
  23.117 -
  23.118 -input [`LM32_WORD_RNG] address_x;                       // X stage load/store address
  23.119 -input [`LM32_WORD_RNG] address_m;                       // M stage load/store address
  23.120 -input load_q_m;                                         // Load instruction in M stage
  23.121 -input store_q_m;                                        // Store instruction in M stage
  23.122 -input [`LM32_WORD_RNG] store_data;                      // Data to store
  23.123 -input [`LM32_BYTE_SELECT_RNG] store_byte_select;        // Which bytes in store data should be modified
  23.124 -
  23.125 -input refill_ready;                                     // Indicates next word of refill data is ready
  23.126 -input [`LM32_WORD_RNG] refill_data;                     // Refill data
  23.127 -
  23.128 -input dflush;                                           // Indicates cache should be flushed
  23.129 -
  23.130 -/////////////////////////////////////////////////////
  23.131 -// Outputs
  23.132 -/////////////////////////////////////////////////////
  23.133 -
  23.134 -output stall_request;                                   // Request pipeline be stalled because cache is busy
  23.135 -wire   stall_request;
  23.136 -output restart_request;                                 // Request to restart instruction that caused the cache miss
  23.137 -reg    restart_request;
  23.138 -output refill_request;                                  // Request a refill 
  23.139 -reg    refill_request;
  23.140 -output [`LM32_WORD_RNG] refill_address;                 // Address to refill from
  23.141 -reg    [`LM32_WORD_RNG] refill_address;
  23.142 -output refilling;                                       // Indicates if the cache is currently refilling
  23.143 -reg    refilling;
  23.144 -output [`LM32_WORD_RNG] load_data;                      // Data read from cache
  23.145 -wire   [`LM32_WORD_RNG] load_data;
  23.146 -
  23.147 -/////////////////////////////////////////////////////
  23.148 -// Internal nets and registers 
  23.149 -/////////////////////////////////////////////////////
  23.150 -
  23.151 -wire read_port_enable;                                  // Cache memory read port clock enable
  23.152 -wire write_port_enable;                                 // Cache memory write port clock enable
  23.153 -wire [0:associativity-1] way_tmem_we;                   // Tag memory write enable
  23.154 -wire [0:associativity-1] way_dmem_we;                   // Data memory write enable
  23.155 -wire [`LM32_WORD_RNG] way_data[0:associativity-1];      // Data read from data memory
  23.156 -wire [`LM32_DC_TAGS_TAG_RNG] way_tag[0:associativity-1];// Tag read from tag memory
  23.157 -wire [0:associativity-1] way_valid;                     // Indicates which ways are valid
  23.158 -wire [0:associativity-1] way_match;                     // Indicates which ways matched
  23.159 -wire miss;                                              // Indicates no ways matched
  23.160 -
  23.161 -wire [`LM32_DC_TMEM_ADDR_RNG] tmem_read_address;        // Tag memory read address
  23.162 -wire [`LM32_DC_TMEM_ADDR_RNG] tmem_write_address;       // Tag memory write address
  23.163 -wire [`LM32_DC_DMEM_ADDR_RNG] dmem_read_address;        // Data memory read address
  23.164 -wire [`LM32_DC_DMEM_ADDR_RNG] dmem_write_address;       // Data memory write address
  23.165 -wire [`LM32_DC_TAGS_RNG] tmem_write_data;               // Tag memory write data        
  23.166 -reg [`LM32_WORD_RNG] dmem_write_data;                   // Data memory write data
  23.167 -
  23.168 -reg [`LM32_DC_STATE_RNG] state;                         // Current state of FSM
  23.169 -wire flushing;                                          // Indicates if cache is currently flushing
  23.170 -wire check;                                             // Indicates if cache is currently checking for hits/misses
  23.171 -wire refill;                                            // Indicates if cache is currently refilling
  23.172 -
  23.173 -wire valid_store;                                       // Indicates if there is a valid store instruction
  23.174 -reg [associativity-1:0] refill_way_select;              // Which way should be refilled
  23.175 -reg [`LM32_DC_ADDR_OFFSET_RNG] refill_offset;           // Which word in cache line should be refilled
  23.176 -wire last_refill;                                       // Indicates when on last cycle of cache refill
  23.177 -reg [`LM32_DC_TMEM_ADDR_RNG] flush_set;                 // Which set is currently being flushed
  23.178 -
  23.179 -genvar i, j;
  23.180 -
  23.181 -/////////////////////////////////////////////////////
  23.182 -// Functions
  23.183 -/////////////////////////////////////////////////////
  23.184 -
  23.185 -`include "lm32_functions.v"
  23.186 -
  23.187 -/////////////////////////////////////////////////////
  23.188 -// Instantiations
  23.189 -/////////////////////////////////////////////////////
  23.190 -
  23.191 -   generate
  23.192 -      for (i = 0; i < associativity; i = i + 1)    
  23.193 -	begin : memories
  23.194 -	   // Way data
  23.195 -           if (`LM32_DC_DMEM_ADDR_WIDTH < 11)
  23.196 -             begin : data_memories
  23.197 -		lm32_ram 
  23.198 -		  #(
  23.199 -		    // ----- Parameters -------
  23.200 -		    .data_width (32),
  23.201 -		    .address_width (`LM32_DC_DMEM_ADDR_WIDTH)
  23.202 -`ifdef PLATFORM_LATTICE
  23.203 -			,
  23.204 - `ifdef CFG_DCACHE_DAT_USE_DP_TRUE
  23.205 -		    .RAM_IMPLEMENTATION ("EBR"),
  23.206 -		    .RAM_TYPE ("RAM_DP_TRUE")
  23.207 - `else
  23.208 -  `ifdef CFG_DCACHE_DAT_USE_SLICE
  23.209 -		    .RAM_IMPLEMENTATION ("SLICE")
  23.210 -  `else
  23.211 -		    .RAM_IMPLEMENTATION ("AUTO")
  23.212 -  `endif
  23.213 - `endif
  23.214 -`endif
  23.215 -		    ) way_0_data_ram 
  23.216 -		    (
  23.217 -		     // ----- Inputs -------
  23.218 -		     .read_clk (clk_i),
  23.219 -		     .write_clk (clk_i),
  23.220 -		     .reset (rst_i),
  23.221 -		     .read_address (dmem_read_address),
  23.222 -		     .enable_read (read_port_enable),
  23.223 -		     .write_address (dmem_write_address),
  23.224 -		     .enable_write (write_port_enable),
  23.225 -		     .write_enable (way_dmem_we[i]),
  23.226 -		     .write_data (dmem_write_data),    
  23.227 -		     // ----- Outputs -------
  23.228 -		     .read_data (way_data[i])
  23.229 -		     );    
  23.230 -             end
  23.231 -           else
  23.232 -             begin
  23.233 -		for (j = 0; j < 4; j = j + 1)    
  23.234 -		  begin : byte_memories
  23.235 -		     lm32_ram 
  23.236 -		       #(
  23.237 -			 // ----- Parameters -------
  23.238 -			 .data_width (8),
  23.239 -			 .address_width (`LM32_DC_DMEM_ADDR_WIDTH)
  23.240 -`ifdef PLATFORM_LATTICE
  23.241 -			 ,
  23.242 - `ifdef CFG_DCACHE_DAT_USE_DP_TRUE
  23.243 -			 .RAM_IMPLEMENTATION ("EBR"),
  23.244 -			 .RAM_TYPE ("RAM_DP_TRUE")
  23.245 - `else
  23.246 -  `ifdef CFG_DCACHE_DAT_USE_SLICE
  23.247 -			 .RAM_IMPLEMENTATION ("SLICE")
  23.248 -  `else
  23.249 -			 .RAM_IMPLEMENTATION ("AUTO")
  23.250 -  `endif
  23.251 - `endif
  23.252 -`endif
  23.253 -			 ) way_0_data_ram 
  23.254 -			 (
  23.255 -			  // ----- Inputs -------
  23.256 -			  .read_clk (clk_i),
  23.257 -			  .write_clk (clk_i),
  23.258 -			  .reset (rst_i),
  23.259 -			  .read_address (dmem_read_address),
  23.260 -			  .enable_read (read_port_enable),
  23.261 -			  .write_address (dmem_write_address),
  23.262 -			  .enable_write (write_port_enable),
  23.263 -			  .write_enable (way_dmem_we[i] & (store_byte_select[j] | refill)),
  23.264 -			  .write_data (dmem_write_data[(j+1)*8-1:j*8]),    
  23.265 -			  // ----- Outputs -------
  23.266 -			  .read_data (way_data[i][(j+1)*8-1:j*8])
  23.267 -			  );
  23.268 -		  end
  23.269 -             end
  23.270 -	   
  23.271 -	   // Way tags
  23.272 -	   lm32_ram 
  23.273 -	     #(
  23.274 -	       // ----- Parameters -------
  23.275 -	       .data_width (`LM32_DC_TAGS_WIDTH),
  23.276 -	       .address_width (`LM32_DC_TMEM_ADDR_WIDTH)
  23.277 -`ifdef PLATFORM_LATTICE
  23.278 -			 ,
  23.279 - `ifdef CFG_DCACHE_DAT_USE_DP_TRUE
  23.280 -	       .RAM_IMPLEMENTATION ("EBR"),
  23.281 -	       .RAM_TYPE ("RAM_DP_TRUE")
  23.282 - `else
  23.283 -  `ifdef CFG_DCACHE_DAT_USE_SLICE
  23.284 -	       .RAM_IMPLEMENTATION ("SLICE")
  23.285 -  `else
  23.286 -	       .RAM_IMPLEMENTATION ("AUTO")
  23.287 -  `endif
  23.288 - `endif
  23.289 -`endif
  23.290 -	       ) way_0_tag_ram 
  23.291 -	       (
  23.292 -		// ----- Inputs -------
  23.293 -		.read_clk (clk_i),
  23.294 -		.write_clk (clk_i),
  23.295 -		.reset (rst_i),
  23.296 -		.read_address (tmem_read_address),
  23.297 -		.enable_read (read_port_enable),
  23.298 -		.write_address (tmem_write_address),
  23.299 -		.enable_write (`TRUE),
  23.300 -		.write_enable (way_tmem_we[i]),
  23.301 -		.write_data (tmem_write_data),
  23.302 -		// ----- Outputs -------
  23.303 -		.read_data ({way_tag[i], way_valid[i]})
  23.304 -		);
  23.305 -	end
  23.306 -      
  23.307 -   endgenerate
  23.308 -
  23.309 -/////////////////////////////////////////////////////
  23.310 -// Combinational logic
  23.311 -/////////////////////////////////////////////////////
  23.312 -
  23.313 -// Compute which ways in the cache match the address being read
  23.314 -generate
  23.315 -    for (i = 0; i < associativity; i = i + 1)
  23.316 -    begin : match
  23.317 -assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_m[`LM32_DC_ADDR_TAG_RNG], `TRUE});
  23.318 -    end
  23.319 -endgenerate
  23.320 -
  23.321 -// Select data from way that matched the address being read     
  23.322 -generate
  23.323 -    if (associativity == 1)    
  23.324 -	 begin : data_1
  23.325 -assign load_data = way_data[0];
  23.326 -    end
  23.327 -    else if (associativity == 2)
  23.328 -	 begin : data_2
  23.329 -assign load_data = way_match[0] ? way_data[0] : way_data[1]; 
  23.330 -    end
  23.331 -endgenerate
  23.332 -
  23.333 -generate
  23.334 -    if (`LM32_DC_DMEM_ADDR_WIDTH < 11)
  23.335 -    begin
  23.336 -// Select data to write to data memories
  23.337 -always @(*)
  23.338 -begin
  23.339 -    if (refill == `TRUE)
  23.340 -        dmem_write_data = refill_data;
  23.341 -    else
  23.342 -    begin
  23.343 -        dmem_write_data[`LM32_BYTE_0_RNG] = store_byte_select[0] ? store_data[`LM32_BYTE_0_RNG] : load_data[`LM32_BYTE_0_RNG];
  23.344 -        dmem_write_data[`LM32_BYTE_1_RNG] = store_byte_select[1] ? store_data[`LM32_BYTE_1_RNG] : load_data[`LM32_BYTE_1_RNG];
  23.345 -        dmem_write_data[`LM32_BYTE_2_RNG] = store_byte_select[2] ? store_data[`LM32_BYTE_2_RNG] : load_data[`LM32_BYTE_2_RNG];
  23.346 -        dmem_write_data[`LM32_BYTE_3_RNG] = store_byte_select[3] ? store_data[`LM32_BYTE_3_RNG] : load_data[`LM32_BYTE_3_RNG];
  23.347 -    end
  23.348 -end
  23.349 -    end
  23.350 -    else
  23.351 -    begin
  23.352 -// Select data to write to data memories - FIXME: Should use different write ports on dual port RAMs, but they don't work
  23.353 -always @(*)
  23.354 -begin
  23.355 -    if (refill == `TRUE)
  23.356 -        dmem_write_data = refill_data;
  23.357 -    else
  23.358 -        dmem_write_data = store_data;
  23.359 -end
  23.360 -    end
  23.361 -endgenerate
  23.362 -
  23.363 -// Compute address to use to index into the data memories
  23.364 -generate 
  23.365 -     if (bytes_per_line > 4)
  23.366 -assign dmem_write_address = (refill == `TRUE) 
  23.367 -                            ? {refill_address[`LM32_DC_ADDR_SET_RNG], refill_offset}
  23.368 -                            : address_m[`LM32_DC_ADDR_IDX_RNG];
  23.369 -    else
  23.370 -assign dmem_write_address = (refill == `TRUE) 
  23.371 -                            ? refill_address[`LM32_DC_ADDR_SET_RNG]
  23.372 -                            : address_m[`LM32_DC_ADDR_IDX_RNG];
  23.373 -endgenerate
  23.374 -assign dmem_read_address = address_x[`LM32_DC_ADDR_IDX_RNG];
  23.375 -// Compute address to use to index into the tag memories   
  23.376 -assign tmem_write_address = (flushing == `TRUE)
  23.377 -                            ? flush_set
  23.378 -                            : refill_address[`LM32_DC_ADDR_SET_RNG];
  23.379 -assign tmem_read_address = address_x[`LM32_DC_ADDR_SET_RNG];
  23.380 -
  23.381 -// Compute signal to indicate when we are on the last refill accesses
  23.382 -generate 
  23.383 -    if (bytes_per_line > 4)                            
  23.384 -assign last_refill = refill_offset == {addr_offset_width{1'b1}};
  23.385 -    else
  23.386 -assign last_refill = `TRUE;
  23.387 -endgenerate
  23.388 -
  23.389 -// Compute data and tag memory access enable
  23.390 -assign read_port_enable = (stall_x == `FALSE);
  23.391 -assign write_port_enable = (refill_ready == `TRUE) || !stall_m;
  23.392 -
  23.393 -// Determine when we have a valid store
  23.394 -assign valid_store = (store_q_m == `TRUE) && (check == `TRUE);
  23.395 -
  23.396 -// Compute data and tag memory write enables
  23.397 -generate
  23.398 -    if (associativity == 1) 
  23.399 -    begin : we_1     
  23.400 -assign way_dmem_we[0] = (refill_ready == `TRUE) || ((valid_store == `TRUE) && (way_match[0] == `TRUE));
  23.401 -assign way_tmem_we[0] = (refill_ready == `TRUE) || (flushing == `TRUE);
  23.402 -    end 
  23.403 -    else 
  23.404 -    begin : we_2
  23.405 -assign way_dmem_we[0] = ((refill_ready == `TRUE) && (refill_way_select[0] == `TRUE)) || ((valid_store == `TRUE) && (way_match[0] == `TRUE));
  23.406 -assign way_dmem_we[1] = ((refill_ready == `TRUE) && (refill_way_select[1] == `TRUE)) || ((valid_store == `TRUE) && (way_match[1] == `TRUE));
  23.407 -assign way_tmem_we[0] = ((refill_ready == `TRUE) && (refill_way_select[0] == `TRUE)) || (flushing == `TRUE);
  23.408 -assign way_tmem_we[1] = ((refill_ready == `TRUE) && (refill_way_select[1] == `TRUE)) || (flushing == `TRUE);
  23.409 -    end
  23.410 -endgenerate
  23.411 -
  23.412 -// On the last refill cycle set the valid bit, for all other writes it should be cleared
  23.413 -assign tmem_write_data[`LM32_DC_TAGS_VALID_RNG] = ((last_refill == `TRUE) || (valid_store == `TRUE)) && (flushing == `FALSE);
  23.414 -assign tmem_write_data[`LM32_DC_TAGS_TAG_RNG] = refill_address[`LM32_DC_ADDR_TAG_RNG];
  23.415 -
  23.416 -// Signals that indicate which state we are in
  23.417 -assign flushing = state[0];
  23.418 -assign check = state[1];
  23.419 -assign refill = state[2];
  23.420 -
  23.421 -assign miss = (~(|way_match)) && (load_q_m == `TRUE) && (stall_m == `FALSE);
  23.422 -assign stall_request = (check == `FALSE);
  23.423 -                      
  23.424 -/////////////////////////////////////////////////////
  23.425 -// Sequential logic
  23.426 -/////////////////////////////////////////////////////
  23.427 -
  23.428 -// Record way selected for replacement on a cache miss
  23.429 -generate
  23.430 -    if (associativity >= 2) 
  23.431 -    begin : way_select      
  23.432 -always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  23.433 -begin
  23.434 -    if (rst_i == `TRUE)
  23.435 -        refill_way_select <= {{associativity-1{1'b0}}, 1'b1};
  23.436 -    else
  23.437 -    begin        
  23.438 -        if (refill_request == `TRUE)
  23.439 -            refill_way_select <= {refill_way_select[0], refill_way_select[1]};
  23.440 -    end
  23.441 -end
  23.442 -    end 
  23.443 -endgenerate   
  23.444 -
  23.445 -// Record whether we are currently refilling
  23.446 -always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  23.447 -begin
  23.448 -    if (rst_i == `TRUE)
  23.449 -        refilling <= `FALSE;
  23.450 -    else 
  23.451 -        refilling <= refill;
  23.452 -end
  23.453 -
  23.454 -// Instruction cache control FSM
  23.455 -always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  23.456 -begin
  23.457 -    if (rst_i == `TRUE)
  23.458 -    begin
  23.459 -        state <= `LM32_DC_STATE_FLUSH;
  23.460 -        flush_set <= {`LM32_DC_TMEM_ADDR_WIDTH{1'b1}};
  23.461 -        refill_request <= `FALSE;
  23.462 -        refill_address <= {`LM32_WORD_WIDTH{1'bx}};
  23.463 -        restart_request <= `FALSE;
  23.464 -    end
  23.465 -    else 
  23.466 -    begin
  23.467 -        case (state)
  23.468 -
  23.469 -        // Flush the cache 
  23.470 -        `LM32_DC_STATE_FLUSH:
  23.471 -        begin
  23.472 -            if (flush_set == {`LM32_DC_TMEM_ADDR_WIDTH{1'b0}})
  23.473 -                state <= `LM32_DC_STATE_CHECK;
  23.474 -            flush_set <= flush_set - 1'b1;
  23.475 -        end
  23.476 -        
  23.477 -        // Check for cache misses
  23.478 -        `LM32_DC_STATE_CHECK:
  23.479 -        begin
  23.480 -            if (stall_a == `FALSE)
  23.481 -                restart_request <= `FALSE;
  23.482 -            if (miss == `TRUE)
  23.483 -            begin
  23.484 -                refill_request <= `TRUE;
  23.485 -                refill_address <= address_m;
  23.486 -                state <= `LM32_DC_STATE_REFILL;
  23.487 -            end
  23.488 -            else if (dflush == `TRUE)
  23.489 -                state <= `LM32_DC_STATE_FLUSH;
  23.490 -        end
  23.491 -
  23.492 -        // Refill a cache line
  23.493 -        `LM32_DC_STATE_REFILL:
  23.494 -        begin
  23.495 -            refill_request <= `FALSE;
  23.496 -            if (refill_ready == `TRUE)
  23.497 -            begin
  23.498 -                if (last_refill == `TRUE)
  23.499 -                begin
  23.500 -                    restart_request <= `TRUE;
  23.501 -                    state <= `LM32_DC_STATE_CHECK;
  23.502 -                end
  23.503 -            end
  23.504 -        end
  23.505 -        
  23.506 -        endcase        
  23.507 -    end
  23.508 -end
  23.509 -
  23.510 -generate
  23.511 -    if (bytes_per_line > 4)
  23.512 -    begin
  23.513 -// Refill offset
  23.514 -always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  23.515 -begin
  23.516 -    if (rst_i == `TRUE)
  23.517 -        refill_offset <= {addr_offset_width{1'b0}};
  23.518 -    else 
  23.519 -    begin
  23.520 -        case (state)
  23.521 -        
  23.522 -        // Check for cache misses
  23.523 -        `LM32_DC_STATE_CHECK:
  23.524 -        begin
  23.525 -            if (miss == `TRUE)
  23.526 -                refill_offset <= {addr_offset_width{1'b0}};
  23.527 -        end
  23.528 -
  23.529 -        // Refill a cache line
  23.530 -        `LM32_DC_STATE_REFILL:
  23.531 -        begin
  23.532 -            if (refill_ready == `TRUE)
  23.533 -                refill_offset <= refill_offset + 1'b1;
  23.534 -        end
  23.535 -        
  23.536 -        endcase        
  23.537 -    end
  23.538 -end
  23.539 -    end
  23.540 -endgenerate
  23.541 -
  23.542 -endmodule
  23.543 -
  23.544 -`endif
  23.545 -

    24.1 --- a/lm32_debug.v	Sun Mar 06 21:17:31 2011 +0000
    24.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    24.3 @@ -1,348 +0,0 @@
    24.4 -// =============================================================================
    24.5 -//                           COPYRIGHT NOTICE
    24.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation
    24.7 -// ALL RIGHTS RESERVED
    24.8 -// This confidential and proprietary software may be used only as authorised by
    24.9 -// a licensing agreement from Lattice Semiconductor Corporation.
   24.10 -// The entire notice above must be reproduced on all authorized copies and
   24.11 -// copies may only be made to the extent permitted by a licensing agreement from
   24.12 -// Lattice Semiconductor Corporation.
   24.13 -//
   24.14 -// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
   24.15 -// 5555 NE Moore Court                            408-826-6000 (other locations)
   24.16 -// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
   24.17 -// U.S.A                                   email: techsupport@latticesemi.com
   24.18 -// =============================================================================/
   24.19 -//                         FILE DETAILS
   24.20 -// Project          : LatticeMico32
   24.21 -// File             : lm32_debug.v
   24.22 -// Title            : Hardware debug registers and associated logic.
   24.23 -// Dependencies     : lm32_include.v
   24.24 -// Version          : 6.1.17
   24.25 -//                  : Initial Release
   24.26 -// Version          : 7.0SP2, 3.0
   24.27 -//                  : No Change
   24.28 -// Version          : 3.1
   24.29 -//                  : No Change
   24.30 -// Version          : 3.2
   24.31 -//                  : Fixed simulation bug which flares up when number of 
   24.32 -//                  : watchpoints is zero.
   24.33 -// =============================================================================
   24.34 -
   24.35 -`include "lm32_include.v"
   24.36 -
   24.37 -`ifdef CFG_DEBUG_ENABLED
   24.38 -
   24.39 -// States for single-step FSM
   24.40 -`define LM32_DEBUG_SS_STATE_RNG                 2:0
   24.41 -`define LM32_DEBUG_SS_STATE_IDLE                3'b000
   24.42 -`define LM32_DEBUG_SS_STATE_WAIT_FOR_RET        3'b001
   24.43 -`define LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN    3'b010
   24.44 -`define LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT    3'b011
   24.45 -`define LM32_DEBUG_SS_STATE_RESTART             3'b100
   24.46 -
   24.47 -/////////////////////////////////////////////////////
   24.48 -// Module interface
   24.49 -/////////////////////////////////////////////////////
   24.50 -
   24.51 -module lm32_debug (
   24.52 -    // ----- Inputs -------
   24.53 -    clk_i, 
   24.54 -    rst_i,
   24.55 -    pc_x,
   24.56 -    load_x,
   24.57 -    store_x,
   24.58 -    load_store_address_x,
   24.59 -    csr_write_enable_x,
   24.60 -    csr_write_data,
   24.61 -    csr_x,
   24.62 -`ifdef CFG_HW_DEBUG_ENABLED
   24.63 -    jtag_csr_write_enable,
   24.64 -    jtag_csr_write_data,
   24.65 -    jtag_csr,
   24.66 -`endif
   24.67 -`ifdef LM32_SINGLE_STEP_ENABLED
   24.68 -    eret_q_x,
   24.69 -    bret_q_x,
   24.70 -    stall_x,
   24.71 -    exception_x,
   24.72 -    q_x,
   24.73 -`ifdef CFG_DCACHE_ENABLED
   24.74 -    dcache_refill_request,
   24.75 -`endif
   24.76 -`endif
   24.77 -    // ----- Outputs -------
   24.78 -`ifdef LM32_SINGLE_STEP_ENABLED
   24.79 -    dc_ss,
   24.80 -`endif
   24.81 -    dc_re,
   24.82 -    bp_match,
   24.83 -    wp_match
   24.84 -    );
   24.85 -    
   24.86 -/////////////////////////////////////////////////////
   24.87 -// Parameters
   24.88 -/////////////////////////////////////////////////////
   24.89 -
   24.90 -parameter breakpoints = 0;                      // Number of breakpoint CSRs
   24.91 -parameter watchpoints = 0;                      // Number of watchpoint CSRs
   24.92 -
   24.93 -/////////////////////////////////////////////////////
   24.94 -// Inputs
   24.95 -/////////////////////////////////////////////////////
   24.96 -
   24.97 -input clk_i;                                    // Clock
   24.98 -input rst_i;                                    // Reset
   24.99 -
  24.100 -input [`LM32_PC_RNG] pc_x;                      // X stage PC
  24.101 -input load_x;                                   // Load instruction in X stage
  24.102 -input store_x;                                  // Store instruction in X stage
  24.103 -input [`LM32_WORD_RNG] load_store_address_x;    // Load or store effective address
  24.104 -input csr_write_enable_x;                       // wcsr instruction in X stage
  24.105 -input [`LM32_WORD_RNG] csr_write_data;          // Data to write to CSR
  24.106 -input [`LM32_CSR_RNG] csr_x;                    // Which CSR to write
  24.107 -`ifdef CFG_HW_DEBUG_ENABLED
  24.108 -input jtag_csr_write_enable;                    // JTAG interface CSR write enable
  24.109 -input [`LM32_WORD_RNG] jtag_csr_write_data;     // Data to write to CSR
  24.110 -input [`LM32_CSR_RNG] jtag_csr;                 // Which CSR to write
  24.111 -`endif
  24.112 -`ifdef LM32_SINGLE_STEP_ENABLED
  24.113 -input eret_q_x;                                 // eret instruction in X stage
  24.114 -input bret_q_x;                                 // bret instruction in X stage
  24.115 -input stall_x;                                  // Instruction in X stage is stalled
  24.116 -input exception_x;                              // An exception has occured in X stage 
  24.117 -input q_x;                                      // Indicates the instruction in the X stage is qualified
  24.118 -`ifdef CFG_DCACHE_ENABLED
  24.119 -input dcache_refill_request;                    // Indicates data cache wants to be refilled 
  24.120 -`endif
  24.121 -`endif
  24.122 -
  24.123 -/////////////////////////////////////////////////////
  24.124 -// Outputs
  24.125 -/////////////////////////////////////////////////////
  24.126 -
  24.127 -`ifdef LM32_SINGLE_STEP_ENABLED
  24.128 -output dc_ss;                                   // Single-step enable
  24.129 -reg    dc_ss;
  24.130 -`endif
  24.131 -output dc_re;                                   // Remap exceptions
  24.132 -reg    dc_re;
  24.133 -output bp_match;                                // Indicates a breakpoint has matched
  24.134 -wire   bp_match;        
  24.135 -output wp_match;                                // Indicates a watchpoint has matched
  24.136 -wire   wp_match;
  24.137 -
  24.138 -/////////////////////////////////////////////////////
  24.139 -// Internal nets and registers 
  24.140 -/////////////////////////////////////////////////////
  24.141 -
  24.142 -genvar i;                                       // Loop index for generate statements
  24.143 -
  24.144 -// Debug CSRs
  24.145 -
  24.146 -reg [`LM32_PC_RNG] bp_a[0:breakpoints-1];       // Instruction breakpoint address
  24.147 -reg bp_e[0:breakpoints-1];                      // Instruction breakpoint enable
  24.148 -wire [0:breakpoints-1]bp_match_n;               // Indicates if a h/w instruction breakpoint matched
  24.149 -
  24.150 -reg [`LM32_WPC_C_RNG] wpc_c[0:watchpoints-1];   // Watchpoint enable
  24.151 -reg [`LM32_WORD_RNG] wp[0:watchpoints-1];       // Watchpoint address
  24.152 -wire [0:watchpoints]wp_match_n;               // Indicates if a h/w data watchpoint matched
  24.153 -
  24.154 -wire debug_csr_write_enable;                    // Debug CSR write enable (from either a wcsr instruction of external debugger)
  24.155 -wire [`LM32_WORD_RNG] debug_csr_write_data;     // Data to write to debug CSR
  24.156 -wire [`LM32_CSR_RNG] debug_csr;                 // Debug CSR to write to
  24.157 -
  24.158 -`ifdef LM32_SINGLE_STEP_ENABLED
  24.159 -// FIXME: Declaring this as a reg causes ModelSim 6.1.15b to crash, so use integer for now
  24.160 -//reg [`LM32_DEBUG_SS_STATE_RNG] state;           // State of single-step FSM
  24.161 -integer state;                                  // State of single-step FSM
  24.162 -`endif
  24.163 -
  24.164 -/////////////////////////////////////////////////////
  24.165 -// Functions
  24.166 -/////////////////////////////////////////////////////
  24.167 -
  24.168 -`include "lm32_functions.v"
  24.169 -
  24.170 -/////////////////////////////////////////////////////
  24.171 -// Combinational Logic
  24.172 -/////////////////////////////////////////////////////
  24.173 -
  24.174 -// Check for breakpoints
  24.175 -generate
  24.176 -    for (i = 0; i < breakpoints; i = i + 1)
  24.177 -    begin : bp_comb
  24.178 -assign bp_match_n[i] = ((bp_a[i] == pc_x) && (bp_e[i] == `TRUE));
  24.179 -    end
  24.180 -endgenerate
  24.181 -generate 
  24.182 -`ifdef LM32_SINGLE_STEP_ENABLED
  24.183 -    if (breakpoints > 0) 
  24.184 -assign bp_match = (|bp_match_n) || (state == `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT);
  24.185 -    else
  24.186 -assign bp_match = state == `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT;
  24.187 -`else
  24.188 -    if (breakpoints > 0) 
  24.189 -assign bp_match = |bp_match_n;
  24.190 -    else
  24.191 -assign bp_match = `FALSE;
  24.192 -`endif
  24.193 -endgenerate    
  24.194 -               
  24.195 -// Check for watchpoints
  24.196 -generate 
  24.197 -    for (i = 0; i < watchpoints; i = i + 1)
  24.198 -    begin : wp_comb
  24.199 -assign wp_match_n[i] = (wp[i] == load_store_address_x) && ((load_x & wpc_c[i][0]) | (store_x & wpc_c[i][1]));
  24.200 -    end               
  24.201 -endgenerate
  24.202 -generate
  24.203 -    if (watchpoints > 0) 
  24.204 -assign wp_match = |wp_match_n;                
  24.205 -    else
  24.206 -assign wp_match = `FALSE;
  24.207 -endgenerate
  24.208 -                
  24.209 -`ifdef CFG_HW_DEBUG_ENABLED                
  24.210 -// Multiplex between wcsr instruction writes and debugger writes to the debug CSRs
  24.211 -assign debug_csr_write_enable = (csr_write_enable_x == `TRUE) || (jtag_csr_write_enable == `TRUE);
  24.212 -assign debug_csr_write_data = jtag_csr_write_enable == `TRUE ? jtag_csr_write_data : csr_write_data;
  24.213 -assign debug_csr = jtag_csr_write_enable == `TRUE ? jtag_csr : csr_x;
  24.214 -`else
  24.215 -assign debug_csr_write_enable = csr_write_enable_x;
  24.216 -assign debug_csr_write_data = csr_write_data;
  24.217 -assign debug_csr = csr_x;
  24.218 -`endif
  24.219 -
  24.220 -/////////////////////////////////////////////////////
  24.221 -// Sequential Logic
  24.222 -/////////////////////////////////////////////////////
  24.223 -
  24.224 -// Breakpoint address and enable CSRs
  24.225 -generate
  24.226 -    for (i = 0; i < breakpoints; i = i + 1)
  24.227 -    begin : bp_seq
  24.228 -always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  24.229 -begin
  24.230 -    if (rst_i == `TRUE)
  24.231 -    begin
  24.232 -        bp_a[i] <= {`LM32_PC_WIDTH{1'bx}};
  24.233 -        bp_e[i] <= `FALSE;
  24.234 -    end
  24.235 -    else
  24.236 -    begin
  24.237 -        if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_BP0 + i))
  24.238 -        begin
  24.239 -            bp_a[i] <= debug_csr_write_data[`LM32_PC_RNG];
  24.240 -            bp_e[i] <= debug_csr_write_data[0];
  24.241 -        end
  24.242 -    end
  24.243 -end    
  24.244 -    end
  24.245 -endgenerate
  24.246 -
  24.247 -// Watchpoint address and control flags CSRs
  24.248 -generate
  24.249 -    for (i = 0; i < watchpoints; i = i + 1)
  24.250 -    begin : wp_seq
  24.251 -always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  24.252 -begin
  24.253 -    if (rst_i == `TRUE)
  24.254 -    begin
  24.255 -        wp[i] <= {`LM32_WORD_WIDTH{1'bx}};
  24.256 -        wpc_c[i] <= `LM32_WPC_C_DISABLED;
  24.257 -    end
  24.258 -    else
  24.259 -    begin
  24.260 -        if (debug_csr_write_enable == `TRUE)
  24.261 -        begin
  24.262 -            if (debug_csr == `LM32_CSR_DC)
  24.263 -                wpc_c[i] <= debug_csr_write_data[3+i*2:2+i*2];
  24.264 -            if (debug_csr == `LM32_CSR_WP0 + i)
  24.265 -                wp[i] <= debug_csr_write_data;
  24.266 -        end
  24.267 -    end  
  24.268 -end
  24.269 -    end
  24.270 -endgenerate
  24.271 -
  24.272 -// Remap exceptions control bit
  24.273 -always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  24.274 -begin
  24.275 -    if (rst_i == `TRUE)
  24.276 -        dc_re <= `FALSE;
  24.277 -    else
  24.278 -    begin
  24.279 -        if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_DC))
  24.280 -            dc_re <= debug_csr_write_data[1];
  24.281 -    end
  24.282 -end    
  24.283 -
  24.284 -`ifdef LM32_SINGLE_STEP_ENABLED
  24.285 -// Single-step control flag
  24.286 -always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  24.287 -begin
  24.288 -    if (rst_i == `TRUE)
  24.289 -    begin
  24.290 -        state <= `LM32_DEBUG_SS_STATE_IDLE;
  24.291 -        dc_ss <= `FALSE;
  24.292 -    end
  24.293 -    else
  24.294 -    begin
  24.295 -        if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_DC))
  24.296 -        begin
  24.297 -            dc_ss <= debug_csr_write_data[0];
  24.298 -            if (debug_csr_write_data[0] == `FALSE) 
  24.299 -                state <= `LM32_DEBUG_SS_STATE_IDLE;
  24.300 -            else 
  24.301 -                state <= `LM32_DEBUG_SS_STATE_WAIT_FOR_RET;
  24.302 -        end
  24.303 -        case (state)
  24.304 -        `LM32_DEBUG_SS_STATE_WAIT_FOR_RET:
  24.305 -        begin
  24.306 -            // Wait for eret or bret instruction to be executed
  24.307 -            if (   (   (eret_q_x == `TRUE)
  24.308 -                    || (bret_q_x == `TRUE)
  24.309 -                    )
  24.310 -                && (stall_x == `FALSE)
  24.311 -               )
  24.312 -                state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 
  24.313 -        end
  24.314 -        `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN:
  24.315 -        begin
  24.316 -            // Wait for an instruction to be executed
  24.317 -            if ((q_x == `TRUE) && (stall_x == `FALSE))
  24.318 -                state <= `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT;
  24.319 -        end
  24.320 -        `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT:
  24.321 -        begin
  24.322 -            // Wait for exception to be raised
  24.323 -`ifdef CFG_DCACHE_ENABLED
  24.324 -            if (dcache_refill_request == `TRUE)
  24.325 -                state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN;
  24.326 -            else 
  24.327 -`endif
  24.328 -                 if ((exception_x == `TRUE) && (q_x == `TRUE) && (stall_x == `FALSE))
  24.329 -            begin
  24.330 -                dc_ss <= `FALSE;
  24.331 -                state <= `LM32_DEBUG_SS_STATE_RESTART;
  24.332 -            end
  24.333 -        end
  24.334 -        `LM32_DEBUG_SS_STATE_RESTART:
  24.335 -        begin
  24.336 -            // Watch to see if stepped instruction is restarted due to a cache miss
  24.337 -`ifdef CFG_DCACHE_ENABLED
  24.338 -            if (dcache_refill_request == `TRUE)
  24.339 -                state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN;
  24.340 -            else 
  24.341 -`endif
  24.342 -                state <= `LM32_DEBUG_SS_STATE_IDLE;
  24.343 -        end
  24.344 -        endcase
  24.345 -    end
  24.346 -end
  24.347 -`endif
  24.348 -
  24.349 -endmodule
  24.350 -
  24.351 -`endif

    25.1 --- a/lm32_decoder.v	Sun Mar 06 21:17:31 2011 +0000
    25.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    25.3 @@ -1,583 +0,0 @@
    25.4 -// =============================================================================
    25.5 -//                           COPYRIGHT NOTICE
    25.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation
    25.7 -// ALL RIGHTS RESERVED
    25.8 -// This confidential and proprietary software may be used only as authorised by
    25.9 -// a licensing agreement from Lattice Semiconductor Corporation.
   25.10 -// The entire notice above must be reproduced on all authorized copies and
   25.11 -// copies may only be made to the extent permitted by a licensing agreement from
   25.12 -// Lattice Semiconductor Corporation.
   25.13 -//
   25.14 -// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
   25.15 -// 5555 NE Moore Court                            408-826-6000 (other locations)
   25.16 -// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
   25.17 -// U.S.A                                   email: techsupport@latticesemi.com
   25.18 -// =============================================================================/
   25.19 -//                         FILE DETAILS
   25.20 -// Project          : LatticeMico32
   25.21 -// File             : lm32_decoder.v
   25.22 -// Title            : Instruction decoder
   25.23 -// Dependencies     : lm32_include.v
   25.24 -// Version          : 6.1.17
   25.25 -//                  : Initial Release
   25.26 -// Version          : 7.0SP2, 3.0
   25.27 -//                  : No Change
   25.28 -// Version          : 3.1
   25.29 -//                  : Support for static branch prediction. Information about
   25.30 -//                  : branch type is generated and passed on to the predictor.
   25.31 -// Version          : 3.2
   25.32 -//                  : No change
   25.33 -// Version          : 3.3
   25.34 -//                  : Renamed port names that conflict with keywords reserved
   25.35 -//                  : in System-Verilog.
   25.36 -// =============================================================================
   25.37 -
   25.38 -`include "lm32_include.v"
   25.39 -
   25.40 -// Index of opcode field in an instruction
   25.41 -`define LM32_OPCODE_RNG         31:26
   25.42 -`define LM32_OP_RNG             30:26
   25.43 -
   25.44 -// Opcodes - Some are only listed as 5 bits as their MSB is a don't care
   25.45 -`define LM32_OPCODE_ADD         5'b01101
   25.46 -`define LM32_OPCODE_AND         5'b01000
   25.47 -`define LM32_OPCODE_ANDHI       6'b011000
   25.48 -`define LM32_OPCODE_B           6'b110000
   25.49 -`define LM32_OPCODE_BI          6'b111000
   25.50 -`define LM32_OPCODE_BE          6'b010001
   25.51 -`define LM32_OPCODE_BG          6'b010010
   25.52 -`define LM32_OPCODE_BGE         6'b010011
   25.53 -`define LM32_OPCODE_BGEU        6'b010100
   25.54 -`define LM32_OPCODE_BGU         6'b010101
   25.55 -`define LM32_OPCODE_BNE         6'b010111
   25.56 -`define LM32_OPCODE_CALL        6'b110110
   25.57 -`define LM32_OPCODE_CALLI       6'b111110
   25.58 -`define LM32_OPCODE_CMPE        5'b11001
   25.59 -`define LM32_OPCODE_CMPG        5'b11010
   25.60 -`define LM32_OPCODE_CMPGE       5'b11011
   25.61 -`define LM32_OPCODE_CMPGEU      5'b11100
   25.62 -`define LM32_OPCODE_CMPGU       5'b11101
   25.63 -`define LM32_OPCODE_CMPNE       5'b11111
   25.64 -`define LM32_OPCODE_DIVU        6'b100011
   25.65 -`define LM32_OPCODE_LB          6'b000100
   25.66 -`define LM32_OPCODE_LBU         6'b010000
   25.67 -`define LM32_OPCODE_LH          6'b000111
   25.68 -`define LM32_OPCODE_LHU         6'b001011
   25.69 -`define LM32_OPCODE_LW          6'b001010
   25.70 -`define LM32_OPCODE_MODU        6'b110001
   25.71 -`define LM32_OPCODE_MUL         5'b00010
   25.72 -`define LM32_OPCODE_NOR         5'b00001
   25.73 -`define LM32_OPCODE_OR          5'b01110
   25.74 -`define LM32_OPCODE_ORHI        6'b011110
   25.75 -`define LM32_OPCODE_RAISE       6'b101011
   25.76 -`define LM32_OPCODE_RCSR        6'b100100
   25.77 -`define LM32_OPCODE_SB          6'b001100
   25.78 -`define LM32_OPCODE_SEXTB       6'b101100
   25.79 -`define LM32_OPCODE_SEXTH       6'b110111
   25.80 -`define LM32_OPCODE_SH          6'b000011
   25.81 -`define LM32_OPCODE_SL          5'b01111
   25.82 -`define LM32_OPCODE_SR          5'b00101
   25.83 -`define LM32_OPCODE_SRU         5'b00000
   25.84 -`define LM32_OPCODE_SUB         6'b110010
   25.85 -`define LM32_OPCODE_SW          6'b010110
   25.86 -`define LM32_OPCODE_USER        6'b110011
   25.87 -`define LM32_OPCODE_WCSR        6'b110100
   25.88 -`define LM32_OPCODE_XNOR        5'b01001
   25.89 -`define LM32_OPCODE_XOR         5'b00110
   25.90 -
   25.91 -/////////////////////////////////////////////////////
   25.92 -// Module interface
   25.93 -/////////////////////////////////////////////////////
   25.94 -
   25.95 -module lm32_decoder (
   25.96 -    // ----- Inputs -------
   25.97 -    instruction,
   25.98 -    // ----- Outputs -------
   25.99 -    d_result_sel_0,
  25.100 -    d_result_sel_1,        
  25.101 -    x_result_sel_csr,
  25.102 -`ifdef LM32_MC_ARITHMETIC_ENABLED
  25.103 -    x_result_sel_mc_arith,
  25.104 -`endif    
  25.105 -`ifdef LM32_NO_BARREL_SHIFT    
  25.106 -    x_result_sel_shift,
  25.107 -`endif
  25.108 -`ifdef CFG_SIGN_EXTEND_ENABLED
  25.109 -    x_result_sel_sext,
  25.110 -`endif    
  25.111 -    x_result_sel_logic,
  25.112 -`ifdef CFG_USER_ENABLED
  25.113 -    x_result_sel_user,
  25.114 -`endif
  25.115 -    x_result_sel_add,
  25.116 -    m_result_sel_compare,
  25.117 -`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  25.118 -    m_result_sel_shift,  
  25.119 -`endif    
  25.120 -    w_result_sel_load,
  25.121 -`ifdef CFG_PL_MULTIPLY_ENABLED
  25.122 -    w_result_sel_mul,
  25.123 -`endif
  25.124 -    x_bypass_enable,
  25.125 -    m_bypass_enable,
  25.126 -    read_enable_0,
  25.127 -    read_idx_0,
  25.128 -    read_enable_1,
  25.129 -    read_idx_1,
  25.130 -    write_enable,
  25.131 -    write_idx,
  25.132 -    immediate,
  25.133 -    branch_offset,
  25.134 -    load,
  25.135 -    store,
  25.136 -    size,
  25.137 -    sign_extend,
  25.138 -    adder_op,
  25.139 -    logic_op,
  25.140 -`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  25.141 -    direction,
  25.142 -`endif
  25.143 -`ifdef CFG_MC_BARREL_SHIFT_ENABLED
  25.144 -    shift_left,
  25.145 -    shift_right,
  25.146 -`endif
  25.147 -`ifdef CFG_MC_MULTIPLY_ENABLED
  25.148 -    multiply,
  25.149 -`endif
  25.150 -`ifdef CFG_MC_DIVIDE_ENABLED
  25.151 -    divide,
  25.152 -    modulus,
  25.153 -`endif
  25.154 -    branch,
  25.155 -    branch_reg,
  25.156 -    condition,
  25.157 -    bi_conditional,
  25.158 -    bi_unconditional,
  25.159 -`ifdef CFG_DEBUG_ENABLED
  25.160 -    break_opcode,
  25.161 -`endif
  25.162 -    scall,
  25.163 -    eret,
  25.164 -`ifdef CFG_DEBUG_ENABLED
  25.165 -    bret,
  25.166 -`endif
  25.167 -`ifdef CFG_USER_ENABLED
  25.168 -    user_opcode,
  25.169 -`endif
  25.170 -    csr_write_enable
  25.171 -    );
  25.172 -
  25.173 -/////////////////////////////////////////////////////
  25.174 -// Inputs
  25.175 -/////////////////////////////////////////////////////
  25.176 -
  25.177 -input [`LM32_INSTRUCTION_RNG] instruction;       // Instruction to decode
  25.178 -
  25.179 -/////////////////////////////////////////////////////
  25.180 -// Outputs
  25.181 -/////////////////////////////////////////////////////
  25.182 -
  25.183 -output [`LM32_D_RESULT_SEL_0_RNG] d_result_sel_0;
  25.184 -reg    [`LM32_D_RESULT_SEL_0_RNG] d_result_sel_0;
  25.185 -output [`LM32_D_RESULT_SEL_1_RNG] d_result_sel_1;
  25.186 -reg    [`LM32_D_RESULT_SEL_1_RNG] d_result_sel_1;
  25.187 -output x_result_sel_csr;
  25.188 -reg    x_result_sel_csr;
  25.189 -`ifdef LM32_MC_ARITHMETIC_ENABLED
  25.190 -output x_result_sel_mc_arith;
  25.191 -reg    x_result_sel_mc_arith;
  25.192 -`endif
  25.193 -`ifdef LM32_NO_BARREL_SHIFT    
  25.194 -output x_result_sel_shift;
  25.195 -reg    x_result_sel_shift;
  25.196 -`endif
  25.197 -`ifdef CFG_SIGN_EXTEND_ENABLED
  25.198 -output x_result_sel_sext;
  25.199 -reg    x_result_sel_sext;
  25.200 -`endif
  25.201 -output x_result_sel_logic;
  25.202 -reg    x_result_sel_logic;
  25.203 -`ifdef CFG_USER_ENABLED
  25.204 -output x_result_sel_user;
  25.205 -reg    x_result_sel_user;
  25.206 -`endif
  25.207 -output x_result_sel_add;
  25.208 -reg    x_result_sel_add;
  25.209 -output m_result_sel_compare;
  25.210 -reg    m_result_sel_compare;
  25.211 -`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  25.212 -output m_result_sel_shift;
  25.213 -reg    m_result_sel_shift;
  25.214 -`endif
  25.215 -output w_result_sel_load;
  25.216 -reg    w_result_sel_load;
  25.217 -`ifdef CFG_PL_MULTIPLY_ENABLED
  25.218 -output w_result_sel_mul;
  25.219 -reg    w_result_sel_mul;
  25.220 -`endif
  25.221 -output x_bypass_enable;
  25.222 -wire   x_bypass_enable;
  25.223 -output m_bypass_enable;
  25.224 -wire   m_bypass_enable;
  25.225 -output read_enable_0;
  25.226 -wire   read_enable_0;
  25.227 -output [`LM32_REG_IDX_RNG] read_idx_0;
  25.228 -wire   [`LM32_REG_IDX_RNG] read_idx_0;
  25.229 -output read_enable_1;
  25.230 -wire   read_enable_1;
  25.231 -output [`LM32_REG_IDX_RNG] read_idx_1;
  25.232 -wire   [`LM32_REG_IDX_RNG] read_idx_1;
  25.233 -output write_enable;
  25.234 -wire   write_enable;
  25.235 -output [`LM32_REG_IDX_RNG] write_idx;
  25.236 -wire   [`LM32_REG_IDX_RNG] write_idx;
  25.237 -output [`LM32_WORD_RNG] immediate;
  25.238 -wire   [`LM32_WORD_RNG] immediate;
  25.239 -output [`LM32_PC_RNG] branch_offset;
  25.240 -wire   [`LM32_PC_RNG] branch_offset;
  25.241 -output load;
  25.242 -wire   load;
  25.243 -output store;
  25.244 -wire   store;
  25.245 -output [`LM32_SIZE_RNG] size;
  25.246 -wire   [`LM32_SIZE_RNG] size;
  25.247 -output sign_extend;
  25.248 -wire   sign_extend;
  25.249 -output adder_op;
  25.250 -wire   adder_op;
  25.251 -output [`LM32_LOGIC_OP_RNG] logic_op;
  25.252 -wire   [`LM32_LOGIC_OP_RNG] logic_op;
  25.253 -`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  25.254 -output direction;
  25.255 -wire   direction;
  25.256 -`endif
  25.257 -`ifdef CFG_MC_BARREL_SHIFT_ENABLED
  25.258 -output shift_left;
  25.259 -wire   shift_left;
  25.260 -output shift_right;
  25.261 -wire   shift_right;
  25.262 -`endif
  25.263 -`ifdef CFG_MC_MULTIPLY_ENABLED
  25.264 -output multiply;
  25.265 -wire   multiply;
  25.266 -`endif
  25.267 -`ifdef CFG_MC_DIVIDE_ENABLED
  25.268 -output divide;
  25.269 -wire   divide;
  25.270 -output modulus;
  25.271 -wire   modulus;
  25.272 -`endif
  25.273 -output branch;
  25.274 -wire   branch;
  25.275 -output branch_reg;
  25.276 -wire   branch_reg;
  25.277 -output [`LM32_CONDITION_RNG] condition;
  25.278 -wire   [`LM32_CONDITION_RNG] condition;
  25.279 -output bi_conditional;
  25.280 -wire bi_conditional;
  25.281 -output bi_unconditional;
  25.282 -wire bi_unconditional;
  25.283 -`ifdef CFG_DEBUG_ENABLED
  25.284 -output break_opcode;
  25.285 -wire   break_opcode;
  25.286 -`endif
  25.287 -output scall;
  25.288 -wire   scall;
  25.289 -output eret;
  25.290 -wire   eret;
  25.291 -`ifdef CFG_DEBUG_ENABLED
  25.292 -output bret;
  25.293 -wire   bret;
  25.294 -`endif
  25.295 -`ifdef CFG_USER_ENABLED
  25.296 -output [`LM32_USER_OPCODE_RNG] user_opcode;
  25.297 -wire   [`LM32_USER_OPCODE_RNG] user_opcode;
  25.298 -`endif
  25.299 -output csr_write_enable;
  25.300 -wire   csr_write_enable;
  25.301 -
  25.302 -/////////////////////////////////////////////////////
  25.303 -// Internal nets and registers 
  25.304 -/////////////////////////////////////////////////////
  25.305 -
  25.306 -wire [`LM32_WORD_RNG] extended_immediate;       // Zero or sign extended immediate
  25.307 -wire [`LM32_WORD_RNG] high_immediate;           // Immediate as high 16 bits
  25.308 -wire [`LM32_WORD_RNG] call_immediate;           // Call immediate
  25.309 -wire [`LM32_WORD_RNG] branch_immediate;         // Conditional branch immediate
  25.310 -wire sign_extend_immediate;                     // Whether the immediate should be sign extended (`TRUE) or zero extended (`FALSE)
  25.311 -wire select_high_immediate;                     // Whether to select the high immediate  
  25.312 -wire select_call_immediate;                     // Whether to select the call immediate 
  25.313 -
  25.314 -/////////////////////////////////////////////////////
  25.315 -// Functions
  25.316 -/////////////////////////////////////////////////////
  25.317 -
  25.318 -`include "lm32_functions.v"
  25.319 -
  25.320 -/////////////////////////////////////////////////////
  25.321 -// Combinational logic
  25.322 -/////////////////////////////////////////////////////
  25.323 -
  25.324 -// Determine opcode
  25.325 -assign op_add    = instruction[`LM32_OP_RNG] == `LM32_OPCODE_ADD;
  25.326 -assign op_and    = instruction[`LM32_OP_RNG] == `LM32_OPCODE_AND;
  25.327 -assign op_andhi  = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_ANDHI;
  25.328 -assign op_b      = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_B;
  25.329 -assign op_bi     = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BI;
  25.330 -assign op_be     = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BE;
  25.331 -assign op_bg     = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BG;
  25.332 -assign op_bge    = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BGE;
  25.333 -assign op_bgeu   = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BGEU;
  25.334 -assign op_bgu    = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BGU;
  25.335 -assign op_bne    = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BNE;
  25.336 -assign op_call   = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_CALL;
  25.337 -assign op_calli  = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_CALLI;
  25.338 -assign op_cmpe   = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPE;
  25.339 -assign op_cmpg   = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPG;
  25.340 -assign op_cmpge  = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPGE;
  25.341 -assign op_cmpgeu = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPGEU;
  25.342 -assign op_cmpgu  = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPGU;
  25.343 -assign op_cmpne  = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPNE;
  25.344 -`ifdef CFG_MC_DIVIDE_ENABLED
  25.345 -assign op_divu   = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_DIVU;
  25.346 -`endif
  25.347 -assign op_lb     = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LB;
  25.348 -assign op_lbu    = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LBU;
  25.349 -assign op_lh     = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LH;
  25.350 -assign op_lhu    = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LHU;
  25.351 -assign op_lw     = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LW;
  25.352 -`ifdef CFG_MC_DIVIDE_ENABLED
  25.353 -assign op_modu   = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_MODU;
  25.354 -`endif
  25.355 -`ifdef LM32_MULTIPLY_ENABLED
  25.356 -assign op_mul    = instruction[`LM32_OP_RNG] == `LM32_OPCODE_MUL;
  25.357 -`endif
  25.358 -assign op_nor    = instruction[`LM32_OP_RNG] == `LM32_OPCODE_NOR;
  25.359 -assign op_or     = instruction[`LM32_OP_RNG] == `LM32_OPCODE_OR;
  25.360 -assign op_orhi   = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_ORHI;
  25.361 -assign op_raise  = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_RAISE;
  25.362 -assign op_rcsr   = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_RCSR;
  25.363 -assign op_sb     = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SB;
  25.364 -`ifdef CFG_SIGN_EXTEND_ENABLED
  25.365 -assign op_sextb  = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SEXTB;
  25.366 -assign op_sexth  = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SEXTH;
  25.367 -`endif
  25.368 -assign op_sh     = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SH;
  25.369 -`ifdef LM32_BARREL_SHIFT_ENABLED
  25.370 -assign op_sl     = instruction[`LM32_OP_RNG] == `LM32_OPCODE_SL;      
  25.371 -`endif
  25.372 -assign op_sr     = instruction[`LM32_OP_RNG] == `LM32_OPCODE_SR;
  25.373 -assign op_sru    = instruction[`LM32_OP_RNG] == `LM32_OPCODE_SRU;
  25.374 -assign op_sub    = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SUB;
  25.375 -assign op_sw     = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SW;
  25.376 -assign op_user   = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_USER;
  25.377 -assign op_wcsr   = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_WCSR;
  25.378 -assign op_xnor   = instruction[`LM32_OP_RNG] == `LM32_OPCODE_XNOR;
  25.379 -assign op_xor    = instruction[`LM32_OP_RNG] == `LM32_OPCODE_XOR;
  25.380 -
  25.381 -// Group opcodes by function
  25.382 -assign arith = op_add | op_sub;
  25.383 -assign logical = op_and | op_andhi | op_nor | op_or | op_orhi | op_xor | op_xnor;
  25.384 -assign cmp = op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne;
  25.385 -assign bi_conditional = op_be | op_bg | op_bge | op_bgeu  | op_bgu | op_bne;
  25.386 -assign bi_unconditional = op_bi;
  25.387 -assign bra = op_b | bi_unconditional | bi_conditional;
  25.388 -assign call = op_call | op_calli;
  25.389 -`ifdef LM32_BARREL_SHIFT_ENABLED
  25.390 -assign shift = op_sl | op_sr | op_sru;
  25.391 -`endif
  25.392 -`ifdef LM32_NO_BARREL_SHIFT
  25.393 -assign shift = op_sr | op_sru;
  25.394 -`endif
  25.395 -`ifdef CFG_MC_BARREL_SHIFT_ENABLED
  25.396 -assign shift_left = op_sl;
  25.397 -assign shift_right = op_sr | op_sru;
  25.398 -`endif
  25.399 -`ifdef CFG_SIGN_EXTEND_ENABLED
  25.400 -assign sext = op_sextb | op_sexth;
  25.401 -`endif
  25.402 -`ifdef LM32_MULTIPLY_ENABLED
  25.403 -assign multiply = op_mul;
  25.404 -`endif
  25.405 -`ifdef CFG_MC_DIVIDE_ENABLED
  25.406 -assign divide = op_divu; 
  25.407 -assign modulus = op_modu;
  25.408 -`endif
  25.409 -assign load = op_lb | op_lbu | op_lh | op_lhu | op_lw;
  25.410 -assign store = op_sb | op_sh | op_sw;
  25.411 -
  25.412 -// Select pipeline multiplexor controls
  25.413 -always @(*)
  25.414 -begin
  25.415 -    // D stage
  25.416 -    if (call) 
  25.417 -        d_result_sel_0 = `LM32_D_RESULT_SEL_0_NEXT_PC;
  25.418 -    else 
  25.419 -        d_result_sel_0 = `LM32_D_RESULT_SEL_0_REG_0;
  25.420 -    if (call) 
  25.421 -        d_result_sel_1 = `LM32_D_RESULT_SEL_1_ZERO;         
  25.422 -    else if ((instruction[31] == 1'b0) && !bra) 
  25.423 -        d_result_sel_1 = `LM32_D_RESULT_SEL_1_IMMEDIATE;
  25.424 -    else
  25.425 -        d_result_sel_1 = `LM32_D_RESULT_SEL_1_REG_1; 
  25.426 -    // X stage
  25.427 -    x_result_sel_csr = `FALSE;
  25.428 -`ifdef LM32_MC_ARITHMETIC_ENABLED
  25.429 -    x_result_sel_mc_arith = `FALSE;
  25.430 -`endif
  25.431 -`ifdef LM32_NO_BARREL_SHIFT
  25.432 -    x_result_sel_shift = `FALSE;
  25.433 -`endif
  25.434 -`ifdef CFG_SIGN_EXTEND_ENABLED
  25.435 -    x_result_sel_sext = `FALSE;
  25.436 -`endif
  25.437 -    x_result_sel_logic = `FALSE;
  25.438 -`ifdef CFG_USER_ENABLED        
  25.439 -    x_result_sel_user = `FALSE;
  25.440 -`endif
  25.441 -    x_result_sel_add = `FALSE;
  25.442 -    if (op_rcsr)
  25.443 -        x_result_sel_csr = `TRUE;
  25.444 -`ifdef LM32_MC_ARITHMETIC_ENABLED    
  25.445 -`ifdef CFG_MC_BARREL_SHIFT_ENABLED
  25.446 -    else if (shift_left | shift_right) 
  25.447 -        x_result_sel_mc_arith = `TRUE;
  25.448 -`endif
  25.449 -`ifdef CFG_MC_DIVIDE_ENABLED
  25.450 -    else if (divide | modulus)
  25.451 -        x_result_sel_mc_arith = `TRUE;        
  25.452 -`endif
  25.453 -`ifdef CFG_MC_MULTIPLY_ENABLED
  25.454 -    else if (multiply)
  25.455 -        x_result_sel_mc_arith = `TRUE;            
  25.456 -`endif
  25.457 -`endif
  25.458 -`ifdef LM32_NO_BARREL_SHIFT
  25.459 -    else if (shift)
  25.460 -        x_result_sel_shift = `TRUE;        
  25.461 -`endif
  25.462 -`ifdef CFG_SIGN_EXTEND_ENABLED
  25.463 -    else if (sext)
  25.464 -        x_result_sel_sext = `TRUE;
  25.465 -`endif        
  25.466 -    else if (logical) 
  25.467 -        x_result_sel_logic = `TRUE;
  25.468 -`ifdef CFG_USER_ENABLED        
  25.469 -    else if (op_user)
  25.470 -        x_result_sel_user = `TRUE;
  25.471 -`endif
  25.472 -    else 
  25.473 -        x_result_sel_add = `TRUE;        
  25.474 -    
  25.475 -    // M stage
  25.476 -
  25.477 -    m_result_sel_compare = cmp;
  25.478 -`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  25.479 -    m_result_sel_shift = shift;
  25.480 -`endif
  25.481 -
  25.482 -    // W stage
  25.483 -    w_result_sel_load = load;
  25.484 -`ifdef CFG_PL_MULTIPLY_ENABLED
  25.485 -    w_result_sel_mul = op_mul; 
  25.486 -`endif
  25.487 -end
  25.488 -
  25.489 -// Set if result is valid at end of X stage
  25.490 -assign x_bypass_enable =  arith 
  25.491 -                        | logical
  25.492 -`ifdef CFG_MC_BARREL_SHIFT_ENABLED
  25.493 -                        | shift_left
  25.494 -                        | shift_right
  25.495 -`endif                        
  25.496 -`ifdef CFG_MC_MULTIPLY_ENABLED
  25.497 -                        | multiply
  25.498 -`endif
  25.499 -`ifdef CFG_MC_DIVIDE_ENABLED
  25.500 -                        | divide
  25.501 -                        | modulus
  25.502 -`endif
  25.503 -`ifdef LM32_NO_BARREL_SHIFT
  25.504 -                        | shift
  25.505 -`endif                  
  25.506 -`ifdef CFG_SIGN_EXTEND_ENABLED
  25.507 -                        | sext 
  25.508 -`endif                        
  25.509 -`ifdef CFG_USER_ENABLED
  25.510 -                        | op_user
  25.511 -`endif
  25.512 -                        | op_rcsr
  25.513 -                        ;
  25.514 -// Set if result is valid at end of M stage                        
  25.515 -assign m_bypass_enable = x_bypass_enable 
  25.516 -`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  25.517 -                        | shift
  25.518 -`endif
  25.519 -                        | cmp
  25.520 -                        ;
  25.521 -// Register file read port 0                        
  25.522 -assign read_enable_0 = ~(op_bi | op_calli);
  25.523 -assign read_idx_0 = instruction[25:21];
  25.524 -// Register file read port 1 
  25.525 -assign read_enable_1 = ~(op_bi | op_calli | load);
  25.526 -assign read_idx_1 = instruction[20:16];
  25.527 -// Register file write port
  25.528 -assign write_enable = ~(bra | op_raise | store | op_wcsr);
  25.529 -assign write_idx = call
  25.530 -                    ? 5'd29
  25.531 -                    : instruction[31] == 1'b0 
  25.532 -                        ? instruction[20:16] 
  25.533 -                        : instruction[15:11];
  25.534 -                        
  25.535 -// Size of load/stores                        
  25.536 -assign size = instruction[27:26];
  25.537 -// Whether to sign or zero extend
  25.538 -assign sign_extend = instruction[28];                      
  25.539 -// Set adder_op to 1 to perform a subtraction
  25.540 -assign adder_op = op_sub | op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne | bra;
  25.541 -// Logic operation (and, or, etc)
  25.542 -assign logic_op = instruction[29:26];
  25.543 -`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  25.544 -// Shift direction
  25.545 -assign direction = instruction[29];
  25.546 -`endif
  25.547 -// Control flow microcodes
  25.548 -assign branch = bra | call;
  25.549 -assign branch_reg = op_call | op_b;
  25.550 -assign condition = instruction[28:26];      
  25.551 -`ifdef CFG_DEBUG_ENABLED
  25.552 -assign break_opcode = op_raise & ~instruction[2];
  25.553 -`endif
  25.554 -assign scall = op_raise & instruction[2];
  25.555 -assign eret = op_b & (instruction[25:21] == 5'd30);
  25.556 -`ifdef CFG_DEBUG_ENABLED
  25.557 -assign bret = op_b & (instruction[25:21] == 5'd31);
  25.558 -`endif
  25.559 -`ifdef CFG_USER_ENABLED
  25.560 -// Extract user opcode
  25.561 -assign user_opcode = instruction[10:0];
  25.562 -`endif
  25.563 -// CSR read/write
  25.564 -assign csr_write_enable = op_wcsr;
  25.565 -
  25.566 -// Extract immediate from instruction
  25.567 -
  25.568 -assign sign_extend_immediate = ~(op_and | op_cmpgeu | op_cmpgu | op_nor | op_or | op_xnor | op_xor);
  25.569 -assign select_high_immediate = op_andhi | op_orhi;
  25.570 -assign select_call_immediate = instruction[31];
  25.571 -
  25.572 -assign high_immediate = {instruction[15:0], 16'h0000};
  25.573 -assign extended_immediate = {{16{sign_extend_immediate & instruction[15]}}, instruction[15:0]};
  25.574 -assign call_immediate = {{6{instruction[25]}}, instruction[25:0]};
  25.575 -assign branch_immediate = {{16{instruction[15]}}, instruction[15:0]};
  25.576 -
  25.577 -assign immediate = select_high_immediate == `TRUE 
  25.578 -                        ? high_immediate 
  25.579 -                        : extended_immediate;
  25.580 -   
  25.581 -assign branch_offset = select_call_immediate == `TRUE   
  25.582 -                        ? call_immediate
  25.583 -                        : branch_immediate;
  25.584 -    
  25.585 -endmodule 
  25.586 -

    26.1 --- a/lm32_dp_ram.v	Sun Mar 06 21:17:31 2011 +0000
    26.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    26.3 @@ -1,35 +0,0 @@
    26.4 -module lm32_dp_ram(
    26.5 -	clk_i,
    26.6 -	rst_i,
    26.7 -	we_i,
    26.8 -	waddr_i,
    26.9 -	wdata_i,
   26.10 -	raddr_i,
   26.11 -	rdata_o);
   26.12 -
   26.13 -parameter addr_width = 32;
   26.14 -parameter addr_depth = 1024;
   26.15 -parameter data_width = 8;
   26.16 -
   26.17 -input clk_i;
   26.18 -input rst_i;
   26.19 -input we_i;
   26.20 -input [addr_width-1:0] waddr_i;
   26.21 -input [data_width-1:0] wdata_i;
   26.22 -input [addr_width-1:0] raddr_i;
   26.23 -output [data_width-1:0] rdata_o;
   26.24 -
   26.25 -reg [data_width-1:0] ram[addr_depth-1:0];
   26.26 -
   26.27 -reg [addr_width-1:0] raddr_r;
   26.28 -assign rdata_o = ram[raddr_r];
   26.29 -
   26.30 -always @ (posedge clk_i)
   26.31 -begin
   26.32 -	if (we_i)
   26.33 -		ram[waddr_i] <= wdata_i;
   26.34 -	raddr_r <= raddr_i;
   26.35 -end
   26.36 -
   26.37 -endmodule
   26.38 -

    27.1 --- a/lm32_functions.v	Sun Mar 06 21:17:31 2011 +0000
    27.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    27.3 @@ -1,49 +0,0 @@
    27.4 -// =============================================================================
    27.5 -//                           COPYRIGHT NOTICE
    27.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation
    27.7 -// ALL RIGHTS RESERVED
    27.8 -// This confidential and proprietary software may be used only as authorised by
    27.9 -// a licensing agreement from Lattice Semiconductor Corporation.
   27.10 -// The entire notice above must be reproduced on all authorized copies and
   27.11 -// copies may only be made to the extent permitted by a licensing agreement from
   27.12 -// Lattice Semiconductor Corporation.
   27.13 -//
   27.14 -// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
   27.15 -// 5555 NE Moore Court                            408-826-6000 (other locations)
   27.16 -// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
   27.17 -// U.S.A                                   email: techsupport@latticesemi.com
   27.18 -// =============================================================================/
   27.19 -//                         FILE DETAILS
   27.20 -// Project      : LatticeMico32
   27.21 -// File         : lm32_functions.v
   27.22 -// Title        : Common functions
   27.23 -// Version      : 6.1.17
   27.24 -//              : Initial Release
   27.25 -// Version      : 7.0SP2, 3.0
   27.26 -//              : No Change
   27.27 -// Version      : 3.5
   27.28 -//              : Added function to generate log-of-two that rounds-up to
   27.29 -//              : power-of-two
   27.30 -// =============================================================================
   27.31 -					  
   27.32 -function integer clogb2;
   27.33 -input [31:0] value;
   27.34 -begin
   27.35 -   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
   27.36 -        value = value >> 1;
   27.37 -end
   27.38 -endfunction 
   27.39 -
   27.40 -function integer clogb2_v1;
   27.41 -input [31:0] value;
   27.42 -reg   [31:0] i;
   27.43 -reg   [31:0] temp;
   27.44 -begin
   27.45 -   temp = 0;
   27.46 -   i    = 0;
   27.47 -   for (i = 0; temp < value; i = i + 1)  
   27.48 -	temp = 1<<i;
   27.49 -   clogb2_v1 = i-1;
   27.50 -end
   27.51 -endfunction
   27.52 -

    28.1 --- a/lm32_icache.v	Sun Mar 06 21:17:31 2011 +0000
    28.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    28.3 @@ -1,494 +0,0 @@
    28.4 -// =============================================================================
    28.5 -//                           COPYRIGHT NOTICE
    28.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation
    28.7 -// ALL RIGHTS RESERVED
    28.8 -// This confidential and proprietary software may be used only as authorised by
    28.9 -// a licensing agreement from Lattice Semiconductor Corporation.
   28.10 -// The entire notice above must be reproduced on all authorized copies and
   28.11 -// copies may only be made to the extent permitted by a licensing agreement from
   28.12 -// Lattice Semiconductor Corporation.
   28.13 -//
   28.14 -// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
   28.15 -// 5555 NE Moore Court                            408-826-6000 (other locations)
   28.16 -// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
   28.17 -// U.S.A                                   email: techsupport@latticesemi.com
   28.18 -// =============================================================================/
   28.19 -//                         FILE DETAILS
   28.20 -// Project          : LatticeMico32
   28.21 -// File             : lm32_icache.v
   28.22 -// Title            : Instruction cache
   28.23 -// Dependencies     : lm32_include.v
   28.24 -// 
   28.25 -// Version 3.5
   28.26 -// 1. Bug Fix: Instruction cache flushes issued from Instruction Inline Memory
   28.27 -//    cause segmentation fault due to incorrect fetches.
   28.28 -//
   28.29 -// Version 3.1
   28.30 -// 1. Feature: Support for user-selected resource usage when implementing
   28.31 -//    cache memory. Additional parameters must be defined when invoking module
   28.32 -//    lm32_ram. Instruction cache miss mechanism is dependent on branch
   28.33 -//    prediction being performed in D stage of pipeline.
   28.34 -//
   28.35 -// Version 7.0SP2, 3.0
   28.36 -// No change
   28.37 -// =============================================================================
   28.38 -					  
   28.39 -`include "lm32_include.v"
   28.40 -
   28.41 -`ifdef CFG_ICACHE_ENABLED
   28.42 -
   28.43 -`define LM32_IC_ADDR_OFFSET_RNG          addr_offset_msb:addr_offset_lsb
   28.44 -`define LM32_IC_ADDR_SET_RNG             addr_set_msb:addr_set_lsb
   28.45 -`define LM32_IC_ADDR_TAG_RNG             addr_tag_msb:addr_tag_lsb
   28.46 -`define LM32_IC_ADDR_IDX_RNG             addr_set_msb:addr_offset_lsb
   28.47 -
   28.48 -`define LM32_IC_TMEM_ADDR_WIDTH          addr_set_width
   28.49 -`define LM32_IC_TMEM_ADDR_RNG            (`LM32_IC_TMEM_ADDR_WIDTH-1):0
   28.50 -`define LM32_IC_DMEM_ADDR_WIDTH          (addr_offset_width+addr_set_width)
   28.51 -`define LM32_IC_DMEM_ADDR_RNG            (`LM32_IC_DMEM_ADDR_WIDTH-1):0
   28.52 -
   28.53 -`define LM32_IC_TAGS_WIDTH               (addr_tag_width+1)
   28.54 -`define LM32_IC_TAGS_RNG                 (`LM32_IC_TAGS_WIDTH-1):0
   28.55 -`define LM32_IC_TAGS_TAG_RNG             (`LM32_IC_TAGS_WIDTH-1):1
   28.56 -`define LM32_IC_TAGS_VALID_RNG           0
   28.57 -
   28.58 -`define LM32_IC_STATE_RNG                3:0
   28.59 -`define LM32_IC_STATE_FLUSH_INIT         4'b0001
   28.60 -`define LM32_IC_STATE_FLUSH              4'b0010
   28.61 -`define LM32_IC_STATE_CHECK              4'b0100
   28.62 -`define LM32_IC_STATE_REFILL             4'b1000
   28.63 -
   28.64 -/////////////////////////////////////////////////////
   28.65 -// Module interface
   28.66 -/////////////////////////////////////////////////////
   28.67 -
   28.68 -module lm32_icache ( 
   28.69 -    // ----- Inputs -----
   28.70 -    clk_i,
   28.71 -    rst_i,    
   28.72 -    stall_a,
   28.73 -    stall_f,
   28.74 -    address_a,
   28.75 -    address_f,
   28.76 -    read_enable_f,
   28.77 -    refill_ready,
   28.78 -    refill_data,
   28.79 -    iflush,
   28.80 -`ifdef CFG_IROM_ENABLED
   28.81 -    select_f,
   28.82 -`endif
   28.83 -    valid_d,
   28.84 -    branch_predict_taken_d,
   28.85 -    // ----- Outputs -----
   28.86 -    stall_request,
   28.87 -    restart_request,
   28.88 -    refill_request,
   28.89 -    refill_address,
   28.90 -    refilling,
   28.91 -    inst
   28.92 -    );
   28.93 -
   28.94 -/////////////////////////////////////////////////////
   28.95 -// Parameters
   28.96 -/////////////////////////////////////////////////////
   28.97 -
   28.98 -parameter associativity = 1;                            // Associativity of the cache (Number of ways)
   28.99 -parameter sets = 512;                                   // Number of sets
  28.100 -parameter bytes_per_line = 16;                          // Number of bytes per cache line
  28.101 -parameter base_address = 0;                             // Base address of cachable memory
  28.102 -parameter limit = 0;                                    // Limit (highest address) of cachable memory
  28.103 -
  28.104 -localparam addr_offset_width = clogb2(bytes_per_line)-1-2;
  28.105 -localparam addr_set_width = clogb2(sets)-1;
  28.106 -localparam addr_offset_lsb = 2;
  28.107 -localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
  28.108 -localparam addr_set_lsb = (addr_offset_msb+1);
  28.109 -localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
  28.110 -localparam addr_tag_lsb = (addr_set_msb+1);
  28.111 -localparam addr_tag_msb = clogb2(`CFG_ICACHE_LIMIT-`CFG_ICACHE_BASE_ADDRESS)-1;
  28.112 -localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);
  28.113 -
  28.114 -/////////////////////////////////////////////////////
  28.115 -// Inputs
  28.116 -/////////////////////////////////////////////////////
  28.117 -
  28.118 -input clk_i;                                        // Clock 
  28.119 -input rst_i;                                        // Reset
  28.120 -
  28.121 -input stall_a;                                      // Stall instruction in A stage
  28.122 -input stall_f;                                      // Stall instruction in F stage
  28.123 -
  28.124 -input valid_d;                                      // Valid instruction in D stage
  28.125 -input branch_predict_taken_d;                       // Instruction in D stage is a branch and is predicted taken
  28.126 -   
  28.127 -input [`LM32_PC_RNG] address_a;                     // Address of instruction in A stage
  28.128 -input [`LM32_PC_RNG] address_f;                     // Address of instruction in F stage
  28.129 -input read_enable_f;                                // Indicates if cache access is valid
  28.130 -
  28.131 -input refill_ready;                                 // Next word of refill data is ready
  28.132 -input [`LM32_INSTRUCTION_RNG] refill_data;          // Data to refill the cache with
  28.133 -
  28.134 -input iflush;                                       // Flush the cache
  28.135 -`ifdef CFG_IROM_ENABLED
  28.136 -input select_f;                                     // Instruction in F stage is mapped through instruction cache
  28.137 -`endif
  28.138 -   
  28.139 -/////////////////////////////////////////////////////
  28.140 -// Outputs
  28.141 -/////////////////////////////////////////////////////
  28.142 -
  28.143 -output stall_request;                               // Request to stall the pipeline
  28.144 -wire   stall_request;
  28.145 -output restart_request;                             // Request to restart instruction that caused the cache miss
  28.146 -reg    restart_request;
  28.147 -output refill_request;                              // Request to refill a cache line
  28.148 -wire   refill_request;
  28.149 -output [`LM32_PC_RNG] refill_address;               // Base address of cache refill
  28.150 -reg    [`LM32_PC_RNG] refill_address;               
  28.151 -output refilling;                                   // Indicates the instruction cache is currently refilling
  28.152 -reg    refilling;
  28.153 -output [`LM32_INSTRUCTION_RNG] inst;                // Instruction read from cache
  28.154 -wire   [`LM32_INSTRUCTION_RNG] inst;
  28.155 -
  28.156 -/////////////////////////////////////////////////////
  28.157 -// Internal nets and registers 
  28.158 -/////////////////////////////////////////////////////
  28.159 -
  28.160 -wire enable;
  28.161 -wire [0:associativity-1] way_mem_we;
  28.162 -wire [`LM32_INSTRUCTION_RNG] way_data[0:associativity-1];
  28.163 -wire [`LM32_IC_TAGS_TAG_RNG] way_tag[0:associativity-1];
  28.164 -wire [0:associativity-1] way_valid;
  28.165 -wire [0:associativity-1] way_match;
  28.166 -wire miss;
  28.167 -
  28.168 -wire [`LM32_IC_TMEM_ADDR_RNG] tmem_read_address;
  28.169 -wire [`LM32_IC_TMEM_ADDR_RNG] tmem_write_address;
  28.170 -wire [`LM32_IC_DMEM_ADDR_RNG] dmem_read_address;
  28.171 -wire [`LM32_IC_DMEM_ADDR_RNG] dmem_write_address;
  28.172 -wire [`LM32_IC_TAGS_RNG] tmem_write_data;
  28.173 -
  28.174 -reg [`LM32_IC_STATE_RNG] state;
  28.175 -wire flushing;
  28.176 -wire check;
  28.177 -wire refill;
  28.178 -
  28.179 -reg [associativity-1:0] refill_way_select;
  28.180 -reg [`LM32_IC_ADDR_OFFSET_RNG] refill_offset;
  28.181 -wire last_refill;
  28.182 -reg [`LM32_IC_TMEM_ADDR_RNG] flush_set;
  28.183 -
  28.184 -genvar i;
  28.185 -
  28.186 -/////////////////////////////////////////////////////
  28.187 -// Functions
  28.188 -/////////////////////////////////////////////////////
  28.189 -
  28.190 -`include "lm32_functions.v"
  28.191 -
  28.192 -/////////////////////////////////////////////////////
  28.193 -// Instantiations
  28.194 -/////////////////////////////////////////////////////
  28.195 -
  28.196 -   generate
  28.197 -      for (i = 0; i < associativity; i = i + 1)
  28.198 -	begin : memories
  28.199 -	   
  28.200 -	   lm32_ram 
  28.201 -	     #(
  28.202 -	       // ----- Parameters -------
  28.203 -	       .data_width                 (32),
  28.204 -	       .address_width              (`LM32_IC_DMEM_ADDR_WIDTH)
  28.205 -`ifdef PLATFORM_LATTICE
  28.206 -			,
  28.207 - `ifdef CFG_ICACHE_DAT_USE_DP_TRUE
  28.208 -	       .RAM_IMPLEMENTATION         ("EBR"),
  28.209 -	       .RAM_TYPE                   ("RAM_DP_TRUE")
  28.210 - `else
  28.211 -  `ifdef CFG_ICACHE_DAT_USE_DP
  28.212 -	       .RAM_IMPLEMENTATION         ("EBR"),
  28.213 -	       .RAM_TYPE                   ("RAM_DP")
  28.214 -  `else
  28.215 -   `ifdef CFG_ICACHE_DAT_USE_SLICE
  28.216 -	       .RAM_IMPLEMENTATION         ("SLICE")
  28.217 -   `else
  28.218 -	       .RAM_IMPLEMENTATION         ("AUTO")
  28.219 -   `endif
  28.220 -  `endif
  28.221 - `endif
  28.222 -`endif
  28.223 -	       ) 
  28.224 -	   way_0_data_ram 
  28.225 -	     (
  28.226 -	      // ----- Inputs -------
  28.227 -	      .read_clk                   (clk_i),
  28.228 -	      .write_clk                  (clk_i),
  28.229 -	      .reset                      (rst_i),
  28.230 -	      .read_address               (dmem_read_address),
  28.231 -	      .enable_read                (enable),
  28.232 -	      .write_address              (dmem_write_address),
  28.233 -	      .enable_write               (`TRUE),
  28.234 -	      .write_enable               (way_mem_we[i]),
  28.235 -	      .write_data                 (refill_data),    
  28.236 -	      // ----- Outputs -------
  28.237 -	      .read_data                  (way_data[i])
  28.238 -	      );
  28.239 -	   
  28.240 -	   lm32_ram 
  28.241 -	     #(
  28.242 -	       // ----- Parameters -------
  28.243 -	       .data_width                 (`LM32_IC_TAGS_WIDTH),
  28.244 -	       .address_width              (`LM32_IC_TMEM_ADDR_WIDTH)
  28.245 -`ifdef PLATFORM_LATTICE
  28.246 -			,
  28.247 - `ifdef CFG_ICACHE_DAT_USE_DP_TRUE
  28.248 -	       .RAM_IMPLEMENTATION         ("EBR"),
  28.249 -	       .RAM_TYPE                   ("RAM_DP_TRUE")
  28.250 - `else
  28.251 -  `ifdef CFG_ICACHE_DAT_USE_DP
  28.252 -	       .RAM_IMPLEMENTATION         ("EBR"),
  28.253 -	       .RAM_TYPE                   ("RAM_DP")
  28.254 -  `else
  28.255 -   `ifdef CFG_ICACHE_DAT_USE_SLICE
  28.256 -	       .RAM_IMPLEMENTATION         ("SLICE")
  28.257 -   `else
  28.258 -	       .RAM_IMPLEMENTATION         ("AUTO")
  28.259 -   `endif
  28.260 -  `endif
  28.261 - `endif
  28.262 -`endif
  28.263 -	       ) 
  28.264 -	   way_0_tag_ram 
  28.265 -	     (
  28.266 -	      // ----- Inputs -------
  28.267 -	      .read_clk                   (clk_i),
  28.268 -	      .write_clk                  (clk_i),
  28.269 -	      .reset                      (rst_i),
  28.270 -	      .read_address               (tmem_read_address),
  28.271 -	      .enable_read                (enable),
  28.272 -	      .write_address              (tmem_write_address),
  28.273 -	      .enable_write               (`TRUE),
  28.274 -	      .write_enable               (way_mem_we[i] | flushing),
  28.275 -	      .write_data                 (tmem_write_data),
  28.276 -	      // ----- Outputs -------
  28.277 -	      .read_data                  ({way_tag[i], way_valid[i]})
  28.278 -	      );
  28.279 -	   
  28.280 -	end
  28.281 -endgenerate
  28.282 -
  28.283 -/////////////////////////////////////////////////////
  28.284 -// Combinational logic
  28.285 -/////////////////////////////////////////////////////
  28.286 -
  28.287 -// Compute which ways in the cache match the address address being read
  28.288 -generate
  28.289 -    for (i = 0; i < associativity; i = i + 1)
  28.290 -    begin : match
  28.291 -assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_f[`LM32_IC_ADDR_TAG_RNG], `TRUE});
  28.292 -    end
  28.293 -endgenerate
  28.294 -
  28.295 -// Select data from way that matched the address being read     
  28.296 -generate
  28.297 -    if (associativity == 1)
  28.298 -    begin : inst_1
  28.299 -assign inst = way_match[0] ? way_data[0] : 32'b0;
  28.300 -    end
  28.301 -    else if (associativity == 2)
  28.302 -	 begin : inst_2
  28.303 -assign inst = way_match[0] ? way_data[0] : (way_match[1] ? way_data[1] : 32'b0);
  28.304 -    end
  28.305 -endgenerate
  28.306 -
  28.307 -// Compute address to use to index into the data memories
  28.308 -generate 
  28.309 -    if (bytes_per_line > 4)
  28.310 -assign dmem_write_address = {refill_address[`LM32_IC_ADDR_SET_RNG], refill_offset};
  28.311 -    else
  28.312 -assign dmem_write_address = refill_address[`LM32_IC_ADDR_SET_RNG];
  28.313 -endgenerate
  28.314 -    
  28.315 -assign dmem_read_address = address_a[`LM32_IC_ADDR_IDX_RNG];
  28.316 -
  28.317 -// Compute address to use to index into the tag memories                        
  28.318 -assign tmem_read_address = address_a[`LM32_IC_ADDR_SET_RNG];
  28.319 -assign tmem_write_address = flushing 
  28.320 -                                ? flush_set
  28.321 -                                : refill_address[`LM32_IC_ADDR_SET_RNG];
  28.322 -
  28.323 -// Compute signal to indicate when we are on the last refill accesses
  28.324 -generate 
  28.325 -    if (bytes_per_line > 4)                            
  28.326 -assign last_refill = refill_offset == {addr_offset_width{1'b1}};
  28.327 -    else
  28.328 -assign last_refill = `TRUE;
  28.329 -endgenerate
  28.330 -
  28.331 -// Compute data and tag memory access enable
  28.332 -assign enable = (stall_a == `FALSE);
  28.333 -
  28.334 -// Compute data and tag memory write enables
  28.335 -generate
  28.336 -    if (associativity == 1) 
  28.337 -    begin : we_1     
  28.338 -assign way_mem_we[0] = (refill_ready == `TRUE);
  28.339 -    end
  28.340 -    else
  28.341 -    begin : we_2
  28.342 -assign way_mem_we[0] = (refill_ready == `TRUE) && (refill_way_select[0] == `TRUE);
  28.343 -assign way_mem_we[1] = (refill_ready == `TRUE) && (refill_way_select[1] == `TRUE);
  28.344 -    end
  28.345 -endgenerate                     
  28.346 -
  28.347 -// On the last refill cycle set the valid bit, for all other writes it should be cleared
  28.348 -assign tmem_write_data[`LM32_IC_TAGS_VALID_RNG] = last_refill & !flushing;
  28.349 -assign tmem_write_data[`LM32_IC_TAGS_TAG_RNG] = refill_address[`LM32_IC_ADDR_TAG_RNG];
  28.350 -
  28.351 -// Signals that indicate which state we are in
  28.352 -assign flushing = |state[1:0];
  28.353 -assign check = state[2];
  28.354 -assign refill = state[3];
  28.355 -
  28.356 -assign miss = (~(|way_match)) && (read_enable_f == `TRUE) && (stall_f == `FALSE) && !(valid_d && branch_predict_taken_d);
  28.357 -assign stall_request = (check == `FALSE);
  28.358 -assign refill_request = (refill == `TRUE);
  28.359 -                      
  28.360 -/////////////////////////////////////////////////////
  28.361 -// Sequential logic
  28.362 -/////////////////////////////////////////////////////
  28.363 -
  28.364 -// Record way selected for replacement on a cache miss
  28.365 -generate
  28.366 -    if (associativity >= 2) 
  28.367 -    begin : way_select      
  28.368 -always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  28.369 -begin
  28.370 -    if (rst_i == `TRUE)
  28.371 -        refill_way_select <= {{associativity-1{1'b0}}, 1'b1};
  28.372 -    else
  28.373 -    begin        
  28.374 -        if (miss == `TRUE)
  28.375 -            refill_way_select <= {refill_way_select[0], refill_way_select[1]};
  28.376 -    end
  28.377 -end
  28.378 -    end
  28.379 -endgenerate
  28.380 -
  28.381 -// Record whether we are refilling
  28.382 -always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  28.383 -begin
  28.384 -    if (rst_i == `TRUE)
  28.385 -        refilling <= `FALSE;
  28.386 -    else
  28.387 -        refilling <= refill;
  28.388 -end
  28.389 -
  28.390 -// Instruction cache control FSM
  28.391 -always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  28.392 -begin
  28.393 -    if (rst_i == `TRUE)
  28.394 -    begin
  28.395 -        state <= `LM32_IC_STATE_FLUSH_INIT;
  28.396 -        flush_set <= {`LM32_IC_TMEM_ADDR_WIDTH{1'b1}};
  28.397 -        refill_address <= {`LM32_PC_WIDTH{1'bx}};
  28.398 -        restart_request <= `FALSE;
  28.399 -    end
  28.400 -    else 
  28.401 -    begin
  28.402 -        case (state)
  28.403 -
  28.404 -        // Flush the cache for the first time after reset
  28.405 -        `LM32_IC_STATE_FLUSH_INIT:
  28.406 -        begin            
  28.407 -            if (flush_set == {`LM32_IC_TMEM_ADDR_WIDTH{1'b0}})
  28.408 -                state <= `LM32_IC_STATE_CHECK;
  28.409 -            flush_set <= flush_set - 1'b1;
  28.410 -        end
  28.411 -
  28.412 -        // Flush the cache in response to an write to the ICC CSR
  28.413 -        `LM32_IC_STATE_FLUSH:
  28.414 -        begin            
  28.415 -            if (flush_set == {`LM32_IC_TMEM_ADDR_WIDTH{1'b0}})
  28.416 -`ifdef CFG_IROM_ENABLED
  28.417 -	      if (select_f)
  28.418 -                state <= `LM32_IC_STATE_REFILL;
  28.419 -	      else
  28.420 -`endif
  28.421 -		state <= `LM32_IC_STATE_CHECK;
  28.422 -	   
  28.423 -            flush_set <= flush_set - 1'b1;
  28.424 -        end
  28.425 -        
  28.426 -        // Check for cache misses
  28.427 -        `LM32_IC_STATE_CHECK:
  28.428 -        begin            
  28.429 -            if (stall_a == `FALSE)
  28.430 -                restart_request <= `FALSE;
  28.431 -            if (iflush == `TRUE)
  28.432 -            begin
  28.433 -                refill_address <= address_f;
  28.434 -                state <= `LM32_IC_STATE_FLUSH;
  28.435 -            end
  28.436 -            else if (miss == `TRUE)
  28.437 -            begin
  28.438 -                refill_address <= address_f;
  28.439 -                state <= `LM32_IC_STATE_REFILL;
  28.440 -            end
  28.441 -        end
  28.442 -
  28.443 -        // Refill a cache line
  28.444 -        `LM32_IC_STATE_REFILL:
  28.445 -        begin            
  28.446 -            if (refill_ready == `TRUE)
  28.447 -            begin
  28.448 -                if (last_refill == `TRUE)
  28.449 -                begin
  28.450 -                    restart_request <= `TRUE;
  28.451 -                    state <= `LM32_IC_STATE_CHECK;
  28.452 -                end
  28.453 -            end
  28.454 -        end
  28.455 -
  28.456 -        endcase        
  28.457 -    end
  28.458 -end
  28.459 -
  28.460 -generate 
  28.461 -    if (bytes_per_line > 4)
  28.462 -    begin
  28.463 -// Refill offset
  28.464 -always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  28.465 -begin
  28.466 -    if (rst_i == `TRUE)
  28.467 -        refill_offset <= {addr_offset_width{1'b0}};
  28.468 -    else 
  28.469 -    begin
  28.470 -        case (state)
  28.471 -        
  28.472 -        // Check for cache misses
  28.473 -        `LM32_IC_STATE_CHECK:
  28.474 -        begin            
  28.475 -            if (iflush == `TRUE)
  28.476 -                refill_offset <= {addr_offset_width{1'b0}};
  28.477 -            else if (miss == `TRUE)
  28.478 -                refill_offset <= {addr_offset_width{1'b0}};
  28.479 -        end
  28.480 -
  28.481 -        // Refill a cache line
  28.482 -        `LM32_IC_STATE_REFILL:
  28.483 -        begin            
  28.484 -            if (refill_ready == `TRUE)
  28.485 -                refill_offset <= refill_offset + 1'b1;
  28.486 -        end
  28.487 -
  28.488 -        endcase        
  28.489 -    end
  28.490 -end
  28.491 -    end
  28.492 -endgenerate
  28.493 -   
  28.494 -endmodule
  28.495 -
  28.496 -`endif
  28.497 -

    29.1 --- a/lm32_include.v	Sun Mar 06 21:17:31 2011 +0000
    29.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    29.3 @@ -1,368 +0,0 @@
    29.4 -// =============================================================================
    29.5 -//                           COPYRIGHT NOTICE
    29.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation
    29.7 -// ALL RIGHTS RESERVED
    29.8 -// This confidential and proprietary software may be used only as authorised by
    29.9 -// a licensing agreement from Lattice Semiconductor Corporation.
   29.10 -// The entire notice above must be reproduced on all authorized copies and
   29.11 -// copies may only be made to the extent permitted by a licensing agreement from
   29.12 -// Lattice Semiconductor Corporation.
   29.13 -//
   29.14 -// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
   29.15 -// 5555 NE Moore Court                            408-826-6000 (other locations)
   29.16 -// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
   29.17 -// U.S.A                                   email: techsupport@latticesemi.com
   29.18 -// =============================================================================/
   29.19 -//                         FILE DETAILS
   29.20 -// Project          : LatticeMico32
   29.21 -// File             : lm32_include.v
   29.22 -// Title            : CPU global macros
   29.23 -// Version          : 6.1.17
   29.24 -//                  : Initial Release
   29.25 -// Version          : 7.0SP2, 3.0
   29.26 -//                  : No Change
   29.27 -// Version          : 3.1
   29.28 -//                  : No Change
   29.29 -// Version          : 3.2
   29.30 -//                  : No Change
   29.31 -// Version          : 3.3
   29.32 -//                  : Support for extended configuration register
   29.33 -// =============================================================================
   29.34 -
   29.35 -`ifdef LM32_INCLUDE_V
   29.36 -`else
   29.37 -`define LM32_INCLUDE_V
   29.38 -
   29.39 -//
   29.40 -// Common configuration options
   29.41 -//
   29.42 -
   29.43 -`define CFG_EBA_RESET 32'h00000000
   29.44 -`define CFG_DEBA_RESET 32'h10000000
   29.45 -
   29.46 -`define CFG_PL_MULTIPLY_ENABLED
   29.47 -`define CFG_PL_BARREL_SHIFT_ENABLED
   29.48 -`define CFG_SIGN_EXTEND_ENABLED
   29.49 -`define CFG_MC_DIVIDE_ENABLED
   29.50 -`define CFG_EBR_POSEDGE_REGISTER_FILE
   29.51 -
   29.52 -// [found by Milkymist dev'rs]
   29.53 -// Bug in Xst:
   29.54 -// CFG_ICACHE_ASSOCIATIVITY=2 => works in most cases (random crash on complex software)
   29.55 -// CFG_ICACHE_ASSOCIATIVITY=1 => disaster, CPU will not work at all
   29.56 -// Works 100% OK with expensive synthesizers.
   29.57 -`define CFG_ICACHE_ENABLED
   29.58 -`define CFG_ICACHE_ASSOCIATIVITY   1
   29.59 -`define CFG_ICACHE_SETS            256
   29.60 -`define CFG_ICACHE_BYTES_PER_LINE  16
   29.61 -`define CFG_ICACHE_BASE_ADDRESS    32'h0
   29.62 -`define CFG_ICACHE_LIMIT           32'h7FFF_FFFF
   29.63 -
   29.64 -`define CFG_DCACHE_ENABLED
   29.65 -`define CFG_DCACHE_ASSOCIATIVITY   1
   29.66 -`define CFG_DCACHE_SETS            256
   29.67 -`define CFG_DCACHE_BYTES_PER_LINE  16
   29.68 -`define CFG_DCACHE_BASE_ADDRESS    32'h0
   29.69 -`define CFG_DCACHE_LIMIT           32'h0FFF_FFFF
   29.70 -
   29.71 -// Enable Debugging
   29.72 -//`define CFG_JTAG_ENABLED
   29.73 -//`define CFG_JTAG_UART_ENABLED
   29.74 -//`define CFG_DEBUG_ENABLED
   29.75 -//`define CFG_HW_DEBUG_ENABLED
   29.76 -//`define CFG_ROM_DEBUG_ENABLED
   29.77 -//`define CFG_BREAKPOINTS 32'h0
   29.78 -//`define CFG_WATCHPOINTS 32'h0
   29.79 -
   29.80 -//
   29.81 -// End of common configuration options
   29.82 -//
   29.83 -
   29.84 -`ifdef TRUE
   29.85 -`else
   29.86 -`define TRUE    1'b1
   29.87 -`define FALSE   1'b0
   29.88 -`define TRUE_N  1'b0
   29.89 -`define FALSE_N 1'b1
   29.90 -`endif
   29.91 -
   29.92 -// Wishbone configuration
   29.93 -`define CFG_IWB_ENABLED
   29.94 -`define CFG_DWB_ENABLED
   29.95 -
   29.96 -// Data-path width
   29.97 -`define LM32_WORD_WIDTH                 32
   29.98 -`define LM32_WORD_RNG                   (`LM32_WORD_WIDTH-1):0
   29.99 -`define LM32_SHIFT_WIDTH                5
  29.100 -`define LM32_SHIFT_RNG                  (`LM32_SHIFT_WIDTH-1):0
  29.101 -`define LM32_BYTE_SELECT_WIDTH          4
  29.102 -`define LM32_BYTE_SELECT_RNG            (`LM32_BYTE_SELECT_WIDTH-1):0
  29.103 -
  29.104 -// Register file size
  29.105 -`define LM32_REGISTERS                  32
  29.106 -`define LM32_REG_IDX_WIDTH              5
  29.107 -`define LM32_REG_IDX_RNG                (`LM32_REG_IDX_WIDTH-1):0
  29.108 -
  29.109 -// Standard register numbers
  29.110 -`define LM32_RA_REG                     `LM32_REG_IDX_WIDTH'd29
  29.111 -`define LM32_EA_REG                     `LM32_REG_IDX_WIDTH'd30
  29.112 -`define LM32_BA_REG                     `LM32_REG_IDX_WIDTH'd31
  29.113 -
  29.114 -// Range of Program Counter. Two LSBs are always 0. 
  29.115 -// `ifdef CFG_ICACHE_ENABLED
  29.116 -// `define LM32_PC_WIDTH                   (clogb2(`CFG_ICACHE_LIMIT-`CFG_ICACHE_BASE_ADDRESS)-2)
  29.117 -// `else
  29.118 -// `ifdef CFG_IWB_ENABLED
  29.119 -`define LM32_PC_WIDTH                   (`LM32_WORD_WIDTH-2)
  29.120 -// `else
  29.121 -// `define LM32_PC_WIDTH                   `LM32_IROM_ADDRESS_WIDTH
  29.122 -// `endif
  29.123 -// `endif
  29.124 -`define LM32_PC_RNG                     (`LM32_PC_WIDTH+2-1):2
  29.125 -
  29.126 -// Range of an instruction
  29.127 -`define LM32_INSTRUCTION_WIDTH          32
  29.128 -`define LM32_INSTRUCTION_RNG            (`LM32_INSTRUCTION_WIDTH-1):0
  29.129 -
  29.130 -// Adder operation
  29.131 -`define LM32_ADDER_OP_ADD               1'b0
  29.132 -`define LM32_ADDER_OP_SUBTRACT          1'b1
  29.133 -
  29.134 -// Shift direction
  29.135 -`define LM32_SHIFT_OP_RIGHT             1'b0
  29.136 -`define LM32_SHIFT_OP_LEFT              1'b1
  29.137 -
  29.138 -// Bus errors
  29.139 -//`define CFG_BUS_ERRORS_ENABLED
  29.140 -
  29.141 -// Derive macro that indicates whether we have single-stepping or not
  29.142 -`ifdef CFG_ROM_DEBUG_ENABLED
  29.143 -`define LM32_SINGLE_STEP_ENABLED
  29.144 -`else
  29.145 -`ifdef CFG_HW_DEBUG_ENABLED
  29.146 -`define LM32_SINGLE_STEP_ENABLED
  29.147 -`endif
  29.148 -`endif
  29.149 -
  29.150 -// Derive macro that indicates whether JTAG interface is required
  29.151 -`ifdef CFG_JTAG_UART_ENABLED
  29.152 -`define LM32_JTAG_ENABLED
  29.153 -`else
  29.154 -`ifdef CFG_DEBUG_ENABLED
  29.155 -`define LM32_JTAG_ENABLED
  29.156 -`else
  29.157 -`endif
  29.158 -`endif
  29.159 -
  29.160 -// Derive macro that indicates whether we have a barrel-shifter or not
  29.161 -`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  29.162 -`define LM32_BARREL_SHIFT_ENABLED
  29.163 -`else // CFG_PL_BARREL_SHIFT_ENABLED
  29.164 -`ifdef CFG_MC_BARREL_SHIFT_ENABLED
  29.165 -`define LM32_BARREL_SHIFT_ENABLED
  29.166 -`else
  29.167 -`define LM32_NO_BARREL_SHIFT
  29.168 -`endif
  29.169 -`endif // CFG_PL_BARREL_SHIFT_ENABLED
  29.170 -
  29.171 -// Derive macro that indicates whether we have a multiplier or not
  29.172 -`ifdef CFG_PL_MULTIPLY_ENABLED
  29.173 -`define LM32_MULTIPLY_ENABLED
  29.174 -`else
  29.175 -`ifdef CFG_MC_MULTIPLY_ENABLED
  29.176 -`define LM32_MULTIPLY_ENABLED
  29.177 -`endif
  29.178 -`endif
  29.179 -
  29.180 -// Derive a macro that indicates whether or not the multi-cycle arithmetic unit is required
  29.181 -`ifdef CFG_MC_DIVIDE_ENABLED
  29.182 -`define LM32_MC_ARITHMETIC_ENABLED
  29.183 -`endif
  29.184 -`ifdef CFG_MC_MULTIPLY_ENABLED
  29.185 -`define LM32_MC_ARITHMETIC_ENABLED
  29.186 -`endif
  29.187 -`ifdef CFG_MC_BARREL_SHIFT_ENABLED
  29.188 -`define LM32_MC_ARITHMETIC_ENABLED
  29.189 -`endif
  29.190 -
  29.191 -// Derive macro that indicates if we are using an EBR register file
  29.192 -`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
  29.193 -`define LM32_EBR_REGISTER_FILE
  29.194 -`endif
  29.195 -`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
  29.196 -`define LM32_EBR_REGISTER_FILE
  29.197 -`endif
  29.198 -
  29.199 -// Revision number
  29.200 -`define LM32_REVISION                   6'h02
  29.201 -
  29.202 -// Logical operations - Function encoded directly in instruction
  29.203 -`define LM32_LOGIC_OP_RNG               3:0
  29.204 -
  29.205 -// Conditions for conditional branches
  29.206 -`define LM32_CONDITION_WIDTH            3
  29.207 -`define LM32_CONDITION_RNG              (`LM32_CONDITION_WIDTH-1):0
  29.208 -`define LM32_CONDITION_E                3'b001
  29.209 -`define LM32_CONDITION_G                3'b010
  29.210 -`define LM32_CONDITION_GE               3'b011
  29.211 -`define LM32_CONDITION_GEU              3'b100
  29.212 -`define LM32_CONDITION_GU               3'b101
  29.213 -`define LM32_CONDITION_NE               3'b111
  29.214 -`define LM32_CONDITION_U1               3'b000
  29.215 -`define LM32_CONDITION_U2               3'b110
  29.216 -
  29.217 -// Size of load or store instruction - Encoding corresponds to opcode
  29.218 -`define LM32_SIZE_WIDTH                 2
  29.219 -`define LM32_SIZE_RNG                   1:0
  29.220 -`define LM32_SIZE_BYTE                  2'b00
  29.221 -`define LM32_SIZE_HWORD                 2'b11
  29.222 -`define LM32_SIZE_WORD                  2'b10
  29.223 -`define LM32_ADDRESS_LSBS_WIDTH         2
  29.224 -
  29.225 -// Width and range of a CSR index
  29.226 -`ifdef CFG_DEBUG_ENABLED
  29.227 -`define LM32_CSR_WIDTH                  5
  29.228 -`define LM32_CSR_RNG                    (`LM32_CSR_WIDTH-1):0
  29.229 -`else
  29.230 -`ifdef CFG_JTAG_ENABLED
  29.231 -`define LM32_CSR_WIDTH                  4
  29.232 -`define LM32_CSR_RNG                    (`LM32_CSR_WIDTH-1):0
  29.233 -`else
  29.234 -`define LM32_CSR_WIDTH                  3
  29.235 -`define LM32_CSR_RNG                    (`LM32_CSR_WIDTH-1):0
  29.236 -`endif
  29.237 -`endif
  29.238 -
  29.239 -// CSR indices
  29.240 -`define LM32_CSR_IE                     `LM32_CSR_WIDTH'h0
  29.241 -`define LM32_CSR_IM                     `LM32_CSR_WIDTH'h1
  29.242 -`define LM32_CSR_IP                     `LM32_CSR_WIDTH'h2
  29.243 -`define LM32_CSR_ICC                    `LM32_CSR_WIDTH'h3
  29.244 -`define LM32_CSR_DCC                    `LM32_CSR_WIDTH'h4
  29.245 -`define LM32_CSR_CC                     `LM32_CSR_WIDTH'h5
  29.246 -`define LM32_CSR_CFG                    `LM32_CSR_WIDTH'h6
  29.247 -`define LM32_CSR_EBA                    `LM32_CSR_WIDTH'h7
  29.248 -`ifdef CFG_DEBUG_ENABLED
  29.249 -`define LM32_CSR_DC                     `LM32_CSR_WIDTH'h8
  29.250 -`define LM32_CSR_DEBA                   `LM32_CSR_WIDTH'h9
  29.251 -`endif
  29.252 -`define LM32_CSR_CFG2                   `LM32_CSR_WIDTH'ha
  29.253 -`ifdef CFG_JTAG_ENABLED
  29.254 -`define LM32_CSR_JTX                    `LM32_CSR_WIDTH'he
  29.255 -`define LM32_CSR_JRX                    `LM32_CSR_WIDTH'hf
  29.256 -`endif
  29.257 -`ifdef CFG_DEBUG_ENABLED
  29.258 -`define LM32_CSR_BP0                    `LM32_CSR_WIDTH'h10
  29.259 -`define LM32_CSR_BP1                    `LM32_CSR_WIDTH'h11
  29.260 -`define LM32_CSR_BP2                    `LM32_CSR_WIDTH'h12
  29.261 -`define LM32_CSR_BP3                    `LM32_CSR_WIDTH'h13
  29.262 -`define LM32_CSR_WP0                    `LM32_CSR_WIDTH'h18
  29.263 -`define LM32_CSR_WP1                    `LM32_CSR_WIDTH'h19
  29.264 -`define LM32_CSR_WP2                    `LM32_CSR_WIDTH'h1a
  29.265 -`define LM32_CSR_WP3                    `LM32_CSR_WIDTH'h1b
  29.266 -`endif 
  29.267 -
  29.268 -// Values for WPC CSR
  29.269 -`define LM32_WPC_C_RNG                  1:0
  29.270 -`define LM32_WPC_C_DISABLED             2'b00
  29.271 -`define LM32_WPC_C_READ                 2'b01
  29.272 -`define LM32_WPC_C_WRITE                2'b10
  29.273 -`define LM32_WPC_C_READ_WRITE           2'b11
  29.274 -
  29.275 -// Exception IDs
  29.276 -`define LM32_EID_WIDTH                  3
  29.277 -`define LM32_EID_RNG                    (`LM32_EID_WIDTH-1):0
  29.278 -`define LM32_EID_RESET                  3'h0
  29.279 -`define LM32_EID_BREAKPOINT             3'd1
  29.280 -`define LM32_EID_INST_BUS_ERROR         3'h2
  29.281 -`define LM32_EID_WATCHPOINT             3'd3
  29.282 -`define LM32_EID_DATA_BUS_ERROR         3'h4
  29.283 -`define LM32_EID_DIVIDE_BY_ZERO         3'h5
  29.284 -`define LM32_EID_INTERRUPT              3'h6
  29.285 -`define LM32_EID_SCALL                  3'h7
  29.286 -
  29.287 -// Pipeline result selection mux controls
  29.288 -
  29.289 -`define LM32_D_RESULT_SEL_0_RNG          0:0
  29.290 -`define LM32_D_RESULT_SEL_0_REG_0        1'b0
  29.291 -`define LM32_D_RESULT_SEL_0_NEXT_PC      1'b1
  29.292 -
  29.293 -`define LM32_D_RESULT_SEL_1_RNG          1:0
  29.294 -`define LM32_D_RESULT_SEL_1_ZERO         2'b00
  29.295 -`define LM32_D_RESULT_SEL_1_REG_1        2'b01
  29.296 -`define LM32_D_RESULT_SEL_1_IMMEDIATE    2'b10
  29.297 -
  29.298 -`define LM32_USER_OPCODE_WIDTH           11
  29.299 -`define LM32_USER_OPCODE_RNG             (`LM32_USER_OPCODE_WIDTH-1):0
  29.300 -
  29.301 -// Derive a macro to indicate if either of the caches are implemented
  29.302 -`ifdef CFG_ICACHE_ENABLED
  29.303 -`define LM32_CACHE_ENABLED      
  29.304 -`else
  29.305 -`ifdef CFG_DCACHE_ENABLED
  29.306 -`define LM32_CACHE_ENABLED
  29.307 -`endif
  29.308 -`endif
  29.309 -
  29.310 -/////////////////////////////////////////////////////
  29.311 -// Interrupts
  29.312 -/////////////////////////////////////////////////////
  29.313 -
  29.314 -// Always enable interrupts
  29.315 -`define CFG_INTERRUPTS_ENABLED
  29.316 -
  29.317 -// Currently this is fixed to 32 and should not be changed
  29.318 -`define CFG_INTERRUPTS                  32
  29.319 -`define LM32_INTERRUPT_WIDTH            `CFG_INTERRUPTS
  29.320 -`define LM32_INTERRUPT_RNG              (`LM32_INTERRUPT_WIDTH-1):0
  29.321 -
  29.322 -/////////////////////////////////////////////////////
  29.323 -// General
  29.324 -/////////////////////////////////////////////////////
  29.325 -
  29.326 -// Sub-word range types
  29.327 -`define LM32_BYTE_WIDTH                 8
  29.328 -`define LM32_BYTE_RNG                   7:0
  29.329 -`define LM32_HWORD_WIDTH                16
  29.330 -`define LM32_HWORD_RNG                  15:0
  29.331 -
  29.332 -// Word sub-byte indicies
  29.333 -`define LM32_BYTE_0_RNG                  7:0
  29.334 -`define LM32_BYTE_1_RNG                  15:8
  29.335 -`define LM32_BYTE_2_RNG                  23:16
  29.336 -`define LM32_BYTE_3_RNG                  31:24
  29.337 -
  29.338 -// Word sub-halfword indices
  29.339 -`define LM32_HWORD_0_RNG                 15:0
  29.340 -`define LM32_HWORD_1_RNG                 31:16
  29.341 -
  29.342 -// Use an asynchronous reset
  29.343 -// To use a synchronous reset, define this macro as nothing
  29.344 -//`define CFG_RESET_SENSITIVITY or posedge rst_i
  29.345 -`define CFG_RESET_SENSITIVITY
  29.346 -
  29.347 -// Whether to include context registers for debug exceptions
  29.348 -// in addition to standard exception handling registers
  29.349 -`define CFG_DEBUG_EXCEPTIONS_ENABLED
  29.350 -
  29.351 -// Wishbone defines
  29.352 -// Refer to Wishbone System-on-Chip Interconnection Architecture
  29.353 -// These should probably be moved to a Wishbone common file
  29.354 -
  29.355 -// Wishbone cycle types
  29.356 -`define LM32_CTYPE_WIDTH                3
  29.357 -`define LM32_CTYPE_RNG                  (`LM32_CTYPE_WIDTH-1):0
  29.358 -`define LM32_CTYPE_CLASSIC              3'b000
  29.359 -`define LM32_CTYPE_CONSTANT             3'b001
  29.360 -`define LM32_CTYPE_INCREMENTING         3'b010
  29.361 -`define LM32_CTYPE_END                  3'b111
  29.362 -
  29.363 -// Wishbone burst types
  29.364 -`define LM32_BTYPE_WIDTH                2
  29.365 -`define LM32_BTYPE_RNG                  (`LM32_BTYPE_WIDTH-1):0
  29.366 -`define LM32_BTYPE_LINEAR               2'b00
  29.367 -`define LM32_BTYPE_4_BEAT               2'b01
  29.368 -`define LM32_BTYPE_8_BEAT               2'b10
  29.369 -`define LM32_BTYPE_16_BEAT              2'b11
  29.370 -
  29.371 -`endif

    30.1 --- a/lm32_instruction_unit.v	Sun Mar 06 21:17:31 2011 +0000
    30.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    30.3 @@ -1,839 +0,0 @@
    30.4 -// =============================================================================
    30.5 -//                           COPYRIGHT NOTICE
    30.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation
    30.7 -// ALL RIGHTS RESERVED
    30.8 -// This confidential and proprietary software may be used only as authorised by
    30.9 -// a licensing agreement from Lattice Semiconductor Corporation.
   30.10 -// The entire notice above must be reproduced on all authorized copies and
   30.11 -// copies may only be made to the extent permitted by a licensing agreement from
   30.12 -// Lattice Semiconductor Corporation.
   30.13 -//
   30.14 -// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
   30.15 -// 5555 NE Moore Court                            408-826-6000 (other locations)
   30.16 -// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
   30.17 -// U.S.A                                   email: techsupport@latticesemi.com
   30.18 -// =============================================================================/
   30.19 -//                         FILE DETAILS
   30.20 -// Project      : LatticeMico32
   30.21 -// File         : lm32_instruction_unit.v
   30.22 -// Title        : Instruction unit
   30.23 -// Dependencies : lm32_include.v
   30.24 -// Version      : 6.1.17
   30.25 -//              : Initial Release
   30.26 -// Version      : 7.0SP2, 3.0
   30.27 -//              : No Change
   30.28 -// Version      : 3.1
   30.29 -//              : Support for static branch prediction is added. Fetching of
   30.30 -//              : instructions can also be altered by branches predicted in D
   30.31 -//              : stage of pipeline, and mispredicted branches in the X and M 
   30.32 -//              : stages of the pipeline.
   30.33 -// Version      : 3.2
   30.34 -//              : EBRs use SYNC resets instead of ASYNC resets.
   30.35 -// Version      : 3.3
   30.36 -//              : Support for a non-cacheable Instruction Memory that has a 
   30.37 -//              : single-cycle access latency. This memory can be accessed by
   30.38 -//              : data port of LM32 (so that debugger has access to it).
   30.39 -// Version      : 3.4
   30.40 -//              : No change
   30.41 -// Version      : 3.5
   30.42 -//              : Bug fix: Inline memory is correctly generated if it is not a
   30.43 -//              : power-of-two.
   30.44 -//              : Bug fix: Fixed a bug that caused LM32 (configured without
   30.45 -//              : instruction cache) to lock up in to an infinite loop due to a 
   30.46 -//              : instruction bus error when EBA was set to instruction inline
   30.47 -//              : memory.
   30.48 -// =============================================================================
   30.49 -
   30.50 -`include "lm32_include.v"
   30.51 -
   30.52 -/////////////////////////////////////////////////////
   30.53 -// Module interface
   30.54 -/////////////////////////////////////////////////////
   30.55 -
   30.56 -module lm32_instruction_unit (
   30.57 -    // ----- Inputs -------
   30.58 -    clk_i,
   30.59 -    rst_i,
   30.60 -    // From pipeline
   30.61 -    stall_a,
   30.62 -    stall_f,
   30.63 -    stall_d,
   30.64 -    stall_x,
   30.65 -    stall_m,
   30.66 -    valid_f,
   30.67 -    valid_d,
   30.68 -    kill_f,
   30.69 -    branch_predict_taken_d,
   30.70 -    branch_predict_address_d,
   30.71 -`ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
   30.72 -    branch_taken_x,
   30.73 -    branch_target_x,
   30.74 -`endif
   30.75 -    exception_m,
   30.76 -    branch_taken_m,
   30.77 -    branch_mispredict_taken_m,
   30.78 -    branch_target_m,
   30.79 -`ifdef CFG_ICACHE_ENABLED
   30.80 -    iflush,
   30.81 -`endif
   30.82 -`ifdef CFG_DCACHE_ENABLED
   30.83 -    dcache_restart_request,
   30.84 -    dcache_refill_request,
   30.85 -    dcache_refilling,
   30.86 -`endif        
   30.87 -`ifdef CFG_IROM_ENABLED
   30.88 -    irom_store_data_m,
   30.89 -    irom_address_xm,
   30.90 -    irom_we_xm,
   30.91 -`endif
   30.92 -`ifdef CFG_IWB_ENABLED
   30.93 -    // From Wishbone
   30.94 -    i_dat_i,
   30.95 -    i_ack_i,
   30.96 -    i_err_i,
   30.97 -`endif
   30.98 -`ifdef CFG_HW_DEBUG_ENABLED
   30.99 -    jtag_read_enable,
  30.100 -    jtag_write_enable,
  30.101 -    jtag_write_data,
  30.102 -    jtag_address,
  30.103 -`endif
  30.104 -    // ----- Outputs -------
  30.105 -    // To pipeline
  30.106 -    pc_f,
  30.107 -    pc_d,
  30.108 -    pc_x,
  30.109 -    pc_m,
  30.110 -    pc_w,
  30.111 -`ifdef CFG_ICACHE_ENABLED
  30.112 -    icache_stall_request,
  30.113 -    icache_restart_request,
  30.114 -    icache_refill_request,
  30.115 -    icache_refilling,
  30.116 -`endif
  30.117 -`ifdef CFG_IROM_ENABLED
  30.118 -    irom_data_m,
  30.119 -`endif
  30.120 -`ifdef CFG_IWB_ENABLED
  30.121 -    // To Wishbone
  30.122 -    i_dat_o,
  30.123 -    i_adr_o,
  30.124 -    i_cyc_o,
  30.125 -    i_sel_o,
  30.126 -    i_stb_o,
  30.127 -    i_we_o,
  30.128 -    i_cti_o,
  30.129 -    i_lock_o,
  30.130 -    i_bte_o,
  30.131 -`endif
  30.132 -`ifdef CFG_HW_DEBUG_ENABLED
  30.133 -    jtag_read_data,
  30.134 -    jtag_access_complete,
  30.135 -`endif
  30.136 -`ifdef CFG_BUS_ERRORS_ENABLED
  30.137 -    bus_error_d,
  30.138 -`endif
  30.139 -`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
  30.140 -    instruction_f,
  30.141 -`endif    
  30.142 -    instruction_d
  30.143 -    );
  30.144 -
  30.145 -/////////////////////////////////////////////////////
  30.146 -// Parameters
  30.147 -/////////////////////////////////////////////////////
  30.148 -
  30.149 -parameter associativity = 1;                            // Associativity of the cache (Number of ways)
  30.150 -parameter sets = 512;                                   // Number of sets
  30.151 -parameter bytes_per_line = 16;                          // Number of bytes per cache line
  30.152 -parameter base_address = 0;                             // Base address of cachable memory
  30.153 -parameter limit = 0;                                    // Limit (highest address) of cachable memory
  30.154 -
  30.155 -// For bytes_per_line == 4, we set 1 so part-select range isn't reversed, even though not really used 
  30.156 -localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2;
  30.157 -localparam addr_offset_lsb = 2;
  30.158 -localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
  30.159 -
  30.160 -/////////////////////////////////////////////////////
  30.161 -// Inputs
  30.162 -/////////////////////////////////////////////////////
  30.163 -
  30.164 -input clk_i;                                            // Clock
  30.165 -input rst_i;                                            // Reset
  30.166 -
  30.167 -input stall_a;                                          // Stall A stage instruction
  30.168 -input stall_f;                                          // Stall F stage instruction
  30.169 -input stall_d;                                          // Stall D stage instruction
  30.170 -input stall_x;                                          // Stall X stage instruction
  30.171 -input stall_m;                                          // Stall M stage instruction
  30.172 -input valid_f;                                          // Instruction in F stage is valid
  30.173 -input valid_d;                                          // Instruction in D stage is valid
  30.174 -input kill_f;                                           // Kill instruction in F stage
  30.175 -
  30.176 -input branch_predict_taken_d;                           // Branch is predicted taken in D stage
  30.177 -input [`LM32_PC_RNG] branch_predict_address_d;          // Branch target address
  30.178 -   
  30.179 -`ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
  30.180 -input branch_taken_x;                                   // Branch instruction in X stage is taken
  30.181 -input [`LM32_PC_RNG] branch_target_x;                   // Target PC of X stage branch instruction
  30.182 -`endif
  30.183 -input exception_m;
  30.184 -input branch_taken_m;                                   // Branch instruction in M stage is taken
  30.185 -input branch_mispredict_taken_m;                        // Branch instruction in M stage is mispredicted as taken
  30.186 -input [`LM32_PC_RNG] branch_target_m;                   // Target PC of M stage branch instruction
  30.187 -
  30.188 -`ifdef CFG_ICACHE_ENABLED
  30.189 -input iflush;                                           // Flush instruction cache
  30.190 -`endif
  30.191 -`ifdef CFG_DCACHE_ENABLED
  30.192 -input dcache_restart_request;                           // Restart instruction that caused a data cache miss
  30.193 -input dcache_refill_request;                            // Request to refill data cache
  30.194 -input dcache_refilling;
  30.195 -`endif        
  30.196 -
  30.197 -`ifdef CFG_IROM_ENABLED
  30.198 -input [`LM32_WORD_RNG] irom_store_data_m;               // Data from load-store unit
  30.199 -input [`LM32_WORD_RNG] irom_address_xm;                 // Address from load-store unit
  30.200 -input irom_we_xm;                                       // Indicates if memory operation is load or store
  30.201 -`endif
  30.202 -
  30.203 -`ifdef CFG_IWB_ENABLED
  30.204 -input [`LM32_WORD_RNG] i_dat_i;                         // Instruction Wishbone interface read data
  30.205 -input i_ack_i;                                          // Instruction Wishbone interface acknowledgement
  30.206 -input i_err_i;                                          // Instruction Wishbone interface error
  30.207 -`endif
  30.208 -
  30.209 -`ifdef CFG_HW_DEBUG_ENABLED
  30.210 -input jtag_read_enable;                                 // JTAG read memory request
  30.211 -input jtag_write_enable;                                // JTAG write memory request
  30.212 -input [`LM32_BYTE_RNG] jtag_write_data;                 // JTAG wrirte data
  30.213 -input [`LM32_WORD_RNG] jtag_address;                    // JTAG read/write address
  30.214 -`endif
  30.215 -
  30.216 -/////////////////////////////////////////////////////
  30.217 -// Outputs
  30.218 -/////////////////////////////////////////////////////
  30.219 -        
  30.220 -output [`LM32_PC_RNG] pc_f;                             // F stage PC
  30.221 -reg    [`LM32_PC_RNG] pc_f;
  30.222 -output [`LM32_PC_RNG] pc_d;                             // D stage PC
  30.223 -reg    [`LM32_PC_RNG] pc_d;
  30.224 -output [`LM32_PC_RNG] pc_x;                             // X stage PC
  30.225 -reg    [`LM32_PC_RNG] pc_x;
  30.226 -output [`LM32_PC_RNG] pc_m;                             // M stage PC
  30.227 -reg    [`LM32_PC_RNG] pc_m;
  30.228 -output [`LM32_PC_RNG] pc_w;                             // W stage PC
  30.229 -reg    [`LM32_PC_RNG] pc_w;
  30.230 -
  30.231 -`ifdef CFG_ICACHE_ENABLED
  30.232 -output icache_stall_request;                            // Instruction cache stall request
  30.233 -wire   icache_stall_request;
  30.234 -output icache_restart_request;                          // Request to restart instruction that cached instruction cache miss
  30.235 -wire   icache_restart_request;
  30.236 -output icache_refill_request;                           // Instruction cache refill request
  30.237 -wire   icache_refill_request;
  30.238 -output icache_refilling;                                // Indicates the icache is refilling
  30.239 -wire   icache_refilling;
  30.240 -`endif
  30.241 -
  30.242 -`ifdef CFG_IROM_ENABLED
  30.243 -output [`LM32_WORD_RNG] irom_data_m;                    // Data to load-store unit on load
  30.244 -wire   [`LM32_WORD_RNG] irom_data_m;                      
  30.245 -`endif   
  30.246 -
  30.247 -`ifdef CFG_IWB_ENABLED
  30.248 -output [`LM32_WORD_RNG] i_dat_o;                        // Instruction Wishbone interface write data
  30.249 -`ifdef CFG_HW_DEBUG_ENABLED
  30.250 -reg    [`LM32_WORD_RNG] i_dat_o;
  30.251 -`else
  30.252 -wire   [`LM32_WORD_RNG] i_dat_o;
  30.253 -`endif
  30.254 -output [`LM32_WORD_RNG] i_adr_o;                        // Instruction Wishbone interface address
  30.255 -reg    [`LM32_WORD_RNG] i_adr_o;
  30.256 -output i_cyc_o;                                         // Instruction Wishbone interface cycle
  30.257 -reg    i_cyc_o; 
  30.258 -output [`LM32_BYTE_SELECT_RNG] i_sel_o;                 // Instruction Wishbone interface byte select
  30.259 -`ifdef CFG_HW_DEBUG_ENABLED
  30.260 -reg    [`LM32_BYTE_SELECT_RNG] i_sel_o;
  30.261 -`else
  30.262 -wire   [`LM32_BYTE_SELECT_RNG] i_sel_o;
  30.263 -`endif
  30.264 -output i_stb_o;                                         // Instruction Wishbone interface strobe
  30.265 -reg    i_stb_o;
  30.266 -output i_we_o;                                          // Instruction Wishbone interface write enable
  30.267 -`ifdef CFG_HW_DEBUG_ENABLED
  30.268 -reg    i_we_o;
  30.269 -`else
  30.270 -wire   i_we_o;
  30.271 -`endif
  30.272 -output [`LM32_CTYPE_RNG] i_cti_o;                       // Instruction Wishbone interface cycle type 
  30.273 -reg    [`LM32_CTYPE_RNG] i_cti_o;
  30.274 -output i_lock_o;                                        // Instruction Wishbone interface lock bus
  30.275 -reg    i_lock_o;
  30.276 -output [`LM32_BTYPE_RNG] i_bte_o;                       // Instruction Wishbone interface burst type 
  30.277 -wire   [`LM32_BTYPE_RNG] i_bte_o;
  30.278 -`endif
  30.279 -
  30.280 -`ifdef CFG_HW_DEBUG_ENABLED
  30.281 -output [`LM32_BYTE_RNG] jtag_read_data;                 // Data read for JTAG interface
  30.282 -reg    [`LM32_BYTE_RNG] jtag_read_data;
  30.283 -output jtag_access_complete;                            // Requested memory access by JTAG interface is complete
  30.284 -wire   jtag_access_complete;
  30.285 -`endif
  30.286 -
  30.287 -`ifdef CFG_BUS_ERRORS_ENABLED
  30.288 -output bus_error_d;                                     // Indicates a bus error occured while fetching the instruction
  30.289 -reg    bus_error_d;
  30.290 -`endif
  30.291 -`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
  30.292 -output [`LM32_INSTRUCTION_RNG] instruction_f;           // F stage instruction (only to have register indices extracted from)
  30.293 -wire   [`LM32_INSTRUCTION_RNG] instruction_f;
  30.294 -`endif
  30.295 -output [`LM32_INSTRUCTION_RNG] instruction_d;           // D stage instruction to be decoded
  30.296 -reg    [`LM32_INSTRUCTION_RNG] instruction_d;
  30.297 -
  30.298 -/////////////////////////////////////////////////////
  30.299 -// Internal nets and registers 
  30.300 -/////////////////////////////////////////////////////
  30.301 -
  30.302 -reg [`LM32_PC_RNG] pc_a;                                // A stage PC
  30.303 -
  30.304 -`ifdef LM32_CACHE_ENABLED
  30.305 -reg [`LM32_PC_RNG] restart_address;                     // Address to restart from after a cache miss  
  30.306 -`endif
  30.307 -
  30.308 -`ifdef CFG_ICACHE_ENABLED
  30.309 -wire icache_read_enable_f;                              // Indicates if instruction cache miss is valid
  30.310 -wire [`LM32_PC_RNG] icache_refill_address;              // Address that caused cache miss
  30.311 -reg icache_refill_ready;                                // Indicates when next word of refill data is ready to be written to cache
  30.312 -reg [`LM32_INSTRUCTION_RNG] icache_refill_data;         // Next word of refill data, fetched from Wishbone
  30.313 -wire [`LM32_INSTRUCTION_RNG] icache_data_f;             // Instruction fetched from instruction cache
  30.314 -wire [`LM32_CTYPE_RNG] first_cycle_type;                // First Wishbone cycle type
  30.315 -wire [`LM32_CTYPE_RNG] next_cycle_type;                 // Next Wishbone cycle type
  30.316 -wire last_word;                                         // Indicates if this is the last word in the cache line
  30.317 -wire [`LM32_PC_RNG] first_address;                      // First cache refill address
  30.318 -`else
  30.319 -`ifdef CFG_IWB_ENABLED
  30.320 -reg [`LM32_INSTRUCTION_RNG] wb_data_f;                  // Instruction fetched from Wishbone
  30.321 -`endif
  30.322 -`endif
  30.323 -`ifdef CFG_IROM_ENABLED
  30.324 -wire irom_select_a;                                     // Indicates if A stage PC maps to a ROM address
  30.325 -reg irom_select_f;                                      // Indicates if F stage PC maps to a ROM address
  30.326 -wire [`LM32_INSTRUCTION_RNG] irom_data_f;               // Instruction fetched from ROM
  30.327 -`endif
  30.328 -`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
  30.329 -`else
  30.330 -wire [`LM32_INSTRUCTION_RNG] instruction_f;             // F stage instruction
  30.331 -`endif
  30.332 -`ifdef CFG_BUS_ERRORS_ENABLED
  30.333 -reg bus_error_f;                                        // Indicates if a bus error occured while fetching the instruction in the F stage
  30.334 -`endif
  30.335 -
  30.336 -`ifdef CFG_HW_DEBUG_ENABLED
  30.337 -reg jtag_access;                                        // Indicates if a JTAG WB access is in progress
  30.338 -`endif
  30.339 -
  30.340 -/////////////////////////////////////////////////////
  30.341 -// Functions
  30.342 -/////////////////////////////////////////////////////
  30.343 -
  30.344 -`include "lm32_functions.v"
  30.345 -
  30.346 -/////////////////////////////////////////////////////
  30.347 -// Instantiations
  30.348 -/////////////////////////////////////////////////////
  30.349 -
  30.350 -// Instruction ROM
  30.351 -`ifdef CFG_IROM_ENABLED  
  30.352 -   pmi_ram_dp_true 
  30.353 -     #(
  30.354 -       // ----- Parameters -------
  30.355 -       .pmi_family             (`LATTICE_FAMILY),
  30.356 -	 
  30.357 -       //.pmi_addr_depth_a       (1 << (clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)),
  30.358 -       //.pmi_addr_width_a       ((clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)),
  30.359 -       //.pmi_data_width_a       (`LM32_WORD_WIDTH),
  30.360 -       //.pmi_addr_depth_b       (1 << (clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)),
  30.361 -       //.pmi_addr_width_b       ((clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)),
  30.362 -       //.pmi_data_width_b       (`LM32_WORD_WIDTH),
  30.363 -	 
  30.364 -       .pmi_addr_depth_a       (`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1),
  30.365 -       .pmi_addr_width_a       (clogb2_v1(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
  30.366 -       .pmi_data_width_a       (`LM32_WORD_WIDTH),
  30.367 -       .pmi_addr_depth_b       (`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1),
  30.368 -       .pmi_addr_width_b       (clogb2_v1(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
  30.369 -       .pmi_data_width_b       (`LM32_WORD_WIDTH),
  30.370 -	 
  30.371 -       .pmi_regmode_a          ("noreg"),
  30.372 -       .pmi_regmode_b          ("noreg"),
  30.373 -       .pmi_gsr                ("enable"),
  30.374 -       .pmi_resetmode          ("sync"),
  30.375 -       .pmi_init_file          (`CFG_IROM_INIT_FILE),
  30.376 -       .pmi_init_file_format   (`CFG_IROM_INIT_FILE_FORMAT),
  30.377 -       .module_type            ("pmi_ram_dp_true")
  30.378 -       ) 
  30.379 -       ram (
  30.380 -	    // ----- Inputs -------
  30.381 -	    .ClockA                 (clk_i),
  30.382 -	    .ClockB                 (clk_i),
  30.383 -	    .ResetA                 (rst_i),
  30.384 -	    .ResetB                 (rst_i),
  30.385 -	    .DataInA                ({32{1'b0}}),
  30.386 -	    .DataInB                (irom_store_data_m),
  30.387 -	    .AddressA               (pc_a[(clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)+2-1:2]),
  30.388 -	    .AddressB               (irom_address_xm[(clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)+2-1:2]),
  30.389 -	    .ClockEnA               (!stall_a),
  30.390 -	    .ClockEnB               (!stall_x || !stall_m),
  30.391 -	    .WrA                    (`FALSE),
  30.392 -	    .WrB                    (irom_we_xm), 
  30.393 -	    // ----- Outputs -------
  30.394 -	    .QA                     (irom_data_f),
  30.395 -	    .QB                     (irom_data_m)
  30.396 -	    );
  30.397 -`endif    
  30.398 - 
  30.399 -`ifdef CFG_ICACHE_ENABLED
  30.400 -// Instruction cache
  30.401 -lm32_icache #(
  30.402 -    .associativity          (associativity),
  30.403 -    .sets                   (sets),
  30.404 -    .bytes_per_line         (bytes_per_line),
  30.405 -    .base_address           (base_address),
  30.406 -    .limit                  (limit)
  30.407 -    ) icache ( 
  30.408 -    // ----- Inputs -----
  30.409 -    .clk_i                  (clk_i),
  30.410 -    .rst_i                  (rst_i),      
  30.411 -    .stall_a                (stall_a),
  30.412 -    .stall_f                (stall_f),
  30.413 -    .branch_predict_taken_d (branch_predict_taken_d),
  30.414 -    .valid_d                (valid_d),
  30.415 -    .address_a              (pc_a),
  30.416 -    .address_f              (pc_f),
  30.417 -    .read_enable_f          (icache_read_enable_f),
  30.418 -    .refill_ready           (icache_refill_ready),
  30.419 -    .refill_data            (icache_refill_data),
  30.420 -    .iflush                 (iflush),
  30.421 -    // ----- Outputs -----
  30.422 -    .stall_request          (icache_stall_request),
  30.423 -    .restart_request        (icache_restart_request),
  30.424 -    .refill_request         (icache_refill_request),
  30.425 -    .refill_address         (icache_refill_address),
  30.426 -    .refilling              (icache_refilling),
  30.427 -    .inst                   (icache_data_f)
  30.428 -    );
  30.429 -`endif
  30.430 -
  30.431 -/////////////////////////////////////////////////////
  30.432 -// Combinational Logic
  30.433 -/////////////////////////////////////////////////////
  30.434 -
  30.435 -`ifdef CFG_ICACHE_ENABLED
  30.436 -// Generate signal that indicates when instruction cache misses are valid
  30.437 -assign icache_read_enable_f =    (valid_f == `TRUE)
  30.438 -                              && (kill_f == `FALSE)
  30.439 -`ifdef CFG_DCACHE_ENABLED
  30.440 -                              && (dcache_restart_request == `FALSE)
  30.441 -`endif                         
  30.442 -`ifdef CFG_IROM_ENABLED 
  30.443 -                              && (irom_select_f == `FALSE)
  30.444 -`endif       
  30.445 -                              ;
  30.446 -`endif
  30.447 -
  30.448 -// Compute address of next instruction to fetch
  30.449 -always @(*)
  30.450 -begin
  30.451 -    // The request from the latest pipeline stage must take priority
  30.452 -`ifdef CFG_DCACHE_ENABLED
  30.453 -    if (dcache_restart_request == `TRUE)
  30.454 -        pc_a = restart_address;
  30.455 -    else 
  30.456 -`endif    
  30.457 -      if (branch_taken_m == `TRUE)
  30.458 -	if ((branch_mispredict_taken_m == `TRUE) && (exception_m == `FALSE))
  30.459 -	  pc_a = pc_x;
  30.460 -	else
  30.461 -          pc_a = branch_target_m;
  30.462 -`ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
  30.463 -      else if (branch_taken_x == `TRUE)
  30.464 -        pc_a = branch_target_x;
  30.465 -`endif
  30.466 -      else
  30.467 -	if ( (valid_d == `TRUE) && (branch_predict_taken_d == `TRUE) )
  30.468 -	  pc_a = branch_predict_address_d;
  30.469 -	else
  30.470 -`ifdef CFG_ICACHE_ENABLED
  30.471 -          if (icache_restart_request == `TRUE)
  30.472 -            pc_a = restart_address;
  30.473 -	  else 
  30.474 -`endif        
  30.475 -            pc_a = pc_f + 1'b1;
  30.476 -end
  30.477 -
  30.478 -// Select where instruction should be fetched from
  30.479 -`ifdef CFG_IROM_ENABLED
  30.480 -assign irom_select_a = ({pc_a, 2'b00} >= `CFG_IROM_BASE_ADDRESS) && ({pc_a, 2'b00} <= `CFG_IROM_LIMIT);
  30.481 -`endif
  30.482 -                     
  30.483 -// Select instruction from selected source
  30.484 -`ifdef CFG_ICACHE_ENABLED
  30.485 -`ifdef CFG_IROM_ENABLED
  30.486 -assign instruction_f = irom_select_f == `TRUE ? irom_data_f : icache_data_f;
  30.487 -`else
  30.488 -assign instruction_f = icache_data_f;
  30.489 -`endif
  30.490 -`else
  30.491 -`ifdef CFG_IROM_ENABLED
  30.492 -`ifdef CFG_IWB_ENABLED
  30.493 -assign instruction_f = irom_select_f == `TRUE ? irom_data_f : wb_data_f;
  30.494 -`else
  30.495 -assign instruction_f = irom_data_f;
  30.496 -`endif
  30.497 -`else
  30.498 -assign instruction_f = wb_data_f;
  30.499 -`endif
  30.500 -`endif
  30.501 -
  30.502 -// Unused/constant Wishbone signals
  30.503 -`ifdef CFG_IWB_ENABLED
  30.504 -`ifdef CFG_HW_DEBUG_ENABLED
  30.505 -`else
  30.506 -assign i_dat_o = 32'd0;
  30.507 -assign i_we_o = `FALSE;
  30.508 -assign i_sel_o = 4'b1111;
  30.509 -`endif
  30.510 -assign i_bte_o = `LM32_BTYPE_LINEAR;
  30.511 -`endif
  30.512 -
  30.513 -`ifdef CFG_ICACHE_ENABLED
  30.514 -// Determine parameters for next cache refill Wishbone access                
  30.515 -generate
  30.516 -    case (bytes_per_line)
  30.517 -    4:
  30.518 -    begin
  30.519 -assign first_cycle_type = `LM32_CTYPE_END;
  30.520 -assign next_cycle_type = `LM32_CTYPE_END;
  30.521 -assign last_word = `TRUE;
  30.522 -assign first_address = icache_refill_address;
  30.523 -    end
  30.524 -    8:
  30.525 -    begin
  30.526 -assign first_cycle_type = `LM32_CTYPE_INCREMENTING;
  30.527 -assign next_cycle_type = `LM32_CTYPE_END;
  30.528 -assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 1'b1;
  30.529 -assign first_address = {icache_refill_address[`LM32_PC_WIDTH+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
  30.530 -    end
  30.531 -    16:
  30.532 -    begin
  30.533 -assign first_cycle_type = `LM32_CTYPE_INCREMENTING;
  30.534 -assign next_cycle_type = i_adr_o[addr_offset_msb] == 1'b1 ? `LM32_CTYPE_END : `LM32_CTYPE_INCREMENTING;
  30.535 -assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 2'b11;
  30.536 -assign first_address = {icache_refill_address[`LM32_PC_WIDTH+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
  30.537 -    end
  30.538 -    endcase
  30.539 -endgenerate
  30.540 -`endif
  30.541 -                     
  30.542 -/////////////////////////////////////////////////////
  30.543 -// Sequential Logic
  30.544 -/////////////////////////////////////////////////////
  30.545 -
  30.546 -// PC 
  30.547 -always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  30.548 -begin
  30.549 -    if (rst_i == `TRUE)
  30.550 -    begin
  30.551 -        pc_f <= (`CFG_EBA_RESET-4)/4;
  30.552 -        pc_d <= {`LM32_PC_WIDTH{1'b0}};
  30.553 -        pc_x <= {`LM32_PC_WIDTH{1'b0}};
  30.554 -        pc_m <= {`LM32_PC_WIDTH{1'b0}};
  30.555 -        pc_w <= {`LM32_PC_WIDTH{1'b0}};
  30.556 -    end
  30.557 -    else
  30.558 -    begin
  30.559 -        if (stall_f == `FALSE)
  30.560 -            pc_f <= pc_a;
  30.561 -        if (stall_d == `FALSE)
  30.562 -            pc_d <= pc_f;
  30.563 -        if (stall_x == `FALSE)
  30.564 -            pc_x <= pc_d;
  30.565 -        if (stall_m == `FALSE)
  30.566 -            pc_m <= pc_x;
  30.567 -        pc_w <= pc_m;
  30.568 -    end
  30.569 -end
  30.570 -
  30.571 -`ifdef LM32_CACHE_ENABLED
  30.572 -// Address to restart from after a cache miss has been handled
  30.573 -always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  30.574 -begin
  30.575 -    if (rst_i == `TRUE)
  30.576 -        restart_address <= {`LM32_PC_WIDTH{1'b0}};
  30.577 -    else
  30.578 -    begin
  30.579 -`ifdef CFG_DCACHE_ENABLED
  30.580 -`ifdef CFG_ICACHE_ENABLED        
  30.581 -            // D-cache restart address must take priority, otherwise instructions will be lost
  30.582 -            if (dcache_refill_request == `TRUE)
  30.583 -                restart_address <= pc_w;
  30.584 -            else if ((icache_refill_request == `TRUE) && (!dcache_refilling) && (!dcache_restart_request))
  30.585 -                restart_address <= icache_refill_address;
  30.586 -`else
  30.587 -            if (dcache_refill_request == `TRUE)
  30.588 -                restart_address <= pc_w;
  30.589 -`endif
  30.590 -`else
  30.591 -`ifdef CFG_ICACHE_ENABLED        
  30.592 -            if (icache_refill_request == `TRUE)
  30.593 -                restart_address <= icache_refill_address;
  30.594 -`endif
  30.595 -`endif
  30.596 -    end
  30.597 -end
  30.598 -`endif
  30.599 -
  30.600 -// Record where instruction was fetched from
  30.601 -`ifdef CFG_IROM_ENABLED
  30.602 -always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  30.603 -begin
  30.604 -    if (rst_i == `TRUE)
  30.605 -        irom_select_f <= `FALSE;
  30.606 -    else
  30.607 -    begin
  30.608 -        if (stall_f == `FALSE)
  30.609 -            irom_select_f <= irom_select_a;
  30.610 -    end
  30.611 -end
  30.612 -`endif
  30.613 -
  30.614 -`ifdef CFG_HW_DEBUG_ENABLED
  30.615 -assign jtag_access_complete = (i_cyc_o == `TRUE) && ((i_ack_i == `TRUE) || (i_err_i == `TRUE)) && (jtag_access == `TRUE);
  30.616 -always @(*)
  30.617 -begin
  30.618 -    case (jtag_address[1:0])
  30.619 -    2'b00: jtag_read_data = i_dat_i[`LM32_BYTE_3_RNG];
  30.620 -    2'b01: jtag_read_data = i_dat_i[`LM32_BYTE_2_RNG];
  30.621 -    2'b10: jtag_read_data = i_dat_i[`LM32_BYTE_1_RNG];
  30.622 -    2'b11: jtag_read_data = i_dat_i[`LM32_BYTE_0_RNG];
  30.623 -    endcase 
  30.624 -end
  30.625 -`endif
  30.626 -
  30.627 -`ifdef CFG_IWB_ENABLED
  30.628 -// Instruction Wishbone interface
  30.629 -`ifdef CFG_ICACHE_ENABLED                
  30.630 -always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  30.631 -begin
  30.632 -    if (rst_i == `TRUE)
  30.633 -    begin
  30.634 -        i_cyc_o <= `FALSE;
  30.635 -        i_stb_o <= `FALSE;
  30.636 -        i_adr_o <= {`LM32_WORD_WIDTH{1'b0}};
  30.637 -        i_cti_o <= `LM32_CTYPE_END;
  30.638 -        i_lock_o <= `FALSE;
  30.639 -        icache_refill_data <= {`LM32_INSTRUCTION_WIDTH{1'b0}};
  30.640 -        icache_refill_ready <= `FALSE;
  30.641 -`ifdef CFG_BUS_ERRORS_ENABLED
  30.642 -        bus_error_f <= `FALSE;
  30.643 -`endif
  30.644 -`ifdef CFG_HW_DEBUG_ENABLED
  30.645 -        i_we_o <= `FALSE;
  30.646 -        i_sel_o <= 4'b1111;
  30.647 -        jtag_access <= `FALSE;
  30.648 -`endif
  30.649 -    end
  30.650 -    else
  30.651 -    begin   
  30.652 -        icache_refill_ready <= `FALSE;
  30.653 -        // Is a cycle in progress?
  30.654 -        if (i_cyc_o == `TRUE)
  30.655 -        begin
  30.656 -            // Has cycle completed?
  30.657 -            if ((i_ack_i == `TRUE) || (i_err_i == `TRUE))
  30.658 -            begin
  30.659 -`ifdef CFG_HW_DEBUG_ENABLED
  30.660 -                if (jtag_access == `TRUE)
  30.661 -                begin
  30.662 -                    i_cyc_o <= `FALSE;
  30.663 -                    i_stb_o <= `FALSE;       
  30.664 -                    i_we_o <= `FALSE;  
  30.665 -                    jtag_access <= `FALSE;    
  30.666 -                end
  30.667 -                else
  30.668 -`endif
  30.669 -                begin
  30.670 -                    if (last_word == `TRUE)
  30.671 -                    begin
  30.672 -                        // Cache line fill complete 
  30.673 -                        i_cyc_o <= `FALSE;
  30.674 -                        i_stb_o <= `FALSE;
  30.675 -                        i_lock_o <= `FALSE;
  30.676 -                    end
  30.677 -                    // Fetch next word in cache line
  30.678 -                    i_adr_o[addr_offset_msb:addr_offset_lsb] <= i_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
  30.679 -                    i_cti_o <= next_cycle_type;
  30.680 -                    // Write fetched data into instruction cache
  30.681 -                    icache_refill_ready <= `TRUE;
  30.682 -                    icache_refill_data <= i_dat_i;
  30.683 -                end
  30.684 -            end
  30.685 -`ifdef CFG_BUS_ERRORS_ENABLED
  30.686 -            if (i_err_i == `TRUE)
  30.687 -            begin
  30.688 -                bus_error_f <= `TRUE;
  30.689 -                $display ("Instruction bus error. Address: %x", i_adr_o);
  30.690 -            end
  30.691 -`endif
  30.692 -        end
  30.693 -        else
  30.694 -        begin
  30.695 -            if ((icache_refill_request == `TRUE) && (icache_refill_ready == `FALSE))
  30.696 -            begin
  30.697 -                // Read first word of cache line
  30.698 -`ifdef CFG_HW_DEBUG_ENABLED     
  30.699 -                i_sel_o <= 4'b1111;
  30.700 -`endif
  30.701 -                i_adr_o <= {first_address, 2'b00};
  30.702 -                i_cyc_o <= `TRUE;
  30.703 -                i_stb_o <= `TRUE;                
  30.704 -                i_cti_o <= first_cycle_type;
  30.705 -                //i_lock_o <= `TRUE;
  30.706 -`ifdef CFG_BUS_ERRORS_ENABLED
  30.707 -                bus_error_f <= `FALSE;
  30.708 -`endif
  30.709 -            end
  30.710 -`ifdef CFG_HW_DEBUG_ENABLED
  30.711 -            else
  30.712 -            begin
  30.713 -                if ((jtag_read_enable == `TRUE) || (jtag_write_enable == `TRUE))
  30.714 -                begin
  30.715 -                    case (jtag_address[1:0])
  30.716 -                    2'b00: i_sel_o <= 4'b1000;
  30.717 -                    2'b01: i_sel_o <= 4'b0100;
  30.718 -                    2'b10: i_sel_o <= 4'b0010;
  30.719 -                    2'b11: i_sel_o <= 4'b0001;
  30.720 -                    endcase
  30.721 -                    i_adr_o <= jtag_address;
  30.722 -                    i_dat_o <= {4{jtag_write_data}};
  30.723 -                    i_cyc_o <= `TRUE;
  30.724 -                    i_stb_o <= `TRUE;
  30.725 -                    i_we_o <= jtag_write_enable;
  30.726 -                    i_cti_o <= `LM32_CTYPE_END;
  30.727 -                    jtag_access <= `TRUE;
  30.728 -                end
  30.729 -            end 
  30.730 -`endif                    
  30.731 -`ifdef CFG_BUS_ERRORS_ENABLED
  30.732 -            // Clear bus error when exception taken, otherwise they would be 
  30.733 -            // continually generated if exception handler is cached
  30.734 -`ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
  30.735 -            if (branch_taken_x == `TRUE)
  30.736 -                bus_error_f <= `FALSE;
  30.737 -`endif
  30.738 -            if (branch_taken_m == `TRUE)
  30.739 -                bus_error_f <= `FALSE;
  30.740 -`endif
  30.741 -        end
  30.742 -    end
  30.743 -end
  30.744 -`else
  30.745 -always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  30.746 -begin
  30.747 -    if (rst_i == `TRUE)
  30.748 -    begin
  30.749 -        i_cyc_o <= `FALSE;
  30.750 -        i_stb_o <= `FALSE;
  30.751 -        i_adr_o <= {`LM32_WORD_WIDTH{1'b0}};
  30.752 -        i_cti_o <= `LM32_CTYPE_END;
  30.753 -        i_lock_o <= `FALSE;
  30.754 -        wb_data_f <= {`LM32_INSTRUCTION_WIDTH{1'b0}};
  30.755 -`ifdef CFG_BUS_ERRORS_ENABLED
  30.756 -        bus_error_f <= `FALSE;
  30.757 -`endif
  30.758 -    end
  30.759 -    else
  30.760 -    begin   
  30.761 -        // Is a cycle in progress?
  30.762 -        if (i_cyc_o == `TRUE)
  30.763 -        begin
  30.764 -            // Has cycle completed?
  30.765 -            if((i_ack_i == `TRUE) || (i_err_i == `TRUE))
  30.766 -            begin
  30.767 -                // Cycle complete
  30.768 -                i_cyc_o <= `FALSE;
  30.769 -                i_stb_o <= `FALSE;
  30.770 -                // Register fetched instruction
  30.771 -                wb_data_f <= i_dat_i;
  30.772 -            end
  30.773 -`ifdef CFG_BUS_ERRORS_ENABLED
  30.774 -            if (i_err_i == `TRUE)
  30.775 -            begin
  30.776 -                bus_error_f <= `TRUE;
  30.777 -                $display ("Instruction bus error. Address: %x", i_adr_o);
  30.778 -            end
  30.779 -`endif
  30.780 -        end
  30.781 -        else
  30.782 -        begin
  30.783 -            // Wait for an instruction fetch from an external address 
  30.784 -            if (   (stall_a == `FALSE) 
  30.785 -`ifdef CFG_IROM_ENABLED 
  30.786 -                && (irom_select_a == `FALSE)
  30.787 -`endif       
  30.788 -               )
  30.789 -            begin
  30.790 -                // Fetch instruction
  30.791 -`ifdef CFG_HW_DEBUG_ENABLED     
  30.792 -                i_sel_o <= 4'b1111;
  30.793 -`endif
  30.794 -                i_adr_o <= {pc_a, 2'b00};
  30.795 -                i_cyc_o <= `TRUE;
  30.796 -                i_stb_o <= `TRUE;
  30.797 -`ifdef CFG_BUS_ERRORS_ENABLED
  30.798 -                bus_error_f <= `FALSE;
  30.799 -`endif
  30.800 -            end
  30.801 -	    else
  30.802 -	    begin
  30.803 -	        if (   (stall_a == `FALSE) 
  30.804 -`ifdef CFG_IROM_ENABLED 
  30.805 -		    && (irom_select_a == `TRUE)
  30.806 -`endif       
  30.807 -	           )
  30.808 -		begin
  30.809 -`ifdef CFG_BUS_ERRORS_ENABLED
  30.810 -		    bus_error_f <= `FALSE;
  30.811 -`endif
  30.812 -		end
  30.813 -	    end
  30.814 -        end
  30.815 -    end
  30.816 -end
  30.817 -`endif
  30.818 -`endif
  30.819 -
  30.820 -// Instruction register
  30.821 -always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  30.822 -begin
  30.823 -    if (rst_i == `TRUE)
  30.824 -    begin
  30.825 -        instruction_d <= {`LM32_INSTRUCTION_WIDTH{1'b0}};
  30.826 -`ifdef CFG_BUS_ERRORS_ENABLED
  30.827 -        bus_error_d <= `FALSE;
  30.828 -`endif
  30.829 -    end
  30.830 -    else
  30.831 -    begin
  30.832 -        if (stall_d == `FALSE)
  30.833 -        begin
  30.834 -            instruction_d <= instruction_f;
  30.835 -`ifdef CFG_BUS_ERRORS_ENABLED
  30.836 -            bus_error_d <= bus_error_f;
  30.837 -`endif
  30.838 -        end
  30.839 -    end
  30.840 -end  
  30.841 -  
  30.842 -endmodule

    31.1 --- a/lm32_interrupt.v	Sun Mar 06 21:17:31 2011 +0000
    31.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    31.3 @@ -1,335 +0,0 @@
    31.4 -// =============================================================================
    31.5 -//                           COPYRIGHT NOTICE
    31.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation
    31.7 -// ALL RIGHTS RESERVED
    31.8 -// This confidential and proprietary software may be used only as authorised by
    31.9 -// a licensing agreement from Lattice Semiconductor Corporation.
   31.10 -// The entire notice above must be reproduced on all authorized copies and
   31.11 -// copies may only be made to the extent permitted by a licensing agreement from
   31.12 -// Lattice Semiconductor Corporation.
   31.13 -//
   31.14 -// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
   31.15 -// 5555 NE Moore Court                            408-826-6000 (other locations)
   31.16 -// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
   31.17 -// U.S.A                                   email: techsupport@latticesemi.com
   31.18 -// =============================================================================/
   31.19 -//                         FILE DETAILS
   31.20 -// Project          : LatticeMico32
   31.21 -// File             : lm32_interrupt.v
   31.22 -// Title            : Interrupt logic
   31.23 -// Dependencies     : lm32_include.v
   31.24 -// Version          : 6.1.17
   31.25 -//                  : Initial Release
   31.26 -// Version          : 7.0SP2, 3.0
   31.27 -//                  : No Change
   31.28 -// Version          : 3.1
   31.29 -//                  : No Change
   31.30 -// =============================================================================
   31.31 -
   31.32 -`include "lm32_include.v"
   31.33 -
   31.34 -/////////////////////////////////////////////////////
   31.35 -// Module interface
   31.36 -/////////////////////////////////////////////////////
   31.37 -
   31.38 -module lm32_interrupt (
   31.39 -    // ----- Inputs -------
   31.40 -    clk_i, 
   31.41 -    rst_i,
   31.42 -    // From external devices
   31.43 -    interrupt,
   31.44 -    // From pipeline
   31.45 -    stall_x,
   31.46 -`ifdef CFG_DEBUG_ENABLED
   31.47 -    non_debug_exception,
   31.48 -    debug_exception,
   31.49 -`else
   31.50 -    exception,
   31.51 -`endif
   31.52 -    eret_q_x,
   31.53 -`ifdef CFG_DEBUG_ENABLED
   31.54 -    bret_q_x,
   31.55 -`endif
   31.56 -    csr,
   31.57 -    csr_write_data,
   31.58 -    csr_write_enable,
   31.59 -    // ----- Outputs -------
   31.60 -    interrupt_exception,
   31.61 -    // To pipeline
   31.62 -    csr_read_data
   31.63 -    );
   31.64 -
   31.65 -/////////////////////////////////////////////////////
   31.66 -// Parameters
   31.67 -/////////////////////////////////////////////////////
   31.68 -
   31.69 -parameter interrupts = `CFG_INTERRUPTS;         // Number of interrupts
   31.70 -
   31.71 -/////////////////////////////////////////////////////
   31.72 -// Inputs
   31.73 -/////////////////////////////////////////////////////
   31.74 -
   31.75 -input clk_i;                                    // Clock
   31.76 -input rst_i;                                    // Reset
   31.77 -
   31.78 -input [interrupts-1:0] interrupt;               // Interrupt pins, active-low
   31.79 -
   31.80 -input stall_x;                                  // Stall X pipeline stage
   31.81 -
   31.82 -`ifdef CFG_DEBUG_ENABLED
   31.83 -input non_debug_exception;                      // Non-debug related exception has been raised
   31.84 -input debug_exception;                          // Debug-related exception has been raised
   31.85 -`else
   31.86 -input exception;                                // Exception has been raised
   31.87 -`endif
   31.88 -input eret_q_x;                                 // Return from exception 
   31.89 -`ifdef CFG_DEBUG_ENABLED
   31.90 -input bret_q_x;                                 // Return from breakpoint 
   31.91 -`endif
   31.92 -
   31.93 -input [`LM32_CSR_RNG] csr;                      // CSR read/write index
   31.94 -input [`LM32_WORD_RNG] csr_write_data;          // Data to write to specified CSR
   31.95 -input csr_write_enable;                         // CSR write enable
   31.96 -
   31.97 -/////////////////////////////////////////////////////
   31.98 -// Outputs
   31.99 -/////////////////////////////////////////////////////
  31.100 -
  31.101 -output interrupt_exception;                     // Request to raide an interrupt exception
  31.102 -wire   interrupt_exception;
  31.103 -
  31.104 -output [`LM32_WORD_RNG] csr_read_data;          // Data read from CSR
  31.105 -reg    [`LM32_WORD_RNG] csr_read_data;
  31.106 -
  31.107 -/////////////////////////////////////////////////////
  31.108 -// Internal nets and registers 
  31.109 -/////////////////////////////////////////////////////
  31.110 -
  31.111 -wire [interrupts-1:0] asserted;                 // Which interrupts are currently being asserted
  31.112 -//pragma attribute asserted preserve_signal true
  31.113 -wire [interrupts-1:0] interrupt_n_exception;
  31.114 -
  31.115 -// Interrupt CSRs
  31.116 -
  31.117 -reg ie;                                         // Interrupt enable
  31.118 -reg eie;                                        // Exception interrupt enable
  31.119 -`ifdef CFG_DEBUG_ENABLED
  31.120 -reg bie;                                        // Breakpoint interrupt enable
  31.121 -`endif
  31.122 -reg [interrupts-1:0] ip;                        // Interrupt pending
  31.123 -reg [interrupts-1:0] im;                        // Interrupt mask
  31.124 -
  31.125 -/////////////////////////////////////////////////////
  31.126 -// Combinational Logic
  31.127 -/////////////////////////////////////////////////////
  31.128 -
  31.129 -// Determine which interrupts have occured and are unmasked
  31.130 -assign interrupt_n_exception = ip & im;
  31.131 -
  31.132 -// Determine if any unmasked interrupts have occured
  31.133 -assign interrupt_exception = (|interrupt_n_exception) & ie;
  31.134 -
  31.135 -// Determine which interrupts are currently being asserted (active-low) or are already pending
  31.136 -assign asserted = ip | interrupt;
  31.137 -       
  31.138 -assign ie_csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}}, 
  31.139 -`ifdef CFG_DEBUG_ENABLED
  31.140 -                           bie,
  31.141 -`else
  31.142 -                           1'b0,
  31.143 -`endif                             
  31.144 -                           eie, 
  31.145 -                           ie
  31.146 -                          };
  31.147 -assign ip_csr_read_data = ip;
  31.148 -assign im_csr_read_data = im;
  31.149 -generate
  31.150 -    if (interrupts > 1) 
  31.151 -    begin
  31.152 -// CSR read
  31.153 -always @(*)
  31.154 -begin
  31.155 -    case (csr)
  31.156 -    `LM32_CSR_IE:  csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}}, 
  31.157 -`ifdef CFG_DEBUG_ENABLED
  31.158 -                                    bie,
  31.159 -`else
  31.160 -                                    1'b0,                                     
  31.161 -`endif
  31.162 -                                    eie, 
  31.163 -                                    ie
  31.164 -                                   };
  31.165 -    `LM32_CSR_IP:  csr_read_data = ip;
  31.166 -    `LM32_CSR_IM:  csr_read_data = im;
  31.167 -    default:       csr_read_data = {`LM32_WORD_WIDTH{1'bx}};
  31.168 -    endcase
  31.169 -end
  31.170 -    end
  31.171 -    else
  31.172 -    begin
  31.173 -// CSR read
  31.174 -always @(*)
  31.175 -begin
  31.176 -    case (csr)
  31.177 -    `LM32_CSR_IE:  csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}}, 
  31.178 -`ifdef CFG_DEBUG_ENABLED
  31.179 -                                    bie, 
  31.180 -`else
  31.181 -                                    1'b0,                                    
  31.182 -`endif
  31.183 -                                    eie, 
  31.184 -                                    ie
  31.185 -                                   };
  31.186 -    `LM32_CSR_IP:  csr_read_data = ip;
  31.187 -    default:       csr_read_data = {`LM32_WORD_WIDTH{1'bx}};
  31.188 -    endcase
  31.189 -end
  31.190 -    end
  31.191 -endgenerate
  31.192 -    
  31.193 -/////////////////////////////////////////////////////
  31.194 -// Sequential Logic
  31.195 -/////////////////////////////////////////////////////
  31.196 -
  31.197 -generate
  31.198 -    if (interrupts > 1)
  31.199 -    begin
  31.200 -// IE, IM, IP - Interrupt Enable, Interrupt Mask and Interrupt Pending CSRs
  31.201 -always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  31.202 -begin
  31.203 -    if (rst_i == `TRUE)
  31.204 -    begin
  31.205 -        ie <= `FALSE;
  31.206 -        eie <= `FALSE;
  31.207 -`ifdef CFG_DEBUG_ENABLED
  31.208 -        bie <= `FALSE;
  31.209 -`endif
  31.210 -        im <= {interrupts{1'b0}};
  31.211 -        ip <= {interrupts{1'b0}};
  31.212 -    end
  31.213 -    else
  31.214 -    begin
  31.215 -        // Set IP bit when interrupt line is asserted
  31.216 -        ip <= asserted;
  31.217 -`ifdef CFG_DEBUG_ENABLED
  31.218 -        if (non_debug_exception == `TRUE)
  31.219 -        begin
  31.220 -            // Save and then clear interrupt enable
  31.221 -            eie <= ie;
  31.222 -            ie <= `FALSE;
  31.223 -        end
  31.224 -        else if (debug_exception == `TRUE)
  31.225 -        begin
  31.226 -            // Save and then clear interrupt enable
  31.227 -            bie <= ie;
  31.228 -            ie <= `FALSE;
  31.229 -        end
  31.230 -`else
  31.231 -        if (exception == `TRUE)
  31.232 -        begin
  31.233 -            // Save and then clear interrupt enable
  31.234 -            eie <= ie;
  31.235 -            ie <= `FALSE;
  31.236 -        end
  31.237 -`endif
  31.238 -        else if (stall_x == `FALSE)
  31.239 -        begin
  31.240 -            if (eret_q_x == `TRUE)
  31.241 -                // Restore interrupt enable
  31.242 -                ie <= eie;          
  31.243 -`ifdef CFG_DEBUG_ENABLED
  31.244 -            else if (bret_q_x == `TRUE)
  31.245 -                // Restore interrupt enable
  31.246 -                ie <= bie;
  31.247 -`endif
  31.248 -            else if (csr_write_enable == `TRUE)
  31.249 -            begin
  31.250 -                // Handle wcsr write
  31.251 -                if (csr == `LM32_CSR_IE)
  31.252 -                begin
  31.253 -                    ie <= csr_write_data[0];
  31.254 -                    eie <= csr_write_data[1];
  31.255 -`ifdef CFG_DEBUG_ENABLED
  31.256 -                    bie <= csr_write_data[2];
  31.257 -`endif
  31.258 -                end
  31.259 -                if (csr == `LM32_CSR_IM)
  31.260 -                    im <= csr_write_data[interrupts-1:0];
  31.261 -                if (csr == `LM32_CSR_IP)
  31.262 -                    ip <= asserted & ~csr_write_data[interrupts-1:0];
  31.263 -            end
  31.264 -        end
  31.265 -    end
  31.266 -end
  31.267 -    end
  31.268 -else
  31.269 -    begin
  31.270 -// IE, IM, IP - Interrupt Enable, Interrupt Mask and Interrupt Pending CSRs
  31.271 -always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  31.272 -begin
  31.273 -    if (rst_i == `TRUE)
  31.274 -    begin
  31.275 -        ie <= `FALSE;
  31.276 -        eie <= `FALSE;
  31.277 -`ifdef CFG_DEBUG_ENABLED
  31.278 -        bie <= `FALSE;
  31.279 -`endif
  31.280 -        ip <= {interrupts{1'b0}};
  31.281 -    end
  31.282 -    else
  31.283 -    begin
  31.284 -        // Set IP bit when interrupt line is asserted
  31.285 -        ip <= asserted;
  31.286 -`ifdef CFG_DEBUG_ENABLED
  31.287 -        if (non_debug_exception == `TRUE)
  31.288 -        begin
  31.289 -            // Save and then clear interrupt enable
  31.290 -            eie <= ie;
  31.291 -            ie <= `FALSE;
  31.292 -        end
  31.293 -        else if (debug_exception == `TRUE)
  31.294 -        begin
  31.295 -            // Save and then clear interrupt enable
  31.296 -            bie <= ie;
  31.297 -            ie <= `FALSE;
  31.298 -        end
  31.299 -`else
  31.300 -        if (exception == `TRUE)
  31.301 -        begin
  31.302 -            // Save and then clear interrupt enable
  31.303 -            eie <= ie;
  31.304 -            ie <= `FALSE;
  31.305 -        end
  31.306 -`endif
  31.307 -        else if (stall_x == `FALSE)
  31.308 -        begin
  31.309 -            if (eret_q_x == `TRUE)
  31.310 -                // Restore interrupt enable
  31.311 -                ie <= eie;          
  31.312 -`ifdef CFG_DEBUG_ENABLED
  31.313 -            else if (bret_q_x == `TRUE)
  31.314 -                // Restore interrupt enable
  31.315 -                ie <= bie;
  31.316 -`endif
  31.317 -            else if (csr_write_enable == `TRUE)
  31.318 -            begin
  31.319 -                // Handle wcsr write
  31.320 -                if (csr == `LM32_CSR_IE)
  31.321 -                begin
  31.322 -                    ie <= csr_write_data[0];
  31.323 -                    eie <= csr_write_data[1];
  31.324 -`ifdef CFG_DEBUG_ENABLED
  31.325 -                    bie <= csr_write_data[2];
  31.326 -`endif
  31.327 -                end
  31.328 -                if (csr == `LM32_CSR_IP)
  31.329 -                    ip <= asserted & ~csr_write_data[interrupts-1:0];
  31.330 -            end
  31.331 -        end
  31.332 -    end
  31.333 -end
  31.334 -    end
  31.335 -endgenerate
  31.336 -
  31.337 -endmodule
  31.338 -

    32.1 --- a/lm32_jtag.v	Sun Mar 06 21:17:31 2011 +0000
    32.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    32.3 @@ -1,469 +0,0 @@
    32.4 -// =============================================================================
    32.5 -//                           COPYRIGHT NOTICE
    32.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation
    32.7 -// ALL RIGHTS RESERVED
    32.8 -// This confidential and proprietary software may be used only as authorised by
    32.9 -// a licensing agreement from Lattice Semiconductor Corporation.
   32.10 -// The entire notice above must be reproduced on all authorized copies and
   32.11 -// copies may only be made to the extent permitted by a licensing agreement from
   32.12 -// Lattice Semiconductor Corporation.
   32.13 -//
   32.14 -// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
   32.15 -// 5555 NE Moore Court                            408-826-6000 (other locations)
   32.16 -// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
   32.17 -// U.S.A                                   email: techsupport@latticesemi.com
   32.18 -// =============================================================================/
   32.19 -//                         FILE DETAILS
   32.20 -// Project          : LatticeMico32
   32.21 -// File             : lm32_jtag.v
   32.22 -// Title            : JTAG interface
   32.23 -// Dependencies     : lm32_include.v
   32.24 -// Version          : 6.1.17
   32.25 -//                  : Initial Release
   32.26 -// Version          : 7.0SP2, 3.0
   32.27 -//                  : No Change
   32.28 -// Version          : 3.1
   32.29 -//                  : No Change
   32.30 -// =============================================================================
   32.31 -
   32.32 -`include "lm32_include.v"
   32.33 -
   32.34 -`ifdef CFG_JTAG_ENABLED
   32.35 -
   32.36 -`define LM32_DP                             3'b000
   32.37 -`define LM32_TX                             3'b001
   32.38 -`define LM32_RX                             3'b010
   32.39 -
   32.40 -// LM32 Debug Protocol commands IDs
   32.41 -`define LM32_DP_RNG                         3:0
   32.42 -`define LM32_DP_READ_MEMORY                 4'b0001
   32.43 -`define LM32_DP_WRITE_MEMORY                4'b0010
   32.44 -`define LM32_DP_READ_SEQUENTIAL             4'b0011
   32.45 -`define LM32_DP_WRITE_SEQUENTIAL            4'b0100
   32.46 -`define LM32_DP_WRITE_CSR                   4'b0101
   32.47 -`define LM32_DP_BREAK                       4'b0110
   32.48 -`define LM32_DP_RESET                       4'b0111
   32.49 -
   32.50 -// States for FSM
   32.51 -`define LM32_JTAG_STATE_RNG                 3:0
   32.52 -`define LM32_JTAG_STATE_READ_COMMAND        4'h0
   32.53 -`define LM32_JTAG_STATE_READ_BYTE_0         4'h1
   32.54 -`define LM32_JTAG_STATE_READ_BYTE_1         4'h2
   32.55 -`define LM32_JTAG_STATE_READ_BYTE_2         4'h3
   32.56 -`define LM32_JTAG_STATE_READ_BYTE_3         4'h4
   32.57 -`define LM32_JTAG_STATE_READ_BYTE_4         4'h5
   32.58 -`define LM32_JTAG_STATE_PROCESS_COMMAND     4'h6
   32.59 -`define LM32_JTAG_STATE_WAIT_FOR_MEMORY     4'h7
   32.60 -`define LM32_JTAG_STATE_WAIT_FOR_CSR        4'h8
   32.61 -
   32.62 -/////////////////////////////////////////////////////
   32.63 -// Module interface
   32.64 -/////////////////////////////////////////////////////
   32.65 -
   32.66 -module lm32_jtag (
   32.67 -    // ----- Inputs -------
   32.68 -    clk_i,
   32.69 -    rst_i,
   32.70 -    jtag_clk, 
   32.71 -    jtag_update,
   32.72 -    jtag_reg_q,
   32.73 -    jtag_reg_addr_q,
   32.74 -`ifdef CFG_JTAG_UART_ENABLED
   32.75 -    csr,
   32.76 -    csr_write_enable,
   32.77 -    csr_write_data,
   32.78 -    stall_x,
   32.79 -`endif
   32.80 -`ifdef CFG_HW_DEBUG_ENABLED
   32.81 -    jtag_read_data,
   32.82 -    jtag_access_complete,
   32.83 -`endif
   32.84 -`ifdef CFG_DEBUG_ENABLED
   32.85 -    exception_q_w,
   32.86 -`endif
   32.87 -    // ----- Outputs -------
   32.88 -`ifdef CFG_JTAG_UART_ENABLED
   32.89 -    jtx_csr_read_data,
   32.90 -    jrx_csr_read_data,
   32.91 -`endif
   32.92 -`ifdef CFG_HW_DEBUG_ENABLED
   32.93 -    jtag_csr_write_enable,
   32.94 -    jtag_csr_write_data,
   32.95 -    jtag_csr,
   32.96 -    jtag_read_enable,
   32.97 -    jtag_write_enable,
   32.98 -    jtag_write_data,
   32.99 -    jtag_address,
  32.100 -`endif
  32.101 -`ifdef CFG_DEBUG_ENABLED
  32.102 -    jtag_break,
  32.103 -    jtag_reset,
  32.104 -`endif
  32.105 -    jtag_reg_d,
  32.106 -    jtag_reg_addr_d
  32.107 -    );
  32.108 -
  32.109 -/////////////////////////////////////////////////////
  32.110 -// Inputs
  32.111 -/////////////////////////////////////////////////////
  32.112 -
  32.113 -input clk_i;                                            // Clock
  32.114 -input rst_i;                                            // Reset
  32.115 -
  32.116 -input jtag_clk;                                         // JTAG clock
  32.117 -input jtag_update;                                      // JTAG data register has been updated
  32.118 -input [`LM32_BYTE_RNG] jtag_reg_q;                      // JTAG data register
  32.119 -input [2:0] jtag_reg_addr_q;                            // JTAG data register
  32.120 -
  32.121 -`ifdef CFG_JTAG_UART_ENABLED
  32.122 -input [`LM32_CSR_RNG] csr;                              // CSR to write
  32.123 -input csr_write_enable;                                 // CSR write enable
  32.124 -input [`LM32_WORD_RNG] csr_write_data;                  // Data to write to specified CSR
  32.125 -input stall_x;                                          // Stall instruction in X stage
  32.126 -`endif
  32.127 -`ifdef CFG_HW_DEBUG_ENABLED
  32.128 -input [`LM32_BYTE_RNG] jtag_read_data;                  // Data read from requested address
  32.129 -input jtag_access_complete;                             // Memory access if complete
  32.130 -`endif
  32.131 -`ifdef CFG_DEBUG_ENABLED
  32.132 -input exception_q_w;                                    // Indicates an exception has occured in W stage
  32.133 -`endif
  32.134 -
  32.135 -/////////////////////////////////////////////////////
  32.136 -// Outputs
  32.137 -/////////////////////////////////////////////////////
  32.138 -       
  32.139 -`ifdef CFG_JTAG_UART_ENABLED
  32.140 -output [`LM32_WORD_RNG] jtx_csr_read_data;              // Value of JTX CSR for rcsr instructions
  32.141 -wire   [`LM32_WORD_RNG] jtx_csr_read_data;
  32.142 -output [`LM32_WORD_RNG] jrx_csr_read_data;              // Value of JRX CSR for rcsr instructions
  32.143 -wire   [`LM32_WORD_RNG] jrx_csr_read_data;
  32.144 -`endif
  32.145 -`ifdef CFG_HW_DEBUG_ENABLED
  32.146 -output jtag_csr_write_enable;                           // CSR write enable
  32.147 -reg    jtag_csr_write_enable;
  32.148 -output [`LM32_WORD_RNG] jtag_csr_write_data;            // Data to write to specified CSR
  32.149 -wire   [`LM32_WORD_RNG] jtag_csr_write_data;
  32.150 -output [`LM32_CSR_RNG] jtag_csr;                        // CSR to write
  32.151 -wire   [`LM32_CSR_RNG] jtag_csr;
  32.152 -output jtag_read_enable;                                // Memory read enable
  32.153 -reg    jtag_read_enable;
  32.154 -output jtag_write_enable;                               // Memory write enable
  32.155 -reg    jtag_write_enable;
  32.156 -output [`LM32_BYTE_RNG] jtag_write_data;                // Data to write to specified address
  32.157 -wire   [`LM32_BYTE_RNG] jtag_write_data;        
  32.158 -output [`LM32_WORD_RNG] jtag_address;                   // Memory read/write address
  32.159 -wire   [`LM32_WORD_RNG] jtag_address;
  32.160 -`endif
  32.161 -`ifdef CFG_DEBUG_ENABLED
  32.162 -output jtag_break;                                      // Request to raise a breakpoint exception
  32.163 -reg    jtag_break;
  32.164 -output jtag_reset;                                      // Request to raise a reset exception
  32.165 -reg    jtag_reset;
  32.166 -`endif
  32.167 -output [`LM32_BYTE_RNG] jtag_reg_d;
  32.168 -reg    [`LM32_BYTE_RNG] jtag_reg_d;
  32.169 -output [2:0] jtag_reg_addr_d;
  32.170 -wire   [2:0] jtag_reg_addr_d;
  32.171 -             
  32.172 -/////////////////////////////////////////////////////
  32.173 -// Internal nets and registers 
  32.174 -/////////////////////////////////////////////////////
  32.175 -
  32.176 -reg rx_update;                          // Clock-domain crossing registers
  32.177 -reg rx_update_r;                        // Registered version of rx_update
  32.178 -reg rx_update_r_r;                      // Registered version of rx_update_r
  32.179 -reg rx_update_r_r_r;                    // Registered version of rx_update_r_r
  32.180 -
  32.181 -// These wires come from the JTAG clock domain.
  32.182 -// They have been held unchanged for an entire JTAG clock cycle before the jtag_update toggle flips
  32.183 -wire [`LM32_BYTE_RNG] rx_byte;   
  32.184 -wire [2:0] rx_addr;
  32.185 -
  32.186 -`ifdef CFG_JTAG_UART_ENABLED                 
  32.187 -reg [`LM32_BYTE_RNG] uart_tx_byte;      // UART TX data
  32.188 -reg uart_tx_valid;                      // TX data is valid
  32.189 -reg [`LM32_BYTE_RNG] uart_rx_byte;      // UART RX data
  32.190 -reg uart_rx_valid;                      // RX data is valid
  32.191 -`endif
  32.192 -
  32.193 -reg [`LM32_DP_RNG] command;             // The last received command
  32.194 -`ifdef CFG_HW_DEBUG_ENABLED
  32.195 -reg [`LM32_BYTE_RNG] jtag_byte_0;       // Registers to hold command paramaters
  32.196 -reg [`LM32_BYTE_RNG] jtag_byte_1;
  32.197 -reg [`LM32_BYTE_RNG] jtag_byte_2;
  32.198 -reg [`LM32_BYTE_RNG] jtag_byte_3;
  32.199 -reg [`LM32_BYTE_RNG] jtag_byte_4;
  32.200 -reg processing;                         // Indicates if we're still processing a memory read/write
  32.201 -`endif
  32.202 -
  32.203 -reg [`LM32_JTAG_STATE_RNG] state;       // Current state of FSM
  32.204 -
  32.205 -/////////////////////////////////////////////////////
  32.206 -// Combinational Logic
  32.207 -/////////////////////////////////////////////////////
  32.208 -
  32.209 -`ifdef CFG_HW_DEBUG_ENABLED
  32.210 -assign jtag_csr_write_data = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
  32.211 -assign jtag_csr = jtag_byte_4[`LM32_CSR_RNG];
  32.212 -assign jtag_address = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
  32.213 -assign jtag_write_data = jtag_byte_4;
  32.214 -`endif
  32.215 -                 
  32.216 -// Generate status flags for reading via the JTAG interface                 
  32.217 -`ifdef CFG_JTAG_UART_ENABLED                 
  32.218 -assign jtag_reg_addr_d[1:0] = {uart_rx_valid, uart_tx_valid};         
  32.219 -`else
  32.220 -assign jtag_reg_addr_d[1:0] = 2'b00;
  32.221 -`endif
  32.222 -`ifdef CFG_HW_DEBUG_ENABLED
  32.223 -assign jtag_reg_addr_d[2] = processing;
  32.224 -`else
  32.225 -assign jtag_reg_addr_d[2] = 1'b0;
  32.226 -`endif
  32.227 -
  32.228 -`ifdef CFG_JTAG_UART_ENABLED                 
  32.229 -assign jtx_csr_read_data = {{`LM32_WORD_WIDTH-9{1'b0}}, uart_tx_valid, 8'h00};
  32.230 -assign jrx_csr_read_data = {{`LM32_WORD_WIDTH-9{1'b0}}, uart_rx_valid, uart_rx_byte};
  32.231 -`endif         
  32.232 -                 
  32.233 -/////////////////////////////////////////////////////
  32.234 -// Sequential Logic
  32.235 -/////////////////////////////////////////////////////
  32.236 -
  32.237 -assign rx_byte = jtag_reg_q;
  32.238 -assign rx_addr = jtag_reg_addr_q;
  32.239 -
  32.240 -// The JTAG latched jtag_reg[_addr]_q at least one JTCK before jtag_update is raised
  32.241 -// Thus, they are stable (and safe to sample) when jtag_update is high
  32.242 -always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  32.243 -begin
  32.244 -    if (rst_i == `TRUE)
  32.245 -    begin
  32.246 -        rx_update <= 1'b0;
  32.247 -        rx_update_r <= 1'b0;
  32.248 -        rx_update_r_r <= 1'b0;
  32.249 -        rx_update_r_r_r <= 1'b0;
  32.250 -    end
  32.251 -    else
  32.252 -    begin
  32.253 -        rx_update <= jtag_update;
  32.254 -        rx_update_r <= rx_update;
  32.255 -        rx_update_r_r <= rx_update_r;
  32.256 -        rx_update_r_r_r <= rx_update_r_r;
  32.257 -    end
  32.258 -end
  32.259 -
  32.260 -// LM32 debug protocol state machine
  32.261 -always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  32.262 -begin
  32.263 -    if (rst_i == `TRUE)
  32.264 -    begin
  32.265 -        state <= `LM32_JTAG_STATE_READ_COMMAND;
  32.266 -        command <= 4'b0000;
  32.267 -        jtag_reg_d <= 8'h00;
  32.268 -`ifdef CFG_HW_DEBUG_ENABLED
  32.269 -        processing <= `FALSE;
  32.270 -        jtag_csr_write_enable <= `FALSE;
  32.271 -        jtag_read_enable <= `FALSE;
  32.272 -        jtag_write_enable <= `FALSE;
  32.273 -`endif
  32.274 -`ifdef CFG_DEBUG_ENABLED
  32.275 -        jtag_break <= `FALSE;
  32.276 -        jtag_reset <= `FALSE;
  32.277 -`endif
  32.278 -`ifdef CFG_JTAG_UART_ENABLED                 
  32.279 -        uart_tx_byte <= 8'h00;
  32.280 -        uart_tx_valid <= `FALSE;
  32.281 -        uart_rx_byte <= 8'h00;
  32.282 -        uart_rx_valid <= `FALSE;
  32.283 -`endif
  32.284 -    end
  32.285 -    else
  32.286 -    begin
  32.287 -`ifdef CFG_JTAG_UART_ENABLED                 
  32.288 -        if ((csr_write_enable == `TRUE) && (stall_x == `FALSE))
  32.289 -        begin
  32.290 -            case (csr)
  32.291 -            `LM32_CSR_JTX:
  32.292 -            begin
  32.293 -                // Set flag indicating data is available
  32.294 -                uart_tx_byte <= csr_write_data[`LM32_BYTE_0_RNG];
  32.295 -                uart_tx_valid <= `TRUE;
  32.296 -            end
  32.297 -            `LM32_CSR_JRX:
  32.298 -            begin
  32.299 -                // Clear flag indidicating data has been received
  32.300 -                uart_rx_valid <= `FALSE;
  32.301 -            end
  32.302 -            endcase
  32.303 -        end
  32.304 -`endif
  32.305 -`ifdef CFG_DEBUG_ENABLED
  32.306 -        // When an exception has occured, clear the requests
  32.307 -        if (exception_q_w == `TRUE)
  32.308 -        begin
  32.309 -            jtag_break <= `FALSE;
  32.310 -            jtag_reset <= `FALSE;
  32.311 -        end
  32.312 -`endif
  32.313 -        case (state)
  32.314 -        `LM32_JTAG_STATE_READ_COMMAND:
  32.315 -        begin
  32.316 -            // Wait for rx register to toggle which indicates new data is available
  32.317 -            if ((~rx_update_r_r_r & rx_update_r_r) == `TRUE)
  32.318 -            begin
  32.319 -                command <= rx_byte[7:4];                
  32.320 -                case (rx_addr)
  32.321 -`ifdef CFG_DEBUG_ENABLED
  32.322 -                `LM32_DP:
  32.323 -                begin
  32.324 -                    case (rx_byte[7:4])
  32.325 -`ifdef CFG_HW_DEBUG_ENABLED
  32.326 -                    `LM32_DP_READ_MEMORY:
  32.327 -                        state <= `LM32_JTAG_STATE_READ_BYTE_0;
  32.328 -                    `LM32_DP_READ_SEQUENTIAL:
  32.329 -                    begin
  32.330 -                        {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
  32.331 -                        state <= `LM32_JTAG_STATE_PROCESS_COMMAND;
  32.332 -                    end
  32.333 -                    `LM32_DP_WRITE_MEMORY:
  32.334 -                        state <= `LM32_JTAG_STATE_READ_BYTE_0;
  32.335 -                    `LM32_DP_WRITE_SEQUENTIAL:
  32.336 -                    begin
  32.337 -                        {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
  32.338 -                        state <= 5;
  32.339 -                    end
  32.340 -                    `LM32_DP_WRITE_CSR:
  32.341 -                        state <= `LM32_JTAG_STATE_READ_BYTE_0;
  32.342 -`endif                    
  32.343 -                    `LM32_DP_BREAK:
  32.344 -                    begin
  32.345 -`ifdef CFG_JTAG_UART_ENABLED     
  32.346 -                        uart_rx_valid <= `FALSE;    
  32.347 -                        uart_tx_valid <= `FALSE;         
  32.348 -`endif
  32.349 -                        jtag_break <= `TRUE;
  32.350 -                    end
  32.351 -                    `LM32_DP_RESET:
  32.352 -                    begin
  32.353 -`ifdef CFG_JTAG_UART_ENABLED     
  32.354 -                        uart_rx_valid <= `FALSE;    
  32.355 -                        uart_tx_valid <= `FALSE;         
  32.356 -`endif
  32.357 -                        jtag_reset <= `TRUE;
  32.358 -                    end
  32.359 -                    endcase                               
  32.360 -                end
  32.361 -`endif
  32.362 -`ifdef CFG_JTAG_UART_ENABLED                 
  32.363 -                `LM32_TX:
  32.364 -                begin
  32.365 -                    uart_rx_byte <= rx_byte;
  32.366 -                    uart_rx_valid <= `TRUE;
  32.367 -                end                    
  32.368 -                `LM32_RX:
  32.369 -                begin
  32.370 -                    jtag_reg_d <= uart_tx_byte;
  32.371 -                    uart_tx_valid <= `FALSE;
  32.372 -                end
  32.373 -`endif
  32.374 -                default:
  32.375 -                    ;
  32.376 -                endcase                
  32.377 -            end
  32.378 -        end
  32.379 -`ifdef CFG_HW_DEBUG_ENABLED
  32.380 -        `LM32_JTAG_STATE_READ_BYTE_0:
  32.381 -        begin
  32.382 -            if ((~rx_update_r_r_r & rx_update_r_r) == `TRUE)
  32.383 -            begin
  32.384 -                jtag_byte_0 <= rx_byte;
  32.385 -                state <= `LM32_JTAG_STATE_READ_BYTE_1;
  32.386 -            end
  32.387 -        end
  32.388 -        `LM32_JTAG_STATE_READ_BYTE_1:
  32.389 -        begin
  32.390 -            if ((~rx_update_r_r_r & rx_update_r_r) == `TRUE)
  32.391 -            begin
  32.392 -                jtag_byte_1 <= rx_byte;
  32.393 -                state <= `LM32_JTAG_STATE_READ_BYTE_2;
  32.394 -            end
  32.395 -        end
  32.396 -        `LM32_JTAG_STATE_READ_BYTE_2:
  32.397 -        begin
  32.398 -            if ((~rx_update_r_r_r & rx_update_r_r) == `TRUE)
  32.399 -            begin
  32.400 -                jtag_byte_2 <= rx_byte;
  32.401 -                state <= `LM32_JTAG_STATE_READ_BYTE_3;
  32.402 -            end
  32.403 -        end
  32.404 -        `LM32_JTAG_STATE_READ_BYTE_3:
  32.405 -        begin
  32.406 -            if ((~rx_update_r_r_r & rx_update_r_r) == `TRUE)
  32.407 -            begin
  32.408 -                jtag_byte_3 <= rx_byte;
  32.409 -                if (command == `LM32_DP_READ_MEMORY)
  32.410 -                    state <= `LM32_JTAG_STATE_PROCESS_COMMAND;
  32.411 -                else 
  32.412 -                    state <= `LM32_JTAG_STATE_READ_BYTE_4;
  32.413 -            end
  32.414 -        end
  32.415 -        `LM32_JTAG_STATE_READ_BYTE_4:
  32.416 -        begin
  32.417 -            if ((~rx_update_r_r_r & rx_update_r_r) == `TRUE)
  32.418 -            begin
  32.419 -                jtag_byte_4 <= rx_byte;
  32.420 -                state <= `LM32_JTAG_STATE_PROCESS_COMMAND;
  32.421 -            end
  32.422 -        end
  32.423 -        `LM32_JTAG_STATE_PROCESS_COMMAND:
  32.424 -        begin
  32.425 -            case (command)
  32.426 -            `LM32_DP_READ_MEMORY,
  32.427 -            `LM32_DP_READ_SEQUENTIAL:
  32.428 -            begin
  32.429 -                jtag_read_enable <= `TRUE;
  32.430 -                processing <= `TRUE;
  32.431 -                state <= `LM32_JTAG_STATE_WAIT_FOR_MEMORY;
  32.432 -            end
  32.433 -            `LM32_DP_WRITE_MEMORY,
  32.434 -            `LM32_DP_WRITE_SEQUENTIAL:
  32.435 -            begin
  32.436 -                jtag_write_enable <= `TRUE;
  32.437 -                processing <= `TRUE;
  32.438 -                state <= `LM32_JTAG_STATE_WAIT_FOR_MEMORY;
  32.439 -            end
  32.440 -            `LM32_DP_WRITE_CSR:
  32.441 -            begin
  32.442 -                jtag_csr_write_enable <= `TRUE;
  32.443 -                processing <= `TRUE;
  32.444 -                state <= `LM32_JTAG_STATE_WAIT_FOR_CSR;
  32.445 -            end
  32.446 -            endcase
  32.447 -        end
  32.448 -        `LM32_JTAG_STATE_WAIT_FOR_MEMORY:
  32.449 -        begin
  32.450 -            if (jtag_access_complete == `TRUE)
  32.451 -            begin          
  32.452 -                jtag_read_enable <= `FALSE;
  32.453 -                jtag_reg_d <= jtag_read_data;
  32.454 -                jtag_write_enable <= `FALSE;  
  32.455 -                processing <= `FALSE;
  32.456 -                state <= `LM32_JTAG_STATE_READ_COMMAND;
  32.457 -            end
  32.458 -        end    
  32.459 -        `LM32_JTAG_STATE_WAIT_FOR_CSR:
  32.460 -        begin
  32.461 -            jtag_csr_write_enable <= `FALSE;
  32.462 -            processing <= `FALSE;
  32.463 -            state <= `LM32_JTAG_STATE_READ_COMMAND;
  32.464 -        end    
  32.465 -`endif
  32.466 -        endcase
  32.467 -    end
  32.468 -end
  32.469 -  
  32.470 -endmodule
  32.471 -
  32.472 -`endif

    33.1 --- a/lm32_load_store_unit.v	Sun Mar 06 21:17:31 2011 +0000
    33.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    33.3 @@ -1,806 +0,0 @@
    33.4 -// =============================================================================
    33.5 -//                           COPYRIGHT NOTICE
    33.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation
    33.7 -// ALL RIGHTS RESERVED
    33.8 -// This confidential and proprietary software may be used only as authorised by
    33.9 -// a licensing agreement from Lattice Semiconductor Corporation.
   33.10 -// The entire notice above must be reproduced on all authorized copies and
   33.11 -// copies may only be made to the extent permitted by a licensing agreement from
   33.12 -// Lattice Semiconductor Corporation.
   33.13 -//
   33.14 -// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
   33.15 -// 5555 NE Moore Court                            408-826-6000 (other locations)
   33.16 -// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
   33.17 -// U.S.A                                   email: techsupport@latticesemi.com
   33.18 -// =============================================================================/
   33.19 -//                         FILE DETAILS
   33.20 -// Project      : LatticeMico32
   33.21 -// File         : lm32_load_store_unit.v
   33.22 -// Title        : Load and store unit
   33.23 -// Dependencies : lm32_include.v
   33.24 -// Version      : 6.1.17
   33.25 -//              : Initial Release
   33.26 -// Version      : 7.0SP2, 3.0
   33.27 -//              : No Change
   33.28 -// Version      : 3.1
   33.29 -//              : Instead of disallowing an instruction cache miss on a data cache 
   33.30 -//              : miss, both can now occur at the same time. If both occur at same 
   33.31 -//              : time, then restart address is the address of instruction that 
   33.32 -//              : caused data cache miss.
   33.33 -// Version      : 3.2
   33.34 -//              : EBRs use SYNC resets instead of ASYNC resets.
   33.35 -// Version      : 3.3
   33.36 -//              : Support for new non-cacheable Data Memory that is accessible by 
   33.37 -//              : the data port and has a one cycle access latency.
   33.38 -// Version      : 3.4
   33.39 -//              : No change
   33.40 -// Version      : 3.5
   33.41 -//              : Bug fix: Inline memory is correctly generated if it is not a
   33.42 -//              : power-of-two
   33.43 -// =============================================================================
   33.44 -
   33.45 -`include "lm32_include.v"
   33.46 -
   33.47 -/////////////////////////////////////////////////////
   33.48 -// Module interface
   33.49 -/////////////////////////////////////////////////////
   33.50 -
   33.51 -module lm32_load_store_unit (
   33.52 -    // ----- Inputs -------
   33.53 -    clk_i,
   33.54 -    rst_i,
   33.55 -    // From pipeline
   33.56 -    stall_a,
   33.57 -    stall_x,
   33.58 -    stall_m,
   33.59 -    kill_m,
   33.60 -    exception_m,
   33.61 -    store_operand_x,
   33.62 -    load_store_address_x,
   33.63 -    load_store_address_m,
   33.64 -    load_store_address_w,
   33.65 -    load_x,
   33.66 -    store_x,
   33.67 -    load_q_x,
   33.68 -    store_q_x,
   33.69 -    load_q_m,
   33.70 -    store_q_m,
   33.71 -    sign_extend_x,
   33.72 -    size_x,
   33.73 -`ifdef CFG_DCACHE_ENABLED
   33.74 -    dflush,
   33.75 -`endif
   33.76 -`ifdef CFG_IROM_ENABLED
   33.77 -    irom_data_m,
   33.78 -`endif
   33.79 -    // From Wishbone
   33.80 -    d_dat_i,
   33.81 -    d_ack_i,
   33.82 -    d_err_i,
   33.83 -    d_rty_i,
   33.84 -    // ----- Outputs -------
   33.85 -    // To pipeline
   33.86 -`ifdef CFG_DCACHE_ENABLED
   33.87 -    dcache_refill_request,
   33.88 -    dcache_restart_request,
   33.89 -    dcache_stall_request,
   33.90 -    dcache_refilling,
   33.91 -`endif    
   33.92 -`ifdef CFG_IROM_ENABLED
   33.93 -    irom_store_data_m,
   33.94 -    irom_address_xm,
   33.95 -    irom_we_xm,
   33.96 -    irom_stall_request_x,
   33.97 -`endif			     
   33.98 -    load_data_w,
   33.99 -    stall_wb_load,
  33.100 -    // To Wishbone
  33.101 -    d_dat_o,
  33.102 -    d_adr_o,
  33.103 -    d_cyc_o,
  33.104 -    d_sel_o,
  33.105 -    d_stb_o,
  33.106 -    d_we_o,
  33.107 -    d_cti_o,
  33.108 -    d_lock_o,
  33.109 -    d_bte_o
  33.110 -    );
  33.111 -
  33.112 -/////////////////////////////////////////////////////
  33.113 -// Parameters
  33.114 -/////////////////////////////////////////////////////
  33.115 -
  33.116 -parameter associativity = 1;                            // Associativity of the cache (Number of ways)
  33.117 -parameter sets = 512;                                   // Number of sets
  33.118 -parameter bytes_per_line = 16;                          // Number of bytes per cache line
  33.119 -parameter base_address = 0;                             // Base address of cachable memory
  33.120 -parameter limit = 0;                                    // Limit (highest address) of cachable memory
  33.121 -
  33.122 -// For bytes_per_line == 4, we set 1 so part-select range isn't reversed, even though not really used 
  33.123 -localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2;
  33.124 -localparam addr_offset_lsb = 2;
  33.125 -localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
  33.126 -
  33.127 -/////////////////////////////////////////////////////
  33.128 -// Inputs
  33.129 -/////////////////////////////////////////////////////
  33.130 -
  33.131 -input clk_i;                                            // Clock 
  33.132 -input rst_i;                                            // Reset
  33.133 -
  33.134 -input stall_a;                                          // A stage stall 
  33.135 -input stall_x;                                          // X stage stall        
  33.136 -input stall_m;                                          // M stage stall
  33.137 -input kill_m;                                           // Kill instruction in M stage
  33.138 -input exception_m;                                      // An exception occured in the M stage
  33.139 -
  33.140 -input [`LM32_WORD_RNG] store_operand_x;                 // Data read from register to store
  33.141 -input [`LM32_WORD_RNG] load_store_address_x;            // X stage load/store address
  33.142 -input [`LM32_WORD_RNG] load_store_address_m;            // M stage load/store address
  33.143 -input [1:0] load_store_address_w;                       // W stage load/store address (only least two significant bits are needed)
  33.144 -input load_x;                                           // Load instruction in X stage
  33.145 -input store_x;                                          // Store instruction in X stage
  33.146 -input load_q_x;                                         // Load instruction in X stage
  33.147 -input store_q_x;                                        // Store instruction in X stage
  33.148 -input load_q_m;                                         // Load instruction in M stage
  33.149 -input store_q_m;                                        // Store instruction in M stage
  33.150 -input sign_extend_x;                                    // Whether load instruction in X stage should sign extend or zero extend
  33.151 -input [`LM32_SIZE_RNG] size_x;                          // Size of load or store (byte, hword, word)
  33.152 -
  33.153 -`ifdef CFG_DCACHE_ENABLED
  33.154 -input dflush;                                           // Flush the data cache
  33.155 -`endif
  33.156 -
  33.157 -`ifdef CFG_IROM_ENABLED   
  33.158 -input [`LM32_WORD_RNG] irom_data_m;                     // Data from Instruction-ROM
  33.159 -`endif
  33.160 -
  33.161 -input [`LM32_WORD_RNG] d_dat_i;                         // Data Wishbone interface read data
  33.162 -input d_ack_i;                                          // Data Wishbone interface acknowledgement
  33.163 -input d_err_i;                                          // Data Wishbone interface error
  33.164 -input d_rty_i;                                          // Data Wishbone interface retry
  33.165 -
  33.166 -/////////////////////////////////////////////////////
  33.167 -// Outputs
  33.168 -/////////////////////////////////////////////////////
  33.169 -
  33.170 -`ifdef CFG_DCACHE_ENABLED
  33.171 -output dcache_refill_request;                           // Request to refill data cache
  33.172 -wire   dcache_refill_request;
  33.173 -output dcache_restart_request;                          // Request to restart the instruction that caused a data cache miss
  33.174 -wire   dcache_restart_request;
  33.175 -output dcache_stall_request;                            // Data cache stall request
  33.176 -wire   dcache_stall_request;
  33.177 -output dcache_refilling;
  33.178 -wire   dcache_refilling;
  33.179 -`endif
  33.180 -
  33.181 -`ifdef CFG_IROM_ENABLED   
  33.182 -output irom_store_data_m;                               // Store data to Instruction ROM
  33.183 -wire   [`LM32_WORD_RNG] irom_store_data_m;
  33.184 -output [`LM32_WORD_RNG] irom_address_xm;                // Load/store address to Instruction ROM
  33.185 -wire   [`LM32_WORD_RNG] irom_address_xm;
  33.186 -output irom_we_xm;                                      // Write-enable of 2nd port of Instruction ROM
  33.187 -wire   irom_we_xm;
  33.188 -output irom_stall_request_x;                            // Stall instruction in D stage  
  33.189 -wire   irom_stall_request_x;                            
  33.190 -`endif
  33.191 -   
  33.192 -output [`LM32_WORD_RNG] load_data_w;                    // Result of a load instruction
  33.193 -reg    [`LM32_WORD_RNG] load_data_w;
  33.194 -output stall_wb_load;                                   // Request to stall pipeline due to a load from the Wishbone interface
  33.195 -reg    stall_wb_load;
  33.196 -
  33.197 -output [`LM32_WORD_RNG] d_dat_o;                        // Data Wishbone interface write data
  33.198 -reg    [`LM32_WORD_RNG] d_dat_o;
  33.199 -output [`LM32_WORD_RNG] d_adr_o;                        // Data Wishbone interface address
  33.200 -reg    [`LM32_WORD_RNG] d_adr_o;
  33.201 -output d_cyc_o;                                         // Data Wishbone interface cycle
  33.202 -reg    d_cyc_o;
  33.203 -output [`LM32_BYTE_SELECT_RNG] d_sel_o;                 // Data Wishbone interface byte select
  33.204 -reg    [`LM32_BYTE_SELECT_RNG] d_sel_o;
  33.205 -output d_stb_o;                                         // Data Wishbone interface strobe
  33.206 -reg    d_stb_o; 
  33.207 -output d_we_o;                                          // Data Wishbone interface write enable
  33.208 -reg    d_we_o;
  33.209 -output [`LM32_CTYPE_RNG] d_cti_o;                       // Data Wishbone interface cycle type 
  33.210 -reg    [`LM32_CTYPE_RNG] d_cti_o;
  33.211 -output d_lock_o;                                        // Date Wishbone interface lock bus
  33.212 -reg    d_lock_o;
  33.213 -output [`LM32_BTYPE_RNG] d_bte_o;                       // Data Wishbone interface burst type 
  33.214 -wire   [`LM32_BTYPE_RNG] d_bte_o;
  33.215 -
  33.216 -/////////////////////////////////////////////////////
  33.217 -// Internal nets and registers 
  33.218 -/////////////////////////////////////////////////////
  33.219 -
  33.220 -// Microcode pipeline registers - See inputs for description
  33.221 -reg [`LM32_SIZE_RNG] size_m;
  33.222 -reg [`LM32_SIZE_RNG] size_w;
  33.223 -reg sign_extend_m;
  33.224 -reg sign_extend_w;
  33.225 -reg [`LM32_WORD_RNG] store_data_x;       
  33.226 -reg [`LM32_WORD_RNG] store_data_m;       
  33.227 -reg [`LM32_BYTE_SELECT_RNG] byte_enable_x;
  33.228 -reg [`LM32_BYTE_SELECT_RNG] byte_enable_m;
  33.229 -wire [`LM32_WORD_RNG] data_m;
  33.230 -reg [`LM32_WORD_RNG] data_w;
  33.231 -
  33.232 -`ifdef CFG_DCACHE_ENABLED
  33.233 -wire dcache_select_x;                                   // Select data cache to load from / store to
  33.234 -reg dcache_select_m;
  33.235 -wire [`LM32_WORD_RNG] dcache_data_m;                    // Data read from cache
  33.236 -wire [`LM32_WORD_RNG] dcache_refill_address;            // Address to refill data cache from
  33.237 -reg dcache_refill_ready;                                // Indicates the next word of refill data is ready
  33.238 -wire [`LM32_CTYPE_RNG] first_cycle_type;                // First Wishbone cycle type
  33.239 -wire [`LM32_CTYPE_RNG] next_cycle_type;                 // Next Wishbone cycle type
  33.240 -wire last_word;                                         // Indicates if this is the last word in the cache line
  33.241 -wire [`LM32_WORD_RNG] first_address;                    // First cache refill address
  33.242 -`endif
  33.243 -`ifdef CFG_DRAM_ENABLED
  33.244 -wire dram_select_x;                                     // Select data RAM to load from / store to
  33.245 -reg dram_select_m;
  33.246 -reg dram_bypass_en;                                     // RAW in data RAM; read latched (bypass) value rather than value from memory
  33.247 -reg [`LM32_WORD_RNG] dram_bypass_data;                  // Latched value of store'd data to data RAM
  33.248 -wire [`LM32_WORD_RNG] dram_data_out;                    // Data read from data RAM
  33.249 -wire [`LM32_WORD_RNG] dram_data_m;                      // Data read from data RAM: bypass value or value from memory
  33.250 -wire [`LM32_WORD_RNG] dram_store_data_m;                // Data to write to RAM
  33.251 -`endif
  33.252 -wire wb_select_x;                                       // Select Wishbone to load from / store to
  33.253 -`ifdef CFG_IROM_ENABLED
  33.254 -wire irom_select_x;                                     // Select instruction ROM to load from / store to
  33.255 -reg  irom_select_m;
  33.256 -`endif
  33.257 -reg wb_select_m;
  33.258 -reg [`LM32_WORD_RNG] wb_data_m;                         // Data read from Wishbone
  33.259 -reg wb_load_complete;                                   // Indicates when a Wishbone load is complete
  33.260 -
  33.261 -/////////////////////////////////////////////////////
  33.262 -// Functions
  33.263 -/////////////////////////////////////////////////////
  33.264 -
  33.265 -`include "lm32_functions.v"
  33.266 -
  33.267 -/////////////////////////////////////////////////////
  33.268 -// Instantiations
  33.269 -/////////////////////////////////////////////////////
  33.270 -
  33.271 -`ifdef CFG_DRAM_ENABLED
  33.272 -   // Data RAM
  33.273 -   pmi_ram_dp_true 
  33.274 -     #(
  33.275 -       // ----- Parameters -------
  33.276 -       .pmi_family             (`LATTICE_FAMILY),
  33.277 -
  33.278 -       //.pmi_addr_depth_a       (1 << (clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)),
  33.279 -       //.pmi_addr_width_a       ((clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)),
  33.280 -       //.pmi_data_width_a       (`LM32_WORD_WIDTH),
  33.281 -       //.pmi_addr_depth_b       (1 << (clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)),
  33.282 -       //.pmi_addr_width_b       ((clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)),
  33.283 -       //.pmi_data_width_b       (`LM32_WORD_WIDTH),
  33.284 -	
  33.285 -       .pmi_addr_depth_a       (`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1),
  33.286 -       .pmi_addr_width_a       (clogb2_v1(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
  33.287 -       .pmi_data_width_a       (`LM32_WORD_WIDTH),
  33.288 -       .pmi_addr_depth_b       (`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1),
  33.289 -       .pmi_addr_width_b       (clogb2_v1(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
  33.290 -       .pmi_data_width_b       (`LM32_WORD_WIDTH),
  33.291 -
  33.292 -       .pmi_regmode_a          ("noreg"),
  33.293 -       .pmi_regmode_b          ("noreg"),
  33.294 -       .pmi_gsr                ("enable"),
  33.295 -       .pmi_resetmode          ("sync"),
  33.296 -       .pmi_init_file          (`CFG_DRAM_INIT_FILE),
  33.297 -       .pmi_init_file_format   (`CFG_DRAM_INIT_FILE_FORMAT),
  33.298 -       .module_type            ("pmi_ram_dp_true")
  33.299 -       ) 
  33.300 -       ram (
  33.301 -	    // ----- Inputs -------
  33.302 -	    .ClockA                 (clk_i),
  33.303 -	    .ClockB                 (clk_i),
  33.304 -	    .ResetA                 (rst_i),
  33.305 -	    .ResetB                 (rst_i),
  33.306 -	    .DataInA                ({32{1'b0}}),
  33.307 -	    .DataInB                (dram_store_data_m),
  33.308 -	    .AddressA               (load_store_address_x[(clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)+2-1:2]),
  33.309 -	    .AddressB               (load_store_address_m[(clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)+2-1:2]),
  33.310 -	    // .ClockEnA               (!stall_x & (load_x | store_x)),
  33.311 -	    .ClockEnA               (!stall_x),
  33.312 -	    .ClockEnB               (!stall_m),
  33.313 -	    .WrA                    (`FALSE),
  33.314 -	    .WrB                    (store_q_m & dram_select_m), 
  33.315 -	    // ----- Outputs -------
  33.316 -	    .QA                     (dram_data_out),
  33.317 -	    .QB                     ()
  33.318 -	    );
  33.319 -   
  33.320 -   /*----------------------------------------------------------------------
  33.321 -    EBRs cannot perform reads from location 'written to' on the same clock
  33.322 -    edge. Therefore bypass logic is required to latch the store'd value
  33.323 -    and use it for the load (instead of value from memory).
  33.324 -    ----------------------------------------------------------------------*/
  33.325 -   always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  33.326 -     if (rst_i == `TRUE)
  33.327 -       begin
  33.328 -	  dram_bypass_en <= `FALSE;
  33.329 -	  dram_bypass_data <= 0;
  33.330 -       end
  33.331 -     else
  33.332 -       begin
  33.333 -	  if (stall_x == `FALSE)
  33.334 -	    dram_bypass_data <= dram_store_data_m;
  33.335 -	  
  33.336 -	  if (   (stall_m == `FALSE) 
  33.337 -              && (stall_x == `FALSE)
  33.338 -	      && (store_q_m == `TRUE)
  33.339 -	      && (   (load_x == `TRUE)
  33.340 -	          || (store_x == `TRUE)
  33.341 -		 )
  33.342 -	      && (load_store_address_x[(`LM32_WORD_WIDTH-1):2] == load_store_address_m[(`LM32_WORD_WIDTH-1):2])
  33.343 -	     )
  33.344 -	    dram_bypass_en <= `TRUE;
  33.345 -	  else
  33.346 -	    if (   (dram_bypass_en == `TRUE)
  33.347 -		&& (stall_x == `FALSE)
  33.348 -	       )
  33.349 -	      dram_bypass_en <= `FALSE;
  33.350 -       end
  33.351 -   
  33.352 -   assign dram_data_m = dram_bypass_en ? dram_bypass_data : dram_data_out;
  33.353 -`endif
  33.354 -
  33.355 -`ifdef CFG_DCACHE_ENABLED
  33.356 -// Data cache
  33.357 -lm32_dcache #(
  33.358 -    .associativity          (associativity),
  33.359 -    .sets                   (sets),
  33.360 -    .bytes_per_line         (bytes_per_line),
  33.361 -    .base_address           (base_address),
  33.362 -    .limit                  (limit)
  33.363 -    ) dcache ( 
  33.364 -    // ----- Inputs -----
  33.365 -    .clk_i                  (clk_i),
  33.366 -    .rst_i                  (rst_i),      
  33.367 -    .stall_a                (stall_a),
  33.368 -    .stall_x                (stall_x),
  33.369 -    .stall_m                (stall_m),
  33.370 -    .address_x              (load_store_address_x),
  33.371 -    .address_m              (load_store_address_m),
  33.372 -    .load_q_m               (load_q_m & dcache_select_m),
  33.373 -    .store_q_m              (store_q_m & dcache_select_m),
  33.374 -    .store_data             (store_data_m),
  33.375 -    .store_byte_select      (byte_enable_m & {4{dcache_select_m}}),
  33.376 -    .refill_ready           (dcache_refill_ready),
  33.377 -    .refill_data            (wb_data_m),
  33.378 -    .dflush                 (dflush),
  33.379 -    // ----- Outputs -----
  33.380 -    .stall_request          (dcache_stall_request),
  33.381 -    .restart_request        (dcache_restart_request),
  33.382 -    .refill_request         (dcache_refill_request),
  33.383 -    .refill_address         (dcache_refill_address),
  33.384 -    .refilling              (dcache_refilling),
  33.385 -    .load_data              (dcache_data_m)
  33.386 -    );
  33.387 -`endif
  33.388 -
  33.389 -/////////////////////////////////////////////////////
  33.390 -// Combinational Logic
  33.391 -/////////////////////////////////////////////////////
  33.392 -
  33.393 -// Select where data should be loaded from / stored to
  33.394 -`ifdef CFG_DRAM_ENABLED
  33.395 -   assign dram_select_x =    (load_store_address_x >= `CFG_DRAM_BASE_ADDRESS) 
  33.396 -                          && (load_store_address_x <= `CFG_DRAM_LIMIT);
  33.397 -`endif
  33.398 -
  33.399 -`ifdef CFG_IROM_ENABLED
  33.400 -   assign irom_select_x =    (load_store_address_x >= `CFG_IROM_BASE_ADDRESS) 
  33.401 -                          && (load_store_address_x <= `CFG_IROM_LIMIT);
  33.402 -`endif
  33.403 -   
  33.404 -`ifdef CFG_DCACHE_ENABLED
  33.405 -   assign dcache_select_x =    (load_store_address_x >= `CFG_DCACHE_BASE_ADDRESS) 
  33.406 -                            && (load_store_address_x <= `CFG_DCACHE_LIMIT)
  33.407 -`ifdef CFG_DRAM_ENABLED
  33.408 -                            && (dram_select_x == `FALSE)
  33.409 -`endif
  33.410 -`ifdef CFG_IROM_ENABLED
  33.411 -                            && (irom_select_x == `FALSE)
  33.412 -`endif
  33.413 -                     ;
  33.414 -`endif
  33.415 -	  
  33.416 -   assign wb_select_x =    `TRUE
  33.417 -`ifdef CFG_DCACHE_ENABLED
  33.418 -                        && !dcache_select_x 
  33.419 -`endif
  33.420 -`ifdef CFG_DRAM_ENABLED
  33.421 -                        && !dram_select_x
  33.422 -`endif
  33.423 -`ifdef CFG_IROM_ENABLED
  33.424 -                        && !irom_select_x
  33.425 -`endif
  33.426 -                     ;
  33.427 -
  33.428 -// Make sure data to store is in correct byte lane
  33.429 -always @(*)
  33.430 -begin
  33.431 -    case (size_x)
  33.432 -    `LM32_SIZE_BYTE:  store_data_x = {4{store_operand_x[7:0]}};
  33.433 -    `LM32_SIZE_HWORD: store_data_x = {2{store_operand_x[15:0]}};
  33.434 -    `LM32_SIZE_WORD:  store_data_x = store_operand_x;    
  33.435 -    default:          store_data_x = {`LM32_WORD_WIDTH{1'bx}};
  33.436 -    endcase
  33.437 -end
  33.438 -
  33.439 -// Generate byte enable accoring to size of load or store and address being accessed
  33.440 -always @(*)
  33.441 -begin
  33.442 -    casez ({size_x, load_store_address_x[1:0]})
  33.443 -    {`LM32_SIZE_BYTE, 2'b11}:  byte_enable_x = 4'b0001;
  33.444 -    {`LM32_SIZE_BYTE, 2'b10}:  byte_enable_x = 4'b0010;
  33.445 -    {`LM32_SIZE_BYTE, 2'b01}:  byte_enable_x = 4'b0100;
  33.446 -    {`LM32_SIZE_BYTE, 2'b00}:  byte_enable_x = 4'b1000;
  33.447 -    {`LM32_SIZE_HWORD, 2'b1?}: byte_enable_x = 4'b0011;
  33.448 -    {`LM32_SIZE_HWORD, 2'b0?}: byte_enable_x = 4'b1100;
  33.449 -    {`LM32_SIZE_WORD, 2'b??}:  byte_enable_x = 4'b1111;
  33.450 -    default:                   byte_enable_x = 4'bxxxx;
  33.451 -    endcase
  33.452 -end
  33.453 -
  33.454 -`ifdef CFG_DRAM_ENABLED
  33.455 -// Only replace selected bytes
  33.456 -assign dram_store_data_m[`LM32_BYTE_0_RNG] = byte_enable_m[0] ? store_data_m[`LM32_BYTE_0_RNG] : dram_data_m[`LM32_BYTE_0_RNG];
  33.457 -assign dram_store_data_m[`LM32_BYTE_1_RNG] = byte_enable_m[1] ? store_data_m[`LM32_BYTE_1_RNG] : dram_data_m[`LM32_BYTE_1_RNG];
  33.458 -assign dram_store_data_m[`LM32_BYTE_2_RNG] = byte_enable_m[2] ? store_data_m[`LM32_BYTE_2_RNG] : dram_data_m[`LM32_BYTE_2_RNG];
  33.459 -assign dram_store_data_m[`LM32_BYTE_3_RNG] = byte_enable_m[3] ? store_data_m[`LM32_BYTE_3_RNG] : dram_data_m[`LM32_BYTE_3_RNG];
  33.460 -`endif
  33.461 -
  33.462 -`ifdef CFG_IROM_ENABLED
  33.463 -// Only replace selected bytes
  33.464 -assign irom_store_data_m[`LM32_BYTE_0_RNG] = byte_enable_m[0] ? store_data_m[`LM32_BYTE_0_RNG] : irom_data_m[`LM32_BYTE_0_RNG];
  33.465 -assign irom_store_data_m[`LM32_BYTE_1_RNG] = byte_enable_m[1] ? store_data_m[`LM32_BYTE_1_RNG] : irom_data_m[`LM32_BYTE_1_RNG];
  33.466 -assign irom_store_data_m[`LM32_BYTE_2_RNG] = byte_enable_m[2] ? store_data_m[`LM32_BYTE_2_RNG] : irom_data_m[`LM32_BYTE_2_RNG];
  33.467 -assign irom_store_data_m[`LM32_BYTE_3_RNG] = byte_enable_m[3] ? store_data_m[`LM32_BYTE_3_RNG] : irom_data_m[`LM32_BYTE_3_RNG];
  33.468 -`endif
  33.469 -
  33.470 -`ifdef CFG_IROM_ENABLED
  33.471 -   // Instead of implementing a byte-addressable instruction ROM (for store byte instruction),
  33.472 -   // a load-and-store architecture is used wherein a 32-bit value is loaded, the requisite
  33.473 -   // byte is replaced, and the whole 32-bit value is written back
  33.474 -   
  33.475 -   assign irom_address_xm = ((irom_select_m == `TRUE) && (store_q_m == `TRUE))
  33.476 -	                    ? load_store_address_m
  33.477 -	                    : load_store_address_x;
  33.478 -   
  33.479 -   // All store instructions perform a write operation in the M stage
  33.480 -   assign irom_we_xm =    (irom_select_m == `TRUE)
  33.481 -	               && (store_q_m == `TRUE);
  33.482 -   
  33.483 -   // A single port in instruction ROM is available to load-store unit for doing loads/stores.
  33.484 -   // Since every store requires a load (in X stage) and then a store (in M stage), we cannot
  33.485 -   // allow load (or store) instructions sequentially after the store instructions to proceed 
  33.486 -   // until the store instruction has vacated M stage (i.e., completed the store operation)
  33.487 -   assign irom_stall_request_x =    (irom_select_x == `TRUE)
  33.488 -	                         && (store_q_x == `TRUE);
  33.489 -`endif
  33.490 -   
  33.491 -`ifdef CFG_DCACHE_ENABLED
  33.492 - `ifdef CFG_DRAM_ENABLED
  33.493 -  `ifdef CFG_IROM_ENABLED
  33.494 -   // WB + DC + DRAM + IROM
  33.495 -   assign data_m = wb_select_m == `TRUE 
  33.496 -                   ? wb_data_m
  33.497 -                   : dram_select_m == `TRUE 
  33.498 -                     ? dram_data_m
  33.499 -                     : irom_select_m == `TRUE
  33.500 -                       ? irom_data_m 
  33.501 -                       : dcache_data_m;
  33.502 -  `else
  33.503 -   // WB + DC + DRAM
  33.504 -   assign data_m = wb_select_m == `TRUE 
  33.505 -                   ? wb_data_m
  33.506 -                   : dram_select_m == `TRUE 
  33.507 -                     ? dram_data_m
  33.508 -                     : dcache_data_m;
  33.509 -  `endif
  33.510 - `else
  33.511 -  `ifdef CFG_IROM_ENABLED
  33.512 -   // WB + DC + IROM
  33.513 -   assign data_m = wb_select_m == `TRUE 
  33.514 -                   ? wb_data_m
  33.515 -                   : irom_select_m == `TRUE 
  33.516 -                     ? irom_data_m
  33.517 -                     : dcache_data_m;
  33.518 -  `else
  33.519 -   // WB + DC
  33.520 -   assign data_m = wb_select_m == `TRUE 
  33.521 -                   ? wb_data_m 
  33.522 -                   : dcache_data_m;
  33.523 -  `endif
  33.524 - `endif
  33.525 -`else
  33.526 - `ifdef CFG_DRAM_ENABLED
  33.527 -  `ifdef CFG_IROM_ENABLED
  33.528 -   // WB + DRAM + IROM
  33.529 -   assign data_m = wb_select_m == `TRUE 
  33.530 -                   ? wb_data_m 
  33.531 -                   : dram_select_m == `TRUE
  33.532 -                     ? dram_data_m
  33.533 -                     : irom_data_m;
  33.534 -  `else
  33.535 -   // WB + DRAM
  33.536 -   assign data_m = wb_select_m == `TRUE 
  33.537 -                   ? wb_data_m 
  33.538 -                   : dram_data_m;
  33.539 -  `endif
  33.540 - `else
  33.541 -  `ifdef CFG_IROM_ENABLED
  33.542 -   // WB + IROM
  33.543 -   assign data_m = wb_select_m == `TRUE 
  33.544 -                   ? wb_data_m 
  33.545 -                   : irom_data_m;
  33.546 -  `else
  33.547 -   // WB
  33.548 -   assign data_m = wb_data_m;
  33.549 -  `endif
  33.550 - `endif
  33.551 -`endif
  33.552 -
  33.553 -// Sub-word selection and sign/zero-extension for loads
  33.554 -always @(*)
  33.555 -begin
  33.556 -    casez ({size_w, load_store_address_w[1:0]})
  33.557 -    {`LM32_SIZE_BYTE, 2'b11}:  load_data_w = {{24{sign_extend_w & data_w[7]}}, data_w[7:0]};
  33.558 -    {`LM32_SIZE_BYTE, 2'b10}:  load_data_w = {{24{sign_extend_w & data_w[15]}}, data_w[15:8]};
  33.559 -    {`LM32_SIZE_BYTE, 2'b01}:  load_data_w = {{24{sign_extend_w & data_w[23]}}, data_w[23:16]};
  33.560 -    {`LM32_SIZE_BYTE, 2'b00}:  load_data_w = {{24{sign_extend_w & data_w[31]}}, data_w[31:24]};
  33.561 -    {`LM32_SIZE_HWORD, 2'b1?}: load_data_w = {{16{sign_extend_w & data_w[15]}}, data_w[15:0]};
  33.562 -    {`LM32_SIZE_HWORD, 2'b0?}: load_data_w = {{16{sign_extend_w & data_w[31]}}, data_w[31:16]};
  33.563 -    {`LM32_SIZE_WORD, 2'b??}:  load_data_w = data_w;
  33.564 -    default:                   load_data_w = {`LM32_WORD_WIDTH{1'bx}};
  33.565 -    endcase
  33.566 -end
  33.567 -
  33.568 -// Unused/constant Wishbone signals
  33.569 -assign d_bte_o = `LM32_BTYPE_LINEAR;
  33.570 -
  33.571 -`ifdef CFG_DCACHE_ENABLED                
  33.572 -// Generate signal to indicate last word in cache line
  33.573 -generate 
  33.574 -    case (bytes_per_line)
  33.575 -    4:
  33.576 -    begin
  33.577 -assign first_cycle_type = `LM32_CTYPE_END;
  33.578 -assign next_cycle_type = `LM32_CTYPE_END;
  33.579 -assign last_word = `TRUE;
  33.580 -assign first_address = {dcache_refill_address[`LM32_WORD_WIDTH-1:2], 2'b00};
  33.581 -    end
  33.582 -    8:
  33.583 -    begin
  33.584 -assign first_cycle_type = `LM32_CTYPE_INCREMENTING;
  33.585 -assign next_cycle_type = `LM32_CTYPE_END;
  33.586 -assign last_word = (&d_adr_o[addr_offset_msb:addr_offset_lsb]) == 1'b1;
  33.587 -assign first_address = {dcache_refill_address[`LM32_WORD_WIDTH-1:addr_offset_msb+1], {addr_offset_width{1'b0}}, 2'b00};
  33.588 -    end
  33.589 -    16:
  33.590 -    begin
  33.591 -assign first_cycle_type = `LM32_CTYPE_INCREMENTING;
  33.592 -assign next_cycle_type = d_adr_o[addr_offset_msb] == 1'b1 ? `LM32_CTYPE_END : `LM32_CTYPE_INCREMENTING;
  33.593 -assign last_word = (&d_adr_o[addr_offset_msb:addr_offset_lsb]) == 1'b1;
  33.594 -assign first_address = {dcache_refill_address[`LM32_WORD_WIDTH-1:addr_offset_msb+1], {addr_offset_width{1'b0}}, 2'b00};
  33.595 -    end
  33.596 -    endcase
  33.597 -endgenerate
  33.598 -`endif
  33.599 -
  33.600 -/////////////////////////////////////////////////////
  33.601 -// Sequential Logic
  33.602 -/////////////////////////////////////////////////////
  33.603 -
  33.604 -// Data Wishbone interface
  33.605 -always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  33.606 -begin
  33.607 -    if (rst_i == `TRUE)
  33.608 -    begin
  33.609 -        d_cyc_o <= `FALSE;
  33.610 -        d_stb_o <= `FALSE;
  33.611 -        d_dat_o <= {`LM32_WORD_WIDTH{1'b0}};
  33.612 -        d_adr_o <= {`LM32_WORD_WIDTH{1'b0}};
  33.613 -        d_sel_o <= {`LM32_BYTE_SELECT_WIDTH{`FALSE}};
  33.614 -        d_we_o <= `FALSE;
  33.615 -        d_cti_o <= `LM32_CTYPE_END;
  33.616 -        d_lock_o <= `FALSE;
  33.617 -        wb_data_m <= {`LM32_WORD_WIDTH{1'b0}};
  33.618 -        wb_load_complete <= `FALSE;
  33.619 -        stall_wb_load <= `FALSE;
  33.620 -`ifdef CFG_DCACHE_ENABLED                
  33.621 -        dcache_refill_ready <= `FALSE;
  33.622 -`endif                
  33.623 -    end
  33.624 -    else
  33.625 -    begin
  33.626 -`ifdef CFG_DCACHE_ENABLED 
  33.627 -        // Refill ready should only be asserted for a single cycle               
  33.628 -        dcache_refill_ready <= `FALSE;
  33.629 -`endif                
  33.630 -        // Is a Wishbone cycle already in progress?
  33.631 -        if (d_cyc_o == `TRUE)
  33.632 -        begin
  33.633 -            // Is the cycle complete?
  33.634 -            if ((d_ack_i == `TRUE) || (d_err_i == `TRUE))
  33.635 -            begin
  33.636 -`ifdef CFG_DCACHE_ENABLED                
  33.637 -                if ((dcache_refilling == `TRUE) && (!last_word))
  33.638 -                begin
  33.639 -                    // Fetch next word of cache line    
  33.640 -                    d_adr_o[addr_offset_msb:addr_offset_lsb] <= d_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
  33.641 -                end
  33.642 -                else
  33.643 -`endif                
  33.644 -                begin
  33.645 -                    // Refill/access complete
  33.646 -                    d_cyc_o <= `FALSE;
  33.647 -                    d_stb_o <= `FALSE;
  33.648 -                    d_lock_o <= `FALSE;
  33.649 -                end
  33.650 -`ifdef CFG_DCACHE_ENABLED    
  33.651 -                d_cti_o <= next_cycle_type;
  33.652 -                // If we are performing a refill, indicate to cache next word of data is ready            
  33.653 -                dcache_refill_ready <= dcache_refilling;
  33.654 -`endif
  33.655 -                // Register data read from Wishbone interface
  33.656 -                wb_data_m <= d_dat_i;
  33.657 -                // Don't set when stores complete - otherwise we'll deadlock if load in m stage
  33.658 -                wb_load_complete <= !d_we_o;
  33.659 -            end
  33.660 -            // synthesis translate_off            
  33.661 -            if (d_err_i == `TRUE)
  33.662 -                $display ("Data bus error. Address: %x", d_adr_o);
  33.663 -            // synthesis translate_on
  33.664 -        end
  33.665 -        else
  33.666 -        begin
  33.667 -`ifdef CFG_DCACHE_ENABLED                
  33.668 -            if (dcache_refill_request == `TRUE)
  33.669 -            begin
  33.670 -                // Start cache refill
  33.671 -                d_adr_o <= first_address;
  33.672 -                d_cyc_o <= `TRUE;
  33.673 -                d_sel_o <= {`LM32_WORD_WIDTH/8{`TRUE}};
  33.674 -                d_stb_o <= `TRUE;                
  33.675 -                d_we_o <= `FALSE;
  33.676 -                d_cti_o <= first_cycle_type;
  33.677 -                //d_lock_o <= `TRUE;
  33.678 -            end
  33.679 -            else 
  33.680 -`endif            
  33.681 -                 if (   (store_q_m == `TRUE)
  33.682 -                     && (stall_m == `FALSE)
  33.683 -`ifdef CFG_DRAM_ENABLED
  33.684 -                     && (dram_select_m == `FALSE)
  33.685 -`endif
  33.686 -`ifdef CFG_IROM_ENABLED
  33.687 -		     && (irom_select_m == `FALSE)
  33.688 -`endif			
  33.689 -                    )
  33.690 -            begin
  33.691 -                // Data cache is write through, so all stores go to memory
  33.692 -                d_dat_o <= store_data_m;
  33.693 -                d_adr_o <= load_store_address_m;
  33.694 -                d_cyc_o <= `TRUE;
  33.695 -                d_sel_o <= byte_enable_m;
  33.696 -                d_stb_o <= `TRUE;
  33.697 -                d_we_o <= `TRUE;
  33.698 -                d_cti_o <= `LM32_CTYPE_END;
  33.699 -            end        
  33.700 -            else if (   (load_q_m == `TRUE) 
  33.701 -                     && (wb_select_m == `TRUE) 
  33.702 -                     && (wb_load_complete == `FALSE)
  33.703 -                     // stall_m will be TRUE, because stall_wb_load will be TRUE 
  33.704 -                    )
  33.705 -            begin
  33.706 -                // Read requested address
  33.707 -                stall_wb_load <= `FALSE;
  33.708 -                d_adr_o <= load_store_address_m;
  33.709 -                d_cyc_o <= `TRUE;
  33.710 -                d_sel_o <= byte_enable_m;
  33.711 -                d_stb_o <= `TRUE;
  33.712 -                d_we_o <= `FALSE;
  33.713 -                d_cti_o <= `LM32_CTYPE_END;
  33.714 -            end
  33.715 -        end
  33.716 -        // Clear load/store complete flag when instruction leaves M stage
  33.717 -        if (stall_m == `FALSE)
  33.718 -            wb_load_complete <= `FALSE;
  33.719 -        // When a Wishbone load first enters the M stage, we need to stall it
  33.720 -        if ((load_q_x == `TRUE) && (wb_select_x == `TRUE) && (stall_x == `FALSE))
  33.721 -            stall_wb_load <= `TRUE;
  33.722 -        // Clear stall request if load instruction is killed
  33.723 -        if ((kill_m == `TRUE) || (exception_m == `TRUE))
  33.724 -            stall_wb_load <= `FALSE;
  33.725 -    end
  33.726 -end
  33.727 -
  33.728 -// Pipeline registers  
  33.729 -
  33.730 -// X/M stage pipeline registers
  33.731 -always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  33.732 -begin
  33.733 -    if (rst_i == `TRUE)
  33.734 -    begin
  33.735 -        sign_extend_m <= `FALSE;
  33.736 -        size_m <= 2'b00;
  33.737 -        byte_enable_m <= `FALSE;
  33.738 -        store_data_m <= {`LM32_WORD_WIDTH{1'b0}};
  33.739 -`ifdef CFG_DCACHE_ENABLED
  33.740 -        dcache_select_m <= `FALSE;
  33.741 -`endif
  33.742 -`ifdef CFG_DRAM_ENABLED
  33.743 -        dram_select_m <= `FALSE;
  33.744 -`endif
  33.745 -`ifdef CFG_IROM_ENABLED
  33.746 -        irom_select_m <= `FALSE;
  33.747 -`endif
  33.748 -        wb_select_m <= `FALSE;        
  33.749 -    end
  33.750 -    else
  33.751 -    begin
  33.752 -        if (stall_m == `FALSE)
  33.753 -        begin
  33.754 -            sign_extend_m <= sign_extend_x;
  33.755 -            size_m <= size_x;
  33.756 -            byte_enable_m <= byte_enable_x;    
  33.757 -            store_data_m <= store_data_x;
  33.758 -`ifdef CFG_DCACHE_ENABLED
  33.759 -            dcache_select_m <= dcache_select_x;
  33.760 -`endif
  33.761 -`ifdef CFG_DRAM_ENABLED
  33.762 -            dram_select_m <= dram_select_x;
  33.763 -`endif
  33.764 -`ifdef CFG_IROM_ENABLED
  33.765 -            irom_select_m <= irom_select_x;
  33.766 -`endif
  33.767 -            wb_select_m <= wb_select_x;
  33.768 -        end
  33.769 -    end
  33.770 -end
  33.771 -
  33.772 -// M/W stage pipeline registers
  33.773 -always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  33.774 -begin
  33.775 -    if (rst_i == `TRUE)
  33.776 -    begin
  33.777 -        size_w <= 2'b00;
  33.778 -        data_w <= {`LM32_WORD_WIDTH{1'b0}};
  33.779 -        sign_extend_w <= `FALSE;
  33.780 -    end
  33.781 -    else
  33.782 -    begin
  33.783 -        size_w <= size_m;
  33.784 -        data_w <= data_m;
  33.785 -        sign_extend_w <= sign_extend_m;
  33.786 -    end
  33.787 -end
  33.788 -
  33.789 -/////////////////////////////////////////////////////
  33.790 -// Behavioural Logic
  33.791 -/////////////////////////////////////////////////////
  33.792 -
  33.793 -// synthesis translate_off
  33.794 -
  33.795 -// Check for non-aligned loads or stores
  33.796 -always @(posedge clk_i)
  33.797 -begin
  33.798 -    if (((load_q_m == `TRUE) || (store_q_m == `TRUE)) && (stall_m == `FALSE)) 
  33.799 -    begin
  33.800 -        if ((size_m === `LM32_SIZE_HWORD) && (load_store_address_m[0] !== 1'b0))
  33.801 -            $display ("Warning: Non-aligned halfword access. Address: 0x%0x Time: %0t.", load_store_address_m, $time);
  33.802 -        if ((size_m === `LM32_SIZE_WORD) && (load_store_address_m[1:0] !== 2'b00))
  33.803 -            $display ("Warning: Non-aligned word access. Address: 0x%0x Time: %0t.", load_store_address_m, $time);
  33.804 -    end
  33.805 -end
  33.806 -
  33.807 -// synthesis translate_on
  33.808 -
  33.809 -endmodule

    34.1 --- a/lm32_logic_op.v	Sun Mar 06 21:17:31 2011 +0000
    34.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    34.3 @@ -1,76 +0,0 @@
    34.4 -// =============================================================================
    34.5 -//                           COPYRIGHT NOTICE
    34.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation
    34.7 -// ALL RIGHTS RESERVED
    34.8 -// This confidential and proprietary software may be used only as authorised by
    34.9 -// a licensing agreement from Lattice Semiconductor Corporation.
   34.10 -// The entire notice above must be reproduced on all authorized copies and
   34.11 -// copies may only be made to the extent permitted by a licensing agreement from
   34.12 -// Lattice Semiconductor Corporation.
   34.13 -//
   34.14 -// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
   34.15 -// 5555 NE Moore Court                            408-826-6000 (other locations)
   34.16 -// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
   34.17 -// U.S.A                                   email: techsupport@latticesemi.com
   34.18 -// =============================================================================/
   34.19 -//                         FILE DETAILS
   34.20 -// Project          : LatticeMico32
   34.21 -// File             : lm32_logic_op.v
   34.22 -// Title            : Logic operations (and / or / not etc)
   34.23 -// Dependencies     : lm32_include.v
   34.24 -// Version          : 6.1.17
   34.25 -//                  : Initial Release
   34.26 -// Version          : 7.0SP2, 3.0
   34.27 -//                  : No Change
   34.28 -// Version          : 3.1
   34.29 -//                  : No Change
   34.30 -// =============================================================================
   34.31 -
   34.32 -`include "lm32_include.v"
   34.33 -
   34.34 -/////////////////////////////////////////////////////
   34.35 -// Module interface
   34.36 -/////////////////////////////////////////////////////
   34.37 -
   34.38 -module lm32_logic_op (
   34.39 -    // ----- Inputs -------
   34.40 -    logic_op_x,
   34.41 -    operand_0_x,
   34.42 -    operand_1_x,
   34.43 -    // ----- Outputs -------
   34.44 -    logic_result_x
   34.45 -    );
   34.46 -
   34.47 -/////////////////////////////////////////////////////
   34.48 -// Inputs
   34.49 -/////////////////////////////////////////////////////
   34.50 -
   34.51 -input [`LM32_LOGIC_OP_RNG] logic_op_x;
   34.52 -input [`LM32_WORD_RNG] operand_0_x;
   34.53 -input [`LM32_WORD_RNG] operand_1_x;
   34.54 -
   34.55 -/////////////////////////////////////////////////////
   34.56 -// Outputs
   34.57 -/////////////////////////////////////////////////////
   34.58 -
   34.59 -output [`LM32_WORD_RNG] logic_result_x;
   34.60 -reg    [`LM32_WORD_RNG] logic_result_x;
   34.61 -    
   34.62 -/////////////////////////////////////////////////////
   34.63 -// Internal nets and registers 
   34.64 -/////////////////////////////////////////////////////
   34.65 -
   34.66 -integer logic_idx;
   34.67 -
   34.68 -/////////////////////////////////////////////////////
   34.69 -// Combinational Logic
   34.70 -/////////////////////////////////////////////////////
   34.71 -
   34.72 -always @(*)
   34.73 -begin
   34.74 -    for(logic_idx = 0; logic_idx < `LM32_WORD_WIDTH; logic_idx = logic_idx + 1)
   34.75 -        logic_result_x[logic_idx] = logic_op_x[{operand_1_x[logic_idx], operand_0_x[logic_idx]}];
   34.76 -end
   34.77 -    
   34.78 -endmodule
   34.79 -

    35.1 --- a/lm32_mc_arithmetic.v	Sun Mar 06 21:17:31 2011 +0000
    35.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    35.3 @@ -1,288 +0,0 @@
    35.4 -// =============================================================================
    35.5 -//                           COPYRIGHT NOTICE
    35.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation
    35.7 -// ALL RIGHTS RESERVED
    35.8 -// This confidential and proprietary software may be used only as authorised by
    35.9 -// a licensing agreement from Lattice Semiconductor Corporation.
   35.10 -// The entire notice above must be reproduced on all authorized copies and
   35.11 -// copies may only be made to the extent permitted by a licensing agreement from
   35.12 -// Lattice Semiconductor Corporation.
   35.13 -//
   35.14 -// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
   35.15 -// 5555 NE Moore Court                            408-826-6000 (other locations)
   35.16 -// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
   35.17 -// U.S.A                                   email: techsupport@latticesemi.com
   35.18 -// =============================================================================/
   35.19 -//                         FILE DETAILS
   35.20 -// Project          : LatticeMico32
   35.21 -// File             : lm_mc_arithmetic.v
   35.22 -// Title            : Multi-cycle arithmetic unit.
   35.23 -// Dependencies     : lm32_include.v
   35.24 -// Version          : 6.1.17
   35.25 -//                  : Initial Release
   35.26 -// Version          : 7.0SP2, 3.0
   35.27 -//                  : No Change
   35.28 -// Version          : 3.1
   35.29 -//                  : No Change
   35.30 -// =============================================================================
   35.31 -
   35.32 -`include "lm32_include.v"
   35.33 -           
   35.34 -`define LM32_MC_STATE_RNG         2:0
   35.35 -`define LM32_MC_STATE_IDLE        3'b000
   35.36 -`define LM32_MC_STATE_MULTIPLY    3'b001
   35.37 -`define LM32_MC_STATE_MODULUS     3'b010   
   35.38 -`define LM32_MC_STATE_DIVIDE      3'b011 
   35.39 -`define LM32_MC_STATE_SHIFT_LEFT  3'b100
   35.40 -`define LM32_MC_STATE_SHIFT_RIGHT 3'b101
   35.41 -
   35.42 -/////////////////////////////////////////////////////
   35.43 -// Module interface
   35.44 -/////////////////////////////////////////////////////
   35.45 -
   35.46 -module lm32_mc_arithmetic (
   35.47 -    // ----- Inputs -----
   35.48 -    clk_i,
   35.49 -    rst_i,
   35.50 -    stall_d,
   35.51 -    kill_x,
   35.52 -`ifdef CFG_MC_DIVIDE_ENABLED
   35.53 -    divide_d,
   35.54 -    modulus_d,
   35.55 -`endif
   35.56 -`ifdef CFG_MC_MULTIPLY_ENABLED
   35.57 -    multiply_d,
   35.58 -`endif
   35.59 -`ifdef CFG_MC_BARREL_SHIFT_ENABLED
   35.60 -    shift_left_d,
   35.61 -    shift_right_d,
   35.62 -    sign_extend_d,
   35.63 -`endif
   35.64 -    operand_0_d,
   35.65 -    operand_1_d,
   35.66 -    // ----- Ouputs -----
   35.67 -    result_x,
   35.68 -`ifdef CFG_MC_DIVIDE_ENABLED
   35.69 -    divide_by_zero_x,
   35.70 -`endif
   35.71 -    stall_request_x
   35.72 -    );
   35.73 -
   35.74 -/////////////////////////////////////////////////////
   35.75 -// Inputs
   35.76 -/////////////////////////////////////////////////////
   35.77 -
   35.78 -input clk_i;                                    // Clock
   35.79 -input rst_i;                                    // Reset
   35.80 -input stall_d;                                  // Stall instruction in D stage
   35.81 -input kill_x;                                   // Kill instruction in X stage
   35.82 -`ifdef CFG_MC_DIVIDE_ENABLED
   35.83 -input divide_d;                                 // Perform divide
   35.84 -input modulus_d;                                // Perform modulus
   35.85 -`endif
   35.86 -`ifdef CFG_MC_MULTIPLY_ENABLED
   35.87 -input multiply_d;                               // Perform multiply
   35.88 -`endif
   35.89 -`ifdef CFG_MC_BARREL_SHIFT_ENABLED
   35.90 -input shift_left_d;                             // Perform left shift
   35.91 -input shift_right_d;                            // Perform right shift
   35.92 -input sign_extend_d;                            // Whether to sign-extend (arithmetic) or zero-extend (logical)
   35.93 -`endif
   35.94 -input [`LM32_WORD_RNG] operand_0_d;
   35.95 -input [`LM32_WORD_RNG] operand_1_d;
   35.96 -
   35.97 -/////////////////////////////////////////////////////
   35.98 -// Outputs
   35.99 -/////////////////////////////////////////////////////
  35.100 -
  35.101 -output [`LM32_WORD_RNG] result_x;               // Result of operation
  35.102 -reg    [`LM32_WORD_RNG] result_x;
  35.103 -`ifdef CFG_MC_DIVIDE_ENABLED
  35.104 -output divide_by_zero_x;                        // A divide by zero was attempted
  35.105 -reg    divide_by_zero_x;
  35.106 -`endif
  35.107 -output stall_request_x;                         // Request to stall pipeline from X stage back
  35.108 -wire   stall_request_x;
  35.109 -
  35.110 -/////////////////////////////////////////////////////
  35.111 -// Internal nets and registers 
  35.112 -/////////////////////////////////////////////////////
  35.113 -
  35.114 -reg [`LM32_WORD_RNG] p;                         // Temporary registers
  35.115 -reg [`LM32_WORD_RNG] a;
  35.116 -reg [`LM32_WORD_RNG] b;
  35.117 -`ifdef CFG_MC_DIVIDE_ENABLED
  35.118 -wire [32:0] t;
  35.119 -`endif
  35.120 -
  35.121 -reg [`LM32_MC_STATE_RNG] state;                 // Current state of FSM
  35.122 -reg [5:0] cycles;                               // Number of cycles remaining in the operation
  35.123 -
  35.124 -`ifdef CFG_MC_BARREL_SHIFT_ENABLED
  35.125 -reg sign_extend_x;                              // Whether to sign extend of zero extend right shifts
  35.126 -wire fill_value;                                // Value to fill with for right barrel-shifts
  35.127 -`endif
  35.128 -
  35.129 -/////////////////////////////////////////////////////
  35.130 -// Combinational logic
  35.131 -/////////////////////////////////////////////////////
  35.132 -
  35.133 -// Stall pipeline while any operation is being performed
  35.134 -assign stall_request_x = state != `LM32_MC_STATE_IDLE;
  35.135 -
  35.136 -`ifdef CFG_MC_DIVIDE_ENABLED
  35.137 -// Subtraction
  35.138 -assign t = {p[`LM32_WORD_WIDTH-2:0], a[`LM32_WORD_WIDTH-1]} - b;
  35.139 -`endif
  35.140 -
  35.141 -`ifdef CFG_MC_BARREL_SHIFT_ENABLED
  35.142 -// Determine fill value for right shift - Sign bit for arithmetic shift, or zero for logical shift
  35.143 -assign fill_value = (sign_extend_x == `TRUE) & b[`LM32_WORD_WIDTH-1];
  35.144 -`endif
  35.145 -
  35.146 -/////////////////////////////////////////////////////
  35.147 -// Sequential logic
  35.148 -/////////////////////////////////////////////////////
  35.149 -
  35.150 -// Perform right shift
  35.151 -always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  35.152 -begin
  35.153 -    if (rst_i == `TRUE)
  35.154 -    begin
  35.155 -        cycles <= {6{1'b0}};
  35.156 -        p <= {`LM32_WORD_WIDTH{1'b0}};
  35.157 -        a <= {`LM32_WORD_WIDTH{1'b0}};
  35.158 -        b <= {`LM32_WORD_WIDTH{1'b0}};
  35.159 -`ifdef CFG_MC_BARREL_SHIFT_ENABLED
  35.160 -        sign_extend_x <= 1'b0;
  35.161 -`endif
  35.162 -`ifdef CFG_MC_DIVIDE_ENABLED
  35.163 -        divide_by_zero_x <= `FALSE;
  35.164 -`endif
  35.165 -        result_x <= {`LM32_WORD_WIDTH{1'b0}};
  35.166 -        state <= `LM32_MC_STATE_IDLE;
  35.167 -    end
  35.168 -    else
  35.169 -    begin
  35.170 -`ifdef CFG_MC_DIVIDE_ENABLED
  35.171 -        divide_by_zero_x <= `FALSE;
  35.172 -`endif
  35.173 -        case (state)
  35.174 -        `LM32_MC_STATE_IDLE:
  35.175 -        begin
  35.176 -            if (stall_d == `FALSE)                 
  35.177 -            begin          
  35.178 -                cycles <= `LM32_WORD_WIDTH;
  35.179 -                p <= 32'b0;
  35.180 -                a <= operand_0_d;
  35.181 -                b <= operand_1_d;                    
  35.182 -`ifdef CFG_MC_DIVIDE_ENABLED
  35.183 -                if (divide_d == `TRUE)
  35.184 -                    state <= `LM32_MC_STATE_DIVIDE;
  35.185 -                if (modulus_d == `TRUE)
  35.186 -                    state <= `LM32_MC_STATE_MODULUS;
  35.187 -`endif                    
  35.188 -`ifdef CFG_MC_MULTIPLY_ENABLED
  35.189 -                if (multiply_d == `TRUE)
  35.190 -                    state <= `LM32_MC_STATE_MULTIPLY;
  35.191 -`endif
  35.192 -`ifdef CFG_MC_BARREL_SHIFT_ENABLED
  35.193 -                if (shift_left_d == `TRUE)
  35.194 -                begin
  35.195 -                    state <= `LM32_MC_STATE_SHIFT_LEFT;
  35.196 -                    sign_extend_x <= sign_extend_d;
  35.197 -                    cycles <= operand_1_d[4:0];
  35.198 -                    a <= operand_0_d;
  35.199 -                    b <= operand_0_d;
  35.200 -                end
  35.201 -                if (shift_right_d == `TRUE)
  35.202 -                begin
  35.203 -                    state <= `LM32_MC_STATE_SHIFT_RIGHT;
  35.204 -                    sign_extend_x <= sign_extend_d;
  35.205 -                    cycles <= operand_1_d[4:0];
  35.206 -                    a <= operand_0_d;
  35.207 -                    b <= operand_0_d;
  35.208 -                end
  35.209 -`endif
  35.210 -            end            
  35.211 -        end
  35.212 -`ifdef CFG_MC_DIVIDE_ENABLED
  35.213 -        `LM32_MC_STATE_DIVIDE:
  35.214 -        begin
  35.215 -            if (t[32] == 1'b0)
  35.216 -            begin
  35.217 -                p <= t[31:0];
  35.218 -                a <= {a[`LM32_WORD_WIDTH-2:0], 1'b1};
  35.219 -            end
  35.220 -            else 
  35.221 -            begin
  35.222 -                p <= {p[`LM32_WORD_WIDTH-2:0], a[`LM32_WORD_WIDTH-1]};
  35.223 -                a <= {a[`LM32_WORD_WIDTH-2:0], 1'b0};
  35.224 -            end
  35.225 -            result_x <= a;
  35.226 -            if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE))
  35.227 -            begin
  35.228 -                // Check for divide by zero
  35.229 -                divide_by_zero_x <= b == {`LM32_WORD_WIDTH{1'b0}};
  35.230 -                state <= `LM32_MC_STATE_IDLE;
  35.231 -            end
  35.232 -            cycles <= cycles - 1'b1;
  35.233 -        end
  35.234 -        `LM32_MC_STATE_MODULUS:
  35.235 -        begin
  35.236 -            if (t[32] == 1'b0)
  35.237 -            begin
  35.238 -                p <= t[31:0];
  35.239 -                a <= {a[`LM32_WORD_WIDTH-2:0], 1'b1};
  35.240 -            end
  35.241 -            else 
  35.242 -            begin
  35.243 -                p <= {p[`LM32_WORD_WIDTH-2:0], a[`LM32_WORD_WIDTH-1]};
  35.244 -                a <= {a[`LM32_WORD_WIDTH-2:0], 1'b0};
  35.245 -            end
  35.246 -            result_x <= p;
  35.247 -            if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE))
  35.248 -            begin
  35.249 -                // Check for divide by zero
  35.250 -                divide_by_zero_x <= b == {`LM32_WORD_WIDTH{1'b0}};
  35.251 -                state <= `LM32_MC_STATE_IDLE;
  35.252 -            end
  35.253 -            cycles <= cycles - 1'b1;
  35.254 -        end
  35.255 -`endif        
  35.256 -`ifdef CFG_MC_MULTIPLY_ENABLED
  35.257 -        `LM32_MC_STATE_MULTIPLY:
  35.258 -        begin
  35.259 -            if (b[0] == 1'b1)
  35.260 -                p <= p + a;
  35.261 -            b <= {1'b0, b[`LM32_WORD_WIDTH-1:1]};
  35.262 -            a <= {a[`LM32_WORD_WIDTH-2:0], 1'b0};
  35.263 -            result_x <= p;
  35.264 -            if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE))
  35.265 -                state <= `LM32_MC_STATE_IDLE;
  35.266 -            cycles <= cycles - 1'b1;
  35.267 -        end
  35.268 -`endif     
  35.269 -`ifdef CFG_MC_BARREL_SHIFT_ENABLED
  35.270 -        `LM32_MC_STATE_SHIFT_LEFT:
  35.271 -        begin       
  35.272 -            a <= {a[`LM32_WORD_WIDTH-2:0], 1'b0};
  35.273 -            result_x <= a;
  35.274 -            if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE))
  35.275 -                state <= `LM32_MC_STATE_IDLE;
  35.276 -            cycles <= cycles - 1'b1;
  35.277 -        end
  35.278 -        `LM32_MC_STATE_SHIFT_RIGHT:
  35.279 -        begin       
  35.280 -            b <= {fill_value, b[`LM32_WORD_WIDTH-1:1]};
  35.281 -            result_x <= b;
  35.282 -            if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE))
  35.283 -                state <= `LM32_MC_STATE_IDLE;
  35.284 -            cycles <= cycles - 1'b1;
  35.285 -        end
  35.286 -`endif   
  35.287 -        endcase
  35.288 -    end
  35.289 -end 
  35.290 -
  35.291 -endmodule

    36.1 --- a/lm32_multiplier.v	Sun Mar 06 21:17:31 2011 +0000
    36.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    36.3 @@ -1,99 +0,0 @@
    36.4 -// =============================================================================
    36.5 -//                           COPYRIGHT NOTICE
    36.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation
    36.7 -// ALL RIGHTS RESERVED
    36.8 -// This confidential and proprietary software may be used only as authorised by
    36.9 -// a licensing agreement from Lattice Semiconductor Corporation.
   36.10 -// The entire notice above must be reproduced on all authorized copies and
   36.11 -// copies may only be made to the extent permitted by a licensing agreement from
   36.12 -// Lattice Semiconductor Corporation.
   36.13 -//
   36.14 -// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
   36.15 -// 5555 NE Moore Court                            408-826-6000 (other locations)
   36.16 -// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
   36.17 -// U.S.A                                   email: techsupport@latticesemi.com
   36.18 -// =============================================================================/
   36.19 -//                         FILE DETAILS
   36.20 -// Project          : LatticeMico32
   36.21 -// File             : lm32_multiplier.v
   36.22 -// Title            : Pipelined multiplier.
   36.23 -// Dependencies     : lm32_include.v
   36.24 -// Version          : 6.1.17
   36.25 -//                  : Initial Release
   36.26 -// Version          : 7.0SP2, 3.0
   36.27 -//                  : No Change
   36.28 -// Version          : 3.1
   36.29 -//                  : No Change
   36.30 -// =============================================================================
   36.31 -                  
   36.32 -`include "lm32_include.v"
   36.33 -
   36.34 -/////////////////////////////////////////////////////
   36.35 -// Module interface
   36.36 -/////////////////////////////////////////////////////
   36.37 -
   36.38 -module lm32_multiplier (
   36.39 -    // ----- Inputs -----
   36.40 -    clk_i,
   36.41 -    rst_i,
   36.42 -    stall_x,
   36.43 -    stall_m,
   36.44 -    operand_0,
   36.45 -    operand_1,
   36.46 -    // ----- Ouputs -----
   36.47 -    result
   36.48 -    );
   36.49 -
   36.50 -/////////////////////////////////////////////////////
   36.51 -// Inputs
   36.52 -/////////////////////////////////////////////////////
   36.53 -
   36.54 -input clk_i;                            // Clock 
   36.55 -input rst_i;                            // Reset
   36.56 -input stall_x;                          // Stall instruction in X stage
   36.57 -input stall_m;                          // Stall instruction in M stage
   36.58 -input [`LM32_WORD_RNG] operand_0;     	// Muliplicand
   36.59 -input [`LM32_WORD_RNG] operand_1;     	// Multiplier
   36.60 -
   36.61 -/////////////////////////////////////////////////////
   36.62 -// Outputs
   36.63 -/////////////////////////////////////////////////////
   36.64 -
   36.65 -output [`LM32_WORD_RNG] result;       	// Product of multiplication
   36.66 -reg    [`LM32_WORD_RNG] result;
   36.67 -
   36.68 -/////////////////////////////////////////////////////
   36.69 -// Internal nets and registers 
   36.70 -/////////////////////////////////////////////////////
   36.71 -
   36.72 -reg [`LM32_WORD_RNG] muliplicand; 
   36.73 -reg [`LM32_WORD_RNG] multiplier; 
   36.74 -reg [`LM32_WORD_RNG] product; 
   36.75 -
   36.76 -/////////////////////////////////////////////////////
   36.77 -// Sequential logic
   36.78 -/////////////////////////////////////////////////////
   36.79 -
   36.80 -always @(posedge clk_i `CFG_RESET_SENSITIVITY)
   36.81 -begin
   36.82 -    if (rst_i == `TRUE)
   36.83 -    begin
   36.84 -        muliplicand <= {`LM32_WORD_WIDTH{1'b0}};
   36.85 -        multiplier <= {`LM32_WORD_WIDTH{1'b0}};
   36.86 -        product <= {`LM32_WORD_WIDTH{1'b0}};
   36.87 -        result <= {`LM32_WORD_WIDTH{1'b0}};
   36.88 -    end
   36.89 -    else
   36.90 -    begin
   36.91 -        if (stall_x == `FALSE)
   36.92 -        begin    
   36.93 -            muliplicand <= operand_0;
   36.94 -            multiplier <= operand_1;
   36.95 -        end
   36.96 -        if (stall_m == `FALSE)
   36.97 -            product <= muliplicand * multiplier;
   36.98 -        result <= product;
   36.99 -    end
  36.100 -end
  36.101 -
  36.102 -endmodule

    37.1 --- a/lm32_ram.v	Sun Mar 06 21:17:31 2011 +0000
    37.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    37.3 @@ -1,294 +0,0 @@
    37.4 -// =============================================================================
    37.5 -//                           COPYRIGHT NOTICE
    37.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation
    37.7 -// ALL RIGHTS RESERVED
    37.8 -// This confidential and proprietary software may be used only as authorised by
    37.9 -// a licensing agreement from Lattice Semiconductor Corporation.
   37.10 -// The entire notice above must be reproduced on all authorized copies and
   37.11 -// copies may only be made to the extent permitted by a licensing agreement from
   37.12 -// Lattice Semiconductor Corporation.
   37.13 -//
   37.14 -// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
   37.15 -// 5555 NE Moore Court                            408-826-6000 (other locations)
   37.16 -// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
   37.17 -// U.S.A                                   email: techsupport@latticesemi.com
   37.18 -// =============================================================================/
   37.19 -//                         FILE DETAILS
   37.20 -// Project          : LatticeMico32
   37.21 -// File             : lm32_ram.v
   37.22 -// Title            : Pseudo dual-port RAM.
   37.23 -// Version          : 6.1.17
   37.24 -//                  : Initial Release
   37.25 -// Version          : 7.0SP2, 3.0
   37.26 -//                  : No Change
   37.27 -// Version          : 3.1
   37.28 -//                  : Options added to select EBRs (True-DP, Psuedo-DP, DQ, or
   37.29 -//                  : Distributed RAM).
   37.30 -// Version          : 3.2
   37.31 -//                  : EBRs use SYNC resets instead of ASYNC resets.
   37.32 -// Version          : 3.5
   37.33 -//                  : Added read-after-write hazard resolution when using true
   37.34 -//                  : dual-port EBRs
   37.35 -// =============================================================================
   37.36 -
   37.37 -`include "lm32_include.v"
   37.38 -
   37.39 -/////////////////////////////////////////////////////
   37.40 -// Module interface
   37.41 -/////////////////////////////////////////////////////
   37.42 -
   37.43 -module lm32_ram 
   37.44 -  (
   37.45 -   // ----- Inputs -------
   37.46 -   read_clk,
   37.47 -   write_clk,
   37.48 -   reset,
   37.49 -   enable_read,
   37.50 -   read_address,
   37.51 -   enable_write,
   37.52 -   write_address,
   37.53 -   write_data,
   37.54 -   write_enable,
   37.55 -   // ----- Outputs -------
   37.56 -   read_data
   37.57 -   );
   37.58 -   
   37.59 -   /*----------------------------------------------------------------------
   37.60 -    Parameters
   37.61 -    ----------------------------------------------------------------------*/
   37.62 -   parameter data_width = 1;               // Width of the data ports
   37.63 -   parameter address_width = 1;            // Width of the address ports
   37.64 -`ifdef PLATFORM_LATTICE
   37.65 -   parameter RAM_IMPLEMENTATION = "AUTO";  // Implement memory in EBRs, else
   37.66 -                                           // let synthesis tool select best 
   37.67 -                                           // possible solution (EBR or LUT)
   37.68 -   parameter RAM_TYPE = "RAM_DP";          // Type of EBR to be used
   37.69 -`endif
   37.70 -   
   37.71 -   /*----------------------------------------------------------------------
   37.72 -    Inputs
   37.73 -    ----------------------------------------------------------------------*/
   37.74 -   input read_clk;                         // Read clock
   37.75 -   input write_clk;                        // Write clock
   37.76 -   input reset;                            // Reset
   37.77 -   
   37.78 -   input enable_read;                      // Access enable
   37.79 -   input [address_width-1:0] read_address; // Read/write address
   37.80 -   input enable_write;                     // Access enable
   37.81 -   input [address_width-1:0] write_address;// Read/write address
   37.82 -   input [data_width-1:0] write_data;      // Data to write to specified address
   37.83 -   input write_enable;                     // Write enable
   37.84 -   
   37.85 -   /*----------------------------------------------------------------------
   37.86 -    Outputs
   37.87 -    ----------------------------------------------------------------------*/
   37.88 -   output [data_width-1:0] read_data;      // Data read from specified addess
   37.89 -   wire   [data_width-1:0] read_data;
   37.90 -
   37.91 -`ifdef PLATFORM_LATTICE
   37.92 -   generate
   37.93 -      
   37.94 -      if ( RAM_IMPLEMENTATION == "EBR" )
   37.95 -	begin
   37.96 -	   if ( RAM_TYPE == "RAM_DP" )
   37.97 -	     begin
   37.98 -		pmi_ram_dp 
   37.99 -		  #( 
  37.100 -		     // ----- Parameters -----
  37.101 -		     .pmi_wr_addr_depth(1<<address_width),
  37.102 -		     .pmi_wr_addr_width(address_width),
  37.103 -		     .pmi_wr_data_width(data_width),
  37.104 -		     .pmi_rd_addr_depth(1<<address_width),
  37.105 -		     .pmi_rd_addr_width(address_width),
  37.106 -		     .pmi_rd_data_width(data_width),
  37.107 -		     .pmi_regmode("noreg"),
  37.108 -		     .pmi_gsr("enable"),
  37.109 -		     .pmi_resetmode("sync"),
  37.110 -		     .pmi_init_file("none"),
  37.111 -		     .pmi_init_file_format("binary"),
  37.112 -		     .pmi_family(`LATTICE_FAMILY),
  37.113 -		     .module_type("pmi_ram_dp")
  37.114 -		     )
  37.115 -		lm32_ram_inst
  37.116 -		  (
  37.117 -		   // ----- Inputs -----
  37.118 -		   .Data(write_data),
  37.119 -		   .WrAddress(write_address),
  37.120 -		   .RdAddress(read_address),
  37.121 -		   .WrClock(write_clk),
  37.122 -		   .RdClock(read_clk),
  37.123 -		   .WrClockEn(enable_write),
  37.124 -		   .RdClockEn(enable_read),
  37.125 -		   .WE(write_enable),
  37.126 -		   .Reset(reset),
  37.127 -		   // ----- Outputs -----
  37.128 -		   .Q(read_data)
  37.129 -		   );
  37.130 -	     end
  37.131 -	   else
  37.132 -	     begin
  37.133 -		// True Dual-Port EBR
  37.134 -		wire   [data_width-1:0] read_data_A, read_data_B;
  37.135 -		reg [data_width-1:0] 	raw_data, raw_data_nxt;
  37.136 -		reg 			raw, raw_nxt;
  37.137 -		
  37.138 -		/*----------------------------------------------------------------------
  37.139 -		 Is a read being performed in the same cycle as a write? Indicate this
  37.140 -		 event with a RAW hazard signal that is released only when a new read
  37.141 -		 or write occurs later.
  37.142 -		 ----------------------------------------------------------------------*/
  37.143 -		always @(/*AUTOSENSE*/enable_read or enable_write
  37.144 -			 or raw or raw_data or read_address
  37.145 -			 or write_address or write_data
  37.146 -			 or write_enable)
  37.147 -		  if (// Read
  37.148 -		      enable_read
  37.149 -		      // Write
  37.150 -		      && enable_write && write_enable
  37.151 -		      // Read and write address match
  37.152 -		      && (read_address == write_address))
  37.153 -		    begin
  37.154 -		       raw_data_nxt = write_data;
  37.155 -		       raw_nxt = 1'b1;
  37.156 -		    end
  37.157 -		  else
  37.158 -		    if (raw && (enable_read == 1'b0) && (enable_write == 1'b0))
  37.159 -		      begin
  37.160 -			 raw_data_nxt = raw_data;
  37.161 -			 raw_nxt = 1'b1;
  37.162 -		      end
  37.163 -		    else
  37.164 -		      begin
  37.165 -			 raw_data_nxt = raw_data;
  37.166 -			 raw_nxt = 1'b0;
  37.167 -		      end
  37.168 -		
  37.169 -		// Send back write data in case of a RAW hazard; else send back
  37.170 -		// data from memory
  37.171 -		assign read_data = raw ? raw_data : read_data_B;
  37.172 -		
  37.173 -		/*----------------------------------------------------------------------
  37.174 -		 Sequential Logic
  37.175 -		 ----------------------------------------------------------------------*/
  37.176 -		always @(posedge read_clk)
  37.177 -		  if (reset)
  37.178 -		    begin
  37.179 -		       raw_data <= #1 0;
  37.180 -		       raw <= #1 1'b0;
  37.181 -		    end
  37.182 -		  else
  37.183 -		    begin
  37.184 -		       raw_data <= #1 raw_data_nxt;
  37.185 -		       raw <= #1 raw_nxt;
  37.186 -		    end
  37.187 -		
  37.188 -		pmi_ram_dp_true 
  37.189 -		  #( 
  37.190 -		     // ----- Parameters -----
  37.191 -		     .pmi_addr_depth_a(1<<address_width),
  37.192 -		     .pmi_addr_width_a(address_width),
  37.193 -		     .pmi_data_width_a(data_width),
  37.194 -		     .pmi_addr_depth_b(1<<address_width),
  37.195 -		     .pmi_addr_width_b(address_width),
  37.196 -		     .pmi_data_width_b(data_width),
  37.197 -		     .pmi_regmode_a("noreg"),
  37.198 -		     .pmi_regmode_b("noreg"),
  37.199 -		     .pmi_gsr("enable"),
  37.200 -		     .pmi_resetmode("sync"),
  37.201 -		     .pmi_init_file("none"),
  37.202 -		     .pmi_init_file_format("binary"),
  37.203 -		     .pmi_family(`LATTICE_FAMILY),
  37.204 -		     .module_type("pmi_ram_dp_true")
  37.205 -		     )
  37.206 -		lm32_ram_inst
  37.207 -		  (
  37.208 -		   // ----- Inputs -----
  37.209 -		   .DataInA(write_data),
  37.210 -		   .DataInB(write_data),
  37.211 -		   .AddressA(write_address),
  37.212 -		   .AddressB(read_address),
  37.213 -		   .ClockA(write_clk),
  37.214 -		   .ClockB(read_clk),
  37.215 -		   .ClockEnA(enable_write),
  37.216 -		   .ClockEnB(enable_read),
  37.217 -		   .WrA(write_enable),
  37.218 -		   .WrB(`FALSE),
  37.219 -		   .ResetA(reset),
  37.220 -		   .ResetB(reset),
  37.221 -		   // ----- Outputs -----
  37.222 -		   .QA(read_data_A),
  37.223 -		   .QB(read_data_B)
  37.224 -		   );
  37.225 -	     end
  37.226 -	end
  37.227 -	else if ( RAM_IMPLEMENTATION == "SLICE" )
  37.228 -	  begin
  37.229 -	     reg [address_width-1:0] ra; // Registered read address
  37.230 -	     
  37.231 -	     pmi_distributed_dpram 
  37.232 -	       #(
  37.233 -		 // ----- Parameters -----
  37.234 -		 .pmi_addr_depth(1<<address_width),
  37.235 -		 .pmi_addr_width(address_width),
  37.236 -		 .pmi_data_width(data_width),
  37.237 -		 .pmi_regmode("noreg"),
  37.238 -		 .pmi_init_file("none"),
  37.239 -		 .pmi_init_file_format("binary"),
  37.240 -		 .pmi_family(`LATTICE_FAMILY),
  37.241 -		 .module_type("pmi_distributed_dpram")
  37.242 -		 )
  37.243 -	     pmi_distributed_dpram_inst
  37.244 -	       (
  37.245 -		// ----- Inputs -----
  37.246 -		.WrAddress(write_address),
  37.247 -		.Data(write_data),
  37.248 -		.WrClock(write_clk),
  37.249 -		.WE(write_enable),
  37.250 -		.WrClockEn(enable_write),
  37.251 -		.RdAddress(ra),
  37.252 -		.RdClock(read_clk),
  37.253 -		.RdClockEn(enable_read),
  37.254 -		.Reset(reset),
  37.255 -		// ----- Outputs -----
  37.256 -		.Q(read_data)
  37.257 -		);
  37.258 -	     
  37.259 -	     always @(posedge read_clk)
  37.260 -	       if (enable_read)
  37.261 -		 ra <= read_address;
  37.262 -	  end
  37.263 -      
  37.264 -	else 
  37.265 -	  begin
  37.266 -`endif
  37.267 -	     /*----------------------------------------------------------------------
  37.268 -	      Internal nets and registers
  37.269 -	      ----------------------------------------------------------------------*/
  37.270 -	     reg [data_width-1:0]    mem[0:(1<<address_width)-1]; // The RAM
  37.271 -	     reg [address_width-1:0] ra; // Registered read address
  37.272 -	     
  37.273 -	     /*----------------------------------------------------------------------
  37.274 -	      Combinational Logic
  37.275 -	      ----------------------------------------------------------------------*/
  37.276 -	     // Read port
  37.277 -	     assign read_data = mem[ra]; 
  37.278 -	     
  37.279 -	     /*----------------------------------------------------------------------
  37.280 -	      Sequential Logic
  37.281 -	      ----------------------------------------------------------------------*/
  37.282 -	     // Write port
  37.283 -	     always @(posedge write_clk)
  37.284 -	       if ((write_enable == `TRUE) && (enable_write == `TRUE))
  37.285 -		 mem[write_address] <= write_data; 
  37.286 -	     
  37.287 -	     // Register read address for use on next cycle
  37.288 -	     always @(posedge read_clk)
  37.289 -	       if (enable_read)
  37.290 -		 ra <= read_address;
  37.291 -	     
  37.292 -`ifdef PLATFORM_LATTICE
  37.293 -	  end
  37.294 -
  37.295 -   endgenerate
  37.296 -`endif
  37.297 -endmodule

    38.1 --- a/lm32_shifter.v	Sun Mar 06 21:17:31 2011 +0000
    38.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    38.3 @@ -1,134 +0,0 @@
    38.4 -// =============================================================================
    38.5 -//                           COPYRIGHT NOTICE
    38.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation
    38.7 -// ALL RIGHTS RESERVED
    38.8 -// This confidential and proprietary software may be used only as authorised by
    38.9 -// a licensing agreement from Lattice Semiconductor Corporation.
   38.10 -// The entire notice above must be reproduced on all authorized copies and
   38.11 -// copies may only be made to the extent permitted by a licensing agreement from
   38.12 -// Lattice Semiconductor Corporation.
   38.13 -//
   38.14 -// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
   38.15 -// 5555 NE Moore Court                            408-826-6000 (other locations)
   38.16 -// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
   38.17 -// U.S.A                                   email: techsupport@latticesemi.com
   38.18 -// =============================================================================/
   38.19 -//                         FILE DETAILS
   38.20 -// Project          : LatticeMico32
   38.21 -// File             : lm32_shifter.v
   38.22 -// Title            : Barrel shifter
   38.23 -// Dependencies     : lm32_include.v
   38.24 -// Version          : 6.1.17
   38.25 -//                  : Initial Release
   38.26 -// Version          : 7.0SP2, 3.0
   38.27 -//                  : No Change
   38.28 -// Version          : 3.1
   38.29 -//                  : No Change
   38.30 -// =============================================================================
   38.31 -
   38.32 -`include "lm32_include.v"
   38.33 -
   38.34 -/////////////////////////////////////////////////////
   38.35 -// Module interface
   38.36 -/////////////////////////////////////////////////////
   38.37 -
   38.38 -module lm32_shifter (
   38.39 -    // ----- Inputs -------
   38.40 -    clk_i,
   38.41 -    rst_i,
   38.42 -    stall_x,
   38.43 -    direction_x,
   38.44 -    sign_extend_x,
   38.45 -    operand_0_x,
   38.46 -    operand_1_x,
   38.47 -    // ----- Outputs -------
   38.48 -    shifter_result_m
   38.49 -    );
   38.50 -
   38.51 -/////////////////////////////////////////////////////
   38.52 -// Inputs
   38.53 -/////////////////////////////////////////////////////
   38.54 -
   38.55 -input clk_i;                                // Clock
   38.56 -input rst_i;                                // Reset
   38.57 -input stall_x;                              // Stall instruction in X stage
   38.58 -input direction_x;                          // Direction to shift
   38.59 -input sign_extend_x;                        // Whether shift is arithmetic (1'b1) or logical (1'b0)
   38.60 -input [`LM32_WORD_RNG] operand_0_x;         // Operand to shift
   38.61 -input [`LM32_WORD_RNG] operand_1_x;         // Operand that specifies how many bits to shift by
   38.62 -
   38.63 -/////////////////////////////////////////////////////
   38.64 -// Outputs
   38.65 -/////////////////////////////////////////////////////
   38.66 -
   38.67 -output [`LM32_WORD_RNG] shifter_result_m;   // Result of shift
   38.68 -wire   [`LM32_WORD_RNG] shifter_result_m;
   38.69 -
   38.70 -/////////////////////////////////////////////////////
   38.71 -// Internal nets and registers 
   38.72 -/////////////////////////////////////////////////////
   38.73 -
   38.74 -reg direction_m;
   38.75 -reg [`LM32_WORD_RNG] left_shift_result;
   38.76 -reg [`LM32_WORD_RNG] right_shift_result;
   38.77 -reg [`LM32_WORD_RNG] left_shift_operand;
   38.78 -wire [`LM32_WORD_RNG] right_shift_operand;
   38.79 -wire fill_value;
   38.80 -wire [`LM32_WORD_RNG] right_shift_in;
   38.81 -
   38.82 -integer shift_idx_0;
   38.83 -integer shift_idx_1;
   38.84 -
   38.85 -/////////////////////////////////////////////////////
   38.86 -// Combinational Logic
   38.87 -/////////////////////////////////////////////////////
   38.88 -    
   38.89 -// Select operands - To perform a left shift, we reverse the bits and perform a right shift
   38.90 -always @(*)
   38.91 -begin
   38.92 -    for (shift_idx_0 = 0; shift_idx_0 < `LM32_WORD_WIDTH; shift_idx_0 = shift_idx_0 + 1)
   38.93 -        left_shift_operand[`LM32_WORD_WIDTH-1-shift_idx_0] = operand_0_x[shift_idx_0];
   38.94 -end
   38.95 -assign right_shift_operand = direction_x == `LM32_SHIFT_OP_LEFT ? left_shift_operand : operand_0_x;
   38.96 -
   38.97 -// Determine fill value for right shift - Sign bit for arithmetic shift, or zero for logical shift
   38.98 -assign fill_value = (sign_extend_x == `TRUE) && (direction_x == `LM32_SHIFT_OP_RIGHT) 
   38.99 -                      ? operand_0_x[`LM32_WORD_WIDTH-1] 
  38.100 -                      : 1'b0;
  38.101 -
  38.102 -// Determine bits to shift in for right shift or rotate
  38.103 -assign right_shift_in = {`LM32_WORD_WIDTH{fill_value}};
  38.104 -
  38.105 -// Reverse bits to get left shift result
  38.106 -always @(*)
  38.107 -begin
  38.108 -    for (shift_idx_1 = 0; shift_idx_1 < `LM32_WORD_WIDTH; shift_idx_1 = shift_idx_1 + 1)
  38.109 -        left_shift_result[`LM32_WORD_WIDTH-1-shift_idx_1] = right_shift_result[shift_idx_1];
  38.110 -end
  38.111 -
  38.112 -// Select result 
  38.113 -assign shifter_result_m = direction_m == `LM32_SHIFT_OP_LEFT ? left_shift_result : right_shift_result;
  38.114 -    
  38.115 -/////////////////////////////////////////////////////
  38.116 -// Sequential Logic
  38.117 -/////////////////////////////////////////////////////
  38.118 -
  38.119 -// Perform right shift
  38.120 -always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  38.121 -begin
  38.122 -    if (rst_i == `TRUE)
  38.123 -    begin
  38.124 -        right_shift_result <= {`LM32_WORD_WIDTH{1'b0}};
  38.125 -        direction_m <= `FALSE;
  38.126 -    end
  38.127 -    else
  38.128 -    begin
  38.129 -        if (stall_x == `FALSE)
  38.130 -        begin
  38.131 -            right_shift_result <= {right_shift_in, right_shift_operand} >> operand_1_x[`LM32_SHIFT_RNG];
  38.132 -            direction_m <= direction_x;
  38.133 -        end
  38.134 -    end
  38.135 -end 
  38.136 -    
  38.137 -endmodule

    39.1 --- a/lm32_top.v	Sun Mar 06 21:17:31 2011 +0000
    39.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    39.3 @@ -1,355 +0,0 @@
    39.4 -// =============================================================================
    39.5 -//                           COPYRIGHT NOTICE
    39.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation
    39.7 -// ALL RIGHTS RESERVED
    39.8 -// This confidential and proprietary software may be used only as authorised by
    39.9 -// a licensing agreement from Lattice Semiconductor Corporation.
   39.10 -// The entire notice above must be reproduced on all authorized copies and
   39.11 -// copies may only be made to the extent permitted by a licensing agreement from
   39.12 -// Lattice Semiconductor Corporation.
   39.13 -//
   39.14 -// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
   39.15 -// 5555 NE Moore Court                            408-826-6000 (other locations)
   39.16 -// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
   39.17 -// U.S.A                                   email: techsupport@latticesemi.com
   39.18 -// =============================================================================/
   39.19 -//                         FILE DETAILS
   39.20 -// Project          : LatticeMico32
   39.21 -// File             : lm32_top.v
   39.22 -// Title            : Top-level of CPU.
   39.23 -// Dependencies     : lm32_include.v
   39.24 -// Version          : 6.1.17
   39.25 -//                  : removed SPI - 04/12/07
   39.26 -// Version          : 7.0SP2, 3.0
   39.27 -//                  : No Change
   39.28 -// Version          : 3.1
   39.29 -//                  : No Change
   39.30 -// =============================================================================
   39.31 -
   39.32 -`include "lm32_include.v"
   39.33 -
   39.34 -/////////////////////////////////////////////////////
   39.35 -// Module interface
   39.36 -/////////////////////////////////////////////////////
   39.37 -
   39.38 -module lm32_top (
   39.39 -    // ----- Inputs -------
   39.40 -    clk_i,
   39.41 -    rst_i,
   39.42 -    // From external devices
   39.43 -`ifdef CFG_INTERRUPTS_ENABLED
   39.44 -    interrupt,
   39.45 -`endif
   39.46 -    // From user logic
   39.47 -`ifdef CFG_USER_ENABLED
   39.48 -    user_result,
   39.49 -    user_complete,
   39.50 -`endif     
   39.51 -`ifdef CFG_IWB_ENABLED
   39.52 -    // Instruction Wishbone master
   39.53 -    I_DAT_I,
   39.54 -    I_ACK_I,
   39.55 -    I_ERR_I,
   39.56 -    I_RTY_I,
   39.57 -`endif
   39.58 -    // Data Wishbone master
   39.59 -    D_DAT_I,
   39.60 -    D_ACK_I,
   39.61 -    D_ERR_I,
   39.62 -    D_RTY_I,
   39.63 -    // ----- Outputs -------
   39.64 -`ifdef CFG_USER_ENABLED    
   39.65 -    user_valid,
   39.66 -    user_opcode,
   39.67 -    user_operand_0,
   39.68 -    user_operand_1,
   39.69 -`endif    
   39.70 -`ifdef CFG_IWB_ENABLED
   39.71 -    // Instruction Wishbone master
   39.72 -    I_DAT_O,
   39.73 -    I_ADR_O,
   39.74 -    I_CYC_O,
   39.75 -    I_SEL_O,
   39.76 -    I_STB_O,
   39.77 -    I_WE_O,
   39.78 -    I_CTI_O,
   39.79 -    I_LOCK_O,
   39.80 -    I_BTE_O,
   39.81 -`endif
   39.82 -    // Data Wishbone master
   39.83 -    D_DAT_O,
   39.84 -    D_ADR_O,
   39.85 -    D_CYC_O,
   39.86 -    D_SEL_O,
   39.87 -    D_STB_O,
   39.88 -    D_WE_O,
   39.89 -    D_CTI_O,
   39.90 -    D_LOCK_O,
   39.91 -    D_BTE_O
   39.92 -    );
   39.93 -
   39.94 -/////////////////////////////////////////////////////
   39.95 -// Inputs
   39.96 -/////////////////////////////////////////////////////
   39.97 -
   39.98 -input clk_i;                                    // Clock
   39.99 -input rst_i;                                    // Reset
  39.100 -
  39.101 -`ifdef CFG_INTERRUPTS_ENABLED
  39.102 -input [`LM32_INTERRUPT_RNG] interrupt;          // Interrupt pins
  39.103 -`endif
  39.104 -
  39.105 -`ifdef CFG_USER_ENABLED
  39.106 -input [`LM32_WORD_RNG] user_result;             // User-defined instruction result
  39.107 -input user_complete;                            // Indicates the user-defined instruction result is valid
  39.108 -`endif    
  39.109 -
  39.110 -`ifdef CFG_IWB_ENABLED
  39.111 -input [`LM32_WORD_RNG] I_DAT_I;                 // Instruction Wishbone interface read data
  39.112 -input I_ACK_I;                                  // Instruction Wishbone interface acknowledgement
  39.113 -input I_ERR_I;                                  // Instruction Wishbone interface error
  39.114 -input I_RTY_I;                                  // Instruction Wishbone interface retry
  39.115 -`endif
  39.116 -
  39.117 -input [`LM32_WORD_RNG] D_DAT_I;                 // Data Wishbone interface read data
  39.118 -input D_ACK_I;                                  // Data Wishbone interface acknowledgement
  39.119 -input D_ERR_I;                                  // Data Wishbone interface error
  39.120 -input D_RTY_I;                                  // Data Wishbone interface retry
  39.121 -
  39.122 -/////////////////////////////////////////////////////
  39.123 -// Outputs
  39.124 -/////////////////////////////////////////////////////
  39.125 -
  39.126 -`ifdef CFG_USER_ENABLED
  39.127 -output user_valid;                              // Indicates that user_opcode and user_operand_* are valid
  39.128 -wire   user_valid;
  39.129 -output [`LM32_USER_OPCODE_RNG] user_opcode;     // User-defined instruction opcode
  39.130 -reg    [`LM32_USER_OPCODE_RNG] user_opcode;
  39.131 -output [`LM32_WORD_RNG] user_operand_0;         // First operand for user-defined instruction
  39.132 -wire   [`LM32_WORD_RNG] user_operand_0;
  39.133 -output [`LM32_WORD_RNG] user_operand_1;         // Second operand for user-defined instruction
  39.134 -wire   [`LM32_WORD_RNG] user_operand_1;
  39.135 -`endif
  39.136 -
  39.137 -`ifdef CFG_IWB_ENABLED
  39.138 -output [`LM32_WORD_RNG] I_DAT_O;                // Instruction Wishbone interface write data
  39.139 -wire   [`LM32_WORD_RNG] I_DAT_O;
  39.140 -output [`LM32_WORD_RNG] I_ADR_O;                // Instruction Wishbone interface address
  39.141 -wire   [`LM32_WORD_RNG] I_ADR_O;
  39.142 -output I_CYC_O;                                 // Instruction Wishbone interface cycle
  39.143 -wire   I_CYC_O;
  39.144 -output [`LM32_BYTE_SELECT_RNG] I_SEL_O;         // Instruction Wishbone interface byte select
  39.145 -wire   [`LM32_BYTE_SELECT_RNG] I_SEL_O;
  39.146 -output I_STB_O;                                 // Instruction Wishbone interface strobe
  39.147 -wire   I_STB_O;
  39.148 -output I_WE_O;                                  // Instruction Wishbone interface write enable
  39.149 -wire   I_WE_O;
  39.150 -output [`LM32_CTYPE_RNG] I_CTI_O;               // Instruction Wishbone interface cycle type 
  39.151 -wire   [`LM32_CTYPE_RNG] I_CTI_O;
  39.152 -output I_LOCK_O;                                // Instruction Wishbone interface lock bus
  39.153 -wire   I_LOCK_O;
  39.154 -output [`LM32_BTYPE_RNG] I_BTE_O;               // Instruction Wishbone interface burst type 
  39.155 -wire   [`LM32_BTYPE_RNG] I_BTE_O;
  39.156 -`endif
  39.157 -
  39.158 -output [`LM32_WORD_RNG] D_DAT_O;                // Data Wishbone interface write data
  39.159 -wire   [`LM32_WORD_RNG] D_DAT_O;
  39.160 -output [`LM32_WORD_RNG] D_ADR_O;                // Data Wishbone interface address
  39.161 -wire   [`LM32_WORD_RNG] D_ADR_O;
  39.162 -output D_CYC_O;                                 // Data Wishbone interface cycle
  39.163 -wire   D_CYC_O;
  39.164 -output [`LM32_BYTE_SELECT_RNG] D_SEL_O;         // Data Wishbone interface byte select
  39.165 -wire   [`LM32_BYTE_SELECT_RNG] D_SEL_O;
  39.166 -output D_STB_O;                                 // Data Wishbone interface strobe
  39.167 -wire   D_STB_O;
  39.168 -output D_WE_O;                                  // Data Wishbone interface write enable
  39.169 -wire   D_WE_O;
  39.170 -output [`LM32_CTYPE_RNG] D_CTI_O;               // Data Wishbone interface cycle type 
  39.171 -wire   [`LM32_CTYPE_RNG] D_CTI_O;
  39.172 -output D_LOCK_O;                                // Date Wishbone interface lock bus
  39.173 -wire   D_LOCK_O;
  39.174 -output [`LM32_BTYPE_RNG] D_BTE_O;               // Data Wishbone interface burst type 
  39.175 -wire   [`LM32_BTYPE_RNG] D_BTE_O;
  39.176 -  
  39.177 -/////////////////////////////////////////////////////
  39.178 -// Internal nets and registers 
  39.179 -/////////////////////////////////////////////////////
  39.180 - 
  39.181 -`ifdef CFG_JTAG_ENABLED
  39.182 -// Signals between JTAG interface and CPU
  39.183 -wire [`LM32_BYTE_RNG] jtag_reg_d;
  39.184 -wire [`LM32_BYTE_RNG] jtag_reg_q;
  39.185 -wire jtag_update;
  39.186 -wire [2:0] jtag_reg_addr_d;
  39.187 -wire [2:0] jtag_reg_addr_q;
  39.188 -wire jtck;
  39.189 -wire jrstn;
  39.190 -`endif
  39.191 -
  39.192 -// TODO: get the trace signals out
  39.193 -`ifdef CFG_TRACE_ENABLED
  39.194 -// PC trace signals
  39.195 -wire [`LM32_PC_RNG] trace_pc;                   // PC to trace (address of next non-sequential instruction)
  39.196 -wire trace_pc_valid;                            // Indicates that a new trace PC is valid
  39.197 -wire trace_exception;                           // Indicates an exception has occured
  39.198 -wire [`LM32_EID_RNG] trace_eid;                 // Indicates what type of exception has occured
  39.199 -wire trace_eret;                                // Indicates an eret instruction has been executed
  39.200 -`ifdef CFG_DEBUG_ENABLED
  39.201 -wire trace_bret;                                // Indicates a bret instruction has been executed
  39.202 -`endif
  39.203 -`endif
  39.204 -
  39.205 -/////////////////////////////////////////////////////
  39.206 -// Functions
  39.207 -/////////////////////////////////////////////////////
  39.208 -
  39.209 -`include "lm32_functions.v"
  39.210 -/////////////////////////////////////////////////////
  39.211 -// Instantiations
  39.212 -///////////////////////////////////////////////////// 
  39.213 -
  39.214 -// LM32 CPU
  39.215 -lm32_cpu cpu (
  39.216 -    // ----- Inputs -------
  39.217 -    .clk_i                 (clk_i),
  39.218 -`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
  39.219 -    .clk_n_i               (clk_n),
  39.220 -`endif
  39.221 -    .rst_i                 (rst_i),
  39.222 -    // From external devices
  39.223 -`ifdef CFG_INTERRUPTS_ENABLED
  39.224 -    .interrupt             (interrupt),
  39.225 -`endif
  39.226 -    // From user logic
  39.227 -`ifdef CFG_USER_ENABLED
  39.228 -    .user_result           (user_result),
  39.229 -    .user_complete         (user_complete),
  39.230 -`endif     
  39.231 -`ifdef CFG_JTAG_ENABLED
  39.232 -    // From JTAG
  39.233 -    .jtag_clk              (jtck),
  39.234 -    .jtag_update           (jtag_update),
  39.235 -    .jtag_reg_q            (jtag_reg_q),
  39.236 -    .jtag_reg_addr_q       (jtag_reg_addr_q),
  39.237 -`endif
  39.238 -`ifdef CFG_IWB_ENABLED
  39.239 -     // Instruction Wishbone master
  39.240 -    .I_DAT_I               (I_DAT_I),
  39.241 -    .I_ACK_I               (I_ACK_I),
  39.242 -    .I_ERR_I               (I_ERR_I),
  39.243 -    .I_RTY_I               (I_RTY_I),
  39.244 -`endif
  39.245 -    // Data Wishbone master
  39.246 -    .D_DAT_I               (D_DAT_I),
  39.247 -    .D_ACK_I               (D_ACK_I),
  39.248 -    .D_ERR_I               (D_ERR_I),
  39.249 -    .D_RTY_I               (D_RTY_I),
  39.250 -    // ----- Outputs -------
  39.251 -`ifdef CFG_TRACE_ENABLED
  39.252 -    .trace_pc              (trace_pc),
  39.253 -    .trace_pc_valid        (trace_pc_valid),
  39.254 -    .trace_exception       (trace_exception),
  39.255 -    .trace_eid             (trace_eid),
  39.256 -    .trace_eret            (trace_eret),
  39.257 -`ifdef CFG_DEBUG_ENABLED
  39.258 -    .trace_bret            (trace_bret),
  39.259 -`endif
  39.260 -`endif
  39.261 -`ifdef CFG_JTAG_ENABLED
  39.262 -    .jtag_reg_d            (jtag_reg_d),
  39.263 -    .jtag_reg_addr_d       (jtag_reg_addr_d),
  39.264 -`endif
  39.265 -`ifdef CFG_USER_ENABLED    
  39.266 -    .user_valid            (user_valid),
  39.267 -    .user_opcode           (user_opcode),
  39.268 -    .user_operand_0        (user_operand_0),
  39.269 -    .user_operand_1        (user_operand_1),
  39.270 -`endif    
  39.271 -`ifdef CFG_IWB_ENABLED
  39.272 -    // Instruction Wishbone master
  39.273 -    .I_DAT_O               (I_DAT_O),
  39.274 -    .I_ADR_O               (I_ADR_O),
  39.275 -    .I_CYC_O               (I_CYC_O),
  39.276 -    .I_SEL_O               (I_SEL_O),
  39.277 -    .I_STB_O               (I_STB_O),
  39.278 -    .I_WE_O                (I_WE_O),
  39.279 -    .I_CTI_O               (I_CTI_O),
  39.280 -    .I_LOCK_O              (I_LOCK_O),
  39.281 -    .I_BTE_O               (I_BTE_O),
  39.282 -    `endif
  39.283 -    // Data Wishbone master
  39.284 -    .D_DAT_O               (D_DAT_O),
  39.285 -    .D_ADR_O               (D_ADR_O),
  39.286 -    .D_CYC_O               (D_CYC_O),
  39.287 -    .D_SEL_O               (D_SEL_O),
  39.288 -    .D_STB_O               (D_STB_O),
  39.289 -    .D_WE_O                (D_WE_O),
  39.290 -    .D_CTI_O               (D_CTI_O),
  39.291 -    .D_LOCK_O              (D_LOCK_O),
  39.292 -    .D_BTE_O               (D_BTE_O)
  39.293 -    );
  39.294 -
  39.295 -   wire TRACE_ACK_O;
  39.296 -   wire [`LM32_WORD_RNG] TRACE_DAT_O;
  39.297 -`ifdef CFG_TRACE_ENABLED
  39.298 -   lm32_trace trace_module (.clk_i	(clk_i),
  39.299 -			    .rst_i	(rst_i),
  39.300 -			    .stb_i	(DEBUG_STB_I & DEBUG_ADR_I[13]),
  39.301 -			    .we_i	(DEBUG_WE_I),
  39.302 -			    .sel_i	(DEBUG_SEL_I),
  39.303 -			    .dat_i	(DEBUG_DAT_I),
  39.304 -			    .adr_i	(DEBUG_ADR_I),
  39.305 -			    .trace_pc	(trace_pc),
  39.306 -			    .trace_eid	(trace_eid),
  39.307 -			    .trace_eret (trace_eret),
  39.308 -			    .trace_bret (trace_bret),
  39.309 -			    .trace_pc_valid (trace_pc_valid),
  39.310 -			    .trace_exception (trace_exception),
  39.311 -			    .ack_o	(TRACE_ACK_O),
  39.312 -			    .dat_o 	(TRACE_DAT_O));   
  39.313 -`else
  39.314 -   assign 		 TRACE_ACK_O = 0;
  39.315 -   assign 		 TRACE_DAT_O = 0;   
  39.316 -`endif   
  39.317 -`ifdef DEBUG_ROM
  39.318 -   wire ROM_ACK_O;
  39.319 -   wire [`LM32_WORD_RNG] ROM_DAT_O;
  39.320 -
  39.321 -   assign DEBUG_ACK_O = DEBUG_ADR_I[13] ? TRACE_ACK_O : ROM_ACK_O;
  39.322 -   assign DEBUG_DAT_O = DEBUG_ADR_I[13] ? TRACE_DAT_O : ROM_DAT_O;
  39.323 -   
  39.324 -   // ROM monitor
  39.325 -   lm32_monitor debug_rom (
  39.326 -			   // ----- Inputs -------
  39.327 -			   .clk_i                 (clk_i),
  39.328 -			   .rst_i                 (rst_i),
  39.329 -			   .MON_ADR_I             (DEBUG_ADR_I[10:2]),
  39.330 -			   .MON_STB_I             (DEBUG_STB_I & ~DEBUG_ADR_I[13]),
  39.331 -			   .MON_CYC_I             (DEBUG_CYC_I & ~DEBUG_ADR_I[13]),
  39.332 -			   .MON_WE_I              (DEBUG_WE_I),
  39.333 -			   .MON_SEL_I             (DEBUG_SEL_I),
  39.334 -			   .MON_DAT_I             (DEBUG_DAT_I),
  39.335 -			   // ----- Outputs ------    
  39.336 -			   .MON_RTY_O             (DEBUG_RTY_O),
  39.337 -			   .MON_ERR_O             (DEBUG_ERR_O),
  39.338 -			   .MON_ACK_O             (ROM_ACK_O),
  39.339 -			   .MON_DAT_O             (ROM_DAT_O)
  39.340 -			   );
  39.341 -`endif 
  39.342 -   
  39.343 -`ifdef CFG_JTAG_ENABLED		   
  39.344 -// JTAG cores 
  39.345 -jtag_cores jtag_cores (
  39.346 -    // ----- Inputs -----
  39.347 -    .reg_d                 (jtag_reg_d),
  39.348 -    .reg_addr_d            (jtag_reg_addr_d),
  39.349 -    // ----- Outputs -----
  39.350 -    .reg_update            (jtag_update),
  39.351 -    .reg_q                 (jtag_reg_q),
  39.352 -    .reg_addr_q            (jtag_reg_addr_q),
  39.353 -    .jtck                  (jtck),
  39.354 -    .jrstn                 (jrstn)
  39.355 -    );
  39.356 -`endif        
  39.357 -   
  39.358 -endmodule

    40.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    40.2 +++ b/rtl/jtag_cores.v	Tue Mar 08 09:40:42 2011 +0000
    40.3 @@ -0,0 +1,66 @@
    40.4 +// Modified by GSI to use simple positive edge clocking and the JTAG capture state
    40.5 +
    40.6 +module jtag_cores (
    40.7 +    input [7:0] reg_d,
    40.8 +    input [2:0] reg_addr_d,
    40.9 +    output reg_update,
   40.10 +    output [7:0] reg_q,
   40.11 +    output [2:0] reg_addr_q,
   40.12 +    output jtck,
   40.13 +    output jrstn
   40.14 +);
   40.15 +
   40.16 +wire tck;
   40.17 +wire tdi;
   40.18 +wire tdo;
   40.19 +wire capture;
   40.20 +wire shift;
   40.21 +wire update;
   40.22 +wire e1dr;
   40.23 +wire reset;
   40.24 +
   40.25 +jtag_tap jtag_tap (
   40.26 +	.tck(tck),
   40.27 +	.tdi(tdi),
   40.28 +	.tdo(tdo),
   40.29 +	.capture(capture),
   40.30 +	.shift(shift),
   40.31 +	.e1dr(e1dr),
   40.32 +	.update(update),
   40.33 +	.reset(reset)
   40.34 +);
   40.35 +
   40.36 +reg [10:0] jtag_shift;
   40.37 +reg [10:0] jtag_latched;
   40.38 +
   40.39 +always @(posedge tck)
   40.40 +begin
   40.41 +	if(reset)
   40.42 +		jtag_shift <= 11'b0;
   40.43 +	else begin
   40.44 +		if (shift)
   40.45 +			jtag_shift <= {tdi, jtag_shift[10:1]};
   40.46 +		else if (capture)
   40.47 +			jtag_shift <= {reg_d, reg_addr_d};
   40.48 +	end
   40.49 +end
   40.50 +
   40.51 +assign tdo = jtag_shift[0];
   40.52 +
   40.53 +always @(posedge tck)
   40.54 +begin
   40.55 +	if(reset)
   40.56 +		jtag_latched <= 11'b0;
   40.57 +	else begin
   40.58 +	   if (e1dr)
   40.59 +		   jtag_latched <= jtag_shift;
   40.60 +	end
   40.61 +end
   40.62 +
   40.63 +assign reg_update = update;
   40.64 +assign reg_q = jtag_latched[10:3];
   40.65 +assign reg_addr_q = jtag_latched[2:0];
   40.66 +assign jtck = tck;
   40.67 +assign jrstn = ~reset;
   40.68 +
   40.69 +endmodule

    41.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    41.2 +++ b/rtl/jtag_tap_altera.v	Tue Mar 08 09:40:42 2011 +0000
    41.3 @@ -0,0 +1,59 @@
    41.4 +module jtag_tap(
    41.5 +  output tck,
    41.6 +  output tdi,
    41.7 +  input tdo,
    41.8 +  output capture,
    41.9 +  output shift,
   41.10 +  output e1dr,
   41.11 +  output update,
   41.12 +  output reset
   41.13 +);
   41.14 +
   41.15 +assign reset = 0;
   41.16 +wire nil1, nil2, nil3, nil4;
   41.17 +
   41.18 +sld_virtual_jtag altera_jtag(
   41.19 +  .ir_in       		(),
   41.20 +  .ir_out		(),
   41.21 +  .tck			(tck),
   41.22 +  .tdo			(tdo),
   41.23 +  .tdi			(tdi),
   41.24 +  .virtual_state_cdr	(capture),
   41.25 +  .virtual_state_sdr	(shift),
   41.26 +  .virtual_state_e1dr	(e1dr),
   41.27 +  .virtual_state_pdr	(nil1),
   41.28 +  .virtual_state_e2dr	(nil2),
   41.29 +  .virtual_state_udr	(update),
   41.30 +  .virtual_state_cir	(nil3),
   41.31 +  .virtual_state_uir	(nil4)
   41.32 +  // synopsys translate_off
   41.33 +  ,
   41.34 +  .jtag_state_cdr	(),
   41.35 +  .jtag_state_cir	(),
   41.36 +  .jtag_state_e1dr	(),
   41.37 +  .jtag_state_e1ir	(),
   41.38 +  .jtag_state_e2dr	(),
   41.39 +  .jtag_state_e2ir	(),
   41.40 +  .jtag_state_pdr	(),
   41.41 +  .jtag_state_pir	(),
   41.42 +  .jtag_state_rti	(),
   41.43 +  .jtag_state_sdr	(),
   41.44 +  .jtag_state_sdrs	(),
   41.45 +  .jtag_state_sir	(),
   41.46 +  .jtag_state_sirs	(),
   41.47 +  .jtag_state_tlr	(),
   41.48 +  .jtag_state_udr	(),
   41.49 +  .jtag_state_uir	(),
   41.50 +  .tms			()
   41.51 +  // synopsys translate_on
   41.52 +  );
   41.53 +
   41.54 +defparam
   41.55 +   altera_jtag.sld_auto_instance_index = "YES",
   41.56 +   altera_jtag.sld_instance_index = 0,
   41.57 +   altera_jtag.sld_ir_width = 1,
   41.58 +   altera_jtag.sld_sim_action = "",
   41.59 +   altera_jtag.sld_sim_n_scan = 0,
   41.60 +   altera_jtag.sld_sim_total_length = 0;
   41.61 +
   41.62 +endmodule

    42.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    42.2 +++ b/rtl/jtag_tap_xilinx_spartan6.v	Tue Mar 08 09:40:42 2011 +0000
    42.3 @@ -0,0 +1,43 @@
    42.4 +
    42.5 +module jtag_tap(
    42.6 +	output tck,
    42.7 +	output tdi,
    42.8 +	input tdo,
    42.9 +	output capture,
   42.10 +	output shift,
   42.11 +	output e1dr,
   42.12 +	output update,
   42.13 +	output reset
   42.14 +);
   42.15 +
   42.16 +// Unfortunately the exit1 state for DR (e1dr) is mising
   42.17 +// We can simulate it by interpretting 'update' as e1dr and delaying 'update'
   42.18 +wire g_capture;
   42.19 +wire g_shift;
   42.20 +wire g_update;
   42.21 +reg update_delay;
   42.22 +
   42.23 +assign capture = g_capture & sel;
   42.24 +assign shift = g_shift & sel;
   42.25 +assign e1dr = g_update & sel;
   42.26 +assign update = update_delay;
   42.27 +
   42.28 +BSCAN_SPARTAN6 #(
   42.29 +	.JTAG_CHAIN(1)
   42.30 +) bscan (
   42.31 +	.CAPTURE(g_capture),
   42.32 +	.DRCK(tck),
   42.33 +	.RESET(reset),
   42.34 +	.RUNTEST(),
   42.35 +	.SEL(sel),
   42.36 +	.SHIFT(g_shift),
   42.37 +	.TCK(),
   42.38 +	.TDI(tdi),
   42.39 +	.TMS(),
   42.40 +	.UPDATE(g_update),
   42.41 +	.TDO(tdo)
   42.42 +);
   42.43 +
   42.44 +update_delay <= g_update;
   42.45 +
   42.46 +endmodule

    43.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    43.2 +++ b/rtl/lm32_adder.v	Tue Mar 08 09:40:42 2011 +0000
    43.3 @@ -0,0 +1,115 @@
    43.4 +// =============================================================================
    43.5 +//                           COPYRIGHT NOTICE
    43.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation
    43.7 +// ALL RIGHTS RESERVED
    43.8 +// This confidential and proprietary software may be used only as authorised by
    43.9 +// a licensing agreement from Lattice Semiconductor Corporation.
   43.10 +// The entire notice above must be reproduced on all authorized copies and
   43.11 +// copies may only be made to the extent permitted by a licensing agreement from
   43.12 +// Lattice Semiconductor Corporation.
   43.13 +//
   43.14 +// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
   43.15 +// 5555 NE Moore Court                            408-826-6000 (other locations)
   43.16 +// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
   43.17 +// U.S.A                                   email: techsupport@latticesemi.com
   43.18 +// ============================================================================/
   43.19 +//                         FILE DETAILS
   43.20 +// Project          : LatticeMico32
   43.21 +// File             : lm32_adder.v
   43.22 +// Title            : Integer adder / subtractor with comparison flag generation 
   43.23 +// Dependencies     : lm32_include.v
   43.24 +// Version          : 6.1.17
   43.25 +//                  : Initial Release
   43.26 +// Version          : 7.0SP2, 3.0
   43.27 +//                  : No Change
   43.28 +// Version          : 3.1
   43.29 +//                  : No Change
   43.30 +// =============================================================================
   43.31 +
   43.32 +`include "lm32_include.v"
   43.33 +
   43.34 +/////////////////////////////////////////////////////
   43.35 +// Module interface
   43.36 +/////////////////////////////////////////////////////
   43.37 +
   43.38 +module lm32_adder (
   43.39 +    // ----- Inputs -------
   43.40 +    adder_op_x,
   43.41 +    adder_op_x_n,
   43.42 +    operand_0_x,
   43.43 +    operand_1_x,
   43.44 +    // ----- Outputs -------
   43.45 +    adder_result_x,
   43.46 +    adder_carry_n_x,
   43.47 +    adder_overflow_x
   43.48 +    );
   43.49 +
   43.50 +/////////////////////////////////////////////////////
   43.51 +// Inputs
   43.52 +/////////////////////////////////////////////////////
   43.53 +
   43.54 +input adder_op_x;                                       // Operating to perform, 0 for addition, 1 for subtraction
   43.55 +input adder_op_x_n;                                     // Inverted version of adder_op_x
   43.56 +input [`LM32_WORD_RNG] operand_0_x;                     // Operand to add, or subtract from
   43.57 +input [`LM32_WORD_RNG] operand_1_x;                     // Opearnd to add, or subtract by
   43.58 +
   43.59 +/////////////////////////////////////////////////////
   43.60 +// Outputs
   43.61 +/////////////////////////////////////////////////////
   43.62 +
   43.63 +output [`LM32_WORD_RNG] adder_result_x;                 // Result of addition or subtraction
   43.64 +wire   [`LM32_WORD_RNG] adder_result_x;
   43.65 +output adder_carry_n_x;                                 // Inverted carry
   43.66 +wire   adder_carry_n_x;
   43.67 +output adder_overflow_x;                                // Indicates if overflow occured, only valid for subtractions
   43.68 +reg    adder_overflow_x;
   43.69 +    
   43.70 +/////////////////////////////////////////////////////
   43.71 +// Internal nets and registers 
   43.72 +/////////////////////////////////////////////////////
   43.73 +
   43.74 +wire a_sign;                                            // Sign (i.e. positive or negative) of operand 0
   43.75 +wire b_sign;                                            // Sign of operand 1
   43.76 +wire result_sign;                                       // Sign of result
   43.77 +
   43.78 +/////////////////////////////////////////////////////
   43.79 +// Instantiations 
   43.80 +/////////////////////////////////////////////////////
   43.81 +
   43.82 +lm32_addsub addsub (
   43.83 +    // ----- Inputs -----
   43.84 +    .DataA          (operand_0_x), 
   43.85 +    .DataB          (operand_1_x), 
   43.86 +    .Cin            (adder_op_x), 
   43.87 +    .Add_Sub        (adder_op_x_n), 
   43.88 +    // ----- Ouputs -----
   43.89 +    .Result         (adder_result_x), 
   43.90 +    .Cout           (adder_carry_n_x)
   43.91 +    );
   43.92 +
   43.93 +/////////////////////////////////////////////////////
   43.94 +// Combinational Logic
   43.95 +/////////////////////////////////////////////////////
   43.96 +
   43.97 +// Extract signs of operands and result
   43.98 +
   43.99 +assign a_sign = operand_0_x[`LM32_WORD_WIDTH-1];
  43.100 +assign b_sign = operand_1_x[`LM32_WORD_WIDTH-1];
  43.101 +assign result_sign = adder_result_x[`LM32_WORD_WIDTH-1];
  43.102 +
  43.103 +// Determine whether an overflow occured when performing a subtraction
  43.104 +
  43.105 +always @(*)
  43.106 +begin    
  43.107 +    //  +ve - -ve = -ve -> overflow
  43.108 +    //  -ve - +ve = +ve -> overflow
  43.109 +    if  (   (!a_sign & b_sign & result_sign)
  43.110 +         || (a_sign & !b_sign & !result_sign)
  43.111 +        )
  43.112 +        adder_overflow_x = `TRUE;
  43.113 +    else
  43.114 +        adder_overflow_x = `FALSE;
  43.115 +end
  43.116 +    
  43.117 +endmodule
  43.118 +

    44.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    44.2 +++ b/rtl/lm32_addsub.v	Tue Mar 08 09:40:42 2011 +0000
    44.3 @@ -0,0 +1,98 @@
    44.4 +// =============================================================================
    44.5 +//                           COPYRIGHT NOTICE
    44.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation
    44.7 +// ALL RIGHTS RESERVED
    44.8 +// This confidential and proprietary software may be used only as authorised by
    44.9 +// a licensing agreement from Lattice Semiconductor Corporation.
   44.10 +// The entire notice above must be reproduced on all authorized copies and
   44.11 +// copies may only be made to the extent permitted by a licensing agreement from
   44.12 +// Lattice Semiconductor Corporation.
   44.13 +//
   44.14 +// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
   44.15 +// 5555 NE Moore Court                            408-826-6000 (other locations)
   44.16 +// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
   44.17 +// U.S.A                                   email: techsupport@latticesemi.com
   44.18 +// =============================================================================/
   44.19 +//                         FILE DETAILS
   44.20 +// Project          : LatticeMico32
   44.21 +// File             : lm32_addsub.v
   44.22 +// Title            : PMI adder/subtractor.
   44.23 +// Version          : 6.1.17
   44.24 +//                  : Initial Release
   44.25 +// Version          : 7.0SP2, 3.0
   44.26 +//                  : No Change
   44.27 +// Version          : 3.1
   44.28 +//                  : No Change
   44.29 +// =============================================================================
   44.30 +
   44.31 +`include "lm32_include.v"
   44.32 +
   44.33 +/////////////////////////////////////////////////////
   44.34 +// Module interface
   44.35 +/////////////////////////////////////////////////////
   44.36 +
   44.37 +module lm32_addsub (
   44.38 +    // ----- Inputs -------
   44.39 +    DataA, 
   44.40 +    DataB, 
   44.41 +    Cin, 
   44.42 +    Add_Sub, 
   44.43 +    // ----- Outputs -------
   44.44 +    Result, 
   44.45 +    Cout
   44.46 +    );
   44.47 +
   44.48 +/////////////////////////////////////////////////////
   44.49 +// Inputs
   44.50 +/////////////////////////////////////////////////////
   44.51 +
   44.52 +input [31:0] DataA;
   44.53 +input [31:0] DataB;
   44.54 +input Cin;
   44.55 +input Add_Sub;
   44.56 +
   44.57 +/////////////////////////////////////////////////////
   44.58 +// Outputs
   44.59 +/////////////////////////////////////////////////////
   44.60 +
   44.61 +output [31:0] Result;
   44.62 +wire   [31:0] Result;
   44.63 +output Cout;
   44.64 +wire   Cout;
   44.65 +
   44.66 +/////////////////////////////////////////////////////
   44.67 +// Instantiations
   44.68 +///////////////////////////////////////////////////// 
   44.69 +
   44.70 +// Only use Lattice specific constructs when compiling with ispLEVER
   44.71 +`ifdef PLATFORM_LATTICE
   44.72 +       generate
   44.73 +	  if (`LATTICE_FAMILY == "SC" || `LATTICE_FAMILY == "SCM") begin
   44.74 +`endif
   44.75 +	     wire [32:0] tmp_addResult = DataA + DataB + Cin;
   44.76 +	     wire [32:0] tmp_subResult = DataA - DataB - !Cin;   
   44.77 +   
   44.78 +	     assign  Result = (Add_Sub == 1) ? tmp_addResult[31:0] : tmp_subResult[31:0];
   44.79 +	     assign  Cout = (Add_Sub == 1) ? tmp_addResult[32] : !tmp_subResult[32];
   44.80 +`ifdef PLATFORM_LATTICE
   44.81 +	  end else begin
   44.82 +	    pmi_addsub #(// ----- Parameters -------
   44.83 +			 .pmi_data_width     (32),
   44.84 +			 .pmi_result_width   (32),
   44.85 +			 .pmi_sign           ("off"),
   44.86 +			 .pmi_family         (`LATTICE_FAMILY),
   44.87 +			 .module_type        ("pmi_addsub")) 
   44.88 +	      addsub    (// ----- Inputs -------
   44.89 +			 .DataA              (DataA),
   44.90 +			 .DataB              (DataB),
   44.91 +			 .Cin                (Cin),
   44.92 +			 .Add_Sub            (Add_Sub),
   44.93 +			 // ----- Outputs -------
   44.94 +			 .Result             (Result),
   44.95 +			 .Cout               (Cout),
   44.96 +			 .Overflow           ());
   44.97 +	  end
   44.98 +       endgenerate 
   44.99 +`endif
  44.100 +
  44.101 +endmodule

    45.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    45.2 +++ b/rtl/lm32_cpu.v	Tue Mar 08 09:40:42 2011 +0000
    45.3 @@ -0,0 +1,2717 @@
    45.4 +// =============================================================================
    45.5 +//                           COPYRIGHT NOTICE
    45.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation
    45.7 +// ALL RIGHTS RESERVED
    45.8 +// This confidential and proprietary software may be used only as authorised by
    45.9 +// a licensing agreement from Lattice Semiconductor Corporation.
   45.10 +// The entire notice above must be reproduced on all authorized copies and
   45.11 +// copies may only be made to the extent permitted by a licensing agreement from
   45.12 +// Lattice Semiconductor Corporation.
   45.13 +//
   45.14 +// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
   45.15 +// 5555 NE Moore Court                            408-826-6000 (other locations)
   45.16 +// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
   45.17 +// U.S.A                                   email: techsupport@latticesemi.com
   45.18 +// =============================================================================/
   45.19 +//                         FILE DETAILS
   45.20 +// Project          : LatticeMico32
   45.21 +// File             : lm32_cpu.v
   45.22 +// Title            : Top-level of CPU.
   45.23 +// Dependencies     : lm32_include.v
   45.24 +//
   45.25 +// Version 3.4
   45.26 +// 1. Bug Fix: In a tight infinite loop (add, sw, bi) incoming interrupts were 
   45.27 +//    never serviced.
   45.28 +//    
   45.29 +// Version 3.3
   45.30 +// 1. Feature: Support for memory that is tightly coupled to processor core, and 
   45.31 +//    has a single-cycle access latency (same as caches). Instruction port has
   45.32 +//    access to a dedicated physically-mapped memory. Data port has access to
   45.33 +//    a dedicated physically-mapped memory. In order to be able to manipulate
   45.34 +//    values in both these memories via the debugger, these memories also
   45.35 +//    interface with the data port of LM32.
   45.36 +// 2. Feature: Extended Configuration Register
   45.37 +// 3. Bug Fix: Removed port names that conflict with keywords reserved in System-
   45.38 +//    Verilog.
   45.39 +//
   45.40 +// Version 3.2
   45.41 +// 1. Bug Fix: Single-stepping a load/store to invalid address causes debugger to
   45.42 +//    hang. At the same time CPU fails to register data bus error exception. Bug
   45.43 +//    is caused because (a) data bus error exception occurs after load/store has
   45.44 +//    passed X stage and next sequential instruction (e.g., brk) is already in X
   45.45 +//    stage, and (b) data bus error exception had lower priority than, say, brk
   45.46 +//    exception.
   45.47 +// 2. Bug Fix: If a brk (or scall/eret/bret) sequentially follows a load/store to
   45.48 +//    invalid location, CPU will fail to register data bus error exception. The
   45.49 +//    solution is to stall scall/eret/bret/brk instructions in D pipeline stage
   45.50 +//    until load/store has completed.
   45.51 +// 3. Feature: Enable precise identification of load/store that causes seg fault.
   45.52 +// 4. SYNC resets used for register file when implemented in EBRs.
   45.53 +//
   45.54 +// Version 3.1
   45.55 +// 1. Feature: LM32 Register File can now be mapped in to on-chip block RAM (EBR)
   45.56 +//    instead of distributed memory by enabling the option in LM32 GUI. 
   45.57 +// 2. Feature: LM32 also adds a static branch predictor to improve branch 
   45.58 +//    performance. All immediate-based forward-pointing branches are predicted 
   45.59 +//    not-taken. All immediate-based backward-pointing branches are predicted taken.
   45.60 +// 
   45.61 +// Version 7.0SP2, 3.0
   45.62 +// No Change
   45.63 +//
   45.64 +// Version 6.1.17
   45.65 +// Initial Release
   45.66 +// =============================================================================
   45.67 +
   45.68 +`include "lm32_include.v"
   45.69 +
   45.70 +/////////////////////////////////////////////////////
   45.71 +// Module interface
   45.72 +/////////////////////////////////////////////////////
   45.73 +
   45.74 +module lm32_cpu (
   45.75 +    // ----- Inputs -------
   45.76 +    clk_i,
   45.77 +`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
   45.78 +    clk_n_i,
   45.79 +`endif    
   45.80 +    rst_i,
   45.81 +    // From external devices
   45.82 +`ifdef CFG_INTERRUPTS_ENABLED
   45.83 +    interrupt,
   45.84 +`endif
   45.85 +    // From user logic
   45.86 +`ifdef CFG_USER_ENABLED
   45.87 +    user_result,
   45.88 +    user_complete,
   45.89 +`endif     
   45.90 +`ifdef CFG_JTAG_ENABLED
   45.91 +    // From JTAG
   45.92 +    jtag_clk,
   45.93 +    jtag_update, 
   45.94 +    jtag_reg_q,
   45.95 +    jtag_reg_addr_q,
   45.96 +`endif
   45.97 +`ifdef CFG_IWB_ENABLED
   45.98 +    // Instruction Wishbone master
   45.99 +    I_DAT_I,
  45.100 +    I_ACK_I,
  45.101 +    I_ERR_I,
  45.102 +    I_RTY_I,
  45.103 +`endif
  45.104 +    // Data Wishbone master
  45.105 +    D_DAT_I,
  45.106 +    D_ACK_I,
  45.107 +    D_ERR_I,
  45.108 +    D_RTY_I,
  45.109 +    // ----- Outputs -------
  45.110 +`ifdef CFG_TRACE_ENABLED
  45.111 +    trace_pc,
  45.112 +    trace_pc_valid,
  45.113 +    trace_exception,
  45.114 +    trace_eid,
  45.115 +    trace_eret,
  45.116 +`ifdef CFG_DEBUG_ENABLED
  45.117 +    trace_bret,
  45.118 +`endif
  45.119 +`endif
  45.120 +`ifdef CFG_JTAG_ENABLED
  45.121 +    jtag_reg_d,
  45.122 +    jtag_reg_addr_d,
  45.123 +`endif
  45.124 +`ifdef CFG_USER_ENABLED    
  45.125 +    user_valid,
  45.126 +    user_opcode,
  45.127 +    user_operand_0,
  45.128 +    user_operand_1,
  45.129 +`endif    
  45.130 +`ifdef CFG_IWB_ENABLED
  45.131 +    // Instruction Wishbone master
  45.132 +    I_DAT_O,
  45.133 +    I_ADR_O,
  45.134 +    I_CYC_O,
  45.135 +    I_SEL_O,
  45.136 +    I_STB_O,
  45.137 +    I_WE_O,
  45.138 +    I_CTI_O,
  45.139 +    I_LOCK_O,
  45.140 +    I_BTE_O,
  45.141 +`endif
  45.142 +    // Data Wishbone master
  45.143 +    D_DAT_O,
  45.144 +    D_ADR_O,
  45.145 +    D_CYC_O,
  45.146 +    D_SEL_O,
  45.147 +    D_STB_O,
  45.148 +    D_WE_O,
  45.149 +    D_CTI_O,
  45.150 +    D_LOCK_O,
  45.151 +    D_BTE_O
  45.152 +    );
  45.153 +
  45.154 +/////////////////////////////////////////////////////
  45.155 +// Parameters
  45.156 +/////////////////////////////////////////////////////
  45.157 +
  45.158 +parameter eba_reset = `CFG_EBA_RESET;                           // Reset value for EBA CSR
  45.159 +`ifdef CFG_DEBUG_ENABLED
  45.160 +parameter deba_reset = `CFG_DEBA_RESET;                         // Reset value for DEBA CSR
  45.161 +`endif
  45.162 +
  45.163 +`ifdef CFG_ICACHE_ENABLED
  45.164 +parameter icache_associativity = `CFG_ICACHE_ASSOCIATIVITY;     // Associativity of the cache (Number of ways)
  45.165 +parameter icache_sets = `CFG_ICACHE_SETS;                       // Number of sets
  45.166 +parameter icache_bytes_per_line = `CFG_ICACHE_BYTES_PER_LINE;   // Number of bytes per cache line
  45.167 +parameter icache_base_address = `CFG_ICACHE_BASE_ADDRESS;       // Base address of cachable memory
  45.168 +parameter icache_limit = `CFG_ICACHE_LIMIT;                     // Limit (highest address) of cachable memory
  45.169 +`else
  45.170 +parameter icache_associativity = 1;    
  45.171 +parameter icache_sets = 512;                      
  45.172 +parameter icache_bytes_per_line = 16;  
  45.173 +parameter icache_base_address = 0;      
  45.174 +parameter icache_limit = 0;                    
  45.175 +`endif
  45.176 +
  45.177 +`ifdef CFG_DCACHE_ENABLED
  45.178 +parameter dcache_associativity = `CFG_DCACHE_ASSOCIATIVITY;     // Associativity of the cache (Number of ways)
  45.179 +parameter dcache_sets = `CFG_DCACHE_SETS;                       // Number of sets
  45.180 +parameter dcache_bytes_per_line = `CFG_DCACHE_BYTES_PER_LINE;   // Number of bytes per cache line
  45.181 +parameter dcache_base_address = `CFG_DCACHE_BASE_ADDRESS;       // Base address of cachable memory
  45.182 +parameter dcache_limit = `CFG_DCACHE_LIMIT;                     // Limit (highest address) of cachable memory
  45.183 +`else
  45.184 +parameter dcache_associativity = 1;    
  45.185 +parameter dcache_sets = 512;                      
  45.186 +parameter dcache_bytes_per_line = 16;  
  45.187 +parameter dcache_base_address = 0;      
  45.188 +parameter dcache_limit = 0;                    
  45.189 +`endif
  45.190 +
  45.191 +`ifdef CFG_DEBUG_ENABLED
  45.192 +parameter watchpoints = `CFG_WATCHPOINTS;                       // Number of h/w watchpoint CSRs
  45.193 +`else
  45.194 +parameter watchpoints = 0;
  45.195 +`endif
  45.196 +`ifdef CFG_ROM_DEBUG_ENABLED
  45.197 +parameter breakpoints = `CFG_BREAKPOINTS;                       // Number of h/w breakpoint CSRs
  45.198 +`else
  45.199 +parameter breakpoints = 0;
  45.200 +`endif
  45.201 +
  45.202 +`ifdef CFG_INTERRUPTS_ENABLED
  45.203 +parameter interrupts = `CFG_INTERRUPTS;                         // Number of interrupts
  45.204 +`else
  45.205 +parameter interrupts = 0;
  45.206 +`endif
  45.207 +
  45.208 +/////////////////////////////////////////////////////
  45.209 +// Inputs
  45.210 +/////////////////////////////////////////////////////
  45.211 +
  45.212 +input clk_i;                                    // Clock
  45.213 +`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
  45.214 +input clk_n_i;                                  // Inverted clock
  45.215 +`endif    
  45.216 +input rst_i;                                    // Reset
  45.217 +
  45.218 +`ifdef CFG_INTERRUPTS_ENABLED
  45.219 +input [`LM32_INTERRUPT_RNG] interrupt;          // Interrupt pins
  45.220 +`endif
  45.221 +
  45.222 +`ifdef CFG_USER_ENABLED
  45.223 +input [`LM32_WORD_RNG] user_result;             // User-defined instruction result
  45.224 +input user_complete;                            // User-defined instruction execution is complete
  45.225 +`endif    
  45.226 +
  45.227 +`ifdef CFG_JTAG_ENABLED
  45.228 +input jtag_clk;                                 // JTAG clock
  45.229 +input jtag_update;                              // JTAG state machine is in data register update state
  45.230 +input [`LM32_BYTE_RNG] jtag_reg_q;              
  45.231 +input [2:0] jtag_reg_addr_q;
  45.232 +`endif
  45.233 +
  45.234 +`ifdef CFG_IWB_ENABLED
  45.235 +input [`LM32_WORD_RNG] I_DAT_I;                 // Instruction Wishbone interface read data
  45.236 +input I_ACK_I;                                  // Instruction Wishbone interface acknowledgement
  45.237 +input I_ERR_I;                                  // Instruction Wishbone interface error
  45.238 +input I_RTY_I;                                  // Instruction Wishbone interface retry
  45.239 +`endif
  45.240 +
  45.241 +input [`LM32_WORD_RNG] D_DAT_I;                 // Data Wishbone interface read data
  45.242 +input D_ACK_I;                                  // Data Wishbone interface acknowledgement
  45.243 +input D_ERR_I;                                  // Data Wishbone interface error
  45.244 +input D_RTY_I;                                  // Data Wishbone interface retry
  45.245 +
  45.246 +/////////////////////////////////////////////////////
  45.247 +// Outputs
  45.248 +/////////////////////////////////////////////////////
  45.249 +
  45.250 +`ifdef CFG_TRACE_ENABLED
  45.251 +output [`LM32_PC_RNG] trace_pc;                 // PC to trace
  45.252 +reg    [`LM32_PC_RNG] trace_pc;
  45.253 +output trace_pc_valid;                          // Indicates that a new trace PC is valid
  45.254 +reg    trace_pc_valid;
  45.255 +output trace_exception;                         // Indicates an exception has occured
  45.256 +reg    trace_exception;
  45.257 +output [`LM32_EID_RNG] trace_eid;               // Indicates what type of exception has occured
  45.258 +reg    [`LM32_EID_RNG] trace_eid;
  45.259 +output trace_eret;                              // Indicates an eret instruction has been executed
  45.260 +reg    trace_eret;
  45.261 +`ifdef CFG_DEBUG_ENABLED
  45.262 +output trace_bret;                              // Indicates a bret instruction has been executed
  45.263 +reg    trace_bret;
  45.264 +`endif
  45.265 +`endif
  45.266 +
  45.267 +`ifdef CFG_JTAG_ENABLED
  45.268 +output [`LM32_BYTE_RNG] jtag_reg_d;
  45.269 +wire   [`LM32_BYTE_RNG] jtag_reg_d;
  45.270 +output [2:0] jtag_reg_addr_d;
  45.271 +wire   [2:0] jtag_reg_addr_d;
  45.272 +`endif
  45.273 +
  45.274 +`ifdef CFG_USER_ENABLED
  45.275 +output user_valid;                              // Indicates if user_opcode is valid
  45.276 +wire   user_valid;
  45.277 +output [`LM32_USER_OPCODE_RNG] user_opcode;     // User-defined instruction opcode
  45.278 +reg    [`LM32_USER_OPCODE_RNG] user_opcode;
  45.279 +output [`LM32_WORD_RNG] user_operand_0;         // First operand for user-defined instruction
  45.280 +wire   [`LM32_WORD_RNG] user_operand_0;
  45.281 +output [`LM32_WORD_RNG] user_operand_1;         // Second operand for user-defined instruction
  45.282 +wire   [`LM32_WORD_RNG] user_operand_1;
  45.283 +`endif
  45.284 +
  45.285 +`ifdef CFG_IWB_ENABLED
  45.286 +output [`LM32_WORD_RNG] I_DAT_O;                // Instruction Wishbone interface write data
  45.287 +wire   [`LM32_WORD_RNG] I_DAT_O;
  45.288 +output [`LM32_WORD_RNG] I_ADR_O;                // Instruction Wishbone interface address
  45.289 +wire   [`LM32_WORD_RNG] I_ADR_O;
  45.290 +output I_CYC_O;                                 // Instruction Wishbone interface cycle
  45.291 +wire   I_CYC_O;
  45.292 +output [`LM32_BYTE_SELECT_RNG] I_SEL_O;         // Instruction Wishbone interface byte select
  45.293 +wire   [`LM32_BYTE_SELECT_RNG] I_SEL_O;
  45.294 +output I_STB_O;                                 // Instruction Wishbone interface strobe
  45.295 +wire   I_STB_O;
  45.296 +output I_WE_O;                                  // Instruction Wishbone interface write enable
  45.297 +wire   I_WE_O;
  45.298 +output [`LM32_CTYPE_RNG] I_CTI_O;               // Instruction Wishbone interface cycle type 
  45.299 +wire   [`LM32_CTYPE_RNG] I_CTI_O;
  45.300 +output I_LOCK_O;                                // Instruction Wishbone interface lock bus
  45.301 +wire   I_LOCK_O;
  45.302 +output [`LM32_BTYPE_RNG] I_BTE_O;               // Instruction Wishbone interface burst type 
  45.303 +wire   [`LM32_BTYPE_RNG] I_BTE_O;
  45.304 +`endif
  45.305 +
  45.306 +output [`LM32_WORD_RNG] D_DAT_O;                // Data Wishbone interface write data
  45.307 +wire   [`LM32_WORD_RNG] D_DAT_O;
  45.308 +output [`LM32_WORD_RNG] D_ADR_O;                // Data Wishbone interface address
  45.309 +wire   [`LM32_WORD_RNG] D_ADR_O;
  45.310 +output D_CYC_O;                                 // Data Wishbone interface cycle
  45.311 +wire   D_CYC_O;
  45.312 +output [`LM32_BYTE_SELECT_RNG] D_SEL_O;         // Data Wishbone interface byte select
  45.313 +wire   [`LM32_BYTE_SELECT_RNG] D_SEL_O;
  45.314 +output D_STB_O;                                 // Data Wishbone interface strobe
  45.315 +wire   D_STB_O;
  45.316 +output D_WE_O;                                  // Data Wishbone interface write enable
  45.317 +wire   D_WE_O;
  45.318 +output [`LM32_CTYPE_RNG] D_CTI_O;               // Data Wishbone interface cycle type 
  45.319 +wire   [`LM32_CTYPE_RNG] D_CTI_O;
  45.320 +output D_LOCK_O;                                // Date Wishbone interface lock bus
  45.321 +wire   D_LOCK_O;
  45.322 +output [`LM32_BTYPE_RNG] D_BTE_O;               // Data Wishbone interface burst type 
  45.323 +wire   [`LM32_BTYPE_RNG] D_BTE_O;
  45.324 +
  45.325 +/////////////////////////////////////////////////////
  45.326 +// Internal nets and registers 
  45.327 +/////////////////////////////////////////////////////
  45.328 +
  45.329 +// Pipeline registers
  45.330 +
  45.331 +`ifdef LM32_CACHE_ENABLED
  45.332 +reg valid_a;                                    // Instruction in A stage is valid
  45.333 +`endif
  45.334 +reg valid_f;                                    // Instruction in F stage is valid
  45.335 +reg valid_d;                                    // Instruction in D stage is valid
  45.336 +reg valid_x;                                    // Instruction in X stage is valid
  45.337 +reg valid_m;                                    // Instruction in M stage is valid
  45.338 +reg valid_w;                                    // Instruction in W stage is valid
  45.339 +   
  45.340 +wire q_x;
  45.341 +wire [`LM32_WORD_RNG] immediate_d;              // Immediate operand
  45.342 +wire load_d;                                    // Indicates a load instruction
  45.343 +reg load_x;                                     
  45.344 +reg load_m;
  45.345 +wire load_q_x;
  45.346 +wire store_q_x;
  45.347 +wire store_d;                                   // Indicates a store instruction
  45.348 +reg store_x;
  45.349 +reg store_m;
  45.350 +wire [`LM32_SIZE_RNG] size_d;                   // Size of load/store (byte, hword, word)
  45.351 +reg [`LM32_SIZE_RNG] size_x;
  45.352 +wire branch_d;                                  // Indicates a branch instruction
  45.353 +wire branch_predict_d;                          // Indicates a branch is predicted
  45.354 +wire branch_predict_taken_d;                    // Indicates a branch is predicted taken
  45.355 +wire [`LM32_PC_RNG] branch_predict_address_d;   // Address to which predicted branch jumps
  45.356 +wire [`LM32_PC_RNG] branch_target_d;
  45.357 +wire bi_unconditional;
  45.358 +wire bi_conditional;
  45.359 +reg branch_x;                                   
  45.360 +reg branch_predict_x;
  45.361 +reg branch_predict_taken_x;
  45.362 +reg branch_m;
  45.363 +reg branch_predict_m;
  45.364 +reg branch_predict_taken_m;
  45.365 +wire branch_mispredict_taken_m;                 // Indicates a branch was mispredicted as taken
  45.366 +wire branch_flushX_m;                           // Indicates that instruction in X stage must be squashed
  45.367 +wire branch_reg_d;                              // Branch to register or immediate
  45.368 +wire [`LM32_PC_RNG] branch_offset_d;            // Branch offset for immediate branches
  45.369 +reg [`LM32_PC_RNG] branch_target_x;             // Address to branch to
  45.370 +reg [`LM32_PC_RNG] branch_target_m;
  45.371 +wire [`LM32_D_RESULT_SEL_0_RNG] d_result_sel_0_d; // Which result should be selected in D stage for operand 0
  45.372 +wire [`LM32_D_RESULT_SEL_1_RNG] d_result_sel_1_d; // Which result should be selected in D stage for operand 1
  45.373 +
  45.374 +wire x_result_sel_csr_d;                        // Select X stage result from CSRs
  45.375 +reg x_result_sel_csr_x;
  45.376 +`ifdef LM32_MC_ARITHMETIC_ENABLED
  45.377 +wire x_result_sel_mc_arith_d;                   // Select X stage result from multi-cycle arithmetic unit
  45.378 +reg x_result_sel_mc_arith_x;
  45.379 +`endif
  45.380 +`ifdef LM32_NO_BARREL_SHIFT    
  45.381 +wire x_result_sel_shift_d;                      // Select X stage result from shifter
  45.382 +reg x_result_sel_shift_x;
  45.383 +`endif
  45.384 +`ifdef CFG_SIGN_EXTEND_ENABLED
  45.385 +wire x_result_sel_sext_d;                       // Select X stage result from sign-extend logic
  45.386 +reg x_result_sel_sext_x;
  45.387 +`endif
  45.388 +wire x_result_sel_logic_d;                      // Select X stage result from logic op unit
  45.389 +reg x_result_sel_logic_x;
  45.390 +`ifdef CFG_USER_ENABLED
  45.391 +wire x_result_sel_user_d;                       // Select X stage result from user-defined logic
  45.392 +reg x_result_sel_user_x;
  45.393 +`endif
  45.394 +wire x_result_sel_add_d;                        // Select X stage result from adder
  45.395 +reg x_result_sel_add_x;
  45.396 +wire m_result_sel_compare_d;                    // Select M stage result from comparison logic
  45.397 +reg m_result_sel_compare_x;
  45.398 +reg m_result_sel_compare_m;
  45.399 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  45.400 +wire m_result_sel_shift_d;                      // Select M stage result from shifter
  45.401 +reg m_result_sel_shift_x;
  45.402 +reg m_result_sel_shift_m;
  45.403 +`endif
  45.404 +wire w_result_sel_load_d;                       // Select W stage result from load/store unit
  45.405 +reg w_result_sel_load_x;
  45.406 +reg w_result_sel_load_m;
  45.407 +reg w_result_sel_load_w;
  45.408 +`ifdef CFG_PL_MULTIPLY_ENABLED
  45.409 +wire w_result_sel_mul_d;                        // Select W stage result from multiplier
  45.410 +reg w_result_sel_mul_x;
  45.411 +reg w_result_sel_mul_m;
  45.412 +reg w_result_sel_mul_w;
  45.413 +`endif
  45.414 +wire x_bypass_enable_d;                         // Whether result is bypassable in X stage
  45.415 +reg x_bypass_enable_x;                          
  45.416 +wire m_bypass_enable_d;                         // Whether result is bypassable in M stage
  45.417 +reg m_bypass_enable_x;                          
  45.418 +reg m_bypass_enable_m;
  45.419 +wire sign_extend_d;                             // Whether to sign-extend or zero-extend
  45.420 +reg sign_extend_x;
  45.421 +wire write_enable_d;                            // Register file write enable
  45.422 +reg write_enable_x;
  45.423 +wire write_enable_q_x;
  45.424 +reg write_enable_m;
  45.425 +wire write_enable_q_m;
  45.426 +reg write_enable_w;
  45.427 +wire write_enable_q_w;
  45.428 +wire read_enable_0_d;                           // Register file read enable 0
  45.429 +wire [`LM32_REG_IDX_RNG] read_idx_0_d;          // Register file read index 0
  45.430 +wire read_enable_1_d;                           // Register file read enable 1
  45.431 +wire [`LM32_REG_IDX_RNG] read_idx_1_d;          // Register file read index 1
  45.432 +wire [`LM32_REG_IDX_RNG] write_idx_d;           // Register file write index
  45.433 +reg [`LM32_REG_IDX_RNG] write_idx_x;            
  45.434 +reg [`LM32_REG_IDX_RNG] write_idx_m;
  45.435 +reg [`LM32_REG_IDX_RNG] write_idx_w;
  45.436 +wire [`LM32_CSR_RNG] csr_d;                     // CSR read/write index
  45.437 +reg  [`LM32_CSR_RNG] csr_x;                  
  45.438 +wire [`LM32_CONDITION_RNG] condition_d;         // Branch condition
  45.439 +reg [`LM32_CONDITION_RNG] condition_x;          
  45.440 +`ifdef CFG_DEBUG_ENABLED
  45.441 +wire break_d;                                   // Indicates a break instruction
  45.442 +reg break_x;                                    
  45.443 +`endif
  45.444 +wire scall_d;                                   // Indicates a scall instruction
  45.445 +reg scall_x;    
  45.446 +wire eret_d;                                    // Indicates an eret instruction
  45.447 +reg eret_x;
  45.448 +wire eret_q_x;
  45.449 +reg eret_m;
  45.450 +`ifdef CFG_TRACE_ENABLED
  45.451 +reg eret_w;
  45.452 +`endif
  45.453 +`ifdef CFG_DEBUG_ENABLED
  45.454 +wire bret_d;                                    // Indicates a bret instruction
  45.455 +reg bret_x;
  45.456 +wire bret_q_x;
  45.457 +reg bret_m;
  45.458 +`ifdef CFG_TRACE_ENABLED
  45.459 +reg bret_w;
  45.460 +`endif
  45.461 +`endif
  45.462 +wire csr_write_enable_d;                        // CSR write enable
  45.463 +reg csr_write_enable_x;
  45.464 +wire csr_write_enable_q_x;
  45.465 +`ifdef CFG_USER_ENABLED
  45.466 +wire [`LM32_USER_OPCODE_RNG] user_opcode_d;     // User-defined instruction opcode
  45.467 +`endif
  45.468 +
  45.469 +`ifdef CFG_BUS_ERRORS_ENABLED
  45.470 +wire bus_error_d;                               // Indicates an bus error occured while fetching the instruction in this pipeline stage
  45.471 +reg bus_error_x;
  45.472 +reg data_bus_error_exception_m;
  45.473 +reg [`LM32_PC_RNG] memop_pc_w;
  45.474 +`endif
  45.475 +
  45.476 +reg [`LM32_WORD_RNG] d_result_0;                // Result of instruction in D stage (operand 0)
  45.477 +reg [`LM32_WORD_RNG] d_result_1;                // Result of instruction in D stage (operand 1)
  45.478 +reg [`LM32_WORD_RNG] x_result;                  // Result of instruction in X stage
  45.479 +reg [`LM32_WORD_RNG] m_result;                  // Result of instruction in M stage
  45.480 +reg [`LM32_WORD_RNG] w_result;                  // Result of instruction in W stage
  45.481 +
  45.482 +reg [`LM32_WORD_RNG] operand_0_x;               // Operand 0 for X stage instruction
  45.483 +reg [`LM32_WORD_RNG] operand_1_x;               // Operand 1 for X stage instruction
  45.484 +reg [`LM32_WORD_RNG] store_operand_x;           // Data read from register to store
  45.485 +reg [`LM32_WORD_RNG] operand_m;                 // Operand for M stage instruction
  45.486 +reg [`LM32_WORD_RNG] operand_w;                 // Operand for W stage instruction
  45.487 +
  45.488 +// To/from register file
  45.489 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
  45.490 +reg [`LM32_WORD_RNG] reg_data_live_0;          
  45.491 +reg [`LM32_WORD_RNG] reg_data_live_1;  
  45.492 +reg use_buf;                                    // Whether to use reg_data_live or reg_data_buf
  45.493 +reg [`LM32_WORD_RNG] reg_data_buf_0;
  45.494 +reg [`LM32_WORD_RNG] reg_data_buf_1;
  45.495 +`endif
  45.496 +`ifdef LM32_EBR_REGISTER_FILE
  45.497 +`else
  45.498 +reg [`LM32_WORD_RNG] registers[0:(1<<`LM32_REG_IDX_WIDTH)-1];   // Register file
  45.499 +`endif
  45.500 +wire [`LM32_WORD_RNG] reg_data_0;               // Register file read port 0 data         
  45.501 +wire [`LM32_WORD_RNG] reg_data_1;               // Register file read port 1 data
  45.502 +reg [`LM32_WORD_RNG] bypass_data_0;             // Register value 0 after bypassing
  45.503 +reg [`LM32_WORD_RNG] bypass_data_1;             // Register value 1 after bypassing
  45.504 +wire reg_write_enable_q_w;
  45.505 +
  45.506 +reg interlock;                                  // Indicates pipeline should be stalled because of a read-after-write hazzard
  45.507 +
  45.508 +wire stall_a;                                   // Stall instruction in A pipeline stage
  45.509 +wire stall_f;                                   // Stall instruction in F pipeline stage
  45.510 +wire stall_d;                                   // Stall instruction in D pipeline stage
  45.511 +wire stall_x;                                   // Stall instruction in X pipeline stage
  45.512 +wire stall_m;                                   // Stall instruction in M pipeline stage
  45.513 +
  45.514 +// To/from adder
  45.515 +wire adder_op_d;                                // Whether to add or subtract
  45.516 +reg adder_op_x;                                 
  45.517 +reg adder_op_x_n;                               // Inverted version of adder_op_x
  45.518 +wire [`LM32_WORD_RNG] adder_result_x;           // Result from adder
  45.519 +wire adder_overflow_x;                          // Whether a signed overflow occured
  45.520 +wire adder_carry_n_x;                           // Whether a carry was generated
  45.521 +
  45.522 +// To/from logical operations unit
  45.523 +wire [`LM32_LOGIC_OP_RNG] logic_op_d;           // Which operation to perform
  45.524 +reg [`LM32_LOGIC_OP_RNG] logic_op_x;            
  45.525 +wire [`LM32_WORD_RNG] logic_result_x;           // Result of logical operation
  45.526 +
  45.527 +`ifdef CFG_SIGN_EXTEND_ENABLED
  45.528 +// From sign-extension unit
  45.529 +wire [`LM32_WORD_RNG] sextb_result_x;           // Result of byte sign-extension
  45.530 +wire [`LM32_WORD_RNG] sexth_result_x;           // Result of half-word sign-extenstion
  45.531 +wire [`LM32_WORD_RNG] sext_result_x;            // Result of sign-extension specified by instruction
  45.532 +`endif
  45.533 +
  45.534 +// To/from shifter
  45.535 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  45.536 +`ifdef CFG_ROTATE_ENABLED
  45.537 +wire rotate_d;                                  // Whether we should rotate or shift
  45.538 +reg rotate_x;                                    
  45.539 +`endif
  45.540 +wire direction_d;                               // Which direction to shift in
  45.541 +reg direction_x;                                        
  45.542 +wire [`LM32_WORD_RNG] shifter_result_m;         // Result of shifter
  45.543 +`endif
  45.544 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED
  45.545 +wire shift_left_d;                              // Indicates whether to perform a left shift or not
  45.546 +wire shift_left_q_d;
  45.547 +wire shift_right_d;                             // Indicates whether to perform a right shift or not
  45.548 +wire shift_right_q_d;
  45.549 +`endif
  45.550 +`ifdef LM32_NO_BARREL_SHIFT
  45.551 +wire [`LM32_WORD_RNG] shifter_result_x;         // Result of single-bit right shifter
  45.552 +`endif
  45.553 +
  45.554 +// To/from multiplier
  45.555 +`ifdef LM32_MULTIPLY_ENABLED
  45.556 +wire [`LM32_WORD_RNG] multiplier_result_w;      // Result from multiplier
  45.557 +`endif
  45.558 +`ifdef CFG_MC_MULTIPLY_ENABLED
  45.559 +wire multiply_d;                                // Indicates whether to perform a multiply or not
  45.560 +wire multiply_q_d;
  45.561 +`endif
  45.562 +
  45.563 +// To/from divider
  45.564 +`ifdef CFG_MC_DIVIDE_ENABLED
  45.565 +wire divide_d;                                  // Indicates whether to perform a divider or not
  45.566 +wire divide_q_d;
  45.567 +wire modulus_d;
  45.568 +wire modulus_q_d;
  45.569 +wire divide_by_zero_x;                          // Indicates an attempt was made to divide by zero
  45.570 +`endif
  45.571 +
  45.572 +// To from multi-cycle arithmetic unit
  45.573 +`ifdef LM32_MC_ARITHMETIC_ENABLED
  45.574 +wire mc_stall_request_x;                        // Multi-cycle arithmetic unit stall request
  45.575 +wire [`LM32_WORD_RNG] mc_result_x;
  45.576 +`endif
  45.577 +
  45.578 +// From CSRs
  45.579 +`ifdef CFG_INTERRUPTS_ENABLED
  45.580 +wire [`LM32_WORD_RNG] interrupt_csr_read_data_x;// Data read from interrupt CSRs
  45.581 +`endif
  45.582 +wire [`LM32_WORD_RNG] cfg;                      // Configuration CSR
  45.583 +wire [`LM32_WORD_RNG] cfg2;                     // Extended Configuration CSR
  45.584 +`ifdef CFG_CYCLE_COUNTER_ENABLED
  45.585 +reg [`LM32_WORD_RNG] cc;                        // Cycle counter CSR
  45.586 +`endif
  45.587 +reg [`LM32_WORD_RNG] csr_read_data_x;           // Data read from CSRs
  45.588 +
  45.589 +// To/from instruction unit
  45.590 +wire [`LM32_PC_RNG] pc_f;                       // PC of instruction in F stage
  45.591 +wire [`LM32_PC_RNG] pc_d;                       // PC of instruction in D stage
  45.592 +wire [`LM32_PC_RNG] pc_x;                       // PC of instruction in X stage
  45.593 +wire [`LM32_PC_RNG] pc_m;                       // PC of instruction in M stage
  45.594 +wire [`LM32_PC_RNG] pc_w;                       // PC of instruction in W stage
  45.595 +`ifdef CFG_TRACE_ENABLED
  45.596 +reg [`LM32_PC_RNG] pc_c;                        // PC of last commited instruction
  45.597 +`endif
  45.598 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
  45.599 +wire [`LM32_INSTRUCTION_RNG] instruction_f;     // Instruction in F stage
  45.600 +`endif
  45.601 +//pragma attribute instruction_d preserve_signal true
  45.602 +//pragma attribute instruction_d preserve_driver true
  45.603 +wire [`LM32_INSTRUCTION_RNG] instruction_d;     // Instruction in D stage
  45.604 +`ifdef CFG_ICACHE_ENABLED
  45.605 +wire iflush;                                    // Flush instruction cache
  45.606 +wire icache_stall_request;                      // Stall pipeline because instruction cache is busy
  45.607 +wire icache_restart_request;                    // Restart instruction that caused an instruction cache miss
  45.608 +wire icache_refill_request;                     // Request to refill instruction cache
  45.609 +wire icache_refilling;                          // Indicates the instruction cache is being refilled
  45.610 +`endif
  45.611 +`ifdef CFG_IROM_ENABLED
  45.612 +wire [`LM32_WORD_RNG] irom_store_data_m;        // Store data to instruction ROM
  45.613 +wire [`LM32_WORD_RNG] irom_address_xm;          // Address to instruction ROM from load-store unit
  45.614 +wire [`LM32_WORD_RNG] irom_data_m;              // Load data from instruction ROM
  45.615 +wire irom_we_xm;                                // Indicates data needs to be written to instruction ROM
  45.616 +wire irom_stall_request_x;                      // Indicates D stage needs to be stalled on a store to instruction ROM
  45.617 +`endif
  45.618 +
  45.619 +// To/from load/store unit
  45.620 +`ifdef CFG_DCACHE_ENABLED
  45.621 +wire dflush_x;                                  // Flush data cache    
  45.622 +reg dflush_m;                                    
  45.623 +wire dcache_stall_request;                      // Stall pipeline because data cache is busy
  45.624 +wire dcache_restart_request;                    // Restart instruction that caused a data cache miss
  45.625 +wire dcache_refill_request;                     // Request to refill data cache
  45.626 +wire dcache_refilling;                          // Indicates the data cache is being refilled
  45.627 +`endif
  45.628 +wire [`LM32_WORD_RNG] load_data_w;              // Result of a load instruction
  45.629 +wire stall_wb_load;                             // Stall pipeline because of a load via the data Wishbone interface
  45.630 +
  45.631 +// To/from JTAG interface
  45.632 +`ifdef CFG_JTAG_ENABLED
  45.633 +`ifdef CFG_JTAG_UART_ENABLED
  45.634 +wire [`LM32_WORD_RNG] jtx_csr_read_data;        // Read data for JTX CSR
  45.635 +wire [`LM32_WORD_RNG] jrx_csr_read_data;        // Read data for JRX CSR
  45.636 +`endif
  45.637 +`ifdef CFG_HW_DEBUG_ENABLED
  45.638 +wire jtag_csr_write_enable;                     // Debugger CSR write enable
  45.639 +wire [`LM32_WORD_RNG] jtag_csr_write_data;      // Data to write to specified CSR
  45.640 +wire [`LM32_CSR_RNG] jtag_csr;                  // Which CSR to write
  45.641 +wire jtag_read_enable;                          
  45.642 +wire [`LM32_BYTE_RNG] jtag_read_data;
  45.643 +wire jtag_write_enable;
  45.644 +wire [`LM32_BYTE_RNG] jtag_write_data;
  45.645 +wire [`LM32_WORD_RNG] jtag_address;
  45.646 +wire jtag_access_complete;
  45.647 +`endif
  45.648 +`ifdef CFG_DEBUG_ENABLED
  45.649 +wire jtag_break;                                // Request from debugger to raise a breakpoint
  45.650 +`endif
  45.651 +`endif
  45.652 +
  45.653 +// Hazzard detection
  45.654 +wire raw_x_0;                                   // RAW hazzard between instruction in X stage and read port 0
  45.655 +wire raw_x_1;                                   // RAW hazzard between instruction in X stage and read port 1
  45.656 +wire raw_m_0;                                   // RAW hazzard between instruction in M stage and read port 0
  45.657 +wire raw_m_1;                                   // RAW hazzard between instruction in M stage and read port 1
  45.658 +wire raw_w_0;                                   // RAW hazzard between instruction in W stage and read port 0
  45.659 +wire raw_w_1;                                   // RAW hazzard between instruction in W stage and read port 1
  45.660 +
  45.661 +// Control flow
  45.662 +wire cmp_zero;                                  // Result of comparison is zero
  45.663 +wire cmp_negative;                              // Result of comparison is negative
  45.664 +wire cmp_overflow;                              // Comparison produced an overflow
  45.665 +wire cmp_carry_n;                               // Comparison produced a carry, inverted
  45.666 +reg condition_met_x;                            // Condition of branch instruction is met
  45.667 +reg condition_met_m;
  45.668 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
  45.669 +wire branch_taken_x;                            // Branch is taken in X stage
  45.670 +`endif
  45.671 +wire branch_taken_m;                            // Branch is taken in M stage
  45.672 +
  45.673 +wire kill_f;                                    // Kill instruction in F stage
  45.674 +wire kill_d;                                    // Kill instruction in D stage
  45.675 +wire kill_x;                                    // Kill instruction in X stage
  45.676 +wire kill_m;                                    // Kill instruction in M stage
  45.677 +wire kill_w;                                    // Kill instruction in W stage
  45.678 +
  45.679 +reg [`LM32_PC_WIDTH+2-1:8] eba;                 // Exception Base Address (EBA) CSR
  45.680 +`ifdef CFG_DEBUG_ENABLED
  45.681 +reg [`LM32_PC_WIDTH+2-1:8] deba;                // Debug Exception Base Address (DEBA) CSR
  45.682 +`endif
  45.683 +reg [`LM32_EID_RNG] eid_x;                      // Exception ID in X stage
  45.684 +`ifdef CFG_TRACE_ENABLED
  45.685 +reg [`LM32_EID_RNG] eid_m;                      // Exception ID in M stage
  45.686 +reg [`LM32_EID_RNG] eid_w;                      // Exception ID in W stage
  45.687 +`endif
  45.688 +
  45.689 +`ifdef CFG_DEBUG_ENABLED
  45.690 +`ifdef LM32_SINGLE_STEP_ENABLED
  45.691 +wire dc_ss;                                     // Is single-step enabled
  45.692 +`endif
  45.693 +wire dc_re;                                     // Remap all exceptions
  45.694 +wire exception_x;                               // An exception occured in the X stage
  45.695 +reg exception_m;                                // An instruction that caused an exception is in the M stage
  45.696 +wire debug_exception_x;                         // Indicates if a debug exception has occured
  45.697 +reg debug_exception_m;
  45.698 +reg debug_exception_w;
  45.699 +wire debug_exception_q_w;
  45.700 +wire non_debug_exception_x;                     // Indicates if a non debug exception has occured
  45.701 +reg non_debug_exception_m;
  45.702 +reg non_debug_exception_w;
  45.703 +wire non_debug_exception_q_w;
  45.704 +`else
  45.705 +wire exception_x;                               // Indicates if a debug exception has occured
  45.706 +reg exception_m;
  45.707 +reg exception_w;
  45.708 +wire exception_q_w;
  45.709 +`endif
  45.710 +
  45.711 +`ifdef CFG_DEBUG_ENABLED
  45.712 +`ifdef CFG_JTAG_ENABLED
  45.713 +wire reset_exception;                           // Indicates if a reset exception has occured
  45.714 +`endif
  45.715 +`endif
  45.716 +`ifdef CFG_INTERRUPTS_ENABLED
  45.717 +wire interrupt_exception;                       // Indicates if an interrupt exception has occured
  45.718 +`endif
  45.719 +`ifdef CFG_DEBUG_ENABLED
  45.720 +wire breakpoint_exception;                      // Indicates if a breakpoint exception has occured
  45.721 +wire watchpoint_exception;                      // Indicates if a watchpoint exception has occured
  45.722 +`endif
  45.723 +`ifdef CFG_BUS_ERRORS_ENABLED
  45.724 +wire instruction_bus_error_exception;           // Indicates if an instruction bus error exception has occured
  45.725 +wire data_bus_error_exception;                  // Indicates if a data bus error exception has occured
  45.726 +`endif
  45.727 +`ifdef CFG_MC_DIVIDE_ENABLED
  45.728 +wire divide_by_zero_exception;                  // Indicates if a divide by zero exception has occured
  45.729 +`endif
  45.730 +wire system_call_exception;                     // Indicates if a system call exception has occured
  45.731 +
  45.732 +`ifdef CFG_BUS_ERRORS_ENABLED
  45.733 +reg data_bus_error_seen;                        // Indicates if a data bus error was seen
  45.734 +`endif
  45.735 +
  45.736 +/////////////////////////////////////////////////////
  45.737 +// Functions
  45.738 +/////////////////////////////////////////////////////
  45.739 +
  45.740 +`include "lm32_functions.v"
  45.741 +
  45.742 +/////////////////////////////////////////////////////
  45.743 +// Instantiations
  45.744 +///////////////////////////////////////////////////// 
  45.745 +
  45.746 +// Instruction unit
  45.747 +lm32_instruction_unit #(
  45.748 +    .associativity          (icache_associativity),
  45.749 +    .sets                   (icache_sets),
  45.750 +    .bytes_per_line         (icache_bytes_per_line),
  45.751 +    .base_address           (icache_base_address),
  45.752 +    .limit                  (icache_limit)
  45.753 +  ) instruction_unit (
  45.754 +    // ----- Inputs -------
  45.755 +    .clk_i                  (clk_i),
  45.756 +    .rst_i                  (rst_i),
  45.757 +    // From pipeline
  45.758 +    .stall_a                (stall_a),
  45.759 +    .stall_f                (stall_f),
  45.760 +    .stall_d                (stall_d),
  45.761 +    .stall_x                (stall_x),
  45.762 +    .stall_m                (stall_m),
  45.763 +    .valid_f                (valid_f),
  45.764 +    .valid_d                (valid_d),
  45.765 +    .kill_f                 (kill_f),
  45.766 +    .branch_predict_taken_d (branch_predict_taken_d),
  45.767 +    .branch_predict_address_d (branch_predict_address_d),
  45.768 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
  45.769 +    .branch_taken_x         (branch_taken_x),
  45.770 +    .branch_target_x        (branch_target_x),
  45.771 +`endif
  45.772 +    .exception_m            (exception_m),
  45.773 +    .branch_taken_m         (branch_taken_m),
  45.774 +    .branch_mispredict_taken_m (branch_mispredict_taken_m),
  45.775 +    .branch_target_m        (branch_target_m),
  45.776 +`ifdef CFG_ICACHE_ENABLED
  45.777 +    .iflush                 (iflush),
  45.778 +`endif
  45.779 +`ifdef CFG_IROM_ENABLED
  45.780 +    .irom_store_data_m      (irom_store_data_m),
  45.781 +    .irom_address_xm        (irom_address_xm),
  45.782 +    .irom_we_xm             (irom_we_xm),
  45.783 +`endif
  45.784 +`ifdef CFG_DCACHE_ENABLED
  45.785 +    .dcache_restart_request (dcache_restart_request),
  45.786 +    .dcache_refill_request  (dcache_refill_request),
  45.787 +    .dcache_refilling       (dcache_refilling),
  45.788 +`endif        
  45.789 +`ifdef CFG_IWB_ENABLED
  45.790 +    // From Wishbone
  45.791 +    .i_dat_i                (I_DAT_I),
  45.792 +    .i_ack_i                (I_ACK_I),
  45.793 +    .i_err_i                (I_ERR_I),
  45.794 +`endif
  45.795 +`ifdef CFG_HW_DEBUG_ENABLED
  45.796 +    .jtag_read_enable       (jtag_read_enable),
  45.797 +    .jtag_write_enable      (jtag_write_enable),
  45.798 +    .jtag_write_data        (jtag_write_data),
  45.799 +    .jtag_address           (jtag_address),
  45.800 +`endif
  45.801 +    // ----- Outputs -------
  45.802 +    // To pipeline
  45.803 +    .pc_f                   (pc_f),
  45.804 +    .pc_d                   (pc_d),
  45.805 +    .pc_x                   (pc_x),
  45.806 +    .pc_m                   (pc_m),
  45.807 +    .pc_w                   (pc_w),
  45.808 +`ifdef CFG_ICACHE_ENABLED
  45.809 +    .icache_stall_request   (icache_stall_request),
  45.810 +    .icache_restart_request (icache_restart_request),
  45.811 +    .icache_refill_request  (icache_refill_request),
  45.812 +    .icache_refilling       (icache_refilling),
  45.813 +`endif
  45.814 +`ifdef CFG_IROM_ENABLED
  45.815 +    .irom_data_m            (irom_data_m),
  45.816 +`endif
  45.817 +`ifdef CFG_IWB_ENABLED
  45.818 +    // To Wishbone
  45.819 +    .i_dat_o                (I_DAT_O),
  45.820 +    .i_adr_o                (I_ADR_O),
  45.821 +    .i_cyc_o                (I_CYC_O),
  45.822 +    .i_sel_o                (I_SEL_O),
  45.823 +    .i_stb_o                (I_STB_O),
  45.824 +    .i_we_o                 (I_WE_O),
  45.825 +    .i_cti_o                (I_CTI_O),
  45.826 +    .i_lock_o               (I_LOCK_O),
  45.827 +    .i_bte_o                (I_BTE_O),
  45.828 +`endif
  45.829 +`ifdef CFG_HW_DEBUG_ENABLED
  45.830 +    .jtag_read_data         (jtag_read_data),
  45.831 +    .jtag_access_complete   (jtag_access_complete),
  45.832 +`endif
  45.833 +`ifdef CFG_BUS_ERRORS_ENABLED
  45.834 +    .bus_error_d            (bus_error_d),
  45.835 +`endif
  45.836 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
  45.837 +    .instruction_f          (instruction_f),
  45.838 +`endif
  45.839 +    .instruction_d          (instruction_d)
  45.840 +    );
  45.841 +
  45.842 +// Instruction decoder
  45.843 +lm32_decoder decoder (
  45.844 +    // ----- Inputs -------
  45.845 +    .instruction            (instruction_d),
  45.846 +    // ----- Outputs -------
  45.847 +    .d_result_sel_0         (d_result_sel_0_d),
  45.848 +    .d_result_sel_1         (d_result_sel_1_d),
  45.849 +    .x_result_sel_csr       (x_result_sel_csr_d),
  45.850 +`ifdef LM32_MC_ARITHMETIC_ENABLED
  45.851 +    .x_result_sel_mc_arith  (x_result_sel_mc_arith_d),
  45.852 +`endif
  45.853 +`ifdef LM32_NO_BARREL_SHIFT    
  45.854 +    .x_result_sel_shift     (x_result_sel_shift_d),
  45.855 +`endif
  45.856 +`ifdef CFG_SIGN_EXTEND_ENABLED
  45.857 +    .x_result_sel_sext      (x_result_sel_sext_d),
  45.858 +`endif    
  45.859 +    .x_result_sel_logic     (x_result_sel_logic_d),
  45.860 +`ifdef CFG_USER_ENABLED
  45.861 +    .x_result_sel_user      (x_result_sel_user_d),
  45.862 +`endif
  45.863 +    .x_result_sel_add       (x_result_sel_add_d),
  45.864 +    .m_result_sel_compare   (m_result_sel_compare_d),
  45.865 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  45.866 +    .m_result_sel_shift     (m_result_sel_shift_d),  
  45.867 +`endif    
  45.868 +    .w_result_sel_load      (w_result_sel_load_d),
  45.869 +`ifdef CFG_PL_MULTIPLY_ENABLED
  45.870 +    .w_result_sel_mul       (w_result_sel_mul_d),
  45.871 +`endif
  45.872 +    .x_bypass_enable        (x_bypass_enable_d),
  45.873 +    .m_bypass_enable        (m_bypass_enable_d),
  45.874 +    .read_enable_0          (read_enable_0_d),
  45.875 +    .read_idx_0             (read_idx_0_d),
  45.876 +    .read_enable_1          (read_enable_1_d),
  45.877 +    .read_idx_1             (read_idx_1_d),
  45.878 +    .write_enable           (write_enable_d),
  45.879 +    .write_idx              (write_idx_d),
  45.880 +    .immediate              (immediate_d),
  45.881 +    .branch_offset          (branch_offset_d),
  45.882 +    .load                   (load_d),
  45.883 +    .store                  (store_d),
  45.884 +    .size                   (size_d),
  45.885 +    .sign_extend            (sign_extend_d),
  45.886 +    .adder_op               (adder_op_d),
  45.887 +    .logic_op               (logic_op_d),
  45.888 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  45.889 +    .direction              (direction_d),
  45.890 +`endif
  45.891 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED
  45.892 +    .shift_left             (shift_left_d),
  45.893 +    .shift_right            (shift_right_d),
  45.894 +`endif
  45.895 +`ifdef CFG_MC_MULTIPLY_ENABLED
  45.896 +    .multiply               (multiply_d),
  45.897 +`endif
  45.898 +`ifdef CFG_MC_DIVIDE_ENABLED
  45.899 +    .divide                 (divide_d),
  45.900 +    .modulus                (modulus_d),
  45.901 +`endif
  45.902 +    .branch                 (branch_d),
  45.903 +    .bi_unconditional       (bi_unconditional),
  45.904 +    .bi_conditional         (bi_conditional),
  45.905 +    .branch_reg             (branch_reg_d),
  45.906 +    .condition              (condition_d),
  45.907 +`ifdef CFG_DEBUG_ENABLED
  45.908 +    .break_opcode           (break_d),
  45.909 +`endif
  45.910 +    .scall                  (scall_d),
  45.911 +    .eret                   (eret_d),
  45.912 +`ifdef CFG_DEBUG_ENABLED
  45.913 +    .bret                   (bret_d),
  45.914 +`endif
  45.915 +`ifdef CFG_USER_ENABLED
  45.916 +    .user_opcode            (user_opcode_d),
  45.917 +`endif
  45.918 +    .csr_write_enable       (csr_write_enable_d)
  45.919 +    ); 
  45.920 +
  45.921 +// Load/store unit       
  45.922 +lm32_load_store_unit #(
  45.923 +    .associativity          (dcache_associativity),
  45.924 +    .sets                   (dcache_sets),
  45.925 +    .bytes_per_line         (dcache_bytes_per_line),
  45.926 +    .base_address           (dcache_base_address),
  45.927 +    .limit                  (dcache_limit)
  45.928 +  ) load_store_unit (
  45.929 +    // ----- Inputs -------
  45.930 +    .clk_i                  (clk_i),
  45.931 +    .rst_i                  (rst_i),
  45.932 +    // From pipeline
  45.933 +    .stall_a                (stall_a),
  45.934 +    .stall_x                (stall_x),
  45.935 +    .stall_m                (stall_m),
  45.936 +    .kill_m                 (kill_m),
  45.937 +    .exception_m            (exception_m),
  45.938 +    .store_operand_x        (store_operand_x),
  45.939 +    .load_store_address_x   (adder_result_x),
  45.940 +    .load_store_address_m   (operand_m),
  45.941 +    .load_store_address_w   (operand_w[1:0]),
  45.942 +    .load_x                 (load_x),
  45.943 +    .store_x                (store_x),
  45.944 +    .load_q_x               (load_q_x),
  45.945 +    .store_q_x              (store_q_x),
  45.946 +    .load_q_m               (load_q_m),
  45.947 +    .store_q_m              (store_q_m),
  45.948 +    .sign_extend_x          (sign_extend_x),
  45.949 +    .size_x                 (size_x),
  45.950 +`ifdef CFG_DCACHE_ENABLED
  45.951 +    .dflush                 (dflush_m),
  45.952 +`endif
  45.953 +`ifdef CFG_IROM_ENABLED
  45.954 +    .irom_data_m            (irom_data_m),
  45.955 +`endif
  45.956 +    // From Wishbone
  45.957 +    .d_dat_i                (D_DAT_I),
  45.958 +    .d_ack_i                (D_ACK_I),
  45.959 +    .d_err_i                (D_ERR_I),
  45.960 +    .d_rty_i                (D_RTY_I),
  45.961 +    // ----- Outputs -------
  45.962 +    // To pipeline
  45.963 +`ifdef CFG_DCACHE_ENABLED
  45.964 +    .dcache_refill_request  (dcache_refill_request),
  45.965 +    .dcache_restart_request (dcache_restart_request),
  45.966 +    .dcache_stall_request   (dcache_stall_request),
  45.967 +    .dcache_refilling       (dcache_refilling),
  45.968 +`endif    
  45.969 +`ifdef CFG_IROM_ENABLED
  45.970 +    .irom_store_data_m      (irom_store_data_m),
  45.971 +    .irom_address_xm        (irom_address_xm),
  45.972 +    .irom_we_xm             (irom_we_xm),
  45.973 +    .irom_stall_request_x   (irom_stall_request_x),
  45.974 +`endif
  45.975 +    .load_data_w            (load_data_w),
  45.976 +    .stall_wb_load          (stall_wb_load),
  45.977 +    // To Wishbone
  45.978 +    .d_dat_o                (D_DAT_O),
  45.979 +    .d_adr_o                (D_ADR_O),
  45.980 +    .d_cyc_o                (D_CYC_O),
  45.981 +    .d_sel_o                (D_SEL_O),
  45.982 +    .d_stb_o                (D_STB_O),
  45.983 +    .d_we_o                 (D_WE_O),
  45.984 +    .d_cti_o                (D_CTI_O),
  45.985 +    .d_lock_o               (D_LOCK_O),
  45.986 +    .d_bte_o                (D_BTE_O)
  45.987 +    );      
  45.988 +       
  45.989 +// Adder       
  45.990 +lm32_adder adder (
  45.991 +    // ----- Inputs -------
  45.992 +    .adder_op_x             (adder_op_x),
  45.993 +    .adder_op_x_n           (adder_op_x_n),
  45.994 +    .operand_0_x            (operand_0_x),
  45.995 +    .operand_1_x            (operand_1_x),
  45.996 +    // ----- Outputs -------
  45.997 +    .adder_result_x         (adder_result_x),
  45.998 +    .adder_carry_n_x        (adder_carry_n_x),
  45.999 +    .adder_overflow_x       (adder_overflow_x)
 45.1000 +    );
 45.1001 +
 45.1002 +// Logic operations
 45.1003 +lm32_logic_op logic_op (
 45.1004 +    // ----- Inputs -------
 45.1005 +    .logic_op_x             (logic_op_x),
 45.1006 +    .operand_0_x            (operand_0_x),
 45.1007 +
 45.1008 +    .operand_1_x            (operand_1_x),
 45.1009 +    // ----- Outputs -------
 45.1010 +    .logic_result_x         (logic_result_x)
 45.1011 +    );
 45.1012 +              
 45.1013 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
 45.1014 +// Pipelined barrel-shifter
 45.1015 +lm32_shifter shifter (
 45.1016 +    // ----- Inputs -------
 45.1017 +    .clk_i                  (clk_i),
 45.1018 +    .rst_i                  (rst_i),
 45.1019 +    .stall_x                (stall_x),
 45.1020 +    .direction_x            (direction_x),
 45.1021 +    .sign_extend_x          (sign_extend_x),
 45.1022 +    .operand_0_x            (operand_0_x),
 45.1023 +    .operand_1_x            (operand_1_x),
 45.1024 +    // ----- Outputs -------
 45.1025 +    .shifter_result_m       (shifter_result_m)
 45.1026 +    );
 45.1027 +`endif
 45.1028 +
 45.1029 +`ifdef CFG_PL_MULTIPLY_ENABLED
 45.1030 +// Pipeline fixed-point multiplier
 45.1031 +lm32_multiplier multiplier (
 45.1032 +    // ----- Inputs -------
 45.1033 +    .clk_i                  (clk_i),
 45.1034 +    .rst_i                  (rst_i),
 45.1035 +    .stall_x                (stall_x),
 45.1036 +    .stall_m                (stall_m),
 45.1037 +    .operand_0              (d_result_0),
 45.1038 +    .operand_1              (d_result_1),
 45.1039 +    // ----- Outputs -------
 45.1040 +    .result                 (multiplier_result_w)    
 45.1041 +    );
 45.1042 +`endif
 45.1043 +
 45.1044 +`ifdef LM32_MC_ARITHMETIC_ENABLED
 45.1045 +// Multi-cycle arithmetic
 45.1046 +lm32_mc_arithmetic mc_arithmetic (
 45.1047 +    // ----- Inputs -------
 45.1048 +    .clk_i                  (clk_i),
 45.1049 +    .rst_i                  (rst_i),
 45.1050 +    .stall_d                (stall_d),
 45.1051 +    .kill_x                 (kill_x),
 45.1052 +`ifdef CFG_MC_DIVIDE_ENABLED                  
 45.1053 +    .divide_d               (divide_q_d),
 45.1054 +    .modulus_d              (modulus_q_d),
 45.1055 +`endif
 45.1056 +`ifdef CFG_MC_MULTIPLY_ENABLED        
 45.1057 +    .multiply_d             (multiply_q_d),
 45.1058 +`endif
 45.1059 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED
 45.1060 +    .shift_left_d           (shift_left_q_d),
 45.1061 +    .shift_right_d          (shift_right_q_d),
 45.1062 +    .sign_extend_d          (sign_extend_d),
 45.1063 +`endif    
 45.1064 +    .operand_0_d            (d_result_0),
 45.1065 +    .operand_1_d            (d_result_1),
 45.1066 +    // ----- Outputs -------
 45.1067 +    .result_x               (mc_result_x),
 45.1068 +`ifdef CFG_MC_DIVIDE_ENABLED                  
 45.1069 +    .divide_by_zero_x       (divide_by_zero_x),
 45.1070 +`endif
 45.1071 +    .stall_request_x        (mc_stall_request_x)
 45.1072 +    );
 45.1073 +`endif
 45.1074 +              
 45.1075 +`ifdef CFG_INTERRUPTS_ENABLED
 45.1076 +// Interrupt unit
 45.1077 +lm32_interrupt interrupt_unit (
 45.1078 +    // ----- Inputs -------
 45.1079 +    .clk_i                  (clk_i),
 45.1080 +    .rst_i                  (rst_i),
 45.1081 +    // From external devices
 45.1082 +    .interrupt              (interrupt),
 45.1083 +    // From pipeline
 45.1084 +    .stall_x                (stall_x),
 45.1085 +`ifdef CFG_DEBUG_ENABLED
 45.1086 +    .non_debug_exception    (non_debug_exception_q_w),
 45.1087 +    .debug_exception        (debug_exception_q_w),
 45.1088 +`else
 45.1089 +    .exception              (exception_q_w),
 45.1090 +`endif
 45.1091 +    .eret_q_x               (eret_q_x),
 45.1092 +`ifdef CFG_DEBUG_ENABLED
 45.1093 +    .bret_q_x               (bret_q_x),
 45.1094 +`endif
 45.1095 +    .csr                    (csr_x),
 45.1096 +    .csr_write_data         (operand_1_x),
 45.1097 +    .csr_write_enable       (csr_write_enable_q_x),
 45.1098 +    // ----- Outputs -------
 45.1099 +    .interrupt_exception    (interrupt_exception),
 45.1100 +    // To pipeline
 45.1101 +    .csr_read_data          (interrupt_csr_read_data_x)
 45.1102 +    );
 45.1103 +`endif
 45.1104 +
 45.1105 +`ifdef CFG_JTAG_ENABLED
 45.1106 +// JTAG interface
 45.1107 +lm32_jtag jtag (
 45.1108 +    // ----- Inputs -------
 45.1109 +    .clk_i                  (clk_i),
 45.1110 +    .rst_i                  (rst_i),
 45.1111 +    // From JTAG
 45.1112 +    .jtag_clk               (jtag_clk),
 45.1113 +    .jtag_update            (jtag_update),
 45.1114 +    .jtag_reg_q             (jtag_reg_q),
 45.1115 +    .jtag_reg_addr_q        (jtag_reg_addr_q),
 45.1116 +    // From pipeline
 45.1117 +`ifdef CFG_JTAG_UART_ENABLED
 45.1118 +    .csr                    (csr_x),
 45.1119 +    .csr_write_data         (operand_1_x),
 45.1120 +    .csr_write_enable       (csr_write_enable_q_x),
 45.1121 +    .stall_x                (stall_x),
 45.1122 +`endif
 45.1123 +`ifdef CFG_HW_DEBUG_ENABLED
 45.1124 +    .jtag_read_data         (jtag_read_data),
 45.1125 +    .jtag_access_complete   (jtag_access_complete),
 45.1126 +`endif
 45.1127 +`ifdef CFG_DEBUG_ENABLED
 45.1128 +    .exception_q_w          (debug_exception_q_w || non_debug_exception_q_w),
 45.1129 +`endif    
 45.1130 +    // ----- Outputs -------
 45.1131 +    // To pipeline
 45.1132 +`ifdef CFG_JTAG_UART_ENABLED
 45.1133 +    .jtx_csr_read_data      (jtx_csr_read_data),
 45.1134 +    .jrx_csr_read_data      (jrx_csr_read_data),
 45.1135 +`endif
 45.1136 +`ifdef CFG_HW_DEBUG_ENABLED
 45.1137 +    .jtag_csr_write_enable  (jtag_csr_write_enable),
 45.1138 +    .jtag_csr_write_data    (jtag_csr_write_data),
 45.1139 +    .jtag_csr               (jtag_csr),
 45.1140 +    .jtag_read_enable       (jtag_read_enable),
 45.1141 +    .jtag_write_enable      (jtag_write_enable),
 45.1142 +    .jtag_write_data        (jtag_write_data),
 45.1143 +    .jtag_address           (jtag_address),
 45.1144 +`endif
 45.1145 +`ifdef CFG_DEBUG_ENABLED
 45.1146 +    .jtag_break             (jtag_break),
 45.1147 +    .jtag_reset             (reset_exception),
 45.1148 +`endif
 45.1149 +    // To JTAG 
 45.1150 +    .jtag_reg_d             (jtag_reg_d),
 45.1151 +    .jtag_reg_addr_d        (jtag_reg_addr_d)
 45.1152 +    );
 45.1153 +`endif
 45.1154 +
 45.1155 +`ifdef CFG_DEBUG_ENABLED
 45.1156 +// Debug unit
 45.1157 +lm32_debug #(
 45.1158 +    .breakpoints            (breakpoints),
 45.1159 +    .watchpoints            (watchpoints)
 45.1160 +  ) hw_debug (
 45.1161 +    // ----- Inputs -------
 45.1162 +    .clk_i                  (clk_i), 
 45.1163 +    .rst_i                  (rst_i),
 45.1164 +    .pc_x                   (pc_x),
 45.1165 +    .load_x                 (load_x),
 45.1166 +    .store_x                (store_x),
 45.1167 +    .load_store_address_x   (adder_result_x),
 45.1168 +    .csr_write_enable_x     (csr_write_enable_q_x),
 45.1169 +    .csr_write_data         (operand_1_x),
 45.1170 +    .csr_x                  (csr_x),
 45.1171 +`ifdef CFG_HW_DEBUG_ENABLED
 45.1172 +    .jtag_csr_write_enable  (jtag_csr_write_enable),
 45.1173 +    .jtag_csr_write_data    (jtag_csr_write_data),
 45.1174 +    .jtag_csr               (jtag_csr),
 45.1175 +`endif
 45.1176 +`ifdef LM32_SINGLE_STEP_ENABLED
 45.1177 +    .eret_q_x               (eret_q_x),
 45.1178 +    .bret_q_x               (bret_q_x),
 45.1179 +    .stall_x                (stall_x),
 45.1180 +    .exception_x            (exception_x),
 45.1181 +    .q_x                    (q_x),
 45.1182 +`ifdef CFG_DCACHE_ENABLED
 45.1183 +    .dcache_refill_request  (dcache_refill_request),
 45.1184 +`endif
 45.1185 +`endif
 45.1186 +    // ----- Outputs -------
 45.1187 +`ifdef LM32_SINGLE_STEP_ENABLED
 45.1188 +    .dc_ss                  (dc_ss),
 45.1189 +`endif
 45.1190 +    .dc_re                  (dc_re),
 45.1191 +    .bp_match               (bp_match),
 45.1192 +    .wp_match               (wp_match)
 45.1193 +    );
 45.1194 +`endif
 45.1195 +
 45.1196 +// Register file
 45.1197 +
 45.1198 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
 45.1199 +   /*----------------------------------------------------------------------
 45.1200 +    Register File is implemented using EBRs. There can be three accesses to
 45.1201 +    the register file in each cycle: two reads and one write. On-chip block
 45.1202 +    RAM has two read/write ports. To accomodate three accesses, two on-chip
 45.1203 +    block RAMs are used (each register file "write" is made to both block
 45.1204 +    RAMs).
 45.1205 +    
 45.1206 +    One limitation of the on-chip block RAMs is that one cannot perform a 
 45.1207 +    read and write to same location in a cycle (if this is done, then the
 45.1208 +    data read out is indeterminate).
 45.1209 +    ----------------------------------------------------------------------*/
 45.1210 +   wire [31:0] regfile_data_0, regfile_data_1;
 45.1211 +   reg [31:0]  w_result_d;
 45.1212 +   reg 	       regfile_raw_0, regfile_raw_0_nxt;
 45.1213 +   reg 	       regfile_raw_1, regfile_raw_1_nxt;
 45.1214 +   
 45.1215 +   /*----------------------------------------------------------------------
 45.1216 +    Check if read and write is being performed to same register in current 
 45.1217 +    cycle? This is done by comparing the read and write IDXs.
 45.1218 +    ----------------------------------------------------------------------*/
 45.1219 +   always @(reg_write_enable_q_w or write_idx_w or instruction_f)
 45.1220 +     begin
 45.1221 +	if (reg_write_enable_q_w
 45.1222 +	    && (write_idx_w == instruction_f[25:21]))
 45.1223 +	  regfile_raw_0_nxt = 1'b1;
 45.1224 +	else
 45.1225 +	  regfile_raw_0_nxt = 1'b0;
 45.1226 +	
 45.1227 +	if (reg_write_enable_q_w
 45.1228 +	    && (write_idx_w == instruction_f[20:16]))
 45.1229 +	  regfile_raw_1_nxt = 1'b1;
 45.1230 +	else
 45.1231 +	  regfile_raw_1_nxt = 1'b0;
 45.1232 +     end
 45.1233 +   
 45.1234 +   /*----------------------------------------------------------------------
 45.1235 +    Select latched (delayed) write value or data from register file. If 
 45.1236 +    read in previous cycle was performed to register written to in same
 45.1237 +    cycle, then latched (delayed) write value is selected.
 45.1238 +    ----------------------------------------------------------------------*/
 45.1239 +   always @(regfile_raw_0 or w_result_d or regfile_data_0)
 45.1240 +     if (regfile_raw_0)
 45.1241 +       reg_data_live_0 = w_result_d;
 45.1242 +     else
 45.1243 +       reg_data_live_0 = regfile_data_0;
 45.1244 +   
 45.1245 +   /*----------------------------------------------------------------------
 45.1246 +    Select latched (delayed) write value or data from register file. If 
 45.1247 +    read in previous cycle was performed to register written to in same
 45.1248 +    cycle, then latched (delayed) write value is selected.
 45.1249 +    ----------------------------------------------------------------------*/
 45.1250 +   always @(regfile_raw_1 or w_result_d or regfile_data_1)
 45.1251 +     if (regfile_raw_1)
 45.1252 +       reg_data_live_1 = w_result_d;
 45.1253 +     else
 45.1254 +       reg_data_live_1 = regfile_data_1;
 45.1255 +   
 45.1256 +   /*----------------------------------------------------------------------
 45.1257 +    Latch value written to register file
 45.1258 +    ----------------------------------------------------------------------*/
 45.1259 +   always @(posedge clk_i `CFG_RESET_SENSITIVITY)
 45.1260 +     if (rst_i == `TRUE)
 45.1261 +       begin
 45.1262 +	  regfile_raw_0 <= 1'b0;
 45.1263 +	  regfile_raw_1 <= 1'b0;
 45.1264 +	  w_result_d <= 32'b0;
 45.1265 +       end
 45.1266 +     else
 45.1267 +       begin
 45.1268 +	  regfile_raw_0 <= regfile_raw_0_nxt;
 45.1269 +	  regfile_raw_1 <= regfile_raw_1_nxt;
 45.1270 +	  w_result_d <= w_result;
 45.1271 +       end
 45.1272 +   
 45.1273 +   /*----------------------------------------------------------------------
 45.1274 +    Register file instantiation as Pseudo-Dual Port EBRs.
 45.1275 +    ----------------------------------------------------------------------*/
 45.1276 +   // Modified by GSI: removed non-portable RAM instantiation
 45.1277 +   lm32_dp_ram
 45.1278 +     #(
 45.1279 +       // ----- Parameters -----
 45.1280 +       .addr_depth(1<<5),
 45.1281 +       .addr_width(5),
 45.1282 +       .data_width(32)
 45.1283 +       )
 45.1284 +   reg_0
 45.1285 +     (
 45.1286 +      // ----- Inputs -----
 45.1287 +      .clk_i	(clk_i),
 45.1288 +      .rst_i	(rst_i), 
 45.1289 +      .we_i	(reg_write_enable_q_w),
 45.1290 +      .wdata_i	(w_result),
 45.1291 +      .waddr_i	(write_idx_w),
 45.1292 +      .raddr_i	(instruction_f[25:21]),
 45.1293 +      // ----- Outputs -----
 45.1294 +      .rdata_o	(regfile_data_0)
 45.1295 +      );
 45.1296 +
 45.1297 +   lm32_dp_ram
 45.1298 +     #(
 45.1299 +       .addr_depth(1<<5),
 45.1300 +       .addr_width(5),
 45.1301 +       .data_width(32)
 45.1302 +       )
 45.1303 +   reg_1
 45.1304 +     (
 45.1305 +      // ----- Inputs -----
 45.1306 +      .clk_i	(clk_i),
 45.1307 +      .rst_i	(rst_i), 
 45.1308 +      .we_i	(reg_write_enable_q_w),
 45.1309 +      .wdata_i	(w_result),
 45.1310 +      .waddr_i	(write_idx_w),
 45.1311 +      .raddr_i	(instruction_f[20:16]),
 45.1312 +      // ----- Outputs -----
 45.1313 +      .rdata_o	(regfile_data_1)
 45.1314 +      );
 45.1315 +`endif
 45.1316 +
 45.1317 +`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
 45.1318 +   pmi_ram_dp
 45.1319 +     #(
 45.1320 +       // ----- Parameters -----
 45.1321 +       .pmi_wr_addr_depth(1<<5),
 45.1322 +       .pmi_wr_addr_width(5),
 45.1323 +       .pmi_wr_data_width(32),
 45.1324 +       .pmi_rd_addr_depth(1<<5),
 45.1325 +       .pmi_rd_addr_width(5),
 45.1326 +       .pmi_rd_data_width(32),
 45.1327 +       .pmi_regmode("noreg"),
 45.1328 +       .pmi_gsr("enable"),
 45.1329 +       .pmi_resetmode("sync"),
 45.1330 +       .pmi_init_file("none"),
 45.1331 +       .pmi_init_file_format("binary"),
 45.1332 +       .pmi_family(`LATTICE_FAMILY),
 45.1333 +       .module_type("pmi_ram_dp")
 45.1334 +       )
 45.1335 +   reg_0
 45.1336 +     (
 45.1337 +      // ----- Inputs -----
 45.1338 +      .Data(w_result),
 45.1339 +      .WrAddress(write_idx_w),
 45.1340 +      .RdAddress(read_idx_0_d),
 45.1341 +      .WrClock(clk_i),
 45.1342 +      .RdClock(clk_n_i),
 45.1343 +      .WrClockEn(`TRUE),
 45.1344 +      .RdClockEn(stall_f == `FALSE),
 45.1345 +      .WE(reg_write_enable_q_w),
 45.1346 +      .Reset(rst_i), 
 45.1347 +      // ----- Outputs -----
 45.1348 +      .Q(reg_data_0)
 45.1349 +      );
 45.1350 +   
 45.1351 +   pmi_ram_dp
 45.1352 +     #(
 45.1353 +       // ----- Parameters -----
 45.1354 +       .pmi_wr_addr_depth(1<<5),
 45.1355 +       .pmi_wr_addr_width(5),
 45.1356 +       .pmi_wr_data_width(32),
 45.1357 +       .pmi_rd_addr_depth(1<<5),
 45.1358 +       .pmi_rd_addr_width(5),
 45.1359 +       .pmi_rd_data_width(32),
 45.1360 +       .pmi_regmode("noreg"),
 45.1361 +       .pmi_gsr("enable"),
 45.1362 +       .pmi_resetmode("sync"),
 45.1363 +       .pmi_init_file("none"),
 45.1364 +       .pmi_init_file_format("binary"),
 45.1365 +       .pmi_family(`LATTICE_FAMILY),
 45.1366 +       .module_type("pmi_ram_dp")
 45.1367 +       )
 45.1368 +   reg_1
 45.1369 +     (
 45.1370 +      // ----- Inputs -----
 45.1371 +      .Data(w_result),
 45.1372 +      .WrAddress(write_idx_w),
 45.1373 +      .RdAddress(read_idx_1_d),
 45.1374 +      .WrClock(clk_i),
 45.1375 +      .RdClock(clk_n_i),
 45.1376 +      .WrClockEn(`TRUE),
 45.1377 +      .RdClockEn(stall_f == `FALSE),
 45.1378 +      .WE(reg_write_enable_q_w),
 45.1379 +      .Reset(rst_i), 
 45.1380 +      // ----- Outputs -----
 45.1381 +      .Q(reg_data_1)
 45.1382 +      );
 45.1383 +`endif
 45.1384 +
 45.1385 +
 45.1386 +/////////////////////////////////////////////////////
 45.1387 +// Combinational Logic
 45.1388 +/////////////////////////////////////////////////////
 45.1389 +
 45.1390 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
 45.1391 +// Select between buffered and live data from register file
 45.1392 +assign reg_data_0 = use_buf ? reg_data_buf_0 : reg_data_live_0;
 45.1393 +assign reg_data_1 = use_buf ? reg_data_buf_1 : reg_data_live_1;
 45.1394 +`endif
 45.1395 +`ifdef LM32_EBR_REGISTER_FILE
 45.1396 +`else
 45.1397 +// Register file read ports
 45.1398 +assign reg_data_0 = registers[read_idx_0_d];
 45.1399 +assign reg_data_1 = registers[read_idx_1_d];
 45.1400 +`endif
 45.1401 +
 45.1402 +// Detect read-after-write hazzards
 45.1403 +assign raw_x_0 = (write_idx_x == read_idx_0_d) && (write_enable_q_x == `TRUE);
 45.1404 +assign raw_m_0 = (write_idx_m == read_idx_0_d) && (write_enable_q_m == `TRUE);
 45.1405 +assign raw_w_0 = (write_idx_w == read_idx_0_d) && (write_enable_q_w == `TRUE);
 45.1406 +assign raw_x_1 = (write_idx_x == read_idx_1_d) && (write_enable_q_x == `TRUE);
 45.1407 +assign raw_m_1 = (write_idx_m == read_idx_1_d) && (write_enable_q_m == `TRUE);
 45.1408 +assign raw_w_1 = (write_idx_w == read_idx_1_d) && (write_enable_q_w == `TRUE);
 45.1409 +
 45.1410 +// Interlock detection - Raise an interlock for RAW hazzards 
 45.1411 +always @(*)
 45.1412 +begin
 45.1413 +    if (   (   (x_bypass_enable_x == `FALSE)
 45.1414 +            && (   ((read_enable_0_d == `TRUE) && (raw_x_0 == `TRUE))
 45.1415 +                || ((read_enable_1_d == `TRUE) && (raw_x_1 == `TRUE))
 45.1416 +               )
 45.1417 +           )
 45.1418 +        || (   (m_bypass_enable_m == `FALSE)
 45.1419 +            && (   ((read_enable_0_d == `TRUE) && (raw_m_0 == `TRUE))
 45.1420 +                || ((read_enable_1_d == `TRUE) && (raw_m_1 == `TRUE))
 45.1421 +               )
 45.1422 +           )
 45.1423 +       )
 45.1424 +        interlock = `TRUE;
 45.1425 +    else
 45.1426 +        interlock = `FALSE;
 45.1427 +end
 45.1428 +
 45.1429 +// Bypass for reg port 0
 45.1430 +always @(*)
 45.1431 +begin
 45.1432 +    if (raw_x_0 == `TRUE)        
 45.1433 +        bypass_data_0 = x_result;
 45.1434 +    else if (raw_m_0 == `TRUE)
 45.1435 +        bypass_data_0 = m_result;
 45.1436 +    else if (raw_w_0 == `TRUE)
 45.1437 +        bypass_data_0 = w_result;
 45.1438 +    else
 45.1439 +        bypass_data_0 = reg_data_0;
 45.1440 +end
 45.1441 +
 45.1442 +// Bypass for reg port 1
 45.1443 +always @(*)
 45.1444 +begin
 45.1445 +    if (raw_x_1 == `TRUE)
 45.1446 +        bypass_data_1 = x_result;
 45.1447 +    else if (raw_m_1 == `TRUE)
 45.1448 +        bypass_data_1 = m_result;
 45.1449 +    else if (raw_w_1 == `TRUE)
 45.1450 +        bypass_data_1 = w_result;
 45.1451 +    else
 45.1452 +        bypass_data_1 = reg_data_1;
 45.1453 +end
 45.1454 +
 45.1455 +   /*----------------------------------------------------------------------
 45.1456 +    Branch prediction is performed in D stage of pipeline. Only PC-relative
 45.1457 +    branches are predicted: forward-pointing conditional branches are not-
 45.1458 +    taken, while backward-pointing conditional branches are taken. 
 45.1459 +    Unconditional branches are always predicted taken!
 45.1460 +    ----------------------------------------------------------------------*/
 45.1461 +   assign branch_predict_d = bi_unconditional | bi_conditional;
 45.1462 +   assign branch_predict_taken_d = bi_unconditional ? 1'b1 : (bi_conditional ? instruction_d[15] : 1'b0);
 45.1463 +   
 45.1464 +   // Compute branch target address: Branch PC PLUS Offset
 45.1465 +   assign branch_target_d = pc_d + branch_offset_d;
 45.1466 +
 45.1467 +   // Compute fetch address. Address of instruction sequentially after the
 45.1468 +   // branch if branch is not taken. Target address of branch is branch is
 45.1469 +   // taken
 45.1470 +   assign branch_predict_address_d = branch_predict_taken_d ? branch_target_d : pc_f;
 45.1471 +
 45.1472 +// D stage result selection
 45.1473 +always @(*)
 45.1474 +begin
 45.1475 +    d_result_0 = d_result_sel_0_d[0] ? {pc_f, 2'b00} : bypass_data_0; 
 45.1476 +    case (d_result_sel_1_d)
 45.1477 +    `LM32_D_RESULT_SEL_1_ZERO:      d_result_1 = {`LM32_WORD_WIDTH{1'b0}};
 45.1478 +    `LM32_D_RESULT_SEL_1_REG_1:     d_result_1 = bypass_data_1;
 45.1479 +    `LM32_D_RESULT_SEL_1_IMMEDIATE: d_result_1 = immediate_d;
 45.1480 +    default:                        d_result_1 = {`LM32_WORD_WIDTH{1'bx}};
 45.1481 +    endcase
 45.1482 +end
 45.1483 +
 45.1484 +`ifdef CFG_USER_ENABLED    
 45.1485 +// Operands for user-defined instructions
 45.1486 +assign user_operand_0 = operand_0_x;
 45.1487 +assign user_operand_1 = operand_1_x;
 45.1488 +`endif
 45.1489 +
 45.1490 +`ifdef CFG_SIGN_EXTEND_ENABLED
 45.1491 +// Sign-extension
 45.1492 +assign sextb_result_x = {{24{operand_0_x[7]}}, operand_0_x[7:0]};
 45.1493 +assign sexth_result_x = {{16{operand_0_x[15]}}, operand_0_x[15:0]};
 45.1494 +assign sext_result_x = size_x == `LM32_SIZE_BYTE ? sextb_result_x : sexth_result_x;
 45.1495 +`endif
 45.1496 +
 45.1497 +`ifdef LM32_NO_BARREL_SHIFT
 45.1498 +// Only single bit shift operations are supported when barrel-shifter isn't implemented
 45.1499 +assign shifter_result_x = {operand_0_x[`LM32_WORD_WIDTH-1] & sign_extend_x, operand_0_x[`LM32_WORD_WIDTH-1:1]};
 45.1500 +`endif
 45.1501 +
 45.1502 +// Condition evaluation
 45.1503 +assign cmp_zero = operand_0_x == operand_1_x;
 45.1504 +assign cmp_negative = adder_result_x[`LM32_WORD_WIDTH-1];
 45.1505 +assign cmp_overflow = adder_overflow_x;
 45.1506 +assign cmp_carry_n = adder_carry_n_x;
 45.1507 +always @(*)
 45.1508 +begin
 45.1509 +    case (condition_x)
 45.1510 +    `LM32_CONDITION_U1:   condition_met_x = `TRUE;
 45.1511 +    `LM32_CONDITION_U2:   condition_met_x = `TRUE;
 45.1512 +    `LM32_CONDITION_E:    condition_met_x = cmp_zero;
 45.1513 +    `LM32_CONDITION_NE:   condition_met_x = !cmp_zero;
 45.1514 +    `LM32_CONDITION_G:    condition_met_x = !cmp_zero && (cmp_negative == cmp_overflow);
 45.1515 +    `LM32_CONDITION_GU:   condition_met_x = cmp_carry_n && !cmp_zero;
 45.1516 +    `LM32_CONDITION_GE:   condition_met_x = cmp_negative == cmp_overflow;
 45.1517 +    `LM32_CONDITION_GEU:  condition_met_x = cmp_carry_n;
 45.1518 +    default:              condition_met_x = 1'bx;
 45.1519 +    endcase 
 45.1520 +end
 45.1521 +
 45.1522 +// X stage result selection
 45.1523 +always @(*)
 45.1524 +begin
 45.1525 +    x_result =   x_result_sel_add_x ? adder_result_x 
 45.1526 +               : x_result_sel_csr_x ? csr_read_data_x
 45.1527 +`ifdef CFG_SIGN_EXTEND_ENABLED
 45.1528 +               : x_result_sel_sext_x ? sext_result_x
 45.1529 +`endif
 45.1530 +`ifdef CFG_USER_ENABLED
 45.1531 +               : x_result_sel_user_x ? user_result
 45.1532 +`endif
 45.1533 +`ifdef LM32_NO_BARREL_SHIFT
 45.1534 +               : x_result_sel_shift_x ? shifter_result_x
 45.1535 +`endif
 45.1536 +`ifdef LM32_MC_ARITHMETIC_ENABLED
 45.1537 +               : x_result_sel_mc_arith_x ? mc_result_x
 45.1538 +`endif
 45.1539 +               : logic_result_x;
 45.1540 +end
 45.1541 +
 45.1542 +// M stage result selection
 45.1543 +always @(*)
 45.1544 +begin
 45.1545 +    m_result =   m_result_sel_compare_m ? {{`LM32_WORD_WIDTH-1{1'b0}}, condition_met_m}
 45.1546 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
 45.1547 +               : m_result_sel_shift_m ? shifter_result_m
 45.1548 +`endif
 45.1549 +               : operand_m; 
 45.1550 +end
 45.1551 +
 45.1552 +// W stage result selection
 45.1553 +always @(*)
 45.1554 +begin
 45.1555 +    w_result =    w_result_sel_load_w ? load_data_w
 45.1556 +`ifdef CFG_PL_MULTIPLY_ENABLED
 45.1557 +                : w_result_sel_mul_w ? multiplier_result_w
 45.1558 +`endif
 45.1559 +                : operand_w;
 45.1560 +end
 45.1561 +
 45.1562 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
 45.1563 +// Indicate when a branch should be taken in X stage
 45.1564 +assign branch_taken_x =      (stall_x == `FALSE)
 45.1565 +                          && (   (branch_x == `TRUE)
 45.1566 +                              && ((condition_x == `LM32_CONDITION_U1) || (condition_x == `LM32_CONDITION_U2))
 45.1567 +                              && (valid_x == `TRUE)
 45.1568 +                              && (branch_predict_x == `FALSE)
 45.1569 +                             ); 
 45.1570 +`endif
 45.1571 +
 45.1572 +// Indicate when a branch should be taken in M stage (exceptions are a type of branch)
 45.1573 +assign branch_taken_m =      (stall_m == `FALSE) 
 45.1574 +                          && (   (   (branch_m == `TRUE) 
 45.1575 +                                  && (valid_m == `TRUE)
 45.1576 +                                  && (   (   (condition_met_m == `TRUE)
 45.1577 +					  && (branch_predict_taken_m == `FALSE)
 45.1578 +					 )
 45.1579 +				      || (   (condition_met_m == `FALSE)
 45.1580 +					  && (branch_predict_m == `TRUE)
 45.1581 +					  && (branch_predict_taken_m == `TRUE)
 45.1582 +					 )
 45.1583 +				     )
 45.1584 +                                 ) 
 45.1585 +                              || (exception_m == `TRUE)
 45.1586 +                             );
 45.1587 +
 45.1588 +// Indicate when a branch in M stage is mispredicted as being taken
 45.1589 +assign branch_mispredict_taken_m =    (condition_met_m == `FALSE)
 45.1590 +                                   && (branch_predict_m == `TRUE)
 45.1591 +	   			   && (branch_predict_taken_m == `TRUE);
 45.1592 +   
 45.1593 +// Indicate when a branch in M stage will cause flush in X stage
 45.1594 +assign branch_flushX_m =    (stall_m == `FALSE)
 45.1595 +                         && (   (   (branch_m == `TRUE) 
 45.1596 +                                 && (valid_m == `TRUE)
 45.1597 +			         && (   (condition_met_m == `TRUE)
 45.1598 +				     || (   (condition_met_m == `FALSE)
 45.1599 +					 && (branch_predict_m == `TRUE)
 45.1600 +					 && (branch_predict_taken_m == `TRUE)
 45.1601 +					)
 45.1602 +				    )
 45.1603 +			        )
 45.1604 +			     || (exception_m == `TRUE)
 45.1605 +			    );
 45.1606 +
 45.1607 +// Generate signal that will kill instructions in each pipeline stage when necessary
 45.1608 +assign kill_f =    (   (valid_d == `TRUE)
 45.1609 +                    && (branch_predict_taken_d == `TRUE)
 45.1610 +		   )
 45.1611 +                || (branch_taken_m == `TRUE) 
 45.1612 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
 45.1613 +                || (branch_taken_x == `TRUE)
 45.1614 +`endif
 45.1615 +`ifdef CFG_ICACHE_ENABLED
 45.1616 +                || (icache_refill_request == `TRUE) 
 45.1617 +`endif
 45.1618 +`ifdef CFG_DCACHE_ENABLED                
 45.1619 +                || (dcache_refill_request == `TRUE)
 45.1620 +`endif
 45.1621 +                ;
 45.1622 +assign kill_d =    (branch_taken_m == `TRUE) 
 45.1623 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
 45.1624 +                || (branch_taken_x == `TRUE)
 45.1625 +`endif
 45.1626 +`ifdef CFG_ICACHE_ENABLED
 45.1627 +                || (icache_refill_request == `TRUE)     
 45.1628 +`endif                
 45.1629 +`ifdef CFG_DCACHE_ENABLED                
 45.1630 +                || (dcache_refill_request == `TRUE)
 45.1631 +`endif
 45.1632 +                ;
 45.1633 +assign kill_x =    (branch_flushX_m == `TRUE) 
 45.1634 +`ifdef CFG_DCACHE_ENABLED                
 45.1635 +                || (dcache_refill_request == `TRUE)
 45.1636 +`endif
 45.1637 +                ;
 45.1638 +assign kill_m =    `FALSE
 45.1639 +`ifdef CFG_DCACHE_ENABLED                
 45.1640 +                || (dcache_refill_request == `TRUE)
 45.1641 +`endif
 45.1642 +                ;                
 45.1643 +assign kill_w =    `FALSE
 45.1644 +`ifdef CFG_DCACHE_ENABLED                
 45.1645 +                || (dcache_refill_request == `TRUE)
 45.1646 +`endif                
 45.1647 +                ;
 45.1648 +
 45.1649 +// Exceptions
 45.1650 +
 45.1651 +`ifdef CFG_DEBUG_ENABLED
 45.1652 +assign breakpoint_exception =    (   (   (break_x == `TRUE)
 45.1653 +				      || (bp_match == `TRUE)
 45.1654 +				     )
 45.1655 +				  && (valid_x == `TRUE)
 45.1656 +				 )
 45.1657 +`ifdef CFG_JTAG_ENABLED
 45.1658 +                              || (jtag_break == `TRUE)
 45.1659 +`endif
 45.1660 +                              ;
 45.1661 +`endif
 45.1662 +
 45.1663 +`ifdef CFG_DEBUG_ENABLED
 45.1664 +assign watchpoint_exception = wp_match == `TRUE;
 45.1665 +`endif
 45.1666 +
 45.1667 +`ifdef CFG_BUS_ERRORS_ENABLED
 45.1668 +assign instruction_bus_error_exception = (   (bus_error_x == `TRUE)
 45.1669 +                                          && (valid_x == `TRUE)
 45.1670 +                                         );
 45.1671 +assign data_bus_error_exception = data_bus_error_seen == `TRUE;
 45.1672 +`endif
 45.1673 +
 45.1674 +`ifdef CFG_MC_DIVIDE_ENABLED
 45.1675 +assign divide_by_zero_exception = divide_by_zero_x == `TRUE;
 45.1676 +`endif
 45.1677 +
 45.1678 +assign system_call_exception = (   (scall_x == `TRUE)
 45.1679 +`ifdef CFG_BUS_ERRORS_ENABLED
 45.1680 +                                && (valid_x == `TRUE)
 45.1681 +`endif
 45.1682 +			       );
 45.1683 +
 45.1684 +`ifdef CFG_DEBUG_ENABLED
 45.1685 +assign debug_exception_x =  (breakpoint_exception == `TRUE)
 45.1686 +                         || (watchpoint_exception == `TRUE)
 45.1687 +                         ;
 45.1688 +
 45.1689 +assign non_debug_exception_x = (system_call_exception == `TRUE)
 45.1690 +`ifdef CFG_JTAG_ENABLED
 45.1691 +                            || (reset_exception == `TRUE)
 45.1692 +`endif
 45.1693 +`ifdef CFG_BUS_ERRORS_ENABLED
 45.1694 +                            || (instruction_bus_error_exception == `TRUE)
 45.1695 +                            || (data_bus_error_exception == `TRUE)
 45.1696 +`endif
 45.1697 +`ifdef CFG_MC_DIVIDE_ENABLED
 45.1698 +                            || (divide_by_zero_exception == `TRUE)
 45.1699 +`endif
 45.1700 +`ifdef CFG_INTERRUPTS_ENABLED
 45.1701 +                            || (   (interrupt_exception == `TRUE)
 45.1702 +`ifdef LM32_SINGLE_STEP_ENABLED
 45.1703 +                                && (dc_ss == `FALSE)
 45.1704 +`endif                            
 45.1705 +`ifdef CFG_BUS_ERRORS_ENABLED
 45.1706 + 				&& (store_q_m == `FALSE)
 45.1707 +				&& (D_CYC_O == `FALSE)
 45.1708 +`endif
 45.1709 +                               )
 45.1710 +`endif
 45.1711 +                            ;
 45.1712 +
 45.1713 +assign exception_x = (debug_exception_x == `TRUE) || (non_debug_exception_x == `TRUE);
 45.1714 +`else
 45.1715 +assign exception_x =           (system_call_exception == `TRUE)
 45.1716 +`ifdef CFG_BUS_ERRORS_ENABLED
 45.1717 +                            || (instruction_bus_error_exception == `TRUE)
 45.1718 +                            || (data_bus_error_exception == `TRUE)
 45.1719 +`endif
 45.1720 +`ifdef CFG_MC_DIVIDE_ENABLED
 45.1721 +                            || (divide_by_zero_exception == `TRUE)
 45.1722 +`endif
 45.1723 +`ifdef CFG_INTERRUPTS_ENABLED
 45.1724 +                            || (   (interrupt_exception == `TRUE)
 45.1725 +`ifdef LM32_SINGLE_STEP_ENABLED
 45.1726 +                                && (dc_ss == `FALSE)
 45.1727 +`endif                            
 45.1728 +`ifdef CFG_BUS_ERRORS_ENABLED
 45.1729 + 				&& (store_q_m == `FALSE)
 45.1730 +				&& (D_CYC_O == `FALSE)
 45.1731 +`endif
 45.1732 +                               )
 45.1733 +`endif
 45.1734 +                            ;
 45.1735 +`endif
 45.1736 +
 45.1737 +// Exception ID
 45.1738 +always @(*)
 45.1739 +begin
 45.1740 +`ifdef CFG_DEBUG_ENABLED
 45.1741 +`ifdef CFG_JTAG_ENABLED
 45.1742 +    if (reset_exception == `TRUE)
 45.1743 +        eid_x = `LM32_EID_RESET;
 45.1744 +    else
 45.1745 +`endif     
 45.1746 +`ifdef CFG_BUS_ERRORS_ENABLED
 45.1747 +         if (data_bus_error_exception == `TRUE)
 45.1748 +        eid_x = `LM32_EID_DATA_BUS_ERROR;
 45.1749 +    else
 45.1750 +`endif
 45.1751 +         if (breakpoint_exception == `TRUE)
 45.1752 +        eid_x = `LM32_EID_BREAKPOINT;
 45.1753 +    else
 45.1754 +`endif
 45.1755 +`ifdef CFG_BUS_ERRORS_ENABLED
 45.1756 +         if (data_bus_error_exception == `TRUE)
 45.1757 +        eid_x = `LM32_EID_DATA_BUS_ERROR;
 45.1758 +    else
 45.1759 +         if (instruction_bus_error_exception == `TRUE)
 45.1760 +        eid_x = `LM32_EID_INST_BUS_ERROR;
 45.1761 +    else
 45.1762 +`endif
 45.1763 +`ifdef CFG_DEBUG_ENABLED
 45.1764 +         if (watchpoint_exception == `TRUE)
 45.1765 +        eid_x = `LM32_EID_WATCHPOINT;
 45.1766 +    else 
 45.1767 +`endif
 45.1768 +`ifdef CFG_MC_DIVIDE_ENABLED
 45.1769 +         if (divide_by_zero_exception == `TRUE)
 45.1770 +        eid_x = `LM32_EID_DIVIDE_BY_ZERO;
 45.1771 +    else
 45.1772 +`endif
 45.1773 +`ifdef CFG_INTERRUPTS_ENABLED
 45.1774 +         if (   (interrupt_exception == `TRUE)
 45.1775 +`ifdef LM32_SINGLE_STEP_ENABLED
 45.1776 +             && (dc_ss == `FALSE)
 45.1777 +`endif                            
 45.1778 +            )
 45.1779 +        eid_x = `LM32_EID_INTERRUPT;
 45.1780 +    else
 45.1781 +`endif
 45.1782 +        eid_x = `LM32_EID_SCALL;
 45.1783 +end
 45.1784 +
 45.1785 +// Stall generation
 45.1786 +
 45.1787 +assign stall_a = (stall_f == `TRUE);
 45.1788 +                
 45.1789 +assign stall_f = (stall_d == `TRUE);
 45.1790 +                
 45.1791 +assign stall_d =   (stall_x == `TRUE) 
 45.1792 +                || (   (interlock == `TRUE)
 45.1793 +                    && (kill_d == `FALSE)
 45.1794 +                   ) 
 45.1795 +		|| (   (   (eret_d == `TRUE)
 45.1796 +			|| (scall_d == `TRUE)
 45.1797 +`ifdef CFG_BUS_ERRORS_ENABLED
 45.1798 +			|| (bus_error_d == `TRUE)
 45.1799 +`endif
 45.1800 +		       )
 45.1801 +		    && (   (load_q_x == `TRUE)
 45.1802 +			|| (load_q_m == `TRUE)
 45.1803 +			|| (store_q_x == `TRUE)
 45.1804 +			|| (store_q_m == `TRUE)
 45.1805 +			|| (D_CYC_O == `TRUE)
 45.1806 +		       )
 45.1807 +                    && (kill_d == `FALSE)
 45.1808 +		   )
 45.1809 +`ifdef CFG_DEBUG_ENABLED
 45.1810 +		|| (   (   (break_d == `TRUE)
 45.1811 +			|| (bret_d == `TRUE)
 45.1812 +		       )
 45.1813 +		    && (   (load_q_x == `TRUE)
 45.1814 +			|| (store_q_x == `TRUE)
 45.1815 +			|| (load_q_m == `TRUE)
 45.1816 +			|| (store_q_m == `TRUE)
 45.1817 +			|| (D_CYC_O == `TRUE)
 45.1818 +		       )
 45.1819 +                    && (kill_d == `FALSE)
 45.1820 +		   )
 45.1821 +`endif                   
 45.1822 +                || (   (csr_write_enable_d == `TRUE)
 45.1823 +                    && (load_q_x == `TRUE)
 45.1824 +                   )                      
 45.1825 +                ;
 45.1826 +                
 45.1827 +assign stall_x =    (stall_m == `TRUE)
 45.1828 +`ifdef LM32_MC_ARITHMETIC_ENABLED
 45.1829 +                 || (   (mc_stall_request_x == `TRUE)
 45.1830 +                     && (kill_x == `FALSE)
 45.1831 +                    ) 
 45.1832 +`endif
 45.1833 +`ifdef CFG_IROM_ENABLED
 45.1834 +                 // Stall load/store instruction in D stage if there is an ongoing store
 45.1835 +                 // operation to instruction ROM in M stage
 45.1836 +                 || (   (irom_stall_request_x == `TRUE)
 45.1837 +		     && (   (load_d == `TRUE)
 45.1838 +			 || (store_d == `TRUE)
 45.1839 +			)
 45.1840 +		    )
 45.1841 +`endif
 45.1842 +                 ;
 45.1843 +
 45.1844 +assign stall_m =    (stall_wb_load == `TRUE)
 45.1845 +`ifdef CFG_SIZE_OVER_SPEED
 45.1846 +                 || (D_CYC_O == `TRUE)
 45.1847 +`else
 45.1848 +                 || (   (D_CYC_O == `TRUE)
 45.1849 +                     && (   (store_m == `TRUE)
 45.1850 +		         /*
 45.1851 +			  Bug: Following loop does not allow interrupts to be services since
 45.1852 +			  either D_CYC_O or store_m is always high during entire duration of
 45.1853 +			  loop.
 45.1854 +		          L1:	addi	r1, r1, 1
 45.1855 +			  	sw	(r2,0), r1
 45.1856 +			  	bi	L1
 45.1857 +			  
 45.1858 +			  Introduce a single-cycle stall when a wishbone cycle is in progress
 45.1859 +			  and a new store instruction is in Execute stage and a interrupt
 45.1860 +			  exception has occured. This stall will ensure that D_CYC_O and 
 45.1861 +			  store_m will both be low for one cycle.
 45.1862 +			  */
 45.1863 +`ifdef CFG_INTERRUPTS_ENABLED
 45.1864 +		         || ((store_x == `TRUE) && (interrupt_exception == `TRUE))
 45.1865 +`endif
 45.1866 +                         || (load_m == `TRUE)
 45.1867 +                         || (load_x == `TRUE)
 45.1868 +                        ) 
 45.1869 +                    ) 
 45.1870 +`endif                 
 45.1871 +`ifdef CFG_DCACHE_ENABLED
 45.1872 +                 || (dcache_stall_request == `TRUE)     // Need to stall in case a taken branch is in M stage and data cache is only being flush, so wont be restarted
 45.1873 +`endif                                    
 45.1874 +`ifdef CFG_ICACHE_ENABLED
 45.1875 +                 || (icache_stall_request == `TRUE)     // Pipeline needs to be stalled otherwise branches may be lost
 45.1876 +                 || ((I_CYC_O == `TRUE) && ((branch_m == `TRUE) || (exception_m == `TRUE))) 
 45.1877 +`else
 45.1878 +`ifdef CFG_IWB_ENABLED
 45.1879 +                 || (I_CYC_O == `TRUE)            
 45.1880 +`endif
 45.1881 +`endif                               
 45.1882 +`ifdef CFG_USER_ENABLED
 45.1883 +                 || (   (user_valid == `TRUE)           // Stall whole pipeline, rather than just X stage, where the instruction is, so we don't have to worry about exceptions (maybe)
 45.1884 +                     && (user_complete == `FALSE)
 45.1885 +                    )
 45.1886 +`endif
 45.1887 +                 ;      
 45.1888 +
 45.1889 +// Qualify state changing control signals
 45.1890 +`ifdef LM32_MC_ARITHMETIC_ENABLED
 45.1891 +assign q_d = (valid_d == `TRUE) && (kill_d == `FALSE);
 45.1892 +`endif
 45.1893 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED
 45.1894 +assign shift_left_q_d = (shift_left_d == `TRUE) && (q_d == `TRUE);
 45.1895 +assign shift_right_q_d = (shift_right_d == `TRUE) && (q_d == `TRUE);
 45.1896 +`endif
 45.1897 +`ifdef CFG_MC_MULTIPLY_ENABLED
 45.1898 +assign multiply_q_d = (multiply_d == `TRUE) && (q_d == `TRUE);
 45.1899 +`endif
 45.1900 +`ifdef CFG_MC_DIVIDE_ENABLED
 45.1901 +assign divide_q_d = (divide_d == `TRUE) && (q_d == `TRUE);
 45.1902 +assign modulus_q_d = (modulus_d == `TRUE) && (q_d == `TRUE);
 45.1903 +`endif
 45.1904 +assign q_x = (valid_x == `TRUE) && (kill_x == `FALSE);
 45.1905 +assign csr_write_enable_q_x = (csr_write_enable_x == `TRUE) && (q_x == `TRUE);
 45.1906 +assign eret_q_x = (eret_x == `TRUE) && (q_x == `TRUE);
 45.1907 +`ifdef CFG_DEBUG_ENABLED
 45.1908 +assign bret_q_x = (bret_x == `TRUE) && (q_x == `TRUE);
 45.1909 +`endif
 45.1910 +assign load_q_x = (load_x == `TRUE) 
 45.1911 +               && (q_x == `TRUE)
 45.1912 +`ifdef CFG_DEBUG_ENABLED
 45.1913 +               && (bp_match == `FALSE)
 45.1914 +`endif
 45.1915 +                  ;
 45.1916 +assign store_q_x = (store_x == `TRUE) 
 45.1917 +               && (q_x == `TRUE)
 45.1918 +`ifdef CFG_DEBUG_ENABLED
 45.1919 +               && (bp_match == `FALSE)
 45.1920 +`endif
 45.1921 +                  ;
 45.1922 +`ifdef CFG_USER_ENABLED
 45.1923 +assign user_valid = (x_result_sel_user_x == `TRUE) && (q_x == `TRUE);
 45.1924 +`endif                              
 45.1925 +assign q_m = (valid_m == `TRUE) && (kill_m == `FALSE) && (exception_m == `FALSE);
 45.1926 +assign load_q_m = (load_m == `TRUE) && (q_m == `TRUE);
 45.1927 +assign store_q_m = (store_m == `TRUE) && (q_m == `TRUE);
 45.1928 +`ifdef CFG_DEBUG_ENABLED
 45.1929 +assign debug_exception_q_w = ((debug_exception_w == `TRUE) && (valid_w == `TRUE));
 45.1930 +assign non_debug_exception_q_w = ((non_debug_exception_w == `TRUE) && (valid_w == `TRUE));        
 45.1931 +`else
 45.1932 +assign exception_q_w = ((exception_w == `TRUE) && (valid_w == `TRUE));        
 45.1933 +`endif
 45.1934 +// Don't qualify register write enables with kill, as the signal is needed early, and it doesn't matter if the instruction is killed (except for the actual write - but that is handled separately)
 45.1935 +assign write_enable_q_x = (write_enable_x == `TRUE) && (valid_x == `TRUE) && (branch_flushX_m == `FALSE);
 45.1936 +assign write_enable_q_m = (write_enable_m == `TRUE) && (valid_m == `TRUE);
 45.1937 +assign write_enable_q_w = (write_enable_w == `TRUE) && (valid_w == `TRUE);
 45.1938 +// The enable that actually does write the registers needs to be qualified with kill
 45.1939 +assign reg_write_enable_q_w = (write_enable_w == `TRUE) && (kill_w == `FALSE) && (valid_w == `TRUE);
 45.1940 +
 45.1941 +// Configuration (CFG) CSR
 45.1942 +assign cfg = {
 45.1943 +              `LM32_REVISION,
 45.1944 +              watchpoints[3:0],
 45.1945 +              breakpoints[3:0],
 45.1946 +              interrupts[5:0],
 45.1947 +`ifdef CFG_JTAG_UART_ENABLED
 45.1948 +              `TRUE,
 45.1949 +`else
 45.1950 +              `FALSE,
 45.1951 +`endif
 45.1952 +`ifdef CFG_ROM_DEBUG_ENABLED
 45.1953 +              `TRUE,
 45.1954 +`else
 45.1955 +              `FALSE,
 45.1956 +`endif
 45.1957 +`ifdef CFG_HW_DEBUG_ENABLED
 45.1958 +              `TRUE,
 45.1959 +`else
 45.1960 +              `FALSE,
 45.1961 +`endif
 45.1962 +`ifdef CFG_DEBUG_ENABLED
 45.1963 +              `TRUE,
 45.1964 +`else
 45.1965 +              `FALSE,
 45.1966 +`endif
 45.1967 +`ifdef CFG_ICACHE_ENABLED
 45.1968 +              `TRUE,
 45.1969 +`else
 45.1970 +              `FALSE,
 45.1971 +`endif
 45.1972 +`ifdef CFG_DCACHE_ENABLED
 45.1973 +              `TRUE,
 45.1974 +`else
 45.1975 +              `FALSE,
 45.1976 +`endif
 45.1977 +`ifdef CFG_CYCLE_COUNTER_ENABLED
 45.1978 +              `TRUE,
 45.1979 +`else
 45.1980 +              `FALSE,
 45.1981 +`endif
 45.1982 +`ifdef CFG_USER_ENABLED
 45.1983 +              `TRUE,
 45.1984 +`else
 45.1985 +              `FALSE,
 45.1986 +`endif
 45.1987 +`ifdef CFG_SIGN_EXTEND_ENABLED
 45.1988 +              `TRUE,
 45.1989 +`else
 45.1990 +              `FALSE,
 45.1991 +`endif
 45.1992 +`ifdef LM32_BARREL_SHIFT_ENABLED
 45.1993 +              `TRUE,
 45.1994 +`else
 45.1995 +              `FALSE,
 45.1996 +`endif
 45.1997 +`ifdef CFG_MC_DIVIDE_ENABLED
 45.1998 +              `TRUE,
 45.1999 +`else
 45.2000 +              `FALSE,
 45.2001 +`endif
 45.2002 +`ifdef LM32_MULTIPLY_ENABLED 
 45.2003 +              `TRUE
 45.2004 +`else
 45.2005 +              `FALSE
 45.2006 +`endif
 45.2007 +              };
 45.2008 +
 45.2009 +assign cfg2 = {
 45.2010 +		     30'b0,
 45.2011 +`ifdef CFG_IROM_ENABLED
 45.2012 +		     `TRUE,
 45.2013 +`else
 45.2014 +		     `FALSE,
 45.2015 +`endif
 45.2016 +`ifdef CFG_DRAM_ENABLED
 45.2017 +		     `TRUE
 45.2018 +`else
 45.2019 +		     `FALSE
 45.2020 +`endif
 45.2021 +		     };
 45.2022 +   
 45.2023 +// Cache flush
 45.2024 +`ifdef CFG_ICACHE_ENABLED
 45.2025 +assign iflush = (   (csr_write_enable_d == `TRUE) 
 45.2026 +                 && (csr_d == `LM32_CSR_ICC)
 45.2027 +                 && (stall_d == `FALSE)
 45.2028 +                 && (kill_d == `FALSE)
 45.2029 +                 && (valid_d == `TRUE))
 45.2030 +// Added by GSI: needed to flush cache after loading firmware per JTAG
 45.2031 +`ifdef CFG_HW_DEBUG_ENABLED
 45.2032 +             ||
 45.2033 +                (   (jtag_csr_write_enable == `TRUE)
 45.2034 +		 && (jtag_csr == `LM32_CSR_ICC))
 45.2035 +`endif
 45.2036 +		 ;
 45.2037 +`endif 
 45.2038 +`ifdef CFG_DCACHE_ENABLED
 45.2039 +assign dflush_x = (   (csr_write_enable_q_x == `TRUE) 
 45.2040 +                   && (csr_x == `LM32_CSR_DCC))
 45.2041 +// Added by GSI: needed to flush cache after loading firmware per JTAG
 45.2042 +`ifdef CFG_HW_DEBUG_ENABLED
 45.2043 +               ||
 45.2044 +                  (   (jtag_csr_write_enable == `TRUE)
 45.2045 +		   && (jtag_csr == `LM32_CSR_DCC))
 45.2046 +`endif
 45.2047 +		   ;
 45.2048 +`endif 
 45.2049 +
 45.2050 +// Extract CSR index
 45.2051 +assign csr_d = read_idx_0_d[`LM32_CSR_RNG];
 45.2052 +
 45.2053 +// CSR reads
 45.2054 +always @(*)
 45.2055 +begin
 45.2056 +    case (csr_x)
 45.2057 +`ifdef CFG_INTERRUPTS_ENABLED
 45.2058 +    `LM32_CSR_IE,
 45.2059 +    `LM32_CSR_IM,
 45.2060 +    `LM32_CSR_IP:   csr_read_data_x = interrupt_csr_read_data_x;  
 45.2061 +`endif
 45.2062 +`ifdef CFG_CYCLE_COUNTER_ENABLED
 45.2063 +    `LM32_CSR_CC:   csr_read_data_x = cc;
 45.2064 +`endif
 45.2065 +    `LM32_CSR_CFG:  csr_read_data_x = cfg;
 45.2066 +    `LM32_CSR_EBA:  csr_read_data_x = {eba, 8'h00};
 45.2067 +`ifdef CFG_DEBUG_ENABLED
 45.2068 +    `LM32_CSR_DEBA: csr_read_data_x = {deba, 8'h00};
 45.2069 +`endif
 45.2070 +`ifdef CFG_JTAG_UART_ENABLED
 45.2071 +    `LM32_CSR_JTX:  csr_read_data_x = jtx_csr_read_data;  
 45.2072 +    `LM32_CSR_JRX:  csr_read_data_x = jrx_csr_read_data;
 45.2073 +`endif
 45.2074 +    `LM32_CSR_CFG2: csr_read_data_x = cfg2;
 45.2075 +      
 45.2076 +    default:        csr_read_data_x = {`LM32_WORD_WIDTH{1'bx}};
 45.2077 +    endcase
 45.2078 +end
 45.2079 +
 45.2080 +/////////////////////////////////////////////////////
 45.2081 +// Sequential Logic
 45.2082 +/////////////////////////////////////////////////////
 45.2083 +
 45.2084 +// Exception Base Address (EBA) CSR
 45.2085 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
 45.2086 +begin
 45.2087 +    if (rst_i == `TRUE)
 45.2088 +        eba <= eba_reset[`LM32_PC_WIDTH+2-1:8];
 45.2089 +    else
 45.2090 +    begin
 45.2091 +        if ((csr_write_enable_q_x == `TRUE) && (csr_x == `LM32_CSR_EBA) && (stall_x == `FALSE))
 45.2092 +            eba <= operand_1_x[`LM32_PC_WIDTH+2-1:8];
 45.2093 +`ifdef CFG_HW_DEBUG_ENABLED
 45.2094 +        if ((jtag_csr_write_enable == `TRUE) && (jtag_csr == `LM32_CSR_EBA))
 45.2095 +            eba <= jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8];
 45.2096 +`endif
 45.2097 +    end
 45.2098 +end
 45.2099 +
 45.2100 +`ifdef CFG_DEBUG_ENABLED
 45.2101 +// Debug Exception Base Address (DEBA) CSR
 45.2102 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
 45.2103 +begin
 45.2104 +    if (rst_i == `TRUE)
 45.2105 +        deba <= deba_reset[`LM32_PC_WIDTH+2-1:8];
 45.2106 +    else
 45.2107 +    begin
 45.2108 +        if ((csr_write_enable_q_x == `TRUE) && (csr_x == `LM32_CSR_DEBA) && (stall_x == `FALSE))
 45.2109 +            deba <= operand_1_x[`LM32_PC_WIDTH+2-1:8];
 45.2110 +`ifdef CFG_HW_DEBUG_ENABLED
 45.2111 +        if ((jtag_csr_write_enable == `TRUE) && (jtag_csr == `LM32_CSR_DEBA))
 45.2112 +            deba <= jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8];
 45.2113 +`endif
 45.2114 +    end
 45.2115 +end
 45.2116 +`endif
 45.2117 +
 45.2118 +// Cycle Counter (CC) CSR
 45.2119 +`ifdef CFG_CYCLE_COUNTER_ENABLED
 45.2120 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
 45.2121 +begin
 45.2122 +    if (rst_i == `TRUE)
 45.2123 +        cc <= {`LM32_WORD_WIDTH{1'b0}};
 45.2124 +    else
 45.2125 +        cc <= cc + 1'b1;
 45.2126 +end
 45.2127 +`endif
 45.2128 +
 45.2129 +`ifdef CFG_BUS_ERRORS_ENABLED
 45.2130 +// Watch for data bus errors
 45.2131 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
 45.2132 +begin
 45.2133 +    if (rst_i == `TRUE)
 45.2134 +        data_bus_error_seen <= `FALSE;
 45.2135 +    else
 45.2136 +    begin
 45.2137 +        // Set flag when bus error is detected
 45.2138 +        if ((D_ERR_I == `TRUE) && (D_CYC_O == `TRUE))
 45.2139 +            data_bus_error_seen <= `TRUE;
 45.2140 +        // Clear flag when exception is taken
 45.2141 +        if ((exception_m == `TRUE) && (kill_m == `FALSE))
 45.2142 +            data_bus_error_seen <= `FALSE;
 45.2143 +    end
 45.2144 +end
 45.2145 +`endif
 45.2146 + 
 45.2147 +// Valid bits to indicate whether an instruction in a partcular pipeline stage is valid or not  
 45.2148 +
 45.2149 +`ifdef CFG_ICACHE_ENABLED
 45.2150 +`ifdef CFG_DCACHE_ENABLED
 45.2151 +always @(*)
 45.2152 +begin
 45.2153 +    if (   (icache_refill_request == `TRUE) 
 45.2154 +        || (dcache_refill_request == `TRUE)
 45.2155 +       )
 45.2156 +        valid_a = `FALSE;
 45.2157 +    else if (   (icache_restart_request == `TRUE) 
 45.2158 +             || (dcache_restart_request == `TRUE) 
 45.2159 +            ) 
 45.2160 +        valid_a = `TRUE;
 45.2161 +    else 
 45.2162 +        valid_a = !icache_refilling && !dcache_refilling;
 45.2163 +end 
 45.2164 +`else
 45.2165 +always @(*)
 45.2166 +begin
 45.2167 +    if (icache_refill_request == `TRUE) 
 45.2168 +        valid_a = `FALSE;
 45.2169 +    else if (icache_restart_request == `TRUE) 
 45.2170 +        valid_a = `TRUE;
 45.2171 +    else 
 45.2172 +        valid_a = !icache_refilling;
 45.2173 +end 
 45.2174 +`endif
 45.2175 +`else
 45.2176 +`ifdef CFG_DCACHE_ENABLED
 45.2177 +always @(*)
 45.2178 +begin
 45.2179 +    if (dcache_refill_request == `TRUE) 
 45.2180 +        valid_a = `FALSE;
 45.2181 +    else if (dcache_restart_request == `TRUE) 
 45.2182 +        valid_a = `TRUE;
 45.2183 +    else 
 45.2184 +        valid_a = !dcache_refilling;
 45.2185 +end 
 45.2186 +`endif
 45.2187 +`endif
 45.2188 +
 45.2189 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
 45.2190 +begin
 45.2191 +    if (rst_i == `TRUE)
 45.2192 +    begin
 45.2193 +        valid_f <= `FALSE;
 45.2194 +        valid_d <= `FALSE;
 45.2195 +        valid_x <= `FALSE;
 45.2196 +        valid_m <= `FALSE;
 45.2197 +        valid_w <= `FALSE;
 45.2198 +    end
 45.2199 +    else
 45.2200 +    begin    
 45.2201 +        if ((kill_f == `TRUE) || (stall_a == `FALSE))
 45.2202 +`ifdef LM32_CACHE_ENABLED
 45.2203 +            valid_f <= valid_a;    
 45.2204 +`else
 45.2205 +            valid_f <= `TRUE;
 45.2206 +`endif            
 45.2207 +        else if (stall_f == `FALSE)
 45.2208 +            valid_f <= `FALSE;            
 45.2209 +
 45.2210 +        if (kill_d == `TRUE)
 45.2211 +            valid_d <= `FALSE;
 45.2212 +        else if (stall_f == `FALSE)
 45.2213 +            valid_d <= valid_f & !kill_f;
 45.2214 +        else if (stall_d == `FALSE)
 45.2215 +            valid_d <= `FALSE;
 45.2216 +       
 45.2217 +        if (stall_d == `FALSE)
 45.2218 +            valid_x <= valid_d & !kill_d;
 45.2219 +        else if (kill_x == `TRUE)
 45.2220 +            valid_x <= `FALSE;
 45.2221 +        else if (stall_x == `FALSE)
 45.2222 +            valid_x <= `FALSE;
 45.2223 +
 45.2224 +        if (kill_m == `TRUE)
 45.2225 +            valid_m <= `FALSE;
 45.2226 +        else if (stall_x == `FALSE)
 45.2227 +            valid_m <= valid_x & !kill_x;
 45.2228 +        else if (stall_m == `FALSE)
 45.2229 +            valid_m <= `FALSE;
 45.2230 +
 45.2231 +        if (stall_m == `FALSE)
 45.2232 +            valid_w <= valid_m & !kill_m;
 45.2233 +        else 
 45.2234 +            valid_w <= `FALSE;        
 45.2235 +    end
 45.2236 +end
 45.2237 +
 45.2238 +// Microcode pipeline registers
 45.2239 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
 45.2240 +begin
 45.2241 +    if (rst_i == `TRUE)
 45.2242 +    begin
 45.2243 +`ifdef CFG_USER_ENABLED
 45.2244 +        user_opcode <= {`LM32_USER_OPCODE_WIDTH{1'b0}};       
 45.2245 +`endif        
 45.2246 +        operand_0_x <= {`LM32_WORD_WIDTH{1'b0}};
 45.2247 +        operand_1_x <= {`LM32_WORD_WIDTH{1'b0}};
 45.2248 +        store_operand_x <= {`LM32_WORD_WIDTH{1'b0}};
 45.2249 +        branch_target_x <= {`LM32_PC_WIDTH{1'b0}};        
 45.2250 +        x_result_sel_csr_x <= `FALSE;
 45.2251 +`ifdef LM32_MC_ARITHMETIC_ENABLED
 45.2252 +        x_result_sel_mc_arith_x <= `FALSE;
 45.2253 +`endif
 45.2254 +`ifdef LM32_NO_BARREL_SHIFT    
 45.2255 +        x_result_sel_shift_x <= `FALSE;
 45.2256 +`endif
 45.2257 +`ifdef CFG_SIGN_EXTEND_ENABLED
 45.2258 +        x_result_sel_sext_x <= `FALSE;
 45.2259 +`endif  
 45.2260 +	x_result_sel_logic_x <= `FALSE;
 45.2261 +`ifdef CFG_USER_ENABLED
 45.2262 +        x_result_sel_user_x <= `FALSE;
 45.2263 +`endif
 45.2264 +        x_result_sel_add_x <= `FALSE;
 45.2265 +        m_result_sel_compare_x <= `FALSE;
 45.2266 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
 45.2267 +        m_result_sel_shift_x <= `FALSE;
 45.2268 +`endif    
 45.2269 +        w_result_sel_load_x <= `FALSE;
 45.2270 +`ifdef CFG_PL_MULTIPLY_ENABLED
 45.2271 +        w_result_sel_mul_x <= `FALSE;
 45.2272 +`endif
 45.2273 +        x_bypass_enable_x <= `FALSE;
 45.2274 +        m_bypass_enable_x <= `FALSE;
 45.2275 +        write_enable_x <= `FALSE;
 45.2276 +        write_idx_x <= {`LM32_REG_IDX_WIDTH{1'b0}};
 45.2277 +        csr_x <= {`LM32_CSR_WIDTH{1'b0}};
 45.2278 +        load_x <= `FALSE;
 45.2279 +        store_x <= `FALSE;
 45.2280 +        size_x <= {`LM32_SIZE_WIDTH{1'b0}};
 45.2281 +        sign_extend_x <= `FALSE;
 45.2282 +        adder_op_x <= `FALSE;
 45.2283 +        adder_op_x_n <= `FALSE;
 45.2284 +        logic_op_x <= 4'h0;
 45.2285 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
 45.2286 +        direction_x <= `FALSE;
 45.2287 +`endif
 45.2288 +`ifdef CFG_ROTATE_ENABLED
 45.2289 +        rotate_x <= `FALSE;
 45.2290 +
 45.2291 +`endif
 45.2292 +        branch_x <= `FALSE;
 45.2293 +        branch_predict_x <= `FALSE;
 45.2294 +        branch_predict_taken_x <= `FALSE;
 45.2295 +        condition_x <= `LM32_CONDITION_U1;
 45.2296 +`ifdef CFG_DEBUG_ENABLED
 45.2297 +        break_x <= `FALSE;
 45.2298 +`endif
 45.2299 +        scall_x <= `FALSE;
 45.2300 +        eret_x <= `FALSE;
 45.2301 +`ifdef CFG_DEBUG_ENABLED
 45.2302 +        bret_x <= `FALSE;
 45.2303 +`endif
 45.2304 +`ifdef CFG_BUS_ERRORS_ENABLED
 45.2305 +        bus_error_x <= `FALSE;
 45.2306 +        data_bus_error_exception_m <= `FALSE;
 45.2307 +`endif
 45.2308 +        csr_write_enable_x <= `FALSE;
 45.2309 +        operand_m <= {`LM32_WORD_WIDTH{1'b0}};
 45.2310 +        branch_target_m <= {`LM32_PC_WIDTH{1'b0}};
 45.2311 +        m_result_sel_compare_m <= `FALSE;
 45.2312 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
 45.2313 +        m_result_sel_shift_m <= `FALSE;
 45.2314 +`endif    
 45.2315 +        w_result_sel_load_m <= `FALSE;
 45.2316 +`ifdef CFG_PL_MULTIPLY_ENABLED
 45.2317 +        w_result_sel_mul_m <= `FALSE;
 45.2318 +`endif
 45.2319 +        m_bypass_enable_m <= `FALSE;
 45.2320 +        branch_m <= `FALSE;
 45.2321 +        branch_predict_m <= `FALSE;
 45.2322 +	branch_predict_taken_m <= `FALSE;
 45.2323 +        exception_m <= `FALSE;
 45.2324 +        load_m <= `FALSE;
 45.2325 +        store_m <= `FALSE;
 45.2326 +        write_enable_m <= `FALSE;            
 45.2327 +        write_idx_m <= {`LM32_REG_IDX_WIDTH{1'b0}};
 45.2328 +        condition_met_m <= `FALSE;
 45.2329 +`ifdef CFG_DCACHE_ENABLED
 45.2330 +        dflush_m <= `FALSE;
 45.2331 +`endif
 45.2332 +`ifdef CFG_DEBUG_ENABLED
 45.2333 +        debug_exception_m <= `FALSE;
 45.2334 +        non_debug_exception_m <= `FALSE;        
 45.2335 +`endif
 45.2336 +        operand_w <= {`LM32_WORD_WIDTH{1'b0}};        
 45.2337 +        w_result_sel_load_w <= `FALSE;
 45.2338 +`ifdef CFG_PL_MULTIPLY_ENABLED
 45.2339 +        w_result_sel_mul_w <= `FALSE;
 45.2340 +`endif
 45.2341 +        write_idx_w <= {`LM32_REG_IDX_WIDTH{1'b0}};        
 45.2342 +        write_enable_w <= `FALSE;
 45.2343 +`ifdef CFG_DEBUG_ENABLED
 45.2344 +        debug_exception_w <= `FALSE;
 45.2345 +        non_debug_exception_w <= `FALSE;        
 45.2346 +`else
 45.2347 +        exception_w <= `FALSE;
 45.2348 +`endif
 45.2349 +`ifdef CFG_BUS_ERRORS_ENABLED
 45.2350 +        memop_pc_w <= {`LM32_PC_WIDTH{1'b0}};
 45.2351 +`endif
 45.2352 +    end
 45.2353 +    else
 45.2354 +    begin
 45.2355 +        // D/X stage registers
 45.2356 +       
 45.2357 +        if (stall_x == `FALSE)
 45.2358 +        begin
 45.2359 +`ifdef CFG_USER_ENABLED
 45.2360 +            user_opcode <= user_opcode_d;       
 45.2361 +`endif        
 45.2362 +            operand_0_x <= d_result_0;
 45.2363 +            operand_1_x <= d_result_1;
 45.2364 +            store_operand_x <= bypass_data_1;
 45.2365 +            branch_target_x <= branch_reg_d == `TRUE ? bypass_data_0[`LM32_PC_RNG] : branch_target_d;            
 45.2366 +            x_result_sel_csr_x <= x_result_sel_csr_d;
 45.2367 +`ifdef LM32_MC_ARITHMETIC_ENABLED
 45.2368 +            x_result_sel_mc_arith_x <= x_result_sel_mc_arith_d;
 45.2369 +`endif
 45.2370 +`ifdef LM32_NO_BARREL_SHIFT    
 45.2371 +            x_result_sel_shift_x <= x_result_sel_shift_d;
 45.2372 +`endif
 45.2373 +`ifdef CFG_SIGN_EXTEND_ENABLED
 45.2374 +            x_result_sel_sext_x <= x_result_sel_sext_d;
 45.2375 +`endif    
 45.2376 +	    x_result_sel_logic_x <= x_result_sel_logic_d;
 45.2377 +`ifdef CFG_USER_ENABLED
 45.2378 +            x_result_sel_user_x <= x_result_sel_user_d;
 45.2379 +`endif
 45.2380 +            x_result_sel_add_x <= x_result_sel_add_d;
 45.2381 +            m_result_sel_compare_x <= m_result_sel_compare_d;
 45.2382 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
 45.2383 +            m_result_sel_shift_x <= m_result_sel_shift_d;
 45.2384 +`endif    
 45.2385 +            w_result_sel_load_x <= w_result_sel_load_d;
 45.2386 +`ifdef CFG_PL_MULTIPLY_ENABLED
 45.2387 +            w_result_sel_mul_x <= w_result_sel_mul_d;
 45.2388 +`endif
 45.2389 +            x_bypass_enable_x <= x_bypass_enable_d;
 45.2390 +            m_bypass_enable_x <= m_bypass_enable_d;
 45.2391 +            load_x <= load_d;
 45.2392 +            store_x <= store_d;
 45.2393 +            branch_x <= branch_d;
 45.2394 +	    branch_predict_x <= branch_predict_d;
 45.2395 +	    branch_predict_taken_x <= branch_predict_taken_d;
 45.2396 +	    write_idx_x <= write_idx_d;
 45.2397 +            csr_x <= csr_d;
 45.2398 +            size_x <= size_d;
 45.2399 +            sign_extend_x <= sign_extend_d;
 45.2400 +            adder_op_x <= adder_op_d;
 45.2401 +            adder_op_x_n <= ~adder_op_d;
 45.2402 +            logic_op_x <= logic_op_d;
 45.2403 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
 45.2404 +            direction_x <= direction_d;
 45.2405 +`endif
 45.2406 +`ifdef CFG_ROTATE_ENABLED
 45.2407 +            rotate_x <= rotate_d;
 45.2408 +`endif
 45.2409 +            condition_x <= condition_d;
 45.2410 +            csr_write_enable_x <= csr_write_enable_d;
 45.2411 +`ifdef CFG_DEBUG_ENABLED
 45.2412 +            break_x <= break_d;
 45.2413 +`endif
 45.2414 +            scall_x <= scall_d;
 45.2415 +`ifdef CFG_BUS_ERRORS_ENABLED
 45.2416 +            bus_error_x <= bus_error_d;
 45.2417 +`endif
 45.2418 +            eret_x <= eret_d;
 45.2419 +`ifdef CFG_DEBUG_ENABLED
 45.2420 +            bret_x <= bret_d; 
 45.2421 +`endif
 45.2422 +            write_enable_x <= write_enable_d;
 45.2423 +        end
 45.2424 +        
 45.2425 +        // X/M stage registers
 45.2426 +
 45.2427 +        if (stall_m == `FALSE)
 45.2428 +        begin
 45.2429 +            operand_m <= x_result;
 45.2430 +            m_result_sel_compare_m <= m_result_sel_compare_x;
 45.2431 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
 45.2432 +            m_result_sel_shift_m <= m_result_sel_shift_x;
 45.2433 +`endif    
 45.2434 +            if (exception_x == `TRUE)
 45.2435 +            begin
 45.2436 +                w_result_sel_load_m <= `FALSE;
 45.2437 +`ifdef CFG_PL_MULTIPLY_ENABLED
 45.2438 +                w_result_sel_mul_m <= `FALSE;
 45.2439 +`endif
 45.2440 +            end
 45.2441 +            else
 45.2442 +            begin
 45.2443 +                w_result_sel_load_m <= w_result_sel_load_x;
 45.2444 +`ifdef CFG_PL_MULTIPLY_ENABLED
 45.2445 +                w_result_sel_mul_m <= w_result_sel_mul_x;
 45.2446 +`endif
 45.2447 +            end
 45.2448 +            m_bypass_enable_m <= m_bypass_enable_x;
 45.2449 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
 45.2450 +`endif
 45.2451 +            load_m <= load_x;
 45.2452 +            store_m <= store_x;
 45.2453 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
 45.2454 +            branch_m <= branch_x && !branch_taken_x;
 45.2455 +`else
 45.2456 +            branch_m <= branch_x;
 45.2457 +	    branch_predict_m <= branch_predict_x;
 45.2458 +	    branch_predict_taken_m <= branch_predict_taken_x;
 45.2459 +`endif
 45.2460 +`ifdef CFG_DEBUG_ENABLED
 45.2461 +	   // Data bus errors are generated by the wishbone and are
 45.2462 +	   // made known to the processor only in next cycle (as a
 45.2463 +	   // non-debug exception). A break instruction can be seen
 45.2464 +	   // in same cycle (causing a debug exception). Handle non
 45.2465 +	   // -debug exception first!
 45.2466 +            if (non_debug_exception_x == `TRUE) 
 45.2467 +                write_idx_m <= `LM32_EA_REG;
 45.2468 +            else if (debug_exception_x == `TRUE)
 45.2469 +                write_idx_m <= `LM32_BA_REG;
 45.2470 +            else 
 45.2471 +                write_idx_m <= write_idx_x;
 45.2472 +`else
 45.2473 +            if (exception_x == `TRUE)
 45.2474 +                write_idx_m <= `LM32_EA_REG;
 45.2475 +            else 
 45.2476 +                write_idx_m <= write_idx_x;
 45.2477 +`endif
 45.2478 +            condition_met_m <= condition_met_x;
 45.2479 +`ifdef CFG_DEBUG_ENABLED
 45.2480 +	   if (exception_x == `TRUE)
 45.2481 +	     if ((dc_re == `TRUE)
 45.2482 +		 || ((debug_exception_x == `TRUE) 
 45.2483 +		     && (non_debug_exception_x == `FALSE)))
 45.2484 +	       branch_target_m <= {deba, eid_x, {3{1'b0}}};
 45.2485 +	     else
 45.2486 +	       branch_target_m <= {eba, eid_x, {3{1'b0}}};
 45.2487 +	   else
 45.2488 +	     branch_target_m <= branch_target_x;
 45.2489 +`else
 45.2490 +            branch_target_m <= exception_x == `TRUE ? {eba, eid_x, {3{1'b0}}} : branch_target_x;
 45.2491 +`endif
 45.2492 +`ifdef CFG_TRACE_ENABLED
 45.2493 +            eid_m <= eid_x;
 45.2494 +`endif
 45.2495 +`ifdef CFG_DCACHE_ENABLED
 45.2496 +            dflush_m <= dflush_x;
 45.2497 +`endif
 45.2498 +            eret_m <= eret_q_x;
 45.2499 +`ifdef CFG_DEBUG_ENABLED
 45.2500 +            bret_m <= bret_q_x; 
 45.2501 +`endif
 45.2502 +            write_enable_m <= exception_x == `TRUE ? `TRUE : write_enable_x;            
 45.2503 +`ifdef CFG_DEBUG_ENABLED
 45.2504 +            debug_exception_m <= debug_exception_x;
 45.2505 +            non_debug_exception_m <= non_debug_exception_x;        
 45.2506 +`endif
 45.2507 +        end
 45.2508 +        
 45.2509 +        // State changing regs
 45.2510 +        if (stall_m == `FALSE)
 45.2511 +        begin
 45.2512 +            if ((exception_x == `TRUE) && (q_x == `TRUE) && (stall_x == `FALSE))
 45.2513 +                exception_m <= `TRUE;
 45.2514 +            else 
 45.2515 +                exception_m <= `FALSE;
 45.2516 +`ifdef CFG_BUS_ERRORS_ENABLED
 45.2517 +	   data_bus_error_exception_m <=    (data_bus_error_exception == `TRUE) 
 45.2518 +`ifdef CFG_DEBUG_ENABLED
 45.2519 +					 && (reset_exception == `FALSE)
 45.2520 +`endif
 45.2521 +					 ;
 45.2522 +`endif
 45.2523 +	end
 45.2524 +                
 45.2525 +        // M/W stage registers
 45.2526 +`ifdef CFG_BUS_ERRORS_ENABLED
 45.2527 +        operand_w <= exception_m == `TRUE ? (data_bus_error_exception_m ? {memop_pc_w, 2'b00} : {pc_m, 2'b00}) : m_result;
 45.2528 +`else
 45.2529 +        operand_w <= exception_m == `TRUE ? {pc_m, 2'b00} : m_result;
 45.2530 +`endif
 45.2531 +        w_result_sel_load_w <= w_result_sel_load_m;
 45.2532 +`ifdef CFG_PL_MULTIPLY_ENABLED
 45.2533 +        w_result_sel_mul_w <= w_result_sel_mul_m;
 45.2534 +`endif
 45.2535 +        write_idx_w <= write_idx_m;
 45.2536 +`ifdef CFG_TRACE_ENABLED
 45.2537 +        eid_w <= eid_m;
 45.2538 +        eret_w <= eret_m;
 45.2539 +`ifdef CFG_DEBUG_ENABLED
 45.2540 +        bret_w <= bret_m; 
 45.2541 +`endif
 45.2542 +`endif
 45.2543 +        write_enable_w <= write_enable_m;
 45.2544 +`ifdef CFG_DEBUG_ENABLED
 45.2545 +        debug_exception_w <= debug_exception_m;
 45.2546 +        non_debug_exception_w <= non_debug_exception_m;
 45.2547 +`else
 45.2548 +        exception_w <= exception_m;
 45.2549 +`endif
 45.2550 +`ifdef CFG_BUS_ERRORS_ENABLED
 45.2551 +        if (   (stall_m == `FALSE)
 45.2552 +            && (   (load_q_m == `TRUE) 
 45.2553 +                || (store_q_m == `TRUE)
 45.2554 +               )
 45.2555 +	   )
 45.2556 +          memop_pc_w <= pc_m;
 45.2557 +`endif
 45.2558 +    end
 45.2559 +end
 45.2560 +
 45.2561 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
 45.2562 +// Buffer data read from register file, in case a stall occurs, and watch for
 45.2563 +// any writes to the modified registers
 45.2564 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
 45.2565 +begin
 45.2566 +    if (rst_i == `TRUE)
 45.2567 +    begin
 45.2568 +        use_buf <= `FALSE;
 45.2569 +        reg_data_buf_0 <= {`LM32_WORD_WIDTH{1'b0}};
 45.2570 +        reg_data_buf_1 <= {`LM32_WORD_WIDTH{1'b0}};
 45.2571 +    end
 45.2572 +    else
 45.2573 +    begin
 45.2574 +        if (stall_d == `FALSE)
 45.2575 +            use_buf <= `FALSE;
 45.2576 +        else if (use_buf == `FALSE)
 45.2577 +        begin        
 45.2578 +            reg_data_buf_0 <= reg_data_live_0;
 45.2579 +            reg_data_buf_1 <= reg_data_live_1;
 45.2580 +            use_buf <= `TRUE;
 45.2581 +        end        
 45.2582 +        if (reg_write_enable_q_w == `TRUE)
 45.2583 +        begin
 45.2584 +            if (write_idx_w == read_idx_0_d)
 45.2585 +                reg_data_buf_0 <= w_result;
 45.2586 +            if (write_idx_w == read_idx_1_d)
 45.2587 +                reg_data_buf_1 <= w_result;
 45.2588 +        end
 45.2589 +    end
 45.2590 +end
 45.2591 +`endif
 45.2592 +
 45.2593 +`ifdef LM32_EBR_REGISTER_FILE
 45.2594 +`else
 45.2595 +// Register file write port
 45.2596 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
 45.2597 +begin
 45.2598 +    if (rst_i == `TRUE) begin
 45.2599 +        registers[0] <= {`LM32_WORD_WIDTH{1'b0}};
 45.2600 +        registers[1] <= {`LM32_WORD_WIDTH{1'b0}};
 45.2601 +        registers[2] <= {`LM32_WORD_WIDTH{1'b0}};
 45.2602 +        registers[3] <= {`LM32_WORD_WIDTH{1'b0}};
 45.2603 +        registers[4] <= {`LM32_WORD_WIDTH{1'b0}};
 45.2604 +        registers[5] <= {`LM32_WORD_WIDTH{1'b0}};
 45.2605 +        registers[6] <= {`LM32_WORD_WIDTH{1'b0}};
 45.2606 +        registers[7] <= {`LM32_WORD_WIDTH{1'b0}};
 45.2607 +        registers[8] <= {`LM32_WORD_WIDTH{1'b0}};
 45.2608 +        registers[9] <= {`LM32_WORD_WIDTH{1'b0}};
 45.2609 +        registers[10] <= {`LM32_WORD_WIDTH{1'b0}};
 45.2610 +        registers[11] <= {`LM32_WORD_WIDTH{1'b0}};
 45.2611 +        registers[12] <= {`LM32_WORD_WIDTH{1'b0}};
 45.2612 +        registers[13] <= {`LM32_WORD_WIDTH{1'b0}};
 45.2613 +        registers[14] <= {`LM32_WORD_WIDTH{1'b0}};
 45.2614 +        registers[15] <= {`LM32_WORD_WIDTH{1'b0}};
 45.2615 +        registers[16] <= {`LM32_WORD_WIDTH{1'b0}};
 45.2616 +        registers[17] <= {`LM32_WORD_WIDTH{1'b0}};
 45.2617 +        registers[18] <= {`LM32_WORD_WIDTH{1'b0}};
 45.2618 +        registers[19] <= {`LM32_WORD_WIDTH{1'b0}};
 45.2619 +        registers[20] <= {`LM32_WORD_WIDTH{1'b0}};
 45.2620 +        registers[21] <= {`LM32_WORD_WIDTH{1'b0}};
 45.2621 +        registers[22] <= {`LM32_WORD_WIDTH{1'b0}};
 45.2622 +        registers[23] <= {`LM32_WORD_WIDTH{1'b0}};
 45.2623 +        registers[24] <= {`LM32_WORD_WIDTH{1'b0}};
 45.2624 +        registers[25] <= {`LM32_WORD_WIDTH{1'b0}};
 45.2625 +        registers[26] <= {`LM32_WORD_WIDTH{1'b0}};
 45.2626 +        registers[27] <= {`LM32_WORD_WIDTH{1'b0}};
 45.2627 +        registers[28] <= {`LM32_WORD_WIDTH{1'b0}};
 45.2628 +        registers[29] <= {`LM32_WORD_WIDTH{1'b0}};
 45.2629 +        registers[30] <= {`LM32_WORD_WIDTH{1'b0}};
 45.2630 +        registers[31] <= {`LM32_WORD_WIDTH{1'b0}}; 
 45.2631 +        end
 45.2632 +    else begin
 45.2633 +        if (reg_write_enable_q_w == `TRUE)
 45.2634 +          registers[write_idx_w] <= w_result;
 45.2635 +        end
 45.2636 +end
 45.2637 +`endif
 45.2638 +
 45.2639 +`ifdef CFG_TRACE_ENABLED
 45.2640 +// PC tracing logic
 45.2641 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
 45.2642 +begin
 45.2643 +    if (rst_i == `TRUE)
 45.2644 +    begin
 45.2645 +        trace_pc_valid <= `FALSE;
 45.2646 +        trace_pc <= {`LM32_PC_WIDTH{1'b0}};
 45.2647 +        trace_exception <= `FALSE;
 45.2648 +        trace_eid <= `LM32_EID_RESET;
 45.2649 +        trace_eret <= `FALSE;
 45.2650 +`ifdef CFG_DEBUG_ENABLED
 45.2651 +        trace_bret <= `FALSE;
 45.2652 +`endif
 45.2653 +        pc_c <= `CFG_EBA_RESET/4;
 45.2654 +    end
 45.2655 +    else
 45.2656 +    begin
 45.2657 +        trace_pc_valid <= `FALSE;
 45.2658 +        // Has an exception occured
 45.2659 +`ifdef CFG_DEBUG_ENABLED
 45.2660 +        if ((debug_exception_q_w == `TRUE) || (non_debug_exception_q_w == `TRUE))
 45.2661 +`else
 45.2662 +        if (exception_q_w == `TRUE)
 45.2663 +`endif
 45.2664 +        begin        
 45.2665 +            trace_exception <= `TRUE;
 45.2666 +            trace_pc_valid <= `TRUE;
 45.2667 +            trace_pc <= pc_w;
 45.2668 +            trace_eid <= eid_w;
 45.2669 +        end
 45.2670 +        else
 45.2671 +            trace_exception <= `FALSE;
 45.2672 +        
 45.2673 +        if ((valid_w == `TRUE) && (!kill_w))
 45.2674 +        begin
 45.2675 +            // An instruction is commiting. Determine if it is non-sequential
 45.2676 +            if (pc_c + 1'b1 != pc_w)
 45.2677 +            begin
 45.2678 +                // Non-sequential instruction
 45.2679 +                trace_pc_valid <= `TRUE;
 45.2680 +                trace_pc <= pc_w;
 45.2681 +            end
 45.2682 +            // Record PC so we can determine if next instruction is sequential or not
 45.2683 +            pc_c <= pc_w;
 45.2684 +            // Indicate if it was an eret/bret instruction
 45.2685 +            trace_eret <= eret_w;
 45.2686 +`ifdef CFG_DEBUG_ENABLED
 45.2687 +            trace_bret <= bret_w;
 45.2688 +`endif
 45.2689 +        end
 45.2690 +        else
 45.2691 +        begin
 45.2692 +            trace_eret <= `FALSE;
 45.2693 +`ifdef CFG_DEBUG_ENABLED
 45.2694 +            trace_bret <= `FALSE;
 45.2695 +`endif
 45.2696 +        end
 45.2697 +    end
 45.2698 +end
 45.2699 +`endif
 45.2700 +      
 45.2701 +/////////////////////////////////////////////////////
 45.2702 +// Behavioural Logic
 45.2703 +/////////////////////////////////////////////////////
 45.2704 +
 45.2705 +// synthesis translate_off            
 45.2706 +
 45.2707 +// Reset register 0. Only needed for simulation. 
 45.2708 +initial
 45.2709 +begin
 45.2710 +`ifdef LM32_EBR_REGISTER_FILE
 45.2711 +    reg_0.mem[0] = {`LM32_WORD_WIDTH{1'b0}};
 45.2712 +    reg_1.mem[0] = {`LM32_WORD_WIDTH{1'b0}};
 45.2713 +`else
 45.2714 +    registers[0] = {`LM32_WORD_WIDTH{1'b0}};
 45.2715 +`endif
 45.2716 +end
 45.2717 +
 45.2718 +// synthesis translate_on
 45.2719 +        
 45.2720 +endmodule 

    46.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    46.2 +++ b/rtl/lm32_dcache.v	Tue Mar 08 09:40:42 2011 +0000
    46.3 @@ -0,0 +1,542 @@
    46.4 +// =============================================================================
    46.5 +//                           COPYRIGHT NOTICE
    46.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation
    46.7 +// ALL RIGHTS RESERVED
    46.8 +// This confidential and proprietary software may be used only as authorised by
    46.9 +// a licensing agreement from Lattice Semiconductor Corporation.
   46.10 +// The entire notice above must be reproduced on all authorized copies and
   46.11 +// copies may only be made to the extent permitted by a licensing agreement from
   46.12 +// Lattice Semiconductor Corporation.
   46.13 +//
   46.14 +// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
   46.15 +// 5555 NE Moore Court                            408-826-6000 (other locations)
   46.16 +// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
   46.17 +// U.S.A                                   email: techsupport@latticesemi.com
   46.18 +// =============================================================================/
   46.19 +//                         FILE DETAILS
   46.20 +// Project          : LatticeMico32
   46.21 +// File             : lm32_dcache.v
   46.22 +// Title            : Data cache
   46.23 +// Dependencies     : lm32_include.v
   46.24 +// Version          : 6.1.17
   46.25 +//                  : Initial Release
   46.26 +// Version          : 7.0SP2, 3.0
   46.27 +//                  : No Change
   46.28 +// Version	    : 3.1
   46.29 +//                  : Support for user-selected resource usage when implementing
   46.30 +//                  : cache memory. Additional parameters must be defined when
   46.31 +//                  : invoking lm32_ram.v
   46.32 +// =============================================================================
   46.33 +								 
   46.34 +`include "lm32_include.v"
   46.35 +
   46.36 +`ifdef CFG_DCACHE_ENABLED
   46.37 +
   46.38 +`define LM32_DC_ADDR_OFFSET_RNG          addr_offset_msb:addr_offset_lsb
   46.39 +`define LM32_DC_ADDR_SET_RNG             addr_set_msb:addr_set_lsb
   46.40 +`define LM32_DC_ADDR_TAG_RNG             addr_tag_msb:addr_tag_lsb
   46.41 +`define LM32_DC_ADDR_IDX_RNG             addr_set_msb:addr_offset_lsb
   46.42 +
   46.43 +`define LM32_DC_TMEM_ADDR_WIDTH          addr_set_width
   46.44 +`define LM32_DC_TMEM_ADDR_RNG            (`LM32_DC_TMEM_ADDR_WIDTH-1):0
   46.45 +`define LM32_DC_DMEM_ADDR_WIDTH          (addr_offset_width+addr_set_width)
   46.46 +`define LM32_DC_DMEM_ADDR_RNG            (`LM32_DC_DMEM_ADDR_WIDTH-1):0
   46.47 +
   46.48 +`define LM32_DC_TAGS_WIDTH               (addr_tag_width+1)
   46.49 +`define LM32_DC_TAGS_RNG                 (`LM32_DC_TAGS_WIDTH-1):0
   46.50 +`define LM32_DC_TAGS_TAG_RNG             (`LM32_DC_TAGS_WIDTH-1):1
   46.51 +`define LM32_DC_TAGS_VALID_RNG           0
   46.52 +
   46.53 +`define LM32_DC_STATE_RNG                2:0
   46.54 +`define LM32_DC_STATE_FLUSH              3'b001
   46.55 +`define LM32_DC_STATE_CHECK              3'b010
   46.56 +`define LM32_DC_STATE_REFILL             3'b100
   46.57 +
   46.58 +/////////////////////////////////////////////////////
   46.59 +// Module interface
   46.60 +/////////////////////////////////////////////////////
   46.61 +
   46.62 +module lm32_dcache ( 
   46.63 +    // ----- Inputs -----
   46.64 +    clk_i,
   46.65 +    rst_i,    
   46.66 +    stall_a,
   46.67 +    stall_x,
   46.68 +    stall_m,
   46.69 +    address_x,
   46.70 +    address_m,
   46.71 +    load_q_m,
   46.72 +    store_q_m,
   46.73 +    store_data,
   46.74 +    store_byte_select,
   46.75 +    refill_ready,
   46.76 +    refill_data,
   46.77 +    dflush,
   46.78 +    // ----- Outputs -----
   46.79 +    stall_request,
   46.80 +    restart_request,
   46.81 +    refill_request,
   46.82 +    refill_address,
   46.83 +    refilling,
   46.84 +    load_data
   46.85 +    );
   46.86 +
   46.87 +/////////////////////////////////////////////////////
   46.88 +// Parameters
   46.89 +/////////////////////////////////////////////////////
   46.90 +
   46.91 +parameter associativity = 1;                            // Associativity of the cache (Number of ways)
   46.92 +parameter sets = 512;                                   // Number of sets
   46.93 +parameter bytes_per_line = 16;                          // Number of bytes per cache line
   46.94 +parameter base_address = 0;                             // Base address of cachable memory
   46.95 +parameter limit = 0;                                    // Limit (highest address) of cachable memory
   46.96 +
   46.97 +localparam addr_offset_width = clogb2(bytes_per_line)-1-2;
   46.98 +localparam addr_set_width = clogb2(sets)-1;
   46.99 +localparam addr_offset_lsb = 2;
  46.100 +localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
  46.101 +localparam addr_set_lsb = (addr_offset_msb+1);
  46.102 +localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
  46.103 +localparam addr_tag_lsb = (addr_set_msb+1);
  46.104 +localparam addr_tag_msb = clogb2(`CFG_DCACHE_LIMIT-`CFG_DCACHE_BASE_ADDRESS)-1;
  46.105 +localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);
  46.106 +
  46.107 +/////////////////////////////////////////////////////
  46.108 +// Inputs
  46.109 +/////////////////////////////////////////////////////
  46.110 +
  46.111 +input clk_i;                                            // Clock
  46.112 +input rst_i;                                            // Reset
  46.113 +
  46.114 +input stall_a;                                          // Stall A stage
  46.115 +input stall_x;                                          // Stall X stage
  46.116 +input stall_m;                                          // Stall M stage
  46.117 +
  46.118 +input [`LM32_WORD_RNG] address_x;                       // X stage load/store address
  46.119 +input [`LM32_WORD_RNG] address_m;                       // M stage load/store address
  46.120 +input load_q_m;                                         // Load instruction in M stage
  46.121 +input store_q_m;                                        // Store instruction in M stage
  46.122 +input [`LM32_WORD_RNG] store_data;                      // Data to store
  46.123 +input [`LM32_BYTE_SELECT_RNG] store_byte_select;        // Which bytes in store data should be modified
  46.124 +
  46.125 +input refill_ready;                                     // Indicates next word of refill data is ready
  46.126 +input [`LM32_WORD_RNG] refill_data;                     // Refill data
  46.127 +
  46.128 +input dflush;                                           // Indicates cache should be flushed
  46.129 +
  46.130 +/////////////////////////////////////////////////////
  46.131 +// Outputs
  46.132 +/////////////////////////////////////////////////////
  46.133 +
  46.134 +output stall_request;                                   // Request pipeline be stalled because cache is busy
  46.135 +wire   stall_request;
  46.136 +output restart_request;                                 // Request to restart instruction that caused the cache miss
  46.137 +reg    restart_request;
  46.138 +output refill_request;                                  // Request a refill 
  46.139 +reg    refill_request;
  46.140 +output [`LM32_WORD_RNG] refill_address;                 // Address to refill from
  46.141 +reg    [`LM32_WORD_RNG] refill_address;
  46.142 +output refilling;                                       // Indicates if the cache is currently refilling
  46.143 +reg    refilling;
  46.144 +output [`LM32_WORD_RNG] load_data;                      // Data read from cache
  46.145 +wire   [`LM32_WORD_RNG] load_data;
  46.146 +
  46.147 +/////////////////////////////////////////////////////
  46.148 +// Internal nets and registers 
  46.149 +/////////////////////////////////////////////////////
  46.150 +
  46.151 +wire read_port_enable;                                  // Cache memory read port clock enable
  46.152 +wire write_port_enable;                                 // Cache memory write port clock enable
  46.153 +wire [0:associativity-1] way_tmem_we;                   // Tag memory write enable
  46.154 +wire [0:associativity-1] way_dmem_we;                   // Data memory write enable
  46.155 +wire [`LM32_WORD_RNG] way_data[0:associativity-1];      // Data read from data memory
  46.156 +wire [`LM32_DC_TAGS_TAG_RNG] way_tag[0:associativity-1];// Tag read from tag memory
  46.157 +wire [0:associativity-1] way_valid;                     // Indicates which ways are valid
  46.158 +wire [0:associativity-1] way_match;                     // Indicates which ways matched
  46.159 +wire miss;                                              // Indicates no ways matched
  46.160 +
  46.161 +wire [`LM32_DC_TMEM_ADDR_RNG] tmem_read_address;        // Tag memory read address
  46.162 +wire [`LM32_DC_TMEM_ADDR_RNG] tmem_write_address;       // Tag memory write address
  46.163 +wire [`LM32_DC_DMEM_ADDR_RNG] dmem_read_address;        // Data memory read address
  46.164 +wire [`LM32_DC_DMEM_ADDR_RNG] dmem_write_address;       // Data memory write address
  46.165 +wire [`LM32_DC_TAGS_RNG] tmem_write_data;               // Tag memory write data        
  46.166 +reg [`LM32_WORD_RNG] dmem_write_data;                   // Data memory write data
  46.167 +
  46.168 +reg [`LM32_DC_STATE_RNG] state;                         // Current state of FSM
  46.169 +wire flushing;                                          // Indicates if cache is currently flushing
  46.170 +wire check;                                             // Indicates if cache is currently checking for hits/misses
  46.171 +wire refill;                                            // Indicates if cache is currently refilling
  46.172 +
  46.173 +wire valid_store;                                       // Indicates if there is a valid store instruction
  46.174 +reg [associativity-1:0] refill_way_select;              // Which way should be refilled
  46.175 +reg [`LM32_DC_ADDR_OFFSET_RNG] refill_offset;           // Which word in cache line should be refilled
  46.176 +wire last_refill;                                       // Indicates when on last cycle of cache refill
  46.177 +reg [`LM32_DC_TMEM_ADDR_RNG] flush_set;                 // Which set is currently being flushed
  46.178 +
  46.179 +genvar i, j;
  46.180 +
  46.181 +/////////////////////////////////////////////////////
  46.182 +// Functions
  46.183 +/////////////////////////////////////////////////////
  46.184 +
  46.185 +`include "lm32_functions.v"
  46.186 +
  46.187 +/////////////////////////////////////////////////////
  46.188 +// Instantiations
  46.189 +/////////////////////////////////////////////////////
  46.190 +
  46.191 +   generate
  46.192 +      for (i = 0; i < associativity; i = i + 1)    
  46.193 +	begin : memories
  46.194 +	   // Way data
  46.195 +           if (`LM32_DC_DMEM_ADDR_WIDTH < 11)
  46.196 +             begin : data_memories
  46.197 +		lm32_ram 
  46.198 +		  #(
  46.199 +		    // ----- Parameters -------
  46.200 +		    .data_width (32),
  46.201 +		    .address_width (`LM32_DC_DMEM_ADDR_WIDTH)
  46.202 +`ifdef PLATFORM_LATTICE
  46.203 +			,
  46.204 + `ifdef CFG_DCACHE_DAT_USE_DP_TRUE
  46.205 +		    .RAM_IMPLEMENTATION ("EBR"),
  46.206 +		    .RAM_TYPE ("RAM_DP_TRUE")
  46.207 + `else
  46.208 +  `ifdef CFG_DCACHE_DAT_USE_SLICE
  46.209 +		    .RAM_IMPLEMENTATION ("SLICE")
  46.210 +  `else
  46.211 +		    .RAM_IMPLEMENTATION ("AUTO")
  46.212 +  `endif
  46.213 + `endif
  46.214 +`endif
  46.215 +		    ) way_0_data_ram 
  46.216 +		    (
  46.217 +		     // ----- Inputs -------
  46.218 +		     .read_clk (clk_i),
  46.219 +		     .write_clk (clk_i),
  46.220 +		     .reset (rst_i),
  46.221 +		     .read_address (dmem_read_address),
  46.222 +		     .enable_read (read_port_enable),
  46.223 +		     .write_address (dmem_write_address),
  46.224 +		     .enable_write (write_port_enable),
  46.225 +		     .write_enable (way_dmem_we[i]),
  46.226 +		     .write_data (dmem_write_data),    
  46.227 +		     // ----- Outputs -------
  46.228 +		     .read_data (way_data[i])
  46.229 +		     );    
  46.230 +             end
  46.231 +           else
  46.232 +             begin
  46.233 +		for (j = 0; j < 4; j = j + 1)    
  46.234 +		  begin : byte_memories
  46.235 +		     lm32_ram 
  46.236 +		       #(
  46.237 +			 // ----- Parameters -------
  46.238 +			 .data_width (8),
  46.239 +			 .address_width (`LM32_DC_DMEM_ADDR_WIDTH)
  46.240 +`ifdef PLATFORM_LATTICE
  46.241 +			 ,
  46.242 + `ifdef CFG_DCACHE_DAT_USE_DP_TRUE
  46.243 +			 .RAM_IMPLEMENTATION ("EBR"),
  46.244 +			 .RAM_TYPE ("RAM_DP_TRUE")
  46.245 + `else
  46.246 +  `ifdef CFG_DCACHE_DAT_USE_SLICE
  46.247 +			 .RAM_IMPLEMENTATION ("SLICE")
  46.248 +  `else
  46.249 +			 .RAM_IMPLEMENTATION ("AUTO")
  46.250 +  `endif
  46.251 + `endif
  46.252 +`endif
  46.253 +			 ) way_0_data_ram 
  46.254 +			 (
  46.255 +			  // ----- Inputs -------
  46.256 +			  .read_clk (clk_i),
  46.257 +			  .write_clk (clk_i),
  46.258 +			  .reset (rst_i),
  46.259 +			  .read_address (dmem_read_address),
  46.260 +			  .enable_read (read_port_enable),
  46.261 +			  .write_address (dmem_write_address),
  46.262 +			  .enable_write (write_port_enable),
  46.263 +			  .write_enable (way_dmem_we[i] & (store_byte_select[j] | refill)),
  46.264 +			  .write_data (dmem_write_data[(j+1)*8-1:j*8]),    
  46.265 +			  // ----- Outputs -------
  46.266 +			  .read_data (way_data[i][(j+1)*8-1:j*8])
  46.267 +			  );
  46.268 +		  end
  46.269 +             end
  46.270 +	   
  46.271 +	   // Way tags
  46.272 +	   lm32_ram 
  46.273 +	     #(
  46.274 +	       // ----- Parameters -------
  46.275 +	       .data_width (`LM32_DC_TAGS_WIDTH),
  46.276 +	       .address_width (`LM32_DC_TMEM_ADDR_WIDTH)
  46.277 +`ifdef PLATFORM_LATTICE
  46.278 +			 ,
  46.279 + `ifdef CFG_DCACHE_DAT_USE_DP_TRUE
  46.280 +	       .RAM_IMPLEMENTATION ("EBR"),
  46.281 +	       .RAM_TYPE ("RAM_DP_TRUE")
  46.282 + `else
  46.283 +  `ifdef CFG_DCACHE_DAT_USE_SLICE
  46.284 +	       .RAM_IMPLEMENTATION ("SLICE")
  46.285 +  `else
  46.286 +	       .RAM_IMPLEMENTATION ("AUTO")
  46.287 +  `endif
  46.288 + `endif
  46.289 +`endif
  46.290 +	       ) way_0_tag_ram 
  46.291 +	       (
  46.292 +		// ----- Inputs -------
  46.293 +		.read_clk (clk_i),
  46.294 +		.write_clk (clk_i),
  46.295 +		.reset (rst_i),
  46.296 +		.read_address (tmem_read_address),
  46.297 +		.enable_read (read_port_enable),
  46.298 +		.write_address (tmem_write_address),
  46.299 +		.enable_write (`TRUE),
  46.300 +		.write_enable (way_tmem_we[i]),
  46.301 +		.write_data (tmem_write_data),
  46.302 +		// ----- Outputs -------
  46.303 +		.read_data ({way_tag[i], way_valid[i]})
  46.304 +		);
  46.305 +	end
  46.306 +      
  46.307 +   endgenerate
  46.308 +
  46.309 +/////////////////////////////////////////////////////
  46.310 +// Combinational logic
  46.311 +/////////////////////////////////////////////////////
  46.312 +
  46.313 +// Compute which ways in the cache match the address being read
  46.314 +generate
  46.315 +    for (i = 0; i < associativity; i = i + 1)
  46.316 +    begin : match
  46.317 +assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_m[`LM32_DC_ADDR_TAG_RNG], `TRUE});
  46.318 +    end
  46.319 +endgenerate
  46.320 +
  46.321 +// Select data from way that matched the address being read     
  46.322 +generate
  46.323 +    if (associativity == 1)    
  46.324 +	 begin : data_1
  46.325 +assign load_data = way_data[0];
  46.326 +    end
  46.327 +    else if (associativity == 2)
  46.328 +	 begin : data_2
  46.329 +assign load_data = way_match[0] ? way_data[0] : way_data[1]; 
  46.330 +    end
  46.331 +endgenerate
  46.332 +
  46.333 +generate
  46.334 +    if (`LM32_DC_DMEM_ADDR_WIDTH < 11)
  46.335 +    begin
  46.336 +// Select data to write to data memories
  46.337 +always @(*)
  46.338 +begin
  46.339 +    if (refill == `TRUE)
  46.340 +        dmem_write_data = refill_data;
  46.341 +    else
  46.342 +    begin
  46.343 +        dmem_write_data[`LM32_BYTE_0_RNG] = store_byte_select[0] ? store_data[`LM32_BYTE_0_RNG] : load_data[`LM32_BYTE_0_RNG];
  46.344 +        dmem_write_data[`LM32_BYTE_1_RNG] = store_byte_select[1] ? store_data[`LM32_BYTE_1_RNG] : load_data[`LM32_BYTE_1_RNG];
  46.345 +        dmem_write_data[`LM32_BYTE_2_RNG] = store_byte_select[2] ? store_data[`LM32_BYTE_2_RNG] : load_data[`LM32_BYTE_2_RNG];
  46.346 +        dmem_write_data[`LM32_BYTE_3_RNG] = store_byte_select[3] ? store_data[`LM32_BYTE_3_RNG] : load_data[`LM32_BYTE_3_RNG];
  46.347 +    end
  46.348 +end
  46.349 +    end
  46.350 +    else
  46.351 +    begin
  46.352 +// Select data to write to data memories - FIXME: Should use different write ports on dual port RAMs, but they don't work
  46.353 +always @(*)
  46.354 +begin
  46.355 +    if (refill == `TRUE)
  46.356 +        dmem_write_data = refill_data;
  46.357 +    else
  46.358 +        dmem_write_data = store_data;
  46.359 +end
  46.360 +    end
  46.361 +endgenerate
  46.362 +
  46.363 +// Compute address to use to index into the data memories
  46.364 +generate 
  46.365 +     if (bytes_per_line > 4)
  46.366 +assign dmem_write_address = (refill == `TRUE) 
  46.367 +                            ? {refill_address[`LM32_DC_ADDR_SET_RNG], refill_offset}
  46.368 +                            : address_m[`LM32_DC_ADDR_IDX_RNG];
  46.369 +    else
  46.370 +assign dmem_write_address = (refill == `TRUE) 
  46.371 +                            ? refill_address[`LM32_DC_ADDR_SET_RNG]
  46.372 +                            : address_m[`LM32_DC_ADDR_IDX_RNG];
  46.373 +endgenerate
  46.374 +assign dmem_read_address = address_x[`LM32_DC_ADDR_IDX_RNG];
  46.375 +// Compute address to use to index into the tag memories   
  46.376 +assign tmem_write_address = (flushing == `TRUE)
  46.377 +                            ? flush_set
  46.378 +                            : refill_address[`LM32_DC_ADDR_SET_RNG];
  46.379 +assign tmem_read_address = address_x[`LM32_DC_ADDR_SET_RNG];
  46.380 +
  46.381 +// Compute signal to indicate when we are on the last refill accesses
  46.382 +generate 
  46.383 +    if (bytes_per_line > 4)                            
  46.384 +assign last_refill = refill_offset == {addr_offset_width{1'b1}};
  46.385 +    else
  46.386 +assign last_refill = `TRUE;
  46.387 +endgenerate
  46.388 +
  46.389 +// Compute data and tag memory access enable
  46.390 +assign read_port_enable = (stall_x == `FALSE);
  46.391 +assign write_port_enable = (refill_ready == `TRUE) || !stall_m;
  46.392 +
  46.393 +// Determine when we have a valid store
  46.394 +assign valid_store = (store_q_m == `TRUE) && (check == `TRUE);
  46.395 +
  46.396 +// Compute data and tag memory write enables
  46.397 +generate
  46.398 +    if (associativity == 1) 
  46.399 +    begin : we_1     
  46.400 +assign way_dmem_we[0] = (refill_ready == `TRUE) || ((valid_store == `TRUE) && (way_match[0] == `TRUE));
  46.401 +assign way_tmem_we[0] = (refill_ready == `TRUE) || (flushing == `TRUE);
  46.402 +    end 
  46.403 +    else 
  46.404 +    begin : we_2
  46.405 +assign way_dmem_we[0] = ((refill_ready == `TRUE) && (refill_way_select[0] == `TRUE)) || ((valid_store == `TRUE) && (way_match[0] == `TRUE));
  46.406 +assign way_dmem_we[1] = ((refill_ready == `TRUE) && (refill_way_select[1] == `TRUE)) || ((valid_store == `TRUE) && (way_match[1] == `TRUE));
  46.407 +assign way_tmem_we[0] = ((refill_ready == `TRUE) && (refill_way_select[0] == `TRUE)) || (flushing == `TRUE);
  46.408 +assign way_tmem_we[1] = ((refill_ready == `TRUE) && (refill_way_select[1] == `TRUE)) || (flushing == `TRUE);
  46.409 +    end
  46.410 +endgenerate
  46.411 +
  46.412 +// On the last refill cycle set the valid bit, for all other writes it should be cleared
  46.413 +assign tmem_write_data[`LM32_DC_TAGS_VALID_RNG] = ((last_refill == `TRUE) || (valid_store == `TRUE)) && (flushing == `FALSE);
  46.414 +assign tmem_write_data[`LM32_DC_TAGS_TAG_RNG] = refill_address[`LM32_DC_ADDR_TAG_RNG];
  46.415 +
  46.416 +// Signals that indicate which state we are in
  46.417 +assign flushing = state[0];
  46.418 +assign check = state[1];
  46.419 +assign refill = state[2];
  46.420 +
  46.421 +assign miss = (~(|way_match)) && (load_q_m == `TRUE) && (stall_m == `FALSE);
  46.422 +assign stall_request = (check == `FALSE);
  46.423 +                      
  46.424 +/////////////////////////////////////////////////////
  46.425 +// Sequential logic
  46.426 +/////////////////////////////////////////////////////
  46.427 +
  46.428 +// Record way selected for replacement on a cache miss
  46.429 +generate
  46.430 +    if (associativity >= 2) 
  46.431 +    begin : way_select      
  46.432 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  46.433 +begin
  46.434 +    if (rst_i == `TRUE)
  46.435 +        refill_way_select <= {{associativity-1{1'b0}}, 1'b1};
  46.436 +    else
  46.437 +    begin        
  46.438 +        if (refill_request == `TRUE)
  46.439 +            refill_way_select <= {refill_way_select[0], refill_way_select[1]};
  46.440 +    end
  46.441 +end
  46.442 +    end 
  46.443 +endgenerate   
  46.444 +
  46.445 +// Record whether we are currently refilling
  46.446 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  46.447 +begin
  46.448 +    if (rst_i == `TRUE)
  46.449 +        refilling <= `FALSE;
  46.450 +    else 
  46.451 +        refilling <= refill;
  46.452 +end
  46.453 +
  46.454 +// Instruction cache control FSM
  46.455 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  46.456 +begin
  46.457 +    if (rst_i == `TRUE)
  46.458 +    begin
  46.459 +        state <= `LM32_DC_STATE_FLUSH;
  46.460 +        flush_set <= {`LM32_DC_TMEM_ADDR_WIDTH{1'b1}};
  46.461 +        refill_request <= `FALSE;
  46.462 +        refill_address <= {`LM32_WORD_WIDTH{1'bx}};
  46.463 +        restart_request <= `FALSE;
  46.464 +    end
  46.465 +    else 
  46.466 +    begin
  46.467 +        case (state)
  46.468 +
  46.469 +        // Flush the cache 
  46.470 +        `LM32_DC_STATE_FLUSH:
  46.471 +        begin
  46.472 +            if (flush_set == {`LM32_DC_TMEM_ADDR_WIDTH{1'b0}})
  46.473 +                state <= `LM32_DC_STATE_CHECK;
  46.474 +            flush_set <= flush_set - 1'b1;
  46.475 +        end
  46.476 +        
  46.477 +        // Check for cache misses
  46.478 +        `LM32_DC_STATE_CHECK:
  46.479 +        begin
  46.480 +            if (stall_a == `FALSE)
  46.481 +                restart_request <= `FALSE;
  46.482 +            if (miss == `TRUE)
  46.483 +            begin
  46.484 +                refill_request <= `TRUE;
  46.485 +                refill_address <= address_m;
  46.486 +                state <= `LM32_DC_STATE_REFILL;
  46.487 +            end
  46.488 +            else if (dflush == `TRUE)
  46.489 +                state <= `LM32_DC_STATE_FLUSH;
  46.490 +        end
  46.491 +
  46.492 +        // Refill a cache line
  46.493 +        `LM32_DC_STATE_REFILL:
  46.494 +        begin
  46.495 +            refill_request <= `FALSE;
  46.496 +            if (refill_ready == `TRUE)
  46.497 +            begin
  46.498 +                if (last_refill == `TRUE)
  46.499 +                begin
  46.500 +                    restart_request <= `TRUE;
  46.501 +                    state <= `LM32_DC_STATE_CHECK;
  46.502 +                end
  46.503 +            end
  46.504 +        end
  46.505 +        
  46.506 +        endcase        
  46.507 +    end
  46.508 +end
  46.509 +
  46.510 +generate
  46.511 +    if (bytes_per_line > 4)
  46.512 +    begin
  46.513 +// Refill offset
  46.514 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  46.515 +begin
  46.516 +    if (rst_i == `TRUE)
  46.517 +        refill_offset <= {addr_offset_width{1'b0}};
  46.518 +    else 
  46.519 +    begin
  46.520 +        case (state)
  46.521 +        
  46.522 +        // Check for cache misses
  46.523 +        `LM32_DC_STATE_CHECK:
  46.524 +        begin
  46.525 +            if (miss == `TRUE)
  46.526 +                refill_offset <= {addr_offset_width{1'b0}};
  46.527 +        end
  46.528 +
  46.529 +        // Refill a cache line
  46.530 +        `LM32_DC_STATE_REFILL:
  46.531 +        begin
  46.532 +            if (refill_ready == `TRUE)
  46.533 +                refill_offset <= refill_offset + 1'b1;
  46.534 +        end
  46.535 +        
  46.536 +        endcase        
  46.537 +    end
  46.538 +end
  46.539 +    end
  46.540 +endgenerate
  46.541 +
  46.542 +endmodule
  46.543 +
  46.544 +`endif
  46.545 +

    47.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    47.2 +++ b/rtl/lm32_debug.v	Tue Mar 08 09:40:42 2011 +0000
    47.3 @@ -0,0 +1,348 @@
    47.4 +// =============================================================================
    47.5 +//                           COPYRIGHT NOTICE
    47.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation
    47.7 +// ALL RIGHTS RESERVED
    47.8 +// This confidential and proprietary software may be used only as authorised by
    47.9 +// a licensing agreement from Lattice Semiconductor Corporation.
   47.10 +// The entire notice above must be reproduced on all authorized copies and
   47.11 +// copies may only be made to the extent permitted by a licensing agreement from
   47.12 +// Lattice Semiconductor Corporation.
   47.13 +//
   47.14 +// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
   47.15 +// 5555 NE Moore Court                            408-826-6000 (other locations)
   47.16 +// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
   47.17 +// U.S.A                                   email: techsupport@latticesemi.com
   47.18 +// =============================================================================/
   47.19 +//                         FILE DETAILS
   47.20 +// Project          : LatticeMico32
   47.21 +// File             : lm32_debug.v
   47.22 +// Title            : Hardware debug registers and associated logic.
   47.23 +// Dependencies     : lm32_include.v
   47.24 +// Version          : 6.1.17
   47.25 +//                  : Initial Release
   47.26 +// Version          : 7.0SP2, 3.0
   47.27 +//                  : No Change
   47.28 +// Version          : 3.1
   47.29 +//                  : No Change
   47.30 +// Version          : 3.2
   47.31 +//                  : Fixed simulation bug which flares up when number of 
   47.32 +//                  : watchpoints is zero.
   47.33 +// =============================================================================
   47.34 +
   47.35 +`include "lm32_include.v"
   47.36 +
   47.37 +`ifdef CFG_DEBUG_ENABLED
   47.38 +
   47.39 +// States for single-step FSM
   47.40 +`define LM32_DEBUG_SS_STATE_RNG                 2:0
   47.41 +`define LM32_DEBUG_SS_STATE_IDLE                3'b000
   47.42 +`define LM32_DEBUG_SS_STATE_WAIT_FOR_RET        3'b001
   47.43 +`define LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN    3'b010
   47.44 +`define LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT    3'b011
   47.45 +`define LM32_DEBUG_SS_STATE_RESTART             3'b100
   47.46 +
   47.47 +/////////////////////////////////////////////////////
   47.48 +// Module interface
   47.49 +/////////////////////////////////////////////////////
   47.50 +
   47.51 +module lm32_debug (
   47.52 +    // ----- Inputs -------
   47.53 +    clk_i, 
   47.54 +    rst_i,
   47.55 +    pc_x,
   47.56 +    load_x,
   47.57 +    store_x,
   47.58 +    load_store_address_x,
   47.59 +    csr_write_enable_x,
   47.60 +    csr_write_data,
   47.61 +    csr_x,
   47.62 +`ifdef CFG_HW_DEBUG_ENABLED
   47.63 +    jtag_csr_write_enable,
   47.64 +    jtag_csr_write_data,
   47.65 +    jtag_csr,
   47.66 +`endif
   47.67 +`ifdef LM32_SINGLE_STEP_ENABLED
   47.68 +    eret_q_x,
   47.69 +    bret_q_x,
   47.70 +    stall_x,
   47.71 +    exception_x,
   47.72 +    q_x,
   47.73 +`ifdef CFG_DCACHE_ENABLED
   47.74 +    dcache_refill_request,
   47.75 +`endif
   47.76 +`endif
   47.77 +    // ----- Outputs -------
   47.78 +`ifdef LM32_SINGLE_STEP_ENABLED
   47.79 +    dc_ss,
   47.80 +`endif
   47.81 +    dc_re,
   47.82 +    bp_match,
   47.83 +    wp_match
   47.84 +    );
   47.85 +    
   47.86 +/////////////////////////////////////////////////////
   47.87 +// Parameters
   47.88 +/////////////////////////////////////////////////////
   47.89 +
   47.90 +parameter breakpoints = 0;                      // Number of breakpoint CSRs
   47.91 +parameter watchpoints = 0;                      // Number of watchpoint CSRs
   47.92 +
   47.93 +/////////////////////////////////////////////////////
   47.94 +// Inputs
   47.95 +/////////////////////////////////////////////////////
   47.96 +
   47.97 +input clk_i;                                    // Clock
   47.98 +input rst_i;                                    // Reset
   47.99 +
  47.100 +input [`LM32_PC_RNG] pc_x;                      // X stage PC
  47.101 +input load_x;                                   // Load instruction in X stage
  47.102 +input store_x;                                  // Store instruction in X stage
  47.103 +input [`LM32_WORD_RNG] load_store_address_x;    // Load or store effective address
  47.104 +input csr_write_enable_x;                       // wcsr instruction in X stage
  47.105 +input [`LM32_WORD_RNG] csr_write_data;          // Data to write to CSR
  47.106 +input [`LM32_CSR_RNG] csr_x;                    // Which CSR to write
  47.107 +`ifdef CFG_HW_DEBUG_ENABLED
  47.108 +input jtag_csr_write_enable;                    // JTAG interface CSR write enable
  47.109 +input [`LM32_WORD_RNG] jtag_csr_write_data;     // Data to write to CSR
  47.110 +input [`LM32_CSR_RNG] jtag_csr;                 // Which CSR to write
  47.111 +`endif
  47.112 +`ifdef LM32_SINGLE_STEP_ENABLED
  47.113 +input eret_q_x;                                 // eret instruction in X stage
  47.114 +input bret_q_x;                                 // bret instruction in X stage
  47.115 +input stall_x;                                  // Instruction in X stage is stalled
  47.116 +input exception_x;                              // An exception has occured in X stage 
  47.117 +input q_x;                                      // Indicates the instruction in the X stage is qualified
  47.118 +`ifdef CFG_DCACHE_ENABLED
  47.119 +input dcache_refill_request;                    // Indicates data cache wants to be refilled 
  47.120 +`endif
  47.121 +`endif
  47.122 +
  47.123 +/////////////////////////////////////////////////////
  47.124 +// Outputs
  47.125 +/////////////////////////////////////////////////////
  47.126 +
  47.127 +`ifdef LM32_SINGLE_STEP_ENABLED
  47.128 +output dc_ss;                                   // Single-step enable
  47.129 +reg    dc_ss;
  47.130 +`endif
  47.131 +output dc_re;                                   // Remap exceptions
  47.132 +reg    dc_re;
  47.133 +output bp_match;                                // Indicates a breakpoint has matched
  47.134 +wire   bp_match;        
  47.135 +output wp_match;                                // Indicates a watchpoint has matched
  47.136 +wire   wp_match;
  47.137 +
  47.138 +/////////////////////////////////////////////////////
  47.139 +// Internal nets and registers 
  47.140 +/////////////////////////////////////////////////////
  47.141 +
  47.142 +genvar i;                                       // Loop index for generate statements
  47.143 +
  47.144 +// Debug CSRs
  47.145 +
  47.146 +reg [`LM32_PC_RNG] bp_a[0:breakpoints-1];       // Instruction breakpoint address
  47.147 +reg bp_e[0:breakpoints-1];                      // Instruction breakpoint enable
  47.148 +wire [0:breakpoints-1]bp_match_n;               // Indicates if a h/w instruction breakpoint matched
  47.149 +
  47.150 +reg [`LM32_WPC_C_RNG] wpc_c[0:watchpoints-1];   // Watchpoint enable
  47.151 +reg [`LM32_WORD_RNG] wp[0:watchpoints-1];       // Watchpoint address
  47.152 +wire [0:watchpoints]wp_match_n;               // Indicates if a h/w data watchpoint matched
  47.153 +
  47.154 +wire debug_csr_write_enable;                    // Debug CSR write enable (from either a wcsr instruction of external debugger)
  47.155 +wire [`LM32_WORD_RNG] debug_csr_write_data;     // Data to write to debug CSR
  47.156 +wire [`LM32_CSR_RNG] debug_csr;                 // Debug CSR to write to
  47.157 +
  47.158 +`ifdef LM32_SINGLE_STEP_ENABLED
  47.159 +// FIXME: Declaring this as a reg causes ModelSim 6.1.15b to crash, so use integer for now
  47.160 +//reg [`LM32_DEBUG_SS_STATE_RNG] state;           // State of single-step FSM
  47.161 +integer state;                                  // State of single-step FSM
  47.162 +`endif
  47.163 +
  47.164 +/////////////////////////////////////////////////////
  47.165 +// Functions
  47.166 +/////////////////////////////////////////////////////
  47.167 +
  47.168 +`include "lm32_functions.v"
  47.169 +
  47.170 +/////////////////////////////////////////////////////
  47.171 +// Combinational Logic
  47.172 +/////////////////////////////////////////////////////
  47.173 +
  47.174 +// Check for breakpoints
  47.175 +generate
  47.176 +    for (i = 0; i < breakpoints; i = i + 1)
  47.177 +    begin : bp_comb
  47.178 +assign bp_match_n[i] = ((bp_a[i] == pc_x) && (bp_e[i] == `TRUE));
  47.179 +    end
  47.180 +endgenerate
  47.181 +generate 
  47.182 +`ifdef LM32_SINGLE_STEP_ENABLED
  47.183 +    if (breakpoints > 0) 
  47.184 +assign bp_match = (|bp_match_n) || (state == `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT);
  47.185 +    else
  47.186 +assign bp_match = state == `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT;
  47.187 +`else
  47.188 +    if (breakpoints > 0) 
  47.189 +assign bp_match = |bp_match_n;
  47.190 +    else
  47.191 +assign bp_match = `FALSE;
  47.192 +`endif
  47.193 +endgenerate    
  47.194 +               
  47.195 +// Check for watchpoints
  47.196 +generate 
  47.197 +    for (i = 0; i < watchpoints; i = i + 1)
  47.198 +    begin : wp_comb
  47.199 +assign wp_match_n[i] = (wp[i] == load_store_address_x) && ((load_x & wpc_c[i][0]) | (store_x & wpc_c[i][1]));
  47.200 +    end               
  47.201 +endgenerate
  47.202 +generate
  47.203 +    if (watchpoints > 0) 
  47.204 +assign wp_match = |wp_match_n;                
  47.205 +    else
  47.206 +assign wp_match = `FALSE;
  47.207 +endgenerate
  47.208 +                
  47.209 +`ifdef CFG_HW_DEBUG_ENABLED                
  47.210 +// Multiplex between wcsr instruction writes and debugger writes to the debug CSRs
  47.211 +assign debug_csr_write_enable = (csr_write_enable_x == `TRUE) || (jtag_csr_write_enable == `TRUE);
  47.212 +assign debug_csr_write_data = jtag_csr_write_enable == `TRUE ? jtag_csr_write_data : csr_write_data;
  47.213 +assign debug_csr = jtag_csr_write_enable == `TRUE ? jtag_csr : csr_x;
  47.214 +`else
  47.215 +assign debug_csr_write_enable = csr_write_enable_x;
  47.216 +assign debug_csr_write_data = csr_write_data;
  47.217 +assign debug_csr = csr_x;
  47.218 +`endif
  47.219 +
  47.220 +/////////////////////////////////////////////////////
  47.221 +// Sequential Logic
  47.222 +/////////////////////////////////////////////////////
  47.223 +
  47.224 +// Breakpoint address and enable CSRs
  47.225 +generate
  47.226 +    for (i = 0; i < breakpoints; i = i + 1)
  47.227 +    begin : bp_seq
  47.228 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  47.229 +begin
  47.230 +    if (rst_i == `TRUE)
  47.231 +    begin
  47.232 +        bp_a[i] <= {`LM32_PC_WIDTH{1'bx}};
  47.233 +        bp_e[i] <= `FALSE;
  47.234 +    end
  47.235 +    else
  47.236 +    begin
  47.237 +        if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_BP0 + i))
  47.238 +        begin
  47.239 +            bp_a[i] <= debug_csr_write_data[`LM32_PC_RNG];
  47.240 +            bp_e[i] <= debug_csr_write_data[0];
  47.241 +        end
  47.242 +    end
  47.243 +end    
  47.244 +    end
  47.245 +endgenerate
  47.246 +
  47.247 +// Watchpoint address and control flags CSRs
  47.248 +generate
  47.249 +    for (i = 0; i < watchpoints; i = i + 1)
  47.250 +    begin : wp_seq
  47.251 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  47.252 +begin
  47.253 +    if (rst_i == `TRUE)
  47.254 +    begin
  47.255 +        wp[i] <= {`LM32_WORD_WIDTH{1'bx}};
  47.256 +        wpc_c[i] <= `LM32_WPC_C_DISABLED;
  47.257 +    end
  47.258 +    else
  47.259 +    begin
  47.260 +        if (debug_csr_write_enable == `TRUE)
  47.261 +        begin
  47.262 +            if (debug_csr == `LM32_CSR_DC)
  47.263 +                wpc_c[i] <= debug_csr_write_data[3+i*2:2+i*2];
  47.264 +            if (debug_csr == `LM32_CSR_WP0 + i)
  47.265 +                wp[i] <= debug_csr_write_data;
  47.266 +        end
  47.267 +    end  
  47.268 +end
  47.269 +    end
  47.270 +endgenerate
  47.271 +
  47.272 +// Remap exceptions control bit
  47.273 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  47.274 +begin
  47.275 +    if (rst_i == `TRUE)
  47.276 +        dc_re <= `FALSE;
  47.277 +    else
  47.278 +    begin
  47.279 +        if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_DC))
  47.280 +            dc_re <= debug_csr_write_data[1];
  47.281 +    end
  47.282 +end    
  47.283 +
  47.284 +`ifdef LM32_SINGLE_STEP_ENABLED
  47.285 +// Single-step control flag
  47.286 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  47.287 +begin
  47.288 +    if (rst_i == `TRUE)
  47.289 +    begin
  47.290 +        state <= `LM32_DEBUG_SS_STATE_IDLE;
  47.291 +        dc_ss <= `FALSE;
  47.292 +    end
  47.293 +    else
  47.294 +    begin
  47.295 +        if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_DC))
  47.296 +        begin
  47.297 +            dc_ss <= debug_csr_write_data[0];
  47.298 +            if (debug_csr_write_data[0] == `FALSE) 
  47.299 +                state <= `LM32_DEBUG_SS_STATE_IDLE;
  47.300 +            else 
  47.301 +                state <= `LM32_DEBUG_SS_STATE_WAIT_FOR_RET;
  47.302 +        end
  47.303 +        case (state)
  47.304 +        `LM32_DEBUG_SS_STATE_WAIT_FOR_RET:
  47.305 +        begin
  47.306 +            // Wait for eret or bret instruction to be executed
  47.307 +            if (   (   (eret_q_x == `TRUE)
  47.308 +                    || (bret_q_x == `TRUE)
  47.309 +                    )
  47.310 +                && (stall_x == `FALSE)
  47.311 +               )
  47.312 +                state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 
  47.313 +        end
  47.314 +        `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN:
  47.315 +        begin
  47.316 +            // Wait for an instruction to be executed
  47.317 +            if ((q_x == `TRUE) && (stall_x == `FALSE))
  47.318 +                state <= `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT;
  47.319 +        end
  47.320 +        `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT:
  47.321 +        begin
  47.322 +            // Wait for exception to be raised
  47.323 +`ifdef CFG_DCACHE_ENABLED
  47.324 +            if (dcache_refill_request == `TRUE)
  47.325 +                state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN;
  47.326 +            else 
  47.327 +`endif
  47.328 +                 if ((exception_x == `TRUE) && (q_x == `TRUE) && (stall_x == `FALSE))
  47.329 +            begin
  47.330 +                dc_ss <= `FALSE;
  47.331 +                state <= `LM32_DEBUG_SS_STATE_RESTART;
  47.332 +            end
  47.333 +        end
  47.334 +        `LM32_DEBUG_SS_STATE_RESTART:
  47.335 +        begin
  47.336 +            // Watch to see if stepped instruction is restarted due to a cache miss
  47.337 +`ifdef CFG_DCACHE_ENABLED
  47.338 +            if (dcache_refill_request == `TRUE)
  47.339 +                state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN;
  47.340 +            else 
  47.341 +`endif
  47.342 +                state <= `LM32_DEBUG_SS_STATE_IDLE;
  47.343 +        end
  47.344 +        endcase
  47.345 +    end
  47.346 +end
  47.347 +`endif
  47.348 +
  47.349 +endmodule
  47.350 +
  47.351 +`endif

    48.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    48.2 +++ b/rtl/lm32_decoder.v	Tue Mar 08 09:40:42 2011 +0000
    48.3 @@ -0,0 +1,583 @@
    48.4 +// =============================================================================
    48.5 +//                           COPYRIGHT NOTICE
    48.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation
    48.7 +// ALL RIGHTS RESERVED
    48.8 +// This confidential and proprietary software may be used only as authorised by
    48.9 +// a licensing agreement from Lattice Semiconductor Corporation.
   48.10 +// The entire notice above must be reproduced on all authorized copies and
   48.11 +// copies may only be made to the extent permitted by a licensing agreement from
   48.12 +// Lattice Semiconductor Corporation.
   48.13 +//
   48.14 +// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
   48.15 +// 5555 NE Moore Court                            408-826-6000 (other locations)
   48.16 +// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
   48.17 +// U.S.A                                   email: techsupport@latticesemi.com
   48.18 +// =============================================================================/
   48.19 +//                         FILE DETAILS
   48.20 +// Project          : LatticeMico32
   48.21 +// File             : lm32_decoder.v
   48.22 +// Title            : Instruction decoder
   48.23 +// Dependencies     : lm32_include.v
   48.24 +// Version          : 6.1.17
   48.25 +//                  : Initial Release
   48.26 +// Version          : 7.0SP2, 3.0
   48.27 +//                  : No Change
   48.28 +// Version          : 3.1
   48.29 +//                  : Support for static branch prediction. Information about
   48.30 +//                  : branch type is generated and passed on to the predictor.
   48.31 +// Version          : 3.2
   48.32 +//                  : No change
   48.33 +// Version          : 3.3
   48.34 +//                  : Renamed port names that conflict with keywords reserved
   48.35 +//                  : in System-Verilog.
   48.36 +// =============================================================================
   48.37 +
   48.38 +`include "lm32_include.v"
   48.39 +
   48.40 +// Index of opcode field in an instruction
   48.41 +`define LM32_OPCODE_RNG         31:26
   48.42 +`define LM32_OP_RNG             30:26
   48.43 +
   48.44 +// Opcodes - Some are only listed as 5 bits as their MSB is a don't care
   48.45 +`define LM32_OPCODE_ADD         5'b01101
   48.46 +`define LM32_OPCODE_AND         5'b01000
   48.47 +`define LM32_OPCODE_ANDHI       6'b011000
   48.48 +`define LM32_OPCODE_B           6'b110000
   48.49 +`define LM32_OPCODE_BI          6'b111000
   48.50 +`define LM32_OPCODE_BE          6'b010001
   48.51 +`define LM32_OPCODE_BG          6'b010010
   48.52 +`define LM32_OPCODE_BGE         6'b010011
   48.53 +`define LM32_OPCODE_BGEU        6'b010100
   48.54 +`define LM32_OPCODE_BGU         6'b010101
   48.55 +`define LM32_OPCODE_BNE         6'b010111
   48.56 +`define LM32_OPCODE_CALL        6'b110110
   48.57 +`define LM32_OPCODE_CALLI       6'b111110
   48.58 +`define LM32_OPCODE_CMPE        5'b11001
   48.59 +`define LM32_OPCODE_CMPG        5'b11010
   48.60 +`define LM32_OPCODE_CMPGE       5'b11011
   48.61 +`define LM32_OPCODE_CMPGEU      5'b11100
   48.62 +`define LM32_OPCODE_CMPGU       5'b11101
   48.63 +`define LM32_OPCODE_CMPNE       5'b11111
   48.64 +`define LM32_OPCODE_DIVU        6'b100011
   48.65 +`define LM32_OPCODE_LB          6'b000100
   48.66 +`define LM32_OPCODE_LBU         6'b010000
   48.67 +`define LM32_OPCODE_LH          6'b000111
   48.68 +`define LM32_OPCODE_LHU         6'b001011
   48.69 +`define LM32_OPCODE_LW          6'b001010
   48.70 +`define LM32_OPCODE_MODU        6'b110001
   48.71 +`define LM32_OPCODE_MUL         5'b00010
   48.72 +`define LM32_OPCODE_NOR         5'b00001
   48.73 +`define LM32_OPCODE_OR          5'b01110
   48.74 +`define LM32_OPCODE_ORHI        6'b011110
   48.75 +`define LM32_OPCODE_RAISE       6'b101011
   48.76 +`define LM32_OPCODE_RCSR        6'b100100
   48.77 +`define LM32_OPCODE_SB          6'b001100
   48.78 +`define LM32_OPCODE_SEXTB       6'b101100
   48.79 +`define LM32_OPCODE_SEXTH       6'b110111
   48.80 +`define LM32_OPCODE_SH          6'b000011
   48.81 +`define LM32_OPCODE_SL          5'b01111
   48.82 +`define LM32_OPCODE_SR          5'b00101
   48.83 +`define LM32_OPCODE_SRU         5'b00000
   48.84 +`define LM32_OPCODE_SUB         6'b110010
   48.85 +`define LM32_OPCODE_SW          6'b010110
   48.86 +`define LM32_OPCODE_USER        6'b110011
   48.87 +`define LM32_OPCODE_WCSR        6'b110100
   48.88 +`define LM32_OPCODE_XNOR        5'b01001
   48.89 +`define LM32_OPCODE_XOR         5'b00110
   48.90 +
   48.91 +/////////////////////////////////////////////////////
   48.92 +// Module interface
   48.93 +/////////////////////////////////////////////////////
   48.94 +
   48.95 +module lm32_decoder (
   48.96 +    // ----- Inputs -------
   48.97 +    instruction,
   48.98 +    // ----- Outputs -------
   48.99 +    d_result_sel_0,
  48.100 +    d_result_sel_1,        
  48.101 +    x_result_sel_csr,
  48.102 +`ifdef LM32_MC_ARITHMETIC_ENABLED
  48.103 +    x_result_sel_mc_arith,
  48.104 +`endif    
  48.105 +`ifdef LM32_NO_BARREL_SHIFT    
  48.106 +    x_result_sel_shift,
  48.107 +`endif
  48.108 +`ifdef CFG_SIGN_EXTEND_ENABLED
  48.109 +    x_result_sel_sext,
  48.110 +`endif    
  48.111 +    x_result_sel_logic,
  48.112 +`ifdef CFG_USER_ENABLED
  48.113 +    x_result_sel_user,
  48.114 +`endif
  48.115 +    x_result_sel_add,
  48.116 +    m_result_sel_compare,
  48.117 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  48.118 +    m_result_sel_shift,  
  48.119 +`endif    
  48.120 +    w_result_sel_load,
  48.121 +`ifdef CFG_PL_MULTIPLY_ENABLED
  48.122 +    w_result_sel_mul,
  48.123 +`endif
  48.124 +    x_bypass_enable,
  48.125 +    m_bypass_enable,
  48.126 +    read_enable_0,
  48.127 +    read_idx_0,
  48.128 +    read_enable_1,
  48.129 +    read_idx_1,
  48.130 +    write_enable,
  48.131 +    write_idx,
  48.132 +    immediate,
  48.133 +    branch_offset,
  48.134 +    load,
  48.135 +    store,
  48.136 +    size,
  48.137 +    sign_extend,
  48.138 +    adder_op,
  48.139 +    logic_op,
  48.140 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  48.141 +    direction,
  48.142 +`endif
  48.143 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED
  48.144 +    shift_left,
  48.145 +    shift_right,
  48.146 +`endif
  48.147 +`ifdef CFG_MC_MULTIPLY_ENABLED
  48.148 +    multiply,
  48.149 +`endif
  48.150 +`ifdef CFG_MC_DIVIDE_ENABLED
  48.151 +    divide,
  48.152 +    modulus,
  48.153 +`endif
  48.154 +    branch,
  48.155 +    branch_reg,
  48.156 +    condition,
  48.157 +    bi_conditional,
  48.158 +    bi_unconditional,
  48.159 +`ifdef CFG_DEBUG_ENABLED
  48.160 +    break_opcode,
  48.161 +`endif
  48.162 +    scall,
  48.163 +    eret,
  48.164 +`ifdef CFG_DEBUG_ENABLED
  48.165 +    bret,
  48.166 +`endif
  48.167 +`ifdef CFG_USER_ENABLED
  48.168 +    user_opcode,
  48.169 +`endif
  48.170 +    csr_write_enable
  48.171 +    );
  48.172 +
  48.173 +/////////////////////////////////////////////////////
  48.174 +// Inputs
  48.175 +/////////////////////////////////////////////////////
  48.176 +
  48.177 +input [`LM32_INSTRUCTION_RNG] instruction;       // Instruction to decode
  48.178 +
  48.179 +/////////////////////////////////////////////////////
  48.180 +// Outputs
  48.181 +/////////////////////////////////////////////////////
  48.182 +
  48.183 +output [`LM32_D_RESULT_SEL_0_RNG] d_result_sel_0;
  48.184 +reg    [`LM32_D_RESULT_SEL_0_RNG] d_result_sel_0;
  48.185 +output [`LM32_D_RESULT_SEL_1_RNG] d_result_sel_1;
  48.186 +reg    [`LM32_D_RESULT_SEL_1_RNG] d_result_sel_1;
  48.187 +output x_result_sel_csr;
  48.188 +reg    x_result_sel_csr;
  48.189 +`ifdef LM32_MC_ARITHMETIC_ENABLED
  48.190 +output x_result_sel_mc_arith;
  48.191 +reg    x_result_sel_mc_arith;
  48.192 +`endif
  48.193 +`ifdef LM32_NO_BARREL_SHIFT    
  48.194 +output x_result_sel_shift;
  48.195 +reg    x_result_sel_shift;
  48.196 +`endif
  48.197 +`ifdef CFG_SIGN_EXTEND_ENABLED
  48.198 +output x_result_sel_sext;
  48.199 +reg    x_result_sel_sext;
  48.200 +`endif
  48.201 +output x_result_sel_logic;
  48.202 +reg    x_result_sel_logic;
  48.203 +`ifdef CFG_USER_ENABLED
  48.204 +output x_result_sel_user;
  48.205 +reg    x_result_sel_user;
  48.206 +`endif
  48.207 +output x_result_sel_add;
  48.208 +reg    x_result_sel_add;
  48.209 +output m_result_sel_compare;
  48.210 +reg    m_result_sel_compare;
  48.211 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  48.212 +output m_result_sel_shift;
  48.213 +reg    m_result_sel_shift;
  48.214 +`endif
  48.215 +output w_result_sel_load;
  48.216 +reg    w_result_sel_load;
  48.217 +`ifdef CFG_PL_MULTIPLY_ENABLED
  48.218 +output w_result_sel_mul;
  48.219 +reg    w_result_sel_mul;
  48.220 +`endif
  48.221 +output x_bypass_enable;
  48.222 +wire   x_bypass_enable;
  48.223 +output m_bypass_enable;
  48.224 +wire   m_bypass_enable;
  48.225 +output read_enable_0;
  48.226 +wire   read_enable_0;
  48.227 +output [`LM32_REG_IDX_RNG] read_idx_0;
  48.228 +wire   [`LM32_REG_IDX_RNG] read_idx_0;
  48.229 +output read_enable_1;
  48.230 +wire   read_enable_1;
  48.231 +output [`LM32_REG_IDX_RNG] read_idx_1;
  48.232 +wire   [`LM32_REG_IDX_RNG] read_idx_1;
  48.233 +output write_enable;
  48.234 +wire   write_enable;
  48.235 +output [`LM32_REG_IDX_RNG] write_idx;
  48.236 +wire   [`LM32_REG_IDX_RNG] write_idx;
  48.237 +output [`LM32_WORD_RNG] immediate;
  48.238 +wire   [`LM32_WORD_RNG] immediate;
  48.239 +output [`LM32_PC_RNG] branch_offset;
  48.240 +wire   [`LM32_PC_RNG] branch_offset;
  48.241 +output load;
  48.242 +wire   load;
  48.243 +output store;
  48.244 +wire   store;
  48.245 +output [`LM32_SIZE_RNG] size;
  48.246 +wire   [`LM32_SIZE_RNG] size;
  48.247 +output sign_extend;
  48.248 +wire   sign_extend;
  48.249 +output adder_op;
  48.250 +wire   adder_op;
  48.251 +output [`LM32_LOGIC_OP_RNG] logic_op;
  48.252 +wire   [`LM32_LOGIC_OP_RNG] logic_op;
  48.253 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  48.254 +output direction;
  48.255 +wire   direction;
  48.256 +`endif
  48.257 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED
  48.258 +output shift_left;
  48.259 +wire   shift_left;
  48.260 +output shift_right;
  48.261 +wire   shift_right;
  48.262 +`endif
  48.263 +`ifdef CFG_MC_MULTIPLY_ENABLED
  48.264 +output multiply;
  48.265 +wire   multiply;
  48.266 +`endif
  48.267 +`ifdef CFG_MC_DIVIDE_ENABLED
  48.268 +output divide;
  48.269 +wire   divide;
  48.270 +output modulus;
  48.271 +wire   modulus;
  48.272 +`endif
  48.273 +output branch;
  48.274 +wire   branch;
  48.275 +output branch_reg;
  48.276 +wire   branch_reg;
  48.277 +output [`LM32_CONDITION_RNG] condition;
  48.278 +wire   [`LM32_CONDITION_RNG] condition;
  48.279 +output bi_conditional;
  48.280 +wire bi_conditional;
  48.281 +output bi_unconditional;
  48.282 +wire bi_unconditional;
  48.283 +`ifdef CFG_DEBUG_ENABLED
  48.284 +output break_opcode;
  48.285 +wire   break_opcode;
  48.286 +`endif
  48.287 +output scall;
  48.288 +wire   scall;
  48.289 +output eret;
  48.290 +wire   eret;
  48.291 +`ifdef CFG_DEBUG_ENABLED
  48.292 +output bret;
  48.293 +wire   bret;
  48.294 +`endif
  48.295 +`ifdef CFG_USER_ENABLED
  48.296 +output [`LM32_USER_OPCODE_RNG] user_opcode;
  48.297 +wire   [`LM32_USER_OPCODE_RNG] user_opcode;
  48.298 +`endif
  48.299 +output csr_write_enable;
  48.300 +wire   csr_write_enable;
  48.301 +
  48.302 +/////////////////////////////////////////////////////
  48.303 +// Internal nets and registers 
  48.304 +/////////////////////////////////////////////////////
  48.305 +
  48.306 +wire [`LM32_WORD_RNG] extended_immediate;       // Zero or sign extended immediate
  48.307 +wire [`LM32_WORD_RNG] high_immediate;           // Immediate as high 16 bits
  48.308 +wire [`LM32_WORD_RNG] call_immediate;           // Call immediate
  48.309 +wire [`LM32_WORD_RNG] branch_immediate;         // Conditional branch immediate
  48.310 +wire sign_extend_immediate;                     // Whether the immediate should be sign extended (`TRUE) or zero extended (`FALSE)
  48.311 +wire select_high_immediate;                     // Whether to select the high immediate  
  48.312 +wire select_call_immediate;                     // Whether to select the call immediate 
  48.313 +
  48.314 +/////////////////////////////////////////////////////
  48.315 +// Functions
  48.316 +/////////////////////////////////////////////////////
  48.317 +
  48.318 +`include "lm32_functions.v"
  48.319 +
  48.320 +/////////////////////////////////////////////////////
  48.321 +// Combinational logic
  48.322 +/////////////////////////////////////////////////////
  48.323 +
  48.324 +// Determine opcode
  48.325 +assign op_add    = instruction[`LM32_OP_RNG] == `LM32_OPCODE_ADD;
  48.326 +assign op_and    = instruction[`LM32_OP_RNG] == `LM32_OPCODE_AND;
  48.327 +assign op_andhi  = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_ANDHI;
  48.328 +assign op_b      = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_B;
  48.329 +assign op_bi     = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BI;
  48.330 +assign op_be     = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BE;
  48.331 +assign op_bg     = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BG;
  48.332 +assign op_bge    = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BGE;
  48.333 +assign op_bgeu   = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BGEU;
  48.334 +assign op_bgu    = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BGU;
  48.335 +assign op_bne    = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BNE;
  48.336 +assign op_call   = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_CALL;
  48.337 +assign op_calli  = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_CALLI;
  48.338 +assign op_cmpe   = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPE;
  48.339 +assign op_cmpg   = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPG;
  48.340 +assign op_cmpge  = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPGE;
  48.341 +assign op_cmpgeu = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPGEU;
  48.342 +assign op_cmpgu  = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPGU;
  48.343 +assign op_cmpne  = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPNE;
  48.344 +`ifdef CFG_MC_DIVIDE_ENABLED
  48.345 +assign op_divu   = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_DIVU;
  48.346 +`endif
  48.347 +assign op_lb     = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LB;
  48.348 +assign op_lbu    = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LBU;
  48.349 +assign op_lh     = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LH;
  48.350 +assign op_lhu    = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LHU;
  48.351 +assign op_lw     = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LW;
  48.352 +`ifdef CFG_MC_DIVIDE_ENABLED
  48.353 +assign op_modu   = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_MODU;
  48.354 +`endif
  48.355 +`ifdef LM32_MULTIPLY_ENABLED
  48.356 +assign op_mul    = instruction[`LM32_OP_RNG] == `LM32_OPCODE_MUL;
  48.357 +`endif
  48.358 +assign op_nor    = instruction[`LM32_OP_RNG] == `LM32_OPCODE_NOR;
  48.359 +assign op_or     = instruction[`LM32_OP_RNG] == `LM32_OPCODE_OR;
  48.360 +assign op_orhi   = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_ORHI;
  48.361 +assign op_raise  = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_RAISE;
  48.362 +assign op_rcsr   = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_RCSR;
  48.363 +assign op_sb     = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SB;
  48.364 +`ifdef CFG_SIGN_EXTEND_ENABLED
  48.365 +assign op_sextb  = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SEXTB;
  48.366 +assign op_sexth  = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SEXTH;
  48.367 +`endif
  48.368 +assign op_sh     = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SH;
  48.369 +`ifdef LM32_BARREL_SHIFT_ENABLED
  48.370 +assign op_sl     = instruction[`LM32_OP_RNG] == `LM32_OPCODE_SL;      
  48.371 +`endif
  48.372 +assign op_sr     = instruction[`LM32_OP_RNG] == `LM32_OPCODE_SR;
  48.373 +assign op_sru    = instruction[`LM32_OP_RNG] == `LM32_OPCODE_SRU;
  48.374 +assign op_sub    = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SUB;
  48.375 +assign op_sw     = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SW;
  48.376 +assign op_user   = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_USER;
  48.377 +assign op_wcsr   = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_WCSR;
  48.378 +assign op_xnor   = instruction[`LM32_OP_RNG] == `LM32_OPCODE_XNOR;
  48.379 +assign op_xor    = instruction[`LM32_OP_RNG] == `LM32_OPCODE_XOR;
  48.380 +
  48.381 +// Group opcodes by function
  48.382 +assign arith = op_add | op_sub;
  48.383 +assign logical = op_and | op_andhi | op_nor | op_or | op_orhi | op_xor | op_xnor;
  48.384 +assign cmp = op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne;
  48.385 +assign bi_conditional = op_be | op_bg | op_bge | op_bgeu  | op_bgu | op_bne;
  48.386 +assign bi_unconditional = op_bi;
  48.387 +assign bra = op_b | bi_unconditional | bi_conditional;
  48.388 +assign call = op_call | op_calli;
  48.389 +`ifdef LM32_BARREL_SHIFT_ENABLED
  48.390 +assign shift = op_sl | op_sr | op_sru;
  48.391 +`endif
  48.392 +`ifdef LM32_NO_BARREL_SHIFT
  48.393 +assign shift = op_sr | op_sru;
  48.394 +`endif
  48.395 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED
  48.396 +assign shift_left = op_sl;
  48.397 +assign shift_right = op_sr | op_sru;
  48.398 +`endif
  48.399 +`ifdef CFG_SIGN_EXTEND_ENABLED
  48.400 +assign sext = op_sextb | op_sexth;
  48.401 +`endif
  48.402 +`ifdef LM32_MULTIPLY_ENABLED
  48.403 +assign multiply = op_mul;
  48.404 +`endif
  48.405 +`ifdef CFG_MC_DIVIDE_ENABLED
  48.406 +assign divide = op_divu; 
  48.407 +assign modulus = op_modu;
  48.408 +`endif
  48.409 +assign load = op_lb | op_lbu | op_lh | op_lhu | op_lw;
  48.410 +assign store = op_sb | op_sh | op_sw;
  48.411 +
  48.412 +// Select pipeline multiplexor controls
  48.413 +always @(*)
  48.414 +begin
  48.415 +    // D stage
  48.416 +    if (call) 
  48.417 +        d_result_sel_0 = `LM32_D_RESULT_SEL_0_NEXT_PC;
  48.418 +    else 
  48.419 +        d_result_sel_0 = `LM32_D_RESULT_SEL_0_REG_0;
  48.420 +    if (call) 
  48.421 +        d_result_sel_1 = `LM32_D_RESULT_SEL_1_ZERO;         
  48.422 +    else if ((instruction[31] == 1'b0) && !bra) 
  48.423 +        d_result_sel_1 = `LM32_D_RESULT_SEL_1_IMMEDIATE;
  48.424 +    else
  48.425 +        d_result_sel_1 = `LM32_D_RESULT_SEL_1_REG_1; 
  48.426 +    // X stage
  48.427 +    x_result_sel_csr = `FALSE;
  48.428 +`ifdef LM32_MC_ARITHMETIC_ENABLED
  48.429 +    x_result_sel_mc_arith = `FALSE;
  48.430 +`endif
  48.431 +`ifdef LM32_NO_BARREL_SHIFT
  48.432 +    x_result_sel_shift = `FALSE;
  48.433 +`endif
  48.434 +`ifdef CFG_SIGN_EXTEND_ENABLED
  48.435 +    x_result_sel_sext = `FALSE;
  48.436 +`endif
  48.437 +    x_result_sel_logic = `FALSE;
  48.438 +`ifdef CFG_USER_ENABLED        
  48.439 +    x_result_sel_user = `FALSE;
  48.440 +`endif
  48.441 +    x_result_sel_add = `FALSE;
  48.442 +    if (op_rcsr)
  48.443 +        x_result_sel_csr = `TRUE;
  48.444 +`ifdef LM32_MC_ARITHMETIC_ENABLED    
  48.445 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED
  48.446 +    else if (shift_left | shift_right) 
  48.447 +        x_result_sel_mc_arith = `TRUE;
  48.448 +`endif
  48.449 +`ifdef CFG_MC_DIVIDE_ENABLED
  48.450 +    else if (divide | modulus)
  48.451 +        x_result_sel_mc_arith = `TRUE;        
  48.452 +`endif
  48.453 +`ifdef CFG_MC_MULTIPLY_ENABLED
  48.454 +    else if (multiply)
  48.455 +        x_result_sel_mc_arith = `TRUE;            
  48.456 +`endif
  48.457 +`endif
  48.458 +`ifdef LM32_NO_BARREL_SHIFT
  48.459 +    else if (shift)
  48.460 +        x_result_sel_shift = `TRUE;        
  48.461 +`endif
  48.462 +`ifdef CFG_SIGN_EXTEND_ENABLED
  48.463 +    else if (sext)
  48.464 +        x_result_sel_sext = `TRUE;
  48.465 +`endif        
  48.466 +    else if (logical) 
  48.467 +        x_result_sel_logic = `TRUE;
  48.468 +`ifdef CFG_USER_ENABLED        
  48.469 +    else if (op_user)
  48.470 +        x_result_sel_user = `TRUE;
  48.471 +`endif
  48.472 +    else 
  48.473 +        x_result_sel_add = `TRUE;        
  48.474 +    
  48.475 +    // M stage
  48.476 +
  48.477 +    m_result_sel_compare = cmp;
  48.478 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  48.479 +    m_result_sel_shift = shift;
  48.480 +`endif
  48.481 +
  48.482 +    // W stage
  48.483 +    w_result_sel_load = load;
  48.484 +`ifdef CFG_PL_MULTIPLY_ENABLED
  48.485 +    w_result_sel_mul = op_mul; 
  48.486 +`endif
  48.487 +end
  48.488 +
  48.489 +// Set if result is valid at end of X stage
  48.490 +assign x_bypass_enable =  arith 
  48.491 +                        | logical
  48.492 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED
  48.493 +                        | shift_left
  48.494 +                        | shift_right
  48.495 +`endif                        
  48.496 +`ifdef CFG_MC_MULTIPLY_ENABLED
  48.497 +                        | multiply
  48.498 +`endif
  48.499 +`ifdef CFG_MC_DIVIDE_ENABLED
  48.500 +                        | divide
  48.501 +                        | modulus
  48.502 +`endif
  48.503 +`ifdef LM32_NO_BARREL_SHIFT
  48.504 +                        | shift
  48.505 +`endif                  
  48.506 +`ifdef CFG_SIGN_EXTEND_ENABLED
  48.507 +                        | sext 
  48.508 +`endif                        
  48.509 +`ifdef CFG_USER_ENABLED
  48.510 +                        | op_user
  48.511 +`endif
  48.512 +                        | op_rcsr
  48.513 +                        ;
  48.514 +// Set if result is valid at end of M stage                        
  48.515 +assign m_bypass_enable = x_bypass_enable 
  48.516 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  48.517 +                        | shift
  48.518 +`endif
  48.519 +                        | cmp
  48.520 +                        ;
  48.521 +// Register file read port 0                        
  48.522 +assign read_enable_0 = ~(op_bi | op_calli);
  48.523 +assign read_idx_0 = instruction[25:21];
  48.524 +// Register file read port 1 
  48.525 +assign read_enable_1 = ~(op_bi | op_calli | load);
  48.526 +assign read_idx_1 = instruction[20:16];
  48.527 +// Register file write port
  48.528 +assign write_enable = ~(bra | op_raise | store | op_wcsr);
  48.529 +assign write_idx = call
  48.530 +                    ? 5'd29
  48.531 +                    : instruction[31] == 1'b0 
  48.532 +                        ? instruction[20:16] 
  48.533 +                        : instruction[15:11];
  48.534 +                        
  48.535 +// Size of load/stores                        
  48.536 +assign size = instruction[27:26];
  48.537 +// Whether to sign or zero extend
  48.538 +assign sign_extend = instruction[28];                      
  48.539 +// Set adder_op to 1 to perform a subtraction
  48.540 +assign adder_op = op_sub | op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne | bra;
  48.541 +// Logic operation (and, or, etc)
  48.542 +assign logic_op = instruction[29:26];
  48.543 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  48.544 +// Shift direction
  48.545 +assign direction = instruction[29];
  48.546 +`endif
  48.547 +// Control flow microcodes
  48.548 +assign branch = bra | call;
  48.549 +assign branch_reg = op_call | op_b;
  48.550 +assign condition = instruction[28:26];      
  48.551 +`ifdef CFG_DEBUG_ENABLED
  48.552 +assign break_opcode = op_raise & ~instruction[2];
  48.553 +`endif
  48.554 +assign scall = op_raise & instruction[2];
  48.555 +assign eret = op_b & (instruction[25:21] == 5'd30);
  48.556 +`ifdef CFG_DEBUG_ENABLED
  48.557 +assign bret = op_b & (instruction[25:21] == 5'd31);
  48.558 +`endif
  48.559 +`ifdef CFG_USER_ENABLED
  48.560 +// Extract user opcode
  48.561 +assign user_opcode = instruction[10:0];
  48.562 +`endif
  48.563 +// CSR read/write
  48.564 +assign csr_write_enable = op_wcsr;
  48.565 +
  48.566 +// Extract immediate from instruction
  48.567 +
  48.568 +assign sign_extend_immediate = ~(op_and | op_cmpgeu | op_cmpgu | op_nor | op_or | op_xnor | op_xor);
  48.569 +assign select_high_immediate = op_andhi | op_orhi;
  48.570 +assign select_call_immediate = instruction[31];
  48.571 +
  48.572 +assign high_immediate = {instruction[15:0], 16'h0000};
  48.573 +assign extended_immediate = {{16{sign_extend_immediate & instruction[15]}}, instruction[15:0]};
  48.574 +assign call_immediate = {{6{instruction[25]}}, instruction[25:0]};
  48.575 +assign branch_immediate = {{16{instruction[15]}}, instruction[15:0]};
  48.576 +
  48.577 +assign immediate = select_high_immediate == `TRUE 
  48.578 +                        ? high_immediate 
  48.579 +                        : extended_immediate;
  48.580 +   
  48.581 +assign branch_offset = select_call_immediate == `TRUE   
  48.582 +                        ? call_immediate
  48.583 +                        : branch_immediate;
  48.584 +    
  48.585 +endmodule 
  48.586 +

    49.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    49.2 +++ b/rtl/lm32_dp_ram.v	Tue Mar 08 09:40:42 2011 +0000
    49.3 @@ -0,0 +1,35 @@
    49.4 +module lm32_dp_ram(
    49.5 +	clk_i,
    49.6 +	rst_i,
    49.7 +	we_i,
    49.8 +	waddr_i,
    49.9 +	wdata_i,
   49.10 +	raddr_i,
   49.11 +	rdata_o);
   49.12 +
   49.13 +parameter addr_width = 32;
   49.14 +parameter addr_depth = 1024;
   49.15 +parameter data_width = 8;
   49.16 +
   49.17 +input clk_i;
   49.18 +input rst_i;
   49.19 +input we_i;
   49.20 +input [addr_width-1:0] waddr_i;
   49.21 +input [data_width-1:0] wdata_i;
   49.22 +input [addr_width-1:0] raddr_i;
   49.23 +output [data_width-1:0] rdata_o;
   49.24 +
   49.25 +reg [data_width-1:0] ram[addr_depth-1:0];
   49.26 +
   49.27 +reg [addr_width-1:0] raddr_r;
   49.28 +assign rdata_o = ram[raddr_r];
   49.29 +
   49.30 +always @ (posedge clk_i)
   49.31 +begin
   49.32 +	if (we_i)
   49.33 +		ram[waddr_i] <= wdata_i;
   49.34 +	raddr_r <= raddr_i;
   49.35 +end
   49.36 +
   49.37 +endmodule
   49.38 +

    50.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    50.2 +++ b/rtl/lm32_functions.v	Tue Mar 08 09:40:42 2011 +0000
    50.3 @@ -0,0 +1,49 @@
    50.4 +// =============================================================================
    50.5 +//                           COPYRIGHT NOTICE
    50.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation
    50.7 +// ALL RIGHTS RESERVED
    50.8 +// This confidential and proprietary software may be used only as authorised by
    50.9 +// a licensing agreement from Lattice Semiconductor Corporation.
   50.10 +// The entire notice above must be reproduced on all authorized copies and
   50.11 +// copies may only be made to the extent permitted by a licensing agreement from
   50.12 +// Lattice Semiconductor Corporation.
   50.13 +//
   50.14 +// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
   50.15 +// 5555 NE Moore Court                            408-826-6000 (other locations)
   50.16 +// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
   50.17 +// U.S.A                                   email: techsupport@latticesemi.com
   50.18 +// =============================================================================/
   50.19 +//                         FILE DETAILS
   50.20 +// Project      : LatticeMico32
   50.21 +// File         : lm32_functions.v
   50.22 +// Title        : Common functions
   50.23 +// Version      : 6.1.17
   50.24 +//              : Initial Release
   50.25 +// Version      : 7.0SP2, 3.0
   50.26 +//              : No Change
   50.27 +// Version      : 3.5
   50.28 +//              : Added function to generate log-of-two that rounds-up to
   50.29 +//              : power-of-two
   50.30 +// =============================================================================
   50.31 +					  
   50.32 +function integer clogb2;
   50.33 +input [31:0] value;
   50.34 +begin
   50.35 +   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
   50.36 +        value = value >> 1;
   50.37 +end
   50.38 +endfunction 
   50.39 +
   50.40 +function integer clogb2_v1;
   50.41 +input [31:0] value;
   50.42 +reg   [31:0] i;
   50.43 +reg   [31:0] temp;
   50.44 +begin
   50.45 +   temp = 0;
   50.46 +   i    = 0;
   50.47 +   for (i = 0; temp < value; i = i + 1)  
   50.48 +	temp = 1<<i;
   50.49 +   clogb2_v1 = i-1;
   50.50 +end
   50.51 +endfunction
   50.52 +

    51.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    51.2 +++ b/rtl/lm32_icache.v	Tue Mar 08 09:40:42 2011 +0000
    51.3 @@ -0,0 +1,494 @@
    51.4 +// =============================================================================
    51.5 +//                           COPYRIGHT NOTICE
    51.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation
    51.7 +// ALL RIGHTS RESERVED
    51.8 +// This confidential and proprietary software may be used only as authorised by
    51.9 +// a licensing agreement from Lattice Semiconductor Corporation.
   51.10 +// The entire notice above must be reproduced on all authorized copies and
   51.11 +// copies may only be made to the extent permitted by a licensing agreement from
   51.12 +// Lattice Semiconductor Corporation.
   51.13 +//
   51.14 +// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
   51.15 +// 5555 NE Moore Court                            408-826-6000 (other locations)
   51.16 +// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
   51.17 +// U.S.A                                   email: techsupport@latticesemi.com
   51.18 +// =============================================================================/
   51.19 +//                         FILE DETAILS
   51.20 +// Project          : LatticeMico32
   51.21 +// File             : lm32_icache.v
   51.22 +// Title            : Instruction cache
   51.23 +// Dependencies     : lm32_include.v
   51.24 +// 
   51.25 +// Version 3.5
   51.26 +// 1. Bug Fix: Instruction cache flushes issued from Instruction Inline Memory
   51.27 +//    cause segmentation fault due to incorrect fetches.
   51.28 +//
   51.29 +// Version 3.1
   51.30 +// 1. Feature: Support for user-selected resource usage when implementing
   51.31 +//    cache memory. Additional parameters must be defined when invoking module
   51.32 +//    lm32_ram. Instruction cache miss mechanism is dependent on branch
   51.33 +//    prediction being performed in D stage of pipeline.
   51.34 +//
   51.35 +// Version 7.0SP2, 3.0
   51.36 +// No change
   51.37 +// =============================================================================
   51.38 +					  
   51.39 +`include "lm32_include.v"
   51.40 +
   51.41 +`ifdef CFG_ICACHE_ENABLED
   51.42 +
   51.43 +`define LM32_IC_ADDR_OFFSET_RNG          addr_offset_msb:addr_offset_lsb
   51.44 +`define LM32_IC_ADDR_SET_RNG             addr_set_msb:addr_set_lsb
   51.45 +`define LM32_IC_ADDR_TAG_RNG             addr_tag_msb:addr_tag_lsb
   51.46 +`define LM32_IC_ADDR_IDX_RNG             addr_set_msb:addr_offset_lsb
   51.47 +
   51.48 +`define LM32_IC_TMEM_ADDR_WIDTH          addr_set_width
   51.49 +`define LM32_IC_TMEM_ADDR_RNG            (`LM32_IC_TMEM_ADDR_WIDTH-1):0
   51.50 +`define LM32_IC_DMEM_ADDR_WIDTH          (addr_offset_width+addr_set_width)
   51.51 +`define LM32_IC_DMEM_ADDR_RNG            (`LM32_IC_DMEM_ADDR_WIDTH-1):0
   51.52 +
   51.53 +`define LM32_IC_TAGS_WIDTH               (addr_tag_width+1)
   51.54 +`define LM32_IC_TAGS_RNG                 (`LM32_IC_TAGS_WIDTH-1):0
   51.55 +`define LM32_IC_TAGS_TAG_RNG             (`LM32_IC_TAGS_WIDTH-1):1
   51.56 +`define LM32_IC_TAGS_VALID_RNG           0
   51.57 +
   51.58 +`define LM32_IC_STATE_RNG                3:0
   51.59 +`define LM32_IC_STATE_FLUSH_INIT         4'b0001
   51.60 +`define LM32_IC_STATE_FLUSH              4'b0010
   51.61 +`define LM32_IC_STATE_CHECK              4'b0100
   51.62 +`define LM32_IC_STATE_REFILL             4'b1000
   51.63 +
   51.64 +/////////////////////////////////////////////////////
   51.65 +// Module interface
   51.66 +/////////////////////////////////////////////////////
   51.67 +
   51.68 +module lm32_icache ( 
   51.69 +    // ----- Inputs -----
   51.70 +    clk_i,
   51.71 +    rst_i,    
   51.72 +    stall_a,
   51.73 +    stall_f,
   51.74 +    address_a,
   51.75 +    address_f,
   51.76 +    read_enable_f,
   51.77 +    refill_ready,
   51.78 +    refill_data,
   51.79 +    iflush,
   51.80 +`ifdef CFG_IROM_ENABLED
   51.81 +    select_f,
   51.82 +`endif
   51.83 +    valid_d,
   51.84 +    branch_predict_taken_d,
   51.85 +    // ----- Outputs -----
   51.86 +    stall_request,
   51.87 +    restart_request,
   51.88 +    refill_request,
   51.89 +    refill_address,
   51.90 +    refilling,
   51.91 +    inst
   51.92 +    );
   51.93 +
   51.94 +/////////////////////////////////////////////////////
   51.95 +// Parameters
   51.96 +/////////////////////////////////////////////////////
   51.97 +
   51.98 +parameter associativity = 1;                            // Associativity of the cache (Number of ways)
   51.99 +parameter sets = 512;                                   // Number of sets
  51.100 +parameter bytes_per_line = 16;                          // Number of bytes per cache line
  51.101 +parameter base_address = 0;                             // Base address of cachable memory
  51.102 +parameter limit = 0;                                    // Limit (highest address) of cachable memory
  51.103 +
  51.104 +localparam addr_offset_width = clogb2(bytes_per_line)-1-2;
  51.105 +localparam addr_set_width = clogb2(sets)-1;
  51.106 +localparam addr_offset_lsb = 2;
  51.107 +localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
  51.108 +localparam addr_set_lsb = (addr_offset_msb+1);
  51.109 +localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
  51.110 +localparam addr_tag_lsb = (addr_set_msb+1);
  51.111 +localparam addr_tag_msb = clogb2(`CFG_ICACHE_LIMIT-`CFG_ICACHE_BASE_ADDRESS)-1;
  51.112 +localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);
  51.113 +
  51.114 +/////////////////////////////////////////////////////
  51.115 +// Inputs
  51.116 +/////////////////////////////////////////////////////
  51.117 +
  51.118 +input clk_i;                                        // Clock 
  51.119 +input rst_i;                                        // Reset
  51.120 +
  51.121 +input stall_a;                                      // Stall instruction in A stage
  51.122 +input stall_f;                                      // Stall instruction in F stage
  51.123 +
  51.124 +input valid_d;                                      // Valid instruction in D stage
  51.125 +input branch_predict_taken_d;                       // Instruction in D stage is a branch and is predicted taken
  51.126 +   
  51.127 +input [`LM32_PC_RNG] address_a;                     // Address of instruction in A stage
  51.128 +input [`LM32_PC_RNG] address_f;                     // Address of instruction in F stage
  51.129 +input read_enable_f;                                // Indicates if cache access is valid
  51.130 +
  51.131 +input refill_ready;                                 // Next word of refill data is ready
  51.132 +input [`LM32_INSTRUCTION_RNG] refill_data;          // Data to refill the cache with
  51.133 +
  51.134 +input iflush;                                       // Flush the cache
  51.135 +`ifdef CFG_IROM_ENABLED
  51.136 +input select_f;                                     // Instruction in F stage is mapped through instruction cache
  51.137 +`endif
  51.138 +   
  51.139 +/////////////////////////////////////////////////////
  51.140 +// Outputs
  51.141 +/////////////////////////////////////////////////////
  51.142 +
  51.143 +output stall_request;                               // Request to stall the pipeline
  51.144 +wire   stall_request;
  51.145 +output restart_request;                             // Request to restart instruction that caused the cache miss
  51.146 +reg    restart_request;
  51.147 +output refill_request;                              // Request to refill a cache line
  51.148 +wire   refill_request;
  51.149 +output [`LM32_PC_RNG] refill_address;               // Base address of cache refill
  51.150 +reg    [`LM32_PC_RNG] refill_address;               
  51.151 +output refilling;                                   // Indicates the instruction cache is currently refilling
  51.152 +reg    refilling;
  51.153 +output [`LM32_INSTRUCTION_RNG] inst;                // Instruction read from cache
  51.154 +wire   [`LM32_INSTRUCTION_RNG] inst;
  51.155 +
  51.156 +/////////////////////////////////////////////////////
  51.157 +// Internal nets and registers 
  51.158 +/////////////////////////////////////////////////////
  51.159 +
  51.160 +wire enable;
  51.161 +wire [0:associativity-1] way_mem_we;
  51.162 +wire [`LM32_INSTRUCTION_RNG] way_data[0:associativity-1];
  51.163 +wire [`LM32_IC_TAGS_TAG_RNG] way_tag[0:associativity-1];
  51.164 +wire [0:associativity-1] way_valid;
  51.165 +wire [0:associativity-1] way_match;
  51.166 +wire miss;
  51.167 +
  51.168 +wire [`LM32_IC_TMEM_ADDR_RNG] tmem_read_address;
  51.169 +wire [`LM32_IC_TMEM_ADDR_RNG] tmem_write_address;
  51.170 +wire [`LM32_IC_DMEM_ADDR_RNG] dmem_read_address;
  51.171 +wire [`LM32_IC_DMEM_ADDR_RNG] dmem_write_address;
  51.172 +wire [`LM32_IC_TAGS_RNG] tmem_write_data;
  51.173 +
  51.174 +reg [`LM32_IC_STATE_RNG] state;
  51.175 +wire flushing;
  51.176 +wire check;
  51.177 +wire refill;
  51.178 +
  51.179 +reg [associativity-1:0] refill_way_select;
  51.180 +reg [`LM32_IC_ADDR_OFFSET_RNG] refill_offset;
  51.181 +wire last_refill;
  51.182 +reg [`LM32_IC_TMEM_ADDR_RNG] flush_set;
  51.183 +
  51.184 +genvar i;
  51.185 +
  51.186 +/////////////////////////////////////////////////////
  51.187 +// Functions
  51.188 +/////////////////////////////////////////////////////
  51.189 +
  51.190 +`include "lm32_functions.v"
  51.191 +
  51.192 +/////////////////////////////////////////////////////
  51.193 +// Instantiations
  51.194 +/////////////////////////////////////////////////////
  51.195 +
  51.196 +   generate
  51.197 +      for (i = 0; i < associativity; i = i + 1)
  51.198 +	begin : memories
  51.199 +	   
  51.200 +	   lm32_ram 
  51.201 +	     #(
  51.202 +	       // ----- Parameters -------
  51.203 +	       .data_width                 (32),
  51.204 +	       .address_width              (`LM32_IC_DMEM_ADDR_WIDTH)
  51.205 +`ifdef PLATFORM_LATTICE
  51.206 +			,
  51.207 + `ifdef CFG_ICACHE_DAT_USE_DP_TRUE
  51.208 +	       .RAM_IMPLEMENTATION         ("EBR"),
  51.209 +	       .RAM_TYPE                   ("RAM_DP_TRUE")
  51.210 + `else
  51.211 +  `ifdef CFG_ICACHE_DAT_USE_DP
  51.212 +	       .RAM_IMPLEMENTATION         ("EBR"),
  51.213 +	       .RAM_TYPE                   ("RAM_DP")
  51.214 +  `else
  51.215 +   `ifdef CFG_ICACHE_DAT_USE_SLICE
  51.216 +	       .RAM_IMPLEMENTATION         ("SLICE")
  51.217 +   `else
  51.218 +	       .RAM_IMPLEMENTATION         ("AUTO")
  51.219 +   `endif
  51.220 +  `endif
  51.221 + `endif
  51.222 +`endif
  51.223 +	       ) 
  51.224 +	   way_0_data_ram 
  51.225 +	     (
  51.226 +	      // ----- Inputs -------
  51.227 +	      .read_clk                   (clk_i),
  51.228 +	      .write_clk                  (clk_i),
  51.229 +	      .reset                      (rst_i),
  51.230 +	      .read_address               (dmem_read_address),
  51.231 +	      .enable_read                (enable),
  51.232 +	      .write_address              (dmem_write_address),
  51.233 +	      .enable_write               (`TRUE),
  51.234 +	      .write_enable               (way_mem_we[i]),
  51.235 +	      .write_data                 (refill_data),    
  51.236 +	      // ----- Outputs -------
  51.237 +	      .read_data                  (way_data[i])
  51.238 +	      );
  51.239 +	   
  51.240 +	   lm32_ram 
  51.241 +	     #(
  51.242 +	       // ----- Parameters -------
  51.243 +	       .data_width                 (`LM32_IC_TAGS_WIDTH),
  51.244 +	       .address_width              (`LM32_IC_TMEM_ADDR_WIDTH)
  51.245 +`ifdef PLATFORM_LATTICE
  51.246 +			,
  51.247 + `ifdef CFG_ICACHE_DAT_USE_DP_TRUE
  51.248 +	       .RAM_IMPLEMENTATION         ("EBR"),
  51.249 +	       .RAM_TYPE                   ("RAM_DP_TRUE")
  51.250 + `else
  51.251 +  `ifdef CFG_ICACHE_DAT_USE_DP
  51.252 +	       .RAM_IMPLEMENTATION         ("EBR"),
  51.253 +	       .RAM_TYPE                   ("RAM_DP")
  51.254 +  `else
  51.255 +   `ifdef CFG_ICACHE_DAT_USE_SLICE
  51.256 +	       .RAM_IMPLEMENTATION         ("SLICE")
  51.257 +   `else
  51.258 +	       .RAM_IMPLEMENTATION         ("AUTO")
  51.259 +   `endif
  51.260 +  `endif
  51.261 + `endif
  51.262 +`endif
  51.263 +	       ) 
  51.264 +	   way_0_tag_ram 
  51.265 +	     (
  51.266 +	      // ----- Inputs -------
  51.267 +	      .read_clk                   (clk_i),
  51.268 +	      .write_clk                  (clk_i),
  51.269 +	      .reset                      (rst_i),
  51.270 +	      .read_address               (tmem_read_address),
  51.271 +	      .enable_read                (enable),
  51.272 +	      .write_address              (tmem_write_address),
  51.273 +	      .enable_write               (`TRUE),
  51.274 +	      .write_enable               (way_mem_we[i] | flushing),
  51.275 +	      .write_data                 (tmem_write_data),
  51.276 +	      // ----- Outputs -------
  51.277 +	      .read_data                  ({way_tag[i], way_valid[i]})
  51.278 +	      );
  51.279 +	   
  51.280 +	end
  51.281 +endgenerate
  51.282 +
  51.283 +/////////////////////////////////////////////////////
  51.284 +// Combinational logic
  51.285 +/////////////////////////////////////////////////////
  51.286 +
  51.287 +// Compute which ways in the cache match the address address being read
  51.288 +generate
  51.289 +    for (i = 0; i < associativity; i = i + 1)
  51.290 +    begin : match
  51.291 +assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_f[`LM32_IC_ADDR_TAG_RNG], `TRUE});
  51.292 +    end
  51.293 +endgenerate
  51.294 +
  51.295 +// Select data from way that matched the address being read     
  51.296 +generate
  51.297 +    if (associativity == 1)
  51.298 +    begin : inst_1
  51.299 +assign inst = way_match[0] ? way_data[0] : 32'b0;
  51.300 +    end
  51.301 +    else if (associativity == 2)
  51.302 +	 begin : inst_2
  51.303 +assign inst = way_match[0] ? way_data[0] : (way_match[1] ? way_data[1] : 32'b0);
  51.304 +    end
  51.305 +endgenerate
  51.306 +
  51.307 +// Compute address to use to index into the data memories
  51.308 +generate 
  51.309 +    if (bytes_per_line > 4)
  51.310 +assign dmem_write_address = {refill_address[`LM32_IC_ADDR_SET_RNG], refill_offset};
  51.311 +    else
  51.312 +assign dmem_write_address = refill_address[`LM32_IC_ADDR_SET_RNG];
  51.313 +endgenerate
  51.314 +    
  51.315 +assign dmem_read_address = address_a[`LM32_IC_ADDR_IDX_RNG];
  51.316 +
  51.317 +// Compute address to use to index into the tag memories                        
  51.318 +assign tmem_read_address = address_a[`LM32_IC_ADDR_SET_RNG];
  51.319 +assign tmem_write_address = flushing 
  51.320 +                                ? flush_set
  51.321 +                                : refill_address[`LM32_IC_ADDR_SET_RNG];
  51.322 +
  51.323 +// Compute signal to indicate when we are on the last refill accesses
  51.324 +generate 
  51.325 +    if (bytes_per_line > 4)                            
  51.326 +assign last_refill = refill_offset == {addr_offset_width{1'b1}};
  51.327 +    else
  51.328 +assign last_refill = `TRUE;
  51.329 +endgenerate
  51.330 +
  51.331 +// Compute data and tag memory access enable
  51.332 +assign enable = (stall_a == `FALSE);
  51.333 +
  51.334 +// Compute data and tag memory write enables
  51.335 +generate
  51.336 +    if (associativity == 1) 
  51.337 +    begin : we_1     
  51.338 +assign way_mem_we[0] = (refill_ready == `TRUE);
  51.339 +    end
  51.340 +    else
  51.341 +    begin : we_2
  51.342 +assign way_mem_we[0] = (refill_ready == `TRUE) && (refill_way_select[0] == `TRUE);
  51.343 +assign way_mem_we[1] = (refill_ready == `TRUE) && (refill_way_select[1] == `TRUE);
  51.344 +    end
  51.345 +endgenerate                     
  51.346 +
  51.347 +// On the last refill cycle set the valid bit, for all other writes it should be cleared
  51.348 +assign tmem_write_data[`LM32_IC_TAGS_VALID_RNG] = last_refill & !flushing;
  51.349 +assign tmem_write_data[`LM32_IC_TAGS_TAG_RNG] = refill_address[`LM32_IC_ADDR_TAG_RNG];
  51.350 +
  51.351 +// Signals that indicate which state we are in
  51.352 +assign flushing = |state[1:0];
  51.353 +assign check = state[2];
  51.354 +assign refill = state[3];
  51.355 +
  51.356 +assign miss = (~(|way_match)) && (read_enable_f == `TRUE) && (stall_f == `FALSE) && !(valid_d && branch_predict_taken_d);
  51.357 +assign stall_request = (check == `FALSE);
  51.358 +assign refill_request = (refill == `TRUE);
  51.359 +                      
  51.360 +/////////////////////////////////////////////////////
  51.361 +// Sequential logic
  51.362 +/////////////////////////////////////////////////////
  51.363 +
  51.364 +// Record way selected for replacement on a cache miss
  51.365 +generate
  51.366 +    if (associativity >= 2) 
  51.367 +    begin : way_select      
  51.368 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  51.369 +begin
  51.370 +    if (rst_i == `TRUE)
  51.371 +        refill_way_select <= {{associativity-1{1'b0}}, 1'b1};
  51.372 +    else
  51.373 +    begin        
  51.374 +        if (miss == `TRUE)
  51.375 +            refill_way_select <= {refill_way_select[0], refill_way_select[1]};
  51.376 +    end
  51.377 +end
  51.378 +    end
  51.379 +endgenerate
  51.380 +
  51.381 +// Record whether we are refilling
  51.382 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  51.383 +begin
  51.384 +    if (rst_i == `TRUE)
  51.385 +        refilling <= `FALSE;
  51.386 +    else
  51.387 +        refilling <= refill;
  51.388 +end
  51.389 +
  51.390 +// Instruction cache control FSM
  51.391 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  51.392 +begin
  51.393 +    if (rst_i == `TRUE)
  51.394 +    begin
  51.395 +        state <= `LM32_IC_STATE_FLUSH_INIT;
  51.396 +        flush_set <= {`LM32_IC_TMEM_ADDR_WIDTH{1'b1}};
  51.397 +        refill_address <= {`LM32_PC_WIDTH{1'bx}};
  51.398 +        restart_request <= `FALSE;
  51.399 +    end
  51.400 +    else 
  51.401 +    begin
  51.402 +        case (state)
  51.403 +
  51.404 +        // Flush the cache for the first time after reset
  51.405 +        `LM32_IC_STATE_FLUSH_INIT:
  51.406 +        begin            
  51.407 +            if (flush_set == {`LM32_IC_TMEM_ADDR_WIDTH{1'b0}})
  51.408 +                state <= `LM32_IC_STATE_CHECK;
  51.409 +            flush_set <= flush_set - 1'b1;
  51.410 +        end
  51.411 +
  51.412 +        // Flush the cache in response to an write to the ICC CSR
  51.413 +        `LM32_IC_STATE_FLUSH:
  51.414 +        begin            
  51.415 +            if (flush_set == {`LM32_IC_TMEM_ADDR_WIDTH{1'b0}})
  51.416 +`ifdef CFG_IROM_ENABLED
  51.417 +	      if (select_f)
  51.418 +                state <= `LM32_IC_STATE_REFILL;
  51.419 +	      else
  51.420 +`endif
  51.421 +		state <= `LM32_IC_STATE_CHECK;
  51.422 +	   
  51.423 +            flush_set <= flush_set - 1'b1;
  51.424 +        end
  51.425 +        
  51.426 +        // Check for cache misses
  51.427 +        `LM32_IC_STATE_CHECK:
  51.428 +        begin            
  51.429 +            if (stall_a == `FALSE)
  51.430 +                restart_request <= `FALSE;
  51.431 +            if (iflush == `TRUE)
  51.432 +            begin
  51.433 +                refill_address <= address_f;
  51.434 +                state <= `LM32_IC_STATE_FLUSH;
  51.435 +            end
  51.436 +            else if (miss == `TRUE)
  51.437 +            begin
  51.438 +                refill_address <= address_f;
  51.439 +                state <= `LM32_IC_STATE_REFILL;
  51.440 +            end
  51.441 +        end
  51.442 +
  51.443 +        // Refill a cache line
  51.444 +        `LM32_IC_STATE_REFILL:
  51.445 +        begin            
  51.446 +            if (refill_ready == `TRUE)
  51.447 +            begin
  51.448 +                if (last_refill == `TRUE)
  51.449 +                begin
  51.450 +                    restart_request <= `TRUE;
  51.451 +                    state <= `LM32_IC_STATE_CHECK;
  51.452 +                end
  51.453 +            end
  51.454 +        end
  51.455 +
  51.456 +        endcase        
  51.457 +    end
  51.458 +end
  51.459 +
  51.460 +generate 
  51.461 +    if (bytes_per_line > 4)
  51.462 +    begin
  51.463 +// Refill offset
  51.464 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  51.465 +begin
  51.466 +    if (rst_i == `TRUE)
  51.467 +        refill_offset <= {addr_offset_width{1'b0}};
  51.468 +    else 
  51.469 +    begin
  51.470 +        case (state)
  51.471 +        
  51.472 +        // Check for cache misses
  51.473 +        `LM32_IC_STATE_CHECK:
  51.474 +        begin            
  51.475 +            if (iflush == `TRUE)
  51.476 +                refill_offset <= {addr_offset_width{1'b0}};
  51.477 +            else if (miss == `TRUE)
  51.478 +                refill_offset <= {addr_offset_width{1'b0}};
  51.479 +        end
  51.480 +
  51.481 +        // Refill a cache line
  51.482 +        `LM32_IC_STATE_REFILL:
  51.483 +        begin            
  51.484 +            if (refill_ready == `TRUE)
  51.485 +                refill_offset <= refill_offset + 1'b1;
  51.486 +        end
  51.487 +
  51.488 +        endcase        
  51.489 +    end
  51.490 +end
  51.491 +    end
  51.492 +endgenerate
  51.493 +   
  51.494 +endmodule
  51.495 +
  51.496 +`endif
  51.497 +

    52.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    52.2 +++ b/rtl/lm32_include.v	Tue Mar 08 09:40:42 2011 +0000
    52.3 @@ -0,0 +1,368 @@
    52.4 +// =============================================================================
    52.5 +//                           COPYRIGHT NOTICE
    52.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation
    52.7 +// ALL RIGHTS RESERVED
    52.8 +// This confidential and proprietary software may be used only as authorised by
    52.9 +// a licensing agreement from Lattice Semiconductor Corporation.
   52.10 +// The entire notice above must be reproduced on all authorized copies and
   52.11 +// copies may only be made to the extent permitted by a licensing agreement from
   52.12 +// Lattice Semiconductor Corporation.
   52.13 +//
   52.14 +// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
   52.15 +// 5555 NE Moore Court                            408-826-6000 (other locations)
   52.16 +// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
   52.17 +// U.S.A                                   email: techsupport@latticesemi.com
   52.18 +// =============================================================================/
   52.19 +//                         FILE DETAILS
   52.20 +// Project          : LatticeMico32
   52.21 +// File             : lm32_include.v
   52.22 +// Title            : CPU global macros
   52.23 +// Version          : 6.1.17
   52.24 +//                  : Initial Release
   52.25 +// Version          : 7.0SP2, 3.0
   52.26 +//                  : No Change
   52.27 +// Version          : 3.1
   52.28 +//                  : No Change
   52.29 +// Version          : 3.2
   52.30 +//                  : No Change
   52.31 +// Version          : 3.3
   52.32 +//                  : Support for extended configuration register
   52.33 +// =============================================================================
   52.34 +
   52.35 +`ifdef LM32_INCLUDE_V
   52.36 +`else
   52.37 +`define LM32_INCLUDE_V
   52.38 +
   52.39 +//
   52.40 +// Common configuration options
   52.41 +//
   52.42 +
   52.43 +`define CFG_EBA_RESET 32'h00000000
   52.44 +`define CFG_DEBA_RESET 32'h10000000
   52.45 +
   52.46 +`define CFG_PL_MULTIPLY_ENABLED
   52.47 +`define CFG_PL_BARREL_SHIFT_ENABLED
   52.48 +`define CFG_SIGN_EXTEND_ENABLED
   52.49 +`define CFG_MC_DIVIDE_ENABLED
   52.50 +`define CFG_EBR_POSEDGE_REGISTER_FILE
   52.51 +
   52.52 +// [found by Milkymist dev'rs]
   52.53 +// Bug in Xst:
   52.54 +// CFG_ICACHE_ASSOCIATIVITY=2 => works in most cases (random crash on complex software)
   52.55 +// CFG_ICACHE_ASSOCIATIVITY=1 => disaster, CPU will not work at all
   52.56 +// Works 100% OK with expensive synthesizers.
   52.57 +`define CFG_ICACHE_ENABLED
   52.58 +`define CFG_ICACHE_ASSOCIATIVITY   1
   52.59 +`define CFG_ICACHE_SETS            256
   52.60 +`define CFG_ICACHE_BYTES_PER_LINE  16
   52.61 +`define CFG_ICACHE_BASE_ADDRESS    32'h0
   52.62 +`define CFG_ICACHE_LIMIT           32'h7FFF_FFFF
   52.63 +
   52.64 +`define CFG_DCACHE_ENABLED
   52.65 +`define CFG_DCACHE_ASSOCIATIVITY   1
   52.66 +`define CFG_DCACHE_SETS            256
   52.67 +`define CFG_DCACHE_BYTES_PER_LINE  16
   52.68 +`define CFG_DCACHE_BASE_ADDRESS    32'h0
   52.69 +`define CFG_DCACHE_LIMIT           32'h0FFF_FFFF
   52.70 +
   52.71 +// Enable Debugging
   52.72 +//`define CFG_JTAG_ENABLED
   52.73 +//`define CFG_JTAG_UART_ENABLED
   52.74 +//`define CFG_DEBUG_ENABLED
   52.75 +//`define CFG_HW_DEBUG_ENABLED
   52.76 +//`define CFG_ROM_DEBUG_ENABLED
   52.77 +//`define CFG_BREAKPOINTS 32'h0
   52.78 +//`define CFG_WATCHPOINTS 32'h0
   52.79 +
   52.80 +//
   52.81 +// End of common configuration options
   52.82 +//
   52.83 +
   52.84 +`ifdef TRUE
   52.85 +`else
   52.86 +`define TRUE    1'b1
   52.87 +`define FALSE   1'b0
   52.88 +`define TRUE_N  1'b0
   52.89 +`define FALSE_N 1'b1
   52.90 +`endif
   52.91 +
   52.92 +// Wishbone configuration
   52.93 +`define CFG_IWB_ENABLED
   52.94 +`define CFG_DWB_ENABLED
   52.95 +
   52.96 +// Data-path width
   52.97 +`define LM32_WORD_WIDTH                 32
   52.98 +`define LM32_WORD_RNG                   (`LM32_WORD_WIDTH-1):0
   52.99 +`define LM32_SHIFT_WIDTH                5
  52.100 +`define LM32_SHIFT_RNG                  (`LM32_SHIFT_WIDTH-1):0
  52.101 +`define LM32_BYTE_SELECT_WIDTH          4
  52.102 +`define LM32_BYTE_SELECT_RNG            (`LM32_BYTE_SELECT_WIDTH-1):0
  52.103 +
  52.104 +// Register file size
  52.105 +`define LM32_REGISTERS                  32
  52.106 +`define LM32_REG_IDX_WIDTH              5
  52.107 +`define LM32_REG_IDX_RNG                (`LM32_REG_IDX_WIDTH-1):0
  52.108 +
  52.109 +// Standard register numbers
  52.110 +`define LM32_RA_REG                     `LM32_REG_IDX_WIDTH'd29
  52.111 +`define LM32_EA_REG                     `LM32_REG_IDX_WIDTH'd30
  52.112 +`define LM32_BA_REG                     `LM32_REG_IDX_WIDTH'd31
  52.113 +
  52.114 +// Range of Program Counter. Two LSBs are always 0. 
  52.115 +// `ifdef CFG_ICACHE_ENABLED
  52.116 +// `define LM32_PC_WIDTH                   (clogb2(`CFG_ICACHE_LIMIT-`CFG_ICACHE_BASE_ADDRESS)-2)
  52.117 +// `else
  52.118 +// `ifdef CFG_IWB_ENABLED
  52.119 +`define LM32_PC_WIDTH                   (`LM32_WORD_WIDTH-2)
  52.120 +// `else
  52.121 +// `define LM32_PC_WIDTH                   `LM32_IROM_ADDRESS_WIDTH
  52.122 +// `endif
  52.123 +// `endif
  52.124 +`define LM32_PC_RNG                     (`LM32_PC_WIDTH+2-1):2
  52.125 +
  52.126 +// Range of an instruction
  52.127 +`define LM32_INSTRUCTION_WIDTH          32
  52.128 +`define LM32_INSTRUCTION_RNG            (`LM32_INSTRUCTION_WIDTH-1):0
  52.129 +
  52.130 +// Adder operation
  52.131 +`define LM32_ADDER_OP_ADD               1'b0
  52.132 +`define LM32_ADDER_OP_SUBTRACT          1'b1
  52.133 +
  52.134 +// Shift direction
  52.135 +`define LM32_SHIFT_OP_RIGHT             1'b0
  52.136 +`define LM32_SHIFT_OP_LEFT              1'b1
  52.137 +
  52.138 +// Bus errors
  52.139 +//`define CFG_BUS_ERRORS_ENABLED
  52.140 +
  52.141 +// Derive macro that indicates whether we have single-stepping or not
  52.142 +`ifdef CFG_ROM_DEBUG_ENABLED
  52.143 +`define LM32_SINGLE_STEP_ENABLED
  52.144 +`else
  52.145 +`ifdef CFG_HW_DEBUG_ENABLED
  52.146 +`define LM32_SINGLE_STEP_ENABLED
  52.147 +`endif
  52.148 +`endif
  52.149 +
  52.150 +// Derive macro that indicates whether JTAG interface is required
  52.151 +`ifdef CFG_JTAG_UART_ENABLED
  52.152 +`define LM32_JTAG_ENABLED
  52.153 +`else
  52.154 +`ifdef CFG_DEBUG_ENABLED
  52.155 +`define LM32_JTAG_ENABLED
  52.156 +`else
  52.157 +`endif
  52.158 +`endif
  52.159 +
  52.160 +// Derive macro that indicates whether we have a barrel-shifter or not
  52.161 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  52.162 +`define LM32_BARREL_SHIFT_ENABLED
  52.163 +`else // CFG_PL_BARREL_SHIFT_ENABLED
  52.164 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED
  52.165 +`define LM32_BARREL_SHIFT_ENABLED
  52.166 +`else
  52.167 +`define LM32_NO_BARREL_SHIFT
  52.168 +`endif
  52.169 +`endif // CFG_PL_BARREL_SHIFT_ENABLED
  52.170 +
  52.171 +// Derive macro that indicates whether we have a multiplier or not
  52.172 +`ifdef CFG_PL_MULTIPLY_ENABLED
  52.173 +`define LM32_MULTIPLY_ENABLED
  52.174 +`else
  52.175 +`ifdef CFG_MC_MULTIPLY_ENABLED
  52.176 +`define LM32_MULTIPLY_ENABLED
  52.177 +`endif
  52.178 +`endif
  52.179 +
  52.180 +// Derive a macro that indicates whether or not the multi-cycle arithmetic unit is required
  52.181 +`ifdef CFG_MC_DIVIDE_ENABLED
  52.182 +`define LM32_MC_ARITHMETIC_ENABLED
  52.183 +`endif
  52.184 +`ifdef CFG_MC_MULTIPLY_ENABLED
  52.185 +`define LM32_MC_ARITHMETIC_ENABLED
  52.186 +`endif
  52.187 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED
  52.188 +`define LM32_MC_ARITHMETIC_ENABLED
  52.189 +`endif
  52.190 +
  52.191 +// Derive macro that indicates if we are using an EBR register file
  52.192 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
  52.193 +`define LM32_EBR_REGISTER_FILE
  52.194 +`endif
  52.195 +`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
  52.196 +`define LM32_EBR_REGISTER_FILE
  52.197 +`endif
  52.198 +
  52.199 +// Revision number
  52.200 +`define LM32_REVISION                   6'h02
  52.201 +
  52.202 +// Logical operations - Function encoded directly in instruction
  52.203 +`define LM32_LOGIC_OP_RNG               3:0
  52.204 +
  52.205 +// Conditions for conditional branches
  52.206 +`define LM32_CONDITION_WIDTH            3
  52.207 +`define LM32_CONDITION_RNG              (`LM32_CONDITION_WIDTH-1):0
  52.208 +`define LM32_CONDITION_E                3'b001
  52.209 +`define LM32_CONDITION_G                3'b010
  52.210 +`define LM32_CONDITION_GE               3'b011
  52.211 +`define LM32_CONDITION_GEU              3'b100
  52.212 +`define LM32_CONDITION_GU               3'b101
  52.213 +`define LM32_CONDITION_NE               3'b111
  52.214 +`define LM32_CONDITION_U1               3'b000
  52.215 +`define LM32_CONDITION_U2               3'b110
  52.216 +
  52.217 +// Size of load or store instruction - Encoding corresponds to opcode
  52.218 +`define LM32_SIZE_WIDTH                 2
  52.219 +`define LM32_SIZE_RNG                   1:0
  52.220 +`define LM32_SIZE_BYTE                  2'b00
  52.221 +`define LM32_SIZE_HWORD                 2'b11
  52.222 +`define LM32_SIZE_WORD                  2'b10
  52.223 +`define LM32_ADDRESS_LSBS_WIDTH         2
  52.224 +
  52.225 +// Width and range of a CSR index
  52.226 +`ifdef CFG_DEBUG_ENABLED
  52.227 +`define LM32_CSR_WIDTH                  5
  52.228 +`define LM32_CSR_RNG                    (`LM32_CSR_WIDTH-1):0
  52.229 +`else
  52.230 +`ifdef CFG_JTAG_ENABLED
  52.231 +`define LM32_CSR_WIDTH                  4
  52.232 +`define LM32_CSR_RNG                    (`LM32_CSR_WIDTH-1):0
  52.233 +`else
  52.234 +`define LM32_CSR_WIDTH                  3
  52.235 +`define LM32_CSR_RNG                    (`LM32_CSR_WIDTH-1):0
  52.236 +`endif
  52.237 +`endif
  52.238 +
  52.239 +// CSR indices
  52.240 +`define LM32_CSR_IE                     `LM32_CSR_WIDTH'h0
  52.241 +`define LM32_CSR_IM                     `LM32_CSR_WIDTH'h1
  52.242 +`define LM32_CSR_IP                     `LM32_CSR_WIDTH'h2
  52.243 +`define LM32_CSR_ICC                    `LM32_CSR_WIDTH'h3
  52.244 +`define LM32_CSR_DCC                    `LM32_CSR_WIDTH'h4
  52.245 +`define LM32_CSR_CC                     `LM32_CSR_WIDTH'h5
  52.246 +`define LM32_CSR_CFG                    `LM32_CSR_WIDTH'h6
  52.247 +`define LM32_CSR_EBA                    `LM32_CSR_WIDTH'h7
  52.248 +`ifdef CFG_DEBUG_ENABLED
  52.249 +`define LM32_CSR_DC                     `LM32_CSR_WIDTH'h8
  52.250 +`define LM32_CSR_DEBA                   `LM32_CSR_WIDTH'h9
  52.251 +`endif
  52.252 +`define LM32_CSR_CFG2                   `LM32_CSR_WIDTH'ha
  52.253 +`ifdef CFG_JTAG_ENABLED
  52.254 +`define LM32_CSR_JTX                    `LM32_CSR_WIDTH'he
  52.255 +`define LM32_CSR_JRX                    `LM32_CSR_WIDTH'hf
  52.256 +`endif
  52.257 +`ifdef CFG_DEBUG_ENABLED
  52.258 +`define LM32_CSR_BP0                    `LM32_CSR_WIDTH'h10
  52.259 +`define LM32_CSR_BP1                    `LM32_CSR_WIDTH'h11
  52.260 +`define LM32_CSR_BP2                    `LM32_CSR_WIDTH'h12
  52.261 +`define LM32_CSR_BP3                    `LM32_CSR_WIDTH'h13
  52.262 +`define LM32_CSR_WP0                    `LM32_CSR_WIDTH'h18
  52.263 +`define LM32_CSR_WP1                    `LM32_CSR_WIDTH'h19
  52.264 +`define LM32_CSR_WP2                    `LM32_CSR_WIDTH'h1a
  52.265 +`define LM32_CSR_WP3                    `LM32_CSR_WIDTH'h1b
  52.266 +`endif 
  52.267 +
  52.268 +// Values for WPC CSR
  52.269 +`define LM32_WPC_C_RNG                  1:0
  52.270 +`define LM32_WPC_C_DISABLED             2'b00
  52.271 +`define LM32_WPC_C_READ                 2'b01
  52.272 +`define LM32_WPC_C_WRITE                2'b10
  52.273 +`define LM32_WPC_C_READ_WRITE           2'b11
  52.274 +
  52.275 +// Exception IDs
  52.276 +`define LM32_EID_WIDTH                  3
  52.277 +`define LM32_EID_RNG                    (`LM32_EID_WIDTH-1):0
  52.278 +`define LM32_EID_RESET                  3'h0
  52.279 +`define LM32_EID_BREAKPOINT             3'd1
  52.280 +`define LM32_EID_INST_BUS_ERROR         3'h2
  52.281 +`define LM32_EID_WATCHPOINT             3'd3
  52.282 +`define LM32_EID_DATA_BUS_ERROR         3'h4
  52.283 +`define LM32_EID_DIVIDE_BY_ZERO         3'h5
  52.284 +`define LM32_EID_INTERRUPT              3'h6
  52.285 +`define LM32_EID_SCALL                  3'h7
  52.286 +
  52.287 +// Pipeline result selection mux controls
  52.288 +
  52.289 +`define LM32_D_RESULT_SEL_0_RNG          0:0
  52.290 +`define LM32_D_RESULT_SEL_0_REG_0        1'b0
  52.291 +`define LM32_D_RESULT_SEL_0_NEXT_PC      1'b1
  52.292 +
  52.293 +`define LM32_D_RESULT_SEL_1_RNG          1:0
  52.294 +`define LM32_D_RESULT_SEL_1_ZERO         2'b00
  52.295 +`define LM32_D_RESULT_SEL_1_REG_1        2'b01
  52.296 +`define LM32_D_RESULT_SEL_1_IMMEDIATE    2'b10
  52.297 +
  52.298 +`define LM32_USER_OPCODE_WIDTH           11
  52.299 +`define LM32_USER_OPCODE_RNG             (`LM32_USER_OPCODE_WIDTH-1):0
  52.300 +
  52.301 +// Derive a macro to indicate if either of the caches are implemented
  52.302 +`ifdef CFG_ICACHE_ENABLED
  52.303 +`define LM32_CACHE_ENABLED      
  52.304 +`else
  52.305 +`ifdef CFG_DCACHE_ENABLED
  52.306 +`define LM32_CACHE_ENABLED
  52.307 +`endif
  52.308 +`endif
  52.309 +
  52.310 +/////////////////////////////////////////////////////
  52.311 +// Interrupts
  52.312 +/////////////////////////////////////////////////////
  52.313 +
  52.314 +// Always enable interrupts
  52.315 +`define CFG_INTERRUPTS_ENABLED
  52.316 +
  52.317 +// Currently this is fixed to 32 and should not be changed
  52.318 +`define CFG_INTERRUPTS                  32
  52.319 +`define LM32_INTERRUPT_WIDTH            `CFG_INTERRUPTS
  52.320 +`define LM32_INTERRUPT_RNG              (`LM32_INTERRUPT_WIDTH-1):0
  52.321 +
  52.322 +/////////////////////////////////////////////////////
  52.323 +// General
  52.324 +/////////////////////////////////////////////////////
  52.325 +
  52.326 +// Sub-word range types
  52.327 +`define LM32_BYTE_WIDTH                 8
  52.328 +`define LM32_BYTE_RNG                   7:0
  52.329 +`define LM32_HWORD_WIDTH                16
  52.330 +`define LM32_HWORD_RNG                  15:0
  52.331 +
  52.332 +// Word sub-byte indicies
  52.333 +`define LM32_BYTE_0_RNG                  7:0
  52.334 +`define LM32_BYTE_1_RNG                  15:8
  52.335 +`define LM32_BYTE_2_RNG                  23:16
  52.336 +`define LM32_BYTE_3_RNG                  31:24
  52.337 +
  52.338 +// Word sub-halfword indices
  52.339 +`define LM32_HWORD_0_RNG                 15:0
  52.340 +`define LM32_HWORD_1_RNG                 31:16
  52.341 +
  52.342 +// Use an asynchronous reset
  52.343 +// To use a synchronous reset, define this macro as nothing
  52.344 +//`define CFG_RESET_SENSITIVITY or posedge rst_i
  52.345 +`define CFG_RESET_SENSITIVITY
  52.346 +
  52.347 +// Whether to include context registers for debug exceptions
  52.348 +// in addition to standard exception handling registers
  52.349 +`define CFG_DEBUG_EXCEPTIONS_ENABLED
  52.350 +
  52.351 +// Wishbone defines
  52.352 +// Refer to Wishbone System-on-Chip Interconnection Architecture
  52.353 +// These should probably be moved to a Wishbone common file
  52.354 +
  52.355 +// Wishbone cycle types
  52.356 +`define LM32_CTYPE_WIDTH                3
  52.357 +`define LM32_CTYPE_RNG                  (`LM32_CTYPE_WIDTH-1):0
  52.358 +`define LM32_CTYPE_CLASSIC              3'b000
  52.359 +`define LM32_CTYPE_CONSTANT             3'b001
  52.360 +`define LM32_CTYPE_INCREMENTING         3'b010
  52.361 +`define LM32_CTYPE_END                  3'b111
  52.362 +
  52.363 +// Wishbone burst types
  52.364 +`define LM32_BTYPE_WIDTH                2
  52.365 +`define LM32_BTYPE_RNG                  (`LM32_BTYPE_WIDTH-1):0
  52.366 +`define LM32_BTYPE_LINEAR               2'b00
  52.367 +`define LM32_BTYPE_4_BEAT               2'b01
  52.368 +`define LM32_BTYPE_8_BEAT               2'b10
  52.369 +`define LM32_BTYPE_16_BEAT              2'b11
  52.370 +
  52.371 +`endif

    53.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    53.2 +++ b/rtl/lm32_instruction_unit.v	Tue Mar 08 09:40:42 2011 +0000
    53.3 @@ -0,0 +1,839 @@
    53.4 +// =============================================================================
    53.5 +//                           COPYRIGHT NOTICE
    53.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation
    53.7 +// ALL RIGHTS RESERVED
    53.8 +// This confidential and proprietary software may be used only as authorised by
    53.9 +// a licensing agreement from Lattice Semiconductor Corporation.
   53.10 +// The entire notice above must be reproduced on all authorized copies and
   53.11 +// copies may only be made to the extent permitted by a licensing agreement from
   53.12 +// Lattice Semiconductor Corporation.
   53.13 +//
   53.14 +// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
   53.15 +// 5555 NE Moore Court                            408-826-6000 (other locations)
   53.16 +// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
   53.17 +// U.S.A                                   email: techsupport@latticesemi.com
   53.18 +// =============================================================================/
   53.19 +//                         FILE DETAILS
   53.20 +// Project      : LatticeMico32
   53.21 +// File         : lm32_instruction_unit.v
   53.22 +// Title        : Instruction unit
   53.23 +// Dependencies : lm32_include.v
   53.24 +// Version      : 6.1.17
   53.25 +//              : Initial Release
   53.26 +// Version      : 7.0SP2, 3.0
   53.27 +//              : No Change
   53.28 +// Version      : 3.1
   53.29 +//              : Support for static branch prediction is added. Fetching of
   53.30 +//              : instructions can also be altered by branches predicted in D
   53.31 +//              : stage of pipeline, and mispredicted branches in the X and M 
   53.32 +//              : stages of the pipeline.
   53.33 +// Version      : 3.2
   53.34 +//              : EBRs use SYNC resets instead of ASYNC resets.
   53.35 +// Version      : 3.3
   53.36 +//              : Support for a non-cacheable Instruction Memory that has a 
   53.37 +//              : single-cycle access latency. This memory can be accessed by
   53.38 +//              : data port of LM32 (so that debugger has access to it).
   53.39 +// Version      : 3.4
   53.40 +//              : No change
   53.41 +// Version      : 3.5
   53.42 +//              : Bug fix: Inline memory is correctly generated if it is not a
   53.43 +//              : power-of-two.
   53.44 +//              : Bug fix: Fixed a bug that caused LM32 (configured without
   53.45 +//              : instruction cache) to lock up in to an infinite loop due to a 
   53.46 +//              : instruction bus error when EBA was set to instruction inline
   53.47 +//              : memory.
   53.48 +// =============================================================================
   53.49 +
   53.50 +`include "lm32_include.v"
   53.51 +
   53.52 +/////////////////////////////////////////////////////
   53.53 +// Module interface
   53.54 +/////////////////////////////////////////////////////
   53.55 +
   53.56 +module lm32_instruction_unit (
   53.57 +    // ----- Inputs -------
   53.58 +    clk_i,
   53.59 +    rst_i,
   53.60 +    // From pipeline
   53.61 +    stall_a,
   53.62 +    stall_f,
   53.63 +    stall_d,
   53.64 +    stall_x,
   53.65 +    stall_m,
   53.66 +    valid_f,
   53.67 +    valid_d,
   53.68 +    kill_f,
   53.69 +    branch_predict_taken_d,
   53.70 +    branch_predict_address_d,
   53.71 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
   53.72 +    branch_taken_x,
   53.73 +    branch_target_x,
   53.74 +`endif
   53.75 +    exception_m,
   53.76 +    branch_taken_m,
   53.77 +    branch_mispredict_taken_m,
   53.78 +    branch_target_m,
   53.79 +`ifdef CFG_ICACHE_ENABLED
   53.80 +    iflush,
   53.81 +`endif
   53.82 +`ifdef CFG_DCACHE_ENABLED
   53.83 +    dcache_restart_request,
   53.84 +    dcache_refill_request,
   53.85 +    dcache_refilling,
   53.86 +`endif        
   53.87 +`ifdef CFG_IROM_ENABLED
   53.88 +    irom_store_data_m,
   53.89 +    irom_address_xm,
   53.90 +    irom_we_xm,
   53.91 +`endif
   53.92 +`ifdef CFG_IWB_ENABLED
   53.93 +    // From Wishbone
   53.94 +    i_dat_i,
   53.95 +    i_ack_i,
   53.96 +    i_err_i,
   53.97 +`endif
   53.98 +`ifdef CFG_HW_DEBUG_ENABLED
   53.99 +    jtag_read_enable,
  53.100 +    jtag_write_enable,
  53.101 +    jtag_write_data,
  53.102 +    jtag_address,
  53.103 +`endif
  53.104 +    // ----- Outputs -------
  53.105 +    // To pipeline
  53.106 +    pc_f,
  53.107 +    pc_d,
  53.108 +    pc_x,
  53.109 +    pc_m,
  53.110 +    pc_w,
  53.111 +`ifdef CFG_ICACHE_ENABLED
  53.112 +    icache_stall_request,
  53.113 +    icache_restart_request,
  53.114 +    icache_refill_request,
  53.115 +    icache_refilling,
  53.116 +`endif
  53.117 +`ifdef CFG_IROM_ENABLED
  53.118 +    irom_data_m,
  53.119 +`endif
  53.120 +`ifdef CFG_IWB_ENABLED
  53.121 +    // To Wishbone
  53.122 +    i_dat_o,
  53.123 +    i_adr_o,
  53.124 +    i_cyc_o,
  53.125 +    i_sel_o,
  53.126 +    i_stb_o,
  53.127 +    i_we_o,
  53.128 +    i_cti_o,
  53.129 +    i_lock_o,
  53.130 +    i_bte_o,
  53.131 +`endif
  53.132 +`ifdef CFG_HW_DEBUG_ENABLED
  53.133 +    jtag_read_data,
  53.134 +    jtag_access_complete,
  53.135 +`endif
  53.136 +`ifdef CFG_BUS_ERRORS_ENABLED
  53.137 +    bus_error_d,
  53.138 +`endif
  53.139 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
  53.140 +    instruction_f,
  53.141 +`endif    
  53.142 +    instruction_d
  53.143 +    );
  53.144 +
  53.145 +/////////////////////////////////////////////////////
  53.146 +// Parameters
  53.147 +/////////////////////////////////////////////////////
  53.148 +
  53.149 +parameter associativity = 1;                            // Associativity of the cache (Number of ways)
  53.150 +parameter sets = 512;                                   // Number of sets
  53.151 +parameter bytes_per_line = 16;                          // Number of bytes per cache line
  53.152 +parameter base_address = 0;                             // Base address of cachable memory
  53.153 +parameter limit = 0;                                    // Limit (highest address) of cachable memory
  53.154 +
  53.155 +// For bytes_per_line == 4, we set 1 so part-select range isn't reversed, even though not really used 
  53.156 +localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2;
  53.157 +localparam addr_offset_lsb = 2;
  53.158 +localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
  53.159 +
  53.160 +/////////////////////////////////////////////////////
  53.161 +// Inputs
  53.162 +/////////////////////////////////////////////////////
  53.163 +
  53.164 +input clk_i;                                            // Clock
  53.165 +input rst_i;                                            // Reset
  53.166 +
  53.167 +input stall_a;                                          // Stall A stage instruction
  53.168 +input stall_f;                                          // Stall F stage instruction
  53.169 +input stall_d;                                          // Stall D stage instruction
  53.170 +input stall_x;                                          // Stall X stage instruction
  53.171 +input stall_m;                                          // Stall M stage instruction
  53.172 +input valid_f;                                          // Instruction in F stage is valid
  53.173 +input valid_d;                                          // Instruction in D stage is valid
  53.174 +input kill_f;                                           // Kill instruction in F stage
  53.175 +
  53.176 +input branch_predict_taken_d;                           // Branch is predicted taken in D stage
  53.177 +input [`LM32_PC_RNG] branch_predict_address_d;          // Branch target address
  53.178 +   
  53.179 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
  53.180 +input branch_taken_x;                                   // Branch instruction in X stage is taken
  53.181 +input [`LM32_PC_RNG] branch_target_x;                   // Target PC of X stage branch instruction
  53.182 +`endif
  53.183 +input exception_m;
  53.184 +input branch_taken_m;                                   // Branch instruction in M stage is taken
  53.185 +input branch_mispredict_taken_m;                        // Branch instruction in M stage is mispredicted as taken
  53.186 +input [`LM32_PC_RNG] branch_target_m;                   // Target PC of M stage branch instruction
  53.187 +
  53.188 +`ifdef CFG_ICACHE_ENABLED
  53.189 +input iflush;                                           // Flush instruction cache
  53.190 +`endif
  53.191 +`ifdef CFG_DCACHE_ENABLED
  53.192 +input dcache_restart_request;                           // Restart instruction that caused a data cache miss
  53.193 +input dcache_refill_request;                            // Request to refill data cache
  53.194 +input dcache_refilling;
  53.195 +`endif        
  53.196 +
  53.197 +`ifdef CFG_IROM_ENABLED
  53.198 +input [`LM32_WORD_RNG] irom_store_data_m;               // Data from load-store unit
  53.199 +input [`LM32_WORD_RNG] irom_address_xm;                 // Address from load-store unit
  53.200 +input irom_we_xm;                                       // Indicates if memory operation is load or store
  53.201 +`endif
  53.202 +
  53.203 +`ifdef CFG_IWB_ENABLED
  53.204 +input [`LM32_WORD_RNG] i_dat_i;                         // Instruction Wishbone interface read data
  53.205 +input i_ack_i;                                          // Instruction Wishbone interface acknowledgement
  53.206 +input i_err_i;                                          // Instruction Wishbone interface error
  53.207 +`endif
  53.208 +
  53.209 +`ifdef CFG_HW_DEBUG_ENABLED
  53.210 +input jtag_read_enable;                                 // JTAG read memory request
  53.211 +input jtag_write_enable;                                // JTAG write memory request
  53.212 +input [`LM32_BYTE_RNG] jtag_write_data;                 // JTAG wrirte data
  53.213 +input [`LM32_WORD_RNG] jtag_address;                    // JTAG read/write address
  53.214 +`endif
  53.215 +
  53.216 +/////////////////////////////////////////////////////
  53.217 +// Outputs
  53.218 +/////////////////////////////////////////////////////
  53.219 +        
  53.220 +output [`LM32_PC_RNG] pc_f;                             // F stage PC
  53.221 +reg    [`LM32_PC_RNG] pc_f;
  53.222 +output [`LM32_PC_RNG] pc_d;                             // D stage PC
  53.223 +reg    [`LM32_PC_RNG] pc_d;
  53.224 +output [`LM32_PC_RNG] pc_x;                             // X stage PC
  53.225 +reg    [`LM32_PC_RNG] pc_x;
  53.226 +output [`LM32_PC_RNG] pc_m;                             // M stage PC
  53.227 +reg    [`LM32_PC_RNG] pc_m;
  53.228 +output [`LM32_PC_RNG] pc_w;                             // W stage PC
  53.229 +reg    [`LM32_PC_RNG] pc_w;
  53.230 +
  53.231 +`ifdef CFG_ICACHE_ENABLED
  53.232 +output icache_stall_request;                            // Instruction cache stall request
  53.233 +wire   icache_stall_request;
  53.234 +output icache_restart_request;                          // Request to restart instruction that cached instruction cache miss
  53.235 +wire   icache_restart_request;
  53.236 +output icache_refill_request;                           // Instruction cache refill request
  53.237 +wire   icache_refill_request;
  53.238 +output icache_refilling;                                // Indicates the icache is refilling
  53.239 +wire   icache_refilling;
  53.240 +`endif
  53.241 +
  53.242 +`ifdef CFG_IROM_ENABLED
  53.243 +output [`LM32_WORD_RNG] irom_data_m;                    // Data to load-store unit on load
  53.244 +wire   [`LM32_WORD_RNG] irom_data_m;                      
  53.245 +`endif   
  53.246 +
  53.247 +`ifdef CFG_IWB_ENABLED
  53.248 +output [`LM32_WORD_RNG] i_dat_o;                        // Instruction Wishbone interface write data
  53.249 +`ifdef CFG_HW_DEBUG_ENABLED
  53.250 +reg    [`LM32_WORD_RNG] i_dat_o;
  53.251 +`else
  53.252 +wire   [`LM32_WORD_RNG] i_dat_o;
  53.253 +`endif
  53.254 +output [`LM32_WORD_RNG] i_adr_o;                        // Instruction Wishbone interface address
  53.255 +reg    [`LM32_WORD_RNG] i_adr_o;
  53.256 +output i_cyc_o;                                         // Instruction Wishbone interface cycle
  53.257 +reg    i_cyc_o; 
  53.258 +output [`LM32_BYTE_SELECT_RNG] i_sel_o;                 // Instruction Wishbone interface byte select
  53.259 +`ifdef CFG_HW_DEBUG_ENABLED
  53.260 +reg    [`LM32_BYTE_SELECT_RNG] i_sel_o;
  53.261 +`else
  53.262 +wire   [`LM32_BYTE_SELECT_RNG] i_sel_o;
  53.263 +`endif
  53.264 +output i_stb_o;                                         // Instruction Wishbone interface strobe
  53.265 +reg    i_stb_o;
  53.266 +output i_we_o;                                          // Instruction Wishbone interface write enable
  53.267 +`ifdef CFG_HW_DEBUG_ENABLED
  53.268 +reg    i_we_o;
  53.269 +`else
  53.270 +wire   i_we_o;
  53.271 +`endif
  53.272 +output [`LM32_CTYPE_RNG] i_cti_o;                       // Instruction Wishbone interface cycle type 
  53.273 +reg    [`LM32_CTYPE_RNG] i_cti_o;
  53.274 +output i_lock_o;                                        // Instruction Wishbone interface lock bus
  53.275 +reg    i_lock_o;
  53.276 +output [`LM32_BTYPE_RNG] i_bte_o;                       // Instruction Wishbone interface burst type 
  53.277 +wire   [`LM32_BTYPE_RNG] i_bte_o;
  53.278 +`endif
  53.279 +
  53.280 +`ifdef CFG_HW_DEBUG_ENABLED
  53.281 +output [`LM32_BYTE_RNG] jtag_read_data;                 // Data read for JTAG interface
  53.282 +reg    [`LM32_BYTE_RNG] jtag_read_data;
  53.283 +output jtag_access_complete;                            // Requested memory access by JTAG interface is complete
  53.284 +wire   jtag_access_complete;
  53.285 +`endif
  53.286 +
  53.287 +`ifdef CFG_BUS_ERRORS_ENABLED
  53.288 +output bus_error_d;                                     // Indicates a bus error occured while fetching the instruction
  53.289 +reg    bus_error_d;
  53.290 +`endif
  53.291 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
  53.292 +output [`LM32_INSTRUCTION_RNG] instruction_f;           // F stage instruction (only to have register indices extracted from)
  53.293 +wire   [`LM32_INSTRUCTION_RNG] instruction_f;
  53.294 +`endif
  53.295 +output [`LM32_INSTRUCTION_RNG] instruction_d;           // D stage instruction to be decoded
  53.296 +reg    [`LM32_INSTRUCTION_RNG] instruction_d;
  53.297 +
  53.298 +/////////////////////////////////////////////////////
  53.299 +// Internal nets and registers 
  53.300 +/////////////////////////////////////////////////////
  53.301 +
  53.302 +reg [`LM32_PC_RNG] pc_a;                                // A stage PC
  53.303 +
  53.304 +`ifdef LM32_CACHE_ENABLED
  53.305 +reg [`LM32_PC_RNG] restart_address;                     // Address to restart from after a cache miss  
  53.306 +`endif
  53.307 +
  53.308 +`ifdef CFG_ICACHE_ENABLED
  53.309 +wire icache_read_enable_f;                              // Indicates if instruction cache miss is valid
  53.310 +wire [`LM32_PC_RNG] icache_refill_address;              // Address that caused cache miss
  53.311 +reg icache_refill_ready;                                // Indicates when next word of refill data is ready to be written to cache
  53.312 +reg [`LM32_INSTRUCTION_RNG] icache_refill_data;         // Next word of refill data, fetched from Wishbone
  53.313 +wire [`LM32_INSTRUCTION_RNG] icache_data_f;             // Instruction fetched from instruction cache
  53.314 +wire [`LM32_CTYPE_RNG] first_cycle_type;                // First Wishbone cycle type
  53.315 +wire [`LM32_CTYPE_RNG] next_cycle_type;                 // Next Wishbone cycle type
  53.316 +wire last_word;                                         // Indicates if this is the last word in the cache line
  53.317 +wire [`LM32_PC_RNG] first_address;                      // First cache refill address
  53.318 +`else
  53.319 +`ifdef CFG_IWB_ENABLED
  53.320 +reg [`LM32_INSTRUCTION_RNG] wb_data_f;                  // Instruction fetched from Wishbone
  53.321 +`endif
  53.322 +`endif
  53.323 +`ifdef CFG_IROM_ENABLED
  53.324 +wire irom_select_a;                                     // Indicates if A stage PC maps to a ROM address
  53.325 +reg irom_select_f;                                      // Indicates if F stage PC maps to a ROM address
  53.326 +wire [`LM32_INSTRUCTION_RNG] irom_data_f;               // Instruction fetched from ROM
  53.327 +`endif
  53.328 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
  53.329 +`else
  53.330 +wire [`LM32_INSTRUCTION_RNG] instruction_f;             // F stage instruction
  53.331 +`endif
  53.332 +`ifdef CFG_BUS_ERRORS_ENABLED
  53.333 +reg bus_error_f;                                        // Indicates if a bus error occured while fetching the instruction in the F stage
  53.334 +`endif
  53.335 +
  53.336 +`ifdef CFG_HW_DEBUG_ENABLED
  53.337 +reg jtag_access;                                        // Indicates if a JTAG WB access is in progress
  53.338 +`endif
  53.339 +
  53.340 +/////////////////////////////////////////////////////
  53.341 +// Functions
  53.342 +/////////////////////////////////////////////////////
  53.343 +
  53.344 +`include "lm32_functions.v"
  53.345 +
  53.346 +/////////////////////////////////////////////////////
  53.347 +// Instantiations
  53.348 +/////////////////////////////////////////////////////
  53.349 +
  53.350 +// Instruction ROM
  53.351 +`ifdef CFG_IROM_ENABLED  
  53.352 +   pmi_ram_dp_true 
  53.353 +     #(
  53.354 +       // ----- Parameters -------
  53.355 +       .pmi_family             (`LATTICE_FAMILY),
  53.356 +	 
  53.357 +       //.pmi_addr_depth_a       (1 << (clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)),
  53.358 +       //.pmi_addr_width_a       ((clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)),
  53.359 +       //.pmi_data_width_a       (`LM32_WORD_WIDTH),
  53.360 +       //.pmi_addr_depth_b       (1 << (clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)),
  53.361 +       //.pmi_addr_width_b       ((clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)),
  53.362 +       //.pmi_data_width_b       (`LM32_WORD_WIDTH),
  53.363 +	 
  53.364 +       .pmi_addr_depth_a       (`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1),
  53.365 +       .pmi_addr_width_a       (clogb2_v1(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
  53.366 +       .pmi_data_width_a       (`LM32_WORD_WIDTH),
  53.367 +       .pmi_addr_depth_b       (`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1),
  53.368 +       .pmi_addr_width_b       (clogb2_v1(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
  53.369 +       .pmi_data_width_b       (`LM32_WORD_WIDTH),
  53.370 +	 
  53.371 +       .pmi_regmode_a          ("noreg"),
  53.372 +       .pmi_regmode_b          ("noreg"),
  53.373 +       .pmi_gsr                ("enable"),
  53.374 +       .pmi_resetmode          ("sync"),
  53.375 +       .pmi_init_file          (`CFG_IROM_INIT_FILE),
  53.376 +       .pmi_init_file_format   (`CFG_IROM_INIT_FILE_FORMAT),
  53.377 +       .module_type            ("pmi_ram_dp_true")
  53.378 +       ) 
  53.379 +       ram (
  53.380 +	    // ----- Inputs -------
  53.381 +	    .ClockA                 (clk_i),
  53.382 +	    .ClockB                 (clk_i),
  53.383 +	    .ResetA                 (rst_i),
  53.384 +	    .ResetB                 (rst_i),
  53.385 +	    .DataInA                ({32{1'b0}}),
  53.386 +	    .DataInB                (irom_store_data_m),
  53.387 +	    .AddressA               (pc_a[(clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)+2-1:2]),
  53.388 +	    .AddressB               (irom_address_xm[(clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)+2-1:2]),
  53.389 +	    .ClockEnA               (!stall_a),
  53.390 +	    .ClockEnB               (!stall_x || !stall_m),
  53.391 +	    .WrA                    (`FALSE),
  53.392 +	    .WrB                    (irom_we_xm), 
  53.393 +	    // ----- Outputs -------
  53.394 +	    .QA                     (irom_data_f),
  53.395 +	    .QB                     (irom_data_m)
  53.396 +	    );
  53.397 +`endif    
  53.398 + 
  53.399 +`ifdef CFG_ICACHE_ENABLED
  53.400 +// Instruction cache
  53.401 +lm32_icache #(
  53.402 +    .associativity          (associativity),
  53.403 +    .sets                   (sets),
  53.404 +    .bytes_per_line         (bytes_per_line),
  53.405 +    .base_address           (base_address),
  53.406 +    .limit                  (limit)
  53.407 +    ) icache ( 
  53.408 +    // ----- Inputs -----
  53.409 +    .clk_i                  (clk_i),
  53.410 +    .rst_i                  (rst_i),      
  53.411 +    .stall_a                (stall_a),
  53.412 +    .stall_f                (stall_f),
  53.413 +    .branch_predict_taken_d (branch_predict_taken_d),
  53.414 +    .valid_d                (valid_d),
  53.415 +    .address_a              (pc_a),
  53.416 +    .address_f              (pc_f),
  53.417 +    .read_enable_f          (icache_read_enable_f),
  53.418 +    .refill_ready           (icache_refill_ready),
  53.419 +    .refill_data            (icache_refill_data),
  53.420 +    .iflush                 (iflush),
  53.421 +    // ----- Outputs -----
  53.422 +    .stall_request          (icache_stall_request),
  53.423 +    .restart_request        (icache_restart_request),
  53.424 +    .refill_request         (icache_refill_request),
  53.425 +    .refill_address         (icache_refill_address),
  53.426 +    .refilling              (icache_refilling),
  53.427 +    .inst                   (icache_data_f)
  53.428 +    );
  53.429 +`endif
  53.430 +
  53.431 +/////////////////////////////////////////////////////
  53.432 +// Combinational Logic
  53.433 +/////////////////////////////////////////////////////
  53.434 +
  53.435 +`ifdef CFG_ICACHE_ENABLED
  53.436 +// Generate signal that indicates when instruction cache misses are valid
  53.437 +assign icache_read_enable_f =    (valid_f == `TRUE)
  53.438 +                              && (kill_f == `FALSE)
  53.439 +`ifdef CFG_DCACHE_ENABLED
  53.440 +                              && (dcache_restart_request == `FALSE)
  53.441 +`endif                         
  53.442 +`ifdef CFG_IROM_ENABLED 
  53.443 +                              && (irom_select_f == `FALSE)
  53.444 +`endif       
  53.445 +                              ;
  53.446 +`endif
  53.447 +
  53.448 +// Compute address of next instruction to fetch
  53.449 +always @(*)
  53.450 +begin
  53.451 +    // The request from the latest pipeline stage must take priority
  53.452 +`ifdef CFG_DCACHE_ENABLED
  53.453 +    if (dcache_restart_request == `TRUE)
  53.454 +        pc_a = restart_address;
  53.455 +    else 
  53.456 +`endif    
  53.457 +      if (branch_taken_m == `TRUE)
  53.458 +	if ((branch_mispredict_taken_m == `TRUE) && (exception_m == `FALSE))
  53.459 +	  pc_a = pc_x;
  53.460 +	else
  53.461 +          pc_a = branch_target_m;
  53.462 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
  53.463 +      else if (branch_taken_x == `TRUE)
  53.464 +        pc_a = branch_target_x;
  53.465 +`endif
  53.466 +      else
  53.467 +	if ( (valid_d == `TRUE) && (branch_predict_taken_d == `TRUE) )
  53.468 +	  pc_a = branch_predict_address_d;
  53.469 +	else
  53.470 +`ifdef CFG_ICACHE_ENABLED
  53.471 +          if (icache_restart_request == `TRUE)
  53.472 +            pc_a = restart_address;
  53.473 +	  else 
  53.474 +`endif        
  53.475 +            pc_a = pc_f + 1'b1;
  53.476 +end
  53.477 +
  53.478 +// Select where instruction should be fetched from
  53.479 +`ifdef CFG_IROM_ENABLED
  53.480 +assign irom_select_a = ({pc_a, 2'b00} >= `CFG_IROM_BASE_ADDRESS) && ({pc_a, 2'b00} <= `CFG_IROM_LIMIT);
  53.481 +`endif
  53.482 +                     
  53.483 +// Select instruction from selected source
  53.484 +`ifdef CFG_ICACHE_ENABLED
  53.485 +`ifdef CFG_IROM_ENABLED
  53.486 +assign instruction_f = irom_select_f == `TRUE ? irom_data_f : icache_data_f;
  53.487 +`else
  53.488 +assign instruction_f = icache_data_f;
  53.489 +`endif
  53.490 +`else
  53.491 +`ifdef CFG_IROM_ENABLED
  53.492 +`ifdef CFG_IWB_ENABLED
  53.493 +assign instruction_f = irom_select_f == `TRUE ? irom_data_f : wb_data_f;
  53.494 +`else
  53.495 +assign instruction_f = irom_data_f;
  53.496 +`endif
  53.497 +`else
  53.498 +assign instruction_f = wb_data_f;
  53.499 +`endif
  53.500 +`endif
  53.501 +
  53.502 +// Unused/constant Wishbone signals
  53.503 +`ifdef CFG_IWB_ENABLED
  53.504 +`ifdef CFG_HW_DEBUG_ENABLED
  53.505 +`else
  53.506 +assign i_dat_o = 32'd0;
  53.507 +assign i_we_o = `FALSE;
  53.508 +assign i_sel_o = 4'b1111;
  53.509 +`endif
  53.510 +assign i_bte_o = `LM32_BTYPE_LINEAR;
  53.511 +`endif
  53.512 +
  53.513 +`ifdef CFG_ICACHE_ENABLED
  53.514 +// Determine parameters for next cache refill Wishbone access                
  53.515 +generate
  53.516 +    case (bytes_per_line)
  53.517 +    4:
  53.518 +    begin
  53.519 +assign first_cycle_type = `LM32_CTYPE_END;
  53.520 +assign next_cycle_type = `LM32_CTYPE_END;
  53.521 +assign last_word = `TRUE;
  53.522 +assign first_address = icache_refill_address;
  53.523 +    end
  53.524 +    8:
  53.525 +    begin
  53.526 +assign first_cycle_type = `LM32_CTYPE_INCREMENTING;
  53.527 +assign next_cycle_type = `LM32_CTYPE_END;
  53.528 +assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 1'b1;
  53.529 +assign first_address = {icache_refill_address[`LM32_PC_WIDTH+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
  53.530 +    end
  53.531 +    16:
  53.532 +    begin
  53.533 +assign first_cycle_type = `LM32_CTYPE_INCREMENTING;
  53.534 +assign next_cycle_type = i_adr_o[addr_offset_msb] == 1'b1 ? `LM32_CTYPE_END : `LM32_CTYPE_INCREMENTING;
  53.535 +assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 2'b11;
  53.536 +assign first_address = {icache_refill_address[`LM32_PC_WIDTH+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
  53.537 +    end
  53.538 +    endcase
  53.539 +endgenerate
  53.540 +`endif
  53.541 +                     
  53.542 +/////////////////////////////////////////////////////
  53.543 +// Sequential Logic
  53.544 +/////////////////////////////////////////////////////
  53.545 +
  53.546 +// PC 
  53.547 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  53.548 +begin
  53.549 +    if (rst_i == `TRUE)
  53.550 +    begin
  53.551 +        pc_f <= (`CFG_EBA_RESET-4)/4;
  53.552 +        pc_d <= {`LM32_PC_WIDTH{1'b0}};
  53.553 +        pc_x <= {`LM32_PC_WIDTH{1'b0}};
  53.554 +        pc_m <= {`LM32_PC_WIDTH{1'b0}};
  53.555 +        pc_w <= {`LM32_PC_WIDTH{1'b0}};
  53.556 +    end
  53.557 +    else
  53.558 +    begin
  53.559 +        if (stall_f == `FALSE)
  53.560 +            pc_f <= pc_a;
  53.561 +        if (stall_d == `FALSE)
  53.562 +            pc_d <= pc_f;
  53.563 +        if (stall_x == `FALSE)
  53.564 +            pc_x <= pc_d;
  53.565 +        if (stall_m == `FALSE)
  53.566 +            pc_m <= pc_x;
  53.567 +        pc_w <= pc_m;
  53.568 +    end
  53.569 +end
  53.570 +
  53.571 +`ifdef LM32_CACHE_ENABLED
  53.572 +// Address to restart from after a cache miss has been handled
  53.573 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  53.574 +begin
  53.575 +    if (rst_i == `TRUE)
  53.576 +        restart_address <= {`LM32_PC_WIDTH{1'b0}};
  53.577 +    else
  53.578 +    begin
  53.579 +`ifdef CFG_DCACHE_ENABLED
  53.580 +`ifdef CFG_ICACHE_ENABLED        
  53.581 +            // D-cache restart address must take priority, otherwise instructions will be lost
  53.582 +            if (dcache_refill_request == `TRUE)
  53.583 +                restart_address <= pc_w;
  53.584 +            else if ((icache_refill_request == `TRUE) && (!dcache_refilling) && (!dcache_restart_request))
  53.585 +                restart_address <= icache_refill_address;
  53.586 +`else
  53.587 +            if (dcache_refill_request == `TRUE)
  53.588 +                restart_address <= pc_w;
  53.589 +`endif
  53.590 +`else
  53.591 +`ifdef CFG_ICACHE_ENABLED        
  53.592 +            if (icache_refill_request == `TRUE)
  53.593 +                restart_address <= icache_refill_address;
  53.594 +`endif
  53.595 +`endif
  53.596 +    end
  53.597 +end
  53.598 +`endif
  53.599 +
  53.600 +// Record where instruction was fetched from
  53.601 +`ifdef CFG_IROM_ENABLED
  53.602 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  53.603 +begin
  53.604 +    if (rst_i == `TRUE)
  53.605 +        irom_select_f <= `FALSE;
  53.606 +    else
  53.607 +    begin
  53.608 +        if (stall_f == `FALSE)
  53.609 +            irom_select_f <= irom_select_a;
  53.610 +    end
  53.611 +end
  53.612 +`endif
  53.613 +
  53.614 +`ifdef CFG_HW_DEBUG_ENABLED
  53.615 +assign jtag_access_complete = (i_cyc_o == `TRUE) && ((i_ack_i == `TRUE) || (i_err_i == `TRUE)) && (jtag_access == `TRUE);
  53.616 +always @(*)
  53.617 +begin
  53.618 +    case (jtag_address[1:0])
  53.619 +    2'b00: jtag_read_data = i_dat_i[`LM32_BYTE_3_RNG];
  53.620 +    2'b01: jtag_read_data = i_dat_i[`LM32_BYTE_2_RNG];
  53.621 +    2'b10: jtag_read_data = i_dat_i[`LM32_BYTE_1_RNG];
  53.622 +    2'b11: jtag_read_data = i_dat_i[`LM32_BYTE_0_RNG];
  53.623 +    endcase 
  53.624 +end
  53.625 +`endif
  53.626 +
  53.627 +`ifdef CFG_IWB_ENABLED
  53.628 +// Instruction Wishbone interface
  53.629 +`ifdef CFG_ICACHE_ENABLED                
  53.630 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  53.631 +begin
  53.632 +    if (rst_i == `TRUE)
  53.633 +    begin
  53.634 +        i_cyc_o <= `FALSE;
  53.635 +        i_stb_o <= `FALSE;
  53.636 +        i_adr_o <= {`LM32_WORD_WIDTH{1'b0}};
  53.637 +        i_cti_o <= `LM32_CTYPE_END;
  53.638 +        i_lock_o <= `FALSE;
  53.639 +        icache_refill_data <= {`LM32_INSTRUCTION_WIDTH{1'b0}};
  53.640 +        icache_refill_ready <= `FALSE;
  53.641 +`ifdef CFG_BUS_ERRORS_ENABLED
  53.642 +        bus_error_f <= `FALSE;
  53.643 +`endif
  53.644 +`ifdef CFG_HW_DEBUG_ENABLED
  53.645 +        i_we_o <= `FALSE;
  53.646 +        i_sel_o <= 4'b1111;
  53.647 +        jtag_access <= `FALSE;
  53.648 +`endif
  53.649 +    end
  53.650 +    else
  53.651 +    begin   
  53.652 +        icache_refill_ready <= `FALSE;
  53.653 +        // Is a cycle in progress?
  53.654 +        if (i_cyc_o == `TRUE)
  53.655 +        begin
  53.656 +            // Has cycle completed?
  53.657 +            if ((i_ack_i == `TRUE) || (i_err_i == `TRUE))
  53.658 +            begin
  53.659 +`ifdef CFG_HW_DEBUG_ENABLED
  53.660 +                if (jtag_access == `TRUE)
  53.661 +                begin
  53.662 +                    i_cyc_o <= `FALSE;
  53.663 +                    i_stb_o <= `FALSE;       
  53.664 +                    i_we_o <= `FALSE;  
  53.665 +                    jtag_access <= `FALSE;    
  53.666 +                end
  53.667 +                else
  53.668 +`endif
  53.669 +                begin
  53.670 +                    if (last_word == `TRUE)
  53.671 +                    begin
  53.672 +                        // Cache line fill complete 
  53.673 +                        i_cyc_o <= `FALSE;
  53.674 +                        i_stb_o <= `FALSE;
  53.675 +                        i_lock_o <= `FALSE;
  53.676 +                    end
  53.677 +                    // Fetch next word in cache line
  53.678 +                    i_adr_o[addr_offset_msb:addr_offset_lsb] <= i_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
  53.679 +                    i_cti_o <= next_cycle_type;
  53.680 +                    // Write fetched data into instruction cache
  53.681 +                    icache_refill_ready <= `TRUE;
  53.682 +                    icache_refill_data <= i_dat_i;
  53.683 +                end
  53.684 +            end
  53.685 +`ifdef CFG_BUS_ERRORS_ENABLED
  53.686 +            if (i_err_i == `TRUE)
  53.687 +            begin
  53.688 +                bus_error_f <= `TRUE;
  53.689 +                $display ("Instruction bus error. Address: %x", i_adr_o);
  53.690 +            end
  53.691 +`endif
  53.692 +        end
  53.693 +        else
  53.694 +        begin
  53.695 +            if ((icache_refill_request == `TRUE) && (icache_refill_ready == `FALSE))
  53.696 +            begin
  53.697 +                // Read first word of cache line
  53.698 +`ifdef CFG_HW_DEBUG_ENABLED     
  53.699 +                i_sel_o <= 4'b1111;
  53.700 +`endif
  53.701 +                i_adr_o <= {first_address, 2'b00};
  53.702 +                i_cyc_o <= `TRUE;
  53.703 +                i_stb_o <= `TRUE;                
  53.704 +                i_cti_o <= first_cycle_type;
  53.705 +                //i_lock_o <= `TRUE;
  53.706 +`ifdef CFG_BUS_ERRORS_ENABLED
  53.707 +                bus_error_f <= `FALSE;
  53.708 +`endif
  53.709 +            end
  53.710 +`ifdef CFG_HW_DEBUG_ENABLED
  53.711 +            else
  53.712 +            begin
  53.713 +                if ((jtag_read_enable == `TRUE) || (jtag_write_enable == `TRUE))
  53.714 +                begin
  53.715 +                    case (jtag_address[1:0])
  53.716 +                    2'b00: i_sel_o <= 4'b1000;
  53.717 +                    2'b01: i_sel_o <= 4'b0100;
  53.718 +                    2'b10: i_sel_o <= 4'b0010;
  53.719 +                    2'b11: i_sel_o <= 4'b0001;
  53.720 +                    endcase
  53.721 +                    i_adr_o <= jtag_address;
  53.722 +                    i_dat_o <= {4{jtag_write_data}};
  53.723 +                    i_cyc_o <= `TRUE;
  53.724 +                    i_stb_o <= `TRUE;
  53.725 +                    i_we_o <= jtag_write_enable;
  53.726 +                    i_cti_o <= `LM32_CTYPE_END;
  53.727 +                    jtag_access <= `TRUE;
  53.728 +                end
  53.729 +            end 
  53.730 +`endif                    
  53.731 +`ifdef CFG_BUS_ERRORS_ENABLED
  53.732 +            // Clear bus error when exception taken, otherwise they would be 
  53.733 +            // continually generated if exception handler is cached
  53.734 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
  53.735 +            if (branch_taken_x == `TRUE)
  53.736 +                bus_error_f <= `FALSE;
  53.737 +`endif
  53.738 +            if (branch_taken_m == `TRUE)
  53.739 +                bus_error_f <= `FALSE;
  53.740 +`endif
  53.741 +        end
  53.742 +    end
  53.743 +end
  53.744 +`else
  53.745 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  53.746 +begin
  53.747 +    if (rst_i == `TRUE)
  53.748 +    begin
  53.749 +        i_cyc_o <= `FALSE;
  53.750 +        i_stb_o <= `FALSE;
  53.751 +        i_adr_o <= {`LM32_WORD_WIDTH{1'b0}};
  53.752 +        i_cti_o <= `LM32_CTYPE_END;
  53.753 +        i_lock_o <= `FALSE;
  53.754 +        wb_data_f <= {`LM32_INSTRUCTION_WIDTH{1'b0}};
  53.755 +`ifdef CFG_BUS_ERRORS_ENABLED
  53.756 +        bus_error_f <= `FALSE;
  53.757 +`endif
  53.758 +    end
  53.759 +    else
  53.760 +    begin   
  53.761 +        // Is a cycle in progress?
  53.762 +        if (i_cyc_o == `TRUE)
  53.763 +        begin
  53.764 +            // Has cycle completed?
  53.765 +            if((i_ack_i == `TRUE) || (i_err_i == `TRUE))
  53.766 +            begin
  53.767 +                // Cycle complete
  53.768 +                i_cyc_o <= `FALSE;
  53.769 +                i_stb_o <= `FALSE;
  53.770 +                // Register fetched instruction
  53.771 +                wb_data_f <= i_dat_i;
  53.772 +            end
  53.773 +`ifdef CFG_BUS_ERRORS_ENABLED
  53.774 +            if (i_err_i == `TRUE)
  53.775 +            begin
  53.776 +                bus_error_f <= `TRUE;
  53.777 +                $display ("Instruction bus error. Address: %x", i_adr_o);
  53.778 +            end
  53.779 +`endif
  53.780 +        end
  53.781 +        else
  53.782 +        begin
  53.783 +            // Wait for an instruction fetch from an external address 
  53.784 +            if (   (stall_a == `FALSE) 
  53.785 +`ifdef CFG_IROM_ENABLED 
  53.786 +                && (irom_select_a == `FALSE)
  53.787 +`endif       
  53.788 +               )
  53.789 +            begin
  53.790 +                // Fetch instruction
  53.791 +`ifdef CFG_HW_DEBUG_ENABLED     
  53.792 +                i_sel_o <= 4'b1111;
  53.793 +`endif
  53.794 +                i_adr_o <= {pc_a, 2'b00};
  53.795 +                i_cyc_o <= `TRUE;
  53.796 +                i_stb_o <= `TRUE;
  53.797 +`ifdef CFG_BUS_ERRORS_ENABLED
  53.798 +                bus_error_f <= `FALSE;
  53.799 +`endif
  53.800 +            end
  53.801 +	    else
  53.802 +	    begin
  53.803 +	        if (   (stall_a == `FALSE) 
  53.804 +`ifdef CFG_IROM_ENABLED 
  53.805 +		    && (irom_select_a == `TRUE)
  53.806 +`endif       
  53.807 +	           )
  53.808 +		begin
  53.809 +`ifdef CFG_BUS_ERRORS_ENABLED
  53.810 +		    bus_error_f <= `FALSE;
  53.811 +`endif
  53.812 +		end
  53.813 +	    end
  53.814 +        end
  53.815 +    end
  53.816 +end
  53.817 +`endif
  53.818 +`endif
  53.819 +
  53.820 +// Instruction register
  53.821 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  53.822 +begin
  53.823 +    if (rst_i == `TRUE)
  53.824 +    begin
  53.825 +        instruction_d <= {`LM32_INSTRUCTION_WIDTH{1'b0}};
  53.826 +`ifdef CFG_BUS_ERRORS_ENABLED
  53.827 +        bus_error_d <= `FALSE;
  53.828 +`endif
  53.829 +    end
  53.830 +    else
  53.831 +    begin
  53.832 +        if (stall_d == `FALSE)
  53.833 +        begin
  53.834 +            instruction_d <= instruction_f;
  53.835 +`ifdef CFG_BUS_ERRORS_ENABLED
  53.836 +            bus_error_d <= bus_error_f;
  53.837 +`endif
  53.838 +        end
  53.839 +    end
  53.840 +end  
  53.841 +  
  53.842 +endmodule

    54.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    54.2 +++ b/rtl/lm32_interrupt.v	Tue Mar 08 09:40:42 2011 +0000
    54.3 @@ -0,0 +1,335 @@
    54.4 +// =============================================================================
    54.5 +//                           COPYRIGHT NOTICE
    54.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation
    54.7 +// ALL RIGHTS RESERVED
    54.8 +// This confidential and proprietary software may be used only as authorised by
    54.9 +// a licensing agreement from Lattice Semiconductor Corporation.
   54.10 +// The entire notice above must be reproduced on all authorized copies and
   54.11 +// copies may only be made to the extent permitted by a licensing agreement from
   54.12 +// Lattice Semiconductor Corporation.
   54.13 +//
   54.14 +// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
   54.15 +// 5555 NE Moore Court                            408-826-6000 (other locations)
   54.16 +// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
   54.17 +// U.S.A                                   email: techsupport@latticesemi.com
   54.18 +// =============================================================================/
   54.19 +//                         FILE DETAILS
   54.20 +// Project          : LatticeMico32
   54.21 +// File             : lm32_interrupt.v
   54.22 +// Title            : Interrupt logic
   54.23 +// Dependencies     : lm32_include.v
   54.24 +// Version          : 6.1.17
   54.25 +//                  : Initial Release
   54.26 +// Version          : 7.0SP2, 3.0
   54.27 +//                  : No Change
   54.28 +// Version          : 3.1
   54.29 +//                  : No Change
   54.30 +// =============================================================================
   54.31 +
   54.32 +`include "lm32_include.v"
   54.33 +
   54.34 +/////////////////////////////////////////////////////
   54.35 +// Module interface
   54.36 +/////////////////////////////////////////////////////
   54.37 +
   54.38 +module lm32_interrupt (
   54.39 +    // ----- Inputs -------
   54.40 +    clk_i, 
   54.41 +    rst_i,
   54.42 +    // From external devices
   54.43 +    interrupt,
   54.44 +    // From pipeline
   54.45 +    stall_x,
   54.46 +`ifdef CFG_DEBUG_ENABLED
   54.47 +    non_debug_exception,
   54.48 +    debug_exception,
   54.49 +`else
   54.50 +    exception,
   54.51 +`endif
   54.52 +    eret_q_x,
   54.53 +`ifdef CFG_DEBUG_ENABLED
   54.54 +    bret_q_x,
   54.55 +`endif
   54.56 +    csr,
   54.57 +    csr_write_data,
   54.58 +    csr_write_enable,
   54.59 +    // ----- Outputs -------
   54.60 +    interrupt_exception,
   54.61 +    // To pipeline
   54.62 +    csr_read_data
   54.63 +    );
   54.64 +
   54.65 +/////////////////////////////////////////////////////
   54.66 +// Parameters
   54.67 +/////////////////////////////////////////////////////
   54.68 +
   54.69 +parameter interrupts = `CFG_INTERRUPTS;         // Number of interrupts
   54.70 +
   54.71 +/////////////////////////////////////////////////////
   54.72 +// Inputs
   54.73 +/////////////////////////////////////////////////////
   54.74 +
   54.75 +input clk_i;                                    // Clock
   54.76 +input rst_i;                                    // Reset
   54.77 +
   54.78 +input [interrupts-1:0] interrupt;               // Interrupt pins, active-low
   54.79 +
   54.80 +input stall_x;                                  // Stall X pipeline stage
   54.81 +
   54.82 +`ifdef CFG_DEBUG_ENABLED
   54.83 +input non_debug_exception;                      // Non-debug related exception has been raised
   54.84 +input debug_exception;                          // Debug-related exception has been raised
   54.85 +`else
   54.86 +input exception;                                // Exception has been raised
   54.87 +`endif
   54.88 +input eret_q_x;                                 // Return from exception 
   54.89 +`ifdef CFG_DEBUG_ENABLED
   54.90 +input bret_q_x;                                 // Return from breakpoint 
   54.91 +`endif
   54.92 +
   54.93 +input [`LM32_CSR_RNG] csr;                      // CSR read/write index
   54.94 +input [`LM32_WORD_RNG] csr_write_data;          // Data to write to specified CSR
   54.95 +input csr_write_enable;                         // CSR write enable
   54.96 +
   54.97 +/////////////////////////////////////////////////////
   54.98 +// Outputs
   54.99 +/////////////////////////////////////////////////////
  54.100 +
  54.101 +output interrupt_exception;                     // Request to raide an interrupt exception
  54.102 +wire   interrupt_exception;
  54.103 +
  54.104 +output [`LM32_WORD_RNG] csr_read_data;          // Data read from CSR
  54.105 +reg    [`LM32_WORD_RNG] csr_read_data;
  54.106 +
  54.107 +/////////////////////////////////////////////////////
  54.108 +// Internal nets and registers 
  54.109 +/////////////////////////////////////////////////////
  54.110 +
  54.111 +wire [interrupts-1:0] asserted;                 // Which interrupts are currently being asserted
  54.112 +//pragma attribute asserted preserve_signal true
  54.113 +wire [interrupts-1:0] interrupt_n_exception;
  54.114 +
  54.115 +// Interrupt CSRs
  54.116 +
  54.117 +reg ie;                                         // Interrupt enable
  54.118 +reg eie;                                        // Exception interrupt enable
  54.119 +`ifdef CFG_DEBUG_ENABLED
  54.120 +reg bie;                                        // Breakpoint interrupt enable
  54.121 +`endif
  54.122 +reg [interrupts-1:0] ip;                        // Interrupt pending
  54.123 +reg [interrupts-1:0] im;                        // Interrupt mask
  54.124 +
  54.125 +/////////////////////////////////////////////////////
  54.126 +// Combinational Logic
  54.127 +/////////////////////////////////////////////////////
  54.128 +
  54.129 +// Determine which interrupts have occured and are unmasked
  54.130 +assign interrupt_n_exception = ip & im;
  54.131 +
  54.132 +// Determine if any unmasked interrupts have occured
  54.133 +assign interrupt_exception = (|interrupt_n_exception) & ie;
  54.134 +
  54.135 +// Determine which interrupts are currently being asserted (active-low) or are already pending
  54.136 +assign asserted = ip | interrupt;
  54.137 +       
  54.138 +assign ie_csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}}, 
  54.139 +`ifdef CFG_DEBUG_ENABLED
  54.140 +                           bie,
  54.141 +`else
  54.142 +                           1'b0,
  54.143 +`endif                             
  54.144 +                           eie, 
  54.145 +                           ie
  54.146 +                          };
  54.147 +assign ip_csr_read_data = ip;
  54.148 +assign im_csr_read_data = im;
  54.149 +generate
  54.150 +    if (interrupts > 1) 
  54.151 +    begin
  54.152 +// CSR read
  54.153 +always @(*)
  54.154 +begin
  54.155 +    case (csr)
  54.156 +    `LM32_CSR_IE:  csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}}, 
  54.157 +`ifdef CFG_DEBUG_ENABLED
  54.158 +                                    bie,
  54.159 +`else
  54.160 +                                    1'b0,                                     
  54.161 +`endif
  54.162 +                                    eie, 
  54.163 +                                    ie
  54.164 +                                   };
  54.165 +    `LM32_CSR_IP:  csr_read_data = ip;
  54.166 +    `LM32_CSR_IM:  csr_read_data = im;
  54.167 +    default:       csr_read_data = {`LM32_WORD_WIDTH{1'bx}};
  54.168 +    endcase
  54.169 +end
  54.170 +    end
  54.171 +    else
  54.172 +    begin
  54.173 +// CSR read
  54.174 +always @(*)
  54.175 +begin
  54.176 +    case (csr)
  54.177 +    `LM32_CSR_IE:  csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}}, 
  54.178 +`ifdef CFG_DEBUG_ENABLED
  54.179 +                                    bie, 
  54.180 +`else
  54.181 +                                    1'b0,                                    
  54.182 +`endif
  54.183 +                                    eie, 
  54.184 +                                    ie
  54.185 +                                   };
  54.186 +    `LM32_CSR_IP:  csr_read_data = ip;
  54.187 +    default:       csr_read_data = {`LM32_WORD_WIDTH{1'bx}};
  54.188 +    endcase
  54.189 +end
  54.190 +    end
  54.191 +endgenerate
  54.192 +    
  54.193 +/////////////////////////////////////////////////////
  54.194 +// Sequential Logic
  54.195 +/////////////////////////////////////////////////////
  54.196 +
  54.197 +generate
  54.198 +    if (interrupts > 1)
  54.199 +    begin
  54.200 +// IE, IM, IP - Interrupt Enable, Interrupt Mask and Interrupt Pending CSRs
  54.201 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  54.202 +begin
  54.203 +    if (rst_i == `TRUE)
  54.204 +    begin
  54.205 +        ie <= `FALSE;
  54.206 +        eie <= `FALSE;
  54.207 +`ifdef CFG_DEBUG_ENABLED
  54.208 +        bie <= `FALSE;
  54.209 +`endif
  54.210 +        im <= {interrupts{1'b0}};
  54.211 +        ip <= {interrupts{1'b0}};
  54.212 +    end
  54.213 +    else
  54.214 +    begin
  54.215 +        // Set IP bit when interrupt line is asserted
  54.216 +        ip <= asserted;
  54.217 +`ifdef CFG_DEBUG_ENABLED
  54.218 +        if (non_debug_exception == `TRUE)
  54.219 +        begin
  54.220 +            // Save and then clear interrupt enable
  54.221 +            eie <= ie;
  54.222 +            ie <= `FALSE;
  54.223 +        end
  54.224 +        else if (debug_exception == `TRUE)
  54.225 +        begin
  54.226 +            // Save and then clear interrupt enable
  54.227 +            bie <= ie;
  54.228 +            ie <= `FALSE;
  54.229 +        end
  54.230 +`else
  54.231 +        if (exception == `TRUE)
  54.232 +        begin
  54.233 +            // Save and then clear interrupt enable
  54.234 +            eie <= ie;
  54.235 +            ie <= `FALSE;
  54.236 +        end
  54.237 +`endif
  54.238 +        else if (stall_x == `FALSE)
  54.239 +        begin
  54.240 +            if (eret_q_x == `TRUE)
  54.241 +                // Restore interrupt enable
  54.242 +                ie <= eie;          
  54.243 +`ifdef CFG_DEBUG_ENABLED
  54.244 +            else if (bret_q_x == `TRUE)
  54.245 +                // Restore interrupt enable
  54.246 +                ie <= bie;
  54.247 +`endif
  54.248 +            else if (csr_write_enable == `TRUE)
  54.249 +            begin
  54.250 +                // Handle wcsr write
  54.251 +                if (csr == `LM32_CSR_IE)
  54.252 +                begin
  54.253 +                    ie <= csr_write_data[0];
  54.254 +                    eie <= csr_write_data[1];
  54.255 +`ifdef CFG_DEBUG_ENABLED
  54.256 +                    bie <= csr_write_data[2];
  54.257 +`endif
  54.258 +                end
  54.259 +                if (csr == `LM32_CSR_IM)
  54.260 +                    im <= csr_write_data[interrupts-1:0];
  54.261 +                if (csr == `LM32_CSR_IP)
  54.262 +                    ip <= asserted & ~csr_write_data[interrupts-1:0];
  54.263 +            end
  54.264 +        end
  54.265 +    end
  54.266 +end
  54.267 +    end
  54.268 +else
  54.269 +    begin
  54.270 +// IE, IM, IP - Interrupt Enable, Interrupt Mask and Interrupt Pending CSRs
  54.271 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  54.272 +begin
  54.273 +    if (rst_i == `TRUE)
  54.274 +    begin
  54.275 +        ie <= `FALSE;
  54.276 +        eie <= `FALSE;
  54.277 +`ifdef CFG_DEBUG_ENABLED
  54.278 +        bie <= `FALSE;
  54.279 +`endif
  54.280 +        ip <= {interrupts{1'b0}};
  54.281 +    end
  54.282 +    else
  54.283 +    begin
  54.284 +        // Set IP bit when interrupt line is asserted
  54.285 +        ip <= asserted;
  54.286 +`ifdef CFG_DEBUG_ENABLED
  54.287 +        if (non_debug_exception == `TRUE)
  54.288 +        begin
  54.289 +            // Save and then clear interrupt enable
  54.290 +            eie <= ie;
  54.291 +            ie <= `FALSE;
  54.292 +        end
  54.293 +        else if (debug_exception == `TRUE)
  54.294 +        begin
  54.295 +            // Save and then clear interrupt enable
  54.296 +            bie <= ie;
  54.297 +            ie <= `FALSE;
  54.298 +        end
  54.299 +`else
  54.300 +        if (exception == `TRUE)
  54.301 +        begin
  54.302 +            // Save and then clear interrupt enable
  54.303 +            eie <= ie;
  54.304 +            ie <= `FALSE;
  54.305 +        end
  54.306 +`endif
  54.307 +        else if (stall_x == `FALSE)
  54.308 +        begin
  54.309 +            if (eret_q_x == `TRUE)
  54.310 +                // Restore interrupt enable
  54.311 +                ie <= eie;          
  54.312 +`ifdef CFG_DEBUG_ENABLED
  54.313 +            else if (bret_q_x == `TRUE)
  54.314 +                // Restore interrupt enable
  54.315 +                ie <= bie;
  54.316 +`endif
  54.317 +            else if (csr_write_enable == `TRUE)
  54.318 +            begin
  54.319 +                // Handle wcsr write
  54.320 +                if (csr == `LM32_CSR_IE)
  54.321 +                begin
  54.322 +                    ie <= csr_write_data[0];
  54.323 +                    eie <= csr_write_data[1];
  54.324 +`ifdef CFG_DEBUG_ENABLED
  54.325 +                    bie <= csr_write_data[2];
  54.326 +`endif
  54.327 +                end
  54.328 +                if (csr == `LM32_CSR_IP)
  54.329 +                    ip <= asserted & ~csr_write_data[interrupts-1:0];
  54.330 +            end
  54.331 +        end
  54.332 +    end
  54.333 +end
  54.334 +    end
  54.335 +endgenerate
  54.336 +
  54.337 +endmodule
  54.338 +

    55.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    55.2 +++ b/rtl/lm32_jtag.v	Tue Mar 08 09:40:42 2011 +0000
    55.3 @@ -0,0 +1,469 @@
    55.4 +// =============================================================================
    55.5 +//                           COPYRIGHT NOTICE
    55.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation
    55.7 +// ALL RIGHTS RESERVED
    55.8 +// This confidential and proprietary software may be used only as authorised by
    55.9 +// a licensing agreement from Lattice Semiconductor Corporation.
   55.10 +// The entire notice above must be reproduced on all authorized copies and
   55.11 +// copies may only be made to the extent permitted by a licensing agreement from
   55.12 +// Lattice Semiconductor Corporation.
   55.13 +//
   55.14 +// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
   55.15 +// 5555 NE Moore Court                            408-826-6000 (other locations)
   55.16 +// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
   55.17 +// U.S.A                                   email: techsupport@latticesemi.com
   55.18 +// =============================================================================/
   55.19 +//                         FILE DETAILS
   55.20 +// Project          : LatticeMico32
   55.21 +// File             : lm32_jtag.v
   55.22 +// Title            : JTAG interface
   55.23 +// Dependencies     : lm32_include.v
   55.24 +// Version          : 6.1.17
   55.25 +//                  : Initial Release
   55.26 +// Version          : 7.0SP2, 3.0
   55.27 +//                  : No Change
   55.28 +// Version          : 3.1
   55.29 +//                  : No Change
   55.30 +// =============================================================================
   55.31 +
   55.32 +`include "lm32_include.v"
   55.33 +
   55.34 +`ifdef CFG_JTAG_ENABLED
   55.35 +
   55.36 +`define LM32_DP                             3'b000
   55.37 +`define LM32_TX                             3'b001
   55.38 +`define LM32_RX                             3'b010
   55.39 +
   55.40 +// LM32 Debug Protocol commands IDs
   55.41 +`define LM32_DP_RNG                         3:0
   55.42 +`define LM32_DP_READ_MEMORY                 4'b0001
   55.43 +`define LM32_DP_WRITE_MEMORY                4'b0010
   55.44 +`define LM32_DP_READ_SEQUENTIAL             4'b0011
   55.45 +`define LM32_DP_WRITE_SEQUENTIAL            4'b0100
   55.46 +`define LM32_DP_WRITE_CSR                   4'b0101
   55.47 +`define LM32_DP_BREAK                       4'b0110
   55.48 +`define LM32_DP_RESET                       4'b0111
   55.49 +
   55.50 +// States for FSM
   55.51 +`define LM32_JTAG_STATE_RNG                 3:0
   55.52 +`define LM32_JTAG_STATE_READ_COMMAND        4'h0
   55.53 +`define LM32_JTAG_STATE_READ_BYTE_0         4'h1
   55.54 +`define LM32_JTAG_STATE_READ_BYTE_1         4'h2
   55.55 +`define LM32_JTAG_STATE_READ_BYTE_2         4'h3
   55.56 +`define LM32_JTAG_STATE_READ_BYTE_3         4'h4
   55.57 +`define LM32_JTAG_STATE_READ_BYTE_4         4'h5
   55.58 +`define LM32_JTAG_STATE_PROCESS_COMMAND     4'h6
   55.59 +`define LM32_JTAG_STATE_WAIT_FOR_MEMORY     4'h7
   55.60 +`define LM32_JTAG_STATE_WAIT_FOR_CSR        4'h8
   55.61 +
   55.62 +/////////////////////////////////////////////////////
   55.63 +// Module interface
   55.64 +/////////////////////////////////////////////////////
   55.65 +
   55.66 +module lm32_jtag (
   55.67 +    // ----- Inputs -------
   55.68 +    clk_i,
   55.69 +    rst_i,
   55.70 +    jtag_clk, 
   55.71 +    jtag_update,
   55.72 +    jtag_reg_q,
   55.73 +    jtag_reg_addr_q,
   55.74 +`ifdef CFG_JTAG_UART_ENABLED
   55.75 +    csr,
   55.76 +    csr_write_enable,
   55.77 +    csr_write_data,
   55.78 +    stall_x,
   55.79 +`endif
   55.80 +`ifdef CFG_HW_DEBUG_ENABLED
   55.81 +    jtag_read_data,
   55.82 +    jtag_access_complete,
   55.83 +`endif
   55.84 +`ifdef CFG_DEBUG_ENABLED
   55.85 +    exception_q_w,
   55.86 +`endif
   55.87 +    // ----- Outputs -------
   55.88 +`ifdef CFG_JTAG_UART_ENABLED
   55.89 +    jtx_csr_read_data,
   55.90 +    jrx_csr_read_data,
   55.91 +`endif
   55.92 +`ifdef CFG_HW_DEBUG_ENABLED
   55.93 +    jtag_csr_write_enable,
   55.94 +    jtag_csr_write_data,
   55.95 +    jtag_csr,
   55.96 +    jtag_read_enable,
   55.97 +    jtag_write_enable,
   55.98 +    jtag_write_data,
   55.99 +    jtag_address,
  55.100 +`endif
  55.101 +`ifdef CFG_DEBUG_ENABLED
  55.102 +    jtag_break,
  55.103 +    jtag_reset,
  55.104 +`endif
  55.105 +    jtag_reg_d,
  55.106 +    jtag_reg_addr_d
  55.107 +    );
  55.108 +
  55.109 +/////////////////////////////////////////////////////
  55.110 +// Inputs
  55.111 +/////////////////////////////////////////////////////
  55.112 +
  55.113 +input clk_i;                                            // Clock
  55.114 +input rst_i;                                            // Reset
  55.115 +
  55.116 +input jtag_clk;                                         // JTAG clock
  55.117 +input jtag_update;                                      // JTAG data register has been updated
  55.118 +input [`LM32_BYTE_RNG] jtag_reg_q;                      // JTAG data register
  55.119 +input [2:0] jtag_reg_addr_q;                            // JTAG data register
  55.120 +
  55.121 +`ifdef CFG_JTAG_UART_ENABLED
  55.122 +input [`LM32_CSR_RNG] csr;                              // CSR to write
  55.123 +input csr_write_enable;                                 // CSR write enable
  55.124 +input [`LM32_WORD_RNG] csr_write_data;                  // Data to write to specified CSR
  55.125 +input stall_x;                                          // Stall instruction in X stage
  55.126 +`endif
  55.127 +`ifdef CFG_HW_DEBUG_ENABLED
  55.128 +input [`LM32_BYTE_RNG] jtag_read_data;                  // Data read from requested address
  55.129 +input jtag_access_complete;                             // Memory access if complete
  55.130 +`endif
  55.131 +`ifdef CFG_DEBUG_ENABLED
  55.132 +input exception_q_w;                                    // Indicates an exception has occured in W stage
  55.133 +`endif
  55.134 +
  55.135 +/////////////////////////////////////////////////////
  55.136 +// Outputs
  55.137 +/////////////////////////////////////////////////////
  55.138 +       
  55.139 +`ifdef CFG_JTAG_UART_ENABLED
  55.140 +output [`LM32_WORD_RNG] jtx_csr_read_data;              // Value of JTX CSR for rcsr instructions
  55.141 +wire   [`LM32_WORD_RNG] jtx_csr_read_data;
  55.142 +output [`LM32_WORD_RNG] jrx_csr_read_data;              // Value of JRX CSR for rcsr instructions
  55.143 +wire   [`LM32_WORD_RNG] jrx_csr_read_data;
  55.144 +`endif
  55.145 +`ifdef CFG_HW_DEBUG_ENABLED
  55.146 +output jtag_csr_write_enable;                           // CSR write enable
  55.147 +reg    jtag_csr_write_enable;
  55.148 +output [`LM32_WORD_RNG] jtag_csr_write_data;            // Data to write to specified CSR
  55.149 +wire   [`LM32_WORD_RNG] jtag_csr_write_data;
  55.150 +output [`LM32_CSR_RNG] jtag_csr;                        // CSR to write
  55.151 +wire   [`LM32_CSR_RNG] jtag_csr;
  55.152 +output jtag_read_enable;                                // Memory read enable
  55.153 +reg    jtag_read_enable;
  55.154 +output jtag_write_enable;                               // Memory write enable
  55.155 +reg    jtag_write_enable;
  55.156 +output [`LM32_BYTE_RNG] jtag_write_data;                // Data to write to specified address
  55.157 +wire   [`LM32_BYTE_RNG] jtag_write_data;        
  55.158 +output [`LM32_WORD_RNG] jtag_address;                   // Memory read/write address
  55.159 +wire   [`LM32_WORD_RNG] jtag_address;
  55.160 +`endif
  55.161 +`ifdef CFG_DEBUG_ENABLED
  55.162 +output jtag_break;                                      // Request to raise a breakpoint exception
  55.163 +reg    jtag_break;
  55.164 +output jtag_reset;                                      // Request to raise a reset exception
  55.165 +reg    jtag_reset;
  55.166 +`endif
  55.167 +output [`LM32_BYTE_RNG] jtag_reg_d;
  55.168 +reg    [`LM32_BYTE_RNG] jtag_reg_d;
  55.169 +output [2:0] jtag_reg_addr_d;
  55.170 +wire   [2:0] jtag_reg_addr_d;
  55.171 +             
  55.172 +/////////////////////////////////////////////////////
  55.173 +// Internal nets and registers 
  55.174 +/////////////////////////////////////////////////////
  55.175 +
  55.176 +reg rx_update;                          // Clock-domain crossing registers
  55.177 +reg rx_update_r;                        // Registered version of rx_update
  55.178 +reg rx_update_r_r;                      // Registered version of rx_update_r
  55.179 +reg rx_update_r_r_r;                    // Registered version of rx_update_r_r
  55.180 +
  55.181 +// These wires come from the JTAG clock domain.
  55.182 +// They have been held unchanged for an entire JTAG clock cycle before the jtag_update toggle flips
  55.183 +wire [`LM32_BYTE_RNG] rx_byte;   
  55.184 +wire [2:0] rx_addr;
  55.185 +
  55.186 +`ifdef CFG_JTAG_UART_ENABLED                 
  55.187 +reg [`LM32_BYTE_RNG] uart_tx_byte;      // UART TX data
  55.188 +reg uart_tx_valid;                      // TX data is valid
  55.189 +reg [`LM32_BYTE_RNG] uart_rx_byte;      // UART RX data
  55.190 +reg uart_rx_valid;                      // RX data is valid
  55.191 +`endif
  55.192 +
  55.193 +reg [`LM32_DP_RNG] command;             // The last received command
  55.194 +`ifdef CFG_HW_DEBUG_ENABLED
  55.195 +reg [`LM32_BYTE_RNG] jtag_byte_0;       // Registers to hold command paramaters
  55.196 +reg [`LM32_BYTE_RNG] jtag_byte_1;
  55.197 +reg [`LM32_BYTE_RNG] jtag_byte_2;
  55.198 +reg [`LM32_BYTE_RNG] jtag_byte_3;
  55.199 +reg [`LM32_BYTE_RNG] jtag_byte_4;
  55.200 +reg processing;                         // Indicates if we're still processing a memory read/write
  55.201 +`endif
  55.202 +
  55.203 +reg [`LM32_JTAG_STATE_RNG] state;       // Current state of FSM
  55.204 +
  55.205 +/////////////////////////////////////////////////////
  55.206 +// Combinational Logic
  55.207 +/////////////////////////////////////////////////////
  55.208 +
  55.209 +`ifdef CFG_HW_DEBUG_ENABLED
  55.210 +assign jtag_csr_write_data = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
  55.211 +assign jtag_csr = jtag_byte_4[`LM32_CSR_RNG];
  55.212 +assign jtag_address = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
  55.213 +assign jtag_write_data = jtag_byte_4;
  55.214 +`endif
  55.215 +                 
  55.216 +// Generate status flags for reading via the JTAG interface                 
  55.217 +`ifdef CFG_JTAG_UART_ENABLED                 
  55.218 +assign jtag_reg_addr_d[1:0] = {uart_rx_valid, uart_tx_valid};         
  55.219 +`else
  55.220 +assign jtag_reg_addr_d[1:0] = 2'b00;
  55.221 +`endif
  55.222 +`ifdef CFG_HW_DEBUG_ENABLED
  55.223 +assign jtag_reg_addr_d[2] = processing;
  55.224 +`else
  55.225 +assign jtag_reg_addr_d[2] = 1'b0;
  55.226 +`endif
  55.227 +
  55.228 +`ifdef CFG_JTAG_UART_ENABLED                 
  55.229 +assign jtx_csr_read_data = {{`LM32_WORD_WIDTH-9{1'b0}}, uart_tx_valid, 8'h00};
  55.230 +assign jrx_csr_read_data = {{`LM32_WORD_WIDTH-9{1'b0}}, uart_rx_valid, uart_rx_byte};
  55.231 +`endif         
  55.232 +                 
  55.233 +/////////////////////////////////////////////////////
  55.234 +// Sequential Logic
  55.235 +/////////////////////////////////////////////////////
  55.236 +
  55.237 +assign rx_byte = jtag_reg_q;
  55.238 +assign rx_addr = jtag_reg_addr_q;
  55.239 +
  55.240 +// The JTAG latched jtag_reg[_addr]_q at least one JTCK before jtag_update is raised
  55.241 +// Thus, they are stable (and safe to sample) when jtag_update is high
  55.242 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  55.243 +begin
  55.244 +    if (rst_i == `TRUE)
  55.245 +    begin
  55.246 +        rx_update <= 1'b0;
  55.247 +        rx_update_r <= 1'b0;
  55.248 +        rx_update_r_r <= 1'b0;
  55.249 +        rx_update_r_r_r <= 1'b0;
  55.250 +    end
  55.251 +    else
  55.252 +    begin
  55.253 +        rx_update <= jtag_update;
  55.254 +        rx_update_r <= rx_update;
  55.255 +        rx_update_r_r <= rx_update_r;
  55.256 +        rx_update_r_r_r <= rx_update_r_r;
  55.257 +    end
  55.258 +end
  55.259 +
  55.260 +// LM32 debug protocol state machine
  55.261 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  55.262 +begin
  55.263 +    if (rst_i == `TRUE)
  55.264 +    begin
  55.265 +        state <= `LM32_JTAG_STATE_READ_COMMAND;
  55.266 +        command <= 4'b0000;
  55.267 +        jtag_reg_d <= 8'h00;
  55.268 +`ifdef CFG_HW_DEBUG_ENABLED
  55.269 +        processing <= `FALSE;
  55.270 +        jtag_csr_write_enable <= `FALSE;
  55.271 +        jtag_read_enable <= `FALSE;
  55.272 +        jtag_write_enable <= `FALSE;
  55.273 +`endif
  55.274 +`ifdef CFG_DEBUG_ENABLED
  55.275 +        jtag_break <= `FALSE;
  55.276 +        jtag_reset <= `FALSE;
  55.277 +`endif
  55.278 +`ifdef CFG_JTAG_UART_ENABLED                 
  55.279 +        uart_tx_byte <= 8'h00;
  55.280 +        uart_tx_valid <= `FALSE;
  55.281 +        uart_rx_byte <= 8'h00;
  55.282 +        uart_rx_valid <= `FALSE;
  55.283 +`endif
  55.284 +    end
  55.285 +    else
  55.286 +    begin
  55.287 +`ifdef CFG_JTAG_UART_ENABLED                 
  55.288 +        if ((csr_write_enable == `TRUE) && (stall_x == `FALSE))
  55.289 +        begin
  55.290 +            case (csr)
  55.291 +            `LM32_CSR_JTX:
  55.292 +            begin
  55.293 +                // Set flag indicating data is available
  55.294 +                uart_tx_byte <= csr_write_data[`LM32_BYTE_0_RNG];
  55.295 +                uart_tx_valid <= `TRUE;
  55.296 +            end
  55.297 +            `LM32_CSR_JRX:
  55.298 +            begin
  55.299 +                // Clear flag indidicating data has been received
  55.300 +                uart_rx_valid <= `FALSE;
  55.301 +            end
  55.302 +            endcase
  55.303 +        end
  55.304 +`endif
  55.305 +`ifdef CFG_DEBUG_ENABLED
  55.306 +        // When an exception has occured, clear the requests
  55.307 +        if (exception_q_w == `TRUE)
  55.308 +        begin
  55.309 +            jtag_break <= `FALSE;
  55.310 +            jtag_reset <= `FALSE;
  55.311 +        end
  55.312 +`endif
  55.313 +        case (state)
  55.314 +        `LM32_JTAG_STATE_READ_COMMAND:
  55.315 +        begin
  55.316 +            // Wait for rx register to toggle which indicates new data is available
  55.317 +            if ((~rx_update_r_r_r & rx_update_r_r) == `TRUE)
  55.318 +            begin
  55.319 +                command <= rx_byte[7:4];                
  55.320 +                case (rx_addr)
  55.321 +`ifdef CFG_DEBUG_ENABLED
  55.322 +                `LM32_DP:
  55.323 +                begin
  55.324 +                    case (rx_byte[7:4])
  55.325 +`ifdef CFG_HW_DEBUG_ENABLED
  55.326 +                    `LM32_DP_READ_MEMORY:
  55.327 +                        state <= `LM32_JTAG_STATE_READ_BYTE_0;
  55.328 +                    `LM32_DP_READ_SEQUENTIAL:
  55.329 +                    begin
  55.330 +                        {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
  55.331 +                        state <= `LM32_JTAG_STATE_PROCESS_COMMAND;
  55.332 +                    end
  55.333 +                    `LM32_DP_WRITE_MEMORY:
  55.334 +                        state <= `LM32_JTAG_STATE_READ_BYTE_0;
  55.335 +                    `LM32_DP_WRITE_SEQUENTIAL:
  55.336 +                    begin
  55.337 +                        {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
  55.338 +                        state <= 5;
  55.339 +                    end
  55.340 +                    `LM32_DP_WRITE_CSR:
  55.341 +                        state <= `LM32_JTAG_STATE_READ_BYTE_0;
  55.342 +`endif                    
  55.343 +                    `LM32_DP_BREAK:
  55.344 +                    begin
  55.345 +`ifdef CFG_JTAG_UART_ENABLED     
  55.346 +                        uart_rx_valid <= `FALSE;    
  55.347 +                        uart_tx_valid <= `FALSE;         
  55.348 +`endif
  55.349 +                        jtag_break <= `TRUE;
  55.350 +                    end
  55.351 +                    `LM32_DP_RESET:
  55.352 +                    begin
  55.353 +`ifdef CFG_JTAG_UART_ENABLED     
  55.354 +                        uart_rx_valid <= `FALSE;    
  55.355 +                        uart_tx_valid <= `FALSE;         
  55.356 +`endif
  55.357 +                        jtag_reset <= `TRUE;
  55.358 +                    end
  55.359 +                    endcase                               
  55.360 +                end
  55.361 +`endif
  55.362 +`ifdef CFG_JTAG_UART_ENABLED                 
  55.363 +                `LM32_TX:
  55.364 +                begin
  55.365 +                    uart_rx_byte <= rx_byte;
  55.366 +                    uart_rx_valid <= `TRUE;
  55.367 +                end                    
  55.368 +                `LM32_RX:
  55.369 +                begin
  55.370 +                    jtag_reg_d <= uart_tx_byte;
  55.371 +                    uart_tx_valid <= `FALSE;
  55.372 +                end
  55.373 +`endif
  55.374 +                default:
  55.375 +                    ;
  55.376 +                endcase                
  55.377 +            end
  55.378 +        end
  55.379 +`ifdef CFG_HW_DEBUG_ENABLED
  55.380 +        `LM32_JTAG_STATE_READ_BYTE_0:
  55.381 +        begin
  55.382 +            if ((~rx_update_r_r_r & rx_update_r_r) == `TRUE)
  55.383 +            begin
  55.384 +                jtag_byte_0 <= rx_byte;
  55.385 +                state <= `LM32_JTAG_STATE_READ_BYTE_1;
  55.386 +            end
  55.387 +        end
  55.388 +        `LM32_JTAG_STATE_READ_BYTE_1:
  55.389 +        begin
  55.390 +            if ((~rx_update_r_r_r & rx_update_r_r) == `TRUE)
  55.391 +            begin
  55.392 +                jtag_byte_1 <= rx_byte;
  55.393 +                state <= `LM32_JTAG_STATE_READ_BYTE_2;
  55.394 +            end
  55.395 +        end
  55.396 +        `LM32_JTAG_STATE_READ_BYTE_2:
  55.397 +        begin
  55.398 +            if ((~rx_update_r_r_r & rx_update_r_r) == `TRUE)
  55.399 +            begin
  55.400 +                jtag_byte_2 <= rx_byte;
  55.401 +                state <= `LM32_JTAG_STATE_READ_BYTE_3;
  55.402 +            end
  55.403 +        end
  55.404 +        `LM32_JTAG_STATE_READ_BYTE_3:
  55.405 +        begin
  55.406 +            if ((~rx_update_r_r_r & rx_update_r_r) == `TRUE)
  55.407 +            begin
  55.408 +                jtag_byte_3 <= rx_byte;
  55.409 +                if (command == `LM32_DP_READ_MEMORY)
  55.410 +                    state <= `LM32_JTAG_STATE_PROCESS_COMMAND;
  55.411 +                else 
  55.412 +                    state <= `LM32_JTAG_STATE_READ_BYTE_4;
  55.413 +            end
  55.414 +        end
  55.415 +        `LM32_JTAG_STATE_READ_BYTE_4:
  55.416 +        begin
  55.417 +            if ((~rx_update_r_r_r & rx_update_r_r) == `TRUE)
  55.418 +            begin
  55.419 +                jtag_byte_4 <= rx_byte;
  55.420 +                state <= `LM32_JTAG_STATE_PROCESS_COMMAND;
  55.421 +            end
  55.422 +        end
  55.423 +        `LM32_JTAG_STATE_PROCESS_COMMAND:
  55.424 +        begin
  55.425 +            case (command)
  55.426 +            `LM32_DP_READ_MEMORY,
  55.427 +            `LM32_DP_READ_SEQUENTIAL:
  55.428 +            begin
  55.429 +                jtag_read_enable <= `TRUE;
  55.430 +                processing <= `TRUE;
  55.431 +                state <= `LM32_JTAG_STATE_WAIT_FOR_MEMORY;
  55.432 +            end
  55.433 +            `LM32_DP_WRITE_MEMORY,
  55.434 +            `LM32_DP_WRITE_SEQUENTIAL:
  55.435 +            begin
  55.436 +                jtag_write_enable <= `TRUE;
  55.437 +                processing <= `TRUE;
  55.438 +                state <= `LM32_JTAG_STATE_WAIT_FOR_MEMORY;
  55.439 +            end
  55.440 +            `LM32_DP_WRITE_CSR:
  55.441 +            begin
  55.442 +                jtag_csr_write_enable <= `TRUE;
  55.443 +                processing <= `TRUE;
  55.444 +                state <= `LM32_JTAG_STATE_WAIT_FOR_CSR;
  55.445 +            end
  55.446 +            endcase
  55.447 +        end
  55.448 +        `LM32_JTAG_STATE_WAIT_FOR_MEMORY:
  55.449 +        begin
  55.450 +            if (jtag_access_complete == `TRUE)
  55.451 +            begin          
  55.452 +                jtag_read_enable <= `FALSE;
  55.453 +                jtag_reg_d <= jtag_read_data;
  55.454 +                jtag_write_enable <= `FALSE;  
  55.455 +                processing <= `FALSE;
  55.456 +                state <= `LM32_JTAG_STATE_READ_COMMAND;
  55.457 +            end
  55.458 +        end    
  55.459 +        `LM32_JTAG_STATE_WAIT_FOR_CSR:
  55.460 +        begin
  55.461 +            jtag_csr_write_enable <= `FALSE;
  55.462 +            processing <= `FALSE;
  55.463 +            state <= `LM32_JTAG_STATE_READ_COMMAND;
  55.464 +        end    
  55.465 +`endif
  55.466 +        endcase
  55.467 +    end
  55.468 +end
  55.469 +  
  55.470 +endmodule
  55.471 +
  55.472 +`endif

    56.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    56.2 +++ b/rtl/lm32_load_store_unit.v	Tue Mar 08 09:40:42 2011 +0000
    56.3 @@ -0,0 +1,806 @@
    56.4 +// =============================================================================
    56.5 +//                           COPYRIGHT NOTICE
    56.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation
    56.7 +// ALL RIGHTS RESERVED
    56.8 +// This confidential and proprietary software may be used only as authorised by
    56.9 +// a licensing agreement from Lattice Semiconductor Corporation.
   56.10 +// The entire notice above must be reproduced on all authorized copies and
   56.11 +// copies may only be made to the extent permitted by a licensing agreement from
   56.12 +// Lattice Semiconductor Corporation.
   56.13 +//
   56.14 +// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
   56.15 +// 5555 NE Moore Court                            408-826-6000 (other locations)
   56.16 +// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
   56.17 +// U.S.A                                   email: techsupport@latticesemi.com
   56.18 +// =============================================================================/
   56.19 +//                         FILE DETAILS
   56.20 +// Project      : LatticeMico32
   56.21 +// File         : lm32_load_store_unit.v
   56.22 +// Title        : Load and store unit
   56.23 +// Dependencies : lm32_include.v
   56.24 +// Version      : 6.1.17
   56.25 +//              : Initial Release
   56.26 +// Version      : 7.0SP2, 3.0
   56.27 +//              : No Change
   56.28 +// Version      : 3.1
   56.29 +//              : Instead of disallowing an instruction cache miss on a data cache 
   56.30 +//              : miss, both can now occur at the same time. If both occur at same 
   56.31 +//              : time, then restart address is the address of instruction that 
   56.32 +//              : caused data cache miss.
   56.33 +// Version      : 3.2
   56.34 +//              : EBRs use SYNC resets instead of ASYNC resets.
   56.35 +// Version      : 3.3
   56.36 +//              : Support for new non-cacheable Data Memory that is accessible by 
   56.37 +//              : the data port and has a one cycle access latency.
   56.38 +// Version      : 3.4
   56.39 +//              : No change
   56.40 +// Version      : 3.5
   56.41 +//              : Bug fix: Inline memory is correctly generated if it is not a
   56.42 +//              : power-of-two
   56.43 +// =============================================================================
   56.44 +
   56.45 +`include "lm32_include.v"
   56.46 +
   56.47 +/////////////////////////////////////////////////////
   56.48 +// Module interface
   56.49 +/////////////////////////////////////////////////////
   56.50 +
   56.51 +module lm32_load_store_unit (
   56.52 +    // ----- Inputs -------
   56.53 +    clk_i,
   56.54 +    rst_i,
   56.55 +    // From pipeline
   56.56 +    stall_a,
   56.57 +    stall_x,
   56.58 +    stall_m,
   56.59 +    kill_m,
   56.60 +    exception_m,
   56.61 +    store_operand_x,
   56.62 +    load_store_address_x,
   56.63 +    load_store_address_m,
   56.64 +    load_store_address_w,
   56.65 +    load_x,
   56.66 +    store_x,
   56.67 +    load_q_x,
   56.68 +    store_q_x,
   56.69 +    load_q_m,
   56.70 +    store_q_m,
   56.71 +    sign_extend_x,
   56.72 +    size_x,
   56.73 +`ifdef CFG_DCACHE_ENABLED
   56.74 +    dflush,
   56.75 +`endif
   56.76 +`ifdef CFG_IROM_ENABLED
   56.77 +    irom_data_m,
   56.78 +`endif
   56.79 +    // From Wishbone
   56.80 +    d_dat_i,
   56.81 +    d_ack_i,
   56.82 +    d_err_i,
   56.83 +    d_rty_i,
   56.84 +    // ----- Outputs -------
   56.85 +    // To pipeline
   56.86 +`ifdef CFG_DCACHE_ENABLED
   56.87 +    dcache_refill_request,
   56.88 +    dcache_restart_request,
   56.89 +    dcache_stall_request,
   56.90 +    dcache_refilling,
   56.91 +`endif    
   56.92 +`ifdef CFG_IROM_ENABLED
   56.93 +    irom_store_data_m,
   56.94 +    irom_address_xm,
   56.95 +    irom_we_xm,
   56.96 +    irom_stall_request_x,
   56.97 +`endif			     
   56.98 +    load_data_w,
   56.99 +    stall_wb_load,
  56.100 +    // To Wishbone
  56.101 +    d_dat_o,
  56.102 +    d_adr_o,
  56.103 +    d_cyc_o,
  56.104 +    d_sel_o,
  56.105 +    d_stb_o,
  56.106 +    d_we_o,
  56.107 +    d_cti_o,
  56.108 +    d_lock_o,
  56.109 +    d_bte_o
  56.110 +    );
  56.111 +
  56.112 +/////////////////////////////////////////////////////
  56.113 +// Parameters
  56.114 +/////////////////////////////////////////////////////
  56.115 +
  56.116 +parameter associativity = 1;                            // Associativity of the cache (Number of ways)
  56.117 +parameter sets = 512;                                   // Number of sets
  56.118 +parameter bytes_per_line = 16;                          // Number of bytes per cache line
  56.119 +parameter base_address = 0;                             // Base address of cachable memory
  56.120 +parameter limit = 0;                                    // Limit (highest address) of cachable memory
  56.121 +
  56.122 +// For bytes_per_line == 4, we set 1 so part-select range isn't reversed, even though not really used 
  56.123 +localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2;
  56.124 +localparam addr_offset_lsb = 2;
  56.125 +localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
  56.126 +
  56.127 +/////////////////////////////////////////////////////
  56.128 +// Inputs
  56.129 +/////////////////////////////////////////////////////
  56.130 +
  56.131 +input clk_i;                                            // Clock 
  56.132 +input rst_i;                                            // Reset
  56.133 +
  56.134 +input stall_a;                                          // A stage stall 
  56.135 +input stall_x;                                          // X stage stall        
  56.136 +input stall_m;                                          // M stage stall
  56.137 +input kill_m;                                           // Kill instruction in M stage
  56.138 +input exception_m;                                      // An exception occured in the M stage
  56.139 +
  56.140 +input [`LM32_WORD_RNG] store_operand_x;                 // Data read from register to store
  56.141 +input [`LM32_WORD_RNG] load_store_address_x;            // X stage load/store address
  56.142 +input [`LM32_WORD_RNG] load_store_address_m;            // M stage load/store address
  56.143 +input [1:0] load_store_address_w;                       // W stage load/store address (only least two significant bits are needed)
  56.144 +input load_x;                                           // Load instruction in X stage
  56.145 +input store_x;                                          // Store instruction in X stage
  56.146 +input load_q_x;                                         // Load instruction in X stage
  56.147 +input store_q_x;                                        // Store instruction in X stage
  56.148 +input load_q_m;                                         // Load instruction in M stage
  56.149 +input store_q_m;                                        // Store instruction in M stage
  56.150 +input sign_extend_x;                                    // Whether load instruction in X stage should sign extend or zero extend
  56.151 +input [`LM32_SIZE_RNG] size_x;                          // Size of load or store (byte, hword, word)
  56.152 +
  56.153 +`ifdef CFG_DCACHE_ENABLED
  56.154 +input dflush;                                           // Flush the data cache
  56.155 +`endif
  56.156 +
  56.157 +`ifdef CFG_IROM_ENABLED   
  56.158 +input [`LM32_WORD_RNG] irom_data_m;                     // Data from Instruction-ROM
  56.159 +`endif
  56.160 +
  56.161 +input [`LM32_WORD_RNG] d_dat_i;                         // Data Wishbone interface read data
  56.162 +input d_ack_i;                                          // Data Wishbone interface acknowledgement
  56.163 +input d_err_i;                                          // Data Wishbone interface error
  56.164 +input d_rty_i;                                          // Data Wishbone interface retry
  56.165 +
  56.166 +/////////////////////////////////////////////////////
  56.167 +// Outputs
  56.168 +/////////////////////////////////////////////////////
  56.169 +
  56.170 +`ifdef CFG_DCACHE_ENABLED
  56.171 +output dcache_refill_request;                           // Request to refill data cache
  56.172 +wire   dcache_refill_request;
  56.173 +output dcache_restart_request;                          // Request to restart the instruction that caused a data cache miss
  56.174 +wire   dcache_restart_request;
  56.175 +output dcache_stall_request;                            // Data cache stall request
  56.176 +wire   dcache_stall_request;
  56.177 +output dcache_refilling;
  56.178 +wire   dcache_refilling;
  56.179 +`endif
  56.180 +
  56.181 +`ifdef CFG_IROM_ENABLED   
  56.182 +output irom_store_data_m;                               // Store data to Instruction ROM
  56.183 +wire   [`LM32_WORD_RNG] irom_store_data_m;
  56.184 +output [`LM32_WORD_RNG] irom_address_xm;                // Load/store address to Instruction ROM
  56.185 +wire   [`LM32_WORD_RNG] irom_address_xm;
  56.186 +output irom_we_xm;                                      // Write-enable of 2nd port of Instruction ROM
  56.187 +wire   irom_we_xm;
  56.188 +output irom_stall_request_x;                            // Stall instruction in D stage  
  56.189 +wire   irom_stall_request_x;                            
  56.190 +`endif
  56.191 +   
  56.192 +output [`LM32_WORD_RNG] load_data_w;                    // Result of a load instruction
  56.193 +reg    [`LM32_WORD_RNG] load_data_w;
  56.194 +output stall_wb_load;                                   // Request to stall pipeline due to a load from the Wishbone interface
  56.195 +reg    stall_wb_load;
  56.196 +
  56.197 +output [`LM32_WORD_RNG] d_dat_o;                        // Data Wishbone interface write data
  56.198 +reg    [`LM32_WORD_RNG] d_dat_o;
  56.199 +output [`LM32_WORD_RNG] d_adr_o;                        // Data Wishbone interface address
  56.200 +reg    [`LM32_WORD_RNG] d_adr_o;
  56.201 +output d_cyc_o;                                         // Data Wishbone interface cycle
  56.202 +reg    d_cyc_o;
  56.203 +output [`LM32_BYTE_SELECT_RNG] d_sel_o;                 // Data Wishbone interface byte select
  56.204 +reg    [`LM32_BYTE_SELECT_RNG] d_sel_o;
  56.205 +output d_stb_o;                                         // Data Wishbone interface strobe
  56.206 +reg    d_stb_o; 
  56.207 +output d_we_o;                                          // Data Wishbone interface write enable
  56.208 +reg    d_we_o;
  56.209 +output [`LM32_CTYPE_RNG] d_cti_o;                       // Data Wishbone interface cycle type 
  56.210 +reg    [`LM32_CTYPE_RNG] d_cti_o;
  56.211 +output d_lock_o;                                        // Date Wishbone interface lock bus
  56.212 +reg    d_lock_o;
  56.213 +output [`LM32_BTYPE_RNG] d_bte_o;                       // Data Wishbone interface burst type 
  56.214 +wire   [`LM32_BTYPE_RNG] d_bte_o;
  56.215 +
  56.216 +/////////////////////////////////////////////////////
  56.217 +// Internal nets and registers 
  56.218 +/////////////////////////////////////////////////////
  56.219 +
  56.220 +// Microcode pipeline registers - See inputs for description
  56.221 +reg [`LM32_SIZE_RNG] size_m;
  56.222 +reg [`LM32_SIZE_RNG] size_w;
  56.223 +reg sign_extend_m;
  56.224 +reg sign_extend_w;
  56.225 +reg [`LM32_WORD_RNG] store_data_x;       
  56.226 +reg [`LM32_WORD_RNG] store_data_m;       
  56.227 +reg [`LM32_BYTE_SELECT_RNG] byte_enable_x;
  56.228 +reg [`LM32_BYTE_SELECT_RNG] byte_enable_m;
  56.229 +wire [`LM32_WORD_RNG] data_m;
  56.230 +reg [`LM32_WORD_RNG] data_w;
  56.231 +
  56.232 +`ifdef CFG_DCACHE_ENABLED
  56.233 +wire dcache_select_x;                                   // Select data cache to load from / store to
  56.234 +reg dcache_select_m;
  56.235 +wire [`LM32_WORD_RNG] dcache_data_m;                    // Data read from cache
  56.236 +wire [`LM32_WORD_RNG] dcache_refill_address;            // Address to refill data cache from
  56.237 +reg dcache_refill_ready;                                // Indicates the next word of refill data is ready
  56.238 +wire [`LM32_CTYPE_RNG] first_cycle_type;                // First Wishbone cycle type
  56.239 +wire [`LM32_CTYPE_RNG] next_cycle_type;                 // Next Wishbone cycle type
  56.240 +wire last_word;                                         // Indicates if this is the last word in the cache line
  56.241 +wire [`LM32_WORD_RNG] first_address;                    // First cache refill address
  56.242 +`endif
  56.243 +`ifdef CFG_DRAM_ENABLED
  56.244 +wire dram_select_x;                                     // Select data RAM to load from / store to
  56.245 +reg dram_select_m;
  56.246 +reg dram_bypass_en;                                     // RAW in data RAM; read latched (bypass) value rather than value from memory
  56.247 +reg [`LM32_WORD_RNG] dram_bypass_data;                  // Latched value of store'd data to data RAM
  56.248 +wire [`LM32_WORD_RNG] dram_data_out;                    // Data read from data RAM
  56.249 +wire [`LM32_WORD_RNG] dram_data_m;                      // Data read from data RAM: bypass value or value from memory
  56.250 +wire [`LM32_WORD_RNG] dram_store_data_m;                // Data to write to RAM
  56.251 +`endif
  56.252 +wire wb_select_x;                                       // Select Wishbone to load from / store to
  56.253 +`ifdef CFG_IROM_ENABLED
  56.254 +wire irom_select_x;                                     // Select instruction ROM to load from / store to
  56.255 +reg  irom_select_m;
  56.256 +`endif
  56.257 +reg wb_select_m;
  56.258 +reg [`LM32_WORD_RNG] wb_data_m;                         // Data read from Wishbone
  56.259 +reg wb_load_complete;                                   // Indicates when a Wishbone load is complete
  56.260 +
  56.261 +/////////////////////////////////////////////////////
  56.262 +// Functions
  56.263 +/////////////////////////////////////////////////////
  56.264 +
  56.265 +`include "lm32_functions.v"
  56.266 +
  56.267 +/////////////////////////////////////////////////////
  56.268 +// Instantiations
  56.269 +/////////////////////////////////////////////////////
  56.270 +
  56.271 +`ifdef CFG_DRAM_ENABLED
  56.272 +   // Data RAM
  56.273 +   pmi_ram_dp_true 
  56.274 +     #(
  56.275 +       // ----- Parameters -------
  56.276 +       .pmi_family             (`LATTICE_FAMILY),
  56.277 +
  56.278 +       //.pmi_addr_depth_a       (1 << (clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)),
  56.279 +       //.pmi_addr_width_a       ((clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)),
  56.280 +       //.pmi_data_width_a       (`LM32_WORD_WIDTH),
  56.281 +       //.pmi_addr_depth_b       (1 << (clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)),
  56.282 +       //.pmi_addr_width_b       ((clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)),
  56.283 +       //.pmi_data_width_b       (`LM32_WORD_WIDTH),
  56.284 +	
  56.285 +       .pmi_addr_depth_a       (`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1),
  56.286 +       .pmi_addr_width_a       (clogb2_v1(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
  56.287 +       .pmi_data_width_a       (`LM32_WORD_WIDTH),
  56.288 +       .pmi_addr_depth_b       (`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1),
  56.289 +       .pmi_addr_width_b       (clogb2_v1(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
  56.290 +       .pmi_data_width_b       (`LM32_WORD_WIDTH),
  56.291 +
  56.292 +       .pmi_regmode_a          ("noreg"),
  56.293 +       .pmi_regmode_b          ("noreg"),
  56.294 +       .pmi_gsr                ("enable"),
  56.295 +       .pmi_resetmode          ("sync"),
  56.296 +       .pmi_init_file          (`CFG_DRAM_INIT_FILE),
  56.297 +       .pmi_init_file_format   (`CFG_DRAM_INIT_FILE_FORMAT),
  56.298 +       .module_type            ("pmi_ram_dp_true")
  56.299 +       ) 
  56.300 +       ram (
  56.301 +	    // ----- Inputs -------
  56.302 +	    .ClockA                 (clk_i),
  56.303 +	    .ClockB                 (clk_i),
  56.304 +	    .ResetA                 (rst_i),
  56.305 +	    .ResetB                 (rst_i),
  56.306 +	    .DataInA                ({32{1'b0}}),
  56.307 +	    .DataInB                (dram_store_data_m),
  56.308 +	    .AddressA               (load_store_address_x[(clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)+2-1:2]),
  56.309 +	    .AddressB               (load_store_address_m[(clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)+2-1:2]),
  56.310 +	    // .ClockEnA               (!stall_x & (load_x | store_x)),
  56.311 +	    .ClockEnA               (!stall_x),
  56.312 +	    .ClockEnB               (!stall_m),
  56.313 +	    .WrA                    (`FALSE),
  56.314 +	    .WrB                    (store_q_m & dram_select_m), 
  56.315 +	    // ----- Outputs -------
  56.316 +	    .QA                     (dram_data_out),
  56.317 +	    .QB                     ()
  56.318 +	    );
  56.319 +   
  56.320 +   /*----------------------------------------------------------------------
  56.321 +    EBRs cannot perform reads from location 'written to' on the same clock
  56.322 +    edge. Therefore bypass logic is required to latch the store'd value
  56.323 +    and use it for the load (instead of value from memory).
  56.324 +    ----------------------------------------------------------------------*/
  56.325 +   always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  56.326 +     if (rst_i == `TRUE)
  56.327 +       begin
  56.328 +	  dram_bypass_en <= `FALSE;
  56.329 +	  dram_bypass_data <= 0;
  56.330 +       end
  56.331 +     else
  56.332 +       begin
  56.333 +	  if (stall_x == `FALSE)
  56.334 +	    dram_bypass_data <= dram_store_data_m;
  56.335 +	  
  56.336 +	  if (   (stall_m == `FALSE) 
  56.337 +              && (stall_x == `FALSE)
  56.338 +	      && (store_q_m == `TRUE)
  56.339 +	      && (   (load_x == `TRUE)
  56.340 +	          || (store_x == `TRUE)
  56.341 +		 )
  56.342 +	      && (load_store_address_x[(`LM32_WORD_WIDTH-1):2] == load_store_address_m[(`LM32_WORD_WIDTH-1):2])
  56.343 +	     )
  56.344 +	    dram_bypass_en <= `TRUE;
  56.345 +	  else
  56.346 +	    if (   (dram_bypass_en == `TRUE)
  56.347 +		&& (stall_x == `FALSE)
  56.348 +	       )
  56.349 +	      dram_bypass_en <= `FALSE;
  56.350 +       end
  56.351 +   
  56.352 +   assign dram_data_m = dram_bypass_en ? dram_bypass_data : dram_data_out;
  56.353 +`endif
  56.354 +
  56.355 +`ifdef CFG_DCACHE_ENABLED
  56.356 +// Data cache
  56.357 +lm32_dcache #(
  56.358 +    .associativity          (associativity),
  56.359 +    .sets                   (sets),
  56.360 +    .bytes_per_line         (bytes_per_line),
  56.361 +    .base_address           (base_address),
  56.362 +    .limit                  (limit)
  56.363 +    ) dcache ( 
  56.364 +    // ----- Inputs -----
  56.365 +    .clk_i                  (clk_i),
  56.366 +    .rst_i                  (rst_i),      
  56.367 +    .stall_a                (stall_a),
  56.368 +    .stall_x                (stall_x),
  56.369 +    .stall_m                (stall_m),
  56.370 +    .address_x              (load_store_address_x),
  56.371 +    .address_m              (load_store_address_m),
  56.372 +    .load_q_m               (load_q_m & dcache_select_m),
  56.373 +    .store_q_m              (store_q_m & dcache_select_m),
  56.374 +    .store_data             (store_data_m),
  56.375 +    .store_byte_select      (byte_enable_m & {4{dcache_select_m}}),
  56.376 +    .refill_ready           (dcache_refill_ready),
  56.377 +    .refill_data            (wb_data_m),
  56.378 +    .dflush                 (dflush),
  56.379 +    // ----- Outputs -----
  56.380 +    .stall_request          (dcache_stall_request),
  56.381 +    .restart_request        (dcache_restart_request),
  56.382 +    .refill_request         (dcache_refill_request),
  56.383 +    .refill_address         (dcache_refill_address),
  56.384 +    .refilling              (dcache_refilling),
  56.385 +    .load_data              (dcache_data_m)
  56.386 +    );
  56.387 +`endif
  56.388 +
  56.389 +/////////////////////////////////////////////////////
  56.390 +// Combinational Logic
  56.391 +/////////////////////////////////////////////////////
  56.392 +
  56.393 +// Select where data should be loaded from / stored to
  56.394 +`ifdef CFG_DRAM_ENABLED
  56.395 +   assign dram_select_x =    (load_store_address_x >= `CFG_DRAM_BASE_ADDRESS) 
  56.396 +                          && (load_store_address_x <= `CFG_DRAM_LIMIT);
  56.397 +`endif
  56.398 +
  56.399 +`ifdef CFG_IROM_ENABLED
  56.400 +   assign irom_select_x =    (load_store_address_x >= `CFG_IROM_BASE_ADDRESS) 
  56.401 +                          && (load_store_address_x <= `CFG_IROM_LIMIT);
  56.402 +`endif
  56.403 +   
  56.404 +`ifdef CFG_DCACHE_ENABLED
  56.405 +   assign dcache_select_x =    (load_store_address_x >= `CFG_DCACHE_BASE_ADDRESS) 
  56.406 +                            && (load_store_address_x <= `CFG_DCACHE_LIMIT)
  56.407 +`ifdef CFG_DRAM_ENABLED
  56.408 +                            && (dram_select_x == `FALSE)
  56.409 +`endif
  56.410 +`ifdef CFG_IROM_ENABLED
  56.411 +                            && (irom_select_x == `FALSE)
  56.412 +`endif
  56.413 +                     ;
  56.414 +`endif
  56.415 +	  
  56.416 +   assign wb_select_x =    `TRUE
  56.417 +`ifdef CFG_DCACHE_ENABLED
  56.418 +                        && !dcache_select_x 
  56.419 +`endif
  56.420 +`ifdef CFG_DRAM_ENABLED
  56.421 +                        && !dram_select_x
  56.422 +`endif
  56.423 +`ifdef CFG_IROM_ENABLED
  56.424 +                        && !irom_select_x
  56.425 +`endif
  56.426 +                     ;
  56.427 +
  56.428 +// Make sure data to store is in correct byte lane
  56.429 +always @(*)
  56.430 +begin
  56.431 +    case (size_x)
  56.432 +    `LM32_SIZE_BYTE:  store_data_x = {4{store_operand_x[7:0]}};
  56.433 +    `LM32_SIZE_HWORD: store_data_x = {2{store_operand_x[15:0]}};
  56.434 +    `LM32_SIZE_WORD:  store_data_x = store_operand_x;    
  56.435 +    default:          store_data_x = {`LM32_WORD_WIDTH{1'bx}};
  56.436 +    endcase
  56.437 +end
  56.438 +
  56.439 +// Generate byte enable accoring to size of load or store and address being accessed
  56.440 +always @(*)
  56.441 +begin
  56.442 +    casez ({size_x, load_store_address_x[1:0]})
  56.443 +    {`LM32_SIZE_BYTE, 2'b11}:  byte_enable_x = 4'b0001;
  56.444 +    {`LM32_SIZE_BYTE, 2'b10}:  byte_enable_x = 4'b0010;
  56.445 +    {`LM32_SIZE_BYTE, 2'b01}:  byte_enable_x = 4'b0100;
  56.446 +    {`LM32_SIZE_BYTE, 2'b00}:  byte_enable_x = 4'b1000;
  56.447 +    {`LM32_SIZE_HWORD, 2'b1?}: byte_enable_x = 4'b0011;
  56.448 +    {`LM32_SIZE_HWORD, 2'b0?}: byte_enable_x = 4'b1100;
  56.449 +    {`LM32_SIZE_WORD, 2'b??}:  byte_enable_x = 4'b1111;
  56.450 +    default:                   byte_enable_x = 4'bxxxx;
  56.451 +    endcase
  56.452 +end
  56.453 +
  56.454 +`ifdef CFG_DRAM_ENABLED
  56.455 +// Only replace selected bytes
  56.456 +assign dram_store_data_m[`LM32_BYTE_0_RNG] = byte_enable_m[0] ? store_data_m[`LM32_BYTE_0_RNG] : dram_data_m[`LM32_BYTE_0_RNG];
  56.457 +assign dram_store_data_m[`LM32_BYTE_1_RNG] = byte_enable_m[1] ? store_data_m[`LM32_BYTE_1_RNG] : dram_data_m[`LM32_BYTE_1_RNG];
  56.458 +assign dram_store_data_m[`LM32_BYTE_2_RNG] = byte_enable_m[2] ? store_data_m[`LM32_BYTE_2_RNG] : dram_data_m[`LM32_BYTE_2_RNG];
  56.459 +assign dram_store_data_m[`LM32_BYTE_3_RNG] = byte_enable_m[3] ? store_data_m[`LM32_BYTE_3_RNG] : dram_data_m[`LM32_BYTE_3_RNG];
  56.460 +`endif
  56.461 +
  56.462 +`ifdef CFG_IROM_ENABLED
  56.463 +// Only replace selected bytes
  56.464 +assign irom_store_data_m[`LM32_BYTE_0_RNG] = byte_enable_m[0] ? store_data_m[`LM32_BYTE_0_RNG] : irom_data_m[`LM32_BYTE_0_RNG];
  56.465 +assign irom_store_data_m[`LM32_BYTE_1_RNG] = byte_enable_m[1] ? store_data_m[`LM32_BYTE_1_RNG] : irom_data_m[`LM32_BYTE_1_RNG];
  56.466 +assign irom_store_data_m[`LM32_BYTE_2_RNG] = byte_enable_m[2] ? store_data_m[`LM32_BYTE_2_RNG] : irom_data_m[`LM32_BYTE_2_RNG];
  56.467 +assign irom_store_data_m[`LM32_BYTE_3_RNG] = byte_enable_m[3] ? store_data_m[`LM32_BYTE_3_RNG] : irom_data_m[`LM32_BYTE_3_RNG];
  56.468 +`endif
  56.469 +
  56.470 +`ifdef CFG_IROM_ENABLED
  56.471 +   // Instead of implementing a byte-addressable instruction ROM (for store byte instruction),
  56.472 +   // a load-and-store architecture is used wherein a 32-bit value is loaded, the requisite
  56.473 +   // byte is replaced, and the whole 32-bit value is written back
  56.474 +   
  56.475 +   assign irom_address_xm = ((irom_select_m == `TRUE) && (store_q_m == `TRUE))
  56.476 +	                    ? load_store_address_m
  56.477 +	                    : load_store_address_x;
  56.478 +   
  56.479 +   // All store instructions perform a write operation in the M stage
  56.480 +   assign irom_we_xm =    (irom_select_m == `TRUE)
  56.481 +	               && (store_q_m == `TRUE);
  56.482 +   
  56.483 +   // A single port in instruction ROM is available to load-store unit for doing loads/stores.
  56.484 +   // Since every store requires a load (in X stage) and then a store (in M stage), we cannot
  56.485 +   // allow load (or store) instructions sequentially after the store instructions to proceed 
  56.486 +   // until the store instruction has vacated M stage (i.e., completed the store operation)
  56.487 +   assign irom_stall_request_x =    (irom_select_x == `TRUE)
  56.488 +	                         && (store_q_x == `TRUE);
  56.489 +`endif
  56.490 +   
  56.491 +`ifdef CFG_DCACHE_ENABLED
  56.492 + `ifdef CFG_DRAM_ENABLED
  56.493 +  `ifdef CFG_IROM_ENABLED
  56.494 +   // WB + DC + DRAM + IROM
  56.495 +   assign data_m = wb_select_m == `TRUE 
  56.496 +                   ? wb_data_m
  56.497 +                   : dram_select_m == `TRUE 
  56.498 +                     ? dram_data_m
  56.499 +                     : irom_select_m == `TRUE
  56.500 +                       ? irom_data_m 
  56.501 +                       : dcache_data_m;
  56.502 +  `else
  56.503 +   // WB + DC + DRAM
  56.504 +   assign data_m = wb_select_m == `TRUE 
  56.505 +                   ? wb_data_m
  56.506 +                   : dram_select_m == `TRUE 
  56.507 +                     ? dram_data_m
  56.508 +                     : dcache_data_m;
  56.509 +  `endif
  56.510 + `else
  56.511 +  `ifdef CFG_IROM_ENABLED
  56.512 +   // WB + DC + IROM
  56.513 +   assign data_m = wb_select_m == `TRUE 
  56.514 +                   ? wb_data_m
  56.515 +                   : irom_select_m == `TRUE 
  56.516 +                     ? irom_data_m
  56.517 +                     : dcache_data_m;
  56.518 +  `else
  56.519 +   // WB + DC
  56.520 +   assign data_m = wb_select_m == `TRUE 
  56.521 +                   ? wb_data_m 
  56.522 +                   : dcache_data_m;
  56.523 +  `endif
  56.524 + `endif
  56.525 +`else
  56.526 + `ifdef CFG_DRAM_ENABLED
  56.527 +  `ifdef CFG_IROM_ENABLED
  56.528 +   // WB + DRAM + IROM
  56.529 +   assign data_m = wb_select_m == `TRUE 
  56.530 +                   ? wb_data_m 
  56.531 +                   : dram_select_m == `TRUE
  56.532 +                     ? dram_data_m
  56.533 +                     : irom_data_m;
  56.534 +  `else
  56.535 +   // WB + DRAM
  56.536 +   assign data_m = wb_select_m == `TRUE 
  56.537 +                   ? wb_data_m 
  56.538 +                   : dram_data_m;
  56.539 +  `endif
  56.540 + `else
  56.541 +  `ifdef CFG_IROM_ENABLED
  56.542 +   // WB + IROM
  56.543 +   assign data_m = wb_select_m == `TRUE 
  56.544 +                   ? wb_data_m 
  56.545 +                   : irom_data_m;
  56.546 +  `else
  56.547 +   // WB
  56.548 +   assign data_m = wb_data_m;
  56.549 +  `endif
  56.550 + `endif
  56.551 +`endif
  56.552 +
  56.553 +// Sub-word selection and sign/zero-extension for loads
  56.554 +always @(*)
  56.555 +begin
  56.556 +    casez ({size_w, load_store_address_w[1:0]})
  56.557 +    {`LM32_SIZE_BYTE, 2'b11}:  load_data_w = {{24{sign_extend_w & data_w[7]}}, data_w[7:0]};
  56.558 +    {`LM32_SIZE_BYTE, 2'b10}:  load_data_w = {{24{sign_extend_w & data_w[15]}}, data_w[15:8]};
  56.559 +    {`LM32_SIZE_BYTE, 2'b01}:  load_data_w = {{24{sign_extend_w & data_w[23]}}, data_w[23:16]};
  56.560 +    {`LM32_SIZE_BYTE, 2'b00}:  load_data_w = {{24{sign_extend_w & data_w[31]}}, data_w[31:24]};
  56.561 +    {`LM32_SIZE_HWORD, 2'b1?}: load_data_w = {{16{sign_extend_w & data_w[15]}}, data_w[15:0]};
  56.562 +    {`LM32_SIZE_HWORD, 2'b0?}: load_data_w = {{16{sign_extend_w & data_w[31]}}, data_w[31:16]};
  56.563 +    {`LM32_SIZE_WORD, 2'b??}:  load_data_w = data_w;
  56.564 +    default:                   load_data_w = {`LM32_WORD_WIDTH{1'bx}};
  56.565 +    endcase
  56.566 +end
  56.567 +
  56.568 +// Unused/constant Wishbone signals
  56.569 +assign d_bte_o = `LM32_BTYPE_LINEAR;
  56.570 +
  56.571 +`ifdef CFG_DCACHE_ENABLED                
  56.572 +// Generate signal to indicate last word in cache line
  56.573 +generate 
  56.574 +    case (bytes_per_line)
  56.575 +    4:
  56.576 +    begin
  56.577 +assign first_cycle_type = `LM32_CTYPE_END;
  56.578 +assign next_cycle_type = `LM32_CTYPE_END;
  56.579 +assign last_word = `TRUE;
  56.580 +assign first_address = {dcache_refill_address[`LM32_WORD_WIDTH-1:2], 2'b00};
  56.581 +    end
  56.582 +    8:
  56.583 +    begin
  56.584 +assign first_cycle_type = `LM32_CTYPE_INCREMENTING;
  56.585 +assign next_cycle_type = `LM32_CTYPE_END;
  56.586 +assign last_word = (&d_adr_o[addr_offset_msb:addr_offset_lsb]) == 1'b1;
  56.587 +assign first_address = {dcache_refill_address[`LM32_WORD_WIDTH-1:addr_offset_msb+1], {addr_offset_width{1'b0}}, 2'b00};
  56.588 +    end
  56.589 +    16:
  56.590 +    begin
  56.591 +assign first_cycle_type = `LM32_CTYPE_INCREMENTING;
  56.592 +assign next_cycle_type = d_adr_o[addr_offset_msb] == 1'b1 ? `LM32_CTYPE_END : `LM32_CTYPE_INCREMENTING;
  56.593 +assign last_word = (&d_adr_o[addr_offset_msb:addr_offset_lsb]) == 1'b1;
  56.594 +assign first_address = {dcache_refill_address[`LM32_WORD_WIDTH-1:addr_offset_msb+1], {addr_offset_width{1'b0}}, 2'b00};
  56.595 +    end
  56.596 +    endcase
  56.597 +endgenerate
  56.598 +`endif
  56.599 +
  56.600 +/////////////////////////////////////////////////////
  56.601 +// Sequential Logic
  56.602 +/////////////////////////////////////////////////////
  56.603 +
  56.604 +// Data Wishbone interface
  56.605 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  56.606 +begin
  56.607 +    if (rst_i == `TRUE)
  56.608 +    begin
  56.609 +        d_cyc_o <= `FALSE;
  56.610 +        d_stb_o <= `FALSE;
  56.611 +        d_dat_o <= {`LM32_WORD_WIDTH{1'b0}};
  56.612 +        d_adr_o <= {`LM32_WORD_WIDTH{1'b0}};
  56.613 +        d_sel_o <= {`LM32_BYTE_SELECT_WIDTH{`FALSE}};
  56.614 +        d_we_o <= `FALSE;
  56.615 +        d_cti_o <= `LM32_CTYPE_END;
  56.616 +        d_lock_o <= `FALSE;
  56.617 +        wb_data_m <= {`LM32_WORD_WIDTH{1'b0}};
  56.618 +        wb_load_complete <= `FALSE;
  56.619 +        stall_wb_load <= `FALSE;
  56.620 +`ifdef CFG_DCACHE_ENABLED                
  56.621 +        dcache_refill_ready <= `FALSE;
  56.622 +`endif                
  56.623 +    end
  56.624 +    else
  56.625 +    begin
  56.626 +`ifdef CFG_DCACHE_ENABLED 
  56.627 +        // Refill ready should only be asserted for a single cycle               
  56.628 +        dcache_refill_ready <= `FALSE;
  56.629 +`endif                
  56.630 +        // Is a Wishbone cycle already in progress?
  56.631 +        if (d_cyc_o == `TRUE)
  56.632 +        begin
  56.633 +            // Is the cycle complete?
  56.634 +            if ((d_ack_i == `TRUE) || (d_err_i == `TRUE))
  56.635 +            begin
  56.636 +`ifdef CFG_DCACHE_ENABLED                
  56.637 +                if ((dcache_refilling == `TRUE) && (!last_word))
  56.638 +                begin
  56.639 +                    // Fetch next word of cache line    
  56.640 +                    d_adr_o[addr_offset_msb:addr_offset_lsb] <= d_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
  56.641 +                end
  56.642 +                else
  56.643 +`endif                
  56.644 +                begin
  56.645 +                    // Refill/access complete
  56.646 +                    d_cyc_o <= `FALSE;
  56.647 +                    d_stb_o <= `FALSE;
  56.648 +                    d_lock_o <= `FALSE;
  56.649 +                end
  56.650 +`ifdef CFG_DCACHE_ENABLED    
  56.651 +                d_cti_o <= next_cycle_type;
  56.652 +                // If we are performing a refill, indicate to cache next word of data is ready            
  56.653 +                dcache_refill_ready <= dcache_refilling;
  56.654 +`endif
  56.655 +                // Register data read from Wishbone interface
  56.656 +                wb_data_m <= d_dat_i;
  56.657 +                // Don't set when stores complete - otherwise we'll deadlock if load in m stage
  56.658 +                wb_load_complete <= !d_we_o;
  56.659 +            end
  56.660 +            // synthesis translate_off            
  56.661 +            if (d_err_i == `TRUE)
  56.662 +                $display ("Data bus error. Address: %x", d_adr_o);
  56.663 +            // synthesis translate_on
  56.664 +        end
  56.665 +        else
  56.666 +        begin
  56.667 +`ifdef CFG_DCACHE_ENABLED                
  56.668 +            if (dcache_refill_request == `TRUE)
  56.669 +            begin
  56.670 +                // Start cache refill
  56.671 +                d_adr_o <= first_address;
  56.672 +                d_cyc_o <= `TRUE;
  56.673 +                d_sel_o <= {`LM32_WORD_WIDTH/8{`TRUE}};
  56.674 +                d_stb_o <= `TRUE;                
  56.675 +                d_we_o <= `FALSE;
  56.676 +                d_cti_o <= first_cycle_type;
  56.677 +                //d_lock_o <= `TRUE;
  56.678 +            end
  56.679 +            else 
  56.680 +`endif            
  56.681 +                 if (   (store_q_m == `TRUE)
  56.682 +                     && (stall_m == `FALSE)
  56.683 +`ifdef CFG_DRAM_ENABLED
  56.684 +                     && (dram_select_m == `FALSE)
  56.685 +`endif
  56.686 +`ifdef CFG_IROM_ENABLED
  56.687 +		     && (irom_select_m == `FALSE)
  56.688 +`endif			
  56.689 +                    )
  56.690 +            begin
  56.691 +                // Data cache is write through, so all stores go to memory
  56.692 +                d_dat_o <= store_data_m;
  56.693 +                d_adr_o <= load_store_address_m;
  56.694 +                d_cyc_o <= `TRUE;
  56.695 +                d_sel_o <= byte_enable_m;
  56.696 +                d_stb_o <= `TRUE;
  56.697 +                d_we_o <= `TRUE;
  56.698 +                d_cti_o <= `LM32_CTYPE_END;
  56.699 +            end        
  56.700 +            else if (   (load_q_m == `TRUE) 
  56.701 +                     && (wb_select_m == `TRUE) 
  56.702 +                     && (wb_load_complete == `FALSE)
  56.703 +                     // stall_m will be TRUE, because stall_wb_load will be TRUE 
  56.704 +                    )
  56.705 +            begin
  56.706 +                // Read requested address
  56.707 +                stall_wb_load <= `FALSE;
  56.708 +                d_adr_o <= load_store_address_m;
  56.709 +                d_cyc_o <= `TRUE;
  56.710 +                d_sel_o <= byte_enable_m;
  56.711 +                d_stb_o <= `TRUE;
  56.712 +                d_we_o <= `FALSE;
  56.713 +                d_cti_o <= `LM32_CTYPE_END;
  56.714 +            end
  56.715 +        end
  56.716 +        // Clear load/store complete flag when instruction leaves M stage
  56.717 +        if (stall_m == `FALSE)
  56.718 +            wb_load_complete <= `FALSE;
  56.719 +        // When a Wishbone load first enters the M stage, we need to stall it
  56.720 +        if ((load_q_x == `TRUE) && (wb_select_x == `TRUE) && (stall_x == `FALSE))
  56.721 +            stall_wb_load <= `TRUE;
  56.722 +        // Clear stall request if load instruction is killed
  56.723 +        if ((kill_m == `TRUE) || (exception_m == `TRUE))
  56.724 +            stall_wb_load <= `FALSE;
  56.725 +    end
  56.726 +end
  56.727 +
  56.728 +// Pipeline registers  
  56.729 +
  56.730 +// X/M stage pipeline registers
  56.731 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  56.732 +begin
  56.733 +    if (rst_i == `TRUE)
  56.734 +    begin
  56.735 +        sign_extend_m <= `FALSE;
  56.736 +        size_m <= 2'b00;
  56.737 +        byte_enable_m <= `FALSE;
  56.738 +        store_data_m <= {`LM32_WORD_WIDTH{1'b0}};
  56.739 +`ifdef CFG_DCACHE_ENABLED
  56.740 +        dcache_select_m <= `FALSE;
  56.741 +`endif
  56.742 +`ifdef CFG_DRAM_ENABLED
  56.743 +        dram_select_m <= `FALSE;
  56.744 +`endif
  56.745 +`ifdef CFG_IROM_ENABLED
  56.746 +        irom_select_m <= `FALSE;
  56.747 +`endif
  56.748 +        wb_select_m <= `FALSE;        
  56.749 +    end
  56.750 +    else
  56.751 +    begin
  56.752 +        if (stall_m == `FALSE)
  56.753 +        begin
  56.754 +            sign_extend_m <= sign_extend_x;
  56.755 +            size_m <= size_x;
  56.756 +            byte_enable_m <= byte_enable_x;    
  56.757 +            store_data_m <= store_data_x;
  56.758 +`ifdef CFG_DCACHE_ENABLED
  56.759 +            dcache_select_m <= dcache_select_x;
  56.760 +`endif
  56.761 +`ifdef CFG_DRAM_ENABLED
  56.762 +            dram_select_m <= dram_select_x;
  56.763 +`endif
  56.764 +`ifdef CFG_IROM_ENABLED
  56.765 +            irom_select_m <= irom_select_x;
  56.766 +`endif
  56.767 +            wb_select_m <= wb_select_x;
  56.768 +        end
  56.769 +    end
  56.770 +end
  56.771 +
  56.772 +// M/W stage pipeline registers
  56.773 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  56.774 +begin
  56.775 +    if (rst_i == `TRUE)
  56.776 +    begin
  56.777 +        size_w <= 2'b00;
  56.778 +        data_w <= {`LM32_WORD_WIDTH{1'b0}};
  56.779 +        sign_extend_w <= `FALSE;
  56.780 +    end
  56.781 +    else
  56.782 +    begin
  56.783 +        size_w <= size_m;
  56.784 +        data_w <= data_m;
  56.785 +        sign_extend_w <= sign_extend_m;
  56.786 +    end
  56.787 +end
  56.788 +
  56.789 +/////////////////////////////////////////////////////
  56.790 +// Behavioural Logic
  56.791 +/////////////////////////////////////////////////////
  56.792 +
  56.793 +// synthesis translate_off
  56.794 +
  56.795 +// Check for non-aligned loads or stores
  56.796 +always @(posedge clk_i)
  56.797 +begin
  56.798 +    if (((load_q_m == `TRUE) || (store_q_m == `TRUE)) && (stall_m == `FALSE)) 
  56.799 +    begin
  56.800 +        if ((size_m === `LM32_SIZE_HWORD) && (load_store_address_m[0] !== 1'b0))
  56.801 +            $display ("Warning: Non-aligned halfword access. Address: 0x%0x Time: %0t.", load_store_address_m, $time);
  56.802 +        if ((size_m === `LM32_SIZE_WORD) && (load_store_address_m[1:0] !== 2'b00))
  56.803 +            $display ("Warning: Non-aligned word access. Address: 0x%0x Time: %0t.", load_store_address_m, $time);
  56.804 +    end
  56.805 +end
  56.806 +
  56.807 +// synthesis translate_on
  56.808 +
  56.809 +endmodule

    57.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    57.2 +++ b/rtl/lm32_logic_op.v	Tue Mar 08 09:40:42 2011 +0000
    57.3 @@ -0,0 +1,76 @@
    57.4 +// =============================================================================
    57.5 +//                           COPYRIGHT NOTICE
    57.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation
    57.7 +// ALL RIGHTS RESERVED
    57.8 +// This confidential and proprietary software may be used only as authorised by
    57.9 +// a licensing agreement from Lattice Semiconductor Corporation.
   57.10 +// The entire notice above must be reproduced on all authorized copies and
   57.11 +// copies may only be made to the extent permitted by a licensing agreement from
   57.12 +// Lattice Semiconductor Corporation.
   57.13 +//
   57.14 +// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
   57.15 +// 5555 NE Moore Court                            408-826-6000 (other locations)
   57.16 +// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
   57.17 +// U.S.A                                   email: techsupport@latticesemi.com
   57.18 +// =============================================================================/
   57.19 +//                         FILE DETAILS
   57.20 +// Project          : LatticeMico32
   57.21 +// File             : lm32_logic_op.v
   57.22 +// Title            : Logic operations (and / or / not etc)
   57.23 +// Dependencies     : lm32_include.v
   57.24 +// Version          : 6.1.17
   57.25 +//                  : Initial Release
   57.26 +// Version          : 7.0SP2, 3.0
   57.27 +//                  : No Change
   57.28 +// Version          : 3.1
   57.29 +//                  : No Change
   57.30 +// =============================================================================
   57.31 +
   57.32 +`include "lm32_include.v"
   57.33 +
   57.34 +/////////////////////////////////////////////////////
   57.35 +// Module interface
   57.36 +/////////////////////////////////////////////////////
   57.37 +
   57.38 +module lm32_logic_op (
   57.39 +    // ----- Inputs -------
   57.40 +    logic_op_x,
   57.41 +    operand_0_x,
   57.42 +    operand_1_x,
   57.43 +    // ----- Outputs -------
   57.44 +    logic_result_x
   57.45 +    );
   57.46 +
   57.47 +/////////////////////////////////////////////////////
   57.48 +// Inputs
   57.49 +/////////////////////////////////////////////////////
   57.50 +
   57.51 +input [`LM32_LOGIC_OP_RNG] logic_op_x;
   57.52 +input [`LM32_WORD_RNG] operand_0_x;
   57.53 +input [`LM32_WORD_RNG] operand_1_x;
   57.54 +
   57.55 +/////////////////////////////////////////////////////
   57.56 +// Outputs
   57.57 +/////////////////////////////////////////////////////
   57.58 +
   57.59 +output [`LM32_WORD_RNG] logic_result_x;
   57.60 +reg    [`LM32_WORD_RNG] logic_result_x;
   57.61 +    
   57.62 +/////////////////////////////////////////////////////
   57.63 +// Internal nets and registers 
   57.64 +/////////////////////////////////////////////////////
   57.65 +
   57.66 +integer logic_idx;
   57.67 +
   57.68 +/////////////////////////////////////////////////////
   57.69 +// Combinational Logic
   57.70 +/////////////////////////////////////////////////////
   57.71 +
   57.72 +always @(*)
   57.73 +begin
   57.74 +    for(logic_idx = 0; logic_idx < `LM32_WORD_WIDTH; logic_idx = logic_idx + 1)
   57.75 +        logic_result_x[logic_idx] = logic_op_x[{operand_1_x[logic_idx], operand_0_x[logic_idx]}];
   57.76 +end
   57.77 +    
   57.78 +endmodule
   57.79 +

    58.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    58.2 +++ b/rtl/lm32_mc_arithmetic.v	Tue Mar 08 09:40:42 2011 +0000
    58.3 @@ -0,0 +1,288 @@
    58.4 +// =============================================================================
    58.5 +//                           COPYRIGHT NOTICE
    58.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation
    58.7 +// ALL RIGHTS RESERVED
    58.8 +// This confidential and proprietary software may be used only as authorised by
    58.9 +// a licensing agreement from Lattice Semiconductor Corporation.
   58.10 +// The entire notice above must be reproduced on all authorized copies and
   58.11 +// copies may only be made to the extent permitted by a licensing agreement from
   58.12 +// Lattice Semiconductor Corporation.
   58.13 +//
   58.14 +// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
   58.15 +// 5555 NE Moore Court                            408-826-6000 (other locations)
   58.16 +// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
   58.17 +// U.S.A                                   email: techsupport@latticesemi.com
   58.18 +// =============================================================================/
   58.19 +//                         FILE DETAILS
   58.20 +// Project          : LatticeMico32
   58.21 +// File             : lm_mc_arithmetic.v
   58.22 +// Title            : Multi-cycle arithmetic unit.
   58.23 +// Dependencies     : lm32_include.v
   58.24 +// Version          : 6.1.17
   58.25 +//                  : Initial Release
   58.26 +// Version          : 7.0SP2, 3.0
   58.27 +//                  : No Change
   58.28 +// Version          : 3.1
   58.29 +//                  : No Change
   58.30 +// =============================================================================
   58.31 +
   58.32 +`include "lm32_include.v"
   58.33 +           
   58.34 +`define LM32_MC_STATE_RNG         2:0
   58.35 +`define LM32_MC_STATE_IDLE        3'b000
   58.36 +`define LM32_MC_STATE_MULTIPLY    3'b001
   58.37 +`define LM32_MC_STATE_MODULUS     3'b010   
   58.38 +`define LM32_MC_STATE_DIVIDE      3'b011 
   58.39 +`define LM32_MC_STATE_SHIFT_LEFT  3'b100
   58.40 +`define LM32_MC_STATE_SHIFT_RIGHT 3'b101
   58.41 +
   58.42 +/////////////////////////////////////////////////////
   58.43 +// Module interface
   58.44 +/////////////////////////////////////////////////////
   58.45 +
   58.46 +module lm32_mc_arithmetic (
   58.47 +    // ----- Inputs -----
   58.48 +    clk_i,
   58.49 +    rst_i,
   58.50 +    stall_d,
   58.51 +    kill_x,
   58.52 +`ifdef CFG_MC_DIVIDE_ENABLED
   58.53 +    divide_d,
   58.54 +    modulus_d,
   58.55 +`endif
   58.56 +`ifdef CFG_MC_MULTIPLY_ENABLED
   58.57 +    multiply_d,
   58.58 +`endif
   58.59 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED
   58.60 +    shift_left_d,
   58.61 +    shift_right_d,
   58.62 +    sign_extend_d,
   58.63 +`endif
   58.64 +    operand_0_d,
   58.65 +    operand_1_d,
   58.66 +    // ----- Ouputs -----
   58.67 +    result_x,
   58.68 +`ifdef CFG_MC_DIVIDE_ENABLED
   58.69 +    divide_by_zero_x,
   58.70 +`endif
   58.71 +    stall_request_x
   58.72 +    );
   58.73 +
   58.74 +/////////////////////////////////////////////////////
   58.75 +// Inputs
   58.76 +/////////////////////////////////////////////////////
   58.77 +
   58.78 +input clk_i;                                    // Clock
   58.79 +input rst_i;                                    // Reset
   58.80 +input stall_d;                                  // Stall instruction in D stage
   58.81 +input kill_x;                                   // Kill instruction in X stage
   58.82 +`ifdef CFG_MC_DIVIDE_ENABLED
   58.83 +input divide_d;                                 // Perform divide
   58.84 +input modulus_d;                                // Perform modulus
   58.85 +`endif
   58.86 +`ifdef CFG_MC_MULTIPLY_ENABLED
   58.87 +input multiply_d;                               // Perform multiply
   58.88 +`endif
   58.89 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED
   58.90 +input shift_left_d;                             // Perform left shift
   58.91 +input shift_right_d;                            // Perform right shift
   58.92 +input sign_extend_d;                            // Whether to sign-extend (arithmetic) or zero-extend (logical)
   58.93 +`endif
   58.94 +input [`LM32_WORD_RNG] operand_0_d;
   58.95 +input [`LM32_WORD_RNG] operand_1_d;
   58.96 +
   58.97 +/////////////////////////////////////////////////////
   58.98 +// Outputs
   58.99 +/////////////////////////////////////////////////////
  58.100 +
  58.101 +output [`LM32_WORD_RNG] result_x;               // Result of operation
  58.102 +reg    [`LM32_WORD_RNG] result_x;
  58.103 +`ifdef CFG_MC_DIVIDE_ENABLED
  58.104 +output divide_by_zero_x;                        // A divide by zero was attempted
  58.105 +reg    divide_by_zero_x;
  58.106 +`endif
  58.107 +output stall_request_x;                         // Request to stall pipeline from X stage back
  58.108 +wire   stall_request_x;
  58.109 +
  58.110 +/////////////////////////////////////////////////////
  58.111 +// Internal nets and registers 
  58.112 +/////////////////////////////////////////////////////
  58.113 +
  58.114 +reg [`LM32_WORD_RNG] p;                         // Temporary registers
  58.115 +reg [`LM32_WORD_RNG] a;
  58.116 +reg [`LM32_WORD_RNG] b;
  58.117 +`ifdef CFG_MC_DIVIDE_ENABLED
  58.118 +wire [32:0] t;
  58.119 +`endif
  58.120 +
  58.121 +reg [`LM32_MC_STATE_RNG] state;                 // Current state of FSM
  58.122 +reg [5:0] cycles;                               // Number of cycles remaining in the operation
  58.123 +
  58.124 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED
  58.125 +reg sign_extend_x;                              // Whether to sign extend of zero extend right shifts
  58.126 +wire fill_value;                                // Value to fill with for right barrel-shifts
  58.127 +`endif
  58.128 +
  58.129 +/////////////////////////////////////////////////////
  58.130 +// Combinational logic
  58.131 +/////////////////////////////////////////////////////
  58.132 +
  58.133 +// Stall pipeline while any operation is being performed
  58.134 +assign stall_request_x = state != `LM32_MC_STATE_IDLE;
  58.135 +
  58.136 +`ifdef CFG_MC_DIVIDE_ENABLED
  58.137 +// Subtraction
  58.138 +assign t = {p[`LM32_WORD_WIDTH-2:0], a[`LM32_WORD_WIDTH-1]} - b;
  58.139 +`endif
  58.140 +
  58.141 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED
  58.142 +// Determine fill value for right shift - Sign bit for arithmetic shift, or zero for logical shift
  58.143 +assign fill_value = (sign_extend_x == `TRUE) & b[`LM32_WORD_WIDTH-1];
  58.144 +`endif
  58.145 +
  58.146 +/////////////////////////////////////////////////////
  58.147 +// Sequential logic
  58.148 +/////////////////////////////////////////////////////
  58.149 +
  58.150 +// Perform right shift
  58.151 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  58.152 +begin
  58.153 +    if (rst_i == `TRUE)
  58.154 +    begin
  58.155 +        cycles <= {6{1'b0}};
  58.156 +        p <= {`LM32_WORD_WIDTH{1'b0}};
  58.157 +        a <= {`LM32_WORD_WIDTH{1'b0}};
  58.158 +        b <= {`LM32_WORD_WIDTH{1'b0}};
  58.159 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED
  58.160 +        sign_extend_x <= 1'b0;
  58.161 +`endif
  58.162 +`ifdef CFG_MC_DIVIDE_ENABLED
  58.163 +        divide_by_zero_x <= `FALSE;
  58.164 +`endif
  58.165 +        result_x <= {`LM32_WORD_WIDTH{1'b0}};
  58.166 +        state <= `LM32_MC_STATE_IDLE;
  58.167 +    end
  58.168 +    else
  58.169 +    begin
  58.170 +`ifdef CFG_MC_DIVIDE_ENABLED
  58.171 +        divide_by_zero_x <= `FALSE;
  58.172 +`endif
  58.173 +        case (state)
  58.174 +        `LM32_MC_STATE_IDLE:
  58.175 +        begin
  58.176 +            if (stall_d == `FALSE)                 
  58.177 +            begin          
  58.178 +                cycles <= `LM32_WORD_WIDTH;
  58.179 +                p <= 32'b0;
  58.180 +                a <= operand_0_d;
  58.181 +                b <= operand_1_d;                    
  58.182 +`ifdef CFG_MC_DIVIDE_ENABLED
  58.183 +                if (divide_d == `TRUE)
  58.184 +                    state <= `LM32_MC_STATE_DIVIDE;
  58.185 +                if (modulus_d == `TRUE)
  58.186 +                    state <= `LM32_MC_STATE_MODULUS;
  58.187 +`endif                    
  58.188 +`ifdef CFG_MC_MULTIPLY_ENABLED
  58.189 +                if (multiply_d == `TRUE)
  58.190 +                    state <= `LM32_MC_STATE_MULTIPLY;
  58.191 +`endif
  58.192 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED
  58.193 +                if (shift_left_d == `TRUE)
  58.194 +                begin
  58.195 +                    state <= `LM32_MC_STATE_SHIFT_LEFT;
  58.196 +                    sign_extend_x <= sign_extend_d;
  58.197 +                    cycles <= operand_1_d[4:0];
  58.198 +                    a <= operand_0_d;
  58.199 +                    b <= operand_0_d;
  58.200 +                end
  58.201 +                if (shift_right_d == `TRUE)
  58.202 +                begin
  58.203 +                    state <= `LM32_MC_STATE_SHIFT_RIGHT;
  58.204 +                    sign_extend_x <= sign_extend_d;
  58.205 +                    cycles <= operand_1_d[4:0];
  58.206 +                    a <= operand_0_d;
  58.207 +                    b <= operand_0_d;
  58.208 +                end
  58.209 +`endif
  58.210 +            end            
  58.211 +        end
  58.212 +`ifdef CFG_MC_DIVIDE_ENABLED
  58.213 +        `LM32_MC_STATE_DIVIDE:
  58.214 +        begin
  58.215 +            if (t[32] == 1'b0)
  58.216 +            begin
  58.217 +                p <= t[31:0];
  58.218 +                a <= {a[`LM32_WORD_WIDTH-2:0], 1'b1};
  58.219 +            end
  58.220 +            else 
  58.221 +            begin
  58.222 +                p <= {p[`LM32_WORD_WIDTH-2:0], a[`LM32_WORD_WIDTH-1]};
  58.223 +                a <= {a[`LM32_WORD_WIDTH-2:0], 1'b0};
  58.224 +            end
  58.225 +            result_x <= a;
  58.226 +            if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE))
  58.227 +            begin
  58.228 +                // Check for divide by zero
  58.229 +                divide_by_zero_x <= b == {`LM32_WORD_WIDTH{1'b0}};
  58.230 +                state <= `LM32_MC_STATE_IDLE;
  58.231 +            end
  58.232 +            cycles <= cycles - 1'b1;
  58.233 +        end
  58.234 +        `LM32_MC_STATE_MODULUS:
  58.235 +        begin
  58.236 +            if (t[32] == 1'b0)
  58.237 +            begin
  58.238 +                p <= t[31:0];
  58.239 +                a <= {a[`LM32_WORD_WIDTH-2:0], 1'b1};
  58.240 +            end
  58.241 +            else 
  58.242 +            begin
  58.243 +                p <= {p[`LM32_WORD_WIDTH-2:0], a[`LM32_WORD_WIDTH-1]};
  58.244 +                a <= {a[`LM32_WORD_WIDTH-2:0], 1'b0};
  58.245 +            end
  58.246 +            result_x <= p;
  58.247 +            if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE))
  58.248 +            begin
  58.249 +                // Check for divide by zero
  58.250 +                divide_by_zero_x <= b == {`LM32_WORD_WIDTH{1'b0}};
  58.251 +                state <= `LM32_MC_STATE_IDLE;
  58.252 +            end
  58.253 +            cycles <= cycles - 1'b1;
  58.254 +        end
  58.255 +`endif        
  58.256 +`ifdef CFG_MC_MULTIPLY_ENABLED
  58.257 +        `LM32_MC_STATE_MULTIPLY:
  58.258 +        begin
  58.259 +            if (b[0] == 1'b1)
  58.260 +                p <= p + a;
  58.261 +            b <= {1'b0, b[`LM32_WORD_WIDTH-1:1]};
  58.262 +            a <= {a[`LM32_WORD_WIDTH-2:0], 1'b0};
  58.263 +            result_x <= p;
  58.264 +            if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE))
  58.265 +                state <= `LM32_MC_STATE_IDLE;
  58.266 +            cycles <= cycles - 1'b1;
  58.267 +        end
  58.268 +`endif     
  58.269 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED
  58.270 +        `LM32_MC_STATE_SHIFT_LEFT:
  58.271 +        begin       
  58.272 +            a <= {a[`LM32_WORD_WIDTH-2:0], 1'b0};
  58.273 +            result_x <= a;
  58.274 +            if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE))
  58.275 +                state <= `LM32_MC_STATE_IDLE;
  58.276 +            cycles <= cycles - 1'b1;
  58.277 +        end
  58.278 +        `LM32_MC_STATE_SHIFT_RIGHT:
  58.279 +        begin       
  58.280 +            b <= {fill_value, b[`LM32_WORD_WIDTH-1:1]};
  58.281 +            result_x <= b;
  58.282 +            if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE))
  58.283 +                state <= `LM32_MC_STATE_IDLE;
  58.284 +            cycles <= cycles - 1'b1;
  58.285 +        end
  58.286 +`endif   
  58.287 +        endcase
  58.288 +    end
  58.289 +end 
  58.290 +
  58.291 +endmodule

    59.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    59.2 +++ b/rtl/lm32_multiplier.v	Tue Mar 08 09:40:42 2011 +0000
    59.3 @@ -0,0 +1,99 @@
    59.4 +// =============================================================================
    59.5 +//                           COPYRIGHT NOTICE
    59.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation
    59.7 +// ALL RIGHTS RESERVED
    59.8 +// This confidential and proprietary software may be used only as authorised by
    59.9 +// a licensing agreement from Lattice Semiconductor Corporation.
   59.10 +// The entire notice above must be reproduced on all authorized copies and
   59.11 +// copies may only be made to the extent permitted by a licensing agreement from
   59.12 +// Lattice Semiconductor Corporation.
   59.13 +//
   59.14 +// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
   59.15 +// 5555 NE Moore Court                            408-826-6000 (other locations)
   59.16 +// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
   59.17 +// U.S.A                                   email: techsupport@latticesemi.com
   59.18 +// =============================================================================/
   59.19 +//                         FILE DETAILS
   59.20 +// Project          : LatticeMico32
   59.21 +// File             : lm32_multiplier.v
   59.22 +// Title            : Pipelined multiplier.
   59.23 +// Dependencies     : lm32_include.v
   59.24 +// Version          : 6.1.17
   59.25 +//                  : Initial Release
   59.26 +// Version          : 7.0SP2, 3.0
   59.27 +//                  : No Change
   59.28 +// Version          : 3.1
   59.29 +//                  : No Change
   59.30 +// =============================================================================
   59.31 +                  
   59.32 +`include "lm32_include.v"
   59.33 +
   59.34 +/////////////////////////////////////////////////////
   59.35 +// Module interface
   59.36 +/////////////////////////////////////////////////////
   59.37 +
   59.38 +module lm32_multiplier (
   59.39 +    // ----- Inputs -----
   59.40 +    clk_i,
   59.41 +    rst_i,
   59.42 +    stall_x,
   59.43 +    stall_m,
   59.44 +    operand_0,
   59.45 +    operand_1,
   59.46 +    // ----- Ouputs -----
   59.47 +    result
   59.48 +    );
   59.49 +
   59.50 +/////////////////////////////////////////////////////
   59.51 +// Inputs
   59.52 +/////////////////////////////////////////////////////
   59.53 +
   59.54 +input clk_i;                            // Clock 
   59.55 +input rst_i;                            // Reset
   59.56 +input stall_x;                          // Stall instruction in X stage
   59.57 +input stall_m;                          // Stall instruction in M stage
   59.58 +input [`LM32_WORD_RNG] operand_0;     	// Muliplicand
   59.59 +input [`LM32_WORD_RNG] operand_1;     	// Multiplier
   59.60 +
   59.61 +/////////////////////////////////////////////////////
   59.62 +// Outputs
   59.63 +/////////////////////////////////////////////////////
   59.64 +
   59.65 +output [`LM32_WORD_RNG] result;       	// Product of multiplication
   59.66 +reg    [`LM32_WORD_RNG] result;
   59.67 +
   59.68 +/////////////////////////////////////////////////////
   59.69 +// Internal nets and registers 
   59.70 +/////////////////////////////////////////////////////
   59.71 +
   59.72 +reg [`LM32_WORD_RNG] muliplicand; 
   59.73 +reg [`LM32_WORD_RNG] multiplier; 
   59.74 +reg [`LM32_WORD_RNG] product; 
   59.75 +
   59.76 +/////////////////////////////////////////////////////
   59.77 +// Sequential logic
   59.78 +/////////////////////////////////////////////////////
   59.79 +
   59.80 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
   59.81 +begin
   59.82 +    if (rst_i == `TRUE)
   59.83 +    begin
   59.84 +        muliplicand <= {`LM32_WORD_WIDTH{1'b0}};
   59.85 +        multiplier <= {`LM32_WORD_WIDTH{1'b0}};
   59.86 +        product <= {`LM32_WORD_WIDTH{1'b0}};
   59.87 +        result <= {`LM32_WORD_WIDTH{1'b0}};
   59.88 +    end
   59.89 +    else
   59.90 +    begin
   59.91 +        if (stall_x == `FALSE)
   59.92 +        begin    
   59.93 +            muliplicand <= operand_0;
   59.94 +            multiplier <= operand_1;
   59.95 +        end
   59.96 +        if (stall_m == `FALSE)
   59.97 +            product <= muliplicand * multiplier;
   59.98 +        result <= product;
   59.99 +    end
  59.100 +end
  59.101 +
  59.102 +endmodule

    60.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    60.2 +++ b/rtl/lm32_ram.v	Tue Mar 08 09:40:42 2011 +0000
    60.3 @@ -0,0 +1,294 @@
    60.4 +// =============================================================================
    60.5 +//                           COPYRIGHT NOTICE
    60.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation
    60.7 +// ALL RIGHTS RESERVED
    60.8 +// This confidential and proprietary software may be used only as authorised by
    60.9 +// a licensing agreement from Lattice Semiconductor Corporation.
   60.10 +// The entire notice above must be reproduced on all authorized copies and
   60.11 +// copies may only be made to the extent permitted by a licensing agreement from
   60.12 +// Lattice Semiconductor Corporation.
   60.13 +//
   60.14 +// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
   60.15 +// 5555 NE Moore Court                            408-826-6000 (other locations)
   60.16 +// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
   60.17 +// U.S.A                                   email: techsupport@latticesemi.com
   60.18 +// =============================================================================/
   60.19 +//                         FILE DETAILS
   60.20 +// Project          : LatticeMico32
   60.21 +// File             : lm32_ram.v
   60.22 +// Title            : Pseudo dual-port RAM.
   60.23 +// Version          : 6.1.17
   60.24 +//                  : Initial Release
   60.25 +// Version          : 7.0SP2, 3.0
   60.26 +//                  : No Change
   60.27 +// Version          : 3.1
   60.28 +//                  : Options added to select EBRs (True-DP, Psuedo-DP, DQ, or
   60.29 +//                  : Distributed RAM).
   60.30 +// Version          : 3.2
   60.31 +//                  : EBRs use SYNC resets instead of ASYNC resets.
   60.32 +// Version          : 3.5
   60.33 +//                  : Added read-after-write hazard resolution when using true
   60.34 +//                  : dual-port EBRs
   60.35 +// =============================================================================
   60.36 +
   60.37 +`include "lm32_include.v"
   60.38 +
   60.39 +/////////////////////////////////////////////////////
   60.40 +// Module interface
   60.41 +/////////////////////////////////////////////////////
   60.42 +
   60.43 +module lm32_ram 
   60.44 +  (
   60.45 +   // ----- Inputs -------
   60.46 +   read_clk,
   60.47 +   write_clk,
   60.48 +   reset,
   60.49 +   enable_read,
   60.50 +   read_address,
   60.51 +   enable_write,
   60.52 +   write_address,
   60.53 +   write_data,
   60.54 +   write_enable,
   60.55 +   // ----- Outputs -------
   60.56 +   read_data
   60.57 +   );
   60.58 +   
   60.59 +   /*----------------------------------------------------------------------
   60.60 +    Parameters
   60.61 +    ----------------------------------------------------------------------*/
   60.62 +   parameter data_width = 1;               // Width of the data ports
   60.63 +   parameter address_width = 1;            // Width of the address ports
   60.64 +`ifdef PLATFORM_LATTICE
   60.65 +   parameter RAM_IMPLEMENTATION = "AUTO";  // Implement memory in EBRs, else
   60.66 +                                           // let synthesis tool select best 
   60.67 +                                           // possible solution (EBR or LUT)
   60.68 +   parameter RAM_TYPE = "RAM_DP";          // Type of EBR to be used
   60.69 +`endif
   60.70 +   
   60.71 +   /*----------------------------------------------------------------------
   60.72 +    Inputs
   60.73 +    ----------------------------------------------------------------------*/
   60.74 +   input read_clk;                         // Read clock
   60.75 +   input write_clk;                        // Write clock
   60.76 +   input reset;                            // Reset
   60.77 +   
   60.78 +   input enable_read;                      // Access enable
   60.79 +   input [address_width-1:0] read_address; // Read/write address
   60.80 +   input enable_write;                     // Access enable
   60.81 +   input [address_width-1:0] write_address;// Read/write address
   60.82 +   input [data_width-1:0] write_data;      // Data to write to specified address
   60.83 +   input write_enable;                     // Write enable
   60.84 +   
   60.85 +   /*----------------------------------------------------------------------
   60.86 +    Outputs
   60.87 +    ----------------------------------------------------------------------*/
   60.88 +   output [data_width-1:0] read_data;      // Data read from specified addess
   60.89 +   wire   [data_width-1:0] read_data;
   60.90 +
   60.91 +`ifdef PLATFORM_LATTICE
   60.92 +   generate
   60.93 +      
   60.94 +      if ( RAM_IMPLEMENTATION == "EBR" )
   60.95 +	begin
   60.96 +	   if ( RAM_TYPE == "RAM_DP" )
   60.97 +	     begin
   60.98 +		pmi_ram_dp 
   60.99 +		  #( 
  60.100 +		     // ----- Parameters -----
  60.101 +		     .pmi_wr_addr_depth(1<<address_width),
  60.102 +		     .pmi_wr_addr_width(address_width),
  60.103 +		     .pmi_wr_data_width(data_width),
  60.104 +		     .pmi_rd_addr_depth(1<<address_width),
  60.105 +		     .pmi_rd_addr_width(address_width),
  60.106 +		     .pmi_rd_data_width(data_width),
  60.107 +		     .pmi_regmode("noreg"),
  60.108 +		     .pmi_gsr("enable"),
  60.109 +		     .pmi_resetmode("sync"),
  60.110 +		     .pmi_init_file("none"),
  60.111 +		     .pmi_init_file_format("binary"),
  60.112 +		     .pmi_family(`LATTICE_FAMILY),
  60.113 +		     .module_type("pmi_ram_dp")
  60.114 +		     )
  60.115 +		lm32_ram_inst
  60.116 +		  (
  60.117 +		   // ----- Inputs -----
  60.118 +		   .Data(write_data),
  60.119 +		   .WrAddress(write_address),
  60.120 +		   .RdAddress(read_address),
  60.121 +		   .WrClock(write_clk),
  60.122 +		   .RdClock(read_clk),
  60.123 +		   .WrClockEn(enable_write),
  60.124 +		   .RdClockEn(enable_read),
  60.125 +		   .WE(write_enable),
  60.126 +		   .Reset(reset),
  60.127 +		   // ----- Outputs -----
  60.128 +		   .Q(read_data)
  60.129 +		   );
  60.130 +	     end
  60.131 +	   else
  60.132 +	     begin
  60.133 +		// True Dual-Port EBR
  60.134 +		wire   [data_width-1:0] read_data_A, read_data_B;
  60.135 +		reg [data_width-1:0] 	raw_data, raw_data_nxt;
  60.136 +		reg 			raw, raw_nxt;
  60.137 +		
  60.138 +		/*----------------------------------------------------------------------
  60.139 +		 Is a read being performed in the same cycle as a write? Indicate this
  60.140 +		 event with a RAW hazard signal that is released only when a new read
  60.141 +		 or write occurs later.
  60.142 +		 ----------------------------------------------------------------------*/
  60.143 +		always @(/*AUTOSENSE*/enable_read or enable_write
  60.144 +			 or raw or raw_data or read_address
  60.145 +			 or write_address or write_data
  60.146 +			 or write_enable)
  60.147 +		  if (// Read
  60.148 +		      enable_read
  60.149 +		      // Write
  60.150 +		      && enable_write && write_enable
  60.151 +		      // Read and write address match
  60.152 +		      && (read_address == write_address))
  60.153 +		    begin
  60.154 +		       raw_data_nxt = write_data;
  60.155 +		       raw_nxt = 1'b1;
  60.156 +		    end
  60.157 +		  else
  60.158 +		    if (raw && (enable_read == 1'b0) && (enable_write == 1'b0))
  60.159 +		      begin
  60.160 +			 raw_data_nxt = raw_data;
  60.161 +			 raw_nxt = 1'b1;
  60.162 +		      end
  60.163 +		    else
  60.164 +		      begin
  60.165 +			 raw_data_nxt = raw_data;
  60.166 +			 raw_nxt = 1'b0;
  60.167 +		      end
  60.168 +		
  60.169 +		// Send back write data in case of a RAW hazard; else send back
  60.170 +		// data from memory
  60.171 +		assign read_data = raw ? raw_data : read_data_B;
  60.172 +		
  60.173 +		/*----------------------------------------------------------------------
  60.174 +		 Sequential Logic
  60.175 +		 ----------------------------------------------------------------------*/
  60.176 +		always @(posedge read_clk)
  60.177 +		  if (reset)
  60.178 +		    begin
  60.179 +		       raw_data <= #1 0;
  60.180 +		       raw <= #1 1'b0;
  60.181 +		    end
  60.182 +		  else
  60.183 +		    begin
  60.184 +		       raw_data <= #1 raw_data_nxt;
  60.185 +		       raw <= #1 raw_nxt;
  60.186 +		    end
  60.187 +		
  60.188 +		pmi_ram_dp_true 
  60.189 +		  #( 
  60.190 +		     // ----- Parameters -----
  60.191 +		     .pmi_addr_depth_a(1<<address_width),
  60.192 +		     .pmi_addr_width_a(address_width),
  60.193 +		     .pmi_data_width_a(data_width),
  60.194 +		     .pmi_addr_depth_b(1<<address_width),
  60.195 +		     .pmi_addr_width_b(address_width),
  60.196 +		     .pmi_data_width_b(data_width),
  60.197 +		     .pmi_regmode_a("noreg"),
  60.198 +		     .pmi_regmode_b("noreg"),
  60.199 +		     .pmi_gsr("enable"),
  60.200 +		     .pmi_resetmode("sync"),
  60.201 +		     .pmi_init_file("none"),
  60.202 +		     .pmi_init_file_format("binary"),
  60.203 +		     .pmi_family(`LATTICE_FAMILY),
  60.204 +		     .module_type("pmi_ram_dp_true")
  60.205 +		     )
  60.206 +		lm32_ram_inst
  60.207 +		  (
  60.208 +		   // ----- Inputs -----
  60.209 +		   .DataInA(write_data),
  60.210 +		   .DataInB(write_data),
  60.211 +		   .AddressA(write_address),
  60.212 +		   .AddressB(read_address),
  60.213 +		   .ClockA(write_clk),
  60.214 +		   .ClockB(read_clk),
  60.215 +		   .ClockEnA(enable_write),
  60.216 +		   .ClockEnB(enable_read),
  60.217 +		   .WrA(write_enable),
  60.218 +		   .WrB(`FALSE),
  60.219 +		   .ResetA(reset),
  60.220 +		   .ResetB(reset),
  60.221 +		   // ----- Outputs -----
  60.222 +		   .QA(read_data_A),
  60.223 +		   .QB(read_data_B)
  60.224 +		   );
  60.225 +	     end
  60.226 +	end
  60.227 +	else if ( RAM_IMPLEMENTATION == "SLICE" )
  60.228 +	  begin
  60.229 +	     reg [address_width-1:0] ra; // Registered read address
  60.230 +	     
  60.231 +	     pmi_distributed_dpram 
  60.232 +	       #(
  60.233 +		 // ----- Parameters -----
  60.234 +		 .pmi_addr_depth(1<<address_width),
  60.235 +		 .pmi_addr_width(address_width),
  60.236 +		 .pmi_data_width(data_width),
  60.237 +		 .pmi_regmode("noreg"),
  60.238 +		 .pmi_init_file("none"),
  60.239 +		 .pmi_init_file_format("binary"),
  60.240 +		 .pmi_family(`LATTICE_FAMILY),
  60.241 +		 .module_type("pmi_distributed_dpram")
  60.242 +		 )
  60.243 +	     pmi_distributed_dpram_inst
  60.244 +	       (
  60.245 +		// ----- Inputs -----
  60.246 +		.WrAddress(write_address),
  60.247 +		.Data(write_data),
  60.248 +		.WrClock(write_clk),
  60.249 +		.WE(write_enable),
  60.250 +		.WrClockEn(enable_write),
  60.251 +		.RdAddress(ra),
  60.252 +		.RdClock(read_clk),
  60.253 +		.RdClockEn(enable_read),
  60.254 +		.Reset(reset),
  60.255 +		// ----- Outputs -----
  60.256 +		.Q(read_data)
  60.257 +		);
  60.258 +	     
  60.259 +	     always @(posedge read_clk)
  60.260 +	       if (enable_read)
  60.261 +		 ra <= read_address;
  60.262 +	  end
  60.263 +      
  60.264 +	else 
  60.265 +	  begin
  60.266 +`endif
  60.267 +	     /*----------------------------------------------------------------------
  60.268 +	      Internal nets and registers
  60.269 +	      ----------------------------------------------------------------------*/
  60.270 +	     reg [data_width-1:0]    mem[0:(1<<address_width)-1]; // The RAM
  60.271 +	     reg [address_width-1:0] ra; // Registered read address
  60.272 +	     
  60.273 +	     /*----------------------------------------------------------------------
  60.274 +	      Combinational Logic
  60.275 +	      ----------------------------------------------------------------------*/
  60.276 +	     // Read port
  60.277 +	     assign read_data = mem[ra]; 
  60.278 +	     
  60.279 +	     /*----------------------------------------------------------------------
  60.280 +	      Sequential Logic
  60.281 +	      ----------------------------------------------------------------------*/
  60.282 +	     // Write port
  60.283 +	     always @(posedge write_clk)
  60.284 +	       if ((write_enable == `TRUE) && (enable_write == `TRUE))
  60.285 +		 mem[write_address] <= write_data; 
  60.286 +	     
  60.287 +	     // Register read address for use on next cycle
  60.288 +	     always @(posedge read_clk)
  60.289 +	       if (enable_read)
  60.290 +		 ra <= read_address;
  60.291 +	     
  60.292 +`ifdef PLATFORM_LATTICE
  60.293 +	  end
  60.294 +
  60.295 +   endgenerate
  60.296 +`endif
  60.297 +endmodule

    61.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    61.2 +++ b/rtl/lm32_shifter.v	Tue Mar 08 09:40:42 2011 +0000
    61.3 @@ -0,0 +1,134 @@
    61.4 +// =============================================================================
    61.5 +//                           COPYRIGHT NOTICE
    61.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation
    61.7 +// ALL RIGHTS RESERVED
    61.8 +// This confidential and proprietary software may be used only as authorised by
    61.9 +// a licensing agreement from Lattice Semiconductor Corporation.
   61.10 +// The entire notice above must be reproduced on all authorized copies and
   61.11 +// copies may only be made to the extent permitted by a licensing agreement from
   61.12 +// Lattice Semiconductor Corporation.
   61.13 +//
   61.14 +// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
   61.15 +// 5555 NE Moore Court                            408-826-6000 (other locations)
   61.16 +// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
   61.17 +// U.S.A                                   email: techsupport@latticesemi.com
   61.18 +// =============================================================================/
   61.19 +//                         FILE DETAILS
   61.20 +// Project          : LatticeMico32
   61.21 +// File             : lm32_shifter.v
   61.22 +// Title            : Barrel shifter
   61.23 +// Dependencies     : lm32_include.v
   61.24 +// Version          : 6.1.17
   61.25 +//                  : Initial Release
   61.26 +// Version          : 7.0SP2, 3.0
   61.27 +//                  : No Change
   61.28 +// Version          : 3.1
   61.29 +//                  : No Change
   61.30 +// =============================================================================
   61.31 +
   61.32 +`include "lm32_include.v"
   61.33 +
   61.34 +/////////////////////////////////////////////////////
   61.35 +// Module interface
   61.36 +/////////////////////////////////////////////////////
   61.37 +
   61.38 +module lm32_shifter (
   61.39 +    // ----- Inputs -------
   61.40 +    clk_i,
   61.41 +    rst_i,
   61.42 +    stall_x,
   61.43 +    direction_x,
   61.44 +    sign_extend_x,
   61.45 +    operand_0_x,
   61.46 +    operand_1_x,
   61.47 +    // ----- Outputs -------
   61.48 +    shifter_result_m
   61.49 +    );
   61.50 +
   61.51 +/////////////////////////////////////////////////////
   61.52 +// Inputs
   61.53 +/////////////////////////////////////////////////////
   61.54 +
   61.55 +input clk_i;                                // Clock
   61.56 +input rst_i;                                // Reset
   61.57 +input stall_x;                              // Stall instruction in X stage
   61.58 +input direction_x;                          // Direction to shift
   61.59 +input sign_extend_x;                        // Whether shift is arithmetic (1'b1) or logical (1'b0)
   61.60 +input [`LM32_WORD_RNG] operand_0_x;         // Operand to shift
   61.61 +input [`LM32_WORD_RNG] operand_1_x;         // Operand that specifies how many bits to shift by
   61.62 +
   61.63 +/////////////////////////////////////////////////////
   61.64 +// Outputs
   61.65 +/////////////////////////////////////////////////////
   61.66 +
   61.67 +output [`LM32_WORD_RNG] shifter_result_m;   // Result of shift
   61.68 +wire   [`LM32_WORD_RNG] shifter_result_m;
   61.69 +
   61.70 +/////////////////////////////////////////////////////
   61.71 +// Internal nets and registers 
   61.72 +/////////////////////////////////////////////////////
   61.73 +
   61.74 +reg direction_m;
   61.75 +reg [`LM32_WORD_RNG] left_shift_result;
   61.76 +reg [`LM32_WORD_RNG] right_shift_result;
   61.77 +reg [`LM32_WORD_RNG] left_shift_operand;
   61.78 +wire [`LM32_WORD_RNG] right_shift_operand;
   61.79 +wire fill_value;
   61.80 +wire [`LM32_WORD_RNG] right_shift_in;
   61.81 +
   61.82 +integer shift_idx_0;
   61.83 +integer shift_idx_1;
   61.84 +
   61.85 +/////////////////////////////////////////////////////
   61.86 +// Combinational Logic
   61.87 +/////////////////////////////////////////////////////
   61.88 +    
   61.89 +// Select operands - To perform a left shift, we reverse the bits and perform a right shift
   61.90 +always @(*)
   61.91 +begin
   61.92 +    for (shift_idx_0 = 0; shift_idx_0 < `LM32_WORD_WIDTH; shift_idx_0 = shift_idx_0 + 1)
   61.93 +        left_shift_operand[`LM32_WORD_WIDTH-1-shift_idx_0] = operand_0_x[shift_idx_0];
   61.94 +end
   61.95 +assign right_shift_operand = direction_x == `LM32_SHIFT_OP_LEFT ? left_shift_operand : operand_0_x;
   61.96 +
   61.97 +// Determine fill value for right shift - Sign bit for arithmetic shift, or zero for logical shift
   61.98 +assign fill_value = (sign_extend_x == `TRUE) && (direction_x == `LM32_SHIFT_OP_RIGHT) 
   61.99 +                      ? operand_0_x[`LM32_WORD_WIDTH-1] 
  61.100 +                      : 1'b0;
  61.101 +
  61.102 +// Determine bits to shift in for right shift or rotate
  61.103 +assign right_shift_in = {`LM32_WORD_WIDTH{fill_value}};
  61.104 +
  61.105 +// Reverse bits to get left shift result
  61.106 +always @(*)
  61.107 +begin
  61.108 +    for (shift_idx_1 = 0; shift_idx_1 < `LM32_WORD_WIDTH; shift_idx_1 = shift_idx_1 + 1)
  61.109 +        left_shift_result[`LM32_WORD_WIDTH-1-shift_idx_1] = right_shift_result[shift_idx_1];
  61.110 +end
  61.111 +
  61.112 +// Select result 
  61.113 +assign shifter_result_m = direction_m == `LM32_SHIFT_OP_LEFT ? left_shift_result : right_shift_result;
  61.114 +    
  61.115 +/////////////////////////////////////////////////////
  61.116 +// Sequential Logic
  61.117 +/////////////////////////////////////////////////////
  61.118 +
  61.119 +// Perform right shift
  61.120 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  61.121 +begin
  61.122 +    if (rst_i == `TRUE)
  61.123 +    begin
  61.124 +        right_shift_result <= {`LM32_WORD_WIDTH{1'b0}};
  61.125 +        direction_m <= `FALSE;
  61.126 +    end
  61.127 +    else
  61.128 +    begin
  61.129 +        if (stall_x == `FALSE)
  61.130 +        begin
  61.131 +            right_shift_result <= {right_shift_in, right_shift_operand} >> operand_1_x[`LM32_SHIFT_RNG];
  61.132 +            direction_m <= direction_x;
  61.133 +        end
  61.134 +    end
  61.135 +end 
  61.136 +    
  61.137 +endmodule

    62.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    62.2 +++ b/rtl/lm32_top.v	Tue Mar 08 09:40:42 2011 +0000
    62.3 @@ -0,0 +1,355 @@
    62.4 +// =============================================================================
    62.5 +//                           COPYRIGHT NOTICE
    62.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation
    62.7 +// ALL RIGHTS RESERVED
    62.8 +// This confidential and proprietary software may be used only as authorised by
    62.9 +// a licensing agreement from Lattice Semiconductor Corporation.
   62.10 +// The entire notice above must be reproduced on all authorized copies and
   62.11 +// copies may only be made to the extent permitted by a licensing agreement from
   62.12 +// Lattice Semiconductor Corporation.
   62.13 +//
   62.14 +// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
   62.15 +// 5555 NE Moore Court                            408-826-6000 (other locations)
   62.16 +// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
   62.17 +// U.S.A                                   email: techsupport@latticesemi.com
   62.18 +// =============================================================================/
   62.19 +//                         FILE DETAILS
   62.20 +// Project          : LatticeMico32
   62.21 +// File             : lm32_top.v
   62.22 +// Title            : Top-level of CPU.
   62.23 +// Dependencies     : lm32_include.v
   62.24 +// Version          : 6.1.17
   62.25 +//                  : removed SPI - 04/12/07
   62.26 +// Version          : 7.0SP2, 3.0
   62.27 +//                  : No Change
   62.28 +// Version          : 3.1
   62.29 +//                  : No Change
   62.30 +// =============================================================================
   62.31 +
   62.32 +`include "lm32_include.v"
   62.33 +
   62.34 +/////////////////////////////////////////////////////
   62.35 +// Module interface
   62.36 +/////////////////////////////////////////////////////
   62.37 +
   62.38 +module lm32_top (
   62.39 +    // ----- Inputs -------
   62.40 +    clk_i,
   62.41 +    rst_i,
   62.42 +    // From external devices
   62.43 +`ifdef CFG_INTERRUPTS_ENABLED
   62.44 +    interrupt,
   62.45 +`endif
   62.46 +    // From user logic
   62.47 +`ifdef CFG_USER_ENABLED
   62.48 +    user_result,
   62.49 +    user_complete,
   62.50 +`endif     
   62.51 +`ifdef CFG_IWB_ENABLED
   62.52 +    // Instruction Wishbone master
   62.53 +    I_DAT_I,
   62.54 +    I_ACK_I,
   62.55 +    I_ERR_I,
   62.56 +    I_RTY_I,
   62.57 +`endif
   62.58 +    // Data Wishbone master
   62.59 +    D_DAT_I,
   62.60 +    D_ACK_I,
   62.61 +    D_ERR_I,
   62.62 +    D_RTY_I,
   62.63 +    // ----- Outputs -------
   62.64 +`ifdef CFG_USER_ENABLED    
   62.65 +    user_valid,
   62.66 +    user_opcode,
   62.67 +    user_operand_0,
   62.68 +    user_operand_1,
   62.69 +`endif    
   62.70 +`ifdef CFG_IWB_ENABLED
   62.71 +    // Instruction Wishbone master
   62.72 +    I_DAT_O,
   62.73 +    I_ADR_O,
   62.74 +    I_CYC_O,
   62.75 +    I_SEL_O,
   62.76 +    I_STB_O,
   62.77 +    I_WE_O,
   62.78 +    I_CTI_O,
   62.79 +    I_LOCK_O,
   62.80 +    I_BTE_O,
   62.81 +`endif
   62.82 +    // Data Wishbone master
   62.83 +    D_DAT_O,
   62.84 +    D_ADR_O,
   62.85 +    D_CYC_O,
   62.86 +    D_SEL_O,
   62.87 +    D_STB_O,
   62.88 +    D_WE_O,
   62.89 +    D_CTI_O,
   62.90 +    D_LOCK_O,
   62.91 +    D_BTE_O
   62.92 +    );
   62.93 +
   62.94 +/////////////////////////////////////////////////////
   62.95 +// Inputs
   62.96 +/////////////////////////////////////////////////////
   62.97 +
   62.98 +input clk_i;                                    // Clock
   62.99 +input rst_i;                                    // Reset
  62.100 +
  62.101 +`ifdef CFG_INTERRUPTS_ENABLED
  62.102 +input [`LM32_INTERRUPT_RNG] interrupt;          // Interrupt pins
  62.103 +`endif
  62.104 +
  62.105 +`ifdef CFG_USER_ENABLED
  62.106 +input [`LM32_WORD_RNG] user_result;             // User-defined instruction result
  62.107 +input user_complete;                            // Indicates the user-defined instruction result is valid
  62.108 +`endif    
  62.109 +
  62.110 +`ifdef CFG_IWB_ENABLED
  62.111 +input [`LM32_WORD_RNG] I_DAT_I;                 // Instruction Wishbone interface read data
  62.112 +input I_ACK_I;                                  // Instruction Wishbone interface acknowledgement
  62.113 +input I_ERR_I;                                  // Instruction Wishbone interface error
  62.114 +input I_RTY_I;                                  // Instruction Wishbone interface retry
  62.115 +`endif
  62.116 +
  62.117 +input [`LM32_WORD_RNG] D_DAT_I;                 // Data Wishbone interface read data
  62.118 +input D_ACK_I;                                  // Data Wishbone interface acknowledgement
  62.119 +input D_ERR_I;                                  // Data Wishbone interface error
  62.120 +input D_RTY_I;                                  // Data Wishbone interface retry
  62.121 +
  62.122 +/////////////////////////////////////////////////////
  62.123 +// Outputs
  62.124 +/////////////////////////////////////////////////////
  62.125 +
  62.126 +`ifdef CFG_USER_ENABLED
  62.127 +output user_valid;                              // Indicates that user_opcode and user_operand_* are valid
  62.128 +wire   user_valid;
  62.129 +output [`LM32_USER_OPCODE_RNG] user_opcode;     // User-defined instruction opcode
  62.130 +reg    [`LM32_USER_OPCODE_RNG] user_opcode;
  62.131 +output [`LM32_WORD_RNG] user_operand_0;         // First operand for user-defined instruction
  62.132 +wire   [`LM32_WORD_RNG] user_operand_0;
  62.133 +output [`LM32_WORD_RNG] user_operand_1;         // Second operand for user-defined instruction
  62.134 +wire   [`LM32_WORD_RNG] user_operand_1;
  62.135 +`endif
  62.136 +
  62.137 +`ifdef CFG_IWB_ENABLED
  62.138 +output [`LM32_WORD_RNG] I_DAT_O;                // Instruction Wishbone interface write data
  62.139 +wire   [`LM32_WORD_RNG] I_DAT_O;
  62.140 +output [`LM32_WORD_RNG] I_ADR_O;                // Instruction Wishbone interface address
  62.141 +wire   [`LM32_WORD_RNG] I_ADR_O;
  62.142 +output I_CYC_O;                                 // Instruction Wishbone interface cycle
  62.143 +wire   I_CYC_O;
  62.144 +output [`LM32_BYTE_SELECT_RNG] I_SEL_O;         // Instruction Wishbone interface byte select
  62.145 +wire   [`LM32_BYTE_SELECT_RNG] I_SEL_O;
  62.146 +output I_STB_O;                                 // Instruction Wishbone interface strobe
  62.147 +wire   I_STB_O;
  62.148 +output I_WE_O;                                  // Instruction Wishbone interface write enable
  62.149 +wire   I_WE_O;
  62.150 +output [`LM32_CTYPE_RNG] I_CTI_O;               // Instruction Wishbone interface cycle type 
  62.151 +wire   [`LM32_CTYPE_RNG] I_CTI_O;
  62.152 +output I_LOCK_O;                                // Instruction Wishbone interface lock bus
  62.153 +wire   I_LOCK_O;
  62.154 +output [`LM32_BTYPE_RNG] I_BTE_O;               // Instruction Wishbone interface burst type 
  62.155 +wire   [`LM32_BTYPE_RNG] I_BTE_O;
  62.156 +`endif
  62.157 +
  62.158 +output [`LM32_WORD_RNG] D_DAT_O;                // Data Wishbone interface write data
  62.159 +wire   [`LM32_WORD_RNG] D_DAT_O;
  62.160 +output [`LM32_WORD_RNG] D_ADR_O;                // Data Wishbone interface address
  62.161 +wire   [`LM32_WORD_RNG] D_ADR_O;
  62.162 +output D_CYC_O;                                 // Data Wishbone interface cycle
  62.163 +wire   D_CYC_O;
  62.164 +output [`LM32_BYTE_SELECT_RNG] D_SEL_O;         // Data Wishbone interface byte select
  62.165 +wire   [`LM32_BYTE_SELECT_RNG] D_SEL_O;
  62.166 +output D_STB_O;                                 // Data Wishbone interface strobe
  62.167 +wire   D_STB_O;
  62.168 +output D_WE_O;                                  // Data Wishbone interface write enable
  62.169 +wire   D_WE_O;
  62.170 +output [`LM32_CTYPE_RNG] D_CTI_O;               // Data Wishbone interface cycle type 
  62.171 +wire   [`LM32_CTYPE_RNG] D_CTI_O;
  62.172 +output D_LOCK_O;                                // Date Wishbone interface lock bus
  62.173 +wire   D_LOCK_O;
  62.174 +output [`LM32_BTYPE_RNG] D_BTE_O;               // Data Wishbone interface burst type 
  62.175 +wire   [`LM32_BTYPE_RNG] D_BTE_O;
  62.176 +  
  62.177 +/////////////////////////////////////////////////////
  62.178 +// Internal nets and registers 
  62.179 +/////////////////////////////////////////////////////
  62.180 + 
  62.181 +`ifdef CFG_JTAG_ENABLED
  62.182 +// Signals between JTAG interface and CPU
  62.183 +wire [`LM32_BYTE_RNG] jtag_reg_d;
  62.184 +wire [`LM32_BYTE_RNG] jtag_reg_q;
  62.185 +wire jtag_update;
  62.186 +wire [2:0] jtag_reg_addr_d;
  62.187 +wire [2:0] jtag_reg_addr_q;
  62.188 +wire jtck;
  62.189 +wire jrstn;
  62.190 +`endif
  62.191 +
  62.192 +// TODO: get the trace signals out
  62.193 +`ifdef CFG_TRACE_ENABLED
  62.194 +// PC trace signals
  62.195 +wire [`LM32_PC_RNG] trace_pc;                   // PC to trace (address of next non-sequential instruction)
  62.196 +wire trace_pc_valid;                            // Indicates that a new trace PC is valid
  62.197 +wire trace_exception;                           // Indicates an exception has occured
  62.198 +wire [`LM32_EID_RNG] trace_eid;                 // Indicates what type of exception has occured
  62.199 +wire trace_eret;                                // Indicates an eret instruction has been executed
  62.200 +`ifdef CFG_DEBUG_ENABLED
  62.201 +wire trace_bret;                                // Indicates a bret instruction has been executed
  62.202 +`endif
  62.203 +`endif
  62.204 +
  62.205 +/////////////////////////////////////////////////////
  62.206 +// Functions
  62.207 +/////////////////////////////////////////////////////
  62.208 +
  62.209 +`include "lm32_functions.v"
  62.210 +/////////////////////////////////////////////////////
  62.211 +// Instantiations
  62.212 +///////////////////////////////////////////////////// 
  62.213 +
  62.214 +// LM32 CPU
  62.215 +lm32_cpu cpu (
  62.216 +    // ----- Inputs -------
  62.217 +    .clk_i                 (clk_i),
  62.218 +`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
  62.219 +    .clk_n_i               (clk_n),
  62.220 +`endif
  62.221 +    .rst_i                 (rst_i),
  62.222 +    // From external devices
  62.223 +`ifdef CFG_INTERRUPTS_ENABLED
  62.224 +    .interrupt             (interrupt),
  62.225 +`endif
  62.226 +    // From user logic
  62.227 +`ifdef CFG_USER_ENABLED
  62.228 +    .user_result           (user_result),
  62.229 +    .user_complete         (user_complete),
  62.230 +`endif     
  62.231 +`ifdef CFG_JTAG_ENABLED
  62.232 +    // From JTAG
  62.233 +    .jtag_clk              (jtck),
  62.234 +    .jtag_update           (jtag_update),
  62.235 +    .jtag_reg_q            (jtag_reg_q),
  62.236 +    .jtag_reg_addr_q       (jtag_reg_addr_q),
  62.237 +`endif
  62.238 +`ifdef CFG_IWB_ENABLED
  62.239 +     // Instruction Wishbone master
  62.240 +    .I_DAT_I               (I_DAT_I),
  62.241 +    .I_ACK_I               (I_ACK_I),
  62.242 +    .I_ERR_I               (I_ERR_I),
  62.243 +    .I_RTY_I               (I_RTY_I),
  62.244 +`endif
  62.245 +    // Data Wishbone master
  62.246 +    .D_DAT_I               (D_DAT_I),
  62.247 +    .D_ACK_I               (D_ACK_I),
  62.248 +    .D_ERR_I               (D_ERR_I),
  62.249 +    .D_RTY_I               (D_RTY_I),
  62.250 +    // ----- Outputs -------
  62.251 +`ifdef CFG_TRACE_ENABLED
  62.252 +    .trace_pc              (trace_pc),
  62.253 +    .trace_pc_valid        (trace_pc_valid),
  62.254 +    .trace_exception       (trace_exception),
  62.255 +    .trace_eid             (trace_eid),
  62.256 +    .trace_eret            (trace_eret),
  62.257 +`ifdef CFG_DEBUG_ENABLED
  62.258 +    .trace_bret            (trace_bret),
  62.259 +`endif
  62.260 +`endif
  62.261 +`ifdef CFG_JTAG_ENABLED
  62.262 +    .jtag_reg_d            (jtag_reg_d),
  62.263 +    .jtag_reg_addr_d       (jtag_reg_addr_d),
  62.264 +`endif
  62.265 +`ifdef CFG_USER_ENABLED    
  62.266 +    .user_valid            (user_valid),
  62.267 +    .user_opcode           (user_opcode),
  62.268 +    .user_operand_0        (user_operand_0),
  62.269 +    .user_operand_1        (user_operand_1),
  62.270 +`endif    
  62.271 +`ifdef CFG_IWB_ENABLED
  62.272 +    // Instruction Wishbone master
  62.273 +    .I_DAT_O               (I_DAT_O),
  62.274 +    .I_ADR_O               (I_ADR_O),
  62.275 +    .I_CYC_O               (I_CYC_O),
  62.276 +    .I_SEL_O               (I_SEL_O),
  62.277 +    .I_STB_O               (I_STB_O),
  62.278 +    .I_WE_O                (I_WE_O),
  62.279 +    .I_CTI_O               (I_CTI_O),
  62.280 +    .I_LOCK_O              (I_LOCK_O),
  62.281 +    .I_BTE_O               (I_BTE_O),
  62.282 +    `endif
  62.283 +    // Data Wishbone master
  62.284 +    .D_DAT_O               (D_DAT_O),
  62.285 +    .D_ADR_O               (D_ADR_O),
  62.286 +    .D_CYC_O               (D_CYC_O),
  62.287 +    .D_SEL_O               (D_SEL_O),
  62.288 +    .D_STB_O               (D_STB_O),
  62.289 +    .D_WE_O                (D_WE_O),
  62.290 +    .D_CTI_O               (D_CTI_O),
  62.291 +    .D_LOCK_O              (D_LOCK_O),
  62.292 +    .D_BTE_O               (D_BTE_O)
  62.293 +    );
  62.294 +
  62.295 +   wire TRACE_ACK_O;
  62.296 +   wire [`LM32_WORD_RNG] TRACE_DAT_O;
  62.297 +`ifdef CFG_TRACE_ENABLED
  62.298 +   lm32_trace trace_module (.clk_i	(clk_i),
  62.299 +			    .rst_i	(rst_i),
  62.300 +			    .stb_i	(DEBUG_STB_I & DEBUG_ADR_I[13]),
  62.301 +			    .we_i	(DEBUG_WE_I),
  62.302 +			    .sel_i	(DEBUG_SEL_I),
  62.303 +			    .dat_i	(DEBUG_DAT_I),
  62.304 +			    .adr_i	(DEBUG_ADR_I),
  62.305 +			    .trace_pc	(trace_pc),
  62.306 +			    .trace_eid	(trace_eid),
  62.307 +			    .trace_eret (trace_eret),
  62.308 +			    .trace_bret (trace_bret),
  62.309 +			    .trace_pc_valid (trace_pc_valid),
  62.310 +			    .trace_exception (trace_exception),
  62.311 +			    .ack_o	(TRACE_ACK_O),
  62.312 +			    .dat_o 	(TRACE_DAT_O));   
  62.313 +`else
  62.314 +   assign 		 TRACE_ACK_O = 0;
  62.315 +   assign 		 TRACE_DAT_O = 0;   
  62.316 +`endif   
  62.317 +`ifdef DEBUG_ROM
  62.318 +   wire ROM_ACK_O;
  62.319 +   wire [`LM32_WORD_RNG] ROM_DAT_O;
  62.320 +
  62.321 +   assign DEBUG_ACK_O = DEBUG_ADR_I[13] ? TRACE_ACK_O : ROM_ACK_O;
  62.322 +   assign DEBUG_DAT_O = DEBUG_ADR_I[13] ? TRACE_DAT_O : ROM_DAT_O;
  62.323 +   
  62.324 +   // ROM monitor
  62.325 +   lm32_monitor debug_rom (
  62.326 +			   // ----- Inputs -------
  62.327 +			   .clk_i                 (clk_i),
  62.328 +			   .rst_i                 (rst_i),
  62.329 +			   .MON_ADR_I             (DEBUG_ADR_I[10:2]),
  62.330 +			   .MON_STB_I             (DEBUG_STB_I & ~DEBUG_ADR_I[13]),
  62.331 +			   .MON_CYC_I             (DEBUG_CYC_I & ~DEBUG_ADR_I[13]),
  62.332 +			   .MON_WE_I              (DEBUG_WE_I),
  62.333 +			   .MON_SEL_I             (DEBUG_SEL_I),
  62.334 +			   .MON_DAT_I             (DEBUG_DAT_I),
  62.335 +			   // ----- Outputs ------    
  62.336 +			   .MON_RTY_O             (DEBUG_RTY_O),
  62.337 +			   .MON_ERR_O             (DEBUG_ERR_O),
  62.338 +			   .MON_ACK_O             (ROM_ACK_O),
  62.339 +			   .MON_DAT_O             (ROM_DAT_O)
  62.340 +			   );
  62.341 +`endif 
  62.342 +   
  62.343 +`ifdef CFG_JTAG_ENABLED		   
  62.344 +// JTAG cores 
  62.345 +jtag_cores jtag_cores (
  62.346 +    // ----- Inputs -----
  62.347 +    .reg_d                 (jtag_reg_d),
  62.348 +    .reg_addr_d            (jtag_reg_addr_d),
  62.349 +    // ----- Outputs -----
  62.350 +    .reg_update            (jtag_update),
  62.351 +    .reg_q                 (jtag_reg_q),
  62.352 +    .reg_addr_q            (jtag_reg_addr_q),
  62.353 +    .jtck                  (jtck),
  62.354 +    .jrstn                 (jrstn)
  62.355 +    );
  62.356 +`endif        
  62.357 +   
  62.358 +endmodule
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