1.1 --- a/lm32_instruction_unit.v Sun Mar 06 21:17:31 2011 +0000 1.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 1.3 @@ -1,839 +0,0 @@ 1.4 -// ============================================================================= 1.5 -// COPYRIGHT NOTICE 1.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation 1.7 -// ALL RIGHTS RESERVED 1.8 -// This confidential and proprietary software may be used only as authorised by 1.9 -// a licensing agreement from Lattice Semiconductor Corporation. 1.10 -// The entire notice above must be reproduced on all authorized copies and 1.11 -// copies may only be made to the extent permitted by a licensing agreement from 1.12 -// Lattice Semiconductor Corporation. 1.13 -// 1.14 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 1.15 -// 5555 NE Moore Court 408-826-6000 (other locations) 1.16 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 1.17 -// U.S.A email: techsupport@latticesemi.com 1.18 -// =============================================================================/ 1.19 -// FILE DETAILS 1.20 -// Project : LatticeMico32 1.21 -// File : lm32_instruction_unit.v 1.22 -// Title : Instruction unit 1.23 -// Dependencies : lm32_include.v 1.24 -// Version : 6.1.17 1.25 -// : Initial Release 1.26 -// Version : 7.0SP2, 3.0 1.27 -// : No Change 1.28 -// Version : 3.1 1.29 -// : Support for static branch prediction is added. Fetching of 1.30 -// : instructions can also be altered by branches predicted in D 1.31 -// : stage of pipeline, and mispredicted branches in the X and M 1.32 -// : stages of the pipeline. 1.33 -// Version : 3.2 1.34 -// : EBRs use SYNC resets instead of ASYNC resets. 1.35 -// Version : 3.3 1.36 -// : Support for a non-cacheable Instruction Memory that has a 1.37 -// : single-cycle access latency. This memory can be accessed by 1.38 -// : data port of LM32 (so that debugger has access to it). 1.39 -// Version : 3.4 1.40 -// : No change 1.41 -// Version : 3.5 1.42 -// : Bug fix: Inline memory is correctly generated if it is not a 1.43 -// : power-of-two. 1.44 -// : Bug fix: Fixed a bug that caused LM32 (configured without 1.45 -// : instruction cache) to lock up in to an infinite loop due to a 1.46 -// : instruction bus error when EBA was set to instruction inline 1.47 -// : memory. 1.48 -// ============================================================================= 1.49 - 1.50 -`include "lm32_include.v" 1.51 - 1.52 -///////////////////////////////////////////////////// 1.53 -// Module interface 1.54 -///////////////////////////////////////////////////// 1.55 - 1.56 -module lm32_instruction_unit ( 1.57 - // ----- Inputs ------- 1.58 - clk_i, 1.59 - rst_i, 1.60 - // From pipeline 1.61 - stall_a, 1.62 - stall_f, 1.63 - stall_d, 1.64 - stall_x, 1.65 - stall_m, 1.66 - valid_f, 1.67 - valid_d, 1.68 - kill_f, 1.69 - branch_predict_taken_d, 1.70 - branch_predict_address_d, 1.71 -`ifdef CFG_FAST_UNCONDITIONAL_BRANCH 1.72 - branch_taken_x, 1.73 - branch_target_x, 1.74 -`endif 1.75 - exception_m, 1.76 - branch_taken_m, 1.77 - branch_mispredict_taken_m, 1.78 - branch_target_m, 1.79 -`ifdef CFG_ICACHE_ENABLED 1.80 - iflush, 1.81 -`endif 1.82 -`ifdef CFG_DCACHE_ENABLED 1.83 - dcache_restart_request, 1.84 - dcache_refill_request, 1.85 - dcache_refilling, 1.86 -`endif 1.87 -`ifdef CFG_IROM_ENABLED 1.88 - irom_store_data_m, 1.89 - irom_address_xm, 1.90 - irom_we_xm, 1.91 -`endif 1.92 -`ifdef CFG_IWB_ENABLED 1.93 - // From Wishbone 1.94 - i_dat_i, 1.95 - i_ack_i, 1.96 - i_err_i, 1.97 -`endif 1.98 -`ifdef CFG_HW_DEBUG_ENABLED 1.99 - jtag_read_enable, 1.100 - jtag_write_enable, 1.101 - jtag_write_data, 1.102 - jtag_address, 1.103 -`endif 1.104 - // ----- Outputs ------- 1.105 - // To pipeline 1.106 - pc_f, 1.107 - pc_d, 1.108 - pc_x, 1.109 - pc_m, 1.110 - pc_w, 1.111 -`ifdef CFG_ICACHE_ENABLED 1.112 - icache_stall_request, 1.113 - icache_restart_request, 1.114 - icache_refill_request, 1.115 - icache_refilling, 1.116 -`endif 1.117 -`ifdef CFG_IROM_ENABLED 1.118 - irom_data_m, 1.119 -`endif 1.120 -`ifdef CFG_IWB_ENABLED 1.121 - // To Wishbone 1.122 - i_dat_o, 1.123 - i_adr_o, 1.124 - i_cyc_o, 1.125 - i_sel_o, 1.126 - i_stb_o, 1.127 - i_we_o, 1.128 - i_cti_o, 1.129 - i_lock_o, 1.130 - i_bte_o, 1.131 -`endif 1.132 -`ifdef CFG_HW_DEBUG_ENABLED 1.133 - jtag_read_data, 1.134 - jtag_access_complete, 1.135 -`endif 1.136 -`ifdef CFG_BUS_ERRORS_ENABLED 1.137 - bus_error_d, 1.138 -`endif 1.139 -`ifdef CFG_EBR_POSEDGE_REGISTER_FILE 1.140 - instruction_f, 1.141 -`endif 1.142 - instruction_d 1.143 - ); 1.144 - 1.145 -///////////////////////////////////////////////////// 1.146 -// Parameters 1.147 -///////////////////////////////////////////////////// 1.148 - 1.149 -parameter associativity = 1; // Associativity of the cache (Number of ways) 1.150 -parameter sets = 512; // Number of sets 1.151 -parameter bytes_per_line = 16; // Number of bytes per cache line 1.152 -parameter base_address = 0; // Base address of cachable memory 1.153 -parameter limit = 0; // Limit (highest address) of cachable memory 1.154 - 1.155 -// For bytes_per_line == 4, we set 1 so part-select range isn't reversed, even though not really used 1.156 -localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2; 1.157 -localparam addr_offset_lsb = 2; 1.158 -localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1); 1.159 - 1.160 -///////////////////////////////////////////////////// 1.161 -// Inputs 1.162 -///////////////////////////////////////////////////// 1.163 - 1.164 -input clk_i; // Clock 1.165 -input rst_i; // Reset 1.166 - 1.167 -input stall_a; // Stall A stage instruction 1.168 -input stall_f; // Stall F stage instruction 1.169 -input stall_d; // Stall D stage instruction 1.170 -input stall_x; // Stall X stage instruction 1.171 -input stall_m; // Stall M stage instruction 1.172 -input valid_f; // Instruction in F stage is valid 1.173 -input valid_d; // Instruction in D stage is valid 1.174 -input kill_f; // Kill instruction in F stage 1.175 - 1.176 -input branch_predict_taken_d; // Branch is predicted taken in D stage 1.177 -input [`LM32_PC_RNG] branch_predict_address_d; // Branch target address 1.178 - 1.179 -`ifdef CFG_FAST_UNCONDITIONAL_BRANCH 1.180 -input branch_taken_x; // Branch instruction in X stage is taken 1.181 -input [`LM32_PC_RNG] branch_target_x; // Target PC of X stage branch instruction 1.182 -`endif 1.183 -input exception_m; 1.184 -input branch_taken_m; // Branch instruction in M stage is taken 1.185 -input branch_mispredict_taken_m; // Branch instruction in M stage is mispredicted as taken 1.186 -input [`LM32_PC_RNG] branch_target_m; // Target PC of M stage branch instruction 1.187 - 1.188 -`ifdef CFG_ICACHE_ENABLED 1.189 -input iflush; // Flush instruction cache 1.190 -`endif 1.191 -`ifdef CFG_DCACHE_ENABLED 1.192 -input dcache_restart_request; // Restart instruction that caused a data cache miss 1.193 -input dcache_refill_request; // Request to refill data cache 1.194 -input dcache_refilling; 1.195 -`endif 1.196 - 1.197 -`ifdef CFG_IROM_ENABLED 1.198 -input [`LM32_WORD_RNG] irom_store_data_m; // Data from load-store unit 1.199 -input [`LM32_WORD_RNG] irom_address_xm; // Address from load-store unit 1.200 -input irom_we_xm; // Indicates if memory operation is load or store 1.201 -`endif 1.202 - 1.203 -`ifdef CFG_IWB_ENABLED 1.204 -input [`LM32_WORD_RNG] i_dat_i; // Instruction Wishbone interface read data 1.205 -input i_ack_i; // Instruction Wishbone interface acknowledgement 1.206 -input i_err_i; // Instruction Wishbone interface error 1.207 -`endif 1.208 - 1.209 -`ifdef CFG_HW_DEBUG_ENABLED 1.210 -input jtag_read_enable; // JTAG read memory request 1.211 -input jtag_write_enable; // JTAG write memory request 1.212 -input [`LM32_BYTE_RNG] jtag_write_data; // JTAG wrirte data 1.213 -input [`LM32_WORD_RNG] jtag_address; // JTAG read/write address 1.214 -`endif 1.215 - 1.216 -///////////////////////////////////////////////////// 1.217 -// Outputs 1.218 -///////////////////////////////////////////////////// 1.219 - 1.220 -output [`LM32_PC_RNG] pc_f; // F stage PC 1.221 -reg [`LM32_PC_RNG] pc_f; 1.222 -output [`LM32_PC_RNG] pc_d; // D stage PC 1.223 -reg [`LM32_PC_RNG] pc_d; 1.224 -output [`LM32_PC_RNG] pc_x; // X stage PC 1.225 -reg [`LM32_PC_RNG] pc_x; 1.226 -output [`LM32_PC_RNG] pc_m; // M stage PC 1.227 -reg [`LM32_PC_RNG] pc_m; 1.228 -output [`LM32_PC_RNG] pc_w; // W stage PC 1.229 -reg [`LM32_PC_RNG] pc_w; 1.230 - 1.231 -`ifdef CFG_ICACHE_ENABLED 1.232 -output icache_stall_request; // Instruction cache stall request 1.233 -wire icache_stall_request; 1.234 -output icache_restart_request; // Request to restart instruction that cached instruction cache miss 1.235 -wire icache_restart_request; 1.236 -output icache_refill_request; // Instruction cache refill request 1.237 -wire icache_refill_request; 1.238 -output icache_refilling; // Indicates the icache is refilling 1.239 -wire icache_refilling; 1.240 -`endif 1.241 - 1.242 -`ifdef CFG_IROM_ENABLED 1.243 -output [`LM32_WORD_RNG] irom_data_m; // Data to load-store unit on load 1.244 -wire [`LM32_WORD_RNG] irom_data_m; 1.245 -`endif 1.246 - 1.247 -`ifdef CFG_IWB_ENABLED 1.248 -output [`LM32_WORD_RNG] i_dat_o; // Instruction Wishbone interface write data 1.249 -`ifdef CFG_HW_DEBUG_ENABLED 1.250 -reg [`LM32_WORD_RNG] i_dat_o; 1.251 -`else 1.252 -wire [`LM32_WORD_RNG] i_dat_o; 1.253 -`endif 1.254 -output [`LM32_WORD_RNG] i_adr_o; // Instruction Wishbone interface address 1.255 -reg [`LM32_WORD_RNG] i_adr_o; 1.256 -output i_cyc_o; // Instruction Wishbone interface cycle 1.257 -reg i_cyc_o; 1.258 -output [`LM32_BYTE_SELECT_RNG] i_sel_o; // Instruction Wishbone interface byte select 1.259 -`ifdef CFG_HW_DEBUG_ENABLED 1.260 -reg [`LM32_BYTE_SELECT_RNG] i_sel_o; 1.261 -`else 1.262 -wire [`LM32_BYTE_SELECT_RNG] i_sel_o; 1.263 -`endif 1.264 -output i_stb_o; // Instruction Wishbone interface strobe 1.265 -reg i_stb_o; 1.266 -output i_we_o; // Instruction Wishbone interface write enable 1.267 -`ifdef CFG_HW_DEBUG_ENABLED 1.268 -reg i_we_o; 1.269 -`else 1.270 -wire i_we_o; 1.271 -`endif 1.272 -output [`LM32_CTYPE_RNG] i_cti_o; // Instruction Wishbone interface cycle type 1.273 -reg [`LM32_CTYPE_RNG] i_cti_o; 1.274 -output i_lock_o; // Instruction Wishbone interface lock bus 1.275 -reg i_lock_o; 1.276 -output [`LM32_BTYPE_RNG] i_bte_o; // Instruction Wishbone interface burst type 1.277 -wire [`LM32_BTYPE_RNG] i_bte_o; 1.278 -`endif 1.279 - 1.280 -`ifdef CFG_HW_DEBUG_ENABLED 1.281 -output [`LM32_BYTE_RNG] jtag_read_data; // Data read for JTAG interface 1.282 -reg [`LM32_BYTE_RNG] jtag_read_data; 1.283 -output jtag_access_complete; // Requested memory access by JTAG interface is complete 1.284 -wire jtag_access_complete; 1.285 -`endif 1.286 - 1.287 -`ifdef CFG_BUS_ERRORS_ENABLED 1.288 -output bus_error_d; // Indicates a bus error occured while fetching the instruction 1.289 -reg bus_error_d; 1.290 -`endif 1.291 -`ifdef CFG_EBR_POSEDGE_REGISTER_FILE 1.292 -output [`LM32_INSTRUCTION_RNG] instruction_f; // F stage instruction (only to have register indices extracted from) 1.293 -wire [`LM32_INSTRUCTION_RNG] instruction_f; 1.294 -`endif 1.295 -output [`LM32_INSTRUCTION_RNG] instruction_d; // D stage instruction to be decoded 1.296 -reg [`LM32_INSTRUCTION_RNG] instruction_d; 1.297 - 1.298 -///////////////////////////////////////////////////// 1.299 -// Internal nets and registers 1.300 -///////////////////////////////////////////////////// 1.301 - 1.302 -reg [`LM32_PC_RNG] pc_a; // A stage PC 1.303 - 1.304 -`ifdef LM32_CACHE_ENABLED 1.305 -reg [`LM32_PC_RNG] restart_address; // Address to restart from after a cache miss 1.306 -`endif 1.307 - 1.308 -`ifdef CFG_ICACHE_ENABLED 1.309 -wire icache_read_enable_f; // Indicates if instruction cache miss is valid 1.310 -wire [`LM32_PC_RNG] icache_refill_address; // Address that caused cache miss 1.311 -reg icache_refill_ready; // Indicates when next word of refill data is ready to be written to cache 1.312 -reg [`LM32_INSTRUCTION_RNG] icache_refill_data; // Next word of refill data, fetched from Wishbone 1.313 -wire [`LM32_INSTRUCTION_RNG] icache_data_f; // Instruction fetched from instruction cache 1.314 -wire [`LM32_CTYPE_RNG] first_cycle_type; // First Wishbone cycle type 1.315 -wire [`LM32_CTYPE_RNG] next_cycle_type; // Next Wishbone cycle type 1.316 -wire last_word; // Indicates if this is the last word in the cache line 1.317 -wire [`LM32_PC_RNG] first_address; // First cache refill address 1.318 -`else 1.319 -`ifdef CFG_IWB_ENABLED 1.320 -reg [`LM32_INSTRUCTION_RNG] wb_data_f; // Instruction fetched from Wishbone 1.321 -`endif 1.322 -`endif 1.323 -`ifdef CFG_IROM_ENABLED 1.324 -wire irom_select_a; // Indicates if A stage PC maps to a ROM address 1.325 -reg irom_select_f; // Indicates if F stage PC maps to a ROM address 1.326 -wire [`LM32_INSTRUCTION_RNG] irom_data_f; // Instruction fetched from ROM 1.327 -`endif 1.328 -`ifdef CFG_EBR_POSEDGE_REGISTER_FILE 1.329 -`else 1.330 -wire [`LM32_INSTRUCTION_RNG] instruction_f; // F stage instruction 1.331 -`endif 1.332 -`ifdef CFG_BUS_ERRORS_ENABLED 1.333 -reg bus_error_f; // Indicates if a bus error occured while fetching the instruction in the F stage 1.334 -`endif 1.335 - 1.336 -`ifdef CFG_HW_DEBUG_ENABLED 1.337 -reg jtag_access; // Indicates if a JTAG WB access is in progress 1.338 -`endif 1.339 - 1.340 -///////////////////////////////////////////////////// 1.341 -// Functions 1.342 -///////////////////////////////////////////////////// 1.343 - 1.344 -`include "lm32_functions.v" 1.345 - 1.346 -///////////////////////////////////////////////////// 1.347 -// Instantiations 1.348 -///////////////////////////////////////////////////// 1.349 - 1.350 -// Instruction ROM 1.351 -`ifdef CFG_IROM_ENABLED 1.352 - pmi_ram_dp_true 1.353 - #( 1.354 - // ----- Parameters ------- 1.355 - .pmi_family (`LATTICE_FAMILY), 1.356 - 1.357 - //.pmi_addr_depth_a (1 << (clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)), 1.358 - //.pmi_addr_width_a ((clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)), 1.359 - //.pmi_data_width_a (`LM32_WORD_WIDTH), 1.360 - //.pmi_addr_depth_b (1 << (clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)), 1.361 - //.pmi_addr_width_b ((clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)), 1.362 - //.pmi_data_width_b (`LM32_WORD_WIDTH), 1.363 - 1.364 - .pmi_addr_depth_a (`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1), 1.365 - .pmi_addr_width_a (clogb2_v1(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)), 1.366 - .pmi_data_width_a (`LM32_WORD_WIDTH), 1.367 - .pmi_addr_depth_b (`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1), 1.368 - .pmi_addr_width_b (clogb2_v1(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)), 1.369 - .pmi_data_width_b (`LM32_WORD_WIDTH), 1.370 - 1.371 - .pmi_regmode_a ("noreg"), 1.372 - .pmi_regmode_b ("noreg"), 1.373 - .pmi_gsr ("enable"), 1.374 - .pmi_resetmode ("sync"), 1.375 - .pmi_init_file (`CFG_IROM_INIT_FILE), 1.376 - .pmi_init_file_format (`CFG_IROM_INIT_FILE_FORMAT), 1.377 - .module_type ("pmi_ram_dp_true") 1.378 - ) 1.379 - ram ( 1.380 - // ----- Inputs ------- 1.381 - .ClockA (clk_i), 1.382 - .ClockB (clk_i), 1.383 - .ResetA (rst_i), 1.384 - .ResetB (rst_i), 1.385 - .DataInA ({32{1'b0}}), 1.386 - .DataInB (irom_store_data_m), 1.387 - .AddressA (pc_a[(clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)+2-1:2]), 1.388 - .AddressB (irom_address_xm[(clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)+2-1:2]), 1.389 - .ClockEnA (!stall_a), 1.390 - .ClockEnB (!stall_x || !stall_m), 1.391 - .WrA (`FALSE), 1.392 - .WrB (irom_we_xm), 1.393 - // ----- Outputs ------- 1.394 - .QA (irom_data_f), 1.395 - .QB (irom_data_m) 1.396 - ); 1.397 -`endif 1.398 - 1.399 -`ifdef CFG_ICACHE_ENABLED 1.400 -// Instruction cache 1.401 -lm32_icache #( 1.402 - .associativity (associativity), 1.403 - .sets (sets), 1.404 - .bytes_per_line (bytes_per_line), 1.405 - .base_address (base_address), 1.406 - .limit (limit) 1.407 - ) icache ( 1.408 - // ----- Inputs ----- 1.409 - .clk_i (clk_i), 1.410 - .rst_i (rst_i), 1.411 - .stall_a (stall_a), 1.412 - .stall_f (stall_f), 1.413 - .branch_predict_taken_d (branch_predict_taken_d), 1.414 - .valid_d (valid_d), 1.415 - .address_a (pc_a), 1.416 - .address_f (pc_f), 1.417 - .read_enable_f (icache_read_enable_f), 1.418 - .refill_ready (icache_refill_ready), 1.419 - .refill_data (icache_refill_data), 1.420 - .iflush (iflush), 1.421 - // ----- Outputs ----- 1.422 - .stall_request (icache_stall_request), 1.423 - .restart_request (icache_restart_request), 1.424 - .refill_request (icache_refill_request), 1.425 - .refill_address (icache_refill_address), 1.426 - .refilling (icache_refilling), 1.427 - .inst (icache_data_f) 1.428 - ); 1.429 -`endif 1.430 - 1.431 -///////////////////////////////////////////////////// 1.432 -// Combinational Logic 1.433 -///////////////////////////////////////////////////// 1.434 - 1.435 -`ifdef CFG_ICACHE_ENABLED 1.436 -// Generate signal that indicates when instruction cache misses are valid 1.437 -assign icache_read_enable_f = (valid_f == `TRUE) 1.438 - && (kill_f == `FALSE) 1.439 -`ifdef CFG_DCACHE_ENABLED 1.440 - && (dcache_restart_request == `FALSE) 1.441 -`endif 1.442 -`ifdef CFG_IROM_ENABLED 1.443 - && (irom_select_f == `FALSE) 1.444 -`endif 1.445 - ; 1.446 -`endif 1.447 - 1.448 -// Compute address of next instruction to fetch 1.449 -always @(*) 1.450 -begin 1.451 - // The request from the latest pipeline stage must take priority 1.452 -`ifdef CFG_DCACHE_ENABLED 1.453 - if (dcache_restart_request == `TRUE) 1.454 - pc_a = restart_address; 1.455 - else 1.456 -`endif 1.457 - if (branch_taken_m == `TRUE) 1.458 - if ((branch_mispredict_taken_m == `TRUE) && (exception_m == `FALSE)) 1.459 - pc_a = pc_x; 1.460 - else 1.461 - pc_a = branch_target_m; 1.462 -`ifdef CFG_FAST_UNCONDITIONAL_BRANCH 1.463 - else if (branch_taken_x == `TRUE) 1.464 - pc_a = branch_target_x; 1.465 -`endif 1.466 - else 1.467 - if ( (valid_d == `TRUE) && (branch_predict_taken_d == `TRUE) ) 1.468 - pc_a = branch_predict_address_d; 1.469 - else 1.470 -`ifdef CFG_ICACHE_ENABLED 1.471 - if (icache_restart_request == `TRUE) 1.472 - pc_a = restart_address; 1.473 - else 1.474 -`endif 1.475 - pc_a = pc_f + 1'b1; 1.476 -end 1.477 - 1.478 -// Select where instruction should be fetched from 1.479 -`ifdef CFG_IROM_ENABLED 1.480 -assign irom_select_a = ({pc_a, 2'b00} >= `CFG_IROM_BASE_ADDRESS) && ({pc_a, 2'b00} <= `CFG_IROM_LIMIT); 1.481 -`endif 1.482 - 1.483 -// Select instruction from selected source 1.484 -`ifdef CFG_ICACHE_ENABLED 1.485 -`ifdef CFG_IROM_ENABLED 1.486 -assign instruction_f = irom_select_f == `TRUE ? irom_data_f : icache_data_f; 1.487 -`else 1.488 -assign instruction_f = icache_data_f; 1.489 -`endif 1.490 -`else 1.491 -`ifdef CFG_IROM_ENABLED 1.492 -`ifdef CFG_IWB_ENABLED 1.493 -assign instruction_f = irom_select_f == `TRUE ? irom_data_f : wb_data_f; 1.494 -`else 1.495 -assign instruction_f = irom_data_f; 1.496 -`endif 1.497 -`else 1.498 -assign instruction_f = wb_data_f; 1.499 -`endif 1.500 -`endif 1.501 - 1.502 -// Unused/constant Wishbone signals 1.503 -`ifdef CFG_IWB_ENABLED 1.504 -`ifdef CFG_HW_DEBUG_ENABLED 1.505 -`else 1.506 -assign i_dat_o = 32'd0; 1.507 -assign i_we_o = `FALSE; 1.508 -assign i_sel_o = 4'b1111; 1.509 -`endif 1.510 -assign i_bte_o = `LM32_BTYPE_LINEAR; 1.511 -`endif 1.512 - 1.513 -`ifdef CFG_ICACHE_ENABLED 1.514 -// Determine parameters for next cache refill Wishbone access 1.515 -generate 1.516 - case (bytes_per_line) 1.517 - 4: 1.518 - begin 1.519 -assign first_cycle_type = `LM32_CTYPE_END; 1.520 -assign next_cycle_type = `LM32_CTYPE_END; 1.521 -assign last_word = `TRUE; 1.522 -assign first_address = icache_refill_address; 1.523 - end 1.524 - 8: 1.525 - begin 1.526 -assign first_cycle_type = `LM32_CTYPE_INCREMENTING; 1.527 -assign next_cycle_type = `LM32_CTYPE_END; 1.528 -assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 1'b1; 1.529 -assign first_address = {icache_refill_address[`LM32_PC_WIDTH+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}}; 1.530 - end 1.531 - 16: 1.532 - begin 1.533 -assign first_cycle_type = `LM32_CTYPE_INCREMENTING; 1.534 -assign next_cycle_type = i_adr_o[addr_offset_msb] == 1'b1 ? `LM32_CTYPE_END : `LM32_CTYPE_INCREMENTING; 1.535 -assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 2'b11; 1.536 -assign first_address = {icache_refill_address[`LM32_PC_WIDTH+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}}; 1.537 - end 1.538 - endcase 1.539 -endgenerate 1.540 -`endif 1.541 - 1.542 -///////////////////////////////////////////////////// 1.543 -// Sequential Logic 1.544 -///////////////////////////////////////////////////// 1.545 - 1.546 -// PC 1.547 -always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.548 -begin 1.549 - if (rst_i == `TRUE) 1.550 - begin 1.551 - pc_f <= (`CFG_EBA_RESET-4)/4; 1.552 - pc_d <= {`LM32_PC_WIDTH{1'b0}}; 1.553 - pc_x <= {`LM32_PC_WIDTH{1'b0}}; 1.554 - pc_m <= {`LM32_PC_WIDTH{1'b0}}; 1.555 - pc_w <= {`LM32_PC_WIDTH{1'b0}}; 1.556 - end 1.557 - else 1.558 - begin 1.559 - if (stall_f == `FALSE) 1.560 - pc_f <= pc_a; 1.561 - if (stall_d == `FALSE) 1.562 - pc_d <= pc_f; 1.563 - if (stall_x == `FALSE) 1.564 - pc_x <= pc_d; 1.565 - if (stall_m == `FALSE) 1.566 - pc_m <= pc_x; 1.567 - pc_w <= pc_m; 1.568 - end 1.569 -end 1.570 - 1.571 -`ifdef LM32_CACHE_ENABLED 1.572 -// Address to restart from after a cache miss has been handled 1.573 -always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.574 -begin 1.575 - if (rst_i == `TRUE) 1.576 - restart_address <= {`LM32_PC_WIDTH{1'b0}}; 1.577 - else 1.578 - begin 1.579 -`ifdef CFG_DCACHE_ENABLED 1.580 -`ifdef CFG_ICACHE_ENABLED 1.581 - // D-cache restart address must take priority, otherwise instructions will be lost 1.582 - if (dcache_refill_request == `TRUE) 1.583 - restart_address <= pc_w; 1.584 - else if ((icache_refill_request == `TRUE) && (!dcache_refilling) && (!dcache_restart_request)) 1.585 - restart_address <= icache_refill_address; 1.586 -`else 1.587 - if (dcache_refill_request == `TRUE) 1.588 - restart_address <= pc_w; 1.589 -`endif 1.590 -`else 1.591 -`ifdef CFG_ICACHE_ENABLED 1.592 - if (icache_refill_request == `TRUE) 1.593 - restart_address <= icache_refill_address; 1.594 -`endif 1.595 -`endif 1.596 - end 1.597 -end 1.598 -`endif 1.599 - 1.600 -// Record where instruction was fetched from 1.601 -`ifdef CFG_IROM_ENABLED 1.602 -always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.603 -begin 1.604 - if (rst_i == `TRUE) 1.605 - irom_select_f <= `FALSE; 1.606 - else 1.607 - begin 1.608 - if (stall_f == `FALSE) 1.609 - irom_select_f <= irom_select_a; 1.610 - end 1.611 -end 1.612 -`endif 1.613 - 1.614 -`ifdef CFG_HW_DEBUG_ENABLED 1.615 -assign jtag_access_complete = (i_cyc_o == `TRUE) && ((i_ack_i == `TRUE) || (i_err_i == `TRUE)) && (jtag_access == `TRUE); 1.616 -always @(*) 1.617 -begin 1.618 - case (jtag_address[1:0]) 1.619 - 2'b00: jtag_read_data = i_dat_i[`LM32_BYTE_3_RNG]; 1.620 - 2'b01: jtag_read_data = i_dat_i[`LM32_BYTE_2_RNG]; 1.621 - 2'b10: jtag_read_data = i_dat_i[`LM32_BYTE_1_RNG]; 1.622 - 2'b11: jtag_read_data = i_dat_i[`LM32_BYTE_0_RNG]; 1.623 - endcase 1.624 -end 1.625 -`endif 1.626 - 1.627 -`ifdef CFG_IWB_ENABLED 1.628 -// Instruction Wishbone interface 1.629 -`ifdef CFG_ICACHE_ENABLED 1.630 -always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.631 -begin 1.632 - if (rst_i == `TRUE) 1.633 - begin 1.634 - i_cyc_o <= `FALSE; 1.635 - i_stb_o <= `FALSE; 1.636 - i_adr_o <= {`LM32_WORD_WIDTH{1'b0}}; 1.637 - i_cti_o <= `LM32_CTYPE_END; 1.638 - i_lock_o <= `FALSE; 1.639 - icache_refill_data <= {`LM32_INSTRUCTION_WIDTH{1'b0}}; 1.640 - icache_refill_ready <= `FALSE; 1.641 -`ifdef CFG_BUS_ERRORS_ENABLED 1.642 - bus_error_f <= `FALSE; 1.643 -`endif 1.644 -`ifdef CFG_HW_DEBUG_ENABLED 1.645 - i_we_o <= `FALSE; 1.646 - i_sel_o <= 4'b1111; 1.647 - jtag_access <= `FALSE; 1.648 -`endif 1.649 - end 1.650 - else 1.651 - begin 1.652 - icache_refill_ready <= `FALSE; 1.653 - // Is a cycle in progress? 1.654 - if (i_cyc_o == `TRUE) 1.655 - begin 1.656 - // Has cycle completed? 1.657 - if ((i_ack_i == `TRUE) || (i_err_i == `TRUE)) 1.658 - begin 1.659 -`ifdef CFG_HW_DEBUG_ENABLED 1.660 - if (jtag_access == `TRUE) 1.661 - begin 1.662 - i_cyc_o <= `FALSE; 1.663 - i_stb_o <= `FALSE; 1.664 - i_we_o <= `FALSE; 1.665 - jtag_access <= `FALSE; 1.666 - end 1.667 - else 1.668 -`endif 1.669 - begin 1.670 - if (last_word == `TRUE) 1.671 - begin 1.672 - // Cache line fill complete 1.673 - i_cyc_o <= `FALSE; 1.674 - i_stb_o <= `FALSE; 1.675 - i_lock_o <= `FALSE; 1.676 - end 1.677 - // Fetch next word in cache line 1.678 - i_adr_o[addr_offset_msb:addr_offset_lsb] <= i_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1; 1.679 - i_cti_o <= next_cycle_type; 1.680 - // Write fetched data into instruction cache 1.681 - icache_refill_ready <= `TRUE; 1.682 - icache_refill_data <= i_dat_i; 1.683 - end 1.684 - end 1.685 -`ifdef CFG_BUS_ERRORS_ENABLED 1.686 - if (i_err_i == `TRUE) 1.687 - begin 1.688 - bus_error_f <= `TRUE; 1.689 - $display ("Instruction bus error. Address: %x", i_adr_o); 1.690 - end 1.691 -`endif 1.692 - end 1.693 - else 1.694 - begin 1.695 - if ((icache_refill_request == `TRUE) && (icache_refill_ready == `FALSE)) 1.696 - begin 1.697 - // Read first word of cache line 1.698 -`ifdef CFG_HW_DEBUG_ENABLED 1.699 - i_sel_o <= 4'b1111; 1.700 -`endif 1.701 - i_adr_o <= {first_address, 2'b00}; 1.702 - i_cyc_o <= `TRUE; 1.703 - i_stb_o <= `TRUE; 1.704 - i_cti_o <= first_cycle_type; 1.705 - //i_lock_o <= `TRUE; 1.706 -`ifdef CFG_BUS_ERRORS_ENABLED 1.707 - bus_error_f <= `FALSE; 1.708 -`endif 1.709 - end 1.710 -`ifdef CFG_HW_DEBUG_ENABLED 1.711 - else 1.712 - begin 1.713 - if ((jtag_read_enable == `TRUE) || (jtag_write_enable == `TRUE)) 1.714 - begin 1.715 - case (jtag_address[1:0]) 1.716 - 2'b00: i_sel_o <= 4'b1000; 1.717 - 2'b01: i_sel_o <= 4'b0100; 1.718 - 2'b10: i_sel_o <= 4'b0010; 1.719 - 2'b11: i_sel_o <= 4'b0001; 1.720 - endcase 1.721 - i_adr_o <= jtag_address; 1.722 - i_dat_o <= {4{jtag_write_data}}; 1.723 - i_cyc_o <= `TRUE; 1.724 - i_stb_o <= `TRUE; 1.725 - i_we_o <= jtag_write_enable; 1.726 - i_cti_o <= `LM32_CTYPE_END; 1.727 - jtag_access <= `TRUE; 1.728 - end 1.729 - end 1.730 -`endif 1.731 -`ifdef CFG_BUS_ERRORS_ENABLED 1.732 - // Clear bus error when exception taken, otherwise they would be 1.733 - // continually generated if exception handler is cached 1.734 -`ifdef CFG_FAST_UNCONDITIONAL_BRANCH 1.735 - if (branch_taken_x == `TRUE) 1.736 - bus_error_f <= `FALSE; 1.737 -`endif 1.738 - if (branch_taken_m == `TRUE) 1.739 - bus_error_f <= `FALSE; 1.740 -`endif 1.741 - end 1.742 - end 1.743 -end 1.744 -`else 1.745 -always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.746 -begin 1.747 - if (rst_i == `TRUE) 1.748 - begin 1.749 - i_cyc_o <= `FALSE; 1.750 - i_stb_o <= `FALSE; 1.751 - i_adr_o <= {`LM32_WORD_WIDTH{1'b0}}; 1.752 - i_cti_o <= `LM32_CTYPE_END; 1.753 - i_lock_o <= `FALSE; 1.754 - wb_data_f <= {`LM32_INSTRUCTION_WIDTH{1'b0}}; 1.755 -`ifdef CFG_BUS_ERRORS_ENABLED 1.756 - bus_error_f <= `FALSE; 1.757 -`endif 1.758 - end 1.759 - else 1.760 - begin 1.761 - // Is a cycle in progress? 1.762 - if (i_cyc_o == `TRUE) 1.763 - begin 1.764 - // Has cycle completed? 1.765 - if((i_ack_i == `TRUE) || (i_err_i == `TRUE)) 1.766 - begin 1.767 - // Cycle complete 1.768 - i_cyc_o <= `FALSE; 1.769 - i_stb_o <= `FALSE; 1.770 - // Register fetched instruction 1.771 - wb_data_f <= i_dat_i; 1.772 - end 1.773 -`ifdef CFG_BUS_ERRORS_ENABLED 1.774 - if (i_err_i == `TRUE) 1.775 - begin 1.776 - bus_error_f <= `TRUE; 1.777 - $display ("Instruction bus error. Address: %x", i_adr_o); 1.778 - end 1.779 -`endif 1.780 - end 1.781 - else 1.782 - begin 1.783 - // Wait for an instruction fetch from an external address 1.784 - if ( (stall_a == `FALSE) 1.785 -`ifdef CFG_IROM_ENABLED 1.786 - && (irom_select_a == `FALSE) 1.787 -`endif 1.788 - ) 1.789 - begin 1.790 - // Fetch instruction 1.791 -`ifdef CFG_HW_DEBUG_ENABLED 1.792 - i_sel_o <= 4'b1111; 1.793 -`endif 1.794 - i_adr_o <= {pc_a, 2'b00}; 1.795 - i_cyc_o <= `TRUE; 1.796 - i_stb_o <= `TRUE; 1.797 -`ifdef CFG_BUS_ERRORS_ENABLED 1.798 - bus_error_f <= `FALSE; 1.799 -`endif 1.800 - end 1.801 - else 1.802 - begin 1.803 - if ( (stall_a == `FALSE) 1.804 -`ifdef CFG_IROM_ENABLED 1.805 - && (irom_select_a == `TRUE) 1.806 -`endif 1.807 - ) 1.808 - begin 1.809 -`ifdef CFG_BUS_ERRORS_ENABLED 1.810 - bus_error_f <= `FALSE; 1.811 -`endif 1.812 - end 1.813 - end 1.814 - end 1.815 - end 1.816 -end 1.817 -`endif 1.818 -`endif 1.819 - 1.820 -// Instruction register 1.821 -always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.822 -begin 1.823 - if (rst_i == `TRUE) 1.824 - begin 1.825 - instruction_d <= {`LM32_INSTRUCTION_WIDTH{1'b0}}; 1.826 -`ifdef CFG_BUS_ERRORS_ENABLED 1.827 - bus_error_d <= `FALSE; 1.828 -`endif 1.829 - end 1.830 - else 1.831 - begin 1.832 - if (stall_d == `FALSE) 1.833 - begin 1.834 - instruction_d <= instruction_f; 1.835 -`ifdef CFG_BUS_ERRORS_ENABLED 1.836 - bus_error_d <= bus_error_f; 1.837 -`endif 1.838 - end 1.839 - end 1.840 -end 1.841 - 1.842 -endmodule