1.1 diff -r 252df75c8f67 -r c336e674a37e lm32_instruction_unit.v 1.2 --- a/lm32_instruction_unit.v Sun Mar 06 21:17:31 2011 +0000 1.3 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 1.4 @@ -1,839 +0,0 @@ 1.5 -// ============================================================================= 1.6 -// COPYRIGHT NOTICE 1.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 1.8 -// ALL RIGHTS RESERVED 1.9 -// This confidential and proprietary software may be used only as authorised by 1.10 -// a licensing agreement from Lattice Semiconductor Corporation. 1.11 -// The entire notice above must be reproduced on all authorized copies and 1.12 -// copies may only be made to the extent permitted by a licensing agreement from 1.13 -// Lattice Semiconductor Corporation. 1.14 -// 1.15 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 1.16 -// 5555 NE Moore Court 408-826-6000 (other locations) 1.17 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 1.18 -// U.S.A email: techsupport@latticesemi.com 1.19 -// =============================================================================/ 1.20 -// FILE DETAILS 1.21 -// Project : LatticeMico32 1.22 -// File : lm32_instruction_unit.v 1.23 -// Title : Instruction unit 1.24 -// Dependencies : lm32_include.v 1.25 -// Version : 6.1.17 1.26 -// : Initial Release 1.27 -// Version : 7.0SP2, 3.0 1.28 -// : No Change 1.29 -// Version : 3.1 1.30 -// : Support for static branch prediction is added. Fetching of 1.31 -// : instructions can also be altered by branches predicted in D 1.32 -// : stage of pipeline, and mispredicted branches in the X and M 1.33 -// : stages of the pipeline. 1.34 -// Version : 3.2 1.35 -// : EBRs use SYNC resets instead of ASYNC resets. 1.36 -// Version : 3.3 1.37 -// : Support for a non-cacheable Instruction Memory that has a 1.38 -// : single-cycle access latency. This memory can be accessed by 1.39 -// : data port of LM32 (so that debugger has access to it). 1.40 -// Version : 3.4 1.41 -// : No change 1.42 -// Version : 3.5 1.43 -// : Bug fix: Inline memory is correctly generated if it is not a 1.44 -// : power-of-two. 1.45 -// : Bug fix: Fixed a bug that caused LM32 (configured without 1.46 -// : instruction cache) to lock up in to an infinite loop due to a 1.47 -// : instruction bus error when EBA was set to instruction inline 1.48 -// : memory. 1.49 -// ============================================================================= 1.50 - 1.51 -`include "lm32_include.v" 1.52 - 1.53 -///////////////////////////////////////////////////// 1.54 -// Module interface 1.55 -///////////////////////////////////////////////////// 1.56 - 1.57 -module lm32_instruction_unit ( 1.58 - // ----- Inputs ------- 1.59 - clk_i, 1.60 - rst_i, 1.61 - // From pipeline 1.62 - stall_a, 1.63 - stall_f, 1.64 - stall_d, 1.65 - stall_x, 1.66 - stall_m, 1.67 - valid_f, 1.68 - valid_d, 1.69 - kill_f, 1.70 - branch_predict_taken_d, 1.71 - branch_predict_address_d, 1.72 -`ifdef CFG_FAST_UNCONDITIONAL_BRANCH 1.73 - branch_taken_x, 1.74 - branch_target_x, 1.75 -`endif 1.76 - exception_m, 1.77 - branch_taken_m, 1.78 - branch_mispredict_taken_m, 1.79 - branch_target_m, 1.80 -`ifdef CFG_ICACHE_ENABLED 1.81 - iflush, 1.82 -`endif 1.83 -`ifdef CFG_DCACHE_ENABLED 1.84 - dcache_restart_request, 1.85 - dcache_refill_request, 1.86 - dcache_refilling, 1.87 -`endif 1.88 -`ifdef CFG_IROM_ENABLED 1.89 - irom_store_data_m, 1.90 - irom_address_xm, 1.91 - irom_we_xm, 1.92 -`endif 1.93 -`ifdef CFG_IWB_ENABLED 1.94 - // From Wishbone 1.95 - i_dat_i, 1.96 - i_ack_i, 1.97 - i_err_i, 1.98 -`endif 1.99 -`ifdef CFG_HW_DEBUG_ENABLED 1.100 - jtag_read_enable, 1.101 - jtag_write_enable, 1.102 - jtag_write_data, 1.103 - jtag_address, 1.104 -`endif 1.105 - // ----- Outputs ------- 1.106 - // To pipeline 1.107 - pc_f, 1.108 - pc_d, 1.109 - pc_x, 1.110 - pc_m, 1.111 - pc_w, 1.112 -`ifdef CFG_ICACHE_ENABLED 1.113 - icache_stall_request, 1.114 - icache_restart_request, 1.115 - icache_refill_request, 1.116 - icache_refilling, 1.117 -`endif 1.118 -`ifdef CFG_IROM_ENABLED 1.119 - irom_data_m, 1.120 -`endif 1.121 -`ifdef CFG_IWB_ENABLED 1.122 - // To Wishbone 1.123 - i_dat_o, 1.124 - i_adr_o, 1.125 - i_cyc_o, 1.126 - i_sel_o, 1.127 - i_stb_o, 1.128 - i_we_o, 1.129 - i_cti_o, 1.130 - i_lock_o, 1.131 - i_bte_o, 1.132 -`endif 1.133 -`ifdef CFG_HW_DEBUG_ENABLED 1.134 - jtag_read_data, 1.135 - jtag_access_complete, 1.136 -`endif 1.137 -`ifdef CFG_BUS_ERRORS_ENABLED 1.138 - bus_error_d, 1.139 -`endif 1.140 -`ifdef CFG_EBR_POSEDGE_REGISTER_FILE 1.141 - instruction_f, 1.142 -`endif 1.143 - instruction_d 1.144 - ); 1.145 - 1.146 -///////////////////////////////////////////////////// 1.147 -// Parameters 1.148 -///////////////////////////////////////////////////// 1.149 - 1.150 -parameter associativity = 1; // Associativity of the cache (Number of ways) 1.151 -parameter sets = 512; // Number of sets 1.152 -parameter bytes_per_line = 16; // Number of bytes per cache line 1.153 -parameter base_address = 0; // Base address of cachable memory 1.154 -parameter limit = 0; // Limit (highest address) of cachable memory 1.155 - 1.156 -// For bytes_per_line == 4, we set 1 so part-select range isn't reversed, even though not really used 1.157 -localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2; 1.158 -localparam addr_offset_lsb = 2; 1.159 -localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1); 1.160 - 1.161 -///////////////////////////////////////////////////// 1.162 -// Inputs 1.163 -///////////////////////////////////////////////////// 1.164 - 1.165 -input clk_i; // Clock 1.166 -input rst_i; // Reset 1.167 - 1.168 -input stall_a; // Stall A stage instruction 1.169 -input stall_f; // Stall F stage instruction 1.170 -input stall_d; // Stall D stage instruction 1.171 -input stall_x; // Stall X stage instruction 1.172 -input stall_m; // Stall M stage instruction 1.173 -input valid_f; // Instruction in F stage is valid 1.174 -input valid_d; // Instruction in D stage is valid 1.175 -input kill_f; // Kill instruction in F stage 1.176 - 1.177 -input branch_predict_taken_d; // Branch is predicted taken in D stage 1.178 -input [`LM32_PC_RNG] branch_predict_address_d; // Branch target address 1.179 - 1.180 -`ifdef CFG_FAST_UNCONDITIONAL_BRANCH 1.181 -input branch_taken_x; // Branch instruction in X stage is taken 1.182 -input [`LM32_PC_RNG] branch_target_x; // Target PC of X stage branch instruction 1.183 -`endif 1.184 -input exception_m; 1.185 -input branch_taken_m; // Branch instruction in M stage is taken 1.186 -input branch_mispredict_taken_m; // Branch instruction in M stage is mispredicted as taken 1.187 -input [`LM32_PC_RNG] branch_target_m; // Target PC of M stage branch instruction 1.188 - 1.189 -`ifdef CFG_ICACHE_ENABLED 1.190 -input iflush; // Flush instruction cache 1.191 -`endif 1.192 -`ifdef CFG_DCACHE_ENABLED 1.193 -input dcache_restart_request; // Restart instruction that caused a data cache miss 1.194 -input dcache_refill_request; // Request to refill data cache 1.195 -input dcache_refilling; 1.196 -`endif 1.197 - 1.198 -`ifdef CFG_IROM_ENABLED 1.199 -input [`LM32_WORD_RNG] irom_store_data_m; // Data from load-store unit 1.200 -input [`LM32_WORD_RNG] irom_address_xm; // Address from load-store unit 1.201 -input irom_we_xm; // Indicates if memory operation is load or store 1.202 -`endif 1.203 - 1.204 -`ifdef CFG_IWB_ENABLED 1.205 -input [`LM32_WORD_RNG] i_dat_i; // Instruction Wishbone interface read data 1.206 -input i_ack_i; // Instruction Wishbone interface acknowledgement 1.207 -input i_err_i; // Instruction Wishbone interface error 1.208 -`endif 1.209 - 1.210 -`ifdef CFG_HW_DEBUG_ENABLED 1.211 -input jtag_read_enable; // JTAG read memory request 1.212 -input jtag_write_enable; // JTAG write memory request 1.213 -input [`LM32_BYTE_RNG] jtag_write_data; // JTAG wrirte data 1.214 -input [`LM32_WORD_RNG] jtag_address; // JTAG read/write address 1.215 -`endif 1.216 - 1.217 -///////////////////////////////////////////////////// 1.218 -// Outputs 1.219 -///////////////////////////////////////////////////// 1.220 - 1.221 -output [`LM32_PC_RNG] pc_f; // F stage PC 1.222 -reg [`LM32_PC_RNG] pc_f; 1.223 -output [`LM32_PC_RNG] pc_d; // D stage PC 1.224 -reg [`LM32_PC_RNG] pc_d; 1.225 -output [`LM32_PC_RNG] pc_x; // X stage PC 1.226 -reg [`LM32_PC_RNG] pc_x; 1.227 -output [`LM32_PC_RNG] pc_m; // M stage PC 1.228 -reg [`LM32_PC_RNG] pc_m; 1.229 -output [`LM32_PC_RNG] pc_w; // W stage PC 1.230 -reg [`LM32_PC_RNG] pc_w; 1.231 - 1.232 -`ifdef CFG_ICACHE_ENABLED 1.233 -output icache_stall_request; // Instruction cache stall request 1.234 -wire icache_stall_request; 1.235 -output icache_restart_request; // Request to restart instruction that cached instruction cache miss 1.236 -wire icache_restart_request; 1.237 -output icache_refill_request; // Instruction cache refill request 1.238 -wire icache_refill_request; 1.239 -output icache_refilling; // Indicates the icache is refilling 1.240 -wire icache_refilling; 1.241 -`endif 1.242 - 1.243 -`ifdef CFG_IROM_ENABLED 1.244 -output [`LM32_WORD_RNG] irom_data_m; // Data to load-store unit on load 1.245 -wire [`LM32_WORD_RNG] irom_data_m; 1.246 -`endif 1.247 - 1.248 -`ifdef CFG_IWB_ENABLED 1.249 -output [`LM32_WORD_RNG] i_dat_o; // Instruction Wishbone interface write data 1.250 -`ifdef CFG_HW_DEBUG_ENABLED 1.251 -reg [`LM32_WORD_RNG] i_dat_o; 1.252 -`else 1.253 -wire [`LM32_WORD_RNG] i_dat_o; 1.254 -`endif 1.255 -output [`LM32_WORD_RNG] i_adr_o; // Instruction Wishbone interface address 1.256 -reg [`LM32_WORD_RNG] i_adr_o; 1.257 -output i_cyc_o; // Instruction Wishbone interface cycle 1.258 -reg i_cyc_o; 1.259 -output [`LM32_BYTE_SELECT_RNG] i_sel_o; // Instruction Wishbone interface byte select 1.260 -`ifdef CFG_HW_DEBUG_ENABLED 1.261 -reg [`LM32_BYTE_SELECT_RNG] i_sel_o; 1.262 -`else 1.263 -wire [`LM32_BYTE_SELECT_RNG] i_sel_o; 1.264 -`endif 1.265 -output i_stb_o; // Instruction Wishbone interface strobe 1.266 -reg i_stb_o; 1.267 -output i_we_o; // Instruction Wishbone interface write enable 1.268 -`ifdef CFG_HW_DEBUG_ENABLED 1.269 -reg i_we_o; 1.270 -`else 1.271 -wire i_we_o; 1.272 -`endif 1.273 -output [`LM32_CTYPE_RNG] i_cti_o; // Instruction Wishbone interface cycle type 1.274 -reg [`LM32_CTYPE_RNG] i_cti_o; 1.275 -output i_lock_o; // Instruction Wishbone interface lock bus 1.276 -reg i_lock_o; 1.277 -output [`LM32_BTYPE_RNG] i_bte_o; // Instruction Wishbone interface burst type 1.278 -wire [`LM32_BTYPE_RNG] i_bte_o; 1.279 -`endif 1.280 - 1.281 -`ifdef CFG_HW_DEBUG_ENABLED 1.282 -output [`LM32_BYTE_RNG] jtag_read_data; // Data read for JTAG interface 1.283 -reg [`LM32_BYTE_RNG] jtag_read_data; 1.284 -output jtag_access_complete; // Requested memory access by JTAG interface is complete 1.285 -wire jtag_access_complete; 1.286 -`endif 1.287 - 1.288 -`ifdef CFG_BUS_ERRORS_ENABLED 1.289 -output bus_error_d; // Indicates a bus error occured while fetching the instruction 1.290 -reg bus_error_d; 1.291 -`endif 1.292 -`ifdef CFG_EBR_POSEDGE_REGISTER_FILE 1.293 -output [`LM32_INSTRUCTION_RNG] instruction_f; // F stage instruction (only to have register indices extracted from) 1.294 -wire [`LM32_INSTRUCTION_RNG] instruction_f; 1.295 -`endif 1.296 -output [`LM32_INSTRUCTION_RNG] instruction_d; // D stage instruction to be decoded 1.297 -reg [`LM32_INSTRUCTION_RNG] instruction_d; 1.298 - 1.299 -///////////////////////////////////////////////////// 1.300 -// Internal nets and registers 1.301 -///////////////////////////////////////////////////// 1.302 - 1.303 -reg [`LM32_PC_RNG] pc_a; // A stage PC 1.304 - 1.305 -`ifdef LM32_CACHE_ENABLED 1.306 -reg [`LM32_PC_RNG] restart_address; // Address to restart from after a cache miss 1.307 -`endif 1.308 - 1.309 -`ifdef CFG_ICACHE_ENABLED 1.310 -wire icache_read_enable_f; // Indicates if instruction cache miss is valid 1.311 -wire [`LM32_PC_RNG] icache_refill_address; // Address that caused cache miss 1.312 -reg icache_refill_ready; // Indicates when next word of refill data is ready to be written to cache 1.313 -reg [`LM32_INSTRUCTION_RNG] icache_refill_data; // Next word of refill data, fetched from Wishbone 1.314 -wire [`LM32_INSTRUCTION_RNG] icache_data_f; // Instruction fetched from instruction cache 1.315 -wire [`LM32_CTYPE_RNG] first_cycle_type; // First Wishbone cycle type 1.316 -wire [`LM32_CTYPE_RNG] next_cycle_type; // Next Wishbone cycle type 1.317 -wire last_word; // Indicates if this is the last word in the cache line 1.318 -wire [`LM32_PC_RNG] first_address; // First cache refill address 1.319 -`else 1.320 -`ifdef CFG_IWB_ENABLED 1.321 -reg [`LM32_INSTRUCTION_RNG] wb_data_f; // Instruction fetched from Wishbone 1.322 -`endif 1.323 -`endif 1.324 -`ifdef CFG_IROM_ENABLED 1.325 -wire irom_select_a; // Indicates if A stage PC maps to a ROM address 1.326 -reg irom_select_f; // Indicates if F stage PC maps to a ROM address 1.327 -wire [`LM32_INSTRUCTION_RNG] irom_data_f; // Instruction fetched from ROM 1.328 -`endif 1.329 -`ifdef CFG_EBR_POSEDGE_REGISTER_FILE 1.330 -`else 1.331 -wire [`LM32_INSTRUCTION_RNG] instruction_f; // F stage instruction 1.332 -`endif 1.333 -`ifdef CFG_BUS_ERRORS_ENABLED 1.334 -reg bus_error_f; // Indicates if a bus error occured while fetching the instruction in the F stage 1.335 -`endif 1.336 - 1.337 -`ifdef CFG_HW_DEBUG_ENABLED 1.338 -reg jtag_access; // Indicates if a JTAG WB access is in progress 1.339 -`endif 1.340 - 1.341 -///////////////////////////////////////////////////// 1.342 -// Functions 1.343 -///////////////////////////////////////////////////// 1.344 - 1.345 -`include "lm32_functions.v" 1.346 - 1.347 -///////////////////////////////////////////////////// 1.348 -// Instantiations 1.349 -///////////////////////////////////////////////////// 1.350 - 1.351 -// Instruction ROM 1.352 -`ifdef CFG_IROM_ENABLED 1.353 - pmi_ram_dp_true 1.354 - #( 1.355 - // ----- Parameters ------- 1.356 - .pmi_family (`LATTICE_FAMILY), 1.357 - 1.358 - //.pmi_addr_depth_a (1 << (clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)), 1.359 - //.pmi_addr_width_a ((clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)), 1.360 - //.pmi_data_width_a (`LM32_WORD_WIDTH), 1.361 - //.pmi_addr_depth_b (1 << (clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)), 1.362 - //.pmi_addr_width_b ((clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)), 1.363 - //.pmi_data_width_b (`LM32_WORD_WIDTH), 1.364 - 1.365 - .pmi_addr_depth_a (`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1), 1.366 - .pmi_addr_width_a (clogb2_v1(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)), 1.367 - .pmi_data_width_a (`LM32_WORD_WIDTH), 1.368 - .pmi_addr_depth_b (`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1), 1.369 - .pmi_addr_width_b (clogb2_v1(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)), 1.370 - .pmi_data_width_b (`LM32_WORD_WIDTH), 1.371 - 1.372 - .pmi_regmode_a ("noreg"), 1.373 - .pmi_regmode_b ("noreg"), 1.374 - .pmi_gsr ("enable"), 1.375 - .pmi_resetmode ("sync"), 1.376 - .pmi_init_file (`CFG_IROM_INIT_FILE), 1.377 - .pmi_init_file_format (`CFG_IROM_INIT_FILE_FORMAT), 1.378 - .module_type ("pmi_ram_dp_true") 1.379 - ) 1.380 - ram ( 1.381 - // ----- Inputs ------- 1.382 - .ClockA (clk_i), 1.383 - .ClockB (clk_i), 1.384 - .ResetA (rst_i), 1.385 - .ResetB (rst_i), 1.386 - .DataInA ({32{1'b0}}), 1.387 - .DataInB (irom_store_data_m), 1.388 - .AddressA (pc_a[(clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)+2-1:2]), 1.389 - .AddressB (irom_address_xm[(clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)+2-1:2]), 1.390 - .ClockEnA (!stall_a), 1.391 - .ClockEnB (!stall_x || !stall_m), 1.392 - .WrA (`FALSE), 1.393 - .WrB (irom_we_xm), 1.394 - // ----- Outputs ------- 1.395 - .QA (irom_data_f), 1.396 - .QB (irom_data_m) 1.397 - ); 1.398 -`endif 1.399 - 1.400 -`ifdef CFG_ICACHE_ENABLED 1.401 -// Instruction cache 1.402 -lm32_icache #( 1.403 - .associativity (associativity), 1.404 - .sets (sets), 1.405 - .bytes_per_line (bytes_per_line), 1.406 - .base_address (base_address), 1.407 - .limit (limit) 1.408 - ) icache ( 1.409 - // ----- Inputs ----- 1.410 - .clk_i (clk_i), 1.411 - .rst_i (rst_i), 1.412 - .stall_a (stall_a), 1.413 - .stall_f (stall_f), 1.414 - .branch_predict_taken_d (branch_predict_taken_d), 1.415 - .valid_d (valid_d), 1.416 - .address_a (pc_a), 1.417 - .address_f (pc_f), 1.418 - .read_enable_f (icache_read_enable_f), 1.419 - .refill_ready (icache_refill_ready), 1.420 - .refill_data (icache_refill_data), 1.421 - .iflush (iflush), 1.422 - // ----- Outputs ----- 1.423 - .stall_request (icache_stall_request), 1.424 - .restart_request (icache_restart_request), 1.425 - .refill_request (icache_refill_request), 1.426 - .refill_address (icache_refill_address), 1.427 - .refilling (icache_refilling), 1.428 - .inst (icache_data_f) 1.429 - ); 1.430 -`endif 1.431 - 1.432 -///////////////////////////////////////////////////// 1.433 -// Combinational Logic 1.434 -///////////////////////////////////////////////////// 1.435 - 1.436 -`ifdef CFG_ICACHE_ENABLED 1.437 -// Generate signal that indicates when instruction cache misses are valid 1.438 -assign icache_read_enable_f = (valid_f == `TRUE) 1.439 - && (kill_f == `FALSE) 1.440 -`ifdef CFG_DCACHE_ENABLED 1.441 - && (dcache_restart_request == `FALSE) 1.442 -`endif 1.443 -`ifdef CFG_IROM_ENABLED 1.444 - && (irom_select_f == `FALSE) 1.445 -`endif 1.446 - ; 1.447 -`endif 1.448 - 1.449 -// Compute address of next instruction to fetch 1.450 -always @(*) 1.451 -begin 1.452 - // The request from the latest pipeline stage must take priority 1.453 -`ifdef CFG_DCACHE_ENABLED 1.454 - if (dcache_restart_request == `TRUE) 1.455 - pc_a = restart_address; 1.456 - else 1.457 -`endif 1.458 - if (branch_taken_m == `TRUE) 1.459 - if ((branch_mispredict_taken_m == `TRUE) && (exception_m == `FALSE)) 1.460 - pc_a = pc_x; 1.461 - else 1.462 - pc_a = branch_target_m; 1.463 -`ifdef CFG_FAST_UNCONDITIONAL_BRANCH 1.464 - else if (branch_taken_x == `TRUE) 1.465 - pc_a = branch_target_x; 1.466 -`endif 1.467 - else 1.468 - if ( (valid_d == `TRUE) && (branch_predict_taken_d == `TRUE) ) 1.469 - pc_a = branch_predict_address_d; 1.470 - else 1.471 -`ifdef CFG_ICACHE_ENABLED 1.472 - if (icache_restart_request == `TRUE) 1.473 - pc_a = restart_address; 1.474 - else 1.475 -`endif 1.476 - pc_a = pc_f + 1'b1; 1.477 -end 1.478 - 1.479 -// Select where instruction should be fetched from 1.480 -`ifdef CFG_IROM_ENABLED 1.481 -assign irom_select_a = ({pc_a, 2'b00} >= `CFG_IROM_BASE_ADDRESS) && ({pc_a, 2'b00} <= `CFG_IROM_LIMIT); 1.482 -`endif 1.483 - 1.484 -// Select instruction from selected source 1.485 -`ifdef CFG_ICACHE_ENABLED 1.486 -`ifdef CFG_IROM_ENABLED 1.487 -assign instruction_f = irom_select_f == `TRUE ? irom_data_f : icache_data_f; 1.488 -`else 1.489 -assign instruction_f = icache_data_f; 1.490 -`endif 1.491 -`else 1.492 -`ifdef CFG_IROM_ENABLED 1.493 -`ifdef CFG_IWB_ENABLED 1.494 -assign instruction_f = irom_select_f == `TRUE ? irom_data_f : wb_data_f; 1.495 -`else 1.496 -assign instruction_f = irom_data_f; 1.497 -`endif 1.498 -`else 1.499 -assign instruction_f = wb_data_f; 1.500 -`endif 1.501 -`endif 1.502 - 1.503 -// Unused/constant Wishbone signals 1.504 -`ifdef CFG_IWB_ENABLED 1.505 -`ifdef CFG_HW_DEBUG_ENABLED 1.506 -`else 1.507 -assign i_dat_o = 32'd0; 1.508 -assign i_we_o = `FALSE; 1.509 -assign i_sel_o = 4'b1111; 1.510 -`endif 1.511 -assign i_bte_o = `LM32_BTYPE_LINEAR; 1.512 -`endif 1.513 - 1.514 -`ifdef CFG_ICACHE_ENABLED 1.515 -// Determine parameters for next cache refill Wishbone access 1.516 -generate 1.517 - case (bytes_per_line) 1.518 - 4: 1.519 - begin 1.520 -assign first_cycle_type = `LM32_CTYPE_END; 1.521 -assign next_cycle_type = `LM32_CTYPE_END; 1.522 -assign last_word = `TRUE; 1.523 -assign first_address = icache_refill_address; 1.524 - end 1.525 - 8: 1.526 - begin 1.527 -assign first_cycle_type = `LM32_CTYPE_INCREMENTING; 1.528 -assign next_cycle_type = `LM32_CTYPE_END; 1.529 -assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 1'b1; 1.530 -assign first_address = {icache_refill_address[`LM32_PC_WIDTH+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}}; 1.531 - end 1.532 - 16: 1.533 - begin 1.534 -assign first_cycle_type = `LM32_CTYPE_INCREMENTING; 1.535 -assign next_cycle_type = i_adr_o[addr_offset_msb] == 1'b1 ? `LM32_CTYPE_END : `LM32_CTYPE_INCREMENTING; 1.536 -assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 2'b11; 1.537 -assign first_address = {icache_refill_address[`LM32_PC_WIDTH+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}}; 1.538 - end 1.539 - endcase 1.540 -endgenerate 1.541 -`endif 1.542 - 1.543 -///////////////////////////////////////////////////// 1.544 -// Sequential Logic 1.545 -///////////////////////////////////////////////////// 1.546 - 1.547 -// PC 1.548 -always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.549 -begin 1.550 - if (rst_i == `TRUE) 1.551 - begin 1.552 - pc_f <= (`CFG_EBA_RESET-4)/4; 1.553 - pc_d <= {`LM32_PC_WIDTH{1'b0}}; 1.554 - pc_x <= {`LM32_PC_WIDTH{1'b0}}; 1.555 - pc_m <= {`LM32_PC_WIDTH{1'b0}}; 1.556 - pc_w <= {`LM32_PC_WIDTH{1'b0}}; 1.557 - end 1.558 - else 1.559 - begin 1.560 - if (stall_f == `FALSE) 1.561 - pc_f <= pc_a; 1.562 - if (stall_d == `FALSE) 1.563 - pc_d <= pc_f; 1.564 - if (stall_x == `FALSE) 1.565 - pc_x <= pc_d; 1.566 - if (stall_m == `FALSE) 1.567 - pc_m <= pc_x; 1.568 - pc_w <= pc_m; 1.569 - end 1.570 -end 1.571 - 1.572 -`ifdef LM32_CACHE_ENABLED 1.573 -// Address to restart from after a cache miss has been handled 1.574 -always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.575 -begin 1.576 - if (rst_i == `TRUE) 1.577 - restart_address <= {`LM32_PC_WIDTH{1'b0}}; 1.578 - else 1.579 - begin 1.580 -`ifdef CFG_DCACHE_ENABLED 1.581 -`ifdef CFG_ICACHE_ENABLED 1.582 - // D-cache restart address must take priority, otherwise instructions will be lost 1.583 - if (dcache_refill_request == `TRUE) 1.584 - restart_address <= pc_w; 1.585 - else if ((icache_refill_request == `TRUE) && (!dcache_refilling) && (!dcache_restart_request)) 1.586 - restart_address <= icache_refill_address; 1.587 -`else 1.588 - if (dcache_refill_request == `TRUE) 1.589 - restart_address <= pc_w; 1.590 -`endif 1.591 -`else 1.592 -`ifdef CFG_ICACHE_ENABLED 1.593 - if (icache_refill_request == `TRUE) 1.594 - restart_address <= icache_refill_address; 1.595 -`endif 1.596 -`endif 1.597 - end 1.598 -end 1.599 -`endif 1.600 - 1.601 -// Record where instruction was fetched from 1.602 -`ifdef CFG_IROM_ENABLED 1.603 -always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.604 -begin 1.605 - if (rst_i == `TRUE) 1.606 - irom_select_f <= `FALSE; 1.607 - else 1.608 - begin 1.609 - if (stall_f == `FALSE) 1.610 - irom_select_f <= irom_select_a; 1.611 - end 1.612 -end 1.613 -`endif 1.614 - 1.615 -`ifdef CFG_HW_DEBUG_ENABLED 1.616 -assign jtag_access_complete = (i_cyc_o == `TRUE) && ((i_ack_i == `TRUE) || (i_err_i == `TRUE)) && (jtag_access == `TRUE); 1.617 -always @(*) 1.618 -begin 1.619 - case (jtag_address[1:0]) 1.620 - 2'b00: jtag_read_data = i_dat_i[`LM32_BYTE_3_RNG]; 1.621 - 2'b01: jtag_read_data = i_dat_i[`LM32_BYTE_2_RNG]; 1.622 - 2'b10: jtag_read_data = i_dat_i[`LM32_BYTE_1_RNG]; 1.623 - 2'b11: jtag_read_data = i_dat_i[`LM32_BYTE_0_RNG]; 1.624 - endcase 1.625 -end 1.626 -`endif 1.627 - 1.628 -`ifdef CFG_IWB_ENABLED 1.629 -// Instruction Wishbone interface 1.630 -`ifdef CFG_ICACHE_ENABLED 1.631 -always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.632 -begin 1.633 - if (rst_i == `TRUE) 1.634 - begin 1.635 - i_cyc_o <= `FALSE; 1.636 - i_stb_o <= `FALSE; 1.637 - i_adr_o <= {`LM32_WORD_WIDTH{1'b0}}; 1.638 - i_cti_o <= `LM32_CTYPE_END; 1.639 - i_lock_o <= `FALSE; 1.640 - icache_refill_data <= {`LM32_INSTRUCTION_WIDTH{1'b0}}; 1.641 - icache_refill_ready <= `FALSE; 1.642 -`ifdef CFG_BUS_ERRORS_ENABLED 1.643 - bus_error_f <= `FALSE; 1.644 -`endif 1.645 -`ifdef CFG_HW_DEBUG_ENABLED 1.646 - i_we_o <= `FALSE; 1.647 - i_sel_o <= 4'b1111; 1.648 - jtag_access <= `FALSE; 1.649 -`endif 1.650 - end 1.651 - else 1.652 - begin 1.653 - icache_refill_ready <= `FALSE; 1.654 - // Is a cycle in progress? 1.655 - if (i_cyc_o == `TRUE) 1.656 - begin 1.657 - // Has cycle completed? 1.658 - if ((i_ack_i == `TRUE) || (i_err_i == `TRUE)) 1.659 - begin 1.660 -`ifdef CFG_HW_DEBUG_ENABLED 1.661 - if (jtag_access == `TRUE) 1.662 - begin 1.663 - i_cyc_o <= `FALSE; 1.664 - i_stb_o <= `FALSE; 1.665 - i_we_o <= `FALSE; 1.666 - jtag_access <= `FALSE; 1.667 - end 1.668 - else 1.669 -`endif 1.670 - begin 1.671 - if (last_word == `TRUE) 1.672 - begin 1.673 - // Cache line fill complete 1.674 - i_cyc_o <= `FALSE; 1.675 - i_stb_o <= `FALSE; 1.676 - i_lock_o <= `FALSE; 1.677 - end 1.678 - // Fetch next word in cache line 1.679 - i_adr_o[addr_offset_msb:addr_offset_lsb] <= i_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1; 1.680 - i_cti_o <= next_cycle_type; 1.681 - // Write fetched data into instruction cache 1.682 - icache_refill_ready <= `TRUE; 1.683 - icache_refill_data <= i_dat_i; 1.684 - end 1.685 - end 1.686 -`ifdef CFG_BUS_ERRORS_ENABLED 1.687 - if (i_err_i == `TRUE) 1.688 - begin 1.689 - bus_error_f <= `TRUE; 1.690 - $display ("Instruction bus error. Address: %x", i_adr_o); 1.691 - end 1.692 -`endif 1.693 - end 1.694 - else 1.695 - begin 1.696 - if ((icache_refill_request == `TRUE) && (icache_refill_ready == `FALSE)) 1.697 - begin 1.698 - // Read first word of cache line 1.699 -`ifdef CFG_HW_DEBUG_ENABLED 1.700 - i_sel_o <= 4'b1111; 1.701 -`endif 1.702 - i_adr_o <= {first_address, 2'b00}; 1.703 - i_cyc_o <= `TRUE; 1.704 - i_stb_o <= `TRUE; 1.705 - i_cti_o <= first_cycle_type; 1.706 - //i_lock_o <= `TRUE; 1.707 -`ifdef CFG_BUS_ERRORS_ENABLED 1.708 - bus_error_f <= `FALSE; 1.709 -`endif 1.710 - end 1.711 -`ifdef CFG_HW_DEBUG_ENABLED 1.712 - else 1.713 - begin 1.714 - if ((jtag_read_enable == `TRUE) || (jtag_write_enable == `TRUE)) 1.715 - begin 1.716 - case (jtag_address[1:0]) 1.717 - 2'b00: i_sel_o <= 4'b1000; 1.718 - 2'b01: i_sel_o <= 4'b0100; 1.719 - 2'b10: i_sel_o <= 4'b0010; 1.720 - 2'b11: i_sel_o <= 4'b0001; 1.721 - endcase 1.722 - i_adr_o <= jtag_address; 1.723 - i_dat_o <= {4{jtag_write_data}}; 1.724 - i_cyc_o <= `TRUE; 1.725 - i_stb_o <= `TRUE; 1.726 - i_we_o <= jtag_write_enable; 1.727 - i_cti_o <= `LM32_CTYPE_END; 1.728 - jtag_access <= `TRUE; 1.729 - end 1.730 - end 1.731 -`endif 1.732 -`ifdef CFG_BUS_ERRORS_ENABLED 1.733 - // Clear bus error when exception taken, otherwise they would be 1.734 - // continually generated if exception handler is cached 1.735 -`ifdef CFG_FAST_UNCONDITIONAL_BRANCH 1.736 - if (branch_taken_x == `TRUE) 1.737 - bus_error_f <= `FALSE; 1.738 -`endif 1.739 - if (branch_taken_m == `TRUE) 1.740 - bus_error_f <= `FALSE; 1.741 -`endif 1.742 - end 1.743 - end 1.744 -end 1.745 -`else 1.746 -always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.747 -begin 1.748 - if (rst_i == `TRUE) 1.749 - begin 1.750 - i_cyc_o <= `FALSE; 1.751 - i_stb_o <= `FALSE; 1.752 - i_adr_o <= {`LM32_WORD_WIDTH{1'b0}}; 1.753 - i_cti_o <= `LM32_CTYPE_END; 1.754 - i_lock_o <= `FALSE; 1.755 - wb_data_f <= {`LM32_INSTRUCTION_WIDTH{1'b0}}; 1.756 -`ifdef CFG_BUS_ERRORS_ENABLED 1.757 - bus_error_f <= `FALSE; 1.758 -`endif 1.759 - end 1.760 - else 1.761 - begin 1.762 - // Is a cycle in progress? 1.763 - if (i_cyc_o == `TRUE) 1.764 - begin 1.765 - // Has cycle completed? 1.766 - if((i_ack_i == `TRUE) || (i_err_i == `TRUE)) 1.767 - begin 1.768 - // Cycle complete 1.769 - i_cyc_o <= `FALSE; 1.770 - i_stb_o <= `FALSE; 1.771 - // Register fetched instruction 1.772 - wb_data_f <= i_dat_i; 1.773 - end 1.774 -`ifdef CFG_BUS_ERRORS_ENABLED 1.775 - if (i_err_i == `TRUE) 1.776 - begin 1.777 - bus_error_f <= `TRUE; 1.778 - $display ("Instruction bus error. Address: %x", i_adr_o); 1.779 - end 1.780 -`endif 1.781 - end 1.782 - else 1.783 - begin 1.784 - // Wait for an instruction fetch from an external address 1.785 - if ( (stall_a == `FALSE) 1.786 -`ifdef CFG_IROM_ENABLED 1.787 - && (irom_select_a == `FALSE) 1.788 -`endif 1.789 - ) 1.790 - begin 1.791 - // Fetch instruction 1.792 -`ifdef CFG_HW_DEBUG_ENABLED 1.793 - i_sel_o <= 4'b1111; 1.794 -`endif 1.795 - i_adr_o <= {pc_a, 2'b00}; 1.796 - i_cyc_o <= `TRUE; 1.797 - i_stb_o <= `TRUE; 1.798 -`ifdef CFG_BUS_ERRORS_ENABLED 1.799 - bus_error_f <= `FALSE; 1.800 -`endif 1.801 - end 1.802 - else 1.803 - begin 1.804 - if ( (stall_a == `FALSE) 1.805 -`ifdef CFG_IROM_ENABLED 1.806 - && (irom_select_a == `TRUE) 1.807 -`endif 1.808 - ) 1.809 - begin 1.810 -`ifdef CFG_BUS_ERRORS_ENABLED 1.811 - bus_error_f <= `FALSE; 1.812 -`endif 1.813 - end 1.814 - end 1.815 - end 1.816 - end 1.817 -end 1.818 -`endif 1.819 -`endif 1.820 - 1.821 -// Instruction register 1.822 -always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.823 -begin 1.824 - if (rst_i == `TRUE) 1.825 - begin 1.826 - instruction_d <= {`LM32_INSTRUCTION_WIDTH{1'b0}}; 1.827 -`ifdef CFG_BUS_ERRORS_ENABLED 1.828 - bus_error_d <= `FALSE; 1.829 -`endif 1.830 - end 1.831 - else 1.832 - begin 1.833 - if (stall_d == `FALSE) 1.834 - begin 1.835 - instruction_d <= instruction_f; 1.836 -`ifdef CFG_BUS_ERRORS_ENABLED 1.837 - bus_error_d <= bus_error_f; 1.838 -`endif 1.839 - end 1.840 - end 1.841 -end 1.842 - 1.843 -endmodule