1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 1.2 +++ b/rtl/lm32_include.v Tue Mar 08 09:40:42 2011 +0000 1.3 @@ -0,0 +1,368 @@ 1.4 +// ============================================================================= 1.5 +// COPYRIGHT NOTICE 1.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation 1.7 +// ALL RIGHTS RESERVED 1.8 +// This confidential and proprietary software may be used only as authorised by 1.9 +// a licensing agreement from Lattice Semiconductor Corporation. 1.10 +// The entire notice above must be reproduced on all authorized copies and 1.11 +// copies may only be made to the extent permitted by a licensing agreement from 1.12 +// Lattice Semiconductor Corporation. 1.13 +// 1.14 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 1.15 +// 5555 NE Moore Court 408-826-6000 (other locations) 1.16 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 1.17 +// U.S.A email: techsupport@latticesemi.com 1.18 +// =============================================================================/ 1.19 +// FILE DETAILS 1.20 +// Project : LatticeMico32 1.21 +// File : lm32_include.v 1.22 +// Title : CPU global macros 1.23 +// Version : 6.1.17 1.24 +// : Initial Release 1.25 +// Version : 7.0SP2, 3.0 1.26 +// : No Change 1.27 +// Version : 3.1 1.28 +// : No Change 1.29 +// Version : 3.2 1.30 +// : No Change 1.31 +// Version : 3.3 1.32 +// : Support for extended configuration register 1.33 +// ============================================================================= 1.34 + 1.35 +`ifdef LM32_INCLUDE_V 1.36 +`else 1.37 +`define LM32_INCLUDE_V 1.38 + 1.39 +// 1.40 +// Common configuration options 1.41 +// 1.42 + 1.43 +`define CFG_EBA_RESET 32'h00000000 1.44 +`define CFG_DEBA_RESET 32'h10000000 1.45 + 1.46 +`define CFG_PL_MULTIPLY_ENABLED 1.47 +`define CFG_PL_BARREL_SHIFT_ENABLED 1.48 +`define CFG_SIGN_EXTEND_ENABLED 1.49 +`define CFG_MC_DIVIDE_ENABLED 1.50 +`define CFG_EBR_POSEDGE_REGISTER_FILE 1.51 + 1.52 +// [found by Milkymist dev'rs] 1.53 +// Bug in Xst: 1.54 +// CFG_ICACHE_ASSOCIATIVITY=2 => works in most cases (random crash on complex software) 1.55 +// CFG_ICACHE_ASSOCIATIVITY=1 => disaster, CPU will not work at all 1.56 +// Works 100% OK with expensive synthesizers. 1.57 +`define CFG_ICACHE_ENABLED 1.58 +`define CFG_ICACHE_ASSOCIATIVITY 1 1.59 +`define CFG_ICACHE_SETS 256 1.60 +`define CFG_ICACHE_BYTES_PER_LINE 16 1.61 +`define CFG_ICACHE_BASE_ADDRESS 32'h0 1.62 +`define CFG_ICACHE_LIMIT 32'h7FFF_FFFF 1.63 + 1.64 +`define CFG_DCACHE_ENABLED 1.65 +`define CFG_DCACHE_ASSOCIATIVITY 1 1.66 +`define CFG_DCACHE_SETS 256 1.67 +`define CFG_DCACHE_BYTES_PER_LINE 16 1.68 +`define CFG_DCACHE_BASE_ADDRESS 32'h0 1.69 +`define CFG_DCACHE_LIMIT 32'h0FFF_FFFF 1.70 + 1.71 +// Enable Debugging 1.72 +//`define CFG_JTAG_ENABLED 1.73 +//`define CFG_JTAG_UART_ENABLED 1.74 +//`define CFG_DEBUG_ENABLED 1.75 +//`define CFG_HW_DEBUG_ENABLED 1.76 +//`define CFG_ROM_DEBUG_ENABLED 1.77 +//`define CFG_BREAKPOINTS 32'h0 1.78 +//`define CFG_WATCHPOINTS 32'h0 1.79 + 1.80 +// 1.81 +// End of common configuration options 1.82 +// 1.83 + 1.84 +`ifdef TRUE 1.85 +`else 1.86 +`define TRUE 1'b1 1.87 +`define FALSE 1'b0 1.88 +`define TRUE_N 1'b0 1.89 +`define FALSE_N 1'b1 1.90 +`endif 1.91 + 1.92 +// Wishbone configuration 1.93 +`define CFG_IWB_ENABLED 1.94 +`define CFG_DWB_ENABLED 1.95 + 1.96 +// Data-path width 1.97 +`define LM32_WORD_WIDTH 32 1.98 +`define LM32_WORD_RNG (`LM32_WORD_WIDTH-1):0 1.99 +`define LM32_SHIFT_WIDTH 5 1.100 +`define LM32_SHIFT_RNG (`LM32_SHIFT_WIDTH-1):0 1.101 +`define LM32_BYTE_SELECT_WIDTH 4 1.102 +`define LM32_BYTE_SELECT_RNG (`LM32_BYTE_SELECT_WIDTH-1):0 1.103 + 1.104 +// Register file size 1.105 +`define LM32_REGISTERS 32 1.106 +`define LM32_REG_IDX_WIDTH 5 1.107 +`define LM32_REG_IDX_RNG (`LM32_REG_IDX_WIDTH-1):0 1.108 + 1.109 +// Standard register numbers 1.110 +`define LM32_RA_REG `LM32_REG_IDX_WIDTH'd29 1.111 +`define LM32_EA_REG `LM32_REG_IDX_WIDTH'd30 1.112 +`define LM32_BA_REG `LM32_REG_IDX_WIDTH'd31 1.113 + 1.114 +// Range of Program Counter. Two LSBs are always 0. 1.115 +// `ifdef CFG_ICACHE_ENABLED 1.116 +// `define LM32_PC_WIDTH (clogb2(`CFG_ICACHE_LIMIT-`CFG_ICACHE_BASE_ADDRESS)-2) 1.117 +// `else 1.118 +// `ifdef CFG_IWB_ENABLED 1.119 +`define LM32_PC_WIDTH (`LM32_WORD_WIDTH-2) 1.120 +// `else 1.121 +// `define LM32_PC_WIDTH `LM32_IROM_ADDRESS_WIDTH 1.122 +// `endif 1.123 +// `endif 1.124 +`define LM32_PC_RNG (`LM32_PC_WIDTH+2-1):2 1.125 + 1.126 +// Range of an instruction 1.127 +`define LM32_INSTRUCTION_WIDTH 32 1.128 +`define LM32_INSTRUCTION_RNG (`LM32_INSTRUCTION_WIDTH-1):0 1.129 + 1.130 +// Adder operation 1.131 +`define LM32_ADDER_OP_ADD 1'b0 1.132 +`define LM32_ADDER_OP_SUBTRACT 1'b1 1.133 + 1.134 +// Shift direction 1.135 +`define LM32_SHIFT_OP_RIGHT 1'b0 1.136 +`define LM32_SHIFT_OP_LEFT 1'b1 1.137 + 1.138 +// Bus errors 1.139 +//`define CFG_BUS_ERRORS_ENABLED 1.140 + 1.141 +// Derive macro that indicates whether we have single-stepping or not 1.142 +`ifdef CFG_ROM_DEBUG_ENABLED 1.143 +`define LM32_SINGLE_STEP_ENABLED 1.144 +`else 1.145 +`ifdef CFG_HW_DEBUG_ENABLED 1.146 +`define LM32_SINGLE_STEP_ENABLED 1.147 +`endif 1.148 +`endif 1.149 + 1.150 +// Derive macro that indicates whether JTAG interface is required 1.151 +`ifdef CFG_JTAG_UART_ENABLED 1.152 +`define LM32_JTAG_ENABLED 1.153 +`else 1.154 +`ifdef CFG_DEBUG_ENABLED 1.155 +`define LM32_JTAG_ENABLED 1.156 +`else 1.157 +`endif 1.158 +`endif 1.159 + 1.160 +// Derive macro that indicates whether we have a barrel-shifter or not 1.161 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 1.162 +`define LM32_BARREL_SHIFT_ENABLED 1.163 +`else // CFG_PL_BARREL_SHIFT_ENABLED 1.164 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED 1.165 +`define LM32_BARREL_SHIFT_ENABLED 1.166 +`else 1.167 +`define LM32_NO_BARREL_SHIFT 1.168 +`endif 1.169 +`endif // CFG_PL_BARREL_SHIFT_ENABLED 1.170 + 1.171 +// Derive macro that indicates whether we have a multiplier or not 1.172 +`ifdef CFG_PL_MULTIPLY_ENABLED 1.173 +`define LM32_MULTIPLY_ENABLED 1.174 +`else 1.175 +`ifdef CFG_MC_MULTIPLY_ENABLED 1.176 +`define LM32_MULTIPLY_ENABLED 1.177 +`endif 1.178 +`endif 1.179 + 1.180 +// Derive a macro that indicates whether or not the multi-cycle arithmetic unit is required 1.181 +`ifdef CFG_MC_DIVIDE_ENABLED 1.182 +`define LM32_MC_ARITHMETIC_ENABLED 1.183 +`endif 1.184 +`ifdef CFG_MC_MULTIPLY_ENABLED 1.185 +`define LM32_MC_ARITHMETIC_ENABLED 1.186 +`endif 1.187 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED 1.188 +`define LM32_MC_ARITHMETIC_ENABLED 1.189 +`endif 1.190 + 1.191 +// Derive macro that indicates if we are using an EBR register file 1.192 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE 1.193 +`define LM32_EBR_REGISTER_FILE 1.194 +`endif 1.195 +`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE 1.196 +`define LM32_EBR_REGISTER_FILE 1.197 +`endif 1.198 + 1.199 +// Revision number 1.200 +`define LM32_REVISION 6'h02 1.201 + 1.202 +// Logical operations - Function encoded directly in instruction 1.203 +`define LM32_LOGIC_OP_RNG 3:0 1.204 + 1.205 +// Conditions for conditional branches 1.206 +`define LM32_CONDITION_WIDTH 3 1.207 +`define LM32_CONDITION_RNG (`LM32_CONDITION_WIDTH-1):0 1.208 +`define LM32_CONDITION_E 3'b001 1.209 +`define LM32_CONDITION_G 3'b010 1.210 +`define LM32_CONDITION_GE 3'b011 1.211 +`define LM32_CONDITION_GEU 3'b100 1.212 +`define LM32_CONDITION_GU 3'b101 1.213 +`define LM32_CONDITION_NE 3'b111 1.214 +`define LM32_CONDITION_U1 3'b000 1.215 +`define LM32_CONDITION_U2 3'b110 1.216 + 1.217 +// Size of load or store instruction - Encoding corresponds to opcode 1.218 +`define LM32_SIZE_WIDTH 2 1.219 +`define LM32_SIZE_RNG 1:0 1.220 +`define LM32_SIZE_BYTE 2'b00 1.221 +`define LM32_SIZE_HWORD 2'b11 1.222 +`define LM32_SIZE_WORD 2'b10 1.223 +`define LM32_ADDRESS_LSBS_WIDTH 2 1.224 + 1.225 +// Width and range of a CSR index 1.226 +`ifdef CFG_DEBUG_ENABLED 1.227 +`define LM32_CSR_WIDTH 5 1.228 +`define LM32_CSR_RNG (`LM32_CSR_WIDTH-1):0 1.229 +`else 1.230 +`ifdef CFG_JTAG_ENABLED 1.231 +`define LM32_CSR_WIDTH 4 1.232 +`define LM32_CSR_RNG (`LM32_CSR_WIDTH-1):0 1.233 +`else 1.234 +`define LM32_CSR_WIDTH 3 1.235 +`define LM32_CSR_RNG (`LM32_CSR_WIDTH-1):0 1.236 +`endif 1.237 +`endif 1.238 + 1.239 +// CSR indices 1.240 +`define LM32_CSR_IE `LM32_CSR_WIDTH'h0 1.241 +`define LM32_CSR_IM `LM32_CSR_WIDTH'h1 1.242 +`define LM32_CSR_IP `LM32_CSR_WIDTH'h2 1.243 +`define LM32_CSR_ICC `LM32_CSR_WIDTH'h3 1.244 +`define LM32_CSR_DCC `LM32_CSR_WIDTH'h4 1.245 +`define LM32_CSR_CC `LM32_CSR_WIDTH'h5 1.246 +`define LM32_CSR_CFG `LM32_CSR_WIDTH'h6 1.247 +`define LM32_CSR_EBA `LM32_CSR_WIDTH'h7 1.248 +`ifdef CFG_DEBUG_ENABLED 1.249 +`define LM32_CSR_DC `LM32_CSR_WIDTH'h8 1.250 +`define LM32_CSR_DEBA `LM32_CSR_WIDTH'h9 1.251 +`endif 1.252 +`define LM32_CSR_CFG2 `LM32_CSR_WIDTH'ha 1.253 +`ifdef CFG_JTAG_ENABLED 1.254 +`define LM32_CSR_JTX `LM32_CSR_WIDTH'he 1.255 +`define LM32_CSR_JRX `LM32_CSR_WIDTH'hf 1.256 +`endif 1.257 +`ifdef CFG_DEBUG_ENABLED 1.258 +`define LM32_CSR_BP0 `LM32_CSR_WIDTH'h10 1.259 +`define LM32_CSR_BP1 `LM32_CSR_WIDTH'h11 1.260 +`define LM32_CSR_BP2 `LM32_CSR_WIDTH'h12 1.261 +`define LM32_CSR_BP3 `LM32_CSR_WIDTH'h13 1.262 +`define LM32_CSR_WP0 `LM32_CSR_WIDTH'h18 1.263 +`define LM32_CSR_WP1 `LM32_CSR_WIDTH'h19 1.264 +`define LM32_CSR_WP2 `LM32_CSR_WIDTH'h1a 1.265 +`define LM32_CSR_WP3 `LM32_CSR_WIDTH'h1b 1.266 +`endif 1.267 + 1.268 +// Values for WPC CSR 1.269 +`define LM32_WPC_C_RNG 1:0 1.270 +`define LM32_WPC_C_DISABLED 2'b00 1.271 +`define LM32_WPC_C_READ 2'b01 1.272 +`define LM32_WPC_C_WRITE 2'b10 1.273 +`define LM32_WPC_C_READ_WRITE 2'b11 1.274 + 1.275 +// Exception IDs 1.276 +`define LM32_EID_WIDTH 3 1.277 +`define LM32_EID_RNG (`LM32_EID_WIDTH-1):0 1.278 +`define LM32_EID_RESET 3'h0 1.279 +`define LM32_EID_BREAKPOINT 3'd1 1.280 +`define LM32_EID_INST_BUS_ERROR 3'h2 1.281 +`define LM32_EID_WATCHPOINT 3'd3 1.282 +`define LM32_EID_DATA_BUS_ERROR 3'h4 1.283 +`define LM32_EID_DIVIDE_BY_ZERO 3'h5 1.284 +`define LM32_EID_INTERRUPT 3'h6 1.285 +`define LM32_EID_SCALL 3'h7 1.286 + 1.287 +// Pipeline result selection mux controls 1.288 + 1.289 +`define LM32_D_RESULT_SEL_0_RNG 0:0 1.290 +`define LM32_D_RESULT_SEL_0_REG_0 1'b0 1.291 +`define LM32_D_RESULT_SEL_0_NEXT_PC 1'b1 1.292 + 1.293 +`define LM32_D_RESULT_SEL_1_RNG 1:0 1.294 +`define LM32_D_RESULT_SEL_1_ZERO 2'b00 1.295 +`define LM32_D_RESULT_SEL_1_REG_1 2'b01 1.296 +`define LM32_D_RESULT_SEL_1_IMMEDIATE 2'b10 1.297 + 1.298 +`define LM32_USER_OPCODE_WIDTH 11 1.299 +`define LM32_USER_OPCODE_RNG (`LM32_USER_OPCODE_WIDTH-1):0 1.300 + 1.301 +// Derive a macro to indicate if either of the caches are implemented 1.302 +`ifdef CFG_ICACHE_ENABLED 1.303 +`define LM32_CACHE_ENABLED 1.304 +`else 1.305 +`ifdef CFG_DCACHE_ENABLED 1.306 +`define LM32_CACHE_ENABLED 1.307 +`endif 1.308 +`endif 1.309 + 1.310 +///////////////////////////////////////////////////// 1.311 +// Interrupts 1.312 +///////////////////////////////////////////////////// 1.313 + 1.314 +// Always enable interrupts 1.315 +`define CFG_INTERRUPTS_ENABLED 1.316 + 1.317 +// Currently this is fixed to 32 and should not be changed 1.318 +`define CFG_INTERRUPTS 32 1.319 +`define LM32_INTERRUPT_WIDTH `CFG_INTERRUPTS 1.320 +`define LM32_INTERRUPT_RNG (`LM32_INTERRUPT_WIDTH-1):0 1.321 + 1.322 +///////////////////////////////////////////////////// 1.323 +// General 1.324 +///////////////////////////////////////////////////// 1.325 + 1.326 +// Sub-word range types 1.327 +`define LM32_BYTE_WIDTH 8 1.328 +`define LM32_BYTE_RNG 7:0 1.329 +`define LM32_HWORD_WIDTH 16 1.330 +`define LM32_HWORD_RNG 15:0 1.331 + 1.332 +// Word sub-byte indicies 1.333 +`define LM32_BYTE_0_RNG 7:0 1.334 +`define LM32_BYTE_1_RNG 15:8 1.335 +`define LM32_BYTE_2_RNG 23:16 1.336 +`define LM32_BYTE_3_RNG 31:24 1.337 + 1.338 +// Word sub-halfword indices 1.339 +`define LM32_HWORD_0_RNG 15:0 1.340 +`define LM32_HWORD_1_RNG 31:16 1.341 + 1.342 +// Use an asynchronous reset 1.343 +// To use a synchronous reset, define this macro as nothing 1.344 +//`define CFG_RESET_SENSITIVITY or posedge rst_i 1.345 +`define CFG_RESET_SENSITIVITY 1.346 + 1.347 +// Whether to include context registers for debug exceptions 1.348 +// in addition to standard exception handling registers 1.349 +`define CFG_DEBUG_EXCEPTIONS_ENABLED 1.350 + 1.351 +// Wishbone defines 1.352 +// Refer to Wishbone System-on-Chip Interconnection Architecture 1.353 +// These should probably be moved to a Wishbone common file 1.354 + 1.355 +// Wishbone cycle types 1.356 +`define LM32_CTYPE_WIDTH 3 1.357 +`define LM32_CTYPE_RNG (`LM32_CTYPE_WIDTH-1):0 1.358 +`define LM32_CTYPE_CLASSIC 3'b000 1.359 +`define LM32_CTYPE_CONSTANT 3'b001 1.360 +`define LM32_CTYPE_INCREMENTING 3'b010 1.361 +`define LM32_CTYPE_END 3'b111 1.362 + 1.363 +// Wishbone burst types 1.364 +`define LM32_BTYPE_WIDTH 2 1.365 +`define LM32_BTYPE_RNG (`LM32_BTYPE_WIDTH-1):0 1.366 +`define LM32_BTYPE_LINEAR 2'b00 1.367 +`define LM32_BTYPE_4_BEAT 2'b01 1.368 +`define LM32_BTYPE_8_BEAT 2'b10 1.369 +`define LM32_BTYPE_16_BEAT 2'b11 1.370 + 1.371 +`endif