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1.107 + 1.108 + } 1.109 + 1.110 + 1.111 + if (window.setRelStartPage) 1.112 + { 1.113 + setRelStartPage("msb_peripherals.htm"); 1.114 + 1.115 + autoSync(0); 1.116 + sendSyncInfo(); 1.117 + sendAveInfoOut(); 1.118 + } 1.119 + 1.120 +} 1.121 +else 1.122 + if (window.gbIE4) 1.123 + document.location.reload(); 1.124 +//--> 1.125 +</script> 1.126 +</head> 1.127 +<body><script type="text/javascript" language="javascript1.2"> 1.128 +<!-- 1.129 +if (window.writeIntopicBar) 1.130 + writeIntopicBar(4); 1.131 +//--> 1.132 +</script> 1.133 +<h1>LatticeMico32 Processor <a title="View Reference Manual" href="lm32_archman.pdf" target="_blank" onmouseover="if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) ehlp_showtip(this,event,'View Reference Manual');" onmouseout="if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) ehlp_hidetip();"><img src="ds_icon_ast.jpg" x-maintain-ratio="TRUE" width="29px" height="31px" border="0" class="img_whs1"></a></h1> 1.134 + 1.135 +<p>The LatticeMico32 processor is a high-performance 32-bit microprocessor 1.136 + optimized for Lattice Semiconductor field-programmable gate arrays. </p> 1.137 + 1.138 +<p class="whs2"><span style="font-style: italic;"><I>*If the 1.139 + processor manual fails to open, see the note at the bottom of this page.</I></span></p> 1.140 + 1.141 +<h2>Revision History</h2> 1.142 + 1.143 +<table x-use-null-cells cellspacing="0" width="738" height="84" class="whs3"> 1.144 +<script language='JavaScript'><!-- 1.145 +if ((navigator.appName == "Netscape") && (parseInt(navigator.appVersion) == 4)) document.write("</table><table x-use-null-cells cellspacing='0' width='738' height='84' border='1' bordercolor='silver' bordercolorlight='silver' bordercolordark='silver'>"); 1.146 +//--></script> 1.147 +<col class="whs4"> 1.148 +<col class="whs5"> 1.149 + 1.150 +<tr valign="top" class="whs6"> 1.151 +<td bgcolor="#DEE8F4" width="93px" class="whs7"> 1.152 +<p class=Table 1.153 + style="font-weight: bold;">Version</td> 1.154 +<td bgcolor="#DEE8F4" width="598px" class="whs8"> 1.155 +<p class=Table 1.156 + style="font-weight: bold;">Description</td></tr> 1.157 + 1.158 +<tr valign="top" class="whs6"> 1.159 +<td colspan="1" rowspan="1" width="93px" class="whs9"> 1.160 +<p class=Table 1.161 + style="font-weight: normal;">3.6</td> 1.162 +<td colspan="1" rowspan="1" width="598px" class="whs10"> 1.163 +<p class=whs10 1.164 + style="margin-left: 0px;">Fixed the issue of the processor locking 1.165 + up when Instruction Cache is not used.</td></tr> 1.166 + 1.167 +<tr valign="top" class="whs6"> 1.168 +<td colspan="1" rowspan="1" width="93px" class="whs9"> 1.169 +<p class=Table 1.170 + style="font-weight: normal;">3.5</td> 1.171 +<td colspan="1" rowspan="1" width="598px" class="whs10"> 1.172 +<p class=whs10 1.173 + style="margin-left: 0px;">Support added to allow Inline Memories to 1.174 + be generated as non-power-of-two, as long as they are a multiple of 1024 1.175 + bytes</td></tr> 1.176 + 1.177 +<tr valign="top" class="whs6"> 1.178 +<td colspan="1" rowspan="1" width="93px" class="whs9"> 1.179 +<p class=Table 1.180 + style="font-weight: normal;">3.4</td> 1.181 +<td colspan="1" rowspan="1" width="598px" class="whs10"> 1.182 +<p class=whs10 1.183 + style="margin-left: 0px;">Updated to support ispLEVER 7.2 SP1.</td></tr> 1.184 + 1.185 +<tr valign="top" class="whs6"> 1.186 +<td colspan="1" rowspan="1" width="93px" class="whs9"> 1.187 +<p class=Table 1.188 + style="font-weight: normal;">3.3</td> 1.189 +<td colspan="1" rowspan="1" width="598px" class="whs10"> 1.190 +<p class=whs10 1.191 + style="margin-left: 0px;">Updated to support ispLEVER 7.2.</p> 1.192 +<p class=whs10 1.193 + style="margin-left: 0px;">Added Inline Memory to support on-chip memory 1.194 + connected through a local bus.</td></tr> 1.195 + 1.196 +<tr valign="top" class="whs6"> 1.197 +<td colspan="1" rowspan="1" width="93px" class="whs9"> 1.198 +<p class=Table 1.199 + style="font-weight: normal;">3.2</td> 1.200 +<td colspan="1" rowspan="1" width="598px" class="whs10"> 1.201 +<p class=whs10 1.202 + style="margin-left: 0px;">Updated to support ispLEVER 7.1 SP1</p> 1.203 +<p class=whs10 1.204 + style="margin-left: 0px;">Added Memory Type to instruction cache and 1.205 + data cache.</td></tr> 1.206 + 1.207 +<tr valign="top" class="whs6"> 1.208 +<td colspan="1" rowspan="1" width="93px" class="whs9"> 1.209 +<p class=Table 1.210 + style="font-weight: normal;">3.1</td> 1.211 +<td colspan="1" rowspan="1" width="598px" class="whs10"> 1.212 +<p class="whs11">Updated to support ispLEVER 7.1.</p> 1.213 +<p class="whs11">Added static predictor to improve the behavior 1.214 + of branches.</p> 1.215 +<p class="whs11">Added support for optionally mapping the register 1.216 + file to EBRs (on-chip memory).</p> 1.217 +<p class="whs11">Added support for selecting between distributed 1.218 + RAM and EBRs (pseudo-dual port or true-dual port) for instruction and 1.219 + data caches.</td></tr> 1.220 + 1.221 +<tr valign="top" class="whs6"> 1.222 +<td colspan="1" rowspan="1" width="93px" class="whs9"> 1.223 +<p class=Table 1.224 + style="font-weight: normal;"><span style="font-weight: normal;">3.0 1.225 + (7.0 SP2)</span></td> 1.226 +<td colspan="1" rowspan="1" width="598px" class="whs10"> 1.227 +<p class="whs11">Updated to support ispLEVER 7.0 SP2.</p> 1.228 +<p class="whs11">Fixed incorrect handling of data cache miss 1.229 + in the presence of an instruction cache miss.</td></tr> 1.230 + 1.231 +<tr valign="top" class="whs6"> 1.232 +<td colspan="1" rowspan="1" width="93px" class="whs9"> 1.233 +<p class="whs11">1.0</td> 1.234 +<td colspan="1" rowspan="1" width="598px" class="whs10"> 1.235 +<p class="whs11">Initial version.</td></tr> 1.236 +<script language='JavaScript'><!-- 1.237 +if ((navigator.appName == "Netscape") && (parseInt(navigator.appVersion) == 4)) document.write("</table></table><table>"); 1.238 +//--></script> 1.239 +</table> 1.240 + 1.241 + 1.242 + 1.243 +<h2>Dialog Box Parameters – 1.244 + General Tab</h2> 1.245 + 1.246 +<table x-use-null-cells cellspacing="0" class="whs12"> 1.247 +<col class="whs13"> 1.248 +<col class="whs14"> 1.249 + 1.250 +<tr valign="top" class="whs15"> 1.251 +<td bgcolor="#DEE8F4" width="167px" class="whs16"> 1.252 +<p class=Table 1.253 + style="font-weight: bold;">Parameter</td> 1.254 +<td bgcolor="#DEE8F4" width="524px" class="whs17"> 1.255 +<p class=Table 1.256 + style="font-weight: bold;">Description</td></tr> 1.257 + 1.258 +<tr valign="top" class="whs15"> 1.259 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.260 +<p class=Table 1.261 + style="font-weight: normal;">Instance Name</td> 1.262 +<td colspan="1" rowspan="1" width="524px" class="whs19"> 1.263 +<p class=Table 1.264 + style="margin-left: 14px;">Specifies the name of the LatticeMico32 1.265 + processor. Alphanumeric values and underscores are supported. The default 1.266 + is LM32.</td></tr> 1.267 + 1.268 +<tr valign="top" class="whs15"> 1.269 +<td colspan="2" rowspan="1" width="691px" class="whs20"> 1.270 +<p class=Table 1.271 + style="font-weight: bold;">Settings</td> 1.272 +</tr> 1.273 + 1.274 +<tr valign="top" class="whs15"> 1.275 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.276 +<p class=Table>Use EBRs for Register File</td> 1.277 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 1.278 +<p class=Table>Uses embedded block RAMS for the register file.</td></tr> 1.279 + 1.280 +<tr valign="top" class="whs15"> 1.281 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.282 +<p class=Table>Enable Divide</td> 1.283 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 1.284 +<p class=Table>Enables the divide and modulus instructions (<span style="font-family: Verdana, sans-serif;">divu, 1.285 + modu</span>).</td></tr> 1.286 + 1.287 +<tr valign="top" class="whs15"> 1.288 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.289 +<p class=Table>Enable Sign Extend</td> 1.290 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 1.291 +<p class=Table>Enables the sign-extension instructions (<span style="font-family: Verdana, sans-serif;">sextb, 1.292 + sexth</span><span style="font-family: Arial, sans-serif;">)</span>.</td></tr> 1.293 + 1.294 +<tr valign="top" class="whs15"> 1.295 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.296 +<p class=Table>Location of Exception Handlers</td> 1.297 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 1.298 +<p class=Table>Specifies the default value for the vector table. This can 1.299 + be changed by updating the EBA control register or status register.</p> 1.300 +<p class=Table>This address must be aligned to a 256-byte boundary, since 1.301 + the hardware ignores the least-significant byte. Unpredictable behavior 1.302 + occurs when the exception base address and the exception vectors are not 1.303 + aligned on a 256-byte boundary.</td></tr> 1.304 + 1.305 +<tr valign="top" class="whs15"> 1.306 +<td colspan="2" rowspan="1" width="691px" class="whs20"> 1.307 +<p class=Table 1.308 + style="font-weight: bold;">Multiplier Settings</td> 1.309 +</tr> 1.310 + 1.311 +<tr valign="top" class="whs15"> 1.312 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.313 +<p class=Table>Enable Multiplier</td> 1.314 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 1.315 +<p class=Table>Enables the multiply instructions (<span style="font-family: Verdana, sans-serif;">mul, 1.316 + muli)</span>.</td></tr> 1.317 + 1.318 +<tr valign="top" class="whs15"> 1.319 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.320 +<p class=Table>Enable Pipelined Multiplier (DSP Block if available)</td> 1.321 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 1.322 +<p class=Table>Enables the multiplier using the DSP block, if available.</td></tr> 1.323 + 1.324 +<tr valign="top" class="whs15"> 1.325 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.326 +<p class=Table>Enable Multicycle (LUT-based, 32 cycles) Multiplier</td> 1.327 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 1.328 +<p class=Table>Enables the multiplier using LUTs.</td></tr> 1.329 + 1.330 +<tr valign="top" class="whs15"> 1.331 +<td colspan="2" rowspan="1" width="691px" class="whs20"> 1.332 +<p class=Table 1.333 + style="font-weight: bold;">Instruction Cache</td> 1.334 +</tr> 1.335 + 1.336 +<tr valign="top" class="whs15"> 1.337 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.338 +<p class=Table>Instruction Cache Enabled</td> 1.339 +<td colspan="1" rowspan="1" width="524px" class="whs19"> 1.340 +<p class=Table 1.341 + style="margin-left: 14px;">Determines whether an instruction cache 1.342 + is implemented.</td></tr> 1.343 + 1.344 +<tr valign="top" class="whs15"> 1.345 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.346 +<p class=Table>Number of Sets</td> 1.347 +<td colspan="1" rowspan="1" width="524px" class="whs19"> 1.348 +<p class=Table 1.349 + style="margin-left: 14px;">Specifies the number of sets in the instruction 1.350 + cache. Supported values are 128, 256, 512, 1024.</td></tr> 1.351 + 1.352 +<tr valign="top" class="whs15"> 1.353 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.354 +<p class=Table>Set Associativity</td> 1.355 +<td colspan="1" rowspan="1" width="524px" class="whs19"> 1.356 +<p class=Table 1.357 + style="margin-left: 14px;">Specifies the associativity of the instruction 1.358 + cache. Supported values are 1, 2.</td></tr> 1.359 + 1.360 +<tr valign="top" class="whs15"> 1.361 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.362 +<p class=Table>Bytes/Cache Line</td> 1.363 +<td colspan="1" rowspan="1" width="524px" class="whs19"> 1.364 +<p class=Table 1.365 + style="margin-left: 15px;">Specifies the number of bytes per instruction 1.366 + cache line. Supported values are 4, 8, 16.</td></tr> 1.367 + 1.368 +<tr valign="top" class="whs15"> 1.369 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.370 +<p class=Table>Memory Type</td> 1.371 +<td colspan="1" rowspan="1" width="524px" class="whs19"> 1.372 +<p class=Table 1.373 + style="margin-left: 15px;">Determines the FPGA resource to be used 1.374 + to implement the instruction cache. The decision can be left to the synthesis 1.375 + tool (Auto), or you can select from the following options:</p> 1.376 +<ul type="disc" class="whs22"> 1.377 + 1.378 + <li class=kadov-p-CBullet><p class=Bullet>Auto – 1.379 + Leaves the implementation of the instruction cache to the synthesis tool.</p></li> 1.380 + 1.381 + <li class=kadov-p-CBullet><p class=Bullet>Distributed RAM – 1.382 + Implements the instruction cache as distributed RAM.</p></li> 1.383 + 1.384 + <li class=kadov-p-CBullet><p class=Bullet>Dual-Port EBR – 1.385 + Implements the instruction cache as dual-port EBR (two read/write ports).</p></li> 1.386 + 1.387 + <li class=kadov-p-CBullet><p class=Bullet>Pseudo Dual-Port EBR – Implements 1.388 + the instruction cache as pseudo-dual-port EBR (one read port and one write 1.389 + port). </p></li> 1.390 +</ul></td></tr> 1.391 + 1.392 +<tr valign="top" class="whs15"> 1.393 +<td colspan="2" rowspan="1" width="691px" class="whs20"> 1.394 +<p class=Table 1.395 + style="font-weight: bold;">Debug Setting</td> 1.396 +</tr> 1.397 + 1.398 +<tr valign="top" class="whs15"> 1.399 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.400 +<p class=Table>Enable Debug Interface</td> 1.401 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 1.402 +<p class=Table>Includes the debugger stub in the CPU, which is required 1.403 + for debugging.</td></tr> 1.404 + 1.405 +<tr valign="top" class="whs15"> 1.406 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.407 +<p class=Table># of H/W Watchpoint Registers</td> 1.408 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 1.409 +<p class=Table 1.410 + style="font-weight: normal;">Specifies the number of hardware watchpoint 1.411 + registers to be used in the debugging process.</td></tr> 1.412 + 1.413 +<tr valign="top" class="whs15"> 1.414 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.415 +<p class=Table>Enable Debugging Code in Flash or ROM</td> 1.416 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 1.417 +<p class=Table 1.418 + style="font-weight: normal;">Enables you to set hardware breakpoints 1.419 + in read-only memory.</td></tr> 1.420 + 1.421 +<tr valign="top" class="whs15"> 1.422 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.423 +<p class=Table># of H/W Breakpoint Registers</td> 1.424 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 1.425 +<p class=Table>Specifies the number of hardware breakpoint registers to 1.426 + be used in the debugging process.</td></tr> 1.427 + 1.428 +<tr valign="top" class="whs15"> 1.429 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.430 +<p class=Table>Enable PC Trace</td> 1.431 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 1.432 +<p class=Table>Enables the Program Counter Trace feature, which enables 1.433 + you to run the program trace during debug to find items in your C or C++ 1.434 + Code during debug, such as breakpoints and exceptions. Refer to <span 1.435 + style="font-weight: bold;"><B>Help > Help Contents > C/C++ SPE</B></span> 1.436 + and <span style="font-weight: bold;"><B>Debug > Concepts > Program 1.437 + Counter Trace</B></span> for more information on Program Counter Trace.</td></tr> 1.438 + 1.439 +<tr valign="top" class="whs15"> 1.440 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.441 +<p class=Table>Trace Depth</td> 1.442 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 1.443 +<p class=Table>Enables you to specify the depth of the Program Counter 1.444 + Trace buffer. Refer to <span style="font-weight: bold;"><B>Help > Help 1.445 + Contents > C/C++ SPE</B></span> and <span style="font-weight: bold;"><B>Debug 1.446 + > Concepts > Program Counter Trace</B></span> for more information on 1.447 + Program Counter Trace.</td></tr> 1.448 + 1.449 +<tr valign="top" class="whs15"> 1.450 +<td colspan="2" rowspan="1" width="691px" class="whs20"> 1.451 +<p class=Table 1.452 + style="font-weight: bold;">Shifter Settings</td> 1.453 +</tr> 1.454 + 1.455 +<tr valign="top" class="whs15"> 1.456 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.457 +<p class=Table>Enable Piplined Barrel Shifter</td> 1.458 +<td colspan="1" rowspan="1" width="524px" class="whs19"> 1.459 +<p>Enables the barrel shifter to be pipelined. The barrel shifter is implemented 1.460 + to perform a shift operation in three cycles.</td></tr> 1.461 + 1.462 +<tr valign="top" class="whs15"> 1.463 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.464 +<p class=Table>Enable Multicycle Barrel Shifter (up to 32 cycles)</td> 1.465 +<td colspan="1" rowspan="1" width="524px" class="whs19"> 1.466 +<p>Enables multi-cycle shift operation for the barrel shifter. The barrel 1.467 + shifter is implemented to shift one bit per cycle and take thirty-two 1.468 + cycles to complete.</td></tr> 1.469 + 1.470 +<tr valign="top" class="whs15"> 1.471 +<td colspan="2" rowspan="1" width="691px" class="whs20"> 1.472 +<p class=Table><span style="font-weight: bold;"><B>Data Cache</B></span></td> 1.473 +</tr> 1.474 + 1.475 +<tr valign="top" class="whs15"> 1.476 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.477 +<p class=Table>Data Cache Enabled</td> 1.478 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 1.479 +<p class=Table>Determines whether a data cache is implemented.</td></tr> 1.480 + 1.481 +<tr valign="top" class="whs15"> 1.482 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.483 +<p class=Table>Number of Sets</td> 1.484 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 1.485 +<p class=Table>Specifies the number of sets in the data cache. Supported 1.486 + values are 128, 256, 512, 1024.</td></tr> 1.487 + 1.488 +<tr valign="top" class="whs15"> 1.489 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.490 +<p class=Table>Set Associativity</td> 1.491 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 1.492 +<p class=Table>Specifies the associativity of the data cache. Supported 1.493 + values are 1, 2.</td></tr> 1.494 + 1.495 +<tr valign="top" class="whs15"> 1.496 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.497 +<p class=Table>Bytes/Cache Line</td> 1.498 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 1.499 +<p class=Table>Specifies the number of bytes per data cache line. Supported 1.500 + values are 4, 8, 16.</td></tr> 1.501 + 1.502 +<tr valign="top" class="whs15"> 1.503 +<td colspan="1" rowspan="1" width="167px" class="whs23"> 1.504 +<p class=Table>Memory Type</td> 1.505 +<td colspan="1" rowspan="1" width="524px" class="whs24"> 1.506 +<p class=Table>Determines the FPGA resource to be used to implement the 1.507 + data cache. The decision can be left to the synthesis tool (Auto), or 1.508 + you can select from the following options:</p> 1.509 +<ul> 1.510 + 1.511 + <li class=kadov-p-CBullet><p class=Bullet>Auto – 1.512 + Leaves the implementation of the data cache to the synthesis tool.</p></li> 1.513 + 1.514 + <li class=kadov-p-CBullet><p class=Bullet>Distributed RAM – 1.515 + Implements the data cache as distributed RAM.</p></li> 1.516 + 1.517 + <li class=kadov-p-CBullet><p class=Bullet>Dual-Port EBR – 1.518 + Implements the data cache as dual-port EBR (two read/write ports).</p></li> 1.519 +</ul></td></tr> 1.520 +</table> 1.521 + 1.522 +<p> </p> 1.523 + 1.524 +<h2>Dialog Box Parameters – 1.525 + Inline Memory Tab</h2> 1.526 + 1.527 +<table x-use-null-cells cellspacing="0" class="whs12"> 1.528 +<col class="whs13"> 1.529 +<col class="whs14"> 1.530 + 1.531 +<tr valign="top" class="whs15"> 1.532 +<td bgcolor="#DEE8F4" width="167px" class="whs25"> 1.533 +<p class=Table 1.534 + style="font-weight: bold;">Parameter</td> 1.535 +<td bgcolor="#DEE8F4" width="524px" class="whs26"> 1.536 +<p class=Table 1.537 + style="font-weight: bold;">Description</td></tr> 1.538 + 1.539 +<tr valign="top" class="whs15"> 1.540 +<td rowspan="1" colspan="2" width="691px" class="whs27"> 1.541 +<p class=Table 1.542 + style="font-weight: bold;">Instruction Inline Memory</td> 1.543 +</tr> 1.544 + 1.545 +<tr valign="top" class="whs15"> 1.546 +<td width="167px" class="whs28"> 1.547 +<p class=Table>Enable</td> 1.548 +<td width="524px" class="whs29"> 1.549 +<p class=Table>Enables the instruction inline memory</td></tr> 1.550 + 1.551 +<tr valign="top" class="whs15"> 1.552 +<td width="167px" class="whs28"> 1.553 +<p class=Table>Instance Name</td> 1.554 +<td width="524px" class="whs29"> 1.555 +<p class=Table>Specifics the name of the instruction inline memory. Alphanumeric 1.556 + values and underscores are supported. The default is Instruction_IM.</td></tr> 1.557 + 1.558 +<tr valign="top" class="whs15"> 1.559 +<td width="167px" class="whs28"> 1.560 +<p class=Table>Base Address</td> 1.561 +<td width="524px" class="whs29"> 1.562 +<p class=Table>Specifies the base address for the instruction inline memory. 1.563 + The default is 0x10000000.</td></tr> 1.564 + 1.565 +<tr valign="top" class="whs15"> 1.566 +<td width="167px" class="whs28"> 1.567 +<p class=Table>Size of Memory in Bytes</td> 1.568 +<td width="524px" class="whs29"> 1.569 +<p class=Table>Specifies the size of the instruction inline memory.</td></tr> 1.570 + 1.571 +<tr valign="top" class="whs15"> 1.572 +<td rowspan="1" colspan="2" width="691px" class="whs27"> 1.573 +<p class=Table><span style="font-weight: bold;"><B>Memory File</B></span></td> 1.574 +</tr> 1.575 + 1.576 +<tr valign="top" class="whs15"> 1.577 +<td width="167px" class="whs28"> 1.578 +<p class=Table>Initialization File Name</td> 1.579 +<td width="524px" class="whs29"> 1.580 +<p class=Table>Specifies the name of the memory initialization file for 1.581 + instruction inline memory.</td></tr> 1.582 + 1.583 +<tr valign="top" class="whs15"> 1.584 +<td width="167px" class="whs28"> 1.585 +<p class=Table>File Format</td> 1.586 +<td width="524px" class="whs29"> 1.587 +<p class=Table>Specifies the format of the memory initialization file: 1.588 + hex or binary.</td></tr> 1.589 + 1.590 +<tr valign="top" class="whs15"> 1.591 +<td rowspan="1" colspan="2" width="691px" class="whs27"> 1.592 +<p class=Table 1.593 + style="font-weight: bold;">Data Inline Memory</td> 1.594 +</tr> 1.595 + 1.596 +<tr valign="top" class="whs15"> 1.597 +<td width="167px" class="whs28"> 1.598 +<p class=Table>Enabled</td> 1.599 +<td width="524px" class="whs29"> 1.600 +<p class=Table>Enables the data inline memory.</td></tr> 1.601 + 1.602 +<tr valign="top" class="whs15"> 1.603 +<td width="167px" class="whs28"> 1.604 +<p class=Table>Instance Name</td> 1.605 +<td width="524px" class="whs29"> 1.606 +<p class=Table>Specifies the name of the data inline memory. Alphanumeric 1.607 + values and underscores are supported. The default is Data_IM.</td></tr> 1.608 + 1.609 +<tr valign="top" class="whs15"> 1.610 +<td width="167px" class="whs28"> 1.611 +<p class=Table>Base Address</td> 1.612 +<td width="524px" class="whs29"> 1.613 +<p class=Table>Specifies the base address for the data inline memory. The 1.614 + default is 0x20000000.</td></tr> 1.615 + 1.616 +<tr valign="top" class="whs15"> 1.617 +<td width="167px" class="whs28"> 1.618 +<p class=Table>Size of Memory in Bytes</td> 1.619 +<td width="524px" class="whs29"> 1.620 +<p class=Table>Specifies the size of the data inline memory.</td></tr> 1.621 + 1.622 +<tr valign="top" class="whs15"> 1.623 +<td colspan="2" rowspan="1" width="691px" class="whs27"> 1.624 +<p class=Table 1.625 + style="font-weight: bold;">Memory File</td> 1.626 +</tr> 1.627 + 1.628 +<tr valign="top" class="whs15"> 1.629 +<td colspan="1" rowspan="1" width="167px" class="whs28"> 1.630 +<p class=Table>Initialization File Name</td> 1.631 +<td colspan="1" rowspan="1" width="524px" class="whs29"> 1.632 +<p class=Table>Specifies the name of the memory initialization file for 1.633 + data inline memory.</td></tr> 1.634 + 1.635 +<tr valign="top" class="whs15"> 1.636 +<td colspan="1" rowspan="1" width="167px" class="whs30"> 1.637 +<p class=Table>File Format</td> 1.638 +<td colspan="1" rowspan="1" width="524px" class="whs31"> 1.639 +<p class=Table>Specifies the format of the memory initialization file: 1.640 + hex or binary.</td></tr> 1.641 +</table> 1.642 + 1.643 +<p> </p> 1.644 + 1.645 +<p>For the revision history of the component RTL files, refer to the header 1.646 + of each component Verilog source file. </p> 1.647 + 1.648 +<p><span style="font-weight: bold;"><B>Note</B></span>: If the processor manual 1.649 + fails to open, click <img src="qm_icon.jpg" x-maintain-ratio="TRUE" width="14px" height="16px" border="0" class="img_whs32"> on the Available Components toolbar, 1.650 + and then click the note button.</p> 1.651 + 1.652 +<script type="text/javascript" language="JavaScript"> 1.653 +<!-- 1.654 + if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) 1.655 + document.write("<div id='tooltip' class='WebHelpPopupMenu'></div>"); 1.656 +//--> 1.657 +</script><script type="text/javascript" language="javascript1.2"> 1.658 +<!-- 1.659 +if (window.writeIntopicBar) 1.660 + writeIntopicBar(0); 1.661 +//--> 1.662 +</script> 1.663 +</body> 1.664 +</html>