1.1 diff -r 252df75c8f67 -r c336e674a37e doc/lm32.htm 1.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 1.3 +++ b/doc/lm32.htm Tue Mar 08 09:40:42 2011 +0000 1.4 @@ -0,0 +1,661 @@ 1.5 +<!doctype HTML public "-//W3C//DTD HTML 4.0 Frameset//EN"> 1.6 + 1.7 +<html> 1.8 + 1.9 +<head> 1.10 +<title>LatticeMico32 processor</title> 1.11 +<meta http-equiv="content-type" content="text/html; charset=windows-1252"> 1.12 +<meta name="generator" content="RoboHelp by eHelp Corporation www.ehelp.com"> 1.13 +<link rel="stylesheet" href="lever40_ns.css"><script type="text/javascript" language="JavaScript" title="WebHelpSplitCss"> 1.14 +<!-- 1.15 +if (navigator.appName !="Netscape") 1.16 +{ document.write("<link rel='stylesheet' href='lever40.css'>");} 1.17 +//--> 1.18 +</script> 1.19 +<style> 1.20 +<!-- 1.21 +body { border-left-style:None; border-right-style:None; border-top-style:None; border-bottom-style:None; } 1.22 +--> 1.23 +</style><style type="text/css"> 1.24 +<!-- 1.25 +img_whs1 { border:none; width:29px; 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1.108 + 1.109 + } 1.110 + 1.111 + 1.112 + if (window.setRelStartPage) 1.113 + { 1.114 + setRelStartPage("msb_peripherals.htm"); 1.115 + 1.116 + autoSync(0); 1.117 + sendSyncInfo(); 1.118 + sendAveInfoOut(); 1.119 + } 1.120 + 1.121 +} 1.122 +else 1.123 + if (window.gbIE4) 1.124 + document.location.reload(); 1.125 +//--> 1.126 +</script> 1.127 +</head> 1.128 +<body><script type="text/javascript" language="javascript1.2"> 1.129 +<!-- 1.130 +if (window.writeIntopicBar) 1.131 + writeIntopicBar(4); 1.132 +//--> 1.133 +</script> 1.134 +<h1>LatticeMico32 Processor <a title="View Reference Manual" href="lm32_archman.pdf" target="_blank" onmouseover="if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) ehlp_showtip(this,event,'View Reference Manual');" onmouseout="if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) ehlp_hidetip();"><img src="ds_icon_ast.jpg" x-maintain-ratio="TRUE" width="29px" height="31px" border="0" class="img_whs1"></a></h1> 1.135 + 1.136 +<p>The LatticeMico32 processor is a high-performance 32-bit microprocessor 1.137 + optimized for Lattice Semiconductor field-programmable gate arrays. </p> 1.138 + 1.139 +<p class="whs2"><span style="font-style: italic;"><I>*If the 1.140 + processor manual fails to open, see the note at the bottom of this page.</I></span></p> 1.141 + 1.142 +<h2>Revision History</h2> 1.143 + 1.144 +<table x-use-null-cells cellspacing="0" width="738" height="84" class="whs3"> 1.145 +<script language='JavaScript'><!-- 1.146 +if ((navigator.appName == "Netscape") && (parseInt(navigator.appVersion) == 4)) document.write("</table><table x-use-null-cells cellspacing='0' width='738' height='84' border='1' bordercolor='silver' bordercolorlight='silver' bordercolordark='silver'>"); 1.147 +//--></script> 1.148 +<col class="whs4"> 1.149 +<col class="whs5"> 1.150 + 1.151 +<tr valign="top" class="whs6"> 1.152 +<td bgcolor="#DEE8F4" width="93px" class="whs7"> 1.153 +<p class=Table 1.154 + style="font-weight: bold;">Version</td> 1.155 +<td bgcolor="#DEE8F4" width="598px" class="whs8"> 1.156 +<p class=Table 1.157 + style="font-weight: bold;">Description</td></tr> 1.158 + 1.159 +<tr valign="top" class="whs6"> 1.160 +<td colspan="1" rowspan="1" width="93px" class="whs9"> 1.161 +<p class=Table 1.162 + style="font-weight: normal;">3.6</td> 1.163 +<td colspan="1" rowspan="1" width="598px" class="whs10"> 1.164 +<p class=whs10 1.165 + style="margin-left: 0px;">Fixed the issue of the processor locking 1.166 + up when Instruction Cache is not used.</td></tr> 1.167 + 1.168 +<tr valign="top" class="whs6"> 1.169 +<td colspan="1" rowspan="1" width="93px" class="whs9"> 1.170 +<p class=Table 1.171 + style="font-weight: normal;">3.5</td> 1.172 +<td colspan="1" rowspan="1" width="598px" class="whs10"> 1.173 +<p class=whs10 1.174 + style="margin-left: 0px;">Support added to allow Inline Memories to 1.175 + be generated as non-power-of-two, as long as they are a multiple of 1024 1.176 + bytes</td></tr> 1.177 + 1.178 +<tr valign="top" class="whs6"> 1.179 +<td colspan="1" rowspan="1" width="93px" class="whs9"> 1.180 +<p class=Table 1.181 + style="font-weight: normal;">3.4</td> 1.182 +<td colspan="1" rowspan="1" width="598px" class="whs10"> 1.183 +<p class=whs10 1.184 + style="margin-left: 0px;">Updated to support ispLEVER 7.2 SP1.</td></tr> 1.185 + 1.186 +<tr valign="top" class="whs6"> 1.187 +<td colspan="1" rowspan="1" width="93px" class="whs9"> 1.188 +<p class=Table 1.189 + style="font-weight: normal;">3.3</td> 1.190 +<td colspan="1" rowspan="1" width="598px" class="whs10"> 1.191 +<p class=whs10 1.192 + style="margin-left: 0px;">Updated to support ispLEVER 7.2.</p> 1.193 +<p class=whs10 1.194 + style="margin-left: 0px;">Added Inline Memory to support on-chip memory 1.195 + connected through a local bus.</td></tr> 1.196 + 1.197 +<tr valign="top" class="whs6"> 1.198 +<td colspan="1" rowspan="1" width="93px" class="whs9"> 1.199 +<p class=Table 1.200 + style="font-weight: normal;">3.2</td> 1.201 +<td colspan="1" rowspan="1" width="598px" class="whs10"> 1.202 +<p class=whs10 1.203 + style="margin-left: 0px;">Updated to support ispLEVER 7.1 SP1</p> 1.204 +<p class=whs10 1.205 + style="margin-left: 0px;">Added Memory Type to instruction cache and 1.206 + data cache.</td></tr> 1.207 + 1.208 +<tr valign="top" class="whs6"> 1.209 +<td colspan="1" rowspan="1" width="93px" class="whs9"> 1.210 +<p class=Table 1.211 + style="font-weight: normal;">3.1</td> 1.212 +<td colspan="1" rowspan="1" width="598px" class="whs10"> 1.213 +<p class="whs11">Updated to support ispLEVER 7.1.</p> 1.214 +<p class="whs11">Added static predictor to improve the behavior 1.215 + of branches.</p> 1.216 +<p class="whs11">Added support for optionally mapping the register 1.217 + file to EBRs (on-chip memory).</p> 1.218 +<p class="whs11">Added support for selecting between distributed 1.219 + RAM and EBRs (pseudo-dual port or true-dual port) for instruction and 1.220 + data caches.</td></tr> 1.221 + 1.222 +<tr valign="top" class="whs6"> 1.223 +<td colspan="1" rowspan="1" width="93px" class="whs9"> 1.224 +<p class=Table 1.225 + style="font-weight: normal;"><span style="font-weight: normal;">3.0 1.226 + (7.0 SP2)</span></td> 1.227 +<td colspan="1" rowspan="1" width="598px" class="whs10"> 1.228 +<p class="whs11">Updated to support ispLEVER 7.0 SP2.</p> 1.229 +<p class="whs11">Fixed incorrect handling of data cache miss 1.230 + in the presence of an instruction cache miss.</td></tr> 1.231 + 1.232 +<tr valign="top" class="whs6"> 1.233 +<td colspan="1" rowspan="1" width="93px" class="whs9"> 1.234 +<p class="whs11">1.0</td> 1.235 +<td colspan="1" rowspan="1" width="598px" class="whs10"> 1.236 +<p class="whs11">Initial version.</td></tr> 1.237 +<script language='JavaScript'><!-- 1.238 +if ((navigator.appName == "Netscape") && (parseInt(navigator.appVersion) == 4)) document.write("</table></table><table>"); 1.239 +//--></script> 1.240 +</table> 1.241 + 1.242 + 1.243 + 1.244 +<h2>Dialog Box Parameters – 1.245 + General Tab</h2> 1.246 + 1.247 +<table x-use-null-cells cellspacing="0" class="whs12"> 1.248 +<col class="whs13"> 1.249 +<col class="whs14"> 1.250 + 1.251 +<tr valign="top" class="whs15"> 1.252 +<td bgcolor="#DEE8F4" width="167px" class="whs16"> 1.253 +<p class=Table 1.254 + style="font-weight: bold;">Parameter</td> 1.255 +<td bgcolor="#DEE8F4" width="524px" class="whs17"> 1.256 +<p class=Table 1.257 + style="font-weight: bold;">Description</td></tr> 1.258 + 1.259 +<tr valign="top" class="whs15"> 1.260 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.261 +<p class=Table 1.262 + style="font-weight: normal;">Instance Name</td> 1.263 +<td colspan="1" rowspan="1" width="524px" class="whs19"> 1.264 +<p class=Table 1.265 + style="margin-left: 14px;">Specifies the name of the LatticeMico32 1.266 + processor. Alphanumeric values and underscores are supported. The default 1.267 + is LM32.</td></tr> 1.268 + 1.269 +<tr valign="top" class="whs15"> 1.270 +<td colspan="2" rowspan="1" width="691px" class="whs20"> 1.271 +<p class=Table 1.272 + style="font-weight: bold;">Settings</td> 1.273 +</tr> 1.274 + 1.275 +<tr valign="top" class="whs15"> 1.276 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.277 +<p class=Table>Use EBRs for Register File</td> 1.278 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 1.279 +<p class=Table>Uses embedded block RAMS for the register file.</td></tr> 1.280 + 1.281 +<tr valign="top" class="whs15"> 1.282 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.283 +<p class=Table>Enable Divide</td> 1.284 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 1.285 +<p class=Table>Enables the divide and modulus instructions (<span style="font-family: Verdana, sans-serif;">divu, 1.286 + modu</span>).</td></tr> 1.287 + 1.288 +<tr valign="top" class="whs15"> 1.289 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.290 +<p class=Table>Enable Sign Extend</td> 1.291 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 1.292 +<p class=Table>Enables the sign-extension instructions (<span style="font-family: Verdana, sans-serif;">sextb, 1.293 + sexth</span><span style="font-family: Arial, sans-serif;">)</span>.</td></tr> 1.294 + 1.295 +<tr valign="top" class="whs15"> 1.296 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.297 +<p class=Table>Location of Exception Handlers</td> 1.298 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 1.299 +<p class=Table>Specifies the default value for the vector table. This can 1.300 + be changed by updating the EBA control register or status register.</p> 1.301 +<p class=Table>This address must be aligned to a 256-byte boundary, since 1.302 + the hardware ignores the least-significant byte. Unpredictable behavior 1.303 + occurs when the exception base address and the exception vectors are not 1.304 + aligned on a 256-byte boundary.</td></tr> 1.305 + 1.306 +<tr valign="top" class="whs15"> 1.307 +<td colspan="2" rowspan="1" width="691px" class="whs20"> 1.308 +<p class=Table 1.309 + style="font-weight: bold;">Multiplier Settings</td> 1.310 +</tr> 1.311 + 1.312 +<tr valign="top" class="whs15"> 1.313 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.314 +<p class=Table>Enable Multiplier</td> 1.315 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 1.316 +<p class=Table>Enables the multiply instructions (<span style="font-family: Verdana, sans-serif;">mul, 1.317 + muli)</span>.</td></tr> 1.318 + 1.319 +<tr valign="top" class="whs15"> 1.320 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.321 +<p class=Table>Enable Pipelined Multiplier (DSP Block if available)</td> 1.322 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 1.323 +<p class=Table>Enables the multiplier using the DSP block, if available.</td></tr> 1.324 + 1.325 +<tr valign="top" class="whs15"> 1.326 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.327 +<p class=Table>Enable Multicycle (LUT-based, 32 cycles) Multiplier</td> 1.328 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 1.329 +<p class=Table>Enables the multiplier using LUTs.</td></tr> 1.330 + 1.331 +<tr valign="top" class="whs15"> 1.332 +<td colspan="2" rowspan="1" width="691px" class="whs20"> 1.333 +<p class=Table 1.334 + style="font-weight: bold;">Instruction Cache</td> 1.335 +</tr> 1.336 + 1.337 +<tr valign="top" class="whs15"> 1.338 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.339 +<p class=Table>Instruction Cache Enabled</td> 1.340 +<td colspan="1" rowspan="1" width="524px" class="whs19"> 1.341 +<p class=Table 1.342 + style="margin-left: 14px;">Determines whether an instruction cache 1.343 + is implemented.</td></tr> 1.344 + 1.345 +<tr valign="top" class="whs15"> 1.346 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.347 +<p class=Table>Number of Sets</td> 1.348 +<td colspan="1" rowspan="1" width="524px" class="whs19"> 1.349 +<p class=Table 1.350 + style="margin-left: 14px;">Specifies the number of sets in the instruction 1.351 + cache. Supported values are 128, 256, 512, 1024.</td></tr> 1.352 + 1.353 +<tr valign="top" class="whs15"> 1.354 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.355 +<p class=Table>Set Associativity</td> 1.356 +<td colspan="1" rowspan="1" width="524px" class="whs19"> 1.357 +<p class=Table 1.358 + style="margin-left: 14px;">Specifies the associativity of the instruction 1.359 + cache. Supported values are 1, 2.</td></tr> 1.360 + 1.361 +<tr valign="top" class="whs15"> 1.362 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.363 +<p class=Table>Bytes/Cache Line</td> 1.364 +<td colspan="1" rowspan="1" width="524px" class="whs19"> 1.365 +<p class=Table 1.366 + style="margin-left: 15px;">Specifies the number of bytes per instruction 1.367 + cache line. Supported values are 4, 8, 16.</td></tr> 1.368 + 1.369 +<tr valign="top" class="whs15"> 1.370 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.371 +<p class=Table>Memory Type</td> 1.372 +<td colspan="1" rowspan="1" width="524px" class="whs19"> 1.373 +<p class=Table 1.374 + style="margin-left: 15px;">Determines the FPGA resource to be used 1.375 + to implement the instruction cache. The decision can be left to the synthesis 1.376 + tool (Auto), or you can select from the following options:</p> 1.377 +<ul type="disc" class="whs22"> 1.378 + 1.379 + <li class=kadov-p-CBullet><p class=Bullet>Auto – 1.380 + Leaves the implementation of the instruction cache to the synthesis tool.</p></li> 1.381 + 1.382 + <li class=kadov-p-CBullet><p class=Bullet>Distributed RAM – 1.383 + Implements the instruction cache as distributed RAM.</p></li> 1.384 + 1.385 + <li class=kadov-p-CBullet><p class=Bullet>Dual-Port EBR – 1.386 + Implements the instruction cache as dual-port EBR (two read/write ports).</p></li> 1.387 + 1.388 + <li class=kadov-p-CBullet><p class=Bullet>Pseudo Dual-Port EBR – Implements 1.389 + the instruction cache as pseudo-dual-port EBR (one read port and one write 1.390 + port). </p></li> 1.391 +</ul></td></tr> 1.392 + 1.393 +<tr valign="top" class="whs15"> 1.394 +<td colspan="2" rowspan="1" width="691px" class="whs20"> 1.395 +<p class=Table 1.396 + style="font-weight: bold;">Debug Setting</td> 1.397 +</tr> 1.398 + 1.399 +<tr valign="top" class="whs15"> 1.400 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.401 +<p class=Table>Enable Debug Interface</td> 1.402 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 1.403 +<p class=Table>Includes the debugger stub in the CPU, which is required 1.404 + for debugging.</td></tr> 1.405 + 1.406 +<tr valign="top" class="whs15"> 1.407 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.408 +<p class=Table># of H/W Watchpoint Registers</td> 1.409 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 1.410 +<p class=Table 1.411 + style="font-weight: normal;">Specifies the number of hardware watchpoint 1.412 + registers to be used in the debugging process.</td></tr> 1.413 + 1.414 +<tr valign="top" class="whs15"> 1.415 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.416 +<p class=Table>Enable Debugging Code in Flash or ROM</td> 1.417 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 1.418 +<p class=Table 1.419 + style="font-weight: normal;">Enables you to set hardware breakpoints 1.420 + in read-only memory.</td></tr> 1.421 + 1.422 +<tr valign="top" class="whs15"> 1.423 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.424 +<p class=Table># of H/W Breakpoint Registers</td> 1.425 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 1.426 +<p class=Table>Specifies the number of hardware breakpoint registers to 1.427 + be used in the debugging process.</td></tr> 1.428 + 1.429 +<tr valign="top" class="whs15"> 1.430 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.431 +<p class=Table>Enable PC Trace</td> 1.432 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 1.433 +<p class=Table>Enables the Program Counter Trace feature, which enables 1.434 + you to run the program trace during debug to find items in your C or C++ 1.435 + Code during debug, such as breakpoints and exceptions. Refer to <span 1.436 + style="font-weight: bold;"><B>Help > Help Contents > C/C++ SPE</B></span> 1.437 + and <span style="font-weight: bold;"><B>Debug > Concepts > Program 1.438 + Counter Trace</B></span> for more information on Program Counter Trace.</td></tr> 1.439 + 1.440 +<tr valign="top" class="whs15"> 1.441 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.442 +<p class=Table>Trace Depth</td> 1.443 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 1.444 +<p class=Table>Enables you to specify the depth of the Program Counter 1.445 + Trace buffer. Refer to <span style="font-weight: bold;"><B>Help > Help 1.446 + Contents > C/C++ SPE</B></span> and <span style="font-weight: bold;"><B>Debug 1.447 + > Concepts > Program Counter Trace</B></span> for more information on 1.448 + Program Counter Trace.</td></tr> 1.449 + 1.450 +<tr valign="top" class="whs15"> 1.451 +<td colspan="2" rowspan="1" width="691px" class="whs20"> 1.452 +<p class=Table 1.453 + style="font-weight: bold;">Shifter Settings</td> 1.454 +</tr> 1.455 + 1.456 +<tr valign="top" class="whs15"> 1.457 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.458 +<p class=Table>Enable Piplined Barrel Shifter</td> 1.459 +<td colspan="1" rowspan="1" width="524px" class="whs19"> 1.460 +<p>Enables the barrel shifter to be pipelined. The barrel shifter is implemented 1.461 + to perform a shift operation in three cycles.</td></tr> 1.462 + 1.463 +<tr valign="top" class="whs15"> 1.464 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.465 +<p class=Table>Enable Multicycle Barrel Shifter (up to 32 cycles)</td> 1.466 +<td colspan="1" rowspan="1" width="524px" class="whs19"> 1.467 +<p>Enables multi-cycle shift operation for the barrel shifter. The barrel 1.468 + shifter is implemented to shift one bit per cycle and take thirty-two 1.469 + cycles to complete.</td></tr> 1.470 + 1.471 +<tr valign="top" class="whs15"> 1.472 +<td colspan="2" rowspan="1" width="691px" class="whs20"> 1.473 +<p class=Table><span style="font-weight: bold;"><B>Data Cache</B></span></td> 1.474 +</tr> 1.475 + 1.476 +<tr valign="top" class="whs15"> 1.477 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.478 +<p class=Table>Data Cache Enabled</td> 1.479 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 1.480 +<p class=Table>Determines whether a data cache is implemented.</td></tr> 1.481 + 1.482 +<tr valign="top" class="whs15"> 1.483 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.484 +<p class=Table>Number of Sets</td> 1.485 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 1.486 +<p class=Table>Specifies the number of sets in the data cache. Supported 1.487 + values are 128, 256, 512, 1024.</td></tr> 1.488 + 1.489 +<tr valign="top" class="whs15"> 1.490 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.491 +<p class=Table>Set Associativity</td> 1.492 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 1.493 +<p class=Table>Specifies the associativity of the data cache. Supported 1.494 + values are 1, 2.</td></tr> 1.495 + 1.496 +<tr valign="top" class="whs15"> 1.497 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 1.498 +<p class=Table>Bytes/Cache Line</td> 1.499 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 1.500 +<p class=Table>Specifies the number of bytes per data cache line. Supported 1.501 + values are 4, 8, 16.</td></tr> 1.502 + 1.503 +<tr valign="top" class="whs15"> 1.504 +<td colspan="1" rowspan="1" width="167px" class="whs23"> 1.505 +<p class=Table>Memory Type</td> 1.506 +<td colspan="1" rowspan="1" width="524px" class="whs24"> 1.507 +<p class=Table>Determines the FPGA resource to be used to implement the 1.508 + data cache. The decision can be left to the synthesis tool (Auto), or 1.509 + you can select from the following options:</p> 1.510 +<ul> 1.511 + 1.512 + <li class=kadov-p-CBullet><p class=Bullet>Auto – 1.513 + Leaves the implementation of the data cache to the synthesis tool.</p></li> 1.514 + 1.515 + <li class=kadov-p-CBullet><p class=Bullet>Distributed RAM – 1.516 + Implements the data cache as distributed RAM.</p></li> 1.517 + 1.518 + <li class=kadov-p-CBullet><p class=Bullet>Dual-Port EBR – 1.519 + Implements the data cache as dual-port EBR (two read/write ports).</p></li> 1.520 +</ul></td></tr> 1.521 +</table> 1.522 + 1.523 +<p> </p> 1.524 + 1.525 +<h2>Dialog Box Parameters – 1.526 + Inline Memory Tab</h2> 1.527 + 1.528 +<table x-use-null-cells cellspacing="0" class="whs12"> 1.529 +<col class="whs13"> 1.530 +<col class="whs14"> 1.531 + 1.532 +<tr valign="top" class="whs15"> 1.533 +<td bgcolor="#DEE8F4" width="167px" class="whs25"> 1.534 +<p class=Table 1.535 + style="font-weight: bold;">Parameter</td> 1.536 +<td bgcolor="#DEE8F4" width="524px" class="whs26"> 1.537 +<p class=Table 1.538 + style="font-weight: bold;">Description</td></tr> 1.539 + 1.540 +<tr valign="top" class="whs15"> 1.541 +<td rowspan="1" colspan="2" width="691px" class="whs27"> 1.542 +<p class=Table 1.543 + style="font-weight: bold;">Instruction Inline Memory</td> 1.544 +</tr> 1.545 + 1.546 +<tr valign="top" class="whs15"> 1.547 +<td width="167px" class="whs28"> 1.548 +<p class=Table>Enable</td> 1.549 +<td width="524px" class="whs29"> 1.550 +<p class=Table>Enables the instruction inline memory</td></tr> 1.551 + 1.552 +<tr valign="top" class="whs15"> 1.553 +<td width="167px" class="whs28"> 1.554 +<p class=Table>Instance Name</td> 1.555 +<td width="524px" class="whs29"> 1.556 +<p class=Table>Specifics the name of the instruction inline memory. Alphanumeric 1.557 + values and underscores are supported. The default is Instruction_IM.</td></tr> 1.558 + 1.559 +<tr valign="top" class="whs15"> 1.560 +<td width="167px" class="whs28"> 1.561 +<p class=Table>Base Address</td> 1.562 +<td width="524px" class="whs29"> 1.563 +<p class=Table>Specifies the base address for the instruction inline memory. 1.564 + The default is 0x10000000.</td></tr> 1.565 + 1.566 +<tr valign="top" class="whs15"> 1.567 +<td width="167px" class="whs28"> 1.568 +<p class=Table>Size of Memory in Bytes</td> 1.569 +<td width="524px" class="whs29"> 1.570 +<p class=Table>Specifies the size of the instruction inline memory.</td></tr> 1.571 + 1.572 +<tr valign="top" class="whs15"> 1.573 +<td rowspan="1" colspan="2" width="691px" class="whs27"> 1.574 +<p class=Table><span style="font-weight: bold;"><B>Memory File</B></span></td> 1.575 +</tr> 1.576 + 1.577 +<tr valign="top" class="whs15"> 1.578 +<td width="167px" class="whs28"> 1.579 +<p class=Table>Initialization File Name</td> 1.580 +<td width="524px" class="whs29"> 1.581 +<p class=Table>Specifies the name of the memory initialization file for 1.582 + instruction inline memory.</td></tr> 1.583 + 1.584 +<tr valign="top" class="whs15"> 1.585 +<td width="167px" class="whs28"> 1.586 +<p class=Table>File Format</td> 1.587 +<td width="524px" class="whs29"> 1.588 +<p class=Table>Specifies the format of the memory initialization file: 1.589 + hex or binary.</td></tr> 1.590 + 1.591 +<tr valign="top" class="whs15"> 1.592 +<td rowspan="1" colspan="2" width="691px" class="whs27"> 1.593 +<p class=Table 1.594 + style="font-weight: bold;">Data Inline Memory</td> 1.595 +</tr> 1.596 + 1.597 +<tr valign="top" class="whs15"> 1.598 +<td width="167px" class="whs28"> 1.599 +<p class=Table>Enabled</td> 1.600 +<td width="524px" class="whs29"> 1.601 +<p class=Table>Enables the data inline memory.</td></tr> 1.602 + 1.603 +<tr valign="top" class="whs15"> 1.604 +<td width="167px" class="whs28"> 1.605 +<p class=Table>Instance Name</td> 1.606 +<td width="524px" class="whs29"> 1.607 +<p class=Table>Specifies the name of the data inline memory. Alphanumeric 1.608 + values and underscores are supported. The default is Data_IM.</td></tr> 1.609 + 1.610 +<tr valign="top" class="whs15"> 1.611 +<td width="167px" class="whs28"> 1.612 +<p class=Table>Base Address</td> 1.613 +<td width="524px" class="whs29"> 1.614 +<p class=Table>Specifies the base address for the data inline memory. The 1.615 + default is 0x20000000.</td></tr> 1.616 + 1.617 +<tr valign="top" class="whs15"> 1.618 +<td width="167px" class="whs28"> 1.619 +<p class=Table>Size of Memory in Bytes</td> 1.620 +<td width="524px" class="whs29"> 1.621 +<p class=Table>Specifies the size of the data inline memory.</td></tr> 1.622 + 1.623 +<tr valign="top" class="whs15"> 1.624 +<td colspan="2" rowspan="1" width="691px" class="whs27"> 1.625 +<p class=Table 1.626 + style="font-weight: bold;">Memory File</td> 1.627 +</tr> 1.628 + 1.629 +<tr valign="top" class="whs15"> 1.630 +<td colspan="1" rowspan="1" width="167px" class="whs28"> 1.631 +<p class=Table>Initialization File Name</td> 1.632 +<td colspan="1" rowspan="1" width="524px" class="whs29"> 1.633 +<p class=Table>Specifies the name of the memory initialization file for 1.634 + data inline memory.</td></tr> 1.635 + 1.636 +<tr valign="top" class="whs15"> 1.637 +<td colspan="1" rowspan="1" width="167px" class="whs30"> 1.638 +<p class=Table>File Format</td> 1.639 +<td colspan="1" rowspan="1" width="524px" class="whs31"> 1.640 +<p class=Table>Specifies the format of the memory initialization file: 1.641 + hex or binary.</td></tr> 1.642 +</table> 1.643 + 1.644 +<p> </p> 1.645 + 1.646 +<p>For the revision history of the component RTL files, refer to the header 1.647 + of each component Verilog source file. </p> 1.648 + 1.649 +<p><span style="font-weight: bold;"><B>Note</B></span>: If the processor manual 1.650 + fails to open, click <img src="qm_icon.jpg" x-maintain-ratio="TRUE" width="14px" height="16px" border="0" class="img_whs32"> on the Available Components toolbar, 1.651 + and then click the note button.</p> 1.652 + 1.653 +<script type="text/javascript" language="JavaScript"> 1.654 +<!-- 1.655 + if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) 1.656 + document.write("<div id='tooltip' class='WebHelpPopupMenu'></div>"); 1.657 +//--> 1.658 +</script><script type="text/javascript" language="javascript1.2"> 1.659 +<!-- 1.660 +if (window.writeIntopicBar) 1.661 + writeIntopicBar(0); 1.662 +//--> 1.663 +</script> 1.664 +</body> 1.665 +</html>