Tue, 08 Mar 2011 09:40:42 +0000
Fix project layout to follow standards
1.1 diff -r 252df75c8f67 -r c336e674a37e doc/ds_icon.jpg 1.2 Binary file doc/ds_icon.jpg has changed
2.1 diff -r 252df75c8f67 -r c336e674a37e doc/ds_icon_ast.jpg 2.2 Binary file doc/ds_icon_ast.jpg has changed
3.1 diff -r 252df75c8f67 -r c336e674a37e doc/dsb_icon.jpg 3.2 Binary file doc/dsb_icon.jpg has changed
4.1 diff -r 252df75c8f67 -r c336e674a37e doc/lever40.css 4.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 4.3 +++ b/doc/lever40.css Tue Mar 08 09:40:42 2011 +0000 4.4 @@ -0,0 +1,245 @@ 4.5 +H1 { 4.6 + font-weight:bold; 4.7 + border-top-style:none; 4.8 + font-family:Arial, helvetica, sans-serif; 4.9 + color:#ea6d23; 4.10 + margin-left:15px; 4.11 + margin-top:3px; 4.12 + margin-bottom:10px; 4.13 + border-bottom-style:Solid; 4.14 + border-bottom-width:2px; 4.15 + border-bottom-color:#dbdbdb; 4.16 + margin-right:0px; 4.17 + line-height:Normal; 4.18 + font-size:1em; } 4.19 +LI.kadov-H1 { 4.20 + font-weight:bold; 4.21 + font-family:Arial, helvetica, sans-serif; 4.22 + color:#ea6d23; 4.23 + line-height:Normal; 4.24 + font-size:1em; } 4.25 +H2 { 4.26 + font-weight:bold; 4.27 + x-text-underline:Off; 4.28 + border-top-style:none; 4.29 + border-bottom-style:none; 4.30 + font-family:Arial, helvetica, sans-serif; 4.31 + color:#ea6d23; 4.32 + margin-left:15px; 4.33 + margin-top:12px; 4.34 + margin-bottom:5px; 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5.1 diff -r 252df75c8f67 -r c336e674a37e doc/lever40_ns.css 5.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 5.3 +++ b/doc/lever40_ns.css Tue Mar 08 09:40:42 2011 +0000 5.4 @@ -0,0 +1,248 @@ 5.5 +H1 { 5.6 + font-weight:bold; 5.7 + border-top-style:none; 5.8 + font-family:Arial, helvetica, sans-serif; 5.9 + color:#ea6d23; 5.10 + margin-left:15px; 5.11 + margin-top:3px; 5.12 + margin-bottom:10px; 5.13 + border-bottom-style:Solid; 5.14 + border-bottom-width:2px; 5.15 + border-bottom-color:#dbdbdb; 5.16 + margin-right:1pt; 5.17 + line-height:Normal; 5.18 + font-size:1em; } 5.19 +LI.kadov-H1 { 5.20 + font-weight:bold; 5.21 + font-family:Arial, helvetica, sans-serif; 5.22 + color:#ea6d23; 5.23 + line-height:Normal; 5.24 + font-size:1em; } 5.25 +H2 { 5.26 + font-weight:bold; 5.27 + x-text-underline:Off; 5.28 + border-top-style:none; 5.29 + border-bottom-style:none; 5.30 + font-family:Arial, helvetica, sans-serif; 5.31 + color:#ea6d23; 5.32 + margin-left:15px; 5.33 + margin-top:12px; 5.34 + margin-bottom:5px; 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6.1 diff -r 252df75c8f67 -r c336e674a37e doc/lm32.htm 6.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 6.3 +++ b/doc/lm32.htm Tue Mar 08 09:40:42 2011 +0000 6.4 @@ -0,0 +1,661 @@ 6.5 +<!doctype HTML public "-//W3C//DTD HTML 4.0 Frameset//EN"> 6.6 + 6.7 +<html> 6.8 + 6.9 +<head> 6.10 +<title>LatticeMico32 processor</title> 6.11 +<meta http-equiv="content-type" content="text/html; charset=windows-1252"> 6.12 +<meta name="generator" content="RoboHelp by eHelp Corporation www.ehelp.com"> 6.13 +<link rel="stylesheet" href="lever40_ns.css"><script type="text/javascript" language="JavaScript" title="WebHelpSplitCss"> 6.14 +<!-- 6.15 +if (navigator.appName !="Netscape") 6.16 +{ document.write("<link rel='stylesheet' href='lever40.css'>");} 6.17 +//--> 6.18 +</script> 6.19 +<style> 6.20 +<!-- 6.21 +body { border-left-style:None; border-right-style:None; border-top-style:None; border-bottom-style:None; } 6.22 +--> 6.23 +</style><style type="text/css"> 6.24 +<!-- 6.25 +img_whs1 { border:none; width:29px; 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padding-left:10px; border-bottom-color:#c0c0c0; border-bottom-style:Solid; border-bottom-width:1px; border-right-color:#c0c0c0; border-right-width:1px; border-right-style:Solid; } 6.56 +img_whs32 { border:none; width:14px; height:16px; float:none; border-style:none; } 6.57 +--> 6.58 +</style><script type="text/javascript" language="JavaScript"> 6.59 +<!-- 6.60 +function ehlp_showtip(current,e,text) 6.61 +{ 6.62 + if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) 6.63 + { 6.64 + document.tooltip.document.write("<layer bgColor='yellow' style='border:1px solid black;font-size:12px;'>"+ text + "</layer>"); 6.65 + document.tooltip.document.close(); 6.66 + document.tooltip.left=e.pageX+5; 6.67 + document.tooltip.top=e.pageY+5; 6.68 + document.tooltip.visibility="show"; 6.69 + } 6.70 +} 6.71 +function ehlp_hidetip() 6.72 +{ 6.73 + document.tooltip.visibility="hidden"; 6.74 +} 6.75 +//--> 6.76 +</script> 6.77 +<script type="text/javascript" language="JavaScript" title="WebHelpInlineScript"> 6.78 +<!-- 6.79 +function reDo() { 6.80 + if (innerWidth != origWidth || innerHeight != origHeight) 6.81 + location.reload(); 6.82 +} 6.83 +if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == "Netscape")) { 6.84 + origWidth = innerWidth; 6.85 + origHeight = innerHeight; 6.86 + onresize = reDo; 6.87 +} 6.88 +onerror = null; 6.89 +//--> 6.90 +</script> 6.91 +<style type="text/css"> 6.92 +<!-- 6.93 +div.WebHelpPopupMenu { position:absolute; left:0px; top:0px; z-index:4; visibility:hidden; } 6.94 +p.WebHelpNavBar { text-align:right; } 6.95 +--> 6.96 +</style><script type="text/javascript" language="javascript1.2" src="whmsg.js"></script> 6.97 +<script type="text/javascript" language="javascript" src="whver.js"></script> 6.98 +<script type="text/javascript" language="javascript1.2" src="whproxy.js"></script> 6.99 +<script type="text/javascript" language="javascript1.2" src="whutils.js"></script> 6.100 +<script type="text/javascript" language="javascript1.2" src="whtopic.js"></script> 6.101 +<script type="text/javascript" language="javascript1.2"> 6.102 +<!-- 6.103 +if (window.gbWhTopic) 6.104 +{ 6.105 + if (window.setRelStartPage) 6.106 + { 6.107 + addTocInfo("LM32"); 6.108 + 6.109 + } 6.110 + 6.111 + 6.112 + if (window.setRelStartPage) 6.113 + { 6.114 + setRelStartPage("msb_peripherals.htm"); 6.115 + 6.116 + autoSync(0); 6.117 + sendSyncInfo(); 6.118 + sendAveInfoOut(); 6.119 + } 6.120 + 6.121 +} 6.122 +else 6.123 + if (window.gbIE4) 6.124 + document.location.reload(); 6.125 +//--> 6.126 +</script> 6.127 +</head> 6.128 +<body><script type="text/javascript" language="javascript1.2"> 6.129 +<!-- 6.130 +if (window.writeIntopicBar) 6.131 + writeIntopicBar(4); 6.132 +//--> 6.133 +</script> 6.134 +<h1>LatticeMico32 Processor <a title="View Reference Manual" href="lm32_archman.pdf" target="_blank" onmouseover="if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) ehlp_showtip(this,event,'View Reference Manual');" onmouseout="if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) ehlp_hidetip();"><img src="ds_icon_ast.jpg" x-maintain-ratio="TRUE" width="29px" height="31px" border="0" class="img_whs1"></a></h1> 6.135 + 6.136 +<p>The LatticeMico32 processor is a high-performance 32-bit microprocessor 6.137 + optimized for Lattice Semiconductor field-programmable gate arrays. </p> 6.138 + 6.139 +<p class="whs2"><span style="font-style: italic;"><I>*If the 6.140 + processor manual fails to open, see the note at the bottom of this page.</I></span></p> 6.141 + 6.142 +<h2>Revision History</h2> 6.143 + 6.144 +<table x-use-null-cells cellspacing="0" width="738" height="84" class="whs3"> 6.145 +<script language='JavaScript'><!-- 6.146 +if ((navigator.appName == "Netscape") && (parseInt(navigator.appVersion) == 4)) document.write("</table><table x-use-null-cells cellspacing='0' width='738' height='84' border='1' bordercolor='silver' bordercolorlight='silver' bordercolordark='silver'>"); 6.147 +//--></script> 6.148 +<col class="whs4"> 6.149 +<col class="whs5"> 6.150 + 6.151 +<tr valign="top" class="whs6"> 6.152 +<td bgcolor="#DEE8F4" width="93px" class="whs7"> 6.153 +<p class=Table 6.154 + style="font-weight: bold;">Version</td> 6.155 +<td bgcolor="#DEE8F4" width="598px" class="whs8"> 6.156 +<p class=Table 6.157 + style="font-weight: bold;">Description</td></tr> 6.158 + 6.159 +<tr valign="top" class="whs6"> 6.160 +<td colspan="1" rowspan="1" width="93px" class="whs9"> 6.161 +<p class=Table 6.162 + style="font-weight: normal;">3.6</td> 6.163 +<td colspan="1" rowspan="1" width="598px" class="whs10"> 6.164 +<p class=whs10 6.165 + style="margin-left: 0px;">Fixed the issue of the processor locking 6.166 + up when Instruction Cache is not used.</td></tr> 6.167 + 6.168 +<tr valign="top" class="whs6"> 6.169 +<td colspan="1" rowspan="1" width="93px" class="whs9"> 6.170 +<p class=Table 6.171 + style="font-weight: normal;">3.5</td> 6.172 +<td colspan="1" rowspan="1" width="598px" class="whs10"> 6.173 +<p class=whs10 6.174 + style="margin-left: 0px;">Support added to allow Inline Memories to 6.175 + be generated as non-power-of-two, as long as they are a multiple of 1024 6.176 + bytes</td></tr> 6.177 + 6.178 +<tr valign="top" class="whs6"> 6.179 +<td colspan="1" rowspan="1" width="93px" class="whs9"> 6.180 +<p class=Table 6.181 + style="font-weight: normal;">3.4</td> 6.182 +<td colspan="1" rowspan="1" width="598px" class="whs10"> 6.183 +<p class=whs10 6.184 + style="margin-left: 0px;">Updated to support ispLEVER 7.2 SP1.</td></tr> 6.185 + 6.186 +<tr valign="top" class="whs6"> 6.187 +<td colspan="1" rowspan="1" width="93px" class="whs9"> 6.188 +<p class=Table 6.189 + style="font-weight: normal;">3.3</td> 6.190 +<td colspan="1" rowspan="1" width="598px" class="whs10"> 6.191 +<p class=whs10 6.192 + style="margin-left: 0px;">Updated to support ispLEVER 7.2.</p> 6.193 +<p class=whs10 6.194 + style="margin-left: 0px;">Added Inline Memory to support on-chip memory 6.195 + connected through a local bus.</td></tr> 6.196 + 6.197 +<tr valign="top" class="whs6"> 6.198 +<td colspan="1" rowspan="1" width="93px" class="whs9"> 6.199 +<p class=Table 6.200 + style="font-weight: normal;">3.2</td> 6.201 +<td colspan="1" rowspan="1" width="598px" class="whs10"> 6.202 +<p class=whs10 6.203 + style="margin-left: 0px;">Updated to support ispLEVER 7.1 SP1</p> 6.204 +<p class=whs10 6.205 + style="margin-left: 0px;">Added Memory Type to instruction cache and 6.206 + data cache.</td></tr> 6.207 + 6.208 +<tr valign="top" class="whs6"> 6.209 +<td colspan="1" rowspan="1" width="93px" class="whs9"> 6.210 +<p class=Table 6.211 + style="font-weight: normal;">3.1</td> 6.212 +<td colspan="1" rowspan="1" width="598px" class="whs10"> 6.213 +<p class="whs11">Updated to support ispLEVER 7.1.</p> 6.214 +<p class="whs11">Added static predictor to improve the behavior 6.215 + of branches.</p> 6.216 +<p class="whs11">Added support for optionally mapping the register 6.217 + file to EBRs (on-chip memory).</p> 6.218 +<p class="whs11">Added support for selecting between distributed 6.219 + RAM and EBRs (pseudo-dual port or true-dual port) for instruction and 6.220 + data caches.</td></tr> 6.221 + 6.222 +<tr valign="top" class="whs6"> 6.223 +<td colspan="1" rowspan="1" width="93px" class="whs9"> 6.224 +<p class=Table 6.225 + style="font-weight: normal;"><span style="font-weight: normal;">3.0 6.226 + (7.0 SP2)</span></td> 6.227 +<td colspan="1" rowspan="1" width="598px" class="whs10"> 6.228 +<p class="whs11">Updated to support ispLEVER 7.0 SP2.</p> 6.229 +<p class="whs11">Fixed incorrect handling of data cache miss 6.230 + in the presence of an instruction cache miss.</td></tr> 6.231 + 6.232 +<tr valign="top" class="whs6"> 6.233 +<td colspan="1" rowspan="1" width="93px" class="whs9"> 6.234 +<p class="whs11">1.0</td> 6.235 +<td colspan="1" rowspan="1" width="598px" class="whs10"> 6.236 +<p class="whs11">Initial version.</td></tr> 6.237 +<script language='JavaScript'><!-- 6.238 +if ((navigator.appName == "Netscape") && (parseInt(navigator.appVersion) == 4)) document.write("</table></table><table>"); 6.239 +//--></script> 6.240 +</table> 6.241 + 6.242 + 6.243 + 6.244 +<h2>Dialog Box Parameters – 6.245 + General Tab</h2> 6.246 + 6.247 +<table x-use-null-cells cellspacing="0" class="whs12"> 6.248 +<col class="whs13"> 6.249 +<col class="whs14"> 6.250 + 6.251 +<tr valign="top" class="whs15"> 6.252 +<td bgcolor="#DEE8F4" width="167px" class="whs16"> 6.253 +<p class=Table 6.254 + style="font-weight: bold;">Parameter</td> 6.255 +<td bgcolor="#DEE8F4" width="524px" class="whs17"> 6.256 +<p class=Table 6.257 + style="font-weight: bold;">Description</td></tr> 6.258 + 6.259 +<tr valign="top" class="whs15"> 6.260 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 6.261 +<p class=Table 6.262 + style="font-weight: normal;">Instance Name</td> 6.263 +<td colspan="1" rowspan="1" width="524px" class="whs19"> 6.264 +<p class=Table 6.265 + style="margin-left: 14px;">Specifies the name of the LatticeMico32 6.266 + processor. Alphanumeric values and underscores are supported. The default 6.267 + is LM32.</td></tr> 6.268 + 6.269 +<tr valign="top" class="whs15"> 6.270 +<td colspan="2" rowspan="1" width="691px" class="whs20"> 6.271 +<p class=Table 6.272 + style="font-weight: bold;">Settings</td> 6.273 +</tr> 6.274 + 6.275 +<tr valign="top" class="whs15"> 6.276 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 6.277 +<p class=Table>Use EBRs for Register File</td> 6.278 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 6.279 +<p class=Table>Uses embedded block RAMS for the register file.</td></tr> 6.280 + 6.281 +<tr valign="top" class="whs15"> 6.282 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 6.283 +<p class=Table>Enable Divide</td> 6.284 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 6.285 +<p class=Table>Enables the divide and modulus instructions (<span style="font-family: Verdana, sans-serif;">divu, 6.286 + modu</span>).</td></tr> 6.287 + 6.288 +<tr valign="top" class="whs15"> 6.289 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 6.290 +<p class=Table>Enable Sign Extend</td> 6.291 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 6.292 +<p class=Table>Enables the sign-extension instructions (<span style="font-family: Verdana, sans-serif;">sextb, 6.293 + sexth</span><span style="font-family: Arial, sans-serif;">)</span>.</td></tr> 6.294 + 6.295 +<tr valign="top" class="whs15"> 6.296 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 6.297 +<p class=Table>Location of Exception Handlers</td> 6.298 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 6.299 +<p class=Table>Specifies the default value for the vector table. This can 6.300 + be changed by updating the EBA control register or status register.</p> 6.301 +<p class=Table>This address must be aligned to a 256-byte boundary, since 6.302 + the hardware ignores the least-significant byte. Unpredictable behavior 6.303 + occurs when the exception base address and the exception vectors are not 6.304 + aligned on a 256-byte boundary.</td></tr> 6.305 + 6.306 +<tr valign="top" class="whs15"> 6.307 +<td colspan="2" rowspan="1" width="691px" class="whs20"> 6.308 +<p class=Table 6.309 + style="font-weight: bold;">Multiplier Settings</td> 6.310 +</tr> 6.311 + 6.312 +<tr valign="top" class="whs15"> 6.313 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 6.314 +<p class=Table>Enable Multiplier</td> 6.315 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 6.316 +<p class=Table>Enables the multiply instructions (<span style="font-family: Verdana, sans-serif;">mul, 6.317 + muli)</span>.</td></tr> 6.318 + 6.319 +<tr valign="top" class="whs15"> 6.320 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 6.321 +<p class=Table>Enable Pipelined Multiplier (DSP Block if available)</td> 6.322 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 6.323 +<p class=Table>Enables the multiplier using the DSP block, if available.</td></tr> 6.324 + 6.325 +<tr valign="top" class="whs15"> 6.326 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 6.327 +<p class=Table>Enable Multicycle (LUT-based, 32 cycles) Multiplier</td> 6.328 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 6.329 +<p class=Table>Enables the multiplier using LUTs.</td></tr> 6.330 + 6.331 +<tr valign="top" class="whs15"> 6.332 +<td colspan="2" rowspan="1" width="691px" class="whs20"> 6.333 +<p class=Table 6.334 + style="font-weight: bold;">Instruction Cache</td> 6.335 +</tr> 6.336 + 6.337 +<tr valign="top" class="whs15"> 6.338 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 6.339 +<p class=Table>Instruction Cache Enabled</td> 6.340 +<td colspan="1" rowspan="1" width="524px" class="whs19"> 6.341 +<p class=Table 6.342 + style="margin-left: 14px;">Determines whether an instruction cache 6.343 + is implemented.</td></tr> 6.344 + 6.345 +<tr valign="top" class="whs15"> 6.346 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 6.347 +<p class=Table>Number of Sets</td> 6.348 +<td colspan="1" rowspan="1" width="524px" class="whs19"> 6.349 +<p class=Table 6.350 + style="margin-left: 14px;">Specifies the number of sets in the instruction 6.351 + cache. Supported values are 128, 256, 512, 1024.</td></tr> 6.352 + 6.353 +<tr valign="top" class="whs15"> 6.354 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 6.355 +<p class=Table>Set Associativity</td> 6.356 +<td colspan="1" rowspan="1" width="524px" class="whs19"> 6.357 +<p class=Table 6.358 + style="margin-left: 14px;">Specifies the associativity of the instruction 6.359 + cache. Supported values are 1, 2.</td></tr> 6.360 + 6.361 +<tr valign="top" class="whs15"> 6.362 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 6.363 +<p class=Table>Bytes/Cache Line</td> 6.364 +<td colspan="1" rowspan="1" width="524px" class="whs19"> 6.365 +<p class=Table 6.366 + style="margin-left: 15px;">Specifies the number of bytes per instruction 6.367 + cache line. Supported values are 4, 8, 16.</td></tr> 6.368 + 6.369 +<tr valign="top" class="whs15"> 6.370 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 6.371 +<p class=Table>Memory Type</td> 6.372 +<td colspan="1" rowspan="1" width="524px" class="whs19"> 6.373 +<p class=Table 6.374 + style="margin-left: 15px;">Determines the FPGA resource to be used 6.375 + to implement the instruction cache. The decision can be left to the synthesis 6.376 + tool (Auto), or you can select from the following options:</p> 6.377 +<ul type="disc" class="whs22"> 6.378 + 6.379 + <li class=kadov-p-CBullet><p class=Bullet>Auto – 6.380 + Leaves the implementation of the instruction cache to the synthesis tool.</p></li> 6.381 + 6.382 + <li class=kadov-p-CBullet><p class=Bullet>Distributed RAM – 6.383 + Implements the instruction cache as distributed RAM.</p></li> 6.384 + 6.385 + <li class=kadov-p-CBullet><p class=Bullet>Dual-Port EBR – 6.386 + Implements the instruction cache as dual-port EBR (two read/write ports).</p></li> 6.387 + 6.388 + <li class=kadov-p-CBullet><p class=Bullet>Pseudo Dual-Port EBR – Implements 6.389 + the instruction cache as pseudo-dual-port EBR (one read port and one write 6.390 + port). </p></li> 6.391 +</ul></td></tr> 6.392 + 6.393 +<tr valign="top" class="whs15"> 6.394 +<td colspan="2" rowspan="1" width="691px" class="whs20"> 6.395 +<p class=Table 6.396 + style="font-weight: bold;">Debug Setting</td> 6.397 +</tr> 6.398 + 6.399 +<tr valign="top" class="whs15"> 6.400 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 6.401 +<p class=Table>Enable Debug Interface</td> 6.402 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 6.403 +<p class=Table>Includes the debugger stub in the CPU, which is required 6.404 + for debugging.</td></tr> 6.405 + 6.406 +<tr valign="top" class="whs15"> 6.407 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 6.408 +<p class=Table># of H/W Watchpoint Registers</td> 6.409 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 6.410 +<p class=Table 6.411 + style="font-weight: normal;">Specifies the number of hardware watchpoint 6.412 + registers to be used in the debugging process.</td></tr> 6.413 + 6.414 +<tr valign="top" class="whs15"> 6.415 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 6.416 +<p class=Table>Enable Debugging Code in Flash or ROM</td> 6.417 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 6.418 +<p class=Table 6.419 + style="font-weight: normal;">Enables you to set hardware breakpoints 6.420 + in read-only memory.</td></tr> 6.421 + 6.422 +<tr valign="top" class="whs15"> 6.423 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 6.424 +<p class=Table># of H/W Breakpoint Registers</td> 6.425 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 6.426 +<p class=Table>Specifies the number of hardware breakpoint registers to 6.427 + be used in the debugging process.</td></tr> 6.428 + 6.429 +<tr valign="top" class="whs15"> 6.430 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 6.431 +<p class=Table>Enable PC Trace</td> 6.432 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 6.433 +<p class=Table>Enables the Program Counter Trace feature, which enables 6.434 + you to run the program trace during debug to find items in your C or C++ 6.435 + Code during debug, such as breakpoints and exceptions. Refer to <span 6.436 + style="font-weight: bold;"><B>Help > Help Contents > C/C++ SPE</B></span> 6.437 + and <span style="font-weight: bold;"><B>Debug > Concepts > Program 6.438 + Counter Trace</B></span> for more information on Program Counter Trace.</td></tr> 6.439 + 6.440 +<tr valign="top" class="whs15"> 6.441 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 6.442 +<p class=Table>Trace Depth</td> 6.443 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 6.444 +<p class=Table>Enables you to specify the depth of the Program Counter 6.445 + Trace buffer. Refer to <span style="font-weight: bold;"><B>Help > Help 6.446 + Contents > C/C++ SPE</B></span> and <span style="font-weight: bold;"><B>Debug 6.447 + > Concepts > Program Counter Trace</B></span> for more information on 6.448 + Program Counter Trace.</td></tr> 6.449 + 6.450 +<tr valign="top" class="whs15"> 6.451 +<td colspan="2" rowspan="1" width="691px" class="whs20"> 6.452 +<p class=Table 6.453 + style="font-weight: bold;">Shifter Settings</td> 6.454 +</tr> 6.455 + 6.456 +<tr valign="top" class="whs15"> 6.457 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 6.458 +<p class=Table>Enable Piplined Barrel Shifter</td> 6.459 +<td colspan="1" rowspan="1" width="524px" class="whs19"> 6.460 +<p>Enables the barrel shifter to be pipelined. The barrel shifter is implemented 6.461 + to perform a shift operation in three cycles.</td></tr> 6.462 + 6.463 +<tr valign="top" class="whs15"> 6.464 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 6.465 +<p class=Table>Enable Multicycle Barrel Shifter (up to 32 cycles)</td> 6.466 +<td colspan="1" rowspan="1" width="524px" class="whs19"> 6.467 +<p>Enables multi-cycle shift operation for the barrel shifter. The barrel 6.468 + shifter is implemented to shift one bit per cycle and take thirty-two 6.469 + cycles to complete.</td></tr> 6.470 + 6.471 +<tr valign="top" class="whs15"> 6.472 +<td colspan="2" rowspan="1" width="691px" class="whs20"> 6.473 +<p class=Table><span style="font-weight: bold;"><B>Data Cache</B></span></td> 6.474 +</tr> 6.475 + 6.476 +<tr valign="top" class="whs15"> 6.477 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 6.478 +<p class=Table>Data Cache Enabled</td> 6.479 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 6.480 +<p class=Table>Determines whether a data cache is implemented.</td></tr> 6.481 + 6.482 +<tr valign="top" class="whs15"> 6.483 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 6.484 +<p class=Table>Number of Sets</td> 6.485 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 6.486 +<p class=Table>Specifies the number of sets in the data cache. Supported 6.487 + values are 128, 256, 512, 1024.</td></tr> 6.488 + 6.489 +<tr valign="top" class="whs15"> 6.490 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 6.491 +<p class=Table>Set Associativity</td> 6.492 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 6.493 +<p class=Table>Specifies the associativity of the data cache. Supported 6.494 + values are 1, 2.</td></tr> 6.495 + 6.496 +<tr valign="top" class="whs15"> 6.497 +<td colspan="1" rowspan="1" width="167px" class="whs18"> 6.498 +<p class=Table>Bytes/Cache Line</td> 6.499 +<td colspan="1" rowspan="1" width="524px" class="whs21"> 6.500 +<p class=Table>Specifies the number of bytes per data cache line. Supported 6.501 + values are 4, 8, 16.</td></tr> 6.502 + 6.503 +<tr valign="top" class="whs15"> 6.504 +<td colspan="1" rowspan="1" width="167px" class="whs23"> 6.505 +<p class=Table>Memory Type</td> 6.506 +<td colspan="1" rowspan="1" width="524px" class="whs24"> 6.507 +<p class=Table>Determines the FPGA resource to be used to implement the 6.508 + data cache. The decision can be left to the synthesis tool (Auto), or 6.509 + you can select from the following options:</p> 6.510 +<ul> 6.511 + 6.512 + <li class=kadov-p-CBullet><p class=Bullet>Auto – 6.513 + Leaves the implementation of the data cache to the synthesis tool.</p></li> 6.514 + 6.515 + <li class=kadov-p-CBullet><p class=Bullet>Distributed RAM – 6.516 + Implements the data cache as distributed RAM.</p></li> 6.517 + 6.518 + <li class=kadov-p-CBullet><p class=Bullet>Dual-Port EBR – 6.519 + Implements the data cache as dual-port EBR (two read/write ports).</p></li> 6.520 +</ul></td></tr> 6.521 +</table> 6.522 + 6.523 +<p> </p> 6.524 + 6.525 +<h2>Dialog Box Parameters – 6.526 + Inline Memory Tab</h2> 6.527 + 6.528 +<table x-use-null-cells cellspacing="0" class="whs12"> 6.529 +<col class="whs13"> 6.530 +<col class="whs14"> 6.531 + 6.532 +<tr valign="top" class="whs15"> 6.533 +<td bgcolor="#DEE8F4" width="167px" class="whs25"> 6.534 +<p class=Table 6.535 + style="font-weight: bold;">Parameter</td> 6.536 +<td bgcolor="#DEE8F4" width="524px" class="whs26"> 6.537 +<p class=Table 6.538 + style="font-weight: bold;">Description</td></tr> 6.539 + 6.540 +<tr valign="top" class="whs15"> 6.541 +<td rowspan="1" colspan="2" width="691px" class="whs27"> 6.542 +<p class=Table 6.543 + style="font-weight: bold;">Instruction Inline Memory</td> 6.544 +</tr> 6.545 + 6.546 +<tr valign="top" class="whs15"> 6.547 +<td width="167px" class="whs28"> 6.548 +<p class=Table>Enable</td> 6.549 +<td width="524px" class="whs29"> 6.550 +<p class=Table>Enables the instruction inline memory</td></tr> 6.551 + 6.552 +<tr valign="top" class="whs15"> 6.553 +<td width="167px" class="whs28"> 6.554 +<p class=Table>Instance Name</td> 6.555 +<td width="524px" class="whs29"> 6.556 +<p class=Table>Specifics the name of the instruction inline memory. Alphanumeric 6.557 + values and underscores are supported. The default is Instruction_IM.</td></tr> 6.558 + 6.559 +<tr valign="top" class="whs15"> 6.560 +<td width="167px" class="whs28"> 6.561 +<p class=Table>Base Address</td> 6.562 +<td width="524px" class="whs29"> 6.563 +<p class=Table>Specifies the base address for the instruction inline memory. 6.564 + The default is 0x10000000.</td></tr> 6.565 + 6.566 +<tr valign="top" class="whs15"> 6.567 +<td width="167px" class="whs28"> 6.568 +<p class=Table>Size of Memory in Bytes</td> 6.569 +<td width="524px" class="whs29"> 6.570 +<p class=Table>Specifies the size of the instruction inline memory.</td></tr> 6.571 + 6.572 +<tr valign="top" class="whs15"> 6.573 +<td rowspan="1" colspan="2" width="691px" class="whs27"> 6.574 +<p class=Table><span style="font-weight: bold;"><B>Memory File</B></span></td> 6.575 +</tr> 6.576 + 6.577 +<tr valign="top" class="whs15"> 6.578 +<td width="167px" class="whs28"> 6.579 +<p class=Table>Initialization File Name</td> 6.580 +<td width="524px" class="whs29"> 6.581 +<p class=Table>Specifies the name of the memory initialization file for 6.582 + instruction inline memory.</td></tr> 6.583 + 6.584 +<tr valign="top" class="whs15"> 6.585 +<td width="167px" class="whs28"> 6.586 +<p class=Table>File Format</td> 6.587 +<td width="524px" class="whs29"> 6.588 +<p class=Table>Specifies the format of the memory initialization file: 6.589 + hex or binary.</td></tr> 6.590 + 6.591 +<tr valign="top" class="whs15"> 6.592 +<td rowspan="1" colspan="2" width="691px" class="whs27"> 6.593 +<p class=Table 6.594 + style="font-weight: bold;">Data Inline Memory</td> 6.595 +</tr> 6.596 + 6.597 +<tr valign="top" class="whs15"> 6.598 +<td width="167px" class="whs28"> 6.599 +<p class=Table>Enabled</td> 6.600 +<td width="524px" class="whs29"> 6.601 +<p class=Table>Enables the data inline memory.</td></tr> 6.602 + 6.603 +<tr valign="top" class="whs15"> 6.604 +<td width="167px" class="whs28"> 6.605 +<p class=Table>Instance Name</td> 6.606 +<td width="524px" class="whs29"> 6.607 +<p class=Table>Specifies the name of the data inline memory. Alphanumeric 6.608 + values and underscores are supported. The default is Data_IM.</td></tr> 6.609 + 6.610 +<tr valign="top" class="whs15"> 6.611 +<td width="167px" class="whs28"> 6.612 +<p class=Table>Base Address</td> 6.613 +<td width="524px" class="whs29"> 6.614 +<p class=Table>Specifies the base address for the data inline memory. The 6.615 + default is 0x20000000.</td></tr> 6.616 + 6.617 +<tr valign="top" class="whs15"> 6.618 +<td width="167px" class="whs28"> 6.619 +<p class=Table>Size of Memory in Bytes</td> 6.620 +<td width="524px" class="whs29"> 6.621 +<p class=Table>Specifies the size of the data inline memory.</td></tr> 6.622 + 6.623 +<tr valign="top" class="whs15"> 6.624 +<td colspan="2" rowspan="1" width="691px" class="whs27"> 6.625 +<p class=Table 6.626 + style="font-weight: bold;">Memory File</td> 6.627 +</tr> 6.628 + 6.629 +<tr valign="top" class="whs15"> 6.630 +<td colspan="1" rowspan="1" width="167px" class="whs28"> 6.631 +<p class=Table>Initialization File Name</td> 6.632 +<td colspan="1" rowspan="1" width="524px" class="whs29"> 6.633 +<p class=Table>Specifies the name of the memory initialization file for 6.634 + data inline memory.</td></tr> 6.635 + 6.636 +<tr valign="top" class="whs15"> 6.637 +<td colspan="1" rowspan="1" width="167px" class="whs30"> 6.638 +<p class=Table>File Format</td> 6.639 +<td colspan="1" rowspan="1" width="524px" class="whs31"> 6.640 +<p class=Table>Specifies the format of the memory initialization file: 6.641 + hex or binary.</td></tr> 6.642 +</table> 6.643 + 6.644 +<p> </p> 6.645 + 6.646 +<p>For the revision history of the component RTL files, refer to the header 6.647 + of each component Verilog source file. </p> 6.648 + 6.649 +<p><span style="font-weight: bold;"><B>Note</B></span>: If the processor manual 6.650 + fails to open, click <img src="qm_icon.jpg" x-maintain-ratio="TRUE" width="14px" height="16px" border="0" class="img_whs32"> on the Available Components toolbar, 6.651 + and then click the note button.</p> 6.652 + 6.653 +<script type="text/javascript" language="JavaScript"> 6.654 +<!-- 6.655 + if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) 6.656 + document.write("<div id='tooltip' class='WebHelpPopupMenu'></div>"); 6.657 +//--> 6.658 +</script><script type="text/javascript" language="javascript1.2"> 6.659 +<!-- 6.660 +if (window.writeIntopicBar) 6.661 + writeIntopicBar(0); 6.662 +//--> 6.663 +</script> 6.664 +</body> 6.665 +</html>
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14.108 - 14.109 - } 14.110 - 14.111 - 14.112 - if (window.setRelStartPage) 14.113 - { 14.114 - setRelStartPage("msb_peripherals.htm"); 14.115 - 14.116 - autoSync(0); 14.117 - sendSyncInfo(); 14.118 - sendAveInfoOut(); 14.119 - } 14.120 - 14.121 -} 14.122 -else 14.123 - if (window.gbIE4) 14.124 - document.location.reload(); 14.125 -//--> 14.126 -</script> 14.127 -</head> 14.128 -<body><script type="text/javascript" language="javascript1.2"> 14.129 -<!-- 14.130 -if (window.writeIntopicBar) 14.131 - writeIntopicBar(4); 14.132 -//--> 14.133 -</script> 14.134 -<h1>LatticeMico32 Processor <a title="View Reference Manual" href="lm32_archman.pdf" target="_blank" onmouseover="if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) ehlp_showtip(this,event,'View Reference Manual');" onmouseout="if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) ehlp_hidetip();"><img src="ds_icon_ast.jpg" x-maintain-ratio="TRUE" width="29px" height="31px" border="0" class="img_whs1"></a></h1> 14.135 - 14.136 -<p>The LatticeMico32 processor is a high-performance 32-bit microprocessor 14.137 - optimized for Lattice Semiconductor field-programmable gate arrays. </p> 14.138 - 14.139 -<p class="whs2"><span style="font-style: italic;"><I>*If the 14.140 - processor manual fails to open, see the note at the bottom of this page.</I></span></p> 14.141 - 14.142 -<h2>Revision History</h2> 14.143 - 14.144 -<table x-use-null-cells cellspacing="0" width="738" height="84" class="whs3"> 14.145 -<script language='JavaScript'><!-- 14.146 -if ((navigator.appName == "Netscape") && (parseInt(navigator.appVersion) == 4)) document.write("</table><table x-use-null-cells cellspacing='0' width='738' height='84' border='1' bordercolor='silver' bordercolorlight='silver' bordercolordark='silver'>"); 14.147 -//--></script> 14.148 -<col class="whs4"> 14.149 -<col class="whs5"> 14.150 - 14.151 -<tr valign="top" class="whs6"> 14.152 -<td bgcolor="#DEE8F4" width="93px" class="whs7"> 14.153 -<p class=Table 14.154 - style="font-weight: bold;">Version</td> 14.155 -<td bgcolor="#DEE8F4" width="598px" class="whs8"> 14.156 -<p class=Table 14.157 - style="font-weight: bold;">Description</td></tr> 14.158 - 14.159 -<tr valign="top" class="whs6"> 14.160 -<td colspan="1" rowspan="1" width="93px" class="whs9"> 14.161 -<p class=Table 14.162 - style="font-weight: normal;">3.6</td> 14.163 -<td colspan="1" rowspan="1" width="598px" class="whs10"> 14.164 -<p class=whs10 14.165 - style="margin-left: 0px;">Fixed the issue of the processor locking 14.166 - up when Instruction Cache is not used.</td></tr> 14.167 - 14.168 -<tr valign="top" class="whs6"> 14.169 -<td colspan="1" rowspan="1" width="93px" class="whs9"> 14.170 -<p class=Table 14.171 - style="font-weight: normal;">3.5</td> 14.172 -<td colspan="1" rowspan="1" width="598px" class="whs10"> 14.173 -<p class=whs10 14.174 - style="margin-left: 0px;">Support added to allow Inline Memories to 14.175 - be generated as non-power-of-two, as long as they are a multiple of 1024 14.176 - bytes</td></tr> 14.177 - 14.178 -<tr valign="top" class="whs6"> 14.179 -<td colspan="1" rowspan="1" width="93px" class="whs9"> 14.180 -<p class=Table 14.181 - style="font-weight: normal;">3.4</td> 14.182 -<td colspan="1" rowspan="1" width="598px" class="whs10"> 14.183 -<p class=whs10 14.184 - style="margin-left: 0px;">Updated to support ispLEVER 7.2 SP1.</td></tr> 14.185 - 14.186 -<tr valign="top" class="whs6"> 14.187 -<td colspan="1" rowspan="1" width="93px" class="whs9"> 14.188 -<p class=Table 14.189 - style="font-weight: normal;">3.3</td> 14.190 -<td colspan="1" rowspan="1" width="598px" class="whs10"> 14.191 -<p class=whs10 14.192 - style="margin-left: 0px;">Updated to support ispLEVER 7.2.</p> 14.193 -<p class=whs10 14.194 - style="margin-left: 0px;">Added Inline Memory to support on-chip memory 14.195 - connected through a local bus.</td></tr> 14.196 - 14.197 -<tr valign="top" class="whs6"> 14.198 -<td colspan="1" rowspan="1" width="93px" class="whs9"> 14.199 -<p class=Table 14.200 - style="font-weight: normal;">3.2</td> 14.201 -<td colspan="1" rowspan="1" width="598px" class="whs10"> 14.202 -<p class=whs10 14.203 - style="margin-left: 0px;">Updated to support ispLEVER 7.1 SP1</p> 14.204 -<p class=whs10 14.205 - style="margin-left: 0px;">Added Memory Type to instruction cache and 14.206 - data cache.</td></tr> 14.207 - 14.208 -<tr valign="top" class="whs6"> 14.209 -<td colspan="1" rowspan="1" width="93px" class="whs9"> 14.210 -<p class=Table 14.211 - style="font-weight: normal;">3.1</td> 14.212 -<td colspan="1" rowspan="1" width="598px" class="whs10"> 14.213 -<p class="whs11">Updated to support ispLEVER 7.1.</p> 14.214 -<p class="whs11">Added static predictor to improve the behavior 14.215 - of branches.</p> 14.216 -<p class="whs11">Added support for optionally mapping the register 14.217 - file to EBRs (on-chip memory).</p> 14.218 -<p class="whs11">Added support for selecting between distributed 14.219 - RAM and EBRs (pseudo-dual port or true-dual port) for instruction and 14.220 - data caches.</td></tr> 14.221 - 14.222 -<tr valign="top" class="whs6"> 14.223 -<td colspan="1" rowspan="1" width="93px" class="whs9"> 14.224 -<p class=Table 14.225 - style="font-weight: normal;"><span style="font-weight: normal;">3.0 14.226 - (7.0 SP2)</span></td> 14.227 -<td colspan="1" rowspan="1" width="598px" class="whs10"> 14.228 -<p class="whs11">Updated to support ispLEVER 7.0 SP2.</p> 14.229 -<p class="whs11">Fixed incorrect handling of data cache miss 14.230 - in the presence of an instruction cache miss.</td></tr> 14.231 - 14.232 -<tr valign="top" class="whs6"> 14.233 -<td colspan="1" rowspan="1" width="93px" class="whs9"> 14.234 -<p class="whs11">1.0</td> 14.235 -<td colspan="1" rowspan="1" width="598px" class="whs10"> 14.236 -<p class="whs11">Initial version.</td></tr> 14.237 -<script language='JavaScript'><!-- 14.238 -if ((navigator.appName == "Netscape") && (parseInt(navigator.appVersion) == 4)) document.write("</table></table><table>"); 14.239 -//--></script> 14.240 -</table> 14.241 - 14.242 - 14.243 - 14.244 -<h2>Dialog Box Parameters – 14.245 - General Tab</h2> 14.246 - 14.247 -<table x-use-null-cells cellspacing="0" class="whs12"> 14.248 -<col class="whs13"> 14.249 -<col class="whs14"> 14.250 - 14.251 -<tr valign="top" class="whs15"> 14.252 -<td bgcolor="#DEE8F4" width="167px" class="whs16"> 14.253 -<p class=Table 14.254 - style="font-weight: bold;">Parameter</td> 14.255 -<td bgcolor="#DEE8F4" width="524px" class="whs17"> 14.256 -<p class=Table 14.257 - style="font-weight: bold;">Description</td></tr> 14.258 - 14.259 -<tr valign="top" class="whs15"> 14.260 -<td colspan="1" rowspan="1" width="167px" class="whs18"> 14.261 -<p class=Table 14.262 - style="font-weight: normal;">Instance Name</td> 14.263 -<td colspan="1" rowspan="1" width="524px" class="whs19"> 14.264 -<p class=Table 14.265 - style="margin-left: 14px;">Specifies the name of the LatticeMico32 14.266 - processor. Alphanumeric values and underscores are supported. The default 14.267 - is LM32.</td></tr> 14.268 - 14.269 -<tr valign="top" class="whs15"> 14.270 -<td colspan="2" rowspan="1" width="691px" class="whs20"> 14.271 -<p class=Table 14.272 - style="font-weight: bold;">Settings</td> 14.273 -</tr> 14.274 - 14.275 -<tr valign="top" class="whs15"> 14.276 -<td colspan="1" rowspan="1" width="167px" class="whs18"> 14.277 -<p class=Table>Use EBRs for Register File</td> 14.278 -<td colspan="1" rowspan="1" width="524px" class="whs21"> 14.279 -<p class=Table>Uses embedded block RAMS for the register file.</td></tr> 14.280 - 14.281 -<tr valign="top" class="whs15"> 14.282 -<td colspan="1" rowspan="1" width="167px" class="whs18"> 14.283 -<p class=Table>Enable Divide</td> 14.284 -<td colspan="1" rowspan="1" width="524px" class="whs21"> 14.285 -<p class=Table>Enables the divide and modulus instructions (<span style="font-family: Verdana, sans-serif;">divu, 14.286 - modu</span>).</td></tr> 14.287 - 14.288 -<tr valign="top" class="whs15"> 14.289 -<td colspan="1" rowspan="1" width="167px" class="whs18"> 14.290 -<p class=Table>Enable Sign Extend</td> 14.291 -<td colspan="1" rowspan="1" width="524px" class="whs21"> 14.292 -<p class=Table>Enables the sign-extension instructions (<span style="font-family: Verdana, sans-serif;">sextb, 14.293 - sexth</span><span style="font-family: Arial, sans-serif;">)</span>.</td></tr> 14.294 - 14.295 -<tr valign="top" class="whs15"> 14.296 -<td colspan="1" rowspan="1" width="167px" class="whs18"> 14.297 -<p class=Table>Location of Exception Handlers</td> 14.298 -<td colspan="1" rowspan="1" width="524px" class="whs21"> 14.299 -<p class=Table>Specifies the default value for the vector table. This can 14.300 - be changed by updating the EBA control register or status register.</p> 14.301 -<p class=Table>This address must be aligned to a 256-byte boundary, since 14.302 - the hardware ignores the least-significant byte. Unpredictable behavior 14.303 - occurs when the exception base address and the exception vectors are not 14.304 - aligned on a 256-byte boundary.</td></tr> 14.305 - 14.306 -<tr valign="top" class="whs15"> 14.307 -<td colspan="2" rowspan="1" width="691px" class="whs20"> 14.308 -<p class=Table 14.309 - style="font-weight: bold;">Multiplier Settings</td> 14.310 -</tr> 14.311 - 14.312 -<tr valign="top" class="whs15"> 14.313 -<td colspan="1" rowspan="1" width="167px" class="whs18"> 14.314 -<p class=Table>Enable Multiplier</td> 14.315 -<td colspan="1" rowspan="1" width="524px" class="whs21"> 14.316 -<p class=Table>Enables the multiply instructions (<span style="font-family: Verdana, sans-serif;">mul, 14.317 - muli)</span>.</td></tr> 14.318 - 14.319 -<tr valign="top" class="whs15"> 14.320 -<td colspan="1" rowspan="1" width="167px" class="whs18"> 14.321 -<p class=Table>Enable Pipelined Multiplier (DSP Block if available)</td> 14.322 -<td colspan="1" rowspan="1" width="524px" class="whs21"> 14.323 -<p class=Table>Enables the multiplier using the DSP block, if available.</td></tr> 14.324 - 14.325 -<tr valign="top" class="whs15"> 14.326 -<td colspan="1" rowspan="1" width="167px" class="whs18"> 14.327 -<p class=Table>Enable Multicycle (LUT-based, 32 cycles) Multiplier</td> 14.328 -<td colspan="1" rowspan="1" width="524px" class="whs21"> 14.329 -<p class=Table>Enables the multiplier using LUTs.</td></tr> 14.330 - 14.331 -<tr valign="top" class="whs15"> 14.332 -<td colspan="2" rowspan="1" width="691px" class="whs20"> 14.333 -<p class=Table 14.334 - style="font-weight: bold;">Instruction Cache</td> 14.335 -</tr> 14.336 - 14.337 -<tr valign="top" class="whs15"> 14.338 -<td colspan="1" rowspan="1" width="167px" class="whs18"> 14.339 -<p class=Table>Instruction Cache Enabled</td> 14.340 -<td colspan="1" rowspan="1" width="524px" class="whs19"> 14.341 -<p class=Table 14.342 - style="margin-left: 14px;">Determines whether an instruction cache 14.343 - is implemented.</td></tr> 14.344 - 14.345 -<tr valign="top" class="whs15"> 14.346 -<td colspan="1" rowspan="1" width="167px" class="whs18"> 14.347 -<p class=Table>Number of Sets</td> 14.348 -<td colspan="1" rowspan="1" width="524px" class="whs19"> 14.349 -<p class=Table 14.350 - style="margin-left: 14px;">Specifies the number of sets in the instruction 14.351 - cache. Supported values are 128, 256, 512, 1024.</td></tr> 14.352 - 14.353 -<tr valign="top" class="whs15"> 14.354 -<td colspan="1" rowspan="1" width="167px" class="whs18"> 14.355 -<p class=Table>Set Associativity</td> 14.356 -<td colspan="1" rowspan="1" width="524px" class="whs19"> 14.357 -<p class=Table 14.358 - style="margin-left: 14px;">Specifies the associativity of the instruction 14.359 - cache. Supported values are 1, 2.</td></tr> 14.360 - 14.361 -<tr valign="top" class="whs15"> 14.362 -<td colspan="1" rowspan="1" width="167px" class="whs18"> 14.363 -<p class=Table>Bytes/Cache Line</td> 14.364 -<td colspan="1" rowspan="1" width="524px" class="whs19"> 14.365 -<p class=Table 14.366 - style="margin-left: 15px;">Specifies the number of bytes per instruction 14.367 - cache line. Supported values are 4, 8, 16.</td></tr> 14.368 - 14.369 -<tr valign="top" class="whs15"> 14.370 -<td colspan="1" rowspan="1" width="167px" class="whs18"> 14.371 -<p class=Table>Memory Type</td> 14.372 -<td colspan="1" rowspan="1" width="524px" class="whs19"> 14.373 -<p class=Table 14.374 - style="margin-left: 15px;">Determines the FPGA resource to be used 14.375 - to implement the instruction cache. The decision can be left to the synthesis 14.376 - tool (Auto), or you can select from the following options:</p> 14.377 -<ul type="disc" class="whs22"> 14.378 - 14.379 - <li class=kadov-p-CBullet><p class=Bullet>Auto – 14.380 - Leaves the implementation of the instruction cache to the synthesis tool.</p></li> 14.381 - 14.382 - <li class=kadov-p-CBullet><p class=Bullet>Distributed RAM – 14.383 - Implements the instruction cache as distributed RAM.</p></li> 14.384 - 14.385 - <li class=kadov-p-CBullet><p class=Bullet>Dual-Port EBR – 14.386 - Implements the instruction cache as dual-port EBR (two read/write ports).</p></li> 14.387 - 14.388 - <li class=kadov-p-CBullet><p class=Bullet>Pseudo Dual-Port EBR – Implements 14.389 - the instruction cache as pseudo-dual-port EBR (one read port and one write 14.390 - port). </p></li> 14.391 -</ul></td></tr> 14.392 - 14.393 -<tr valign="top" class="whs15"> 14.394 -<td colspan="2" rowspan="1" width="691px" class="whs20"> 14.395 -<p class=Table 14.396 - style="font-weight: bold;">Debug Setting</td> 14.397 -</tr> 14.398 - 14.399 -<tr valign="top" class="whs15"> 14.400 -<td colspan="1" rowspan="1" width="167px" class="whs18"> 14.401 -<p class=Table>Enable Debug Interface</td> 14.402 -<td colspan="1" rowspan="1" width="524px" class="whs21"> 14.403 -<p class=Table>Includes the debugger stub in the CPU, which is required 14.404 - for debugging.</td></tr> 14.405 - 14.406 -<tr valign="top" class="whs15"> 14.407 -<td colspan="1" rowspan="1" width="167px" class="whs18"> 14.408 -<p class=Table># of H/W Watchpoint Registers</td> 14.409 -<td colspan="1" rowspan="1" width="524px" class="whs21"> 14.410 -<p class=Table 14.411 - style="font-weight: normal;">Specifies the number of hardware watchpoint 14.412 - registers to be used in the debugging process.</td></tr> 14.413 - 14.414 -<tr valign="top" class="whs15"> 14.415 -<td colspan="1" rowspan="1" width="167px" class="whs18"> 14.416 -<p class=Table>Enable Debugging Code in Flash or ROM</td> 14.417 -<td colspan="1" rowspan="1" width="524px" class="whs21"> 14.418 -<p class=Table 14.419 - style="font-weight: normal;">Enables you to set hardware breakpoints 14.420 - in read-only memory.</td></tr> 14.421 - 14.422 -<tr valign="top" class="whs15"> 14.423 -<td colspan="1" rowspan="1" width="167px" class="whs18"> 14.424 -<p class=Table># of H/W Breakpoint Registers</td> 14.425 -<td colspan="1" rowspan="1" width="524px" class="whs21"> 14.426 -<p class=Table>Specifies the number of hardware breakpoint registers to 14.427 - be used in the debugging process.</td></tr> 14.428 - 14.429 -<tr valign="top" class="whs15"> 14.430 -<td colspan="1" rowspan="1" width="167px" class="whs18"> 14.431 -<p class=Table>Enable PC Trace</td> 14.432 -<td colspan="1" rowspan="1" width="524px" class="whs21"> 14.433 -<p class=Table>Enables the Program Counter Trace feature, which enables 14.434 - you to run the program trace during debug to find items in your C or C++ 14.435 - Code during debug, such as breakpoints and exceptions. Refer to <span 14.436 - style="font-weight: bold;"><B>Help > Help Contents > C/C++ SPE</B></span> 14.437 - and <span style="font-weight: bold;"><B>Debug > Concepts > Program 14.438 - Counter Trace</B></span> for more information on Program Counter Trace.</td></tr> 14.439 - 14.440 -<tr valign="top" class="whs15"> 14.441 -<td colspan="1" rowspan="1" width="167px" class="whs18"> 14.442 -<p class=Table>Trace Depth</td> 14.443 -<td colspan="1" rowspan="1" width="524px" class="whs21"> 14.444 -<p class=Table>Enables you to specify the depth of the Program Counter 14.445 - Trace buffer. Refer to <span style="font-weight: bold;"><B>Help > Help 14.446 - Contents > C/C++ SPE</B></span> and <span style="font-weight: bold;"><B>Debug 14.447 - > Concepts > Program Counter Trace</B></span> for more information on 14.448 - Program Counter Trace.</td></tr> 14.449 - 14.450 -<tr valign="top" class="whs15"> 14.451 -<td colspan="2" rowspan="1" width="691px" class="whs20"> 14.452 -<p class=Table 14.453 - style="font-weight: bold;">Shifter Settings</td> 14.454 -</tr> 14.455 - 14.456 -<tr valign="top" class="whs15"> 14.457 -<td colspan="1" rowspan="1" width="167px" class="whs18"> 14.458 -<p class=Table>Enable Piplined Barrel Shifter</td> 14.459 -<td colspan="1" rowspan="1" width="524px" class="whs19"> 14.460 -<p>Enables the barrel shifter to be pipelined. The barrel shifter is implemented 14.461 - to perform a shift operation in three cycles.</td></tr> 14.462 - 14.463 -<tr valign="top" class="whs15"> 14.464 -<td colspan="1" rowspan="1" width="167px" class="whs18"> 14.465 -<p class=Table>Enable Multicycle Barrel Shifter (up to 32 cycles)</td> 14.466 -<td colspan="1" rowspan="1" width="524px" class="whs19"> 14.467 -<p>Enables multi-cycle shift operation for the barrel shifter. The barrel 14.468 - shifter is implemented to shift one bit per cycle and take thirty-two 14.469 - cycles to complete.</td></tr> 14.470 - 14.471 -<tr valign="top" class="whs15"> 14.472 -<td colspan="2" rowspan="1" width="691px" class="whs20"> 14.473 -<p class=Table><span style="font-weight: bold;"><B>Data Cache</B></span></td> 14.474 -</tr> 14.475 - 14.476 -<tr valign="top" class="whs15"> 14.477 -<td colspan="1" rowspan="1" width="167px" class="whs18"> 14.478 -<p class=Table>Data Cache Enabled</td> 14.479 -<td colspan="1" rowspan="1" width="524px" class="whs21"> 14.480 -<p class=Table>Determines whether a data cache is implemented.</td></tr> 14.481 - 14.482 -<tr valign="top" class="whs15"> 14.483 -<td colspan="1" rowspan="1" width="167px" class="whs18"> 14.484 -<p class=Table>Number of Sets</td> 14.485 -<td colspan="1" rowspan="1" width="524px" class="whs21"> 14.486 -<p class=Table>Specifies the number of sets in the data cache. Supported 14.487 - values are 128, 256, 512, 1024.</td></tr> 14.488 - 14.489 -<tr valign="top" class="whs15"> 14.490 -<td colspan="1" rowspan="1" width="167px" class="whs18"> 14.491 -<p class=Table>Set Associativity</td> 14.492 -<td colspan="1" rowspan="1" width="524px" class="whs21"> 14.493 -<p class=Table>Specifies the associativity of the data cache. Supported 14.494 - values are 1, 2.</td></tr> 14.495 - 14.496 -<tr valign="top" class="whs15"> 14.497 -<td colspan="1" rowspan="1" width="167px" class="whs18"> 14.498 -<p class=Table>Bytes/Cache Line</td> 14.499 -<td colspan="1" rowspan="1" width="524px" class="whs21"> 14.500 -<p class=Table>Specifies the number of bytes per data cache line. Supported 14.501 - values are 4, 8, 16.</td></tr> 14.502 - 14.503 -<tr valign="top" class="whs15"> 14.504 -<td colspan="1" rowspan="1" width="167px" class="whs23"> 14.505 -<p class=Table>Memory Type</td> 14.506 -<td colspan="1" rowspan="1" width="524px" class="whs24"> 14.507 -<p class=Table>Determines the FPGA resource to be used to implement the 14.508 - data cache. The decision can be left to the synthesis tool (Auto), or 14.509 - you can select from the following options:</p> 14.510 -<ul> 14.511 - 14.512 - <li class=kadov-p-CBullet><p class=Bullet>Auto – 14.513 - Leaves the implementation of the data cache to the synthesis tool.</p></li> 14.514 - 14.515 - <li class=kadov-p-CBullet><p class=Bullet>Distributed RAM – 14.516 - Implements the data cache as distributed RAM.</p></li> 14.517 - 14.518 - <li class=kadov-p-CBullet><p class=Bullet>Dual-Port EBR – 14.519 - Implements the data cache as dual-port EBR (two read/write ports).</p></li> 14.520 -</ul></td></tr> 14.521 -</table> 14.522 - 14.523 -<p> </p> 14.524 - 14.525 -<h2>Dialog Box Parameters – 14.526 - Inline Memory Tab</h2> 14.527 - 14.528 -<table x-use-null-cells cellspacing="0" class="whs12"> 14.529 -<col class="whs13"> 14.530 -<col class="whs14"> 14.531 - 14.532 -<tr valign="top" class="whs15"> 14.533 -<td bgcolor="#DEE8F4" width="167px" class="whs25"> 14.534 -<p class=Table 14.535 - style="font-weight: bold;">Parameter</td> 14.536 -<td bgcolor="#DEE8F4" width="524px" class="whs26"> 14.537 -<p class=Table 14.538 - style="font-weight: bold;">Description</td></tr> 14.539 - 14.540 -<tr valign="top" class="whs15"> 14.541 -<td rowspan="1" colspan="2" width="691px" class="whs27"> 14.542 -<p class=Table 14.543 - style="font-weight: bold;">Instruction Inline Memory</td> 14.544 -</tr> 14.545 - 14.546 -<tr valign="top" class="whs15"> 14.547 -<td width="167px" class="whs28"> 14.548 -<p class=Table>Enable</td> 14.549 -<td width="524px" class="whs29"> 14.550 -<p class=Table>Enables the instruction inline memory</td></tr> 14.551 - 14.552 -<tr valign="top" class="whs15"> 14.553 -<td width="167px" class="whs28"> 14.554 -<p class=Table>Instance Name</td> 14.555 -<td width="524px" class="whs29"> 14.556 -<p class=Table>Specifics the name of the instruction inline memory. Alphanumeric 14.557 - values and underscores are supported. The default is Instruction_IM.</td></tr> 14.558 - 14.559 -<tr valign="top" class="whs15"> 14.560 -<td width="167px" class="whs28"> 14.561 -<p class=Table>Base Address</td> 14.562 -<td width="524px" class="whs29"> 14.563 -<p class=Table>Specifies the base address for the instruction inline memory. 14.564 - The default is 0x10000000.</td></tr> 14.565 - 14.566 -<tr valign="top" class="whs15"> 14.567 -<td width="167px" class="whs28"> 14.568 -<p class=Table>Size of Memory in Bytes</td> 14.569 -<td width="524px" class="whs29"> 14.570 -<p class=Table>Specifies the size of the instruction inline memory.</td></tr> 14.571 - 14.572 -<tr valign="top" class="whs15"> 14.573 -<td rowspan="1" colspan="2" width="691px" class="whs27"> 14.574 -<p class=Table><span style="font-weight: bold;"><B>Memory File</B></span></td> 14.575 -</tr> 14.576 - 14.577 -<tr valign="top" class="whs15"> 14.578 -<td width="167px" class="whs28"> 14.579 -<p class=Table>Initialization File Name</td> 14.580 -<td width="524px" class="whs29"> 14.581 -<p class=Table>Specifies the name of the memory initialization file for 14.582 - instruction inline memory.</td></tr> 14.583 - 14.584 -<tr valign="top" class="whs15"> 14.585 -<td width="167px" class="whs28"> 14.586 -<p class=Table>File Format</td> 14.587 -<td width="524px" class="whs29"> 14.588 -<p class=Table>Specifies the format of the memory initialization file: 14.589 - hex or binary.</td></tr> 14.590 - 14.591 -<tr valign="top" class="whs15"> 14.592 -<td rowspan="1" colspan="2" width="691px" class="whs27"> 14.593 -<p class=Table 14.594 - style="font-weight: bold;">Data Inline Memory</td> 14.595 -</tr> 14.596 - 14.597 -<tr valign="top" class="whs15"> 14.598 -<td width="167px" class="whs28"> 14.599 -<p class=Table>Enabled</td> 14.600 -<td width="524px" class="whs29"> 14.601 -<p class=Table>Enables the data inline memory.</td></tr> 14.602 - 14.603 -<tr valign="top" class="whs15"> 14.604 -<td width="167px" class="whs28"> 14.605 -<p class=Table>Instance Name</td> 14.606 -<td width="524px" class="whs29"> 14.607 -<p class=Table>Specifies the name of the data inline memory. Alphanumeric 14.608 - values and underscores are supported. The default is Data_IM.</td></tr> 14.609 - 14.610 -<tr valign="top" class="whs15"> 14.611 -<td width="167px" class="whs28"> 14.612 -<p class=Table>Base Address</td> 14.613 -<td width="524px" class="whs29"> 14.614 -<p class=Table>Specifies the base address for the data inline memory. The 14.615 - default is 0x20000000.</td></tr> 14.616 - 14.617 -<tr valign="top" class="whs15"> 14.618 -<td width="167px" class="whs28"> 14.619 -<p class=Table>Size of Memory in Bytes</td> 14.620 -<td width="524px" class="whs29"> 14.621 -<p class=Table>Specifies the size of the data inline memory.</td></tr> 14.622 - 14.623 -<tr valign="top" class="whs15"> 14.624 -<td colspan="2" rowspan="1" width="691px" class="whs27"> 14.625 -<p class=Table 14.626 - style="font-weight: bold;">Memory File</td> 14.627 -</tr> 14.628 - 14.629 -<tr valign="top" class="whs15"> 14.630 -<td colspan="1" rowspan="1" width="167px" class="whs28"> 14.631 -<p class=Table>Initialization File Name</td> 14.632 -<td colspan="1" rowspan="1" width="524px" class="whs29"> 14.633 -<p class=Table>Specifies the name of the memory initialization file for 14.634 - data inline memory.</td></tr> 14.635 - 14.636 -<tr valign="top" class="whs15"> 14.637 -<td colspan="1" rowspan="1" width="167px" class="whs30"> 14.638 -<p class=Table>File Format</td> 14.639 -<td colspan="1" rowspan="1" width="524px" class="whs31"> 14.640 -<p class=Table>Specifies the format of the memory initialization file: 14.641 - hex or binary.</td></tr> 14.642 -</table> 14.643 - 14.644 -<p> </p> 14.645 - 14.646 -<p>For the revision history of the component RTL files, refer to the header 14.647 - of each component Verilog source file. </p> 14.648 - 14.649 -<p><span style="font-weight: bold;"><B>Note</B></span>: If the processor manual 14.650 - fails to open, click <img src="qm_icon.jpg" x-maintain-ratio="TRUE" width="14px" height="16px" border="0" class="img_whs32"> on the Available Components toolbar, 14.651 - and then click the note button.</p> 14.652 - 14.653 -<script type="text/javascript" language="JavaScript"> 14.654 -<!-- 14.655 - if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) 14.656 - document.write("<div id='tooltip' class='WebHelpPopupMenu'></div>"); 14.657 -//--> 14.658 -</script><script type="text/javascript" language="javascript1.2"> 14.659 -<!-- 14.660 -if (window.writeIntopicBar) 14.661 - writeIntopicBar(0); 14.662 -//--> 14.663 -</script> 14.664 -</body> 14.665 -</html>
15.1 diff -r 252df75c8f67 -r c336e674a37e document/lm32_archman.pdf 15.2 Binary file document/lm32_archman.pdf has changed
16.1 diff -r 252df75c8f67 -r c336e674a37e document/qm_icon.jpg 16.2 Binary file document/qm_icon.jpg has changed
17.1 diff -r 252df75c8f67 -r c336e674a37e jtag_cores.v 17.2 --- a/jtag_cores.v Sun Mar 06 21:17:31 2011 +0000 17.3 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 17.4 @@ -1,66 +0,0 @@ 17.5 -// Modified by GSI to use simple positive edge clocking and the JTAG capture state 17.6 - 17.7 -module jtag_cores ( 17.8 - input [7:0] reg_d, 17.9 - input [2:0] reg_addr_d, 17.10 - output reg_update, 17.11 - output [7:0] reg_q, 17.12 - output [2:0] reg_addr_q, 17.13 - output jtck, 17.14 - output jrstn 17.15 -); 17.16 - 17.17 -wire tck; 17.18 -wire tdi; 17.19 -wire tdo; 17.20 -wire capture; 17.21 -wire shift; 17.22 -wire update; 17.23 -wire e1dr; 17.24 -wire reset; 17.25 - 17.26 -jtag_tap jtag_tap ( 17.27 - .tck(tck), 17.28 - .tdi(tdi), 17.29 - .tdo(tdo), 17.30 - .capture(capture), 17.31 - .shift(shift), 17.32 - .e1dr(e1dr), 17.33 - .update(update), 17.34 - .reset(reset) 17.35 -); 17.36 - 17.37 -reg [10:0] jtag_shift; 17.38 -reg [10:0] jtag_latched; 17.39 - 17.40 -always @(posedge tck) 17.41 -begin 17.42 - if(reset) 17.43 - jtag_shift <= 11'b0; 17.44 - else begin 17.45 - if (shift) 17.46 - jtag_shift <= {tdi, jtag_shift[10:1]}; 17.47 - else if (capture) 17.48 - jtag_shift <= {reg_d, reg_addr_d}; 17.49 - end 17.50 -end 17.51 - 17.52 -assign tdo = jtag_shift[0]; 17.53 - 17.54 -always @(posedge tck) 17.55 -begin 17.56 - if(reset) 17.57 - jtag_latched <= 11'b0; 17.58 - else begin 17.59 - if (e1dr) 17.60 - jtag_latched <= jtag_shift; 17.61 - end 17.62 -end 17.63 - 17.64 -assign reg_update = update; 17.65 -assign reg_q = jtag_latched[10:3]; 17.66 -assign reg_addr_q = jtag_latched[2:0]; 17.67 -assign jtck = tck; 17.68 -assign jrstn = ~reset; 17.69 - 17.70 -endmodule
18.1 diff -r 252df75c8f67 -r c336e674a37e jtag_tap_altera.v 18.2 --- a/jtag_tap_altera.v Sun Mar 06 21:17:31 2011 +0000 18.3 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 18.4 @@ -1,59 +0,0 @@ 18.5 -module jtag_tap( 18.6 - output tck, 18.7 - output tdi, 18.8 - input tdo, 18.9 - output capture, 18.10 - output shift, 18.11 - output e1dr, 18.12 - output update, 18.13 - output reset 18.14 -); 18.15 - 18.16 -assign reset = 0; 18.17 -wire nil1, nil2, nil3, nil4; 18.18 - 18.19 -sld_virtual_jtag altera_jtag( 18.20 - .ir_in (), 18.21 - .ir_out (), 18.22 - .tck (tck), 18.23 - .tdo (tdo), 18.24 - .tdi (tdi), 18.25 - .virtual_state_cdr (capture), 18.26 - .virtual_state_sdr (shift), 18.27 - .virtual_state_e1dr (e1dr), 18.28 - .virtual_state_pdr (nil1), 18.29 - .virtual_state_e2dr (nil2), 18.30 - .virtual_state_udr (update), 18.31 - .virtual_state_cir (nil3), 18.32 - .virtual_state_uir (nil4) 18.33 - // synopsys translate_off 18.34 - , 18.35 - .jtag_state_cdr (), 18.36 - .jtag_state_cir (), 18.37 - .jtag_state_e1dr (), 18.38 - .jtag_state_e1ir (), 18.39 - .jtag_state_e2dr (), 18.40 - .jtag_state_e2ir (), 18.41 - .jtag_state_pdr (), 18.42 - .jtag_state_pir (), 18.43 - .jtag_state_rti (), 18.44 - .jtag_state_sdr (), 18.45 - .jtag_state_sdrs (), 18.46 - .jtag_state_sir (), 18.47 - .jtag_state_sirs (), 18.48 - .jtag_state_tlr (), 18.49 - .jtag_state_udr (), 18.50 - .jtag_state_uir (), 18.51 - .tms () 18.52 - // synopsys translate_on 18.53 - ); 18.54 - 18.55 -defparam 18.56 - altera_jtag.sld_auto_instance_index = "YES", 18.57 - altera_jtag.sld_instance_index = 0, 18.58 - altera_jtag.sld_ir_width = 1, 18.59 - altera_jtag.sld_sim_action = "", 18.60 - altera_jtag.sld_sim_n_scan = 0, 18.61 - altera_jtag.sld_sim_total_length = 0; 18.62 - 18.63 -endmodule
19.1 diff -r 252df75c8f67 -r c336e674a37e jtag_tap_xilinx_spartan6.v 19.2 --- a/jtag_tap_xilinx_spartan6.v Sun Mar 06 21:17:31 2011 +0000 19.3 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 19.4 @@ -1,43 +0,0 @@ 19.5 - 19.6 -module jtag_tap( 19.7 - output tck, 19.8 - output tdi, 19.9 - input tdo, 19.10 - output capture, 19.11 - output shift, 19.12 - output e1dr, 19.13 - output update, 19.14 - output reset 19.15 -); 19.16 - 19.17 -// Unfortunately the exit1 state for DR (e1dr) is mising 19.18 -// We can simulate it by interpretting 'update' as e1dr and delaying 'update' 19.19 -wire g_capture; 19.20 -wire g_shift; 19.21 -wire g_update; 19.22 -reg update_delay; 19.23 - 19.24 -assign capture = g_capture & sel; 19.25 -assign shift = g_shift & sel; 19.26 -assign e1dr = g_update & sel; 19.27 -assign update = update_delay; 19.28 - 19.29 -BSCAN_SPARTAN6 #( 19.30 - .JTAG_CHAIN(1) 19.31 -) bscan ( 19.32 - .CAPTURE(g_capture), 19.33 - .DRCK(tck), 19.34 - .RESET(reset), 19.35 - .RUNTEST(), 19.36 - .SEL(sel), 19.37 - .SHIFT(g_shift), 19.38 - .TCK(), 19.39 - .TDI(tdi), 19.40 - .TMS(), 19.41 - .UPDATE(g_update), 19.42 - .TDO(tdo) 19.43 -); 19.44 - 19.45 -update_delay <= g_update; 19.46 - 19.47 -endmodule
20.1 diff -r 252df75c8f67 -r c336e674a37e lm32_adder.v 20.2 --- a/lm32_adder.v Sun Mar 06 21:17:31 2011 +0000 20.3 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 20.4 @@ -1,115 +0,0 @@ 20.5 -// ============================================================================= 20.6 -// COPYRIGHT NOTICE 20.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 20.8 -// ALL RIGHTS RESERVED 20.9 -// This confidential and proprietary software may be used only as authorised by 20.10 -// a licensing agreement from Lattice Semiconductor Corporation. 20.11 -// The entire notice above must be reproduced on all authorized copies and 20.12 -// copies may only be made to the extent permitted by a licensing agreement from 20.13 -// Lattice Semiconductor Corporation. 20.14 -// 20.15 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 20.16 -// 5555 NE Moore Court 408-826-6000 (other locations) 20.17 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 20.18 -// U.S.A email: techsupport@latticesemi.com 20.19 -// ============================================================================/ 20.20 -// FILE DETAILS 20.21 -// Project : LatticeMico32 20.22 -// File : lm32_adder.v 20.23 -// Title : Integer adder / subtractor with comparison flag generation 20.24 -// Dependencies : lm32_include.v 20.25 -// Version : 6.1.17 20.26 -// : Initial Release 20.27 -// Version : 7.0SP2, 3.0 20.28 -// : No Change 20.29 -// Version : 3.1 20.30 -// : No Change 20.31 -// ============================================================================= 20.32 - 20.33 -`include "lm32_include.v" 20.34 - 20.35 -///////////////////////////////////////////////////// 20.36 -// Module interface 20.37 -///////////////////////////////////////////////////// 20.38 - 20.39 -module lm32_adder ( 20.40 - // ----- Inputs ------- 20.41 - adder_op_x, 20.42 - adder_op_x_n, 20.43 - operand_0_x, 20.44 - operand_1_x, 20.45 - // ----- Outputs ------- 20.46 - adder_result_x, 20.47 - adder_carry_n_x, 20.48 - adder_overflow_x 20.49 - ); 20.50 - 20.51 -///////////////////////////////////////////////////// 20.52 -// Inputs 20.53 -///////////////////////////////////////////////////// 20.54 - 20.55 -input adder_op_x; // Operating to perform, 0 for addition, 1 for subtraction 20.56 -input adder_op_x_n; // Inverted version of adder_op_x 20.57 -input [`LM32_WORD_RNG] operand_0_x; // Operand to add, or subtract from 20.58 -input [`LM32_WORD_RNG] operand_1_x; // Opearnd to add, or subtract by 20.59 - 20.60 -///////////////////////////////////////////////////// 20.61 -// Outputs 20.62 -///////////////////////////////////////////////////// 20.63 - 20.64 -output [`LM32_WORD_RNG] adder_result_x; // Result of addition or subtraction 20.65 -wire [`LM32_WORD_RNG] adder_result_x; 20.66 -output adder_carry_n_x; // Inverted carry 20.67 -wire adder_carry_n_x; 20.68 -output adder_overflow_x; // Indicates if overflow occured, only valid for subtractions 20.69 -reg adder_overflow_x; 20.70 - 20.71 -///////////////////////////////////////////////////// 20.72 -// Internal nets and registers 20.73 -///////////////////////////////////////////////////// 20.74 - 20.75 -wire a_sign; // Sign (i.e. positive or negative) of operand 0 20.76 -wire b_sign; // Sign of operand 1 20.77 -wire result_sign; // Sign of result 20.78 - 20.79 -///////////////////////////////////////////////////// 20.80 -// Instantiations 20.81 -///////////////////////////////////////////////////// 20.82 - 20.83 -lm32_addsub addsub ( 20.84 - // ----- Inputs ----- 20.85 - .DataA (operand_0_x), 20.86 - .DataB (operand_1_x), 20.87 - .Cin (adder_op_x), 20.88 - .Add_Sub (adder_op_x_n), 20.89 - // ----- Ouputs ----- 20.90 - .Result (adder_result_x), 20.91 - .Cout (adder_carry_n_x) 20.92 - ); 20.93 - 20.94 -///////////////////////////////////////////////////// 20.95 -// Combinational Logic 20.96 -///////////////////////////////////////////////////// 20.97 - 20.98 -// Extract signs of operands and result 20.99 - 20.100 -assign a_sign = operand_0_x[`LM32_WORD_WIDTH-1]; 20.101 -assign b_sign = operand_1_x[`LM32_WORD_WIDTH-1]; 20.102 -assign result_sign = adder_result_x[`LM32_WORD_WIDTH-1]; 20.103 - 20.104 -// Determine whether an overflow occured when performing a subtraction 20.105 - 20.106 -always @(*) 20.107 -begin 20.108 - // +ve - -ve = -ve -> overflow 20.109 - // -ve - +ve = +ve -> overflow 20.110 - if ( (!a_sign & b_sign & result_sign) 20.111 - || (a_sign & !b_sign & !result_sign) 20.112 - ) 20.113 - adder_overflow_x = `TRUE; 20.114 - else 20.115 - adder_overflow_x = `FALSE; 20.116 -end 20.117 - 20.118 -endmodule 20.119 -
21.1 diff -r 252df75c8f67 -r c336e674a37e lm32_addsub.v 21.2 --- a/lm32_addsub.v Sun Mar 06 21:17:31 2011 +0000 21.3 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 21.4 @@ -1,98 +0,0 @@ 21.5 -// ============================================================================= 21.6 -// COPYRIGHT NOTICE 21.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 21.8 -// ALL RIGHTS RESERVED 21.9 -// This confidential and proprietary software may be used only as authorised by 21.10 -// a licensing agreement from Lattice Semiconductor Corporation. 21.11 -// The entire notice above must be reproduced on all authorized copies and 21.12 -// copies may only be made to the extent permitted by a licensing agreement from 21.13 -// Lattice Semiconductor Corporation. 21.14 -// 21.15 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 21.16 -// 5555 NE Moore Court 408-826-6000 (other locations) 21.17 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 21.18 -// U.S.A email: techsupport@latticesemi.com 21.19 -// =============================================================================/ 21.20 -// FILE DETAILS 21.21 -// Project : LatticeMico32 21.22 -// File : lm32_addsub.v 21.23 -// Title : PMI adder/subtractor. 21.24 -// Version : 6.1.17 21.25 -// : Initial Release 21.26 -// Version : 7.0SP2, 3.0 21.27 -// : No Change 21.28 -// Version : 3.1 21.29 -// : No Change 21.30 -// ============================================================================= 21.31 - 21.32 -`include "lm32_include.v" 21.33 - 21.34 -///////////////////////////////////////////////////// 21.35 -// Module interface 21.36 -///////////////////////////////////////////////////// 21.37 - 21.38 -module lm32_addsub ( 21.39 - // ----- Inputs ------- 21.40 - DataA, 21.41 - DataB, 21.42 - Cin, 21.43 - Add_Sub, 21.44 - // ----- Outputs ------- 21.45 - Result, 21.46 - Cout 21.47 - ); 21.48 - 21.49 -///////////////////////////////////////////////////// 21.50 -// Inputs 21.51 -///////////////////////////////////////////////////// 21.52 - 21.53 -input [31:0] DataA; 21.54 -input [31:0] DataB; 21.55 -input Cin; 21.56 -input Add_Sub; 21.57 - 21.58 -///////////////////////////////////////////////////// 21.59 -// Outputs 21.60 -///////////////////////////////////////////////////// 21.61 - 21.62 -output [31:0] Result; 21.63 -wire [31:0] Result; 21.64 -output Cout; 21.65 -wire Cout; 21.66 - 21.67 -///////////////////////////////////////////////////// 21.68 -// Instantiations 21.69 -///////////////////////////////////////////////////// 21.70 - 21.71 -// Only use Lattice specific constructs when compiling with ispLEVER 21.72 -`ifdef PLATFORM_LATTICE 21.73 - generate 21.74 - if (`LATTICE_FAMILY == "SC" || `LATTICE_FAMILY == "SCM") begin 21.75 -`endif 21.76 - wire [32:0] tmp_addResult = DataA + DataB + Cin; 21.77 - wire [32:0] tmp_subResult = DataA - DataB - !Cin; 21.78 - 21.79 - assign Result = (Add_Sub == 1) ? tmp_addResult[31:0] : tmp_subResult[31:0]; 21.80 - assign Cout = (Add_Sub == 1) ? tmp_addResult[32] : !tmp_subResult[32]; 21.81 -`ifdef PLATFORM_LATTICE 21.82 - end else begin 21.83 - pmi_addsub #(// ----- Parameters ------- 21.84 - .pmi_data_width (32), 21.85 - .pmi_result_width (32), 21.86 - .pmi_sign ("off"), 21.87 - .pmi_family (`LATTICE_FAMILY), 21.88 - .module_type ("pmi_addsub")) 21.89 - addsub (// ----- Inputs ------- 21.90 - .DataA (DataA), 21.91 - .DataB (DataB), 21.92 - .Cin (Cin), 21.93 - .Add_Sub (Add_Sub), 21.94 - // ----- Outputs ------- 21.95 - .Result (Result), 21.96 - .Cout (Cout), 21.97 - .Overflow ()); 21.98 - end 21.99 - endgenerate 21.100 -`endif 21.101 - 21.102 -endmodule
22.1 diff -r 252df75c8f67 -r c336e674a37e lm32_cpu.v 22.2 --- a/lm32_cpu.v Sun Mar 06 21:17:31 2011 +0000 22.3 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 22.4 @@ -1,2717 +0,0 @@ 22.5 -// ============================================================================= 22.6 -// COPYRIGHT NOTICE 22.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 22.8 -// ALL RIGHTS RESERVED 22.9 -// This confidential and proprietary software may be used only as authorised by 22.10 -// a licensing agreement from Lattice Semiconductor Corporation. 22.11 -// The entire notice above must be reproduced on all authorized copies and 22.12 -// copies may only be made to the extent permitted by a licensing agreement from 22.13 -// Lattice Semiconductor Corporation. 22.14 -// 22.15 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 22.16 -// 5555 NE Moore Court 408-826-6000 (other locations) 22.17 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 22.18 -// U.S.A email: techsupport@latticesemi.com 22.19 -// =============================================================================/ 22.20 -// FILE DETAILS 22.21 -// Project : LatticeMico32 22.22 -// File : lm32_cpu.v 22.23 -// Title : Top-level of CPU. 22.24 -// Dependencies : lm32_include.v 22.25 -// 22.26 -// Version 3.4 22.27 -// 1. Bug Fix: In a tight infinite loop (add, sw, bi) incoming interrupts were 22.28 -// never serviced. 22.29 -// 22.30 -// Version 3.3 22.31 -// 1. Feature: Support for memory that is tightly coupled to processor core, and 22.32 -// has a single-cycle access latency (same as caches). Instruction port has 22.33 -// access to a dedicated physically-mapped memory. Data port has access to 22.34 -// a dedicated physically-mapped memory. In order to be able to manipulate 22.35 -// values in both these memories via the debugger, these memories also 22.36 -// interface with the data port of LM32. 22.37 -// 2. Feature: Extended Configuration Register 22.38 -// 3. Bug Fix: Removed port names that conflict with keywords reserved in System- 22.39 -// Verilog. 22.40 -// 22.41 -// Version 3.2 22.42 -// 1. Bug Fix: Single-stepping a load/store to invalid address causes debugger to 22.43 -// hang. At the same time CPU fails to register data bus error exception. Bug 22.44 -// is caused because (a) data bus error exception occurs after load/store has 22.45 -// passed X stage and next sequential instruction (e.g., brk) is already in X 22.46 -// stage, and (b) data bus error exception had lower priority than, say, brk 22.47 -// exception. 22.48 -// 2. Bug Fix: If a brk (or scall/eret/bret) sequentially follows a load/store to 22.49 -// invalid location, CPU will fail to register data bus error exception. The 22.50 -// solution is to stall scall/eret/bret/brk instructions in D pipeline stage 22.51 -// until load/store has completed. 22.52 -// 3. Feature: Enable precise identification of load/store that causes seg fault. 22.53 -// 4. SYNC resets used for register file when implemented in EBRs. 22.54 -// 22.55 -// Version 3.1 22.56 -// 1. Feature: LM32 Register File can now be mapped in to on-chip block RAM (EBR) 22.57 -// instead of distributed memory by enabling the option in LM32 GUI. 22.58 -// 2. Feature: LM32 also adds a static branch predictor to improve branch 22.59 -// performance. All immediate-based forward-pointing branches are predicted 22.60 -// not-taken. All immediate-based backward-pointing branches are predicted taken. 22.61 -// 22.62 -// Version 7.0SP2, 3.0 22.63 -// No Change 22.64 -// 22.65 -// Version 6.1.17 22.66 -// Initial Release 22.67 -// ============================================================================= 22.68 - 22.69 -`include "lm32_include.v" 22.70 - 22.71 -///////////////////////////////////////////////////// 22.72 -// Module interface 22.73 -///////////////////////////////////////////////////// 22.74 - 22.75 -module lm32_cpu ( 22.76 - // ----- Inputs ------- 22.77 - clk_i, 22.78 -`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE 22.79 - clk_n_i, 22.80 -`endif 22.81 - rst_i, 22.82 - // From external devices 22.83 -`ifdef CFG_INTERRUPTS_ENABLED 22.84 - interrupt, 22.85 -`endif 22.86 - // From user logic 22.87 -`ifdef CFG_USER_ENABLED 22.88 - user_result, 22.89 - user_complete, 22.90 -`endif 22.91 -`ifdef CFG_JTAG_ENABLED 22.92 - // From JTAG 22.93 - jtag_clk, 22.94 - jtag_update, 22.95 - jtag_reg_q, 22.96 - jtag_reg_addr_q, 22.97 -`endif 22.98 -`ifdef CFG_IWB_ENABLED 22.99 - // Instruction Wishbone master 22.100 - I_DAT_I, 22.101 - I_ACK_I, 22.102 - I_ERR_I, 22.103 - I_RTY_I, 22.104 -`endif 22.105 - // Data Wishbone master 22.106 - D_DAT_I, 22.107 - D_ACK_I, 22.108 - D_ERR_I, 22.109 - D_RTY_I, 22.110 - // ----- Outputs ------- 22.111 -`ifdef CFG_TRACE_ENABLED 22.112 - trace_pc, 22.113 - trace_pc_valid, 22.114 - trace_exception, 22.115 - trace_eid, 22.116 - trace_eret, 22.117 -`ifdef CFG_DEBUG_ENABLED 22.118 - trace_bret, 22.119 -`endif 22.120 -`endif 22.121 -`ifdef CFG_JTAG_ENABLED 22.122 - jtag_reg_d, 22.123 - jtag_reg_addr_d, 22.124 -`endif 22.125 -`ifdef CFG_USER_ENABLED 22.126 - user_valid, 22.127 - user_opcode, 22.128 - user_operand_0, 22.129 - user_operand_1, 22.130 -`endif 22.131 -`ifdef CFG_IWB_ENABLED 22.132 - // Instruction Wishbone master 22.133 - I_DAT_O, 22.134 - I_ADR_O, 22.135 - I_CYC_O, 22.136 - I_SEL_O, 22.137 - I_STB_O, 22.138 - I_WE_O, 22.139 - I_CTI_O, 22.140 - I_LOCK_O, 22.141 - I_BTE_O, 22.142 -`endif 22.143 - // Data Wishbone master 22.144 - D_DAT_O, 22.145 - D_ADR_O, 22.146 - D_CYC_O, 22.147 - D_SEL_O, 22.148 - D_STB_O, 22.149 - D_WE_O, 22.150 - D_CTI_O, 22.151 - D_LOCK_O, 22.152 - D_BTE_O 22.153 - ); 22.154 - 22.155 -///////////////////////////////////////////////////// 22.156 -// Parameters 22.157 -///////////////////////////////////////////////////// 22.158 - 22.159 -parameter eba_reset = `CFG_EBA_RESET; // Reset value for EBA CSR 22.160 -`ifdef CFG_DEBUG_ENABLED 22.161 -parameter deba_reset = `CFG_DEBA_RESET; // Reset value for DEBA CSR 22.162 -`endif 22.163 - 22.164 -`ifdef CFG_ICACHE_ENABLED 22.165 -parameter icache_associativity = `CFG_ICACHE_ASSOCIATIVITY; // Associativity of the cache (Number of ways) 22.166 -parameter icache_sets = `CFG_ICACHE_SETS; // Number of sets 22.167 -parameter icache_bytes_per_line = `CFG_ICACHE_BYTES_PER_LINE; // Number of bytes per cache line 22.168 -parameter icache_base_address = `CFG_ICACHE_BASE_ADDRESS; // Base address of cachable memory 22.169 -parameter icache_limit = `CFG_ICACHE_LIMIT; // Limit (highest address) of cachable memory 22.170 -`else 22.171 -parameter icache_associativity = 1; 22.172 -parameter icache_sets = 512; 22.173 -parameter icache_bytes_per_line = 16; 22.174 -parameter icache_base_address = 0; 22.175 -parameter icache_limit = 0; 22.176 -`endif 22.177 - 22.178 -`ifdef CFG_DCACHE_ENABLED 22.179 -parameter dcache_associativity = `CFG_DCACHE_ASSOCIATIVITY; // Associativity of the cache (Number of ways) 22.180 -parameter dcache_sets = `CFG_DCACHE_SETS; // Number of sets 22.181 -parameter dcache_bytes_per_line = `CFG_DCACHE_BYTES_PER_LINE; // Number of bytes per cache line 22.182 -parameter dcache_base_address = `CFG_DCACHE_BASE_ADDRESS; // Base address of cachable memory 22.183 -parameter dcache_limit = `CFG_DCACHE_LIMIT; // Limit (highest address) of cachable memory 22.184 -`else 22.185 -parameter dcache_associativity = 1; 22.186 -parameter dcache_sets = 512; 22.187 -parameter dcache_bytes_per_line = 16; 22.188 -parameter dcache_base_address = 0; 22.189 -parameter dcache_limit = 0; 22.190 -`endif 22.191 - 22.192 -`ifdef CFG_DEBUG_ENABLED 22.193 -parameter watchpoints = `CFG_WATCHPOINTS; // Number of h/w watchpoint CSRs 22.194 -`else 22.195 -parameter watchpoints = 0; 22.196 -`endif 22.197 -`ifdef CFG_ROM_DEBUG_ENABLED 22.198 -parameter breakpoints = `CFG_BREAKPOINTS; // Number of h/w breakpoint CSRs 22.199 -`else 22.200 -parameter breakpoints = 0; 22.201 -`endif 22.202 - 22.203 -`ifdef CFG_INTERRUPTS_ENABLED 22.204 -parameter interrupts = `CFG_INTERRUPTS; // Number of interrupts 22.205 -`else 22.206 -parameter interrupts = 0; 22.207 -`endif 22.208 - 22.209 -///////////////////////////////////////////////////// 22.210 -// Inputs 22.211 -///////////////////////////////////////////////////// 22.212 - 22.213 -input clk_i; // Clock 22.214 -`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE 22.215 -input clk_n_i; // Inverted clock 22.216 -`endif 22.217 -input rst_i; // Reset 22.218 - 22.219 -`ifdef CFG_INTERRUPTS_ENABLED 22.220 -input [`LM32_INTERRUPT_RNG] interrupt; // Interrupt pins 22.221 -`endif 22.222 - 22.223 -`ifdef CFG_USER_ENABLED 22.224 -input [`LM32_WORD_RNG] user_result; // User-defined instruction result 22.225 -input user_complete; // User-defined instruction execution is complete 22.226 -`endif 22.227 - 22.228 -`ifdef CFG_JTAG_ENABLED 22.229 -input jtag_clk; // JTAG clock 22.230 -input jtag_update; // JTAG state machine is in data register update state 22.231 -input [`LM32_BYTE_RNG] jtag_reg_q; 22.232 -input [2:0] jtag_reg_addr_q; 22.233 -`endif 22.234 - 22.235 -`ifdef CFG_IWB_ENABLED 22.236 -input [`LM32_WORD_RNG] I_DAT_I; // Instruction Wishbone interface read data 22.237 -input I_ACK_I; // Instruction Wishbone interface acknowledgement 22.238 -input I_ERR_I; // Instruction Wishbone interface error 22.239 -input I_RTY_I; // Instruction Wishbone interface retry 22.240 -`endif 22.241 - 22.242 -input [`LM32_WORD_RNG] D_DAT_I; // Data Wishbone interface read data 22.243 -input D_ACK_I; // Data Wishbone interface acknowledgement 22.244 -input D_ERR_I; // Data Wishbone interface error 22.245 -input D_RTY_I; // Data Wishbone interface retry 22.246 - 22.247 -///////////////////////////////////////////////////// 22.248 -// Outputs 22.249 -///////////////////////////////////////////////////// 22.250 - 22.251 -`ifdef CFG_TRACE_ENABLED 22.252 -output [`LM32_PC_RNG] trace_pc; // PC to trace 22.253 -reg [`LM32_PC_RNG] trace_pc; 22.254 -output trace_pc_valid; // Indicates that a new trace PC is valid 22.255 -reg trace_pc_valid; 22.256 -output trace_exception; // Indicates an exception has occured 22.257 -reg trace_exception; 22.258 -output [`LM32_EID_RNG] trace_eid; // Indicates what type of exception has occured 22.259 -reg [`LM32_EID_RNG] trace_eid; 22.260 -output trace_eret; // Indicates an eret instruction has been executed 22.261 -reg trace_eret; 22.262 -`ifdef CFG_DEBUG_ENABLED 22.263 -output trace_bret; // Indicates a bret instruction has been executed 22.264 -reg trace_bret; 22.265 -`endif 22.266 -`endif 22.267 - 22.268 -`ifdef CFG_JTAG_ENABLED 22.269 -output [`LM32_BYTE_RNG] jtag_reg_d; 22.270 -wire [`LM32_BYTE_RNG] jtag_reg_d; 22.271 -output [2:0] jtag_reg_addr_d; 22.272 -wire [2:0] jtag_reg_addr_d; 22.273 -`endif 22.274 - 22.275 -`ifdef CFG_USER_ENABLED 22.276 -output user_valid; // Indicates if user_opcode is valid 22.277 -wire user_valid; 22.278 -output [`LM32_USER_OPCODE_RNG] user_opcode; // User-defined instruction opcode 22.279 -reg [`LM32_USER_OPCODE_RNG] user_opcode; 22.280 -output [`LM32_WORD_RNG] user_operand_0; // First operand for user-defined instruction 22.281 -wire [`LM32_WORD_RNG] user_operand_0; 22.282 -output [`LM32_WORD_RNG] user_operand_1; // Second operand for user-defined instruction 22.283 -wire [`LM32_WORD_RNG] user_operand_1; 22.284 -`endif 22.285 - 22.286 -`ifdef CFG_IWB_ENABLED 22.287 -output [`LM32_WORD_RNG] I_DAT_O; // Instruction Wishbone interface write data 22.288 -wire [`LM32_WORD_RNG] I_DAT_O; 22.289 -output [`LM32_WORD_RNG] I_ADR_O; // Instruction Wishbone interface address 22.290 -wire [`LM32_WORD_RNG] I_ADR_O; 22.291 -output I_CYC_O; // Instruction Wishbone interface cycle 22.292 -wire I_CYC_O; 22.293 -output [`LM32_BYTE_SELECT_RNG] I_SEL_O; // Instruction Wishbone interface byte select 22.294 -wire [`LM32_BYTE_SELECT_RNG] I_SEL_O; 22.295 -output I_STB_O; // Instruction Wishbone interface strobe 22.296 -wire I_STB_O; 22.297 -output I_WE_O; // Instruction Wishbone interface write enable 22.298 -wire I_WE_O; 22.299 -output [`LM32_CTYPE_RNG] I_CTI_O; // Instruction Wishbone interface cycle type 22.300 -wire [`LM32_CTYPE_RNG] I_CTI_O; 22.301 -output I_LOCK_O; // Instruction Wishbone interface lock bus 22.302 -wire I_LOCK_O; 22.303 -output [`LM32_BTYPE_RNG] I_BTE_O; // Instruction Wishbone interface burst type 22.304 -wire [`LM32_BTYPE_RNG] I_BTE_O; 22.305 -`endif 22.306 - 22.307 -output [`LM32_WORD_RNG] D_DAT_O; // Data Wishbone interface write data 22.308 -wire [`LM32_WORD_RNG] D_DAT_O; 22.309 -output [`LM32_WORD_RNG] D_ADR_O; // Data Wishbone interface address 22.310 -wire [`LM32_WORD_RNG] D_ADR_O; 22.311 -output D_CYC_O; // Data Wishbone interface cycle 22.312 -wire D_CYC_O; 22.313 -output [`LM32_BYTE_SELECT_RNG] D_SEL_O; // Data Wishbone interface byte select 22.314 -wire [`LM32_BYTE_SELECT_RNG] D_SEL_O; 22.315 -output D_STB_O; // Data Wishbone interface strobe 22.316 -wire D_STB_O; 22.317 -output D_WE_O; // Data Wishbone interface write enable 22.318 -wire D_WE_O; 22.319 -output [`LM32_CTYPE_RNG] D_CTI_O; // Data Wishbone interface cycle type 22.320 -wire [`LM32_CTYPE_RNG] D_CTI_O; 22.321 -output D_LOCK_O; // Date Wishbone interface lock bus 22.322 -wire D_LOCK_O; 22.323 -output [`LM32_BTYPE_RNG] D_BTE_O; // Data Wishbone interface burst type 22.324 -wire [`LM32_BTYPE_RNG] D_BTE_O; 22.325 - 22.326 -///////////////////////////////////////////////////// 22.327 -// Internal nets and registers 22.328 -///////////////////////////////////////////////////// 22.329 - 22.330 -// Pipeline registers 22.331 - 22.332 -`ifdef LM32_CACHE_ENABLED 22.333 -reg valid_a; // Instruction in A stage is valid 22.334 -`endif 22.335 -reg valid_f; // Instruction in F stage is valid 22.336 -reg valid_d; // Instruction in D stage is valid 22.337 -reg valid_x; // Instruction in X stage is valid 22.338 -reg valid_m; // Instruction in M stage is valid 22.339 -reg valid_w; // Instruction in W stage is valid 22.340 - 22.341 -wire q_x; 22.342 -wire [`LM32_WORD_RNG] immediate_d; // Immediate operand 22.343 -wire load_d; // Indicates a load instruction 22.344 -reg load_x; 22.345 -reg load_m; 22.346 -wire load_q_x; 22.347 -wire store_q_x; 22.348 -wire store_d; // Indicates a store instruction 22.349 -reg store_x; 22.350 -reg store_m; 22.351 -wire [`LM32_SIZE_RNG] size_d; // Size of load/store (byte, hword, word) 22.352 -reg [`LM32_SIZE_RNG] size_x; 22.353 -wire branch_d; // Indicates a branch instruction 22.354 -wire branch_predict_d; // Indicates a branch is predicted 22.355 -wire branch_predict_taken_d; // Indicates a branch is predicted taken 22.356 -wire [`LM32_PC_RNG] branch_predict_address_d; // Address to which predicted branch jumps 22.357 -wire [`LM32_PC_RNG] branch_target_d; 22.358 -wire bi_unconditional; 22.359 -wire bi_conditional; 22.360 -reg branch_x; 22.361 -reg branch_predict_x; 22.362 -reg branch_predict_taken_x; 22.363 -reg branch_m; 22.364 -reg branch_predict_m; 22.365 -reg branch_predict_taken_m; 22.366 -wire branch_mispredict_taken_m; // Indicates a branch was mispredicted as taken 22.367 -wire branch_flushX_m; // Indicates that instruction in X stage must be squashed 22.368 -wire branch_reg_d; // Branch to register or immediate 22.369 -wire [`LM32_PC_RNG] branch_offset_d; // Branch offset for immediate branches 22.370 -reg [`LM32_PC_RNG] branch_target_x; // Address to branch to 22.371 -reg [`LM32_PC_RNG] branch_target_m; 22.372 -wire [`LM32_D_RESULT_SEL_0_RNG] d_result_sel_0_d; // Which result should be selected in D stage for operand 0 22.373 -wire [`LM32_D_RESULT_SEL_1_RNG] d_result_sel_1_d; // Which result should be selected in D stage for operand 1 22.374 - 22.375 -wire x_result_sel_csr_d; // Select X stage result from CSRs 22.376 -reg x_result_sel_csr_x; 22.377 -`ifdef LM32_MC_ARITHMETIC_ENABLED 22.378 -wire x_result_sel_mc_arith_d; // Select X stage result from multi-cycle arithmetic unit 22.379 -reg x_result_sel_mc_arith_x; 22.380 -`endif 22.381 -`ifdef LM32_NO_BARREL_SHIFT 22.382 -wire x_result_sel_shift_d; // Select X stage result from shifter 22.383 -reg x_result_sel_shift_x; 22.384 -`endif 22.385 -`ifdef CFG_SIGN_EXTEND_ENABLED 22.386 -wire x_result_sel_sext_d; // Select X stage result from sign-extend logic 22.387 -reg x_result_sel_sext_x; 22.388 -`endif 22.389 -wire x_result_sel_logic_d; // Select X stage result from logic op unit 22.390 -reg x_result_sel_logic_x; 22.391 -`ifdef CFG_USER_ENABLED 22.392 -wire x_result_sel_user_d; // Select X stage result from user-defined logic 22.393 -reg x_result_sel_user_x; 22.394 -`endif 22.395 -wire x_result_sel_add_d; // Select X stage result from adder 22.396 -reg x_result_sel_add_x; 22.397 -wire m_result_sel_compare_d; // Select M stage result from comparison logic 22.398 -reg m_result_sel_compare_x; 22.399 -reg m_result_sel_compare_m; 22.400 -`ifdef CFG_PL_BARREL_SHIFT_ENABLED 22.401 -wire m_result_sel_shift_d; // Select M stage result from shifter 22.402 -reg m_result_sel_shift_x; 22.403 -reg m_result_sel_shift_m; 22.404 -`endif 22.405 -wire w_result_sel_load_d; // Select W stage result from load/store unit 22.406 -reg w_result_sel_load_x; 22.407 -reg w_result_sel_load_m; 22.408 -reg w_result_sel_load_w; 22.409 -`ifdef CFG_PL_MULTIPLY_ENABLED 22.410 -wire w_result_sel_mul_d; // Select W stage result from multiplier 22.411 -reg w_result_sel_mul_x; 22.412 -reg w_result_sel_mul_m; 22.413 -reg w_result_sel_mul_w; 22.414 -`endif 22.415 -wire x_bypass_enable_d; // Whether result is bypassable in X stage 22.416 -reg x_bypass_enable_x; 22.417 -wire m_bypass_enable_d; // Whether result is bypassable in M stage 22.418 -reg m_bypass_enable_x; 22.419 -reg m_bypass_enable_m; 22.420 -wire sign_extend_d; // Whether to sign-extend or zero-extend 22.421 -reg sign_extend_x; 22.422 -wire write_enable_d; // Register file write enable 22.423 -reg write_enable_x; 22.424 -wire write_enable_q_x; 22.425 -reg write_enable_m; 22.426 -wire write_enable_q_m; 22.427 -reg write_enable_w; 22.428 -wire write_enable_q_w; 22.429 -wire read_enable_0_d; // Register file read enable 0 22.430 -wire [`LM32_REG_IDX_RNG] read_idx_0_d; // Register file read index 0 22.431 -wire read_enable_1_d; // Register file read enable 1 22.432 -wire [`LM32_REG_IDX_RNG] read_idx_1_d; // Register file read index 1 22.433 -wire [`LM32_REG_IDX_RNG] write_idx_d; // Register file write index 22.434 -reg [`LM32_REG_IDX_RNG] write_idx_x; 22.435 -reg [`LM32_REG_IDX_RNG] write_idx_m; 22.436 -reg [`LM32_REG_IDX_RNG] write_idx_w; 22.437 -wire [`LM32_CSR_RNG] csr_d; // CSR read/write index 22.438 -reg [`LM32_CSR_RNG] csr_x; 22.439 -wire [`LM32_CONDITION_RNG] condition_d; // Branch condition 22.440 -reg [`LM32_CONDITION_RNG] condition_x; 22.441 -`ifdef CFG_DEBUG_ENABLED 22.442 -wire break_d; // Indicates a break instruction 22.443 -reg break_x; 22.444 -`endif 22.445 -wire scall_d; // Indicates a scall instruction 22.446 -reg scall_x; 22.447 -wire eret_d; // Indicates an eret instruction 22.448 -reg eret_x; 22.449 -wire eret_q_x; 22.450 -reg eret_m; 22.451 -`ifdef CFG_TRACE_ENABLED 22.452 -reg eret_w; 22.453 -`endif 22.454 -`ifdef CFG_DEBUG_ENABLED 22.455 -wire bret_d; // Indicates a bret instruction 22.456 -reg bret_x; 22.457 -wire bret_q_x; 22.458 -reg bret_m; 22.459 -`ifdef CFG_TRACE_ENABLED 22.460 -reg bret_w; 22.461 -`endif 22.462 -`endif 22.463 -wire csr_write_enable_d; // CSR write enable 22.464 -reg csr_write_enable_x; 22.465 -wire csr_write_enable_q_x; 22.466 -`ifdef CFG_USER_ENABLED 22.467 -wire [`LM32_USER_OPCODE_RNG] user_opcode_d; // User-defined instruction opcode 22.468 -`endif 22.469 - 22.470 -`ifdef CFG_BUS_ERRORS_ENABLED 22.471 -wire bus_error_d; // Indicates an bus error occured while fetching the instruction in this pipeline stage 22.472 -reg bus_error_x; 22.473 -reg data_bus_error_exception_m; 22.474 -reg [`LM32_PC_RNG] memop_pc_w; 22.475 -`endif 22.476 - 22.477 -reg [`LM32_WORD_RNG] d_result_0; // Result of instruction in D stage (operand 0) 22.478 -reg [`LM32_WORD_RNG] d_result_1; // Result of instruction in D stage (operand 1) 22.479 -reg [`LM32_WORD_RNG] x_result; // Result of instruction in X stage 22.480 -reg [`LM32_WORD_RNG] m_result; // Result of instruction in M stage 22.481 -reg [`LM32_WORD_RNG] w_result; // Result of instruction in W stage 22.482 - 22.483 -reg [`LM32_WORD_RNG] operand_0_x; // Operand 0 for X stage instruction 22.484 -reg [`LM32_WORD_RNG] operand_1_x; // Operand 1 for X stage instruction 22.485 -reg [`LM32_WORD_RNG] store_operand_x; // Data read from register to store 22.486 -reg [`LM32_WORD_RNG] operand_m; // Operand for M stage instruction 22.487 -reg [`LM32_WORD_RNG] operand_w; // Operand for W stage instruction 22.488 - 22.489 -// To/from register file 22.490 -`ifdef CFG_EBR_POSEDGE_REGISTER_FILE 22.491 -reg [`LM32_WORD_RNG] reg_data_live_0; 22.492 -reg [`LM32_WORD_RNG] reg_data_live_1; 22.493 -reg use_buf; // Whether to use reg_data_live or reg_data_buf 22.494 -reg [`LM32_WORD_RNG] reg_data_buf_0; 22.495 -reg [`LM32_WORD_RNG] reg_data_buf_1; 22.496 -`endif 22.497 -`ifdef LM32_EBR_REGISTER_FILE 22.498 -`else 22.499 -reg [`LM32_WORD_RNG] registers[0:(1<<`LM32_REG_IDX_WIDTH)-1]; // Register file 22.500 -`endif 22.501 -wire [`LM32_WORD_RNG] reg_data_0; // Register file read port 0 data 22.502 -wire [`LM32_WORD_RNG] reg_data_1; // Register file read port 1 data 22.503 -reg [`LM32_WORD_RNG] bypass_data_0; // Register value 0 after bypassing 22.504 -reg [`LM32_WORD_RNG] bypass_data_1; // Register value 1 after bypassing 22.505 -wire reg_write_enable_q_w; 22.506 - 22.507 -reg interlock; // Indicates pipeline should be stalled because of a read-after-write hazzard 22.508 - 22.509 -wire stall_a; // Stall instruction in A pipeline stage 22.510 -wire stall_f; // Stall instruction in F pipeline stage 22.511 -wire stall_d; // Stall instruction in D pipeline stage 22.512 -wire stall_x; // Stall instruction in X pipeline stage 22.513 -wire stall_m; // Stall instruction in M pipeline stage 22.514 - 22.515 -// To/from adder 22.516 -wire adder_op_d; // Whether to add or subtract 22.517 -reg adder_op_x; 22.518 -reg adder_op_x_n; // Inverted version of adder_op_x 22.519 -wire [`LM32_WORD_RNG] adder_result_x; // Result from adder 22.520 -wire adder_overflow_x; // Whether a signed overflow occured 22.521 -wire adder_carry_n_x; // Whether a carry was generated 22.522 - 22.523 -// To/from logical operations unit 22.524 -wire [`LM32_LOGIC_OP_RNG] logic_op_d; // Which operation to perform 22.525 -reg [`LM32_LOGIC_OP_RNG] logic_op_x; 22.526 -wire [`LM32_WORD_RNG] logic_result_x; // Result of logical operation 22.527 - 22.528 -`ifdef CFG_SIGN_EXTEND_ENABLED 22.529 -// From sign-extension unit 22.530 -wire [`LM32_WORD_RNG] sextb_result_x; // Result of byte sign-extension 22.531 -wire [`LM32_WORD_RNG] sexth_result_x; // Result of half-word sign-extenstion 22.532 -wire [`LM32_WORD_RNG] sext_result_x; // Result of sign-extension specified by instruction 22.533 -`endif 22.534 - 22.535 -// To/from shifter 22.536 -`ifdef CFG_PL_BARREL_SHIFT_ENABLED 22.537 -`ifdef CFG_ROTATE_ENABLED 22.538 -wire rotate_d; // Whether we should rotate or shift 22.539 -reg rotate_x; 22.540 -`endif 22.541 -wire direction_d; // Which direction to shift in 22.542 -reg direction_x; 22.543 -wire [`LM32_WORD_RNG] shifter_result_m; // Result of shifter 22.544 -`endif 22.545 -`ifdef CFG_MC_BARREL_SHIFT_ENABLED 22.546 -wire shift_left_d; // Indicates whether to perform a left shift or not 22.547 -wire shift_left_q_d; 22.548 -wire shift_right_d; // Indicates whether to perform a right shift or not 22.549 -wire shift_right_q_d; 22.550 -`endif 22.551 -`ifdef LM32_NO_BARREL_SHIFT 22.552 -wire [`LM32_WORD_RNG] shifter_result_x; // Result of single-bit right shifter 22.553 -`endif 22.554 - 22.555 -// To/from multiplier 22.556 -`ifdef LM32_MULTIPLY_ENABLED 22.557 -wire [`LM32_WORD_RNG] multiplier_result_w; // Result from multiplier 22.558 -`endif 22.559 -`ifdef CFG_MC_MULTIPLY_ENABLED 22.560 -wire multiply_d; // Indicates whether to perform a multiply or not 22.561 -wire multiply_q_d; 22.562 -`endif 22.563 - 22.564 -// To/from divider 22.565 -`ifdef CFG_MC_DIVIDE_ENABLED 22.566 -wire divide_d; // Indicates whether to perform a divider or not 22.567 -wire divide_q_d; 22.568 -wire modulus_d; 22.569 -wire modulus_q_d; 22.570 -wire divide_by_zero_x; // Indicates an attempt was made to divide by zero 22.571 -`endif 22.572 - 22.573 -// To from multi-cycle arithmetic unit 22.574 -`ifdef LM32_MC_ARITHMETIC_ENABLED 22.575 -wire mc_stall_request_x; // Multi-cycle arithmetic unit stall request 22.576 -wire [`LM32_WORD_RNG] mc_result_x; 22.577 -`endif 22.578 - 22.579 -// From CSRs 22.580 -`ifdef CFG_INTERRUPTS_ENABLED 22.581 -wire [`LM32_WORD_RNG] interrupt_csr_read_data_x;// Data read from interrupt CSRs 22.582 -`endif 22.583 -wire [`LM32_WORD_RNG] cfg; // Configuration CSR 22.584 -wire [`LM32_WORD_RNG] cfg2; // Extended Configuration CSR 22.585 -`ifdef CFG_CYCLE_COUNTER_ENABLED 22.586 -reg [`LM32_WORD_RNG] cc; // Cycle counter CSR 22.587 -`endif 22.588 -reg [`LM32_WORD_RNG] csr_read_data_x; // Data read from CSRs 22.589 - 22.590 -// To/from instruction unit 22.591 -wire [`LM32_PC_RNG] pc_f; // PC of instruction in F stage 22.592 -wire [`LM32_PC_RNG] pc_d; // PC of instruction in D stage 22.593 -wire [`LM32_PC_RNG] pc_x; // PC of instruction in X stage 22.594 -wire [`LM32_PC_RNG] pc_m; // PC of instruction in M stage 22.595 -wire [`LM32_PC_RNG] pc_w; // PC of instruction in W stage 22.596 -`ifdef CFG_TRACE_ENABLED 22.597 -reg [`LM32_PC_RNG] pc_c; // PC of last commited instruction 22.598 -`endif 22.599 -`ifdef CFG_EBR_POSEDGE_REGISTER_FILE 22.600 -wire [`LM32_INSTRUCTION_RNG] instruction_f; // Instruction in F stage 22.601 -`endif 22.602 -//pragma attribute instruction_d preserve_signal true 22.603 -//pragma attribute instruction_d preserve_driver true 22.604 -wire [`LM32_INSTRUCTION_RNG] instruction_d; // Instruction in D stage 22.605 -`ifdef CFG_ICACHE_ENABLED 22.606 -wire iflush; // Flush instruction cache 22.607 -wire icache_stall_request; // Stall pipeline because instruction cache is busy 22.608 -wire icache_restart_request; // Restart instruction that caused an instruction cache miss 22.609 -wire icache_refill_request; // Request to refill instruction cache 22.610 -wire icache_refilling; // Indicates the instruction cache is being refilled 22.611 -`endif 22.612 -`ifdef CFG_IROM_ENABLED 22.613 -wire [`LM32_WORD_RNG] irom_store_data_m; // Store data to instruction ROM 22.614 -wire [`LM32_WORD_RNG] irom_address_xm; // Address to instruction ROM from load-store unit 22.615 -wire [`LM32_WORD_RNG] irom_data_m; // Load data from instruction ROM 22.616 -wire irom_we_xm; // Indicates data needs to be written to instruction ROM 22.617 -wire irom_stall_request_x; // Indicates D stage needs to be stalled on a store to instruction ROM 22.618 -`endif 22.619 - 22.620 -// To/from load/store unit 22.621 -`ifdef CFG_DCACHE_ENABLED 22.622 -wire dflush_x; // Flush data cache 22.623 -reg dflush_m; 22.624 -wire dcache_stall_request; // Stall pipeline because data cache is busy 22.625 -wire dcache_restart_request; // Restart instruction that caused a data cache miss 22.626 -wire dcache_refill_request; // Request to refill data cache 22.627 -wire dcache_refilling; // Indicates the data cache is being refilled 22.628 -`endif 22.629 -wire [`LM32_WORD_RNG] load_data_w; // Result of a load instruction 22.630 -wire stall_wb_load; // Stall pipeline because of a load via the data Wishbone interface 22.631 - 22.632 -// To/from JTAG interface 22.633 -`ifdef CFG_JTAG_ENABLED 22.634 -`ifdef CFG_JTAG_UART_ENABLED 22.635 -wire [`LM32_WORD_RNG] jtx_csr_read_data; // Read data for JTX CSR 22.636 -wire [`LM32_WORD_RNG] jrx_csr_read_data; // Read data for JRX CSR 22.637 -`endif 22.638 -`ifdef CFG_HW_DEBUG_ENABLED 22.639 -wire jtag_csr_write_enable; // Debugger CSR write enable 22.640 -wire [`LM32_WORD_RNG] jtag_csr_write_data; // Data to write to specified CSR 22.641 -wire [`LM32_CSR_RNG] jtag_csr; // Which CSR to write 22.642 -wire jtag_read_enable; 22.643 -wire [`LM32_BYTE_RNG] jtag_read_data; 22.644 -wire jtag_write_enable; 22.645 -wire [`LM32_BYTE_RNG] jtag_write_data; 22.646 -wire [`LM32_WORD_RNG] jtag_address; 22.647 -wire jtag_access_complete; 22.648 -`endif 22.649 -`ifdef CFG_DEBUG_ENABLED 22.650 -wire jtag_break; // Request from debugger to raise a breakpoint 22.651 -`endif 22.652 -`endif 22.653 - 22.654 -// Hazzard detection 22.655 -wire raw_x_0; // RAW hazzard between instruction in X stage and read port 0 22.656 -wire raw_x_1; // RAW hazzard between instruction in X stage and read port 1 22.657 -wire raw_m_0; // RAW hazzard between instruction in M stage and read port 0 22.658 -wire raw_m_1; // RAW hazzard between instruction in M stage and read port 1 22.659 -wire raw_w_0; // RAW hazzard between instruction in W stage and read port 0 22.660 -wire raw_w_1; // RAW hazzard between instruction in W stage and read port 1 22.661 - 22.662 -// Control flow 22.663 -wire cmp_zero; // Result of comparison is zero 22.664 -wire cmp_negative; // Result of comparison is negative 22.665 -wire cmp_overflow; // Comparison produced an overflow 22.666 -wire cmp_carry_n; // Comparison produced a carry, inverted 22.667 -reg condition_met_x; // Condition of branch instruction is met 22.668 -reg condition_met_m; 22.669 -`ifdef CFG_FAST_UNCONDITIONAL_BRANCH 22.670 -wire branch_taken_x; // Branch is taken in X stage 22.671 -`endif 22.672 -wire branch_taken_m; // Branch is taken in M stage 22.673 - 22.674 -wire kill_f; // Kill instruction in F stage 22.675 -wire kill_d; // Kill instruction in D stage 22.676 -wire kill_x; // Kill instruction in X stage 22.677 -wire kill_m; // Kill instruction in M stage 22.678 -wire kill_w; // Kill instruction in W stage 22.679 - 22.680 -reg [`LM32_PC_WIDTH+2-1:8] eba; // Exception Base Address (EBA) CSR 22.681 -`ifdef CFG_DEBUG_ENABLED 22.682 -reg [`LM32_PC_WIDTH+2-1:8] deba; // Debug Exception Base Address (DEBA) CSR 22.683 -`endif 22.684 -reg [`LM32_EID_RNG] eid_x; // Exception ID in X stage 22.685 -`ifdef CFG_TRACE_ENABLED 22.686 -reg [`LM32_EID_RNG] eid_m; // Exception ID in M stage 22.687 -reg [`LM32_EID_RNG] eid_w; // Exception ID in W stage 22.688 -`endif 22.689 - 22.690 -`ifdef CFG_DEBUG_ENABLED 22.691 -`ifdef LM32_SINGLE_STEP_ENABLED 22.692 -wire dc_ss; // Is single-step enabled 22.693 -`endif 22.694 -wire dc_re; // Remap all exceptions 22.695 -wire exception_x; // An exception occured in the X stage 22.696 -reg exception_m; // An instruction that caused an exception is in the M stage 22.697 -wire debug_exception_x; // Indicates if a debug exception has occured 22.698 -reg debug_exception_m; 22.699 -reg debug_exception_w; 22.700 -wire debug_exception_q_w; 22.701 -wire non_debug_exception_x; // Indicates if a non debug exception has occured 22.702 -reg non_debug_exception_m; 22.703 -reg non_debug_exception_w; 22.704 -wire non_debug_exception_q_w; 22.705 -`else 22.706 -wire exception_x; // Indicates if a debug exception has occured 22.707 -reg exception_m; 22.708 -reg exception_w; 22.709 -wire exception_q_w; 22.710 -`endif 22.711 - 22.712 -`ifdef CFG_DEBUG_ENABLED 22.713 -`ifdef CFG_JTAG_ENABLED 22.714 -wire reset_exception; // Indicates if a reset exception has occured 22.715 -`endif 22.716 -`endif 22.717 -`ifdef CFG_INTERRUPTS_ENABLED 22.718 -wire interrupt_exception; // Indicates if an interrupt exception has occured 22.719 -`endif 22.720 -`ifdef CFG_DEBUG_ENABLED 22.721 -wire breakpoint_exception; // Indicates if a breakpoint exception has occured 22.722 -wire watchpoint_exception; // Indicates if a watchpoint exception has occured 22.723 -`endif 22.724 -`ifdef CFG_BUS_ERRORS_ENABLED 22.725 -wire instruction_bus_error_exception; // Indicates if an instruction bus error exception has occured 22.726 -wire data_bus_error_exception; // Indicates if a data bus error exception has occured 22.727 -`endif 22.728 -`ifdef CFG_MC_DIVIDE_ENABLED 22.729 -wire divide_by_zero_exception; // Indicates if a divide by zero exception has occured 22.730 -`endif 22.731 -wire system_call_exception; // Indicates if a system call exception has occured 22.732 - 22.733 -`ifdef CFG_BUS_ERRORS_ENABLED 22.734 -reg data_bus_error_seen; // Indicates if a data bus error was seen 22.735 -`endif 22.736 - 22.737 -///////////////////////////////////////////////////// 22.738 -// Functions 22.739 -///////////////////////////////////////////////////// 22.740 - 22.741 -`include "lm32_functions.v" 22.742 - 22.743 -///////////////////////////////////////////////////// 22.744 -// Instantiations 22.745 -///////////////////////////////////////////////////// 22.746 - 22.747 -// Instruction unit 22.748 -lm32_instruction_unit #( 22.749 - .associativity (icache_associativity), 22.750 - .sets (icache_sets), 22.751 - .bytes_per_line (icache_bytes_per_line), 22.752 - .base_address (icache_base_address), 22.753 - .limit (icache_limit) 22.754 - ) instruction_unit ( 22.755 - // ----- Inputs ------- 22.756 - .clk_i (clk_i), 22.757 - .rst_i (rst_i), 22.758 - // From pipeline 22.759 - .stall_a (stall_a), 22.760 - .stall_f (stall_f), 22.761 - .stall_d (stall_d), 22.762 - .stall_x (stall_x), 22.763 - .stall_m (stall_m), 22.764 - .valid_f (valid_f), 22.765 - .valid_d (valid_d), 22.766 - .kill_f (kill_f), 22.767 - .branch_predict_taken_d (branch_predict_taken_d), 22.768 - .branch_predict_address_d (branch_predict_address_d), 22.769 -`ifdef CFG_FAST_UNCONDITIONAL_BRANCH 22.770 - .branch_taken_x (branch_taken_x), 22.771 - .branch_target_x (branch_target_x), 22.772 -`endif 22.773 - .exception_m (exception_m), 22.774 - .branch_taken_m (branch_taken_m), 22.775 - .branch_mispredict_taken_m (branch_mispredict_taken_m), 22.776 - .branch_target_m (branch_target_m), 22.777 -`ifdef CFG_ICACHE_ENABLED 22.778 - .iflush (iflush), 22.779 -`endif 22.780 -`ifdef CFG_IROM_ENABLED 22.781 - .irom_store_data_m (irom_store_data_m), 22.782 - .irom_address_xm (irom_address_xm), 22.783 - .irom_we_xm (irom_we_xm), 22.784 -`endif 22.785 -`ifdef CFG_DCACHE_ENABLED 22.786 - .dcache_restart_request (dcache_restart_request), 22.787 - .dcache_refill_request (dcache_refill_request), 22.788 - .dcache_refilling (dcache_refilling), 22.789 -`endif 22.790 -`ifdef CFG_IWB_ENABLED 22.791 - // From Wishbone 22.792 - .i_dat_i (I_DAT_I), 22.793 - .i_ack_i (I_ACK_I), 22.794 - .i_err_i (I_ERR_I), 22.795 -`endif 22.796 -`ifdef CFG_HW_DEBUG_ENABLED 22.797 - .jtag_read_enable (jtag_read_enable), 22.798 - .jtag_write_enable (jtag_write_enable), 22.799 - .jtag_write_data (jtag_write_data), 22.800 - .jtag_address (jtag_address), 22.801 -`endif 22.802 - // ----- Outputs ------- 22.803 - // To pipeline 22.804 - .pc_f (pc_f), 22.805 - .pc_d (pc_d), 22.806 - .pc_x (pc_x), 22.807 - .pc_m (pc_m), 22.808 - .pc_w (pc_w), 22.809 -`ifdef CFG_ICACHE_ENABLED 22.810 - .icache_stall_request (icache_stall_request), 22.811 - .icache_restart_request (icache_restart_request), 22.812 - .icache_refill_request (icache_refill_request), 22.813 - .icache_refilling (icache_refilling), 22.814 -`endif 22.815 -`ifdef CFG_IROM_ENABLED 22.816 - .irom_data_m (irom_data_m), 22.817 -`endif 22.818 -`ifdef CFG_IWB_ENABLED 22.819 - // To Wishbone 22.820 - .i_dat_o (I_DAT_O), 22.821 - .i_adr_o (I_ADR_O), 22.822 - .i_cyc_o (I_CYC_O), 22.823 - .i_sel_o (I_SEL_O), 22.824 - .i_stb_o (I_STB_O), 22.825 - .i_we_o (I_WE_O), 22.826 - .i_cti_o (I_CTI_O), 22.827 - .i_lock_o (I_LOCK_O), 22.828 - .i_bte_o (I_BTE_O), 22.829 -`endif 22.830 -`ifdef CFG_HW_DEBUG_ENABLED 22.831 - .jtag_read_data (jtag_read_data), 22.832 - .jtag_access_complete (jtag_access_complete), 22.833 -`endif 22.834 -`ifdef CFG_BUS_ERRORS_ENABLED 22.835 - .bus_error_d (bus_error_d), 22.836 -`endif 22.837 -`ifdef CFG_EBR_POSEDGE_REGISTER_FILE 22.838 - .instruction_f (instruction_f), 22.839 -`endif 22.840 - .instruction_d (instruction_d) 22.841 - ); 22.842 - 22.843 -// Instruction decoder 22.844 -lm32_decoder decoder ( 22.845 - // ----- Inputs ------- 22.846 - .instruction (instruction_d), 22.847 - // ----- Outputs ------- 22.848 - .d_result_sel_0 (d_result_sel_0_d), 22.849 - .d_result_sel_1 (d_result_sel_1_d), 22.850 - .x_result_sel_csr (x_result_sel_csr_d), 22.851 -`ifdef LM32_MC_ARITHMETIC_ENABLED 22.852 - .x_result_sel_mc_arith (x_result_sel_mc_arith_d), 22.853 -`endif 22.854 -`ifdef LM32_NO_BARREL_SHIFT 22.855 - .x_result_sel_shift (x_result_sel_shift_d), 22.856 -`endif 22.857 -`ifdef CFG_SIGN_EXTEND_ENABLED 22.858 - .x_result_sel_sext (x_result_sel_sext_d), 22.859 -`endif 22.860 - .x_result_sel_logic (x_result_sel_logic_d), 22.861 -`ifdef CFG_USER_ENABLED 22.862 - .x_result_sel_user (x_result_sel_user_d), 22.863 -`endif 22.864 - .x_result_sel_add (x_result_sel_add_d), 22.865 - .m_result_sel_compare (m_result_sel_compare_d), 22.866 -`ifdef CFG_PL_BARREL_SHIFT_ENABLED 22.867 - .m_result_sel_shift (m_result_sel_shift_d), 22.868 -`endif 22.869 - .w_result_sel_load (w_result_sel_load_d), 22.870 -`ifdef CFG_PL_MULTIPLY_ENABLED 22.871 - .w_result_sel_mul (w_result_sel_mul_d), 22.872 -`endif 22.873 - .x_bypass_enable (x_bypass_enable_d), 22.874 - .m_bypass_enable (m_bypass_enable_d), 22.875 - .read_enable_0 (read_enable_0_d), 22.876 - .read_idx_0 (read_idx_0_d), 22.877 - .read_enable_1 (read_enable_1_d), 22.878 - .read_idx_1 (read_idx_1_d), 22.879 - .write_enable (write_enable_d), 22.880 - .write_idx (write_idx_d), 22.881 - .immediate (immediate_d), 22.882 - .branch_offset (branch_offset_d), 22.883 - .load (load_d), 22.884 - .store (store_d), 22.885 - .size (size_d), 22.886 - .sign_extend (sign_extend_d), 22.887 - .adder_op (adder_op_d), 22.888 - .logic_op (logic_op_d), 22.889 -`ifdef CFG_PL_BARREL_SHIFT_ENABLED 22.890 - .direction (direction_d), 22.891 -`endif 22.892 -`ifdef CFG_MC_BARREL_SHIFT_ENABLED 22.893 - .shift_left (shift_left_d), 22.894 - .shift_right (shift_right_d), 22.895 -`endif 22.896 -`ifdef CFG_MC_MULTIPLY_ENABLED 22.897 - .multiply (multiply_d), 22.898 -`endif 22.899 -`ifdef CFG_MC_DIVIDE_ENABLED 22.900 - .divide (divide_d), 22.901 - .modulus (modulus_d), 22.902 -`endif 22.903 - .branch (branch_d), 22.904 - .bi_unconditional (bi_unconditional), 22.905 - .bi_conditional (bi_conditional), 22.906 - .branch_reg (branch_reg_d), 22.907 - .condition (condition_d), 22.908 -`ifdef CFG_DEBUG_ENABLED 22.909 - .break_opcode (break_d), 22.910 -`endif 22.911 - .scall (scall_d), 22.912 - .eret (eret_d), 22.913 -`ifdef CFG_DEBUG_ENABLED 22.914 - .bret (bret_d), 22.915 -`endif 22.916 -`ifdef CFG_USER_ENABLED 22.917 - .user_opcode (user_opcode_d), 22.918 -`endif 22.919 - .csr_write_enable (csr_write_enable_d) 22.920 - ); 22.921 - 22.922 -// Load/store unit 22.923 -lm32_load_store_unit #( 22.924 - .associativity (dcache_associativity), 22.925 - .sets (dcache_sets), 22.926 - .bytes_per_line (dcache_bytes_per_line), 22.927 - .base_address (dcache_base_address), 22.928 - .limit (dcache_limit) 22.929 - ) load_store_unit ( 22.930 - // ----- Inputs ------- 22.931 - .clk_i (clk_i), 22.932 - .rst_i (rst_i), 22.933 - // From pipeline 22.934 - .stall_a (stall_a), 22.935 - .stall_x (stall_x), 22.936 - .stall_m (stall_m), 22.937 - .kill_m (kill_m), 22.938 - .exception_m (exception_m), 22.939 - .store_operand_x (store_operand_x), 22.940 - .load_store_address_x (adder_result_x), 22.941 - .load_store_address_m (operand_m), 22.942 - .load_store_address_w (operand_w[1:0]), 22.943 - .load_x (load_x), 22.944 - .store_x (store_x), 22.945 - .load_q_x (load_q_x), 22.946 - .store_q_x (store_q_x), 22.947 - .load_q_m (load_q_m), 22.948 - .store_q_m (store_q_m), 22.949 - .sign_extend_x (sign_extend_x), 22.950 - .size_x (size_x), 22.951 -`ifdef CFG_DCACHE_ENABLED 22.952 - .dflush (dflush_m), 22.953 -`endif 22.954 -`ifdef CFG_IROM_ENABLED 22.955 - .irom_data_m (irom_data_m), 22.956 -`endif 22.957 - // From Wishbone 22.958 - .d_dat_i (D_DAT_I), 22.959 - .d_ack_i (D_ACK_I), 22.960 - .d_err_i (D_ERR_I), 22.961 - .d_rty_i (D_RTY_I), 22.962 - // ----- Outputs ------- 22.963 - // To pipeline 22.964 -`ifdef CFG_DCACHE_ENABLED 22.965 - .dcache_refill_request (dcache_refill_request), 22.966 - .dcache_restart_request (dcache_restart_request), 22.967 - .dcache_stall_request (dcache_stall_request), 22.968 - .dcache_refilling (dcache_refilling), 22.969 -`endif 22.970 -`ifdef CFG_IROM_ENABLED 22.971 - .irom_store_data_m (irom_store_data_m), 22.972 - .irom_address_xm (irom_address_xm), 22.973 - .irom_we_xm (irom_we_xm), 22.974 - .irom_stall_request_x (irom_stall_request_x), 22.975 -`endif 22.976 - .load_data_w (load_data_w), 22.977 - .stall_wb_load (stall_wb_load), 22.978 - // To Wishbone 22.979 - .d_dat_o (D_DAT_O), 22.980 - .d_adr_o (D_ADR_O), 22.981 - .d_cyc_o (D_CYC_O), 22.982 - .d_sel_o (D_SEL_O), 22.983 - .d_stb_o (D_STB_O), 22.984 - .d_we_o (D_WE_O), 22.985 - .d_cti_o (D_CTI_O), 22.986 - .d_lock_o (D_LOCK_O), 22.987 - .d_bte_o (D_BTE_O) 22.988 - ); 22.989 - 22.990 -// Adder 22.991 -lm32_adder adder ( 22.992 - // ----- Inputs ------- 22.993 - .adder_op_x (adder_op_x), 22.994 - .adder_op_x_n (adder_op_x_n), 22.995 - .operand_0_x (operand_0_x), 22.996 - .operand_1_x (operand_1_x), 22.997 - // ----- Outputs ------- 22.998 - .adder_result_x (adder_result_x), 22.999 - .adder_carry_n_x (adder_carry_n_x), 22.1000 - .adder_overflow_x (adder_overflow_x) 22.1001 - ); 22.1002 - 22.1003 -// Logic operations 22.1004 -lm32_logic_op logic_op ( 22.1005 - // ----- Inputs ------- 22.1006 - .logic_op_x (logic_op_x), 22.1007 - .operand_0_x (operand_0_x), 22.1008 - 22.1009 - .operand_1_x (operand_1_x), 22.1010 - // ----- Outputs ------- 22.1011 - .logic_result_x (logic_result_x) 22.1012 - ); 22.1013 - 22.1014 -`ifdef CFG_PL_BARREL_SHIFT_ENABLED 22.1015 -// Pipelined barrel-shifter 22.1016 -lm32_shifter shifter ( 22.1017 - // ----- Inputs ------- 22.1018 - .clk_i (clk_i), 22.1019 - .rst_i (rst_i), 22.1020 - .stall_x (stall_x), 22.1021 - .direction_x (direction_x), 22.1022 - .sign_extend_x (sign_extend_x), 22.1023 - .operand_0_x (operand_0_x), 22.1024 - .operand_1_x (operand_1_x), 22.1025 - // ----- Outputs ------- 22.1026 - .shifter_result_m (shifter_result_m) 22.1027 - ); 22.1028 -`endif 22.1029 - 22.1030 -`ifdef CFG_PL_MULTIPLY_ENABLED 22.1031 -// Pipeline fixed-point multiplier 22.1032 -lm32_multiplier multiplier ( 22.1033 - // ----- Inputs ------- 22.1034 - .clk_i (clk_i), 22.1035 - .rst_i (rst_i), 22.1036 - .stall_x (stall_x), 22.1037 - .stall_m (stall_m), 22.1038 - .operand_0 (d_result_0), 22.1039 - .operand_1 (d_result_1), 22.1040 - // ----- Outputs ------- 22.1041 - .result (multiplier_result_w) 22.1042 - ); 22.1043 -`endif 22.1044 - 22.1045 -`ifdef LM32_MC_ARITHMETIC_ENABLED 22.1046 -// Multi-cycle arithmetic 22.1047 -lm32_mc_arithmetic mc_arithmetic ( 22.1048 - // ----- Inputs ------- 22.1049 - .clk_i (clk_i), 22.1050 - .rst_i (rst_i), 22.1051 - .stall_d (stall_d), 22.1052 - .kill_x (kill_x), 22.1053 -`ifdef CFG_MC_DIVIDE_ENABLED 22.1054 - .divide_d (divide_q_d), 22.1055 - .modulus_d (modulus_q_d), 22.1056 -`endif 22.1057 -`ifdef CFG_MC_MULTIPLY_ENABLED 22.1058 - .multiply_d (multiply_q_d), 22.1059 -`endif 22.1060 -`ifdef CFG_MC_BARREL_SHIFT_ENABLED 22.1061 - .shift_left_d (shift_left_q_d), 22.1062 - .shift_right_d (shift_right_q_d), 22.1063 - .sign_extend_d (sign_extend_d), 22.1064 -`endif 22.1065 - .operand_0_d (d_result_0), 22.1066 - .operand_1_d (d_result_1), 22.1067 - // ----- Outputs ------- 22.1068 - .result_x (mc_result_x), 22.1069 -`ifdef CFG_MC_DIVIDE_ENABLED 22.1070 - .divide_by_zero_x (divide_by_zero_x), 22.1071 -`endif 22.1072 - .stall_request_x (mc_stall_request_x) 22.1073 - ); 22.1074 -`endif 22.1075 - 22.1076 -`ifdef CFG_INTERRUPTS_ENABLED 22.1077 -// Interrupt unit 22.1078 -lm32_interrupt interrupt_unit ( 22.1079 - // ----- Inputs ------- 22.1080 - .clk_i (clk_i), 22.1081 - .rst_i (rst_i), 22.1082 - // From external devices 22.1083 - .interrupt (interrupt), 22.1084 - // From pipeline 22.1085 - .stall_x (stall_x), 22.1086 -`ifdef CFG_DEBUG_ENABLED 22.1087 - .non_debug_exception (non_debug_exception_q_w), 22.1088 - .debug_exception (debug_exception_q_w), 22.1089 -`else 22.1090 - .exception (exception_q_w), 22.1091 -`endif 22.1092 - .eret_q_x (eret_q_x), 22.1093 -`ifdef CFG_DEBUG_ENABLED 22.1094 - .bret_q_x (bret_q_x), 22.1095 -`endif 22.1096 - .csr (csr_x), 22.1097 - .csr_write_data (operand_1_x), 22.1098 - .csr_write_enable (csr_write_enable_q_x), 22.1099 - // ----- Outputs ------- 22.1100 - .interrupt_exception (interrupt_exception), 22.1101 - // To pipeline 22.1102 - .csr_read_data (interrupt_csr_read_data_x) 22.1103 - ); 22.1104 -`endif 22.1105 - 22.1106 -`ifdef CFG_JTAG_ENABLED 22.1107 -// JTAG interface 22.1108 -lm32_jtag jtag ( 22.1109 - // ----- Inputs ------- 22.1110 - .clk_i (clk_i), 22.1111 - .rst_i (rst_i), 22.1112 - // From JTAG 22.1113 - .jtag_clk (jtag_clk), 22.1114 - .jtag_update (jtag_update), 22.1115 - .jtag_reg_q (jtag_reg_q), 22.1116 - .jtag_reg_addr_q (jtag_reg_addr_q), 22.1117 - // From pipeline 22.1118 -`ifdef CFG_JTAG_UART_ENABLED 22.1119 - .csr (csr_x), 22.1120 - .csr_write_data (operand_1_x), 22.1121 - .csr_write_enable (csr_write_enable_q_x), 22.1122 - .stall_x (stall_x), 22.1123 -`endif 22.1124 -`ifdef CFG_HW_DEBUG_ENABLED 22.1125 - .jtag_read_data (jtag_read_data), 22.1126 - .jtag_access_complete (jtag_access_complete), 22.1127 -`endif 22.1128 -`ifdef CFG_DEBUG_ENABLED 22.1129 - .exception_q_w (debug_exception_q_w || non_debug_exception_q_w), 22.1130 -`endif 22.1131 - // ----- Outputs ------- 22.1132 - // To pipeline 22.1133 -`ifdef CFG_JTAG_UART_ENABLED 22.1134 - .jtx_csr_read_data (jtx_csr_read_data), 22.1135 - .jrx_csr_read_data (jrx_csr_read_data), 22.1136 -`endif 22.1137 -`ifdef CFG_HW_DEBUG_ENABLED 22.1138 - .jtag_csr_write_enable (jtag_csr_write_enable), 22.1139 - .jtag_csr_write_data (jtag_csr_write_data), 22.1140 - .jtag_csr (jtag_csr), 22.1141 - .jtag_read_enable (jtag_read_enable), 22.1142 - .jtag_write_enable (jtag_write_enable), 22.1143 - .jtag_write_data (jtag_write_data), 22.1144 - .jtag_address (jtag_address), 22.1145 -`endif 22.1146 -`ifdef CFG_DEBUG_ENABLED 22.1147 - .jtag_break (jtag_break), 22.1148 - .jtag_reset (reset_exception), 22.1149 -`endif 22.1150 - // To JTAG 22.1151 - .jtag_reg_d (jtag_reg_d), 22.1152 - .jtag_reg_addr_d (jtag_reg_addr_d) 22.1153 - ); 22.1154 -`endif 22.1155 - 22.1156 -`ifdef CFG_DEBUG_ENABLED 22.1157 -// Debug unit 22.1158 -lm32_debug #( 22.1159 - .breakpoints (breakpoints), 22.1160 - .watchpoints (watchpoints) 22.1161 - ) hw_debug ( 22.1162 - // ----- Inputs ------- 22.1163 - .clk_i (clk_i), 22.1164 - .rst_i (rst_i), 22.1165 - .pc_x (pc_x), 22.1166 - .load_x (load_x), 22.1167 - .store_x (store_x), 22.1168 - .load_store_address_x (adder_result_x), 22.1169 - .csr_write_enable_x (csr_write_enable_q_x), 22.1170 - .csr_write_data (operand_1_x), 22.1171 - .csr_x (csr_x), 22.1172 -`ifdef CFG_HW_DEBUG_ENABLED 22.1173 - .jtag_csr_write_enable (jtag_csr_write_enable), 22.1174 - .jtag_csr_write_data (jtag_csr_write_data), 22.1175 - .jtag_csr (jtag_csr), 22.1176 -`endif 22.1177 -`ifdef LM32_SINGLE_STEP_ENABLED 22.1178 - .eret_q_x (eret_q_x), 22.1179 - .bret_q_x (bret_q_x), 22.1180 - .stall_x (stall_x), 22.1181 - .exception_x (exception_x), 22.1182 - .q_x (q_x), 22.1183 -`ifdef CFG_DCACHE_ENABLED 22.1184 - .dcache_refill_request (dcache_refill_request), 22.1185 -`endif 22.1186 -`endif 22.1187 - // ----- Outputs ------- 22.1188 -`ifdef LM32_SINGLE_STEP_ENABLED 22.1189 - .dc_ss (dc_ss), 22.1190 -`endif 22.1191 - .dc_re (dc_re), 22.1192 - .bp_match (bp_match), 22.1193 - .wp_match (wp_match) 22.1194 - ); 22.1195 -`endif 22.1196 - 22.1197 -// Register file 22.1198 - 22.1199 -`ifdef CFG_EBR_POSEDGE_REGISTER_FILE 22.1200 - /*---------------------------------------------------------------------- 22.1201 - Register File is implemented using EBRs. There can be three accesses to 22.1202 - the register file in each cycle: two reads and one write. On-chip block 22.1203 - RAM has two read/write ports. To accomodate three accesses, two on-chip 22.1204 - block RAMs are used (each register file "write" is made to both block 22.1205 - RAMs). 22.1206 - 22.1207 - One limitation of the on-chip block RAMs is that one cannot perform a 22.1208 - read and write to same location in a cycle (if this is done, then the 22.1209 - data read out is indeterminate). 22.1210 - ----------------------------------------------------------------------*/ 22.1211 - wire [31:0] regfile_data_0, regfile_data_1; 22.1212 - reg [31:0] w_result_d; 22.1213 - reg regfile_raw_0, regfile_raw_0_nxt; 22.1214 - reg regfile_raw_1, regfile_raw_1_nxt; 22.1215 - 22.1216 - /*---------------------------------------------------------------------- 22.1217 - Check if read and write is being performed to same register in current 22.1218 - cycle? This is done by comparing the read and write IDXs. 22.1219 - ----------------------------------------------------------------------*/ 22.1220 - always @(reg_write_enable_q_w or write_idx_w or instruction_f) 22.1221 - begin 22.1222 - if (reg_write_enable_q_w 22.1223 - && (write_idx_w == instruction_f[25:21])) 22.1224 - regfile_raw_0_nxt = 1'b1; 22.1225 - else 22.1226 - regfile_raw_0_nxt = 1'b0; 22.1227 - 22.1228 - if (reg_write_enable_q_w 22.1229 - && (write_idx_w == instruction_f[20:16])) 22.1230 - regfile_raw_1_nxt = 1'b1; 22.1231 - else 22.1232 - regfile_raw_1_nxt = 1'b0; 22.1233 - end 22.1234 - 22.1235 - /*---------------------------------------------------------------------- 22.1236 - Select latched (delayed) write value or data from register file. If 22.1237 - read in previous cycle was performed to register written to in same 22.1238 - cycle, then latched (delayed) write value is selected. 22.1239 - ----------------------------------------------------------------------*/ 22.1240 - always @(regfile_raw_0 or w_result_d or regfile_data_0) 22.1241 - if (regfile_raw_0) 22.1242 - reg_data_live_0 = w_result_d; 22.1243 - else 22.1244 - reg_data_live_0 = regfile_data_0; 22.1245 - 22.1246 - /*---------------------------------------------------------------------- 22.1247 - Select latched (delayed) write value or data from register file. If 22.1248 - read in previous cycle was performed to register written to in same 22.1249 - cycle, then latched (delayed) write value is selected. 22.1250 - ----------------------------------------------------------------------*/ 22.1251 - always @(regfile_raw_1 or w_result_d or regfile_data_1) 22.1252 - if (regfile_raw_1) 22.1253 - reg_data_live_1 = w_result_d; 22.1254 - else 22.1255 - reg_data_live_1 = regfile_data_1; 22.1256 - 22.1257 - /*---------------------------------------------------------------------- 22.1258 - Latch value written to register file 22.1259 - ----------------------------------------------------------------------*/ 22.1260 - always @(posedge clk_i `CFG_RESET_SENSITIVITY) 22.1261 - if (rst_i == `TRUE) 22.1262 - begin 22.1263 - regfile_raw_0 <= 1'b0; 22.1264 - regfile_raw_1 <= 1'b0; 22.1265 - w_result_d <= 32'b0; 22.1266 - end 22.1267 - else 22.1268 - begin 22.1269 - regfile_raw_0 <= regfile_raw_0_nxt; 22.1270 - regfile_raw_1 <= regfile_raw_1_nxt; 22.1271 - w_result_d <= w_result; 22.1272 - end 22.1273 - 22.1274 - /*---------------------------------------------------------------------- 22.1275 - Register file instantiation as Pseudo-Dual Port EBRs. 22.1276 - ----------------------------------------------------------------------*/ 22.1277 - // Modified by GSI: removed non-portable RAM instantiation 22.1278 - lm32_dp_ram 22.1279 - #( 22.1280 - // ----- Parameters ----- 22.1281 - .addr_depth(1<<5), 22.1282 - .addr_width(5), 22.1283 - .data_width(32) 22.1284 - ) 22.1285 - reg_0 22.1286 - ( 22.1287 - // ----- Inputs ----- 22.1288 - .clk_i (clk_i), 22.1289 - .rst_i (rst_i), 22.1290 - .we_i (reg_write_enable_q_w), 22.1291 - .wdata_i (w_result), 22.1292 - .waddr_i (write_idx_w), 22.1293 - .raddr_i (instruction_f[25:21]), 22.1294 - // ----- Outputs ----- 22.1295 - .rdata_o (regfile_data_0) 22.1296 - ); 22.1297 - 22.1298 - lm32_dp_ram 22.1299 - #( 22.1300 - .addr_depth(1<<5), 22.1301 - .addr_width(5), 22.1302 - .data_width(32) 22.1303 - ) 22.1304 - reg_1 22.1305 - ( 22.1306 - // ----- Inputs ----- 22.1307 - .clk_i (clk_i), 22.1308 - .rst_i (rst_i), 22.1309 - .we_i (reg_write_enable_q_w), 22.1310 - .wdata_i (w_result), 22.1311 - .waddr_i (write_idx_w), 22.1312 - .raddr_i (instruction_f[20:16]), 22.1313 - // ----- Outputs ----- 22.1314 - .rdata_o (regfile_data_1) 22.1315 - ); 22.1316 -`endif 22.1317 - 22.1318 -`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE 22.1319 - pmi_ram_dp 22.1320 - #( 22.1321 - // ----- Parameters ----- 22.1322 - .pmi_wr_addr_depth(1<<5), 22.1323 - .pmi_wr_addr_width(5), 22.1324 - .pmi_wr_data_width(32), 22.1325 - .pmi_rd_addr_depth(1<<5), 22.1326 - .pmi_rd_addr_width(5), 22.1327 - .pmi_rd_data_width(32), 22.1328 - .pmi_regmode("noreg"), 22.1329 - .pmi_gsr("enable"), 22.1330 - .pmi_resetmode("sync"), 22.1331 - .pmi_init_file("none"), 22.1332 - .pmi_init_file_format("binary"), 22.1333 - .pmi_family(`LATTICE_FAMILY), 22.1334 - .module_type("pmi_ram_dp") 22.1335 - ) 22.1336 - reg_0 22.1337 - ( 22.1338 - // ----- Inputs ----- 22.1339 - .Data(w_result), 22.1340 - .WrAddress(write_idx_w), 22.1341 - .RdAddress(read_idx_0_d), 22.1342 - .WrClock(clk_i), 22.1343 - .RdClock(clk_n_i), 22.1344 - .WrClockEn(`TRUE), 22.1345 - .RdClockEn(stall_f == `FALSE), 22.1346 - .WE(reg_write_enable_q_w), 22.1347 - .Reset(rst_i), 22.1348 - // ----- Outputs ----- 22.1349 - .Q(reg_data_0) 22.1350 - ); 22.1351 - 22.1352 - pmi_ram_dp 22.1353 - #( 22.1354 - // ----- Parameters ----- 22.1355 - .pmi_wr_addr_depth(1<<5), 22.1356 - .pmi_wr_addr_width(5), 22.1357 - .pmi_wr_data_width(32), 22.1358 - .pmi_rd_addr_depth(1<<5), 22.1359 - .pmi_rd_addr_width(5), 22.1360 - .pmi_rd_data_width(32), 22.1361 - .pmi_regmode("noreg"), 22.1362 - .pmi_gsr("enable"), 22.1363 - .pmi_resetmode("sync"), 22.1364 - .pmi_init_file("none"), 22.1365 - .pmi_init_file_format("binary"), 22.1366 - .pmi_family(`LATTICE_FAMILY), 22.1367 - .module_type("pmi_ram_dp") 22.1368 - ) 22.1369 - reg_1 22.1370 - ( 22.1371 - // ----- Inputs ----- 22.1372 - .Data(w_result), 22.1373 - .WrAddress(write_idx_w), 22.1374 - .RdAddress(read_idx_1_d), 22.1375 - .WrClock(clk_i), 22.1376 - .RdClock(clk_n_i), 22.1377 - .WrClockEn(`TRUE), 22.1378 - .RdClockEn(stall_f == `FALSE), 22.1379 - .WE(reg_write_enable_q_w), 22.1380 - .Reset(rst_i), 22.1381 - // ----- Outputs ----- 22.1382 - .Q(reg_data_1) 22.1383 - ); 22.1384 -`endif 22.1385 - 22.1386 - 22.1387 -///////////////////////////////////////////////////// 22.1388 -// Combinational Logic 22.1389 -///////////////////////////////////////////////////// 22.1390 - 22.1391 -`ifdef CFG_EBR_POSEDGE_REGISTER_FILE 22.1392 -// Select between buffered and live data from register file 22.1393 -assign reg_data_0 = use_buf ? reg_data_buf_0 : reg_data_live_0; 22.1394 -assign reg_data_1 = use_buf ? reg_data_buf_1 : reg_data_live_1; 22.1395 -`endif 22.1396 -`ifdef LM32_EBR_REGISTER_FILE 22.1397 -`else 22.1398 -// Register file read ports 22.1399 -assign reg_data_0 = registers[read_idx_0_d]; 22.1400 -assign reg_data_1 = registers[read_idx_1_d]; 22.1401 -`endif 22.1402 - 22.1403 -// Detect read-after-write hazzards 22.1404 -assign raw_x_0 = (write_idx_x == read_idx_0_d) && (write_enable_q_x == `TRUE); 22.1405 -assign raw_m_0 = (write_idx_m == read_idx_0_d) && (write_enable_q_m == `TRUE); 22.1406 -assign raw_w_0 = (write_idx_w == read_idx_0_d) && (write_enable_q_w == `TRUE); 22.1407 -assign raw_x_1 = (write_idx_x == read_idx_1_d) && (write_enable_q_x == `TRUE); 22.1408 -assign raw_m_1 = (write_idx_m == read_idx_1_d) && (write_enable_q_m == `TRUE); 22.1409 -assign raw_w_1 = (write_idx_w == read_idx_1_d) && (write_enable_q_w == `TRUE); 22.1410 - 22.1411 -// Interlock detection - Raise an interlock for RAW hazzards 22.1412 -always @(*) 22.1413 -begin 22.1414 - if ( ( (x_bypass_enable_x == `FALSE) 22.1415 - && ( ((read_enable_0_d == `TRUE) && (raw_x_0 == `TRUE)) 22.1416 - || ((read_enable_1_d == `TRUE) && (raw_x_1 == `TRUE)) 22.1417 - ) 22.1418 - ) 22.1419 - || ( (m_bypass_enable_m == `FALSE) 22.1420 - && ( ((read_enable_0_d == `TRUE) && (raw_m_0 == `TRUE)) 22.1421 - || ((read_enable_1_d == `TRUE) && (raw_m_1 == `TRUE)) 22.1422 - ) 22.1423 - ) 22.1424 - ) 22.1425 - interlock = `TRUE; 22.1426 - else 22.1427 - interlock = `FALSE; 22.1428 -end 22.1429 - 22.1430 -// Bypass for reg port 0 22.1431 -always @(*) 22.1432 -begin 22.1433 - if (raw_x_0 == `TRUE) 22.1434 - bypass_data_0 = x_result; 22.1435 - else if (raw_m_0 == `TRUE) 22.1436 - bypass_data_0 = m_result; 22.1437 - else if (raw_w_0 == `TRUE) 22.1438 - bypass_data_0 = w_result; 22.1439 - else 22.1440 - bypass_data_0 = reg_data_0; 22.1441 -end 22.1442 - 22.1443 -// Bypass for reg port 1 22.1444 -always @(*) 22.1445 -begin 22.1446 - if (raw_x_1 == `TRUE) 22.1447 - bypass_data_1 = x_result; 22.1448 - else if (raw_m_1 == `TRUE) 22.1449 - bypass_data_1 = m_result; 22.1450 - else if (raw_w_1 == `TRUE) 22.1451 - bypass_data_1 = w_result; 22.1452 - else 22.1453 - bypass_data_1 = reg_data_1; 22.1454 -end 22.1455 - 22.1456 - /*---------------------------------------------------------------------- 22.1457 - Branch prediction is performed in D stage of pipeline. Only PC-relative 22.1458 - branches are predicted: forward-pointing conditional branches are not- 22.1459 - taken, while backward-pointing conditional branches are taken. 22.1460 - Unconditional branches are always predicted taken! 22.1461 - ----------------------------------------------------------------------*/ 22.1462 - assign branch_predict_d = bi_unconditional | bi_conditional; 22.1463 - assign branch_predict_taken_d = bi_unconditional ? 1'b1 : (bi_conditional ? instruction_d[15] : 1'b0); 22.1464 - 22.1465 - // Compute branch target address: Branch PC PLUS Offset 22.1466 - assign branch_target_d = pc_d + branch_offset_d; 22.1467 - 22.1468 - // Compute fetch address. Address of instruction sequentially after the 22.1469 - // branch if branch is not taken. Target address of branch is branch is 22.1470 - // taken 22.1471 - assign branch_predict_address_d = branch_predict_taken_d ? branch_target_d : pc_f; 22.1472 - 22.1473 -// D stage result selection 22.1474 -always @(*) 22.1475 -begin 22.1476 - d_result_0 = d_result_sel_0_d[0] ? {pc_f, 2'b00} : bypass_data_0; 22.1477 - case (d_result_sel_1_d) 22.1478 - `LM32_D_RESULT_SEL_1_ZERO: d_result_1 = {`LM32_WORD_WIDTH{1'b0}}; 22.1479 - `LM32_D_RESULT_SEL_1_REG_1: d_result_1 = bypass_data_1; 22.1480 - `LM32_D_RESULT_SEL_1_IMMEDIATE: d_result_1 = immediate_d; 22.1481 - default: d_result_1 = {`LM32_WORD_WIDTH{1'bx}}; 22.1482 - endcase 22.1483 -end 22.1484 - 22.1485 -`ifdef CFG_USER_ENABLED 22.1486 -// Operands for user-defined instructions 22.1487 -assign user_operand_0 = operand_0_x; 22.1488 -assign user_operand_1 = operand_1_x; 22.1489 -`endif 22.1490 - 22.1491 -`ifdef CFG_SIGN_EXTEND_ENABLED 22.1492 -// Sign-extension 22.1493 -assign sextb_result_x = {{24{operand_0_x[7]}}, operand_0_x[7:0]}; 22.1494 -assign sexth_result_x = {{16{operand_0_x[15]}}, operand_0_x[15:0]}; 22.1495 -assign sext_result_x = size_x == `LM32_SIZE_BYTE ? sextb_result_x : sexth_result_x; 22.1496 -`endif 22.1497 - 22.1498 -`ifdef LM32_NO_BARREL_SHIFT 22.1499 -// Only single bit shift operations are supported when barrel-shifter isn't implemented 22.1500 -assign shifter_result_x = {operand_0_x[`LM32_WORD_WIDTH-1] & sign_extend_x, operand_0_x[`LM32_WORD_WIDTH-1:1]}; 22.1501 -`endif 22.1502 - 22.1503 -// Condition evaluation 22.1504 -assign cmp_zero = operand_0_x == operand_1_x; 22.1505 -assign cmp_negative = adder_result_x[`LM32_WORD_WIDTH-1]; 22.1506 -assign cmp_overflow = adder_overflow_x; 22.1507 -assign cmp_carry_n = adder_carry_n_x; 22.1508 -always @(*) 22.1509 -begin 22.1510 - case (condition_x) 22.1511 - `LM32_CONDITION_U1: condition_met_x = `TRUE; 22.1512 - `LM32_CONDITION_U2: condition_met_x = `TRUE; 22.1513 - `LM32_CONDITION_E: condition_met_x = cmp_zero; 22.1514 - `LM32_CONDITION_NE: condition_met_x = !cmp_zero; 22.1515 - `LM32_CONDITION_G: condition_met_x = !cmp_zero && (cmp_negative == cmp_overflow); 22.1516 - `LM32_CONDITION_GU: condition_met_x = cmp_carry_n && !cmp_zero; 22.1517 - `LM32_CONDITION_GE: condition_met_x = cmp_negative == cmp_overflow; 22.1518 - `LM32_CONDITION_GEU: condition_met_x = cmp_carry_n; 22.1519 - default: condition_met_x = 1'bx; 22.1520 - endcase 22.1521 -end 22.1522 - 22.1523 -// X stage result selection 22.1524 -always @(*) 22.1525 -begin 22.1526 - x_result = x_result_sel_add_x ? adder_result_x 22.1527 - : x_result_sel_csr_x ? csr_read_data_x 22.1528 -`ifdef CFG_SIGN_EXTEND_ENABLED 22.1529 - : x_result_sel_sext_x ? sext_result_x 22.1530 -`endif 22.1531 -`ifdef CFG_USER_ENABLED 22.1532 - : x_result_sel_user_x ? user_result 22.1533 -`endif 22.1534 -`ifdef LM32_NO_BARREL_SHIFT 22.1535 - : x_result_sel_shift_x ? shifter_result_x 22.1536 -`endif 22.1537 -`ifdef LM32_MC_ARITHMETIC_ENABLED 22.1538 - : x_result_sel_mc_arith_x ? mc_result_x 22.1539 -`endif 22.1540 - : logic_result_x; 22.1541 -end 22.1542 - 22.1543 -// M stage result selection 22.1544 -always @(*) 22.1545 -begin 22.1546 - m_result = m_result_sel_compare_m ? {{`LM32_WORD_WIDTH-1{1'b0}}, condition_met_m} 22.1547 -`ifdef CFG_PL_BARREL_SHIFT_ENABLED 22.1548 - : m_result_sel_shift_m ? shifter_result_m 22.1549 -`endif 22.1550 - : operand_m; 22.1551 -end 22.1552 - 22.1553 -// W stage result selection 22.1554 -always @(*) 22.1555 -begin 22.1556 - w_result = w_result_sel_load_w ? load_data_w 22.1557 -`ifdef CFG_PL_MULTIPLY_ENABLED 22.1558 - : w_result_sel_mul_w ? multiplier_result_w 22.1559 -`endif 22.1560 - : operand_w; 22.1561 -end 22.1562 - 22.1563 -`ifdef CFG_FAST_UNCONDITIONAL_BRANCH 22.1564 -// Indicate when a branch should be taken in X stage 22.1565 -assign branch_taken_x = (stall_x == `FALSE) 22.1566 - && ( (branch_x == `TRUE) 22.1567 - && ((condition_x == `LM32_CONDITION_U1) || (condition_x == `LM32_CONDITION_U2)) 22.1568 - && (valid_x == `TRUE) 22.1569 - && (branch_predict_x == `FALSE) 22.1570 - ); 22.1571 -`endif 22.1572 - 22.1573 -// Indicate when a branch should be taken in M stage (exceptions are a type of branch) 22.1574 -assign branch_taken_m = (stall_m == `FALSE) 22.1575 - && ( ( (branch_m == `TRUE) 22.1576 - && (valid_m == `TRUE) 22.1577 - && ( ( (condition_met_m == `TRUE) 22.1578 - && (branch_predict_taken_m == `FALSE) 22.1579 - ) 22.1580 - || ( (condition_met_m == `FALSE) 22.1581 - && (branch_predict_m == `TRUE) 22.1582 - && (branch_predict_taken_m == `TRUE) 22.1583 - ) 22.1584 - ) 22.1585 - ) 22.1586 - || (exception_m == `TRUE) 22.1587 - ); 22.1588 - 22.1589 -// Indicate when a branch in M stage is mispredicted as being taken 22.1590 -assign branch_mispredict_taken_m = (condition_met_m == `FALSE) 22.1591 - && (branch_predict_m == `TRUE) 22.1592 - && (branch_predict_taken_m == `TRUE); 22.1593 - 22.1594 -// Indicate when a branch in M stage will cause flush in X stage 22.1595 -assign branch_flushX_m = (stall_m == `FALSE) 22.1596 - && ( ( (branch_m == `TRUE) 22.1597 - && (valid_m == `TRUE) 22.1598 - && ( (condition_met_m == `TRUE) 22.1599 - || ( (condition_met_m == `FALSE) 22.1600 - && (branch_predict_m == `TRUE) 22.1601 - && (branch_predict_taken_m == `TRUE) 22.1602 - ) 22.1603 - ) 22.1604 - ) 22.1605 - || (exception_m == `TRUE) 22.1606 - ); 22.1607 - 22.1608 -// Generate signal that will kill instructions in each pipeline stage when necessary 22.1609 -assign kill_f = ( (valid_d == `TRUE) 22.1610 - && (branch_predict_taken_d == `TRUE) 22.1611 - ) 22.1612 - || (branch_taken_m == `TRUE) 22.1613 -`ifdef CFG_FAST_UNCONDITIONAL_BRANCH 22.1614 - || (branch_taken_x == `TRUE) 22.1615 -`endif 22.1616 -`ifdef CFG_ICACHE_ENABLED 22.1617 - || (icache_refill_request == `TRUE) 22.1618 -`endif 22.1619 -`ifdef CFG_DCACHE_ENABLED 22.1620 - || (dcache_refill_request == `TRUE) 22.1621 -`endif 22.1622 - ; 22.1623 -assign kill_d = (branch_taken_m == `TRUE) 22.1624 -`ifdef CFG_FAST_UNCONDITIONAL_BRANCH 22.1625 - || (branch_taken_x == `TRUE) 22.1626 -`endif 22.1627 -`ifdef CFG_ICACHE_ENABLED 22.1628 - || (icache_refill_request == `TRUE) 22.1629 -`endif 22.1630 -`ifdef CFG_DCACHE_ENABLED 22.1631 - || (dcache_refill_request == `TRUE) 22.1632 -`endif 22.1633 - ; 22.1634 -assign kill_x = (branch_flushX_m == `TRUE) 22.1635 -`ifdef CFG_DCACHE_ENABLED 22.1636 - || (dcache_refill_request == `TRUE) 22.1637 -`endif 22.1638 - ; 22.1639 -assign kill_m = `FALSE 22.1640 -`ifdef CFG_DCACHE_ENABLED 22.1641 - || (dcache_refill_request == `TRUE) 22.1642 -`endif 22.1643 - ; 22.1644 -assign kill_w = `FALSE 22.1645 -`ifdef CFG_DCACHE_ENABLED 22.1646 - || (dcache_refill_request == `TRUE) 22.1647 -`endif 22.1648 - ; 22.1649 - 22.1650 -// Exceptions 22.1651 - 22.1652 -`ifdef CFG_DEBUG_ENABLED 22.1653 -assign breakpoint_exception = ( ( (break_x == `TRUE) 22.1654 - || (bp_match == `TRUE) 22.1655 - ) 22.1656 - && (valid_x == `TRUE) 22.1657 - ) 22.1658 -`ifdef CFG_JTAG_ENABLED 22.1659 - || (jtag_break == `TRUE) 22.1660 -`endif 22.1661 - ; 22.1662 -`endif 22.1663 - 22.1664 -`ifdef CFG_DEBUG_ENABLED 22.1665 -assign watchpoint_exception = wp_match == `TRUE; 22.1666 -`endif 22.1667 - 22.1668 -`ifdef CFG_BUS_ERRORS_ENABLED 22.1669 -assign instruction_bus_error_exception = ( (bus_error_x == `TRUE) 22.1670 - && (valid_x == `TRUE) 22.1671 - ); 22.1672 -assign data_bus_error_exception = data_bus_error_seen == `TRUE; 22.1673 -`endif 22.1674 - 22.1675 -`ifdef CFG_MC_DIVIDE_ENABLED 22.1676 -assign divide_by_zero_exception = divide_by_zero_x == `TRUE; 22.1677 -`endif 22.1678 - 22.1679 -assign system_call_exception = ( (scall_x == `TRUE) 22.1680 -`ifdef CFG_BUS_ERRORS_ENABLED 22.1681 - && (valid_x == `TRUE) 22.1682 -`endif 22.1683 - ); 22.1684 - 22.1685 -`ifdef CFG_DEBUG_ENABLED 22.1686 -assign debug_exception_x = (breakpoint_exception == `TRUE) 22.1687 - || (watchpoint_exception == `TRUE) 22.1688 - ; 22.1689 - 22.1690 -assign non_debug_exception_x = (system_call_exception == `TRUE) 22.1691 -`ifdef CFG_JTAG_ENABLED 22.1692 - || (reset_exception == `TRUE) 22.1693 -`endif 22.1694 -`ifdef CFG_BUS_ERRORS_ENABLED 22.1695 - || (instruction_bus_error_exception == `TRUE) 22.1696 - || (data_bus_error_exception == `TRUE) 22.1697 -`endif 22.1698 -`ifdef CFG_MC_DIVIDE_ENABLED 22.1699 - || (divide_by_zero_exception == `TRUE) 22.1700 -`endif 22.1701 -`ifdef CFG_INTERRUPTS_ENABLED 22.1702 - || ( (interrupt_exception == `TRUE) 22.1703 -`ifdef LM32_SINGLE_STEP_ENABLED 22.1704 - && (dc_ss == `FALSE) 22.1705 -`endif 22.1706 -`ifdef CFG_BUS_ERRORS_ENABLED 22.1707 - && (store_q_m == `FALSE) 22.1708 - && (D_CYC_O == `FALSE) 22.1709 -`endif 22.1710 - ) 22.1711 -`endif 22.1712 - ; 22.1713 - 22.1714 -assign exception_x = (debug_exception_x == `TRUE) || (non_debug_exception_x == `TRUE); 22.1715 -`else 22.1716 -assign exception_x = (system_call_exception == `TRUE) 22.1717 -`ifdef CFG_BUS_ERRORS_ENABLED 22.1718 - || (instruction_bus_error_exception == `TRUE) 22.1719 - || (data_bus_error_exception == `TRUE) 22.1720 -`endif 22.1721 -`ifdef CFG_MC_DIVIDE_ENABLED 22.1722 - || (divide_by_zero_exception == `TRUE) 22.1723 -`endif 22.1724 -`ifdef CFG_INTERRUPTS_ENABLED 22.1725 - || ( (interrupt_exception == `TRUE) 22.1726 -`ifdef LM32_SINGLE_STEP_ENABLED 22.1727 - && (dc_ss == `FALSE) 22.1728 -`endif 22.1729 -`ifdef CFG_BUS_ERRORS_ENABLED 22.1730 - && (store_q_m == `FALSE) 22.1731 - && (D_CYC_O == `FALSE) 22.1732 -`endif 22.1733 - ) 22.1734 -`endif 22.1735 - ; 22.1736 -`endif 22.1737 - 22.1738 -// Exception ID 22.1739 -always @(*) 22.1740 -begin 22.1741 -`ifdef CFG_DEBUG_ENABLED 22.1742 -`ifdef CFG_JTAG_ENABLED 22.1743 - if (reset_exception == `TRUE) 22.1744 - eid_x = `LM32_EID_RESET; 22.1745 - else 22.1746 -`endif 22.1747 -`ifdef CFG_BUS_ERRORS_ENABLED 22.1748 - if (data_bus_error_exception == `TRUE) 22.1749 - eid_x = `LM32_EID_DATA_BUS_ERROR; 22.1750 - else 22.1751 -`endif 22.1752 - if (breakpoint_exception == `TRUE) 22.1753 - eid_x = `LM32_EID_BREAKPOINT; 22.1754 - else 22.1755 -`endif 22.1756 -`ifdef CFG_BUS_ERRORS_ENABLED 22.1757 - if (data_bus_error_exception == `TRUE) 22.1758 - eid_x = `LM32_EID_DATA_BUS_ERROR; 22.1759 - else 22.1760 - if (instruction_bus_error_exception == `TRUE) 22.1761 - eid_x = `LM32_EID_INST_BUS_ERROR; 22.1762 - else 22.1763 -`endif 22.1764 -`ifdef CFG_DEBUG_ENABLED 22.1765 - if (watchpoint_exception == `TRUE) 22.1766 - eid_x = `LM32_EID_WATCHPOINT; 22.1767 - else 22.1768 -`endif 22.1769 -`ifdef CFG_MC_DIVIDE_ENABLED 22.1770 - if (divide_by_zero_exception == `TRUE) 22.1771 - eid_x = `LM32_EID_DIVIDE_BY_ZERO; 22.1772 - else 22.1773 -`endif 22.1774 -`ifdef CFG_INTERRUPTS_ENABLED 22.1775 - if ( (interrupt_exception == `TRUE) 22.1776 -`ifdef LM32_SINGLE_STEP_ENABLED 22.1777 - && (dc_ss == `FALSE) 22.1778 -`endif 22.1779 - ) 22.1780 - eid_x = `LM32_EID_INTERRUPT; 22.1781 - else 22.1782 -`endif 22.1783 - eid_x = `LM32_EID_SCALL; 22.1784 -end 22.1785 - 22.1786 -// Stall generation 22.1787 - 22.1788 -assign stall_a = (stall_f == `TRUE); 22.1789 - 22.1790 -assign stall_f = (stall_d == `TRUE); 22.1791 - 22.1792 -assign stall_d = (stall_x == `TRUE) 22.1793 - || ( (interlock == `TRUE) 22.1794 - && (kill_d == `FALSE) 22.1795 - ) 22.1796 - || ( ( (eret_d == `TRUE) 22.1797 - || (scall_d == `TRUE) 22.1798 -`ifdef CFG_BUS_ERRORS_ENABLED 22.1799 - || (bus_error_d == `TRUE) 22.1800 -`endif 22.1801 - ) 22.1802 - && ( (load_q_x == `TRUE) 22.1803 - || (load_q_m == `TRUE) 22.1804 - || (store_q_x == `TRUE) 22.1805 - || (store_q_m == `TRUE) 22.1806 - || (D_CYC_O == `TRUE) 22.1807 - ) 22.1808 - && (kill_d == `FALSE) 22.1809 - ) 22.1810 -`ifdef CFG_DEBUG_ENABLED 22.1811 - || ( ( (break_d == `TRUE) 22.1812 - || (bret_d == `TRUE) 22.1813 - ) 22.1814 - && ( (load_q_x == `TRUE) 22.1815 - || (store_q_x == `TRUE) 22.1816 - || (load_q_m == `TRUE) 22.1817 - || (store_q_m == `TRUE) 22.1818 - || (D_CYC_O == `TRUE) 22.1819 - ) 22.1820 - && (kill_d == `FALSE) 22.1821 - ) 22.1822 -`endif 22.1823 - || ( (csr_write_enable_d == `TRUE) 22.1824 - && (load_q_x == `TRUE) 22.1825 - ) 22.1826 - ; 22.1827 - 22.1828 -assign stall_x = (stall_m == `TRUE) 22.1829 -`ifdef LM32_MC_ARITHMETIC_ENABLED 22.1830 - || ( (mc_stall_request_x == `TRUE) 22.1831 - && (kill_x == `FALSE) 22.1832 - ) 22.1833 -`endif 22.1834 -`ifdef CFG_IROM_ENABLED 22.1835 - // Stall load/store instruction in D stage if there is an ongoing store 22.1836 - // operation to instruction ROM in M stage 22.1837 - || ( (irom_stall_request_x == `TRUE) 22.1838 - && ( (load_d == `TRUE) 22.1839 - || (store_d == `TRUE) 22.1840 - ) 22.1841 - ) 22.1842 -`endif 22.1843 - ; 22.1844 - 22.1845 -assign stall_m = (stall_wb_load == `TRUE) 22.1846 -`ifdef CFG_SIZE_OVER_SPEED 22.1847 - || (D_CYC_O == `TRUE) 22.1848 -`else 22.1849 - || ( (D_CYC_O == `TRUE) 22.1850 - && ( (store_m == `TRUE) 22.1851 - /* 22.1852 - Bug: Following loop does not allow interrupts to be services since 22.1853 - either D_CYC_O or store_m is always high during entire duration of 22.1854 - loop. 22.1855 - L1: addi r1, r1, 1 22.1856 - sw (r2,0), r1 22.1857 - bi L1 22.1858 - 22.1859 - Introduce a single-cycle stall when a wishbone cycle is in progress 22.1860 - and a new store instruction is in Execute stage and a interrupt 22.1861 - exception has occured. This stall will ensure that D_CYC_O and 22.1862 - store_m will both be low for one cycle. 22.1863 - */ 22.1864 -`ifdef CFG_INTERRUPTS_ENABLED 22.1865 - || ((store_x == `TRUE) && (interrupt_exception == `TRUE)) 22.1866 -`endif 22.1867 - || (load_m == `TRUE) 22.1868 - || (load_x == `TRUE) 22.1869 - ) 22.1870 - ) 22.1871 -`endif 22.1872 -`ifdef CFG_DCACHE_ENABLED 22.1873 - || (dcache_stall_request == `TRUE) // Need to stall in case a taken branch is in M stage and data cache is only being flush, so wont be restarted 22.1874 -`endif 22.1875 -`ifdef CFG_ICACHE_ENABLED 22.1876 - || (icache_stall_request == `TRUE) // Pipeline needs to be stalled otherwise branches may be lost 22.1877 - || ((I_CYC_O == `TRUE) && ((branch_m == `TRUE) || (exception_m == `TRUE))) 22.1878 -`else 22.1879 -`ifdef CFG_IWB_ENABLED 22.1880 - || (I_CYC_O == `TRUE) 22.1881 -`endif 22.1882 -`endif 22.1883 -`ifdef CFG_USER_ENABLED 22.1884 - || ( (user_valid == `TRUE) // Stall whole pipeline, rather than just X stage, where the instruction is, so we don't have to worry about exceptions (maybe) 22.1885 - && (user_complete == `FALSE) 22.1886 - ) 22.1887 -`endif 22.1888 - ; 22.1889 - 22.1890 -// Qualify state changing control signals 22.1891 -`ifdef LM32_MC_ARITHMETIC_ENABLED 22.1892 -assign q_d = (valid_d == `TRUE) && (kill_d == `FALSE); 22.1893 -`endif 22.1894 -`ifdef CFG_MC_BARREL_SHIFT_ENABLED 22.1895 -assign shift_left_q_d = (shift_left_d == `TRUE) && (q_d == `TRUE); 22.1896 -assign shift_right_q_d = (shift_right_d == `TRUE) && (q_d == `TRUE); 22.1897 -`endif 22.1898 -`ifdef CFG_MC_MULTIPLY_ENABLED 22.1899 -assign multiply_q_d = (multiply_d == `TRUE) && (q_d == `TRUE); 22.1900 -`endif 22.1901 -`ifdef CFG_MC_DIVIDE_ENABLED 22.1902 -assign divide_q_d = (divide_d == `TRUE) && (q_d == `TRUE); 22.1903 -assign modulus_q_d = (modulus_d == `TRUE) && (q_d == `TRUE); 22.1904 -`endif 22.1905 -assign q_x = (valid_x == `TRUE) && (kill_x == `FALSE); 22.1906 -assign csr_write_enable_q_x = (csr_write_enable_x == `TRUE) && (q_x == `TRUE); 22.1907 -assign eret_q_x = (eret_x == `TRUE) && (q_x == `TRUE); 22.1908 -`ifdef CFG_DEBUG_ENABLED 22.1909 -assign bret_q_x = (bret_x == `TRUE) && (q_x == `TRUE); 22.1910 -`endif 22.1911 -assign load_q_x = (load_x == `TRUE) 22.1912 - && (q_x == `TRUE) 22.1913 -`ifdef CFG_DEBUG_ENABLED 22.1914 - && (bp_match == `FALSE) 22.1915 -`endif 22.1916 - ; 22.1917 -assign store_q_x = (store_x == `TRUE) 22.1918 - && (q_x == `TRUE) 22.1919 -`ifdef CFG_DEBUG_ENABLED 22.1920 - && (bp_match == `FALSE) 22.1921 -`endif 22.1922 - ; 22.1923 -`ifdef CFG_USER_ENABLED 22.1924 -assign user_valid = (x_result_sel_user_x == `TRUE) && (q_x == `TRUE); 22.1925 -`endif 22.1926 -assign q_m = (valid_m == `TRUE) && (kill_m == `FALSE) && (exception_m == `FALSE); 22.1927 -assign load_q_m = (load_m == `TRUE) && (q_m == `TRUE); 22.1928 -assign store_q_m = (store_m == `TRUE) && (q_m == `TRUE); 22.1929 -`ifdef CFG_DEBUG_ENABLED 22.1930 -assign debug_exception_q_w = ((debug_exception_w == `TRUE) && (valid_w == `TRUE)); 22.1931 -assign non_debug_exception_q_w = ((non_debug_exception_w == `TRUE) && (valid_w == `TRUE)); 22.1932 -`else 22.1933 -assign exception_q_w = ((exception_w == `TRUE) && (valid_w == `TRUE)); 22.1934 -`endif 22.1935 -// Don't qualify register write enables with kill, as the signal is needed early, and it doesn't matter if the instruction is killed (except for the actual write - but that is handled separately) 22.1936 -assign write_enable_q_x = (write_enable_x == `TRUE) && (valid_x == `TRUE) && (branch_flushX_m == `FALSE); 22.1937 -assign write_enable_q_m = (write_enable_m == `TRUE) && (valid_m == `TRUE); 22.1938 -assign write_enable_q_w = (write_enable_w == `TRUE) && (valid_w == `TRUE); 22.1939 -// The enable that actually does write the registers needs to be qualified with kill 22.1940 -assign reg_write_enable_q_w = (write_enable_w == `TRUE) && (kill_w == `FALSE) && (valid_w == `TRUE); 22.1941 - 22.1942 -// Configuration (CFG) CSR 22.1943 -assign cfg = { 22.1944 - `LM32_REVISION, 22.1945 - watchpoints[3:0], 22.1946 - breakpoints[3:0], 22.1947 - interrupts[5:0], 22.1948 -`ifdef CFG_JTAG_UART_ENABLED 22.1949 - `TRUE, 22.1950 -`else 22.1951 - `FALSE, 22.1952 -`endif 22.1953 -`ifdef CFG_ROM_DEBUG_ENABLED 22.1954 - `TRUE, 22.1955 -`else 22.1956 - `FALSE, 22.1957 -`endif 22.1958 -`ifdef CFG_HW_DEBUG_ENABLED 22.1959 - `TRUE, 22.1960 -`else 22.1961 - `FALSE, 22.1962 -`endif 22.1963 -`ifdef CFG_DEBUG_ENABLED 22.1964 - `TRUE, 22.1965 -`else 22.1966 - `FALSE, 22.1967 -`endif 22.1968 -`ifdef CFG_ICACHE_ENABLED 22.1969 - `TRUE, 22.1970 -`else 22.1971 - `FALSE, 22.1972 -`endif 22.1973 -`ifdef CFG_DCACHE_ENABLED 22.1974 - `TRUE, 22.1975 -`else 22.1976 - `FALSE, 22.1977 -`endif 22.1978 -`ifdef CFG_CYCLE_COUNTER_ENABLED 22.1979 - `TRUE, 22.1980 -`else 22.1981 - `FALSE, 22.1982 -`endif 22.1983 -`ifdef CFG_USER_ENABLED 22.1984 - `TRUE, 22.1985 -`else 22.1986 - `FALSE, 22.1987 -`endif 22.1988 -`ifdef CFG_SIGN_EXTEND_ENABLED 22.1989 - `TRUE, 22.1990 -`else 22.1991 - `FALSE, 22.1992 -`endif 22.1993 -`ifdef LM32_BARREL_SHIFT_ENABLED 22.1994 - `TRUE, 22.1995 -`else 22.1996 - `FALSE, 22.1997 -`endif 22.1998 -`ifdef CFG_MC_DIVIDE_ENABLED 22.1999 - `TRUE, 22.2000 -`else 22.2001 - `FALSE, 22.2002 -`endif 22.2003 -`ifdef LM32_MULTIPLY_ENABLED 22.2004 - `TRUE 22.2005 -`else 22.2006 - `FALSE 22.2007 -`endif 22.2008 - }; 22.2009 - 22.2010 -assign cfg2 = { 22.2011 - 30'b0, 22.2012 -`ifdef CFG_IROM_ENABLED 22.2013 - `TRUE, 22.2014 -`else 22.2015 - `FALSE, 22.2016 -`endif 22.2017 -`ifdef CFG_DRAM_ENABLED 22.2018 - `TRUE 22.2019 -`else 22.2020 - `FALSE 22.2021 -`endif 22.2022 - }; 22.2023 - 22.2024 -// Cache flush 22.2025 -`ifdef CFG_ICACHE_ENABLED 22.2026 -assign iflush = ( (csr_write_enable_d == `TRUE) 22.2027 - && (csr_d == `LM32_CSR_ICC) 22.2028 - && (stall_d == `FALSE) 22.2029 - && (kill_d == `FALSE) 22.2030 - && (valid_d == `TRUE)) 22.2031 -// Added by GSI: needed to flush cache after loading firmware per JTAG 22.2032 -`ifdef CFG_HW_DEBUG_ENABLED 22.2033 - || 22.2034 - ( (jtag_csr_write_enable == `TRUE) 22.2035 - && (jtag_csr == `LM32_CSR_ICC)) 22.2036 -`endif 22.2037 - ; 22.2038 -`endif 22.2039 -`ifdef CFG_DCACHE_ENABLED 22.2040 -assign dflush_x = ( (csr_write_enable_q_x == `TRUE) 22.2041 - && (csr_x == `LM32_CSR_DCC)) 22.2042 -// Added by GSI: needed to flush cache after loading firmware per JTAG 22.2043 -`ifdef CFG_HW_DEBUG_ENABLED 22.2044 - || 22.2045 - ( (jtag_csr_write_enable == `TRUE) 22.2046 - && (jtag_csr == `LM32_CSR_DCC)) 22.2047 -`endif 22.2048 - ; 22.2049 -`endif 22.2050 - 22.2051 -// Extract CSR index 22.2052 -assign csr_d = read_idx_0_d[`LM32_CSR_RNG]; 22.2053 - 22.2054 -// CSR reads 22.2055 -always @(*) 22.2056 -begin 22.2057 - case (csr_x) 22.2058 -`ifdef CFG_INTERRUPTS_ENABLED 22.2059 - `LM32_CSR_IE, 22.2060 - `LM32_CSR_IM, 22.2061 - `LM32_CSR_IP: csr_read_data_x = interrupt_csr_read_data_x; 22.2062 -`endif 22.2063 -`ifdef CFG_CYCLE_COUNTER_ENABLED 22.2064 - `LM32_CSR_CC: csr_read_data_x = cc; 22.2065 -`endif 22.2066 - `LM32_CSR_CFG: csr_read_data_x = cfg; 22.2067 - `LM32_CSR_EBA: csr_read_data_x = {eba, 8'h00}; 22.2068 -`ifdef CFG_DEBUG_ENABLED 22.2069 - `LM32_CSR_DEBA: csr_read_data_x = {deba, 8'h00}; 22.2070 -`endif 22.2071 -`ifdef CFG_JTAG_UART_ENABLED 22.2072 - `LM32_CSR_JTX: csr_read_data_x = jtx_csr_read_data; 22.2073 - `LM32_CSR_JRX: csr_read_data_x = jrx_csr_read_data; 22.2074 -`endif 22.2075 - `LM32_CSR_CFG2: csr_read_data_x = cfg2; 22.2076 - 22.2077 - default: csr_read_data_x = {`LM32_WORD_WIDTH{1'bx}}; 22.2078 - endcase 22.2079 -end 22.2080 - 22.2081 -///////////////////////////////////////////////////// 22.2082 -// Sequential Logic 22.2083 -///////////////////////////////////////////////////// 22.2084 - 22.2085 -// Exception Base Address (EBA) CSR 22.2086 -always @(posedge clk_i `CFG_RESET_SENSITIVITY) 22.2087 -begin 22.2088 - if (rst_i == `TRUE) 22.2089 - eba <= eba_reset[`LM32_PC_WIDTH+2-1:8]; 22.2090 - else 22.2091 - begin 22.2092 - if ((csr_write_enable_q_x == `TRUE) && (csr_x == `LM32_CSR_EBA) && (stall_x == `FALSE)) 22.2093 - eba <= operand_1_x[`LM32_PC_WIDTH+2-1:8]; 22.2094 -`ifdef CFG_HW_DEBUG_ENABLED 22.2095 - if ((jtag_csr_write_enable == `TRUE) && (jtag_csr == `LM32_CSR_EBA)) 22.2096 - eba <= jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8]; 22.2097 -`endif 22.2098 - end 22.2099 -end 22.2100 - 22.2101 -`ifdef CFG_DEBUG_ENABLED 22.2102 -// Debug Exception Base Address (DEBA) CSR 22.2103 -always @(posedge clk_i `CFG_RESET_SENSITIVITY) 22.2104 -begin 22.2105 - if (rst_i == `TRUE) 22.2106 - deba <= deba_reset[`LM32_PC_WIDTH+2-1:8]; 22.2107 - else 22.2108 - begin 22.2109 - if ((csr_write_enable_q_x == `TRUE) && (csr_x == `LM32_CSR_DEBA) && (stall_x == `FALSE)) 22.2110 - deba <= operand_1_x[`LM32_PC_WIDTH+2-1:8]; 22.2111 -`ifdef CFG_HW_DEBUG_ENABLED 22.2112 - if ((jtag_csr_write_enable == `TRUE) && (jtag_csr == `LM32_CSR_DEBA)) 22.2113 - deba <= jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8]; 22.2114 -`endif 22.2115 - end 22.2116 -end 22.2117 -`endif 22.2118 - 22.2119 -// Cycle Counter (CC) CSR 22.2120 -`ifdef CFG_CYCLE_COUNTER_ENABLED 22.2121 -always @(posedge clk_i `CFG_RESET_SENSITIVITY) 22.2122 -begin 22.2123 - if (rst_i == `TRUE) 22.2124 - cc <= {`LM32_WORD_WIDTH{1'b0}}; 22.2125 - else 22.2126 - cc <= cc + 1'b1; 22.2127 -end 22.2128 -`endif 22.2129 - 22.2130 -`ifdef CFG_BUS_ERRORS_ENABLED 22.2131 -// Watch for data bus errors 22.2132 -always @(posedge clk_i `CFG_RESET_SENSITIVITY) 22.2133 -begin 22.2134 - if (rst_i == `TRUE) 22.2135 - data_bus_error_seen <= `FALSE; 22.2136 - else 22.2137 - begin 22.2138 - // Set flag when bus error is detected 22.2139 - if ((D_ERR_I == `TRUE) && (D_CYC_O == `TRUE)) 22.2140 - data_bus_error_seen <= `TRUE; 22.2141 - // Clear flag when exception is taken 22.2142 - if ((exception_m == `TRUE) && (kill_m == `FALSE)) 22.2143 - data_bus_error_seen <= `FALSE; 22.2144 - end 22.2145 -end 22.2146 -`endif 22.2147 - 22.2148 -// Valid bits to indicate whether an instruction in a partcular pipeline stage is valid or not 22.2149 - 22.2150 -`ifdef CFG_ICACHE_ENABLED 22.2151 -`ifdef CFG_DCACHE_ENABLED 22.2152 -always @(*) 22.2153 -begin 22.2154 - if ( (icache_refill_request == `TRUE) 22.2155 - || (dcache_refill_request == `TRUE) 22.2156 - ) 22.2157 - valid_a = `FALSE; 22.2158 - else if ( (icache_restart_request == `TRUE) 22.2159 - || (dcache_restart_request == `TRUE) 22.2160 - ) 22.2161 - valid_a = `TRUE; 22.2162 - else 22.2163 - valid_a = !icache_refilling && !dcache_refilling; 22.2164 -end 22.2165 -`else 22.2166 -always @(*) 22.2167 -begin 22.2168 - if (icache_refill_request == `TRUE) 22.2169 - valid_a = `FALSE; 22.2170 - else if (icache_restart_request == `TRUE) 22.2171 - valid_a = `TRUE; 22.2172 - else 22.2173 - valid_a = !icache_refilling; 22.2174 -end 22.2175 -`endif 22.2176 -`else 22.2177 -`ifdef CFG_DCACHE_ENABLED 22.2178 -always @(*) 22.2179 -begin 22.2180 - if (dcache_refill_request == `TRUE) 22.2181 - valid_a = `FALSE; 22.2182 - else if (dcache_restart_request == `TRUE) 22.2183 - valid_a = `TRUE; 22.2184 - else 22.2185 - valid_a = !dcache_refilling; 22.2186 -end 22.2187 -`endif 22.2188 -`endif 22.2189 - 22.2190 -always @(posedge clk_i `CFG_RESET_SENSITIVITY) 22.2191 -begin 22.2192 - if (rst_i == `TRUE) 22.2193 - begin 22.2194 - valid_f <= `FALSE; 22.2195 - valid_d <= `FALSE; 22.2196 - valid_x <= `FALSE; 22.2197 - valid_m <= `FALSE; 22.2198 - valid_w <= `FALSE; 22.2199 - end 22.2200 - else 22.2201 - begin 22.2202 - if ((kill_f == `TRUE) || (stall_a == `FALSE)) 22.2203 -`ifdef LM32_CACHE_ENABLED 22.2204 - valid_f <= valid_a; 22.2205 -`else 22.2206 - valid_f <= `TRUE; 22.2207 -`endif 22.2208 - else if (stall_f == `FALSE) 22.2209 - valid_f <= `FALSE; 22.2210 - 22.2211 - if (kill_d == `TRUE) 22.2212 - valid_d <= `FALSE; 22.2213 - else if (stall_f == `FALSE) 22.2214 - valid_d <= valid_f & !kill_f; 22.2215 - else if (stall_d == `FALSE) 22.2216 - valid_d <= `FALSE; 22.2217 - 22.2218 - if (stall_d == `FALSE) 22.2219 - valid_x <= valid_d & !kill_d; 22.2220 - else if (kill_x == `TRUE) 22.2221 - valid_x <= `FALSE; 22.2222 - else if (stall_x == `FALSE) 22.2223 - valid_x <= `FALSE; 22.2224 - 22.2225 - if (kill_m == `TRUE) 22.2226 - valid_m <= `FALSE; 22.2227 - else if (stall_x == `FALSE) 22.2228 - valid_m <= valid_x & !kill_x; 22.2229 - else if (stall_m == `FALSE) 22.2230 - valid_m <= `FALSE; 22.2231 - 22.2232 - if (stall_m == `FALSE) 22.2233 - valid_w <= valid_m & !kill_m; 22.2234 - else 22.2235 - valid_w <= `FALSE; 22.2236 - end 22.2237 -end 22.2238 - 22.2239 -// Microcode pipeline registers 22.2240 -always @(posedge clk_i `CFG_RESET_SENSITIVITY) 22.2241 -begin 22.2242 - if (rst_i == `TRUE) 22.2243 - begin 22.2244 -`ifdef CFG_USER_ENABLED 22.2245 - user_opcode <= {`LM32_USER_OPCODE_WIDTH{1'b0}}; 22.2246 -`endif 22.2247 - operand_0_x <= {`LM32_WORD_WIDTH{1'b0}}; 22.2248 - operand_1_x <= {`LM32_WORD_WIDTH{1'b0}}; 22.2249 - store_operand_x <= {`LM32_WORD_WIDTH{1'b0}}; 22.2250 - branch_target_x <= {`LM32_PC_WIDTH{1'b0}}; 22.2251 - x_result_sel_csr_x <= `FALSE; 22.2252 -`ifdef LM32_MC_ARITHMETIC_ENABLED 22.2253 - x_result_sel_mc_arith_x <= `FALSE; 22.2254 -`endif 22.2255 -`ifdef LM32_NO_BARREL_SHIFT 22.2256 - x_result_sel_shift_x <= `FALSE; 22.2257 -`endif 22.2258 -`ifdef CFG_SIGN_EXTEND_ENABLED 22.2259 - x_result_sel_sext_x <= `FALSE; 22.2260 -`endif 22.2261 - x_result_sel_logic_x <= `FALSE; 22.2262 -`ifdef CFG_USER_ENABLED 22.2263 - x_result_sel_user_x <= `FALSE; 22.2264 -`endif 22.2265 - x_result_sel_add_x <= `FALSE; 22.2266 - m_result_sel_compare_x <= `FALSE; 22.2267 -`ifdef CFG_PL_BARREL_SHIFT_ENABLED 22.2268 - m_result_sel_shift_x <= `FALSE; 22.2269 -`endif 22.2270 - w_result_sel_load_x <= `FALSE; 22.2271 -`ifdef CFG_PL_MULTIPLY_ENABLED 22.2272 - w_result_sel_mul_x <= `FALSE; 22.2273 -`endif 22.2274 - x_bypass_enable_x <= `FALSE; 22.2275 - m_bypass_enable_x <= `FALSE; 22.2276 - write_enable_x <= `FALSE; 22.2277 - write_idx_x <= {`LM32_REG_IDX_WIDTH{1'b0}}; 22.2278 - csr_x <= {`LM32_CSR_WIDTH{1'b0}}; 22.2279 - load_x <= `FALSE; 22.2280 - store_x <= `FALSE; 22.2281 - size_x <= {`LM32_SIZE_WIDTH{1'b0}}; 22.2282 - sign_extend_x <= `FALSE; 22.2283 - adder_op_x <= `FALSE; 22.2284 - adder_op_x_n <= `FALSE; 22.2285 - logic_op_x <= 4'h0; 22.2286 -`ifdef CFG_PL_BARREL_SHIFT_ENABLED 22.2287 - direction_x <= `FALSE; 22.2288 -`endif 22.2289 -`ifdef CFG_ROTATE_ENABLED 22.2290 - rotate_x <= `FALSE; 22.2291 - 22.2292 -`endif 22.2293 - branch_x <= `FALSE; 22.2294 - branch_predict_x <= `FALSE; 22.2295 - branch_predict_taken_x <= `FALSE; 22.2296 - condition_x <= `LM32_CONDITION_U1; 22.2297 -`ifdef CFG_DEBUG_ENABLED 22.2298 - break_x <= `FALSE; 22.2299 -`endif 22.2300 - scall_x <= `FALSE; 22.2301 - eret_x <= `FALSE; 22.2302 -`ifdef CFG_DEBUG_ENABLED 22.2303 - bret_x <= `FALSE; 22.2304 -`endif 22.2305 -`ifdef CFG_BUS_ERRORS_ENABLED 22.2306 - bus_error_x <= `FALSE; 22.2307 - data_bus_error_exception_m <= `FALSE; 22.2308 -`endif 22.2309 - csr_write_enable_x <= `FALSE; 22.2310 - operand_m <= {`LM32_WORD_WIDTH{1'b0}}; 22.2311 - branch_target_m <= {`LM32_PC_WIDTH{1'b0}}; 22.2312 - m_result_sel_compare_m <= `FALSE; 22.2313 -`ifdef CFG_PL_BARREL_SHIFT_ENABLED 22.2314 - m_result_sel_shift_m <= `FALSE; 22.2315 -`endif 22.2316 - w_result_sel_load_m <= `FALSE; 22.2317 -`ifdef CFG_PL_MULTIPLY_ENABLED 22.2318 - w_result_sel_mul_m <= `FALSE; 22.2319 -`endif 22.2320 - m_bypass_enable_m <= `FALSE; 22.2321 - branch_m <= `FALSE; 22.2322 - branch_predict_m <= `FALSE; 22.2323 - branch_predict_taken_m <= `FALSE; 22.2324 - exception_m <= `FALSE; 22.2325 - load_m <= `FALSE; 22.2326 - store_m <= `FALSE; 22.2327 - write_enable_m <= `FALSE; 22.2328 - write_idx_m <= {`LM32_REG_IDX_WIDTH{1'b0}}; 22.2329 - condition_met_m <= `FALSE; 22.2330 -`ifdef CFG_DCACHE_ENABLED 22.2331 - dflush_m <= `FALSE; 22.2332 -`endif 22.2333 -`ifdef CFG_DEBUG_ENABLED 22.2334 - debug_exception_m <= `FALSE; 22.2335 - non_debug_exception_m <= `FALSE; 22.2336 -`endif 22.2337 - operand_w <= {`LM32_WORD_WIDTH{1'b0}}; 22.2338 - w_result_sel_load_w <= `FALSE; 22.2339 -`ifdef CFG_PL_MULTIPLY_ENABLED 22.2340 - w_result_sel_mul_w <= `FALSE; 22.2341 -`endif 22.2342 - write_idx_w <= {`LM32_REG_IDX_WIDTH{1'b0}}; 22.2343 - write_enable_w <= `FALSE; 22.2344 -`ifdef CFG_DEBUG_ENABLED 22.2345 - debug_exception_w <= `FALSE; 22.2346 - non_debug_exception_w <= `FALSE; 22.2347 -`else 22.2348 - exception_w <= `FALSE; 22.2349 -`endif 22.2350 -`ifdef CFG_BUS_ERRORS_ENABLED 22.2351 - memop_pc_w <= {`LM32_PC_WIDTH{1'b0}}; 22.2352 -`endif 22.2353 - end 22.2354 - else 22.2355 - begin 22.2356 - // D/X stage registers 22.2357 - 22.2358 - if (stall_x == `FALSE) 22.2359 - begin 22.2360 -`ifdef CFG_USER_ENABLED 22.2361 - user_opcode <= user_opcode_d; 22.2362 -`endif 22.2363 - operand_0_x <= d_result_0; 22.2364 - operand_1_x <= d_result_1; 22.2365 - store_operand_x <= bypass_data_1; 22.2366 - branch_target_x <= branch_reg_d == `TRUE ? bypass_data_0[`LM32_PC_RNG] : branch_target_d; 22.2367 - x_result_sel_csr_x <= x_result_sel_csr_d; 22.2368 -`ifdef LM32_MC_ARITHMETIC_ENABLED 22.2369 - x_result_sel_mc_arith_x <= x_result_sel_mc_arith_d; 22.2370 -`endif 22.2371 -`ifdef LM32_NO_BARREL_SHIFT 22.2372 - x_result_sel_shift_x <= x_result_sel_shift_d; 22.2373 -`endif 22.2374 -`ifdef CFG_SIGN_EXTEND_ENABLED 22.2375 - x_result_sel_sext_x <= x_result_sel_sext_d; 22.2376 -`endif 22.2377 - x_result_sel_logic_x <= x_result_sel_logic_d; 22.2378 -`ifdef CFG_USER_ENABLED 22.2379 - x_result_sel_user_x <= x_result_sel_user_d; 22.2380 -`endif 22.2381 - x_result_sel_add_x <= x_result_sel_add_d; 22.2382 - m_result_sel_compare_x <= m_result_sel_compare_d; 22.2383 -`ifdef CFG_PL_BARREL_SHIFT_ENABLED 22.2384 - m_result_sel_shift_x <= m_result_sel_shift_d; 22.2385 -`endif 22.2386 - w_result_sel_load_x <= w_result_sel_load_d; 22.2387 -`ifdef CFG_PL_MULTIPLY_ENABLED 22.2388 - w_result_sel_mul_x <= w_result_sel_mul_d; 22.2389 -`endif 22.2390 - x_bypass_enable_x <= x_bypass_enable_d; 22.2391 - m_bypass_enable_x <= m_bypass_enable_d; 22.2392 - load_x <= load_d; 22.2393 - store_x <= store_d; 22.2394 - branch_x <= branch_d; 22.2395 - branch_predict_x <= branch_predict_d; 22.2396 - branch_predict_taken_x <= branch_predict_taken_d; 22.2397 - write_idx_x <= write_idx_d; 22.2398 - csr_x <= csr_d; 22.2399 - size_x <= size_d; 22.2400 - sign_extend_x <= sign_extend_d; 22.2401 - adder_op_x <= adder_op_d; 22.2402 - adder_op_x_n <= ~adder_op_d; 22.2403 - logic_op_x <= logic_op_d; 22.2404 -`ifdef CFG_PL_BARREL_SHIFT_ENABLED 22.2405 - direction_x <= direction_d; 22.2406 -`endif 22.2407 -`ifdef CFG_ROTATE_ENABLED 22.2408 - rotate_x <= rotate_d; 22.2409 -`endif 22.2410 - condition_x <= condition_d; 22.2411 - csr_write_enable_x <= csr_write_enable_d; 22.2412 -`ifdef CFG_DEBUG_ENABLED 22.2413 - break_x <= break_d; 22.2414 -`endif 22.2415 - scall_x <= scall_d; 22.2416 -`ifdef CFG_BUS_ERRORS_ENABLED 22.2417 - bus_error_x <= bus_error_d; 22.2418 -`endif 22.2419 - eret_x <= eret_d; 22.2420 -`ifdef CFG_DEBUG_ENABLED 22.2421 - bret_x <= bret_d; 22.2422 -`endif 22.2423 - write_enable_x <= write_enable_d; 22.2424 - end 22.2425 - 22.2426 - // X/M stage registers 22.2427 - 22.2428 - if (stall_m == `FALSE) 22.2429 - begin 22.2430 - operand_m <= x_result; 22.2431 - m_result_sel_compare_m <= m_result_sel_compare_x; 22.2432 -`ifdef CFG_PL_BARREL_SHIFT_ENABLED 22.2433 - m_result_sel_shift_m <= m_result_sel_shift_x; 22.2434 -`endif 22.2435 - if (exception_x == `TRUE) 22.2436 - begin 22.2437 - w_result_sel_load_m <= `FALSE; 22.2438 -`ifdef CFG_PL_MULTIPLY_ENABLED 22.2439 - w_result_sel_mul_m <= `FALSE; 22.2440 -`endif 22.2441 - end 22.2442 - else 22.2443 - begin 22.2444 - w_result_sel_load_m <= w_result_sel_load_x; 22.2445 -`ifdef CFG_PL_MULTIPLY_ENABLED 22.2446 - w_result_sel_mul_m <= w_result_sel_mul_x; 22.2447 -`endif 22.2448 - end 22.2449 - m_bypass_enable_m <= m_bypass_enable_x; 22.2450 -`ifdef CFG_PL_BARREL_SHIFT_ENABLED 22.2451 -`endif 22.2452 - load_m <= load_x; 22.2453 - store_m <= store_x; 22.2454 -`ifdef CFG_FAST_UNCONDITIONAL_BRANCH 22.2455 - branch_m <= branch_x && !branch_taken_x; 22.2456 -`else 22.2457 - branch_m <= branch_x; 22.2458 - branch_predict_m <= branch_predict_x; 22.2459 - branch_predict_taken_m <= branch_predict_taken_x; 22.2460 -`endif 22.2461 -`ifdef CFG_DEBUG_ENABLED 22.2462 - // Data bus errors are generated by the wishbone and are 22.2463 - // made known to the processor only in next cycle (as a 22.2464 - // non-debug exception). A break instruction can be seen 22.2465 - // in same cycle (causing a debug exception). Handle non 22.2466 - // -debug exception first! 22.2467 - if (non_debug_exception_x == `TRUE) 22.2468 - write_idx_m <= `LM32_EA_REG; 22.2469 - else if (debug_exception_x == `TRUE) 22.2470 - write_idx_m <= `LM32_BA_REG; 22.2471 - else 22.2472 - write_idx_m <= write_idx_x; 22.2473 -`else 22.2474 - if (exception_x == `TRUE) 22.2475 - write_idx_m <= `LM32_EA_REG; 22.2476 - else 22.2477 - write_idx_m <= write_idx_x; 22.2478 -`endif 22.2479 - condition_met_m <= condition_met_x; 22.2480 -`ifdef CFG_DEBUG_ENABLED 22.2481 - if (exception_x == `TRUE) 22.2482 - if ((dc_re == `TRUE) 22.2483 - || ((debug_exception_x == `TRUE) 22.2484 - && (non_debug_exception_x == `FALSE))) 22.2485 - branch_target_m <= {deba, eid_x, {3{1'b0}}}; 22.2486 - else 22.2487 - branch_target_m <= {eba, eid_x, {3{1'b0}}}; 22.2488 - else 22.2489 - branch_target_m <= branch_target_x; 22.2490 -`else 22.2491 - branch_target_m <= exception_x == `TRUE ? {eba, eid_x, {3{1'b0}}} : branch_target_x; 22.2492 -`endif 22.2493 -`ifdef CFG_TRACE_ENABLED 22.2494 - eid_m <= eid_x; 22.2495 -`endif 22.2496 -`ifdef CFG_DCACHE_ENABLED 22.2497 - dflush_m <= dflush_x; 22.2498 -`endif 22.2499 - eret_m <= eret_q_x; 22.2500 -`ifdef CFG_DEBUG_ENABLED 22.2501 - bret_m <= bret_q_x; 22.2502 -`endif 22.2503 - write_enable_m <= exception_x == `TRUE ? `TRUE : write_enable_x; 22.2504 -`ifdef CFG_DEBUG_ENABLED 22.2505 - debug_exception_m <= debug_exception_x; 22.2506 - non_debug_exception_m <= non_debug_exception_x; 22.2507 -`endif 22.2508 - end 22.2509 - 22.2510 - // State changing regs 22.2511 - if (stall_m == `FALSE) 22.2512 - begin 22.2513 - if ((exception_x == `TRUE) && (q_x == `TRUE) && (stall_x == `FALSE)) 22.2514 - exception_m <= `TRUE; 22.2515 - else 22.2516 - exception_m <= `FALSE; 22.2517 -`ifdef CFG_BUS_ERRORS_ENABLED 22.2518 - data_bus_error_exception_m <= (data_bus_error_exception == `TRUE) 22.2519 -`ifdef CFG_DEBUG_ENABLED 22.2520 - && (reset_exception == `FALSE) 22.2521 -`endif 22.2522 - ; 22.2523 -`endif 22.2524 - end 22.2525 - 22.2526 - // M/W stage registers 22.2527 -`ifdef CFG_BUS_ERRORS_ENABLED 22.2528 - operand_w <= exception_m == `TRUE ? (data_bus_error_exception_m ? {memop_pc_w, 2'b00} : {pc_m, 2'b00}) : m_result; 22.2529 -`else 22.2530 - operand_w <= exception_m == `TRUE ? {pc_m, 2'b00} : m_result; 22.2531 -`endif 22.2532 - w_result_sel_load_w <= w_result_sel_load_m; 22.2533 -`ifdef CFG_PL_MULTIPLY_ENABLED 22.2534 - w_result_sel_mul_w <= w_result_sel_mul_m; 22.2535 -`endif 22.2536 - write_idx_w <= write_idx_m; 22.2537 -`ifdef CFG_TRACE_ENABLED 22.2538 - eid_w <= eid_m; 22.2539 - eret_w <= eret_m; 22.2540 -`ifdef CFG_DEBUG_ENABLED 22.2541 - bret_w <= bret_m; 22.2542 -`endif 22.2543 -`endif 22.2544 - write_enable_w <= write_enable_m; 22.2545 -`ifdef CFG_DEBUG_ENABLED 22.2546 - debug_exception_w <= debug_exception_m; 22.2547 - non_debug_exception_w <= non_debug_exception_m; 22.2548 -`else 22.2549 - exception_w <= exception_m; 22.2550 -`endif 22.2551 -`ifdef CFG_BUS_ERRORS_ENABLED 22.2552 - if ( (stall_m == `FALSE) 22.2553 - && ( (load_q_m == `TRUE) 22.2554 - || (store_q_m == `TRUE) 22.2555 - ) 22.2556 - ) 22.2557 - memop_pc_w <= pc_m; 22.2558 -`endif 22.2559 - end 22.2560 -end 22.2561 - 22.2562 -`ifdef CFG_EBR_POSEDGE_REGISTER_FILE 22.2563 -// Buffer data read from register file, in case a stall occurs, and watch for 22.2564 -// any writes to the modified registers 22.2565 -always @(posedge clk_i `CFG_RESET_SENSITIVITY) 22.2566 -begin 22.2567 - if (rst_i == `TRUE) 22.2568 - begin 22.2569 - use_buf <= `FALSE; 22.2570 - reg_data_buf_0 <= {`LM32_WORD_WIDTH{1'b0}}; 22.2571 - reg_data_buf_1 <= {`LM32_WORD_WIDTH{1'b0}}; 22.2572 - end 22.2573 - else 22.2574 - begin 22.2575 - if (stall_d == `FALSE) 22.2576 - use_buf <= `FALSE; 22.2577 - else if (use_buf == `FALSE) 22.2578 - begin 22.2579 - reg_data_buf_0 <= reg_data_live_0; 22.2580 - reg_data_buf_1 <= reg_data_live_1; 22.2581 - use_buf <= `TRUE; 22.2582 - end 22.2583 - if (reg_write_enable_q_w == `TRUE) 22.2584 - begin 22.2585 - if (write_idx_w == read_idx_0_d) 22.2586 - reg_data_buf_0 <= w_result; 22.2587 - if (write_idx_w == read_idx_1_d) 22.2588 - reg_data_buf_1 <= w_result; 22.2589 - end 22.2590 - end 22.2591 -end 22.2592 -`endif 22.2593 - 22.2594 -`ifdef LM32_EBR_REGISTER_FILE 22.2595 -`else 22.2596 -// Register file write port 22.2597 -always @(posedge clk_i `CFG_RESET_SENSITIVITY) 22.2598 -begin 22.2599 - if (rst_i == `TRUE) begin 22.2600 - registers[0] <= {`LM32_WORD_WIDTH{1'b0}}; 22.2601 - registers[1] <= {`LM32_WORD_WIDTH{1'b0}}; 22.2602 - registers[2] <= {`LM32_WORD_WIDTH{1'b0}}; 22.2603 - registers[3] <= {`LM32_WORD_WIDTH{1'b0}}; 22.2604 - registers[4] <= {`LM32_WORD_WIDTH{1'b0}}; 22.2605 - registers[5] <= {`LM32_WORD_WIDTH{1'b0}}; 22.2606 - registers[6] <= {`LM32_WORD_WIDTH{1'b0}}; 22.2607 - registers[7] <= {`LM32_WORD_WIDTH{1'b0}}; 22.2608 - registers[8] <= {`LM32_WORD_WIDTH{1'b0}}; 22.2609 - registers[9] <= {`LM32_WORD_WIDTH{1'b0}}; 22.2610 - registers[10] <= {`LM32_WORD_WIDTH{1'b0}}; 22.2611 - registers[11] <= {`LM32_WORD_WIDTH{1'b0}}; 22.2612 - registers[12] <= {`LM32_WORD_WIDTH{1'b0}}; 22.2613 - registers[13] <= {`LM32_WORD_WIDTH{1'b0}}; 22.2614 - registers[14] <= {`LM32_WORD_WIDTH{1'b0}}; 22.2615 - registers[15] <= {`LM32_WORD_WIDTH{1'b0}}; 22.2616 - registers[16] <= {`LM32_WORD_WIDTH{1'b0}}; 22.2617 - registers[17] <= {`LM32_WORD_WIDTH{1'b0}}; 22.2618 - registers[18] <= {`LM32_WORD_WIDTH{1'b0}}; 22.2619 - registers[19] <= {`LM32_WORD_WIDTH{1'b0}}; 22.2620 - registers[20] <= {`LM32_WORD_WIDTH{1'b0}}; 22.2621 - registers[21] <= {`LM32_WORD_WIDTH{1'b0}}; 22.2622 - registers[22] <= {`LM32_WORD_WIDTH{1'b0}}; 22.2623 - registers[23] <= {`LM32_WORD_WIDTH{1'b0}}; 22.2624 - registers[24] <= {`LM32_WORD_WIDTH{1'b0}}; 22.2625 - registers[25] <= {`LM32_WORD_WIDTH{1'b0}}; 22.2626 - registers[26] <= {`LM32_WORD_WIDTH{1'b0}}; 22.2627 - registers[27] <= {`LM32_WORD_WIDTH{1'b0}}; 22.2628 - registers[28] <= {`LM32_WORD_WIDTH{1'b0}}; 22.2629 - registers[29] <= {`LM32_WORD_WIDTH{1'b0}}; 22.2630 - registers[30] <= {`LM32_WORD_WIDTH{1'b0}}; 22.2631 - registers[31] <= {`LM32_WORD_WIDTH{1'b0}}; 22.2632 - end 22.2633 - else begin 22.2634 - if (reg_write_enable_q_w == `TRUE) 22.2635 - registers[write_idx_w] <= w_result; 22.2636 - end 22.2637 -end 22.2638 -`endif 22.2639 - 22.2640 -`ifdef CFG_TRACE_ENABLED 22.2641 -// PC tracing logic 22.2642 -always @(posedge clk_i `CFG_RESET_SENSITIVITY) 22.2643 -begin 22.2644 - if (rst_i == `TRUE) 22.2645 - begin 22.2646 - trace_pc_valid <= `FALSE; 22.2647 - trace_pc <= {`LM32_PC_WIDTH{1'b0}}; 22.2648 - trace_exception <= `FALSE; 22.2649 - trace_eid <= `LM32_EID_RESET; 22.2650 - trace_eret <= `FALSE; 22.2651 -`ifdef CFG_DEBUG_ENABLED 22.2652 - trace_bret <= `FALSE; 22.2653 -`endif 22.2654 - pc_c <= `CFG_EBA_RESET/4; 22.2655 - end 22.2656 - else 22.2657 - begin 22.2658 - trace_pc_valid <= `FALSE; 22.2659 - // Has an exception occured 22.2660 -`ifdef CFG_DEBUG_ENABLED 22.2661 - if ((debug_exception_q_w == `TRUE) || (non_debug_exception_q_w == `TRUE)) 22.2662 -`else 22.2663 - if (exception_q_w == `TRUE) 22.2664 -`endif 22.2665 - begin 22.2666 - trace_exception <= `TRUE; 22.2667 - trace_pc_valid <= `TRUE; 22.2668 - trace_pc <= pc_w; 22.2669 - trace_eid <= eid_w; 22.2670 - end 22.2671 - else 22.2672 - trace_exception <= `FALSE; 22.2673 - 22.2674 - if ((valid_w == `TRUE) && (!kill_w)) 22.2675 - begin 22.2676 - // An instruction is commiting. Determine if it is non-sequential 22.2677 - if (pc_c + 1'b1 != pc_w) 22.2678 - begin 22.2679 - // Non-sequential instruction 22.2680 - trace_pc_valid <= `TRUE; 22.2681 - trace_pc <= pc_w; 22.2682 - end 22.2683 - // Record PC so we can determine if next instruction is sequential or not 22.2684 - pc_c <= pc_w; 22.2685 - // Indicate if it was an eret/bret instruction 22.2686 - trace_eret <= eret_w; 22.2687 -`ifdef CFG_DEBUG_ENABLED 22.2688 - trace_bret <= bret_w; 22.2689 -`endif 22.2690 - end 22.2691 - else 22.2692 - begin 22.2693 - trace_eret <= `FALSE; 22.2694 -`ifdef CFG_DEBUG_ENABLED 22.2695 - trace_bret <= `FALSE; 22.2696 -`endif 22.2697 - end 22.2698 - end 22.2699 -end 22.2700 -`endif 22.2701 - 22.2702 -///////////////////////////////////////////////////// 22.2703 -// Behavioural Logic 22.2704 -///////////////////////////////////////////////////// 22.2705 - 22.2706 -// synthesis translate_off 22.2707 - 22.2708 -// Reset register 0. Only needed for simulation. 22.2709 -initial 22.2710 -begin 22.2711 -`ifdef LM32_EBR_REGISTER_FILE 22.2712 - reg_0.mem[0] = {`LM32_WORD_WIDTH{1'b0}}; 22.2713 - reg_1.mem[0] = {`LM32_WORD_WIDTH{1'b0}}; 22.2714 -`else 22.2715 - registers[0] = {`LM32_WORD_WIDTH{1'b0}}; 22.2716 -`endif 22.2717 -end 22.2718 - 22.2719 -// synthesis translate_on 22.2720 - 22.2721 -endmodule
23.1 diff -r 252df75c8f67 -r c336e674a37e lm32_dcache.v 23.2 --- a/lm32_dcache.v Sun Mar 06 21:17:31 2011 +0000 23.3 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 23.4 @@ -1,542 +0,0 @@ 23.5 -// ============================================================================= 23.6 -// COPYRIGHT NOTICE 23.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 23.8 -// ALL RIGHTS RESERVED 23.9 -// This confidential and proprietary software may be used only as authorised by 23.10 -// a licensing agreement from Lattice Semiconductor Corporation. 23.11 -// The entire notice above must be reproduced on all authorized copies and 23.12 -// copies may only be made to the extent permitted by a licensing agreement from 23.13 -// Lattice Semiconductor Corporation. 23.14 -// 23.15 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 23.16 -// 5555 NE Moore Court 408-826-6000 (other locations) 23.17 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 23.18 -// U.S.A email: techsupport@latticesemi.com 23.19 -// =============================================================================/ 23.20 -// FILE DETAILS 23.21 -// Project : LatticeMico32 23.22 -// File : lm32_dcache.v 23.23 -// Title : Data cache 23.24 -// Dependencies : lm32_include.v 23.25 -// Version : 6.1.17 23.26 -// : Initial Release 23.27 -// Version : 7.0SP2, 3.0 23.28 -// : No Change 23.29 -// Version : 3.1 23.30 -// : Support for user-selected resource usage when implementing 23.31 -// : cache memory. Additional parameters must be defined when 23.32 -// : invoking lm32_ram.v 23.33 -// ============================================================================= 23.34 - 23.35 -`include "lm32_include.v" 23.36 - 23.37 -`ifdef CFG_DCACHE_ENABLED 23.38 - 23.39 -`define LM32_DC_ADDR_OFFSET_RNG addr_offset_msb:addr_offset_lsb 23.40 -`define LM32_DC_ADDR_SET_RNG addr_set_msb:addr_set_lsb 23.41 -`define LM32_DC_ADDR_TAG_RNG addr_tag_msb:addr_tag_lsb 23.42 -`define LM32_DC_ADDR_IDX_RNG addr_set_msb:addr_offset_lsb 23.43 - 23.44 -`define LM32_DC_TMEM_ADDR_WIDTH addr_set_width 23.45 -`define LM32_DC_TMEM_ADDR_RNG (`LM32_DC_TMEM_ADDR_WIDTH-1):0 23.46 -`define LM32_DC_DMEM_ADDR_WIDTH (addr_offset_width+addr_set_width) 23.47 -`define LM32_DC_DMEM_ADDR_RNG (`LM32_DC_DMEM_ADDR_WIDTH-1):0 23.48 - 23.49 -`define LM32_DC_TAGS_WIDTH (addr_tag_width+1) 23.50 -`define LM32_DC_TAGS_RNG (`LM32_DC_TAGS_WIDTH-1):0 23.51 -`define LM32_DC_TAGS_TAG_RNG (`LM32_DC_TAGS_WIDTH-1):1 23.52 -`define LM32_DC_TAGS_VALID_RNG 0 23.53 - 23.54 -`define LM32_DC_STATE_RNG 2:0 23.55 -`define LM32_DC_STATE_FLUSH 3'b001 23.56 -`define LM32_DC_STATE_CHECK 3'b010 23.57 -`define LM32_DC_STATE_REFILL 3'b100 23.58 - 23.59 -///////////////////////////////////////////////////// 23.60 -// Module interface 23.61 -///////////////////////////////////////////////////// 23.62 - 23.63 -module lm32_dcache ( 23.64 - // ----- Inputs ----- 23.65 - clk_i, 23.66 - rst_i, 23.67 - stall_a, 23.68 - stall_x, 23.69 - stall_m, 23.70 - address_x, 23.71 - address_m, 23.72 - load_q_m, 23.73 - store_q_m, 23.74 - store_data, 23.75 - store_byte_select, 23.76 - refill_ready, 23.77 - refill_data, 23.78 - dflush, 23.79 - // ----- Outputs ----- 23.80 - stall_request, 23.81 - restart_request, 23.82 - refill_request, 23.83 - refill_address, 23.84 - refilling, 23.85 - load_data 23.86 - ); 23.87 - 23.88 -///////////////////////////////////////////////////// 23.89 -// Parameters 23.90 -///////////////////////////////////////////////////// 23.91 - 23.92 -parameter associativity = 1; // Associativity of the cache (Number of ways) 23.93 -parameter sets = 512; // Number of sets 23.94 -parameter bytes_per_line = 16; // Number of bytes per cache line 23.95 -parameter base_address = 0; // Base address of cachable memory 23.96 -parameter limit = 0; // Limit (highest address) of cachable memory 23.97 - 23.98 -localparam addr_offset_width = clogb2(bytes_per_line)-1-2; 23.99 -localparam addr_set_width = clogb2(sets)-1; 23.100 -localparam addr_offset_lsb = 2; 23.101 -localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1); 23.102 -localparam addr_set_lsb = (addr_offset_msb+1); 23.103 -localparam addr_set_msb = (addr_set_lsb+addr_set_width-1); 23.104 -localparam addr_tag_lsb = (addr_set_msb+1); 23.105 -localparam addr_tag_msb = clogb2(`CFG_DCACHE_LIMIT-`CFG_DCACHE_BASE_ADDRESS)-1; 23.106 -localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1); 23.107 - 23.108 -///////////////////////////////////////////////////// 23.109 -// Inputs 23.110 -///////////////////////////////////////////////////// 23.111 - 23.112 -input clk_i; // Clock 23.113 -input rst_i; // Reset 23.114 - 23.115 -input stall_a; // Stall A stage 23.116 -input stall_x; // Stall X stage 23.117 -input stall_m; // Stall M stage 23.118 - 23.119 -input [`LM32_WORD_RNG] address_x; // X stage load/store address 23.120 -input [`LM32_WORD_RNG] address_m; // M stage load/store address 23.121 -input load_q_m; // Load instruction in M stage 23.122 -input store_q_m; // Store instruction in M stage 23.123 -input [`LM32_WORD_RNG] store_data; // Data to store 23.124 -input [`LM32_BYTE_SELECT_RNG] store_byte_select; // Which bytes in store data should be modified 23.125 - 23.126 -input refill_ready; // Indicates next word of refill data is ready 23.127 -input [`LM32_WORD_RNG] refill_data; // Refill data 23.128 - 23.129 -input dflush; // Indicates cache should be flushed 23.130 - 23.131 -///////////////////////////////////////////////////// 23.132 -// Outputs 23.133 -///////////////////////////////////////////////////// 23.134 - 23.135 -output stall_request; // Request pipeline be stalled because cache is busy 23.136 -wire stall_request; 23.137 -output restart_request; // Request to restart instruction that caused the cache miss 23.138 -reg restart_request; 23.139 -output refill_request; // Request a refill 23.140 -reg refill_request; 23.141 -output [`LM32_WORD_RNG] refill_address; // Address to refill from 23.142 -reg [`LM32_WORD_RNG] refill_address; 23.143 -output refilling; // Indicates if the cache is currently refilling 23.144 -reg refilling; 23.145 -output [`LM32_WORD_RNG] load_data; // Data read from cache 23.146 -wire [`LM32_WORD_RNG] load_data; 23.147 - 23.148 -///////////////////////////////////////////////////// 23.149 -// Internal nets and registers 23.150 -///////////////////////////////////////////////////// 23.151 - 23.152 -wire read_port_enable; // Cache memory read port clock enable 23.153 -wire write_port_enable; // Cache memory write port clock enable 23.154 -wire [0:associativity-1] way_tmem_we; // Tag memory write enable 23.155 -wire [0:associativity-1] way_dmem_we; // Data memory write enable 23.156 -wire [`LM32_WORD_RNG] way_data[0:associativity-1]; // Data read from data memory 23.157 -wire [`LM32_DC_TAGS_TAG_RNG] way_tag[0:associativity-1];// Tag read from tag memory 23.158 -wire [0:associativity-1] way_valid; // Indicates which ways are valid 23.159 -wire [0:associativity-1] way_match; // Indicates which ways matched 23.160 -wire miss; // Indicates no ways matched 23.161 - 23.162 -wire [`LM32_DC_TMEM_ADDR_RNG] tmem_read_address; // Tag memory read address 23.163 -wire [`LM32_DC_TMEM_ADDR_RNG] tmem_write_address; // Tag memory write address 23.164 -wire [`LM32_DC_DMEM_ADDR_RNG] dmem_read_address; // Data memory read address 23.165 -wire [`LM32_DC_DMEM_ADDR_RNG] dmem_write_address; // Data memory write address 23.166 -wire [`LM32_DC_TAGS_RNG] tmem_write_data; // Tag memory write data 23.167 -reg [`LM32_WORD_RNG] dmem_write_data; // Data memory write data 23.168 - 23.169 -reg [`LM32_DC_STATE_RNG] state; // Current state of FSM 23.170 -wire flushing; // Indicates if cache is currently flushing 23.171 -wire check; // Indicates if cache is currently checking for hits/misses 23.172 -wire refill; // Indicates if cache is currently refilling 23.173 - 23.174 -wire valid_store; // Indicates if there is a valid store instruction 23.175 -reg [associativity-1:0] refill_way_select; // Which way should be refilled 23.176 -reg [`LM32_DC_ADDR_OFFSET_RNG] refill_offset; // Which word in cache line should be refilled 23.177 -wire last_refill; // Indicates when on last cycle of cache refill 23.178 -reg [`LM32_DC_TMEM_ADDR_RNG] flush_set; // Which set is currently being flushed 23.179 - 23.180 -genvar i, j; 23.181 - 23.182 -///////////////////////////////////////////////////// 23.183 -// Functions 23.184 -///////////////////////////////////////////////////// 23.185 - 23.186 -`include "lm32_functions.v" 23.187 - 23.188 -///////////////////////////////////////////////////// 23.189 -// Instantiations 23.190 -///////////////////////////////////////////////////// 23.191 - 23.192 - generate 23.193 - for (i = 0; i < associativity; i = i + 1) 23.194 - begin : memories 23.195 - // Way data 23.196 - if (`LM32_DC_DMEM_ADDR_WIDTH < 11) 23.197 - begin : data_memories 23.198 - lm32_ram 23.199 - #( 23.200 - // ----- Parameters ------- 23.201 - .data_width (32), 23.202 - .address_width (`LM32_DC_DMEM_ADDR_WIDTH) 23.203 -`ifdef PLATFORM_LATTICE 23.204 - , 23.205 - `ifdef CFG_DCACHE_DAT_USE_DP_TRUE 23.206 - .RAM_IMPLEMENTATION ("EBR"), 23.207 - .RAM_TYPE ("RAM_DP_TRUE") 23.208 - `else 23.209 - `ifdef CFG_DCACHE_DAT_USE_SLICE 23.210 - .RAM_IMPLEMENTATION ("SLICE") 23.211 - `else 23.212 - .RAM_IMPLEMENTATION ("AUTO") 23.213 - `endif 23.214 - `endif 23.215 -`endif 23.216 - ) way_0_data_ram 23.217 - ( 23.218 - // ----- Inputs ------- 23.219 - .read_clk (clk_i), 23.220 - .write_clk (clk_i), 23.221 - .reset (rst_i), 23.222 - .read_address (dmem_read_address), 23.223 - .enable_read (read_port_enable), 23.224 - .write_address (dmem_write_address), 23.225 - .enable_write (write_port_enable), 23.226 - .write_enable (way_dmem_we[i]), 23.227 - .write_data (dmem_write_data), 23.228 - // ----- Outputs ------- 23.229 - .read_data (way_data[i]) 23.230 - ); 23.231 - end 23.232 - else 23.233 - begin 23.234 - for (j = 0; j < 4; j = j + 1) 23.235 - begin : byte_memories 23.236 - lm32_ram 23.237 - #( 23.238 - // ----- Parameters ------- 23.239 - .data_width (8), 23.240 - .address_width (`LM32_DC_DMEM_ADDR_WIDTH) 23.241 -`ifdef PLATFORM_LATTICE 23.242 - , 23.243 - `ifdef CFG_DCACHE_DAT_USE_DP_TRUE 23.244 - .RAM_IMPLEMENTATION ("EBR"), 23.245 - .RAM_TYPE ("RAM_DP_TRUE") 23.246 - `else 23.247 - `ifdef CFG_DCACHE_DAT_USE_SLICE 23.248 - .RAM_IMPLEMENTATION ("SLICE") 23.249 - `else 23.250 - .RAM_IMPLEMENTATION ("AUTO") 23.251 - `endif 23.252 - `endif 23.253 -`endif 23.254 - ) way_0_data_ram 23.255 - ( 23.256 - // ----- Inputs ------- 23.257 - .read_clk (clk_i), 23.258 - .write_clk (clk_i), 23.259 - .reset (rst_i), 23.260 - .read_address (dmem_read_address), 23.261 - .enable_read (read_port_enable), 23.262 - .write_address (dmem_write_address), 23.263 - .enable_write (write_port_enable), 23.264 - .write_enable (way_dmem_we[i] & (store_byte_select[j] | refill)), 23.265 - .write_data (dmem_write_data[(j+1)*8-1:j*8]), 23.266 - // ----- Outputs ------- 23.267 - .read_data (way_data[i][(j+1)*8-1:j*8]) 23.268 - ); 23.269 - end 23.270 - end 23.271 - 23.272 - // Way tags 23.273 - lm32_ram 23.274 - #( 23.275 - // ----- Parameters ------- 23.276 - .data_width (`LM32_DC_TAGS_WIDTH), 23.277 - .address_width (`LM32_DC_TMEM_ADDR_WIDTH) 23.278 -`ifdef PLATFORM_LATTICE 23.279 - , 23.280 - `ifdef CFG_DCACHE_DAT_USE_DP_TRUE 23.281 - .RAM_IMPLEMENTATION ("EBR"), 23.282 - .RAM_TYPE ("RAM_DP_TRUE") 23.283 - `else 23.284 - `ifdef CFG_DCACHE_DAT_USE_SLICE 23.285 - .RAM_IMPLEMENTATION ("SLICE") 23.286 - `else 23.287 - .RAM_IMPLEMENTATION ("AUTO") 23.288 - `endif 23.289 - `endif 23.290 -`endif 23.291 - ) way_0_tag_ram 23.292 - ( 23.293 - // ----- Inputs ------- 23.294 - .read_clk (clk_i), 23.295 - .write_clk (clk_i), 23.296 - .reset (rst_i), 23.297 - .read_address (tmem_read_address), 23.298 - .enable_read (read_port_enable), 23.299 - .write_address (tmem_write_address), 23.300 - .enable_write (`TRUE), 23.301 - .write_enable (way_tmem_we[i]), 23.302 - .write_data (tmem_write_data), 23.303 - // ----- Outputs ------- 23.304 - .read_data ({way_tag[i], way_valid[i]}) 23.305 - ); 23.306 - end 23.307 - 23.308 - endgenerate 23.309 - 23.310 -///////////////////////////////////////////////////// 23.311 -// Combinational logic 23.312 -///////////////////////////////////////////////////// 23.313 - 23.314 -// Compute which ways in the cache match the address being read 23.315 -generate 23.316 - for (i = 0; i < associativity; i = i + 1) 23.317 - begin : match 23.318 -assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_m[`LM32_DC_ADDR_TAG_RNG], `TRUE}); 23.319 - end 23.320 -endgenerate 23.321 - 23.322 -// Select data from way that matched the address being read 23.323 -generate 23.324 - if (associativity == 1) 23.325 - begin : data_1 23.326 -assign load_data = way_data[0]; 23.327 - end 23.328 - else if (associativity == 2) 23.329 - begin : data_2 23.330 -assign load_data = way_match[0] ? way_data[0] : way_data[1]; 23.331 - end 23.332 -endgenerate 23.333 - 23.334 -generate 23.335 - if (`LM32_DC_DMEM_ADDR_WIDTH < 11) 23.336 - begin 23.337 -// Select data to write to data memories 23.338 -always @(*) 23.339 -begin 23.340 - if (refill == `TRUE) 23.341 - dmem_write_data = refill_data; 23.342 - else 23.343 - begin 23.344 - dmem_write_data[`LM32_BYTE_0_RNG] = store_byte_select[0] ? store_data[`LM32_BYTE_0_RNG] : load_data[`LM32_BYTE_0_RNG]; 23.345 - dmem_write_data[`LM32_BYTE_1_RNG] = store_byte_select[1] ? store_data[`LM32_BYTE_1_RNG] : load_data[`LM32_BYTE_1_RNG]; 23.346 - dmem_write_data[`LM32_BYTE_2_RNG] = store_byte_select[2] ? store_data[`LM32_BYTE_2_RNG] : load_data[`LM32_BYTE_2_RNG]; 23.347 - dmem_write_data[`LM32_BYTE_3_RNG] = store_byte_select[3] ? store_data[`LM32_BYTE_3_RNG] : load_data[`LM32_BYTE_3_RNG]; 23.348 - end 23.349 -end 23.350 - end 23.351 - else 23.352 - begin 23.353 -// Select data to write to data memories - FIXME: Should use different write ports on dual port RAMs, but they don't work 23.354 -always @(*) 23.355 -begin 23.356 - if (refill == `TRUE) 23.357 - dmem_write_data = refill_data; 23.358 - else 23.359 - dmem_write_data = store_data; 23.360 -end 23.361 - end 23.362 -endgenerate 23.363 - 23.364 -// Compute address to use to index into the data memories 23.365 -generate 23.366 - if (bytes_per_line > 4) 23.367 -assign dmem_write_address = (refill == `TRUE) 23.368 - ? {refill_address[`LM32_DC_ADDR_SET_RNG], refill_offset} 23.369 - : address_m[`LM32_DC_ADDR_IDX_RNG]; 23.370 - else 23.371 -assign dmem_write_address = (refill == `TRUE) 23.372 - ? refill_address[`LM32_DC_ADDR_SET_RNG] 23.373 - : address_m[`LM32_DC_ADDR_IDX_RNG]; 23.374 -endgenerate 23.375 -assign dmem_read_address = address_x[`LM32_DC_ADDR_IDX_RNG]; 23.376 -// Compute address to use to index into the tag memories 23.377 -assign tmem_write_address = (flushing == `TRUE) 23.378 - ? flush_set 23.379 - : refill_address[`LM32_DC_ADDR_SET_RNG]; 23.380 -assign tmem_read_address = address_x[`LM32_DC_ADDR_SET_RNG]; 23.381 - 23.382 -// Compute signal to indicate when we are on the last refill accesses 23.383 -generate 23.384 - if (bytes_per_line > 4) 23.385 -assign last_refill = refill_offset == {addr_offset_width{1'b1}}; 23.386 - else 23.387 -assign last_refill = `TRUE; 23.388 -endgenerate 23.389 - 23.390 -// Compute data and tag memory access enable 23.391 -assign read_port_enable = (stall_x == `FALSE); 23.392 -assign write_port_enable = (refill_ready == `TRUE) || !stall_m; 23.393 - 23.394 -// Determine when we have a valid store 23.395 -assign valid_store = (store_q_m == `TRUE) && (check == `TRUE); 23.396 - 23.397 -// Compute data and tag memory write enables 23.398 -generate 23.399 - if (associativity == 1) 23.400 - begin : we_1 23.401 -assign way_dmem_we[0] = (refill_ready == `TRUE) || ((valid_store == `TRUE) && (way_match[0] == `TRUE)); 23.402 -assign way_tmem_we[0] = (refill_ready == `TRUE) || (flushing == `TRUE); 23.403 - end 23.404 - else 23.405 - begin : we_2 23.406 -assign way_dmem_we[0] = ((refill_ready == `TRUE) && (refill_way_select[0] == `TRUE)) || ((valid_store == `TRUE) && (way_match[0] == `TRUE)); 23.407 -assign way_dmem_we[1] = ((refill_ready == `TRUE) && (refill_way_select[1] == `TRUE)) || ((valid_store == `TRUE) && (way_match[1] == `TRUE)); 23.408 -assign way_tmem_we[0] = ((refill_ready == `TRUE) && (refill_way_select[0] == `TRUE)) || (flushing == `TRUE); 23.409 -assign way_tmem_we[1] = ((refill_ready == `TRUE) && (refill_way_select[1] == `TRUE)) || (flushing == `TRUE); 23.410 - end 23.411 -endgenerate 23.412 - 23.413 -// On the last refill cycle set the valid bit, for all other writes it should be cleared 23.414 -assign tmem_write_data[`LM32_DC_TAGS_VALID_RNG] = ((last_refill == `TRUE) || (valid_store == `TRUE)) && (flushing == `FALSE); 23.415 -assign tmem_write_data[`LM32_DC_TAGS_TAG_RNG] = refill_address[`LM32_DC_ADDR_TAG_RNG]; 23.416 - 23.417 -// Signals that indicate which state we are in 23.418 -assign flushing = state[0]; 23.419 -assign check = state[1]; 23.420 -assign refill = state[2]; 23.421 - 23.422 -assign miss = (~(|way_match)) && (load_q_m == `TRUE) && (stall_m == `FALSE); 23.423 -assign stall_request = (check == `FALSE); 23.424 - 23.425 -///////////////////////////////////////////////////// 23.426 -// Sequential logic 23.427 -///////////////////////////////////////////////////// 23.428 - 23.429 -// Record way selected for replacement on a cache miss 23.430 -generate 23.431 - if (associativity >= 2) 23.432 - begin : way_select 23.433 -always @(posedge clk_i `CFG_RESET_SENSITIVITY) 23.434 -begin 23.435 - if (rst_i == `TRUE) 23.436 - refill_way_select <= {{associativity-1{1'b0}}, 1'b1}; 23.437 - else 23.438 - begin 23.439 - if (refill_request == `TRUE) 23.440 - refill_way_select <= {refill_way_select[0], refill_way_select[1]}; 23.441 - end 23.442 -end 23.443 - end 23.444 -endgenerate 23.445 - 23.446 -// Record whether we are currently refilling 23.447 -always @(posedge clk_i `CFG_RESET_SENSITIVITY) 23.448 -begin 23.449 - if (rst_i == `TRUE) 23.450 - refilling <= `FALSE; 23.451 - else 23.452 - refilling <= refill; 23.453 -end 23.454 - 23.455 -// Instruction cache control FSM 23.456 -always @(posedge clk_i `CFG_RESET_SENSITIVITY) 23.457 -begin 23.458 - if (rst_i == `TRUE) 23.459 - begin 23.460 - state <= `LM32_DC_STATE_FLUSH; 23.461 - flush_set <= {`LM32_DC_TMEM_ADDR_WIDTH{1'b1}}; 23.462 - refill_request <= `FALSE; 23.463 - refill_address <= {`LM32_WORD_WIDTH{1'bx}}; 23.464 - restart_request <= `FALSE; 23.465 - end 23.466 - else 23.467 - begin 23.468 - case (state) 23.469 - 23.470 - // Flush the cache 23.471 - `LM32_DC_STATE_FLUSH: 23.472 - begin 23.473 - if (flush_set == {`LM32_DC_TMEM_ADDR_WIDTH{1'b0}}) 23.474 - state <= `LM32_DC_STATE_CHECK; 23.475 - flush_set <= flush_set - 1'b1; 23.476 - end 23.477 - 23.478 - // Check for cache misses 23.479 - `LM32_DC_STATE_CHECK: 23.480 - begin 23.481 - if (stall_a == `FALSE) 23.482 - restart_request <= `FALSE; 23.483 - if (miss == `TRUE) 23.484 - begin 23.485 - refill_request <= `TRUE; 23.486 - refill_address <= address_m; 23.487 - state <= `LM32_DC_STATE_REFILL; 23.488 - end 23.489 - else if (dflush == `TRUE) 23.490 - state <= `LM32_DC_STATE_FLUSH; 23.491 - end 23.492 - 23.493 - // Refill a cache line 23.494 - `LM32_DC_STATE_REFILL: 23.495 - begin 23.496 - refill_request <= `FALSE; 23.497 - if (refill_ready == `TRUE) 23.498 - begin 23.499 - if (last_refill == `TRUE) 23.500 - begin 23.501 - restart_request <= `TRUE; 23.502 - state <= `LM32_DC_STATE_CHECK; 23.503 - end 23.504 - end 23.505 - end 23.506 - 23.507 - endcase 23.508 - end 23.509 -end 23.510 - 23.511 -generate 23.512 - if (bytes_per_line > 4) 23.513 - begin 23.514 -// Refill offset 23.515 -always @(posedge clk_i `CFG_RESET_SENSITIVITY) 23.516 -begin 23.517 - if (rst_i == `TRUE) 23.518 - refill_offset <= {addr_offset_width{1'b0}}; 23.519 - else 23.520 - begin 23.521 - case (state) 23.522 - 23.523 - // Check for cache misses 23.524 - `LM32_DC_STATE_CHECK: 23.525 - begin 23.526 - if (miss == `TRUE) 23.527 - refill_offset <= {addr_offset_width{1'b0}}; 23.528 - end 23.529 - 23.530 - // Refill a cache line 23.531 - `LM32_DC_STATE_REFILL: 23.532 - begin 23.533 - if (refill_ready == `TRUE) 23.534 - refill_offset <= refill_offset + 1'b1; 23.535 - end 23.536 - 23.537 - endcase 23.538 - end 23.539 -end 23.540 - end 23.541 -endgenerate 23.542 - 23.543 -endmodule 23.544 - 23.545 -`endif 23.546 -
24.1 diff -r 252df75c8f67 -r c336e674a37e lm32_debug.v 24.2 --- a/lm32_debug.v Sun Mar 06 21:17:31 2011 +0000 24.3 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 24.4 @@ -1,348 +0,0 @@ 24.5 -// ============================================================================= 24.6 -// COPYRIGHT NOTICE 24.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 24.8 -// ALL RIGHTS RESERVED 24.9 -// This confidential and proprietary software may be used only as authorised by 24.10 -// a licensing agreement from Lattice Semiconductor Corporation. 24.11 -// The entire notice above must be reproduced on all authorized copies and 24.12 -// copies may only be made to the extent permitted by a licensing agreement from 24.13 -// Lattice Semiconductor Corporation. 24.14 -// 24.15 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 24.16 -// 5555 NE Moore Court 408-826-6000 (other locations) 24.17 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 24.18 -// U.S.A email: techsupport@latticesemi.com 24.19 -// =============================================================================/ 24.20 -// FILE DETAILS 24.21 -// Project : LatticeMico32 24.22 -// File : lm32_debug.v 24.23 -// Title : Hardware debug registers and associated logic. 24.24 -// Dependencies : lm32_include.v 24.25 -// Version : 6.1.17 24.26 -// : Initial Release 24.27 -// Version : 7.0SP2, 3.0 24.28 -// : No Change 24.29 -// Version : 3.1 24.30 -// : No Change 24.31 -// Version : 3.2 24.32 -// : Fixed simulation bug which flares up when number of 24.33 -// : watchpoints is zero. 24.34 -// ============================================================================= 24.35 - 24.36 -`include "lm32_include.v" 24.37 - 24.38 -`ifdef CFG_DEBUG_ENABLED 24.39 - 24.40 -// States for single-step FSM 24.41 -`define LM32_DEBUG_SS_STATE_RNG 2:0 24.42 -`define LM32_DEBUG_SS_STATE_IDLE 3'b000 24.43 -`define LM32_DEBUG_SS_STATE_WAIT_FOR_RET 3'b001 24.44 -`define LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN 3'b010 24.45 -`define LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT 3'b011 24.46 -`define LM32_DEBUG_SS_STATE_RESTART 3'b100 24.47 - 24.48 -///////////////////////////////////////////////////// 24.49 -// Module interface 24.50 -///////////////////////////////////////////////////// 24.51 - 24.52 -module lm32_debug ( 24.53 - // ----- Inputs ------- 24.54 - clk_i, 24.55 - rst_i, 24.56 - pc_x, 24.57 - load_x, 24.58 - store_x, 24.59 - load_store_address_x, 24.60 - csr_write_enable_x, 24.61 - csr_write_data, 24.62 - csr_x, 24.63 -`ifdef CFG_HW_DEBUG_ENABLED 24.64 - jtag_csr_write_enable, 24.65 - jtag_csr_write_data, 24.66 - jtag_csr, 24.67 -`endif 24.68 -`ifdef LM32_SINGLE_STEP_ENABLED 24.69 - eret_q_x, 24.70 - bret_q_x, 24.71 - stall_x, 24.72 - exception_x, 24.73 - q_x, 24.74 -`ifdef CFG_DCACHE_ENABLED 24.75 - dcache_refill_request, 24.76 -`endif 24.77 -`endif 24.78 - // ----- Outputs ------- 24.79 -`ifdef LM32_SINGLE_STEP_ENABLED 24.80 - dc_ss, 24.81 -`endif 24.82 - dc_re, 24.83 - bp_match, 24.84 - wp_match 24.85 - ); 24.86 - 24.87 -///////////////////////////////////////////////////// 24.88 -// Parameters 24.89 -///////////////////////////////////////////////////// 24.90 - 24.91 -parameter breakpoints = 0; // Number of breakpoint CSRs 24.92 -parameter watchpoints = 0; // Number of watchpoint CSRs 24.93 - 24.94 -///////////////////////////////////////////////////// 24.95 -// Inputs 24.96 -///////////////////////////////////////////////////// 24.97 - 24.98 -input clk_i; // Clock 24.99 -input rst_i; // Reset 24.100 - 24.101 -input [`LM32_PC_RNG] pc_x; // X stage PC 24.102 -input load_x; // Load instruction in X stage 24.103 -input store_x; // Store instruction in X stage 24.104 -input [`LM32_WORD_RNG] load_store_address_x; // Load or store effective address 24.105 -input csr_write_enable_x; // wcsr instruction in X stage 24.106 -input [`LM32_WORD_RNG] csr_write_data; // Data to write to CSR 24.107 -input [`LM32_CSR_RNG] csr_x; // Which CSR to write 24.108 -`ifdef CFG_HW_DEBUG_ENABLED 24.109 -input jtag_csr_write_enable; // JTAG interface CSR write enable 24.110 -input [`LM32_WORD_RNG] jtag_csr_write_data; // Data to write to CSR 24.111 -input [`LM32_CSR_RNG] jtag_csr; // Which CSR to write 24.112 -`endif 24.113 -`ifdef LM32_SINGLE_STEP_ENABLED 24.114 -input eret_q_x; // eret instruction in X stage 24.115 -input bret_q_x; // bret instruction in X stage 24.116 -input stall_x; // Instruction in X stage is stalled 24.117 -input exception_x; // An exception has occured in X stage 24.118 -input q_x; // Indicates the instruction in the X stage is qualified 24.119 -`ifdef CFG_DCACHE_ENABLED 24.120 -input dcache_refill_request; // Indicates data cache wants to be refilled 24.121 -`endif 24.122 -`endif 24.123 - 24.124 -///////////////////////////////////////////////////// 24.125 -// Outputs 24.126 -///////////////////////////////////////////////////// 24.127 - 24.128 -`ifdef LM32_SINGLE_STEP_ENABLED 24.129 -output dc_ss; // Single-step enable 24.130 -reg dc_ss; 24.131 -`endif 24.132 -output dc_re; // Remap exceptions 24.133 -reg dc_re; 24.134 -output bp_match; // Indicates a breakpoint has matched 24.135 -wire bp_match; 24.136 -output wp_match; // Indicates a watchpoint has matched 24.137 -wire wp_match; 24.138 - 24.139 -///////////////////////////////////////////////////// 24.140 -// Internal nets and registers 24.141 -///////////////////////////////////////////////////// 24.142 - 24.143 -genvar i; // Loop index for generate statements 24.144 - 24.145 -// Debug CSRs 24.146 - 24.147 -reg [`LM32_PC_RNG] bp_a[0:breakpoints-1]; // Instruction breakpoint address 24.148 -reg bp_e[0:breakpoints-1]; // Instruction breakpoint enable 24.149 -wire [0:breakpoints-1]bp_match_n; // Indicates if a h/w instruction breakpoint matched 24.150 - 24.151 -reg [`LM32_WPC_C_RNG] wpc_c[0:watchpoints-1]; // Watchpoint enable 24.152 -reg [`LM32_WORD_RNG] wp[0:watchpoints-1]; // Watchpoint address 24.153 -wire [0:watchpoints]wp_match_n; // Indicates if a h/w data watchpoint matched 24.154 - 24.155 -wire debug_csr_write_enable; // Debug CSR write enable (from either a wcsr instruction of external debugger) 24.156 -wire [`LM32_WORD_RNG] debug_csr_write_data; // Data to write to debug CSR 24.157 -wire [`LM32_CSR_RNG] debug_csr; // Debug CSR to write to 24.158 - 24.159 -`ifdef LM32_SINGLE_STEP_ENABLED 24.160 -// FIXME: Declaring this as a reg causes ModelSim 6.1.15b to crash, so use integer for now 24.161 -//reg [`LM32_DEBUG_SS_STATE_RNG] state; // State of single-step FSM 24.162 -integer state; // State of single-step FSM 24.163 -`endif 24.164 - 24.165 -///////////////////////////////////////////////////// 24.166 -// Functions 24.167 -///////////////////////////////////////////////////// 24.168 - 24.169 -`include "lm32_functions.v" 24.170 - 24.171 -///////////////////////////////////////////////////// 24.172 -// Combinational Logic 24.173 -///////////////////////////////////////////////////// 24.174 - 24.175 -// Check for breakpoints 24.176 -generate 24.177 - for (i = 0; i < breakpoints; i = i + 1) 24.178 - begin : bp_comb 24.179 -assign bp_match_n[i] = ((bp_a[i] == pc_x) && (bp_e[i] == `TRUE)); 24.180 - end 24.181 -endgenerate 24.182 -generate 24.183 -`ifdef LM32_SINGLE_STEP_ENABLED 24.184 - if (breakpoints > 0) 24.185 -assign bp_match = (|bp_match_n) || (state == `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT); 24.186 - else 24.187 -assign bp_match = state == `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT; 24.188 -`else 24.189 - if (breakpoints > 0) 24.190 -assign bp_match = |bp_match_n; 24.191 - else 24.192 -assign bp_match = `FALSE; 24.193 -`endif 24.194 -endgenerate 24.195 - 24.196 -// Check for watchpoints 24.197 -generate 24.198 - for (i = 0; i < watchpoints; i = i + 1) 24.199 - begin : wp_comb 24.200 -assign wp_match_n[i] = (wp[i] == load_store_address_x) && ((load_x & wpc_c[i][0]) | (store_x & wpc_c[i][1])); 24.201 - end 24.202 -endgenerate 24.203 -generate 24.204 - if (watchpoints > 0) 24.205 -assign wp_match = |wp_match_n; 24.206 - else 24.207 -assign wp_match = `FALSE; 24.208 -endgenerate 24.209 - 24.210 -`ifdef CFG_HW_DEBUG_ENABLED 24.211 -// Multiplex between wcsr instruction writes and debugger writes to the debug CSRs 24.212 -assign debug_csr_write_enable = (csr_write_enable_x == `TRUE) || (jtag_csr_write_enable == `TRUE); 24.213 -assign debug_csr_write_data = jtag_csr_write_enable == `TRUE ? jtag_csr_write_data : csr_write_data; 24.214 -assign debug_csr = jtag_csr_write_enable == `TRUE ? jtag_csr : csr_x; 24.215 -`else 24.216 -assign debug_csr_write_enable = csr_write_enable_x; 24.217 -assign debug_csr_write_data = csr_write_data; 24.218 -assign debug_csr = csr_x; 24.219 -`endif 24.220 - 24.221 -///////////////////////////////////////////////////// 24.222 -// Sequential Logic 24.223 -///////////////////////////////////////////////////// 24.224 - 24.225 -// Breakpoint address and enable CSRs 24.226 -generate 24.227 - for (i = 0; i < breakpoints; i = i + 1) 24.228 - begin : bp_seq 24.229 -always @(posedge clk_i `CFG_RESET_SENSITIVITY) 24.230 -begin 24.231 - if (rst_i == `TRUE) 24.232 - begin 24.233 - bp_a[i] <= {`LM32_PC_WIDTH{1'bx}}; 24.234 - bp_e[i] <= `FALSE; 24.235 - end 24.236 - else 24.237 - begin 24.238 - if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_BP0 + i)) 24.239 - begin 24.240 - bp_a[i] <= debug_csr_write_data[`LM32_PC_RNG]; 24.241 - bp_e[i] <= debug_csr_write_data[0]; 24.242 - end 24.243 - end 24.244 -end 24.245 - end 24.246 -endgenerate 24.247 - 24.248 -// Watchpoint address and control flags CSRs 24.249 -generate 24.250 - for (i = 0; i < watchpoints; i = i + 1) 24.251 - begin : wp_seq 24.252 -always @(posedge clk_i `CFG_RESET_SENSITIVITY) 24.253 -begin 24.254 - if (rst_i == `TRUE) 24.255 - begin 24.256 - wp[i] <= {`LM32_WORD_WIDTH{1'bx}}; 24.257 - wpc_c[i] <= `LM32_WPC_C_DISABLED; 24.258 - end 24.259 - else 24.260 - begin 24.261 - if (debug_csr_write_enable == `TRUE) 24.262 - begin 24.263 - if (debug_csr == `LM32_CSR_DC) 24.264 - wpc_c[i] <= debug_csr_write_data[3+i*2:2+i*2]; 24.265 - if (debug_csr == `LM32_CSR_WP0 + i) 24.266 - wp[i] <= debug_csr_write_data; 24.267 - end 24.268 - end 24.269 -end 24.270 - end 24.271 -endgenerate 24.272 - 24.273 -// Remap exceptions control bit 24.274 -always @(posedge clk_i `CFG_RESET_SENSITIVITY) 24.275 -begin 24.276 - if (rst_i == `TRUE) 24.277 - dc_re <= `FALSE; 24.278 - else 24.279 - begin 24.280 - if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_DC)) 24.281 - dc_re <= debug_csr_write_data[1]; 24.282 - end 24.283 -end 24.284 - 24.285 -`ifdef LM32_SINGLE_STEP_ENABLED 24.286 -// Single-step control flag 24.287 -always @(posedge clk_i `CFG_RESET_SENSITIVITY) 24.288 -begin 24.289 - if (rst_i == `TRUE) 24.290 - begin 24.291 - state <= `LM32_DEBUG_SS_STATE_IDLE; 24.292 - dc_ss <= `FALSE; 24.293 - end 24.294 - else 24.295 - begin 24.296 - if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_DC)) 24.297 - begin 24.298 - dc_ss <= debug_csr_write_data[0]; 24.299 - if (debug_csr_write_data[0] == `FALSE) 24.300 - state <= `LM32_DEBUG_SS_STATE_IDLE; 24.301 - else 24.302 - state <= `LM32_DEBUG_SS_STATE_WAIT_FOR_RET; 24.303 - end 24.304 - case (state) 24.305 - `LM32_DEBUG_SS_STATE_WAIT_FOR_RET: 24.306 - begin 24.307 - // Wait for eret or bret instruction to be executed 24.308 - if ( ( (eret_q_x == `TRUE) 24.309 - || (bret_q_x == `TRUE) 24.310 - ) 24.311 - && (stall_x == `FALSE) 24.312 - ) 24.313 - state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 24.314 - end 24.315 - `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN: 24.316 - begin 24.317 - // Wait for an instruction to be executed 24.318 - if ((q_x == `TRUE) && (stall_x == `FALSE)) 24.319 - state <= `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT; 24.320 - end 24.321 - `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT: 24.322 - begin 24.323 - // Wait for exception to be raised 24.324 -`ifdef CFG_DCACHE_ENABLED 24.325 - if (dcache_refill_request == `TRUE) 24.326 - state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 24.327 - else 24.328 -`endif 24.329 - if ((exception_x == `TRUE) && (q_x == `TRUE) && (stall_x == `FALSE)) 24.330 - begin 24.331 - dc_ss <= `FALSE; 24.332 - state <= `LM32_DEBUG_SS_STATE_RESTART; 24.333 - end 24.334 - end 24.335 - `LM32_DEBUG_SS_STATE_RESTART: 24.336 - begin 24.337 - // Watch to see if stepped instruction is restarted due to a cache miss 24.338 -`ifdef CFG_DCACHE_ENABLED 24.339 - if (dcache_refill_request == `TRUE) 24.340 - state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 24.341 - else 24.342 -`endif 24.343 - state <= `LM32_DEBUG_SS_STATE_IDLE; 24.344 - end 24.345 - endcase 24.346 - end 24.347 -end 24.348 -`endif 24.349 - 24.350 -endmodule 24.351 - 24.352 -`endif
25.1 diff -r 252df75c8f67 -r c336e674a37e lm32_decoder.v 25.2 --- a/lm32_decoder.v Sun Mar 06 21:17:31 2011 +0000 25.3 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 25.4 @@ -1,583 +0,0 @@ 25.5 -// ============================================================================= 25.6 -// COPYRIGHT NOTICE 25.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 25.8 -// ALL RIGHTS RESERVED 25.9 -// This confidential and proprietary software may be used only as authorised by 25.10 -// a licensing agreement from Lattice Semiconductor Corporation. 25.11 -// The entire notice above must be reproduced on all authorized copies and 25.12 -// copies may only be made to the extent permitted by a licensing agreement from 25.13 -// Lattice Semiconductor Corporation. 25.14 -// 25.15 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 25.16 -// 5555 NE Moore Court 408-826-6000 (other locations) 25.17 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 25.18 -// U.S.A email: techsupport@latticesemi.com 25.19 -// =============================================================================/ 25.20 -// FILE DETAILS 25.21 -// Project : LatticeMico32 25.22 -// File : lm32_decoder.v 25.23 -// Title : Instruction decoder 25.24 -// Dependencies : lm32_include.v 25.25 -// Version : 6.1.17 25.26 -// : Initial Release 25.27 -// Version : 7.0SP2, 3.0 25.28 -// : No Change 25.29 -// Version : 3.1 25.30 -// : Support for static branch prediction. Information about 25.31 -// : branch type is generated and passed on to the predictor. 25.32 -// Version : 3.2 25.33 -// : No change 25.34 -// Version : 3.3 25.35 -// : Renamed port names that conflict with keywords reserved 25.36 -// : in System-Verilog. 25.37 -// ============================================================================= 25.38 - 25.39 -`include "lm32_include.v" 25.40 - 25.41 -// Index of opcode field in an instruction 25.42 -`define LM32_OPCODE_RNG 31:26 25.43 -`define LM32_OP_RNG 30:26 25.44 - 25.45 -// Opcodes - Some are only listed as 5 bits as their MSB is a don't care 25.46 -`define LM32_OPCODE_ADD 5'b01101 25.47 -`define LM32_OPCODE_AND 5'b01000 25.48 -`define LM32_OPCODE_ANDHI 6'b011000 25.49 -`define LM32_OPCODE_B 6'b110000 25.50 -`define LM32_OPCODE_BI 6'b111000 25.51 -`define LM32_OPCODE_BE 6'b010001 25.52 -`define LM32_OPCODE_BG 6'b010010 25.53 -`define LM32_OPCODE_BGE 6'b010011 25.54 -`define LM32_OPCODE_BGEU 6'b010100 25.55 -`define LM32_OPCODE_BGU 6'b010101 25.56 -`define LM32_OPCODE_BNE 6'b010111 25.57 -`define LM32_OPCODE_CALL 6'b110110 25.58 -`define LM32_OPCODE_CALLI 6'b111110 25.59 -`define LM32_OPCODE_CMPE 5'b11001 25.60 -`define LM32_OPCODE_CMPG 5'b11010 25.61 -`define LM32_OPCODE_CMPGE 5'b11011 25.62 -`define LM32_OPCODE_CMPGEU 5'b11100 25.63 -`define LM32_OPCODE_CMPGU 5'b11101 25.64 -`define LM32_OPCODE_CMPNE 5'b11111 25.65 -`define LM32_OPCODE_DIVU 6'b100011 25.66 -`define LM32_OPCODE_LB 6'b000100 25.67 -`define LM32_OPCODE_LBU 6'b010000 25.68 -`define LM32_OPCODE_LH 6'b000111 25.69 -`define LM32_OPCODE_LHU 6'b001011 25.70 -`define LM32_OPCODE_LW 6'b001010 25.71 -`define LM32_OPCODE_MODU 6'b110001 25.72 -`define LM32_OPCODE_MUL 5'b00010 25.73 -`define LM32_OPCODE_NOR 5'b00001 25.74 -`define LM32_OPCODE_OR 5'b01110 25.75 -`define LM32_OPCODE_ORHI 6'b011110 25.76 -`define LM32_OPCODE_RAISE 6'b101011 25.77 -`define LM32_OPCODE_RCSR 6'b100100 25.78 -`define LM32_OPCODE_SB 6'b001100 25.79 -`define LM32_OPCODE_SEXTB 6'b101100 25.80 -`define LM32_OPCODE_SEXTH 6'b110111 25.81 -`define LM32_OPCODE_SH 6'b000011 25.82 -`define LM32_OPCODE_SL 5'b01111 25.83 -`define LM32_OPCODE_SR 5'b00101 25.84 -`define LM32_OPCODE_SRU 5'b00000 25.85 -`define LM32_OPCODE_SUB 6'b110010 25.86 -`define LM32_OPCODE_SW 6'b010110 25.87 -`define LM32_OPCODE_USER 6'b110011 25.88 -`define LM32_OPCODE_WCSR 6'b110100 25.89 -`define LM32_OPCODE_XNOR 5'b01001 25.90 -`define LM32_OPCODE_XOR 5'b00110 25.91 - 25.92 -///////////////////////////////////////////////////// 25.93 -// Module interface 25.94 -///////////////////////////////////////////////////// 25.95 - 25.96 -module lm32_decoder ( 25.97 - // ----- Inputs ------- 25.98 - instruction, 25.99 - // ----- Outputs ------- 25.100 - d_result_sel_0, 25.101 - d_result_sel_1, 25.102 - x_result_sel_csr, 25.103 -`ifdef LM32_MC_ARITHMETIC_ENABLED 25.104 - x_result_sel_mc_arith, 25.105 -`endif 25.106 -`ifdef LM32_NO_BARREL_SHIFT 25.107 - x_result_sel_shift, 25.108 -`endif 25.109 -`ifdef CFG_SIGN_EXTEND_ENABLED 25.110 - x_result_sel_sext, 25.111 -`endif 25.112 - x_result_sel_logic, 25.113 -`ifdef CFG_USER_ENABLED 25.114 - x_result_sel_user, 25.115 -`endif 25.116 - x_result_sel_add, 25.117 - m_result_sel_compare, 25.118 -`ifdef CFG_PL_BARREL_SHIFT_ENABLED 25.119 - m_result_sel_shift, 25.120 -`endif 25.121 - w_result_sel_load, 25.122 -`ifdef CFG_PL_MULTIPLY_ENABLED 25.123 - w_result_sel_mul, 25.124 -`endif 25.125 - x_bypass_enable, 25.126 - m_bypass_enable, 25.127 - read_enable_0, 25.128 - read_idx_0, 25.129 - read_enable_1, 25.130 - read_idx_1, 25.131 - write_enable, 25.132 - write_idx, 25.133 - immediate, 25.134 - branch_offset, 25.135 - load, 25.136 - store, 25.137 - size, 25.138 - sign_extend, 25.139 - adder_op, 25.140 - logic_op, 25.141 -`ifdef CFG_PL_BARREL_SHIFT_ENABLED 25.142 - direction, 25.143 -`endif 25.144 -`ifdef CFG_MC_BARREL_SHIFT_ENABLED 25.145 - shift_left, 25.146 - shift_right, 25.147 -`endif 25.148 -`ifdef CFG_MC_MULTIPLY_ENABLED 25.149 - multiply, 25.150 -`endif 25.151 -`ifdef CFG_MC_DIVIDE_ENABLED 25.152 - divide, 25.153 - modulus, 25.154 -`endif 25.155 - branch, 25.156 - branch_reg, 25.157 - condition, 25.158 - bi_conditional, 25.159 - bi_unconditional, 25.160 -`ifdef CFG_DEBUG_ENABLED 25.161 - break_opcode, 25.162 -`endif 25.163 - scall, 25.164 - eret, 25.165 -`ifdef CFG_DEBUG_ENABLED 25.166 - bret, 25.167 -`endif 25.168 -`ifdef CFG_USER_ENABLED 25.169 - user_opcode, 25.170 -`endif 25.171 - csr_write_enable 25.172 - ); 25.173 - 25.174 -///////////////////////////////////////////////////// 25.175 -// Inputs 25.176 -///////////////////////////////////////////////////// 25.177 - 25.178 -input [`LM32_INSTRUCTION_RNG] instruction; // Instruction to decode 25.179 - 25.180 -///////////////////////////////////////////////////// 25.181 -// Outputs 25.182 -///////////////////////////////////////////////////// 25.183 - 25.184 -output [`LM32_D_RESULT_SEL_0_RNG] d_result_sel_0; 25.185 -reg [`LM32_D_RESULT_SEL_0_RNG] d_result_sel_0; 25.186 -output [`LM32_D_RESULT_SEL_1_RNG] d_result_sel_1; 25.187 -reg [`LM32_D_RESULT_SEL_1_RNG] d_result_sel_1; 25.188 -output x_result_sel_csr; 25.189 -reg x_result_sel_csr; 25.190 -`ifdef LM32_MC_ARITHMETIC_ENABLED 25.191 -output x_result_sel_mc_arith; 25.192 -reg x_result_sel_mc_arith; 25.193 -`endif 25.194 -`ifdef LM32_NO_BARREL_SHIFT 25.195 -output x_result_sel_shift; 25.196 -reg x_result_sel_shift; 25.197 -`endif 25.198 -`ifdef CFG_SIGN_EXTEND_ENABLED 25.199 -output x_result_sel_sext; 25.200 -reg x_result_sel_sext; 25.201 -`endif 25.202 -output x_result_sel_logic; 25.203 -reg x_result_sel_logic; 25.204 -`ifdef CFG_USER_ENABLED 25.205 -output x_result_sel_user; 25.206 -reg x_result_sel_user; 25.207 -`endif 25.208 -output x_result_sel_add; 25.209 -reg x_result_sel_add; 25.210 -output m_result_sel_compare; 25.211 -reg m_result_sel_compare; 25.212 -`ifdef CFG_PL_BARREL_SHIFT_ENABLED 25.213 -output m_result_sel_shift; 25.214 -reg m_result_sel_shift; 25.215 -`endif 25.216 -output w_result_sel_load; 25.217 -reg w_result_sel_load; 25.218 -`ifdef CFG_PL_MULTIPLY_ENABLED 25.219 -output w_result_sel_mul; 25.220 -reg w_result_sel_mul; 25.221 -`endif 25.222 -output x_bypass_enable; 25.223 -wire x_bypass_enable; 25.224 -output m_bypass_enable; 25.225 -wire m_bypass_enable; 25.226 -output read_enable_0; 25.227 -wire read_enable_0; 25.228 -output [`LM32_REG_IDX_RNG] read_idx_0; 25.229 -wire [`LM32_REG_IDX_RNG] read_idx_0; 25.230 -output read_enable_1; 25.231 -wire read_enable_1; 25.232 -output [`LM32_REG_IDX_RNG] read_idx_1; 25.233 -wire [`LM32_REG_IDX_RNG] read_idx_1; 25.234 -output write_enable; 25.235 -wire write_enable; 25.236 -output [`LM32_REG_IDX_RNG] write_idx; 25.237 -wire [`LM32_REG_IDX_RNG] write_idx; 25.238 -output [`LM32_WORD_RNG] immediate; 25.239 -wire [`LM32_WORD_RNG] immediate; 25.240 -output [`LM32_PC_RNG] branch_offset; 25.241 -wire [`LM32_PC_RNG] branch_offset; 25.242 -output load; 25.243 -wire load; 25.244 -output store; 25.245 -wire store; 25.246 -output [`LM32_SIZE_RNG] size; 25.247 -wire [`LM32_SIZE_RNG] size; 25.248 -output sign_extend; 25.249 -wire sign_extend; 25.250 -output adder_op; 25.251 -wire adder_op; 25.252 -output [`LM32_LOGIC_OP_RNG] logic_op; 25.253 -wire [`LM32_LOGIC_OP_RNG] logic_op; 25.254 -`ifdef CFG_PL_BARREL_SHIFT_ENABLED 25.255 -output direction; 25.256 -wire direction; 25.257 -`endif 25.258 -`ifdef CFG_MC_BARREL_SHIFT_ENABLED 25.259 -output shift_left; 25.260 -wire shift_left; 25.261 -output shift_right; 25.262 -wire shift_right; 25.263 -`endif 25.264 -`ifdef CFG_MC_MULTIPLY_ENABLED 25.265 -output multiply; 25.266 -wire multiply; 25.267 -`endif 25.268 -`ifdef CFG_MC_DIVIDE_ENABLED 25.269 -output divide; 25.270 -wire divide; 25.271 -output modulus; 25.272 -wire modulus; 25.273 -`endif 25.274 -output branch; 25.275 -wire branch; 25.276 -output branch_reg; 25.277 -wire branch_reg; 25.278 -output [`LM32_CONDITION_RNG] condition; 25.279 -wire [`LM32_CONDITION_RNG] condition; 25.280 -output bi_conditional; 25.281 -wire bi_conditional; 25.282 -output bi_unconditional; 25.283 -wire bi_unconditional; 25.284 -`ifdef CFG_DEBUG_ENABLED 25.285 -output break_opcode; 25.286 -wire break_opcode; 25.287 -`endif 25.288 -output scall; 25.289 -wire scall; 25.290 -output eret; 25.291 -wire eret; 25.292 -`ifdef CFG_DEBUG_ENABLED 25.293 -output bret; 25.294 -wire bret; 25.295 -`endif 25.296 -`ifdef CFG_USER_ENABLED 25.297 -output [`LM32_USER_OPCODE_RNG] user_opcode; 25.298 -wire [`LM32_USER_OPCODE_RNG] user_opcode; 25.299 -`endif 25.300 -output csr_write_enable; 25.301 -wire csr_write_enable; 25.302 - 25.303 -///////////////////////////////////////////////////// 25.304 -// Internal nets and registers 25.305 -///////////////////////////////////////////////////// 25.306 - 25.307 -wire [`LM32_WORD_RNG] extended_immediate; // Zero or sign extended immediate 25.308 -wire [`LM32_WORD_RNG] high_immediate; // Immediate as high 16 bits 25.309 -wire [`LM32_WORD_RNG] call_immediate; // Call immediate 25.310 -wire [`LM32_WORD_RNG] branch_immediate; // Conditional branch immediate 25.311 -wire sign_extend_immediate; // Whether the immediate should be sign extended (`TRUE) or zero extended (`FALSE) 25.312 -wire select_high_immediate; // Whether to select the high immediate 25.313 -wire select_call_immediate; // Whether to select the call immediate 25.314 - 25.315 -///////////////////////////////////////////////////// 25.316 -// Functions 25.317 -///////////////////////////////////////////////////// 25.318 - 25.319 -`include "lm32_functions.v" 25.320 - 25.321 -///////////////////////////////////////////////////// 25.322 -// Combinational logic 25.323 -///////////////////////////////////////////////////// 25.324 - 25.325 -// Determine opcode 25.326 -assign op_add = instruction[`LM32_OP_RNG] == `LM32_OPCODE_ADD; 25.327 -assign op_and = instruction[`LM32_OP_RNG] == `LM32_OPCODE_AND; 25.328 -assign op_andhi = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_ANDHI; 25.329 -assign op_b = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_B; 25.330 -assign op_bi = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BI; 25.331 -assign op_be = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BE; 25.332 -assign op_bg = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BG; 25.333 -assign op_bge = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BGE; 25.334 -assign op_bgeu = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BGEU; 25.335 -assign op_bgu = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BGU; 25.336 -assign op_bne = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BNE; 25.337 -assign op_call = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_CALL; 25.338 -assign op_calli = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_CALLI; 25.339 -assign op_cmpe = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPE; 25.340 -assign op_cmpg = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPG; 25.341 -assign op_cmpge = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPGE; 25.342 -assign op_cmpgeu = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPGEU; 25.343 -assign op_cmpgu = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPGU; 25.344 -assign op_cmpne = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPNE; 25.345 -`ifdef CFG_MC_DIVIDE_ENABLED 25.346 -assign op_divu = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_DIVU; 25.347 -`endif 25.348 -assign op_lb = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LB; 25.349 -assign op_lbu = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LBU; 25.350 -assign op_lh = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LH; 25.351 -assign op_lhu = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LHU; 25.352 -assign op_lw = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LW; 25.353 -`ifdef CFG_MC_DIVIDE_ENABLED 25.354 -assign op_modu = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_MODU; 25.355 -`endif 25.356 -`ifdef LM32_MULTIPLY_ENABLED 25.357 -assign op_mul = instruction[`LM32_OP_RNG] == `LM32_OPCODE_MUL; 25.358 -`endif 25.359 -assign op_nor = instruction[`LM32_OP_RNG] == `LM32_OPCODE_NOR; 25.360 -assign op_or = instruction[`LM32_OP_RNG] == `LM32_OPCODE_OR; 25.361 -assign op_orhi = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_ORHI; 25.362 -assign op_raise = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_RAISE; 25.363 -assign op_rcsr = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_RCSR; 25.364 -assign op_sb = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SB; 25.365 -`ifdef CFG_SIGN_EXTEND_ENABLED 25.366 -assign op_sextb = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SEXTB; 25.367 -assign op_sexth = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SEXTH; 25.368 -`endif 25.369 -assign op_sh = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SH; 25.370 -`ifdef LM32_BARREL_SHIFT_ENABLED 25.371 -assign op_sl = instruction[`LM32_OP_RNG] == `LM32_OPCODE_SL; 25.372 -`endif 25.373 -assign op_sr = instruction[`LM32_OP_RNG] == `LM32_OPCODE_SR; 25.374 -assign op_sru = instruction[`LM32_OP_RNG] == `LM32_OPCODE_SRU; 25.375 -assign op_sub = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SUB; 25.376 -assign op_sw = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SW; 25.377 -assign op_user = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_USER; 25.378 -assign op_wcsr = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_WCSR; 25.379 -assign op_xnor = instruction[`LM32_OP_RNG] == `LM32_OPCODE_XNOR; 25.380 -assign op_xor = instruction[`LM32_OP_RNG] == `LM32_OPCODE_XOR; 25.381 - 25.382 -// Group opcodes by function 25.383 -assign arith = op_add | op_sub; 25.384 -assign logical = op_and | op_andhi | op_nor | op_or | op_orhi | op_xor | op_xnor; 25.385 -assign cmp = op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne; 25.386 -assign bi_conditional = op_be | op_bg | op_bge | op_bgeu | op_bgu | op_bne; 25.387 -assign bi_unconditional = op_bi; 25.388 -assign bra = op_b | bi_unconditional | bi_conditional; 25.389 -assign call = op_call | op_calli; 25.390 -`ifdef LM32_BARREL_SHIFT_ENABLED 25.391 -assign shift = op_sl | op_sr | op_sru; 25.392 -`endif 25.393 -`ifdef LM32_NO_BARREL_SHIFT 25.394 -assign shift = op_sr | op_sru; 25.395 -`endif 25.396 -`ifdef CFG_MC_BARREL_SHIFT_ENABLED 25.397 -assign shift_left = op_sl; 25.398 -assign shift_right = op_sr | op_sru; 25.399 -`endif 25.400 -`ifdef CFG_SIGN_EXTEND_ENABLED 25.401 -assign sext = op_sextb | op_sexth; 25.402 -`endif 25.403 -`ifdef LM32_MULTIPLY_ENABLED 25.404 -assign multiply = op_mul; 25.405 -`endif 25.406 -`ifdef CFG_MC_DIVIDE_ENABLED 25.407 -assign divide = op_divu; 25.408 -assign modulus = op_modu; 25.409 -`endif 25.410 -assign load = op_lb | op_lbu | op_lh | op_lhu | op_lw; 25.411 -assign store = op_sb | op_sh | op_sw; 25.412 - 25.413 -// Select pipeline multiplexor controls 25.414 -always @(*) 25.415 -begin 25.416 - // D stage 25.417 - if (call) 25.418 - d_result_sel_0 = `LM32_D_RESULT_SEL_0_NEXT_PC; 25.419 - else 25.420 - d_result_sel_0 = `LM32_D_RESULT_SEL_0_REG_0; 25.421 - if (call) 25.422 - d_result_sel_1 = `LM32_D_RESULT_SEL_1_ZERO; 25.423 - else if ((instruction[31] == 1'b0) && !bra) 25.424 - d_result_sel_1 = `LM32_D_RESULT_SEL_1_IMMEDIATE; 25.425 - else 25.426 - d_result_sel_1 = `LM32_D_RESULT_SEL_1_REG_1; 25.427 - // X stage 25.428 - x_result_sel_csr = `FALSE; 25.429 -`ifdef LM32_MC_ARITHMETIC_ENABLED 25.430 - x_result_sel_mc_arith = `FALSE; 25.431 -`endif 25.432 -`ifdef LM32_NO_BARREL_SHIFT 25.433 - x_result_sel_shift = `FALSE; 25.434 -`endif 25.435 -`ifdef CFG_SIGN_EXTEND_ENABLED 25.436 - x_result_sel_sext = `FALSE; 25.437 -`endif 25.438 - x_result_sel_logic = `FALSE; 25.439 -`ifdef CFG_USER_ENABLED 25.440 - x_result_sel_user = `FALSE; 25.441 -`endif 25.442 - x_result_sel_add = `FALSE; 25.443 - if (op_rcsr) 25.444 - x_result_sel_csr = `TRUE; 25.445 -`ifdef LM32_MC_ARITHMETIC_ENABLED 25.446 -`ifdef CFG_MC_BARREL_SHIFT_ENABLED 25.447 - else if (shift_left | shift_right) 25.448 - x_result_sel_mc_arith = `TRUE; 25.449 -`endif 25.450 -`ifdef CFG_MC_DIVIDE_ENABLED 25.451 - else if (divide | modulus) 25.452 - x_result_sel_mc_arith = `TRUE; 25.453 -`endif 25.454 -`ifdef CFG_MC_MULTIPLY_ENABLED 25.455 - else if (multiply) 25.456 - x_result_sel_mc_arith = `TRUE; 25.457 -`endif 25.458 -`endif 25.459 -`ifdef LM32_NO_BARREL_SHIFT 25.460 - else if (shift) 25.461 - x_result_sel_shift = `TRUE; 25.462 -`endif 25.463 -`ifdef CFG_SIGN_EXTEND_ENABLED 25.464 - else if (sext) 25.465 - x_result_sel_sext = `TRUE; 25.466 -`endif 25.467 - else if (logical) 25.468 - x_result_sel_logic = `TRUE; 25.469 -`ifdef CFG_USER_ENABLED 25.470 - else if (op_user) 25.471 - x_result_sel_user = `TRUE; 25.472 -`endif 25.473 - else 25.474 - x_result_sel_add = `TRUE; 25.475 - 25.476 - // M stage 25.477 - 25.478 - m_result_sel_compare = cmp; 25.479 -`ifdef CFG_PL_BARREL_SHIFT_ENABLED 25.480 - m_result_sel_shift = shift; 25.481 -`endif 25.482 - 25.483 - // W stage 25.484 - w_result_sel_load = load; 25.485 -`ifdef CFG_PL_MULTIPLY_ENABLED 25.486 - w_result_sel_mul = op_mul; 25.487 -`endif 25.488 -end 25.489 - 25.490 -// Set if result is valid at end of X stage 25.491 -assign x_bypass_enable = arith 25.492 - | logical 25.493 -`ifdef CFG_MC_BARREL_SHIFT_ENABLED 25.494 - | shift_left 25.495 - | shift_right 25.496 -`endif 25.497 -`ifdef CFG_MC_MULTIPLY_ENABLED 25.498 - | multiply 25.499 -`endif 25.500 -`ifdef CFG_MC_DIVIDE_ENABLED 25.501 - | divide 25.502 - | modulus 25.503 -`endif 25.504 -`ifdef LM32_NO_BARREL_SHIFT 25.505 - | shift 25.506 -`endif 25.507 -`ifdef CFG_SIGN_EXTEND_ENABLED 25.508 - | sext 25.509 -`endif 25.510 -`ifdef CFG_USER_ENABLED 25.511 - | op_user 25.512 -`endif 25.513 - | op_rcsr 25.514 - ; 25.515 -// Set if result is valid at end of M stage 25.516 -assign m_bypass_enable = x_bypass_enable 25.517 -`ifdef CFG_PL_BARREL_SHIFT_ENABLED 25.518 - | shift 25.519 -`endif 25.520 - | cmp 25.521 - ; 25.522 -// Register file read port 0 25.523 -assign read_enable_0 = ~(op_bi | op_calli); 25.524 -assign read_idx_0 = instruction[25:21]; 25.525 -// Register file read port 1 25.526 -assign read_enable_1 = ~(op_bi | op_calli | load); 25.527 -assign read_idx_1 = instruction[20:16]; 25.528 -// Register file write port 25.529 -assign write_enable = ~(bra | op_raise | store | op_wcsr); 25.530 -assign write_idx = call 25.531 - ? 5'd29 25.532 - : instruction[31] == 1'b0 25.533 - ? instruction[20:16] 25.534 - : instruction[15:11]; 25.535 - 25.536 -// Size of load/stores 25.537 -assign size = instruction[27:26]; 25.538 -// Whether to sign or zero extend 25.539 -assign sign_extend = instruction[28]; 25.540 -// Set adder_op to 1 to perform a subtraction 25.541 -assign adder_op = op_sub | op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne | bra; 25.542 -// Logic operation (and, or, etc) 25.543 -assign logic_op = instruction[29:26]; 25.544 -`ifdef CFG_PL_BARREL_SHIFT_ENABLED 25.545 -// Shift direction 25.546 -assign direction = instruction[29]; 25.547 -`endif 25.548 -// Control flow microcodes 25.549 -assign branch = bra | call; 25.550 -assign branch_reg = op_call | op_b; 25.551 -assign condition = instruction[28:26]; 25.552 -`ifdef CFG_DEBUG_ENABLED 25.553 -assign break_opcode = op_raise & ~instruction[2]; 25.554 -`endif 25.555 -assign scall = op_raise & instruction[2]; 25.556 -assign eret = op_b & (instruction[25:21] == 5'd30); 25.557 -`ifdef CFG_DEBUG_ENABLED 25.558 -assign bret = op_b & (instruction[25:21] == 5'd31); 25.559 -`endif 25.560 -`ifdef CFG_USER_ENABLED 25.561 -// Extract user opcode 25.562 -assign user_opcode = instruction[10:0]; 25.563 -`endif 25.564 -// CSR read/write 25.565 -assign csr_write_enable = op_wcsr; 25.566 - 25.567 -// Extract immediate from instruction 25.568 - 25.569 -assign sign_extend_immediate = ~(op_and | op_cmpgeu | op_cmpgu | op_nor | op_or | op_xnor | op_xor); 25.570 -assign select_high_immediate = op_andhi | op_orhi; 25.571 -assign select_call_immediate = instruction[31]; 25.572 - 25.573 -assign high_immediate = {instruction[15:0], 16'h0000}; 25.574 -assign extended_immediate = {{16{sign_extend_immediate & instruction[15]}}, instruction[15:0]}; 25.575 -assign call_immediate = {{6{instruction[25]}}, instruction[25:0]}; 25.576 -assign branch_immediate = {{16{instruction[15]}}, instruction[15:0]}; 25.577 - 25.578 -assign immediate = select_high_immediate == `TRUE 25.579 - ? high_immediate 25.580 - : extended_immediate; 25.581 - 25.582 -assign branch_offset = select_call_immediate == `TRUE 25.583 - ? call_immediate 25.584 - : branch_immediate; 25.585 - 25.586 -endmodule 25.587 -
26.1 diff -r 252df75c8f67 -r c336e674a37e lm32_dp_ram.v 26.2 --- a/lm32_dp_ram.v Sun Mar 06 21:17:31 2011 +0000 26.3 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 26.4 @@ -1,35 +0,0 @@ 26.5 -module lm32_dp_ram( 26.6 - clk_i, 26.7 - rst_i, 26.8 - we_i, 26.9 - waddr_i, 26.10 - wdata_i, 26.11 - raddr_i, 26.12 - rdata_o); 26.13 - 26.14 -parameter addr_width = 32; 26.15 -parameter addr_depth = 1024; 26.16 -parameter data_width = 8; 26.17 - 26.18 -input clk_i; 26.19 -input rst_i; 26.20 -input we_i; 26.21 -input [addr_width-1:0] waddr_i; 26.22 -input [data_width-1:0] wdata_i; 26.23 -input [addr_width-1:0] raddr_i; 26.24 -output [data_width-1:0] rdata_o; 26.25 - 26.26 -reg [data_width-1:0] ram[addr_depth-1:0]; 26.27 - 26.28 -reg [addr_width-1:0] raddr_r; 26.29 -assign rdata_o = ram[raddr_r]; 26.30 - 26.31 -always @ (posedge clk_i) 26.32 -begin 26.33 - if (we_i) 26.34 - ram[waddr_i] <= wdata_i; 26.35 - raddr_r <= raddr_i; 26.36 -end 26.37 - 26.38 -endmodule 26.39 -
27.1 diff -r 252df75c8f67 -r c336e674a37e lm32_functions.v 27.2 --- a/lm32_functions.v Sun Mar 06 21:17:31 2011 +0000 27.3 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 27.4 @@ -1,49 +0,0 @@ 27.5 -// ============================================================================= 27.6 -// COPYRIGHT NOTICE 27.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 27.8 -// ALL RIGHTS RESERVED 27.9 -// This confidential and proprietary software may be used only as authorised by 27.10 -// a licensing agreement from Lattice Semiconductor Corporation. 27.11 -// The entire notice above must be reproduced on all authorized copies and 27.12 -// copies may only be made to the extent permitted by a licensing agreement from 27.13 -// Lattice Semiconductor Corporation. 27.14 -// 27.15 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 27.16 -// 5555 NE Moore Court 408-826-6000 (other locations) 27.17 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 27.18 -// U.S.A email: techsupport@latticesemi.com 27.19 -// =============================================================================/ 27.20 -// FILE DETAILS 27.21 -// Project : LatticeMico32 27.22 -// File : lm32_functions.v 27.23 -// Title : Common functions 27.24 -// Version : 6.1.17 27.25 -// : Initial Release 27.26 -// Version : 7.0SP2, 3.0 27.27 -// : No Change 27.28 -// Version : 3.5 27.29 -// : Added function to generate log-of-two that rounds-up to 27.30 -// : power-of-two 27.31 -// ============================================================================= 27.32 - 27.33 -function integer clogb2; 27.34 -input [31:0] value; 27.35 -begin 27.36 - for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) 27.37 - value = value >> 1; 27.38 -end 27.39 -endfunction 27.40 - 27.41 -function integer clogb2_v1; 27.42 -input [31:0] value; 27.43 -reg [31:0] i; 27.44 -reg [31:0] temp; 27.45 -begin 27.46 - temp = 0; 27.47 - i = 0; 27.48 - for (i = 0; temp < value; i = i + 1) 27.49 - temp = 1<<i; 27.50 - clogb2_v1 = i-1; 27.51 -end 27.52 -endfunction 27.53 -
28.1 diff -r 252df75c8f67 -r c336e674a37e lm32_icache.v 28.2 --- a/lm32_icache.v Sun Mar 06 21:17:31 2011 +0000 28.3 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 28.4 @@ -1,494 +0,0 @@ 28.5 -// ============================================================================= 28.6 -// COPYRIGHT NOTICE 28.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 28.8 -// ALL RIGHTS RESERVED 28.9 -// This confidential and proprietary software may be used only as authorised by 28.10 -// a licensing agreement from Lattice Semiconductor Corporation. 28.11 -// The entire notice above must be reproduced on all authorized copies and 28.12 -// copies may only be made to the extent permitted by a licensing agreement from 28.13 -// Lattice Semiconductor Corporation. 28.14 -// 28.15 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 28.16 -// 5555 NE Moore Court 408-826-6000 (other locations) 28.17 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 28.18 -// U.S.A email: techsupport@latticesemi.com 28.19 -// =============================================================================/ 28.20 -// FILE DETAILS 28.21 -// Project : LatticeMico32 28.22 -// File : lm32_icache.v 28.23 -// Title : Instruction cache 28.24 -// Dependencies : lm32_include.v 28.25 -// 28.26 -// Version 3.5 28.27 -// 1. Bug Fix: Instruction cache flushes issued from Instruction Inline Memory 28.28 -// cause segmentation fault due to incorrect fetches. 28.29 -// 28.30 -// Version 3.1 28.31 -// 1. Feature: Support for user-selected resource usage when implementing 28.32 -// cache memory. Additional parameters must be defined when invoking module 28.33 -// lm32_ram. Instruction cache miss mechanism is dependent on branch 28.34 -// prediction being performed in D stage of pipeline. 28.35 -// 28.36 -// Version 7.0SP2, 3.0 28.37 -// No change 28.38 -// ============================================================================= 28.39 - 28.40 -`include "lm32_include.v" 28.41 - 28.42 -`ifdef CFG_ICACHE_ENABLED 28.43 - 28.44 -`define LM32_IC_ADDR_OFFSET_RNG addr_offset_msb:addr_offset_lsb 28.45 -`define LM32_IC_ADDR_SET_RNG addr_set_msb:addr_set_lsb 28.46 -`define LM32_IC_ADDR_TAG_RNG addr_tag_msb:addr_tag_lsb 28.47 -`define LM32_IC_ADDR_IDX_RNG addr_set_msb:addr_offset_lsb 28.48 - 28.49 -`define LM32_IC_TMEM_ADDR_WIDTH addr_set_width 28.50 -`define LM32_IC_TMEM_ADDR_RNG (`LM32_IC_TMEM_ADDR_WIDTH-1):0 28.51 -`define LM32_IC_DMEM_ADDR_WIDTH (addr_offset_width+addr_set_width) 28.52 -`define LM32_IC_DMEM_ADDR_RNG (`LM32_IC_DMEM_ADDR_WIDTH-1):0 28.53 - 28.54 -`define LM32_IC_TAGS_WIDTH (addr_tag_width+1) 28.55 -`define LM32_IC_TAGS_RNG (`LM32_IC_TAGS_WIDTH-1):0 28.56 -`define LM32_IC_TAGS_TAG_RNG (`LM32_IC_TAGS_WIDTH-1):1 28.57 -`define LM32_IC_TAGS_VALID_RNG 0 28.58 - 28.59 -`define LM32_IC_STATE_RNG 3:0 28.60 -`define LM32_IC_STATE_FLUSH_INIT 4'b0001 28.61 -`define LM32_IC_STATE_FLUSH 4'b0010 28.62 -`define LM32_IC_STATE_CHECK 4'b0100 28.63 -`define LM32_IC_STATE_REFILL 4'b1000 28.64 - 28.65 -///////////////////////////////////////////////////// 28.66 -// Module interface 28.67 -///////////////////////////////////////////////////// 28.68 - 28.69 -module lm32_icache ( 28.70 - // ----- Inputs ----- 28.71 - clk_i, 28.72 - rst_i, 28.73 - stall_a, 28.74 - stall_f, 28.75 - address_a, 28.76 - address_f, 28.77 - read_enable_f, 28.78 - refill_ready, 28.79 - refill_data, 28.80 - iflush, 28.81 -`ifdef CFG_IROM_ENABLED 28.82 - select_f, 28.83 -`endif 28.84 - valid_d, 28.85 - branch_predict_taken_d, 28.86 - // ----- Outputs ----- 28.87 - stall_request, 28.88 - restart_request, 28.89 - refill_request, 28.90 - refill_address, 28.91 - refilling, 28.92 - inst 28.93 - ); 28.94 - 28.95 -///////////////////////////////////////////////////// 28.96 -// Parameters 28.97 -///////////////////////////////////////////////////// 28.98 - 28.99 -parameter associativity = 1; // Associativity of the cache (Number of ways) 28.100 -parameter sets = 512; // Number of sets 28.101 -parameter bytes_per_line = 16; // Number of bytes per cache line 28.102 -parameter base_address = 0; // Base address of cachable memory 28.103 -parameter limit = 0; // Limit (highest address) of cachable memory 28.104 - 28.105 -localparam addr_offset_width = clogb2(bytes_per_line)-1-2; 28.106 -localparam addr_set_width = clogb2(sets)-1; 28.107 -localparam addr_offset_lsb = 2; 28.108 -localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1); 28.109 -localparam addr_set_lsb = (addr_offset_msb+1); 28.110 -localparam addr_set_msb = (addr_set_lsb+addr_set_width-1); 28.111 -localparam addr_tag_lsb = (addr_set_msb+1); 28.112 -localparam addr_tag_msb = clogb2(`CFG_ICACHE_LIMIT-`CFG_ICACHE_BASE_ADDRESS)-1; 28.113 -localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1); 28.114 - 28.115 -///////////////////////////////////////////////////// 28.116 -// Inputs 28.117 -///////////////////////////////////////////////////// 28.118 - 28.119 -input clk_i; // Clock 28.120 -input rst_i; // Reset 28.121 - 28.122 -input stall_a; // Stall instruction in A stage 28.123 -input stall_f; // Stall instruction in F stage 28.124 - 28.125 -input valid_d; // Valid instruction in D stage 28.126 -input branch_predict_taken_d; // Instruction in D stage is a branch and is predicted taken 28.127 - 28.128 -input [`LM32_PC_RNG] address_a; // Address of instruction in A stage 28.129 -input [`LM32_PC_RNG] address_f; // Address of instruction in F stage 28.130 -input read_enable_f; // Indicates if cache access is valid 28.131 - 28.132 -input refill_ready; // Next word of refill data is ready 28.133 -input [`LM32_INSTRUCTION_RNG] refill_data; // Data to refill the cache with 28.134 - 28.135 -input iflush; // Flush the cache 28.136 -`ifdef CFG_IROM_ENABLED 28.137 -input select_f; // Instruction in F stage is mapped through instruction cache 28.138 -`endif 28.139 - 28.140 -///////////////////////////////////////////////////// 28.141 -// Outputs 28.142 -///////////////////////////////////////////////////// 28.143 - 28.144 -output stall_request; // Request to stall the pipeline 28.145 -wire stall_request; 28.146 -output restart_request; // Request to restart instruction that caused the cache miss 28.147 -reg restart_request; 28.148 -output refill_request; // Request to refill a cache line 28.149 -wire refill_request; 28.150 -output [`LM32_PC_RNG] refill_address; // Base address of cache refill 28.151 -reg [`LM32_PC_RNG] refill_address; 28.152 -output refilling; // Indicates the instruction cache is currently refilling 28.153 -reg refilling; 28.154 -output [`LM32_INSTRUCTION_RNG] inst; // Instruction read from cache 28.155 -wire [`LM32_INSTRUCTION_RNG] inst; 28.156 - 28.157 -///////////////////////////////////////////////////// 28.158 -// Internal nets and registers 28.159 -///////////////////////////////////////////////////// 28.160 - 28.161 -wire enable; 28.162 -wire [0:associativity-1] way_mem_we; 28.163 -wire [`LM32_INSTRUCTION_RNG] way_data[0:associativity-1]; 28.164 -wire [`LM32_IC_TAGS_TAG_RNG] way_tag[0:associativity-1]; 28.165 -wire [0:associativity-1] way_valid; 28.166 -wire [0:associativity-1] way_match; 28.167 -wire miss; 28.168 - 28.169 -wire [`LM32_IC_TMEM_ADDR_RNG] tmem_read_address; 28.170 -wire [`LM32_IC_TMEM_ADDR_RNG] tmem_write_address; 28.171 -wire [`LM32_IC_DMEM_ADDR_RNG] dmem_read_address; 28.172 -wire [`LM32_IC_DMEM_ADDR_RNG] dmem_write_address; 28.173 -wire [`LM32_IC_TAGS_RNG] tmem_write_data; 28.174 - 28.175 -reg [`LM32_IC_STATE_RNG] state; 28.176 -wire flushing; 28.177 -wire check; 28.178 -wire refill; 28.179 - 28.180 -reg [associativity-1:0] refill_way_select; 28.181 -reg [`LM32_IC_ADDR_OFFSET_RNG] refill_offset; 28.182 -wire last_refill; 28.183 -reg [`LM32_IC_TMEM_ADDR_RNG] flush_set; 28.184 - 28.185 -genvar i; 28.186 - 28.187 -///////////////////////////////////////////////////// 28.188 -// Functions 28.189 -///////////////////////////////////////////////////// 28.190 - 28.191 -`include "lm32_functions.v" 28.192 - 28.193 -///////////////////////////////////////////////////// 28.194 -// Instantiations 28.195 -///////////////////////////////////////////////////// 28.196 - 28.197 - generate 28.198 - for (i = 0; i < associativity; i = i + 1) 28.199 - begin : memories 28.200 - 28.201 - lm32_ram 28.202 - #( 28.203 - // ----- Parameters ------- 28.204 - .data_width (32), 28.205 - .address_width (`LM32_IC_DMEM_ADDR_WIDTH) 28.206 -`ifdef PLATFORM_LATTICE 28.207 - , 28.208 - `ifdef CFG_ICACHE_DAT_USE_DP_TRUE 28.209 - .RAM_IMPLEMENTATION ("EBR"), 28.210 - .RAM_TYPE ("RAM_DP_TRUE") 28.211 - `else 28.212 - `ifdef CFG_ICACHE_DAT_USE_DP 28.213 - .RAM_IMPLEMENTATION ("EBR"), 28.214 - .RAM_TYPE ("RAM_DP") 28.215 - `else 28.216 - `ifdef CFG_ICACHE_DAT_USE_SLICE 28.217 - .RAM_IMPLEMENTATION ("SLICE") 28.218 - `else 28.219 - .RAM_IMPLEMENTATION ("AUTO") 28.220 - `endif 28.221 - `endif 28.222 - `endif 28.223 -`endif 28.224 - ) 28.225 - way_0_data_ram 28.226 - ( 28.227 - // ----- Inputs ------- 28.228 - .read_clk (clk_i), 28.229 - .write_clk (clk_i), 28.230 - .reset (rst_i), 28.231 - .read_address (dmem_read_address), 28.232 - .enable_read (enable), 28.233 - .write_address (dmem_write_address), 28.234 - .enable_write (`TRUE), 28.235 - .write_enable (way_mem_we[i]), 28.236 - .write_data (refill_data), 28.237 - // ----- Outputs ------- 28.238 - .read_data (way_data[i]) 28.239 - ); 28.240 - 28.241 - lm32_ram 28.242 - #( 28.243 - // ----- Parameters ------- 28.244 - .data_width (`LM32_IC_TAGS_WIDTH), 28.245 - .address_width (`LM32_IC_TMEM_ADDR_WIDTH) 28.246 -`ifdef PLATFORM_LATTICE 28.247 - , 28.248 - `ifdef CFG_ICACHE_DAT_USE_DP_TRUE 28.249 - .RAM_IMPLEMENTATION ("EBR"), 28.250 - .RAM_TYPE ("RAM_DP_TRUE") 28.251 - `else 28.252 - `ifdef CFG_ICACHE_DAT_USE_DP 28.253 - .RAM_IMPLEMENTATION ("EBR"), 28.254 - .RAM_TYPE ("RAM_DP") 28.255 - `else 28.256 - `ifdef CFG_ICACHE_DAT_USE_SLICE 28.257 - .RAM_IMPLEMENTATION ("SLICE") 28.258 - `else 28.259 - .RAM_IMPLEMENTATION ("AUTO") 28.260 - `endif 28.261 - `endif 28.262 - `endif 28.263 -`endif 28.264 - ) 28.265 - way_0_tag_ram 28.266 - ( 28.267 - // ----- Inputs ------- 28.268 - .read_clk (clk_i), 28.269 - .write_clk (clk_i), 28.270 - .reset (rst_i), 28.271 - .read_address (tmem_read_address), 28.272 - .enable_read (enable), 28.273 - .write_address (tmem_write_address), 28.274 - .enable_write (`TRUE), 28.275 - .write_enable (way_mem_we[i] | flushing), 28.276 - .write_data (tmem_write_data), 28.277 - // ----- Outputs ------- 28.278 - .read_data ({way_tag[i], way_valid[i]}) 28.279 - ); 28.280 - 28.281 - end 28.282 -endgenerate 28.283 - 28.284 -///////////////////////////////////////////////////// 28.285 -// Combinational logic 28.286 -///////////////////////////////////////////////////// 28.287 - 28.288 -// Compute which ways in the cache match the address address being read 28.289 -generate 28.290 - for (i = 0; i < associativity; i = i + 1) 28.291 - begin : match 28.292 -assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_f[`LM32_IC_ADDR_TAG_RNG], `TRUE}); 28.293 - end 28.294 -endgenerate 28.295 - 28.296 -// Select data from way that matched the address being read 28.297 -generate 28.298 - if (associativity == 1) 28.299 - begin : inst_1 28.300 -assign inst = way_match[0] ? way_data[0] : 32'b0; 28.301 - end 28.302 - else if (associativity == 2) 28.303 - begin : inst_2 28.304 -assign inst = way_match[0] ? way_data[0] : (way_match[1] ? way_data[1] : 32'b0); 28.305 - end 28.306 -endgenerate 28.307 - 28.308 -// Compute address to use to index into the data memories 28.309 -generate 28.310 - if (bytes_per_line > 4) 28.311 -assign dmem_write_address = {refill_address[`LM32_IC_ADDR_SET_RNG], refill_offset}; 28.312 - else 28.313 -assign dmem_write_address = refill_address[`LM32_IC_ADDR_SET_RNG]; 28.314 -endgenerate 28.315 - 28.316 -assign dmem_read_address = address_a[`LM32_IC_ADDR_IDX_RNG]; 28.317 - 28.318 -// Compute address to use to index into the tag memories 28.319 -assign tmem_read_address = address_a[`LM32_IC_ADDR_SET_RNG]; 28.320 -assign tmem_write_address = flushing 28.321 - ? flush_set 28.322 - : refill_address[`LM32_IC_ADDR_SET_RNG]; 28.323 - 28.324 -// Compute signal to indicate when we are on the last refill accesses 28.325 -generate 28.326 - if (bytes_per_line > 4) 28.327 -assign last_refill = refill_offset == {addr_offset_width{1'b1}}; 28.328 - else 28.329 -assign last_refill = `TRUE; 28.330 -endgenerate 28.331 - 28.332 -// Compute data and tag memory access enable 28.333 -assign enable = (stall_a == `FALSE); 28.334 - 28.335 -// Compute data and tag memory write enables 28.336 -generate 28.337 - if (associativity == 1) 28.338 - begin : we_1 28.339 -assign way_mem_we[0] = (refill_ready == `TRUE); 28.340 - end 28.341 - else 28.342 - begin : we_2 28.343 -assign way_mem_we[0] = (refill_ready == `TRUE) && (refill_way_select[0] == `TRUE); 28.344 -assign way_mem_we[1] = (refill_ready == `TRUE) && (refill_way_select[1] == `TRUE); 28.345 - end 28.346 -endgenerate 28.347 - 28.348 -// On the last refill cycle set the valid bit, for all other writes it should be cleared 28.349 -assign tmem_write_data[`LM32_IC_TAGS_VALID_RNG] = last_refill & !flushing; 28.350 -assign tmem_write_data[`LM32_IC_TAGS_TAG_RNG] = refill_address[`LM32_IC_ADDR_TAG_RNG]; 28.351 - 28.352 -// Signals that indicate which state we are in 28.353 -assign flushing = |state[1:0]; 28.354 -assign check = state[2]; 28.355 -assign refill = state[3]; 28.356 - 28.357 -assign miss = (~(|way_match)) && (read_enable_f == `TRUE) && (stall_f == `FALSE) && !(valid_d && branch_predict_taken_d); 28.358 -assign stall_request = (check == `FALSE); 28.359 -assign refill_request = (refill == `TRUE); 28.360 - 28.361 -///////////////////////////////////////////////////// 28.362 -// Sequential logic 28.363 -///////////////////////////////////////////////////// 28.364 - 28.365 -// Record way selected for replacement on a cache miss 28.366 -generate 28.367 - if (associativity >= 2) 28.368 - begin : way_select 28.369 -always @(posedge clk_i `CFG_RESET_SENSITIVITY) 28.370 -begin 28.371 - if (rst_i == `TRUE) 28.372 - refill_way_select <= {{associativity-1{1'b0}}, 1'b1}; 28.373 - else 28.374 - begin 28.375 - if (miss == `TRUE) 28.376 - refill_way_select <= {refill_way_select[0], refill_way_select[1]}; 28.377 - end 28.378 -end 28.379 - end 28.380 -endgenerate 28.381 - 28.382 -// Record whether we are refilling 28.383 -always @(posedge clk_i `CFG_RESET_SENSITIVITY) 28.384 -begin 28.385 - if (rst_i == `TRUE) 28.386 - refilling <= `FALSE; 28.387 - else 28.388 - refilling <= refill; 28.389 -end 28.390 - 28.391 -// Instruction cache control FSM 28.392 -always @(posedge clk_i `CFG_RESET_SENSITIVITY) 28.393 -begin 28.394 - if (rst_i == `TRUE) 28.395 - begin 28.396 - state <= `LM32_IC_STATE_FLUSH_INIT; 28.397 - flush_set <= {`LM32_IC_TMEM_ADDR_WIDTH{1'b1}}; 28.398 - refill_address <= {`LM32_PC_WIDTH{1'bx}}; 28.399 - restart_request <= `FALSE; 28.400 - end 28.401 - else 28.402 - begin 28.403 - case (state) 28.404 - 28.405 - // Flush the cache for the first time after reset 28.406 - `LM32_IC_STATE_FLUSH_INIT: 28.407 - begin 28.408 - if (flush_set == {`LM32_IC_TMEM_ADDR_WIDTH{1'b0}}) 28.409 - state <= `LM32_IC_STATE_CHECK; 28.410 - flush_set <= flush_set - 1'b1; 28.411 - end 28.412 - 28.413 - // Flush the cache in response to an write to the ICC CSR 28.414 - `LM32_IC_STATE_FLUSH: 28.415 - begin 28.416 - if (flush_set == {`LM32_IC_TMEM_ADDR_WIDTH{1'b0}}) 28.417 -`ifdef CFG_IROM_ENABLED 28.418 - if (select_f) 28.419 - state <= `LM32_IC_STATE_REFILL; 28.420 - else 28.421 -`endif 28.422 - state <= `LM32_IC_STATE_CHECK; 28.423 - 28.424 - flush_set <= flush_set - 1'b1; 28.425 - end 28.426 - 28.427 - // Check for cache misses 28.428 - `LM32_IC_STATE_CHECK: 28.429 - begin 28.430 - if (stall_a == `FALSE) 28.431 - restart_request <= `FALSE; 28.432 - if (iflush == `TRUE) 28.433 - begin 28.434 - refill_address <= address_f; 28.435 - state <= `LM32_IC_STATE_FLUSH; 28.436 - end 28.437 - else if (miss == `TRUE) 28.438 - begin 28.439 - refill_address <= address_f; 28.440 - state <= `LM32_IC_STATE_REFILL; 28.441 - end 28.442 - end 28.443 - 28.444 - // Refill a cache line 28.445 - `LM32_IC_STATE_REFILL: 28.446 - begin 28.447 - if (refill_ready == `TRUE) 28.448 - begin 28.449 - if (last_refill == `TRUE) 28.450 - begin 28.451 - restart_request <= `TRUE; 28.452 - state <= `LM32_IC_STATE_CHECK; 28.453 - end 28.454 - end 28.455 - end 28.456 - 28.457 - endcase 28.458 - end 28.459 -end 28.460 - 28.461 -generate 28.462 - if (bytes_per_line > 4) 28.463 - begin 28.464 -// Refill offset 28.465 -always @(posedge clk_i `CFG_RESET_SENSITIVITY) 28.466 -begin 28.467 - if (rst_i == `TRUE) 28.468 - refill_offset <= {addr_offset_width{1'b0}}; 28.469 - else 28.470 - begin 28.471 - case (state) 28.472 - 28.473 - // Check for cache misses 28.474 - `LM32_IC_STATE_CHECK: 28.475 - begin 28.476 - if (iflush == `TRUE) 28.477 - refill_offset <= {addr_offset_width{1'b0}}; 28.478 - else if (miss == `TRUE) 28.479 - refill_offset <= {addr_offset_width{1'b0}}; 28.480 - end 28.481 - 28.482 - // Refill a cache line 28.483 - `LM32_IC_STATE_REFILL: 28.484 - begin 28.485 - if (refill_ready == `TRUE) 28.486 - refill_offset <= refill_offset + 1'b1; 28.487 - end 28.488 - 28.489 - endcase 28.490 - end 28.491 -end 28.492 - end 28.493 -endgenerate 28.494 - 28.495 -endmodule 28.496 - 28.497 -`endif 28.498 -
29.1 diff -r 252df75c8f67 -r c336e674a37e lm32_include.v 29.2 --- a/lm32_include.v Sun Mar 06 21:17:31 2011 +0000 29.3 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 29.4 @@ -1,368 +0,0 @@ 29.5 -// ============================================================================= 29.6 -// COPYRIGHT NOTICE 29.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 29.8 -// ALL RIGHTS RESERVED 29.9 -// This confidential and proprietary software may be used only as authorised by 29.10 -// a licensing agreement from Lattice Semiconductor Corporation. 29.11 -// The entire notice above must be reproduced on all authorized copies and 29.12 -// copies may only be made to the extent permitted by a licensing agreement from 29.13 -// Lattice Semiconductor Corporation. 29.14 -// 29.15 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 29.16 -// 5555 NE Moore Court 408-826-6000 (other locations) 29.17 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 29.18 -// U.S.A email: techsupport@latticesemi.com 29.19 -// =============================================================================/ 29.20 -// FILE DETAILS 29.21 -// Project : LatticeMico32 29.22 -// File : lm32_include.v 29.23 -// Title : CPU global macros 29.24 -// Version : 6.1.17 29.25 -// : Initial Release 29.26 -// Version : 7.0SP2, 3.0 29.27 -// : No Change 29.28 -// Version : 3.1 29.29 -// : No Change 29.30 -// Version : 3.2 29.31 -// : No Change 29.32 -// Version : 3.3 29.33 -// : Support for extended configuration register 29.34 -// ============================================================================= 29.35 - 29.36 -`ifdef LM32_INCLUDE_V 29.37 -`else 29.38 -`define LM32_INCLUDE_V 29.39 - 29.40 -// 29.41 -// Common configuration options 29.42 -// 29.43 - 29.44 -`define CFG_EBA_RESET 32'h00000000 29.45 -`define CFG_DEBA_RESET 32'h10000000 29.46 - 29.47 -`define CFG_PL_MULTIPLY_ENABLED 29.48 -`define CFG_PL_BARREL_SHIFT_ENABLED 29.49 -`define CFG_SIGN_EXTEND_ENABLED 29.50 -`define CFG_MC_DIVIDE_ENABLED 29.51 -`define CFG_EBR_POSEDGE_REGISTER_FILE 29.52 - 29.53 -// [found by Milkymist dev'rs] 29.54 -// Bug in Xst: 29.55 -// CFG_ICACHE_ASSOCIATIVITY=2 => works in most cases (random crash on complex software) 29.56 -// CFG_ICACHE_ASSOCIATIVITY=1 => disaster, CPU will not work at all 29.57 -// Works 100% OK with expensive synthesizers. 29.58 -`define CFG_ICACHE_ENABLED 29.59 -`define CFG_ICACHE_ASSOCIATIVITY 1 29.60 -`define CFG_ICACHE_SETS 256 29.61 -`define CFG_ICACHE_BYTES_PER_LINE 16 29.62 -`define CFG_ICACHE_BASE_ADDRESS 32'h0 29.63 -`define CFG_ICACHE_LIMIT 32'h7FFF_FFFF 29.64 - 29.65 -`define CFG_DCACHE_ENABLED 29.66 -`define CFG_DCACHE_ASSOCIATIVITY 1 29.67 -`define CFG_DCACHE_SETS 256 29.68 -`define CFG_DCACHE_BYTES_PER_LINE 16 29.69 -`define CFG_DCACHE_BASE_ADDRESS 32'h0 29.70 -`define CFG_DCACHE_LIMIT 32'h0FFF_FFFF 29.71 - 29.72 -// Enable Debugging 29.73 -//`define CFG_JTAG_ENABLED 29.74 -//`define CFG_JTAG_UART_ENABLED 29.75 -//`define CFG_DEBUG_ENABLED 29.76 -//`define CFG_HW_DEBUG_ENABLED 29.77 -//`define CFG_ROM_DEBUG_ENABLED 29.78 -//`define CFG_BREAKPOINTS 32'h0 29.79 -//`define CFG_WATCHPOINTS 32'h0 29.80 - 29.81 -// 29.82 -// End of common configuration options 29.83 -// 29.84 - 29.85 -`ifdef TRUE 29.86 -`else 29.87 -`define TRUE 1'b1 29.88 -`define FALSE 1'b0 29.89 -`define TRUE_N 1'b0 29.90 -`define FALSE_N 1'b1 29.91 -`endif 29.92 - 29.93 -// Wishbone configuration 29.94 -`define CFG_IWB_ENABLED 29.95 -`define CFG_DWB_ENABLED 29.96 - 29.97 -// Data-path width 29.98 -`define LM32_WORD_WIDTH 32 29.99 -`define LM32_WORD_RNG (`LM32_WORD_WIDTH-1):0 29.100 -`define LM32_SHIFT_WIDTH 5 29.101 -`define LM32_SHIFT_RNG (`LM32_SHIFT_WIDTH-1):0 29.102 -`define LM32_BYTE_SELECT_WIDTH 4 29.103 -`define LM32_BYTE_SELECT_RNG (`LM32_BYTE_SELECT_WIDTH-1):0 29.104 - 29.105 -// Register file size 29.106 -`define LM32_REGISTERS 32 29.107 -`define LM32_REG_IDX_WIDTH 5 29.108 -`define LM32_REG_IDX_RNG (`LM32_REG_IDX_WIDTH-1):0 29.109 - 29.110 -// Standard register numbers 29.111 -`define LM32_RA_REG `LM32_REG_IDX_WIDTH'd29 29.112 -`define LM32_EA_REG `LM32_REG_IDX_WIDTH'd30 29.113 -`define LM32_BA_REG `LM32_REG_IDX_WIDTH'd31 29.114 - 29.115 -// Range of Program Counter. Two LSBs are always 0. 29.116 -// `ifdef CFG_ICACHE_ENABLED 29.117 -// `define LM32_PC_WIDTH (clogb2(`CFG_ICACHE_LIMIT-`CFG_ICACHE_BASE_ADDRESS)-2) 29.118 -// `else 29.119 -// `ifdef CFG_IWB_ENABLED 29.120 -`define LM32_PC_WIDTH (`LM32_WORD_WIDTH-2) 29.121 -// `else 29.122 -// `define LM32_PC_WIDTH `LM32_IROM_ADDRESS_WIDTH 29.123 -// `endif 29.124 -// `endif 29.125 -`define LM32_PC_RNG (`LM32_PC_WIDTH+2-1):2 29.126 - 29.127 -// Range of an instruction 29.128 -`define LM32_INSTRUCTION_WIDTH 32 29.129 -`define LM32_INSTRUCTION_RNG (`LM32_INSTRUCTION_WIDTH-1):0 29.130 - 29.131 -// Adder operation 29.132 -`define LM32_ADDER_OP_ADD 1'b0 29.133 -`define LM32_ADDER_OP_SUBTRACT 1'b1 29.134 - 29.135 -// Shift direction 29.136 -`define LM32_SHIFT_OP_RIGHT 1'b0 29.137 -`define LM32_SHIFT_OP_LEFT 1'b1 29.138 - 29.139 -// Bus errors 29.140 -//`define CFG_BUS_ERRORS_ENABLED 29.141 - 29.142 -// Derive macro that indicates whether we have single-stepping or not 29.143 -`ifdef CFG_ROM_DEBUG_ENABLED 29.144 -`define LM32_SINGLE_STEP_ENABLED 29.145 -`else 29.146 -`ifdef CFG_HW_DEBUG_ENABLED 29.147 -`define LM32_SINGLE_STEP_ENABLED 29.148 -`endif 29.149 -`endif 29.150 - 29.151 -// Derive macro that indicates whether JTAG interface is required 29.152 -`ifdef CFG_JTAG_UART_ENABLED 29.153 -`define LM32_JTAG_ENABLED 29.154 -`else 29.155 -`ifdef CFG_DEBUG_ENABLED 29.156 -`define LM32_JTAG_ENABLED 29.157 -`else 29.158 -`endif 29.159 -`endif 29.160 - 29.161 -// Derive macro that indicates whether we have a barrel-shifter or not 29.162 -`ifdef CFG_PL_BARREL_SHIFT_ENABLED 29.163 -`define LM32_BARREL_SHIFT_ENABLED 29.164 -`else // CFG_PL_BARREL_SHIFT_ENABLED 29.165 -`ifdef CFG_MC_BARREL_SHIFT_ENABLED 29.166 -`define LM32_BARREL_SHIFT_ENABLED 29.167 -`else 29.168 -`define LM32_NO_BARREL_SHIFT 29.169 -`endif 29.170 -`endif // CFG_PL_BARREL_SHIFT_ENABLED 29.171 - 29.172 -// Derive macro that indicates whether we have a multiplier or not 29.173 -`ifdef CFG_PL_MULTIPLY_ENABLED 29.174 -`define LM32_MULTIPLY_ENABLED 29.175 -`else 29.176 -`ifdef CFG_MC_MULTIPLY_ENABLED 29.177 -`define LM32_MULTIPLY_ENABLED 29.178 -`endif 29.179 -`endif 29.180 - 29.181 -// Derive a macro that indicates whether or not the multi-cycle arithmetic unit is required 29.182 -`ifdef CFG_MC_DIVIDE_ENABLED 29.183 -`define LM32_MC_ARITHMETIC_ENABLED 29.184 -`endif 29.185 -`ifdef CFG_MC_MULTIPLY_ENABLED 29.186 -`define LM32_MC_ARITHMETIC_ENABLED 29.187 -`endif 29.188 -`ifdef CFG_MC_BARREL_SHIFT_ENABLED 29.189 -`define LM32_MC_ARITHMETIC_ENABLED 29.190 -`endif 29.191 - 29.192 -// Derive macro that indicates if we are using an EBR register file 29.193 -`ifdef CFG_EBR_POSEDGE_REGISTER_FILE 29.194 -`define LM32_EBR_REGISTER_FILE 29.195 -`endif 29.196 -`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE 29.197 -`define LM32_EBR_REGISTER_FILE 29.198 -`endif 29.199 - 29.200 -// Revision number 29.201 -`define LM32_REVISION 6'h02 29.202 - 29.203 -// Logical operations - Function encoded directly in instruction 29.204 -`define LM32_LOGIC_OP_RNG 3:0 29.205 - 29.206 -// Conditions for conditional branches 29.207 -`define LM32_CONDITION_WIDTH 3 29.208 -`define LM32_CONDITION_RNG (`LM32_CONDITION_WIDTH-1):0 29.209 -`define LM32_CONDITION_E 3'b001 29.210 -`define LM32_CONDITION_G 3'b010 29.211 -`define LM32_CONDITION_GE 3'b011 29.212 -`define LM32_CONDITION_GEU 3'b100 29.213 -`define LM32_CONDITION_GU 3'b101 29.214 -`define LM32_CONDITION_NE 3'b111 29.215 -`define LM32_CONDITION_U1 3'b000 29.216 -`define LM32_CONDITION_U2 3'b110 29.217 - 29.218 -// Size of load or store instruction - Encoding corresponds to opcode 29.219 -`define LM32_SIZE_WIDTH 2 29.220 -`define LM32_SIZE_RNG 1:0 29.221 -`define LM32_SIZE_BYTE 2'b00 29.222 -`define LM32_SIZE_HWORD 2'b11 29.223 -`define LM32_SIZE_WORD 2'b10 29.224 -`define LM32_ADDRESS_LSBS_WIDTH 2 29.225 - 29.226 -// Width and range of a CSR index 29.227 -`ifdef CFG_DEBUG_ENABLED 29.228 -`define LM32_CSR_WIDTH 5 29.229 -`define LM32_CSR_RNG (`LM32_CSR_WIDTH-1):0 29.230 -`else 29.231 -`ifdef CFG_JTAG_ENABLED 29.232 -`define LM32_CSR_WIDTH 4 29.233 -`define LM32_CSR_RNG (`LM32_CSR_WIDTH-1):0 29.234 -`else 29.235 -`define LM32_CSR_WIDTH 3 29.236 -`define LM32_CSR_RNG (`LM32_CSR_WIDTH-1):0 29.237 -`endif 29.238 -`endif 29.239 - 29.240 -// CSR indices 29.241 -`define LM32_CSR_IE `LM32_CSR_WIDTH'h0 29.242 -`define LM32_CSR_IM `LM32_CSR_WIDTH'h1 29.243 -`define LM32_CSR_IP `LM32_CSR_WIDTH'h2 29.244 -`define LM32_CSR_ICC `LM32_CSR_WIDTH'h3 29.245 -`define LM32_CSR_DCC `LM32_CSR_WIDTH'h4 29.246 -`define LM32_CSR_CC `LM32_CSR_WIDTH'h5 29.247 -`define LM32_CSR_CFG `LM32_CSR_WIDTH'h6 29.248 -`define LM32_CSR_EBA `LM32_CSR_WIDTH'h7 29.249 -`ifdef CFG_DEBUG_ENABLED 29.250 -`define LM32_CSR_DC `LM32_CSR_WIDTH'h8 29.251 -`define LM32_CSR_DEBA `LM32_CSR_WIDTH'h9 29.252 -`endif 29.253 -`define LM32_CSR_CFG2 `LM32_CSR_WIDTH'ha 29.254 -`ifdef CFG_JTAG_ENABLED 29.255 -`define LM32_CSR_JTX `LM32_CSR_WIDTH'he 29.256 -`define LM32_CSR_JRX `LM32_CSR_WIDTH'hf 29.257 -`endif 29.258 -`ifdef CFG_DEBUG_ENABLED 29.259 -`define LM32_CSR_BP0 `LM32_CSR_WIDTH'h10 29.260 -`define LM32_CSR_BP1 `LM32_CSR_WIDTH'h11 29.261 -`define LM32_CSR_BP2 `LM32_CSR_WIDTH'h12 29.262 -`define LM32_CSR_BP3 `LM32_CSR_WIDTH'h13 29.263 -`define LM32_CSR_WP0 `LM32_CSR_WIDTH'h18 29.264 -`define LM32_CSR_WP1 `LM32_CSR_WIDTH'h19 29.265 -`define LM32_CSR_WP2 `LM32_CSR_WIDTH'h1a 29.266 -`define LM32_CSR_WP3 `LM32_CSR_WIDTH'h1b 29.267 -`endif 29.268 - 29.269 -// Values for WPC CSR 29.270 -`define LM32_WPC_C_RNG 1:0 29.271 -`define LM32_WPC_C_DISABLED 2'b00 29.272 -`define LM32_WPC_C_READ 2'b01 29.273 -`define LM32_WPC_C_WRITE 2'b10 29.274 -`define LM32_WPC_C_READ_WRITE 2'b11 29.275 - 29.276 -// Exception IDs 29.277 -`define LM32_EID_WIDTH 3 29.278 -`define LM32_EID_RNG (`LM32_EID_WIDTH-1):0 29.279 -`define LM32_EID_RESET 3'h0 29.280 -`define LM32_EID_BREAKPOINT 3'd1 29.281 -`define LM32_EID_INST_BUS_ERROR 3'h2 29.282 -`define LM32_EID_WATCHPOINT 3'd3 29.283 -`define LM32_EID_DATA_BUS_ERROR 3'h4 29.284 -`define LM32_EID_DIVIDE_BY_ZERO 3'h5 29.285 -`define LM32_EID_INTERRUPT 3'h6 29.286 -`define LM32_EID_SCALL 3'h7 29.287 - 29.288 -// Pipeline result selection mux controls 29.289 - 29.290 -`define LM32_D_RESULT_SEL_0_RNG 0:0 29.291 -`define LM32_D_RESULT_SEL_0_REG_0 1'b0 29.292 -`define LM32_D_RESULT_SEL_0_NEXT_PC 1'b1 29.293 - 29.294 -`define LM32_D_RESULT_SEL_1_RNG 1:0 29.295 -`define LM32_D_RESULT_SEL_1_ZERO 2'b00 29.296 -`define LM32_D_RESULT_SEL_1_REG_1 2'b01 29.297 -`define LM32_D_RESULT_SEL_1_IMMEDIATE 2'b10 29.298 - 29.299 -`define LM32_USER_OPCODE_WIDTH 11 29.300 -`define LM32_USER_OPCODE_RNG (`LM32_USER_OPCODE_WIDTH-1):0 29.301 - 29.302 -// Derive a macro to indicate if either of the caches are implemented 29.303 -`ifdef CFG_ICACHE_ENABLED 29.304 -`define LM32_CACHE_ENABLED 29.305 -`else 29.306 -`ifdef CFG_DCACHE_ENABLED 29.307 -`define LM32_CACHE_ENABLED 29.308 -`endif 29.309 -`endif 29.310 - 29.311 -///////////////////////////////////////////////////// 29.312 -// Interrupts 29.313 -///////////////////////////////////////////////////// 29.314 - 29.315 -// Always enable interrupts 29.316 -`define CFG_INTERRUPTS_ENABLED 29.317 - 29.318 -// Currently this is fixed to 32 and should not be changed 29.319 -`define CFG_INTERRUPTS 32 29.320 -`define LM32_INTERRUPT_WIDTH `CFG_INTERRUPTS 29.321 -`define LM32_INTERRUPT_RNG (`LM32_INTERRUPT_WIDTH-1):0 29.322 - 29.323 -///////////////////////////////////////////////////// 29.324 -// General 29.325 -///////////////////////////////////////////////////// 29.326 - 29.327 -// Sub-word range types 29.328 -`define LM32_BYTE_WIDTH 8 29.329 -`define LM32_BYTE_RNG 7:0 29.330 -`define LM32_HWORD_WIDTH 16 29.331 -`define LM32_HWORD_RNG 15:0 29.332 - 29.333 -// Word sub-byte indicies 29.334 -`define LM32_BYTE_0_RNG 7:0 29.335 -`define LM32_BYTE_1_RNG 15:8 29.336 -`define LM32_BYTE_2_RNG 23:16 29.337 -`define LM32_BYTE_3_RNG 31:24 29.338 - 29.339 -// Word sub-halfword indices 29.340 -`define LM32_HWORD_0_RNG 15:0 29.341 -`define LM32_HWORD_1_RNG 31:16 29.342 - 29.343 -// Use an asynchronous reset 29.344 -// To use a synchronous reset, define this macro as nothing 29.345 -//`define CFG_RESET_SENSITIVITY or posedge rst_i 29.346 -`define CFG_RESET_SENSITIVITY 29.347 - 29.348 -// Whether to include context registers for debug exceptions 29.349 -// in addition to standard exception handling registers 29.350 -`define CFG_DEBUG_EXCEPTIONS_ENABLED 29.351 - 29.352 -// Wishbone defines 29.353 -// Refer to Wishbone System-on-Chip Interconnection Architecture 29.354 -// These should probably be moved to a Wishbone common file 29.355 - 29.356 -// Wishbone cycle types 29.357 -`define LM32_CTYPE_WIDTH 3 29.358 -`define LM32_CTYPE_RNG (`LM32_CTYPE_WIDTH-1):0 29.359 -`define LM32_CTYPE_CLASSIC 3'b000 29.360 -`define LM32_CTYPE_CONSTANT 3'b001 29.361 -`define LM32_CTYPE_INCREMENTING 3'b010 29.362 -`define LM32_CTYPE_END 3'b111 29.363 - 29.364 -// Wishbone burst types 29.365 -`define LM32_BTYPE_WIDTH 2 29.366 -`define LM32_BTYPE_RNG (`LM32_BTYPE_WIDTH-1):0 29.367 -`define LM32_BTYPE_LINEAR 2'b00 29.368 -`define LM32_BTYPE_4_BEAT 2'b01 29.369 -`define LM32_BTYPE_8_BEAT 2'b10 29.370 -`define LM32_BTYPE_16_BEAT 2'b11 29.371 - 29.372 -`endif
30.1 diff -r 252df75c8f67 -r c336e674a37e lm32_instruction_unit.v 30.2 --- a/lm32_instruction_unit.v Sun Mar 06 21:17:31 2011 +0000 30.3 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 30.4 @@ -1,839 +0,0 @@ 30.5 -// ============================================================================= 30.6 -// COPYRIGHT NOTICE 30.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 30.8 -// ALL RIGHTS RESERVED 30.9 -// This confidential and proprietary software may be used only as authorised by 30.10 -// a licensing agreement from Lattice Semiconductor Corporation. 30.11 -// The entire notice above must be reproduced on all authorized copies and 30.12 -// copies may only be made to the extent permitted by a licensing agreement from 30.13 -// Lattice Semiconductor Corporation. 30.14 -// 30.15 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 30.16 -// 5555 NE Moore Court 408-826-6000 (other locations) 30.17 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 30.18 -// U.S.A email: techsupport@latticesemi.com 30.19 -// =============================================================================/ 30.20 -// FILE DETAILS 30.21 -// Project : LatticeMico32 30.22 -// File : lm32_instruction_unit.v 30.23 -// Title : Instruction unit 30.24 -// Dependencies : lm32_include.v 30.25 -// Version : 6.1.17 30.26 -// : Initial Release 30.27 -// Version : 7.0SP2, 3.0 30.28 -// : No Change 30.29 -// Version : 3.1 30.30 -// : Support for static branch prediction is added. Fetching of 30.31 -// : instructions can also be altered by branches predicted in D 30.32 -// : stage of pipeline, and mispredicted branches in the X and M 30.33 -// : stages of the pipeline. 30.34 -// Version : 3.2 30.35 -// : EBRs use SYNC resets instead of ASYNC resets. 30.36 -// Version : 3.3 30.37 -// : Support for a non-cacheable Instruction Memory that has a 30.38 -// : single-cycle access latency. This memory can be accessed by 30.39 -// : data port of LM32 (so that debugger has access to it). 30.40 -// Version : 3.4 30.41 -// : No change 30.42 -// Version : 3.5 30.43 -// : Bug fix: Inline memory is correctly generated if it is not a 30.44 -// : power-of-two. 30.45 -// : Bug fix: Fixed a bug that caused LM32 (configured without 30.46 -// : instruction cache) to lock up in to an infinite loop due to a 30.47 -// : instruction bus error when EBA was set to instruction inline 30.48 -// : memory. 30.49 -// ============================================================================= 30.50 - 30.51 -`include "lm32_include.v" 30.52 - 30.53 -///////////////////////////////////////////////////// 30.54 -// Module interface 30.55 -///////////////////////////////////////////////////// 30.56 - 30.57 -module lm32_instruction_unit ( 30.58 - // ----- Inputs ------- 30.59 - clk_i, 30.60 - rst_i, 30.61 - // From pipeline 30.62 - stall_a, 30.63 - stall_f, 30.64 - stall_d, 30.65 - stall_x, 30.66 - stall_m, 30.67 - valid_f, 30.68 - valid_d, 30.69 - kill_f, 30.70 - branch_predict_taken_d, 30.71 - branch_predict_address_d, 30.72 -`ifdef CFG_FAST_UNCONDITIONAL_BRANCH 30.73 - branch_taken_x, 30.74 - branch_target_x, 30.75 -`endif 30.76 - exception_m, 30.77 - branch_taken_m, 30.78 - branch_mispredict_taken_m, 30.79 - branch_target_m, 30.80 -`ifdef CFG_ICACHE_ENABLED 30.81 - iflush, 30.82 -`endif 30.83 -`ifdef CFG_DCACHE_ENABLED 30.84 - dcache_restart_request, 30.85 - dcache_refill_request, 30.86 - dcache_refilling, 30.87 -`endif 30.88 -`ifdef CFG_IROM_ENABLED 30.89 - irom_store_data_m, 30.90 - irom_address_xm, 30.91 - irom_we_xm, 30.92 -`endif 30.93 -`ifdef CFG_IWB_ENABLED 30.94 - // From Wishbone 30.95 - i_dat_i, 30.96 - i_ack_i, 30.97 - i_err_i, 30.98 -`endif 30.99 -`ifdef CFG_HW_DEBUG_ENABLED 30.100 - jtag_read_enable, 30.101 - jtag_write_enable, 30.102 - jtag_write_data, 30.103 - jtag_address, 30.104 -`endif 30.105 - // ----- Outputs ------- 30.106 - // To pipeline 30.107 - pc_f, 30.108 - pc_d, 30.109 - pc_x, 30.110 - pc_m, 30.111 - pc_w, 30.112 -`ifdef CFG_ICACHE_ENABLED 30.113 - icache_stall_request, 30.114 - icache_restart_request, 30.115 - icache_refill_request, 30.116 - icache_refilling, 30.117 -`endif 30.118 -`ifdef CFG_IROM_ENABLED 30.119 - irom_data_m, 30.120 -`endif 30.121 -`ifdef CFG_IWB_ENABLED 30.122 - // To Wishbone 30.123 - i_dat_o, 30.124 - i_adr_o, 30.125 - i_cyc_o, 30.126 - i_sel_o, 30.127 - i_stb_o, 30.128 - i_we_o, 30.129 - i_cti_o, 30.130 - i_lock_o, 30.131 - i_bte_o, 30.132 -`endif 30.133 -`ifdef CFG_HW_DEBUG_ENABLED 30.134 - jtag_read_data, 30.135 - jtag_access_complete, 30.136 -`endif 30.137 -`ifdef CFG_BUS_ERRORS_ENABLED 30.138 - bus_error_d, 30.139 -`endif 30.140 -`ifdef CFG_EBR_POSEDGE_REGISTER_FILE 30.141 - instruction_f, 30.142 -`endif 30.143 - instruction_d 30.144 - ); 30.145 - 30.146 -///////////////////////////////////////////////////// 30.147 -// Parameters 30.148 -///////////////////////////////////////////////////// 30.149 - 30.150 -parameter associativity = 1; // Associativity of the cache (Number of ways) 30.151 -parameter sets = 512; // Number of sets 30.152 -parameter bytes_per_line = 16; // Number of bytes per cache line 30.153 -parameter base_address = 0; // Base address of cachable memory 30.154 -parameter limit = 0; // Limit (highest address) of cachable memory 30.155 - 30.156 -// For bytes_per_line == 4, we set 1 so part-select range isn't reversed, even though not really used 30.157 -localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2; 30.158 -localparam addr_offset_lsb = 2; 30.159 -localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1); 30.160 - 30.161 -///////////////////////////////////////////////////// 30.162 -// Inputs 30.163 -///////////////////////////////////////////////////// 30.164 - 30.165 -input clk_i; // Clock 30.166 -input rst_i; // Reset 30.167 - 30.168 -input stall_a; // Stall A stage instruction 30.169 -input stall_f; // Stall F stage instruction 30.170 -input stall_d; // Stall D stage instruction 30.171 -input stall_x; // Stall X stage instruction 30.172 -input stall_m; // Stall M stage instruction 30.173 -input valid_f; // Instruction in F stage is valid 30.174 -input valid_d; // Instruction in D stage is valid 30.175 -input kill_f; // Kill instruction in F stage 30.176 - 30.177 -input branch_predict_taken_d; // Branch is predicted taken in D stage 30.178 -input [`LM32_PC_RNG] branch_predict_address_d; // Branch target address 30.179 - 30.180 -`ifdef CFG_FAST_UNCONDITIONAL_BRANCH 30.181 -input branch_taken_x; // Branch instruction in X stage is taken 30.182 -input [`LM32_PC_RNG] branch_target_x; // Target PC of X stage branch instruction 30.183 -`endif 30.184 -input exception_m; 30.185 -input branch_taken_m; // Branch instruction in M stage is taken 30.186 -input branch_mispredict_taken_m; // Branch instruction in M stage is mispredicted as taken 30.187 -input [`LM32_PC_RNG] branch_target_m; // Target PC of M stage branch instruction 30.188 - 30.189 -`ifdef CFG_ICACHE_ENABLED 30.190 -input iflush; // Flush instruction cache 30.191 -`endif 30.192 -`ifdef CFG_DCACHE_ENABLED 30.193 -input dcache_restart_request; // Restart instruction that caused a data cache miss 30.194 -input dcache_refill_request; // Request to refill data cache 30.195 -input dcache_refilling; 30.196 -`endif 30.197 - 30.198 -`ifdef CFG_IROM_ENABLED 30.199 -input [`LM32_WORD_RNG] irom_store_data_m; // Data from load-store unit 30.200 -input [`LM32_WORD_RNG] irom_address_xm; // Address from load-store unit 30.201 -input irom_we_xm; // Indicates if memory operation is load or store 30.202 -`endif 30.203 - 30.204 -`ifdef CFG_IWB_ENABLED 30.205 -input [`LM32_WORD_RNG] i_dat_i; // Instruction Wishbone interface read data 30.206 -input i_ack_i; // Instruction Wishbone interface acknowledgement 30.207 -input i_err_i; // Instruction Wishbone interface error 30.208 -`endif 30.209 - 30.210 -`ifdef CFG_HW_DEBUG_ENABLED 30.211 -input jtag_read_enable; // JTAG read memory request 30.212 -input jtag_write_enable; // JTAG write memory request 30.213 -input [`LM32_BYTE_RNG] jtag_write_data; // JTAG wrirte data 30.214 -input [`LM32_WORD_RNG] jtag_address; // JTAG read/write address 30.215 -`endif 30.216 - 30.217 -///////////////////////////////////////////////////// 30.218 -// Outputs 30.219 -///////////////////////////////////////////////////// 30.220 - 30.221 -output [`LM32_PC_RNG] pc_f; // F stage PC 30.222 -reg [`LM32_PC_RNG] pc_f; 30.223 -output [`LM32_PC_RNG] pc_d; // D stage PC 30.224 -reg [`LM32_PC_RNG] pc_d; 30.225 -output [`LM32_PC_RNG] pc_x; // X stage PC 30.226 -reg [`LM32_PC_RNG] pc_x; 30.227 -output [`LM32_PC_RNG] pc_m; // M stage PC 30.228 -reg [`LM32_PC_RNG] pc_m; 30.229 -output [`LM32_PC_RNG] pc_w; // W stage PC 30.230 -reg [`LM32_PC_RNG] pc_w; 30.231 - 30.232 -`ifdef CFG_ICACHE_ENABLED 30.233 -output icache_stall_request; // Instruction cache stall request 30.234 -wire icache_stall_request; 30.235 -output icache_restart_request; // Request to restart instruction that cached instruction cache miss 30.236 -wire icache_restart_request; 30.237 -output icache_refill_request; // Instruction cache refill request 30.238 -wire icache_refill_request; 30.239 -output icache_refilling; // Indicates the icache is refilling 30.240 -wire icache_refilling; 30.241 -`endif 30.242 - 30.243 -`ifdef CFG_IROM_ENABLED 30.244 -output [`LM32_WORD_RNG] irom_data_m; // Data to load-store unit on load 30.245 -wire [`LM32_WORD_RNG] irom_data_m; 30.246 -`endif 30.247 - 30.248 -`ifdef CFG_IWB_ENABLED 30.249 -output [`LM32_WORD_RNG] i_dat_o; // Instruction Wishbone interface write data 30.250 -`ifdef CFG_HW_DEBUG_ENABLED 30.251 -reg [`LM32_WORD_RNG] i_dat_o; 30.252 -`else 30.253 -wire [`LM32_WORD_RNG] i_dat_o; 30.254 -`endif 30.255 -output [`LM32_WORD_RNG] i_adr_o; // Instruction Wishbone interface address 30.256 -reg [`LM32_WORD_RNG] i_adr_o; 30.257 -output i_cyc_o; // Instruction Wishbone interface cycle 30.258 -reg i_cyc_o; 30.259 -output [`LM32_BYTE_SELECT_RNG] i_sel_o; // Instruction Wishbone interface byte select 30.260 -`ifdef CFG_HW_DEBUG_ENABLED 30.261 -reg [`LM32_BYTE_SELECT_RNG] i_sel_o; 30.262 -`else 30.263 -wire [`LM32_BYTE_SELECT_RNG] i_sel_o; 30.264 -`endif 30.265 -output i_stb_o; // Instruction Wishbone interface strobe 30.266 -reg i_stb_o; 30.267 -output i_we_o; // Instruction Wishbone interface write enable 30.268 -`ifdef CFG_HW_DEBUG_ENABLED 30.269 -reg i_we_o; 30.270 -`else 30.271 -wire i_we_o; 30.272 -`endif 30.273 -output [`LM32_CTYPE_RNG] i_cti_o; // Instruction Wishbone interface cycle type 30.274 -reg [`LM32_CTYPE_RNG] i_cti_o; 30.275 -output i_lock_o; // Instruction Wishbone interface lock bus 30.276 -reg i_lock_o; 30.277 -output [`LM32_BTYPE_RNG] i_bte_o; // Instruction Wishbone interface burst type 30.278 -wire [`LM32_BTYPE_RNG] i_bte_o; 30.279 -`endif 30.280 - 30.281 -`ifdef CFG_HW_DEBUG_ENABLED 30.282 -output [`LM32_BYTE_RNG] jtag_read_data; // Data read for JTAG interface 30.283 -reg [`LM32_BYTE_RNG] jtag_read_data; 30.284 -output jtag_access_complete; // Requested memory access by JTAG interface is complete 30.285 -wire jtag_access_complete; 30.286 -`endif 30.287 - 30.288 -`ifdef CFG_BUS_ERRORS_ENABLED 30.289 -output bus_error_d; // Indicates a bus error occured while fetching the instruction 30.290 -reg bus_error_d; 30.291 -`endif 30.292 -`ifdef CFG_EBR_POSEDGE_REGISTER_FILE 30.293 -output [`LM32_INSTRUCTION_RNG] instruction_f; // F stage instruction (only to have register indices extracted from) 30.294 -wire [`LM32_INSTRUCTION_RNG] instruction_f; 30.295 -`endif 30.296 -output [`LM32_INSTRUCTION_RNG] instruction_d; // D stage instruction to be decoded 30.297 -reg [`LM32_INSTRUCTION_RNG] instruction_d; 30.298 - 30.299 -///////////////////////////////////////////////////// 30.300 -// Internal nets and registers 30.301 -///////////////////////////////////////////////////// 30.302 - 30.303 -reg [`LM32_PC_RNG] pc_a; // A stage PC 30.304 - 30.305 -`ifdef LM32_CACHE_ENABLED 30.306 -reg [`LM32_PC_RNG] restart_address; // Address to restart from after a cache miss 30.307 -`endif 30.308 - 30.309 -`ifdef CFG_ICACHE_ENABLED 30.310 -wire icache_read_enable_f; // Indicates if instruction cache miss is valid 30.311 -wire [`LM32_PC_RNG] icache_refill_address; // Address that caused cache miss 30.312 -reg icache_refill_ready; // Indicates when next word of refill data is ready to be written to cache 30.313 -reg [`LM32_INSTRUCTION_RNG] icache_refill_data; // Next word of refill data, fetched from Wishbone 30.314 -wire [`LM32_INSTRUCTION_RNG] icache_data_f; // Instruction fetched from instruction cache 30.315 -wire [`LM32_CTYPE_RNG] first_cycle_type; // First Wishbone cycle type 30.316 -wire [`LM32_CTYPE_RNG] next_cycle_type; // Next Wishbone cycle type 30.317 -wire last_word; // Indicates if this is the last word in the cache line 30.318 -wire [`LM32_PC_RNG] first_address; // First cache refill address 30.319 -`else 30.320 -`ifdef CFG_IWB_ENABLED 30.321 -reg [`LM32_INSTRUCTION_RNG] wb_data_f; // Instruction fetched from Wishbone 30.322 -`endif 30.323 -`endif 30.324 -`ifdef CFG_IROM_ENABLED 30.325 -wire irom_select_a; // Indicates if A stage PC maps to a ROM address 30.326 -reg irom_select_f; // Indicates if F stage PC maps to a ROM address 30.327 -wire [`LM32_INSTRUCTION_RNG] irom_data_f; // Instruction fetched from ROM 30.328 -`endif 30.329 -`ifdef CFG_EBR_POSEDGE_REGISTER_FILE 30.330 -`else 30.331 -wire [`LM32_INSTRUCTION_RNG] instruction_f; // F stage instruction 30.332 -`endif 30.333 -`ifdef CFG_BUS_ERRORS_ENABLED 30.334 -reg bus_error_f; // Indicates if a bus error occured while fetching the instruction in the F stage 30.335 -`endif 30.336 - 30.337 -`ifdef CFG_HW_DEBUG_ENABLED 30.338 -reg jtag_access; // Indicates if a JTAG WB access is in progress 30.339 -`endif 30.340 - 30.341 -///////////////////////////////////////////////////// 30.342 -// Functions 30.343 -///////////////////////////////////////////////////// 30.344 - 30.345 -`include "lm32_functions.v" 30.346 - 30.347 -///////////////////////////////////////////////////// 30.348 -// Instantiations 30.349 -///////////////////////////////////////////////////// 30.350 - 30.351 -// Instruction ROM 30.352 -`ifdef CFG_IROM_ENABLED 30.353 - pmi_ram_dp_true 30.354 - #( 30.355 - // ----- Parameters ------- 30.356 - .pmi_family (`LATTICE_FAMILY), 30.357 - 30.358 - //.pmi_addr_depth_a (1 << (clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)), 30.359 - //.pmi_addr_width_a ((clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)), 30.360 - //.pmi_data_width_a (`LM32_WORD_WIDTH), 30.361 - //.pmi_addr_depth_b (1 << (clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)), 30.362 - //.pmi_addr_width_b ((clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)), 30.363 - //.pmi_data_width_b (`LM32_WORD_WIDTH), 30.364 - 30.365 - .pmi_addr_depth_a (`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1), 30.366 - .pmi_addr_width_a (clogb2_v1(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)), 30.367 - .pmi_data_width_a (`LM32_WORD_WIDTH), 30.368 - .pmi_addr_depth_b (`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1), 30.369 - .pmi_addr_width_b (clogb2_v1(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)), 30.370 - .pmi_data_width_b (`LM32_WORD_WIDTH), 30.371 - 30.372 - .pmi_regmode_a ("noreg"), 30.373 - .pmi_regmode_b ("noreg"), 30.374 - .pmi_gsr ("enable"), 30.375 - .pmi_resetmode ("sync"), 30.376 - .pmi_init_file (`CFG_IROM_INIT_FILE), 30.377 - .pmi_init_file_format (`CFG_IROM_INIT_FILE_FORMAT), 30.378 - .module_type ("pmi_ram_dp_true") 30.379 - ) 30.380 - ram ( 30.381 - // ----- Inputs ------- 30.382 - .ClockA (clk_i), 30.383 - .ClockB (clk_i), 30.384 - .ResetA (rst_i), 30.385 - .ResetB (rst_i), 30.386 - .DataInA ({32{1'b0}}), 30.387 - .DataInB (irom_store_data_m), 30.388 - .AddressA (pc_a[(clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)+2-1:2]), 30.389 - .AddressB (irom_address_xm[(clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)+2-1:2]), 30.390 - .ClockEnA (!stall_a), 30.391 - .ClockEnB (!stall_x || !stall_m), 30.392 - .WrA (`FALSE), 30.393 - .WrB (irom_we_xm), 30.394 - // ----- Outputs ------- 30.395 - .QA (irom_data_f), 30.396 - .QB (irom_data_m) 30.397 - ); 30.398 -`endif 30.399 - 30.400 -`ifdef CFG_ICACHE_ENABLED 30.401 -// Instruction cache 30.402 -lm32_icache #( 30.403 - .associativity (associativity), 30.404 - .sets (sets), 30.405 - .bytes_per_line (bytes_per_line), 30.406 - .base_address (base_address), 30.407 - .limit (limit) 30.408 - ) icache ( 30.409 - // ----- Inputs ----- 30.410 - .clk_i (clk_i), 30.411 - .rst_i (rst_i), 30.412 - .stall_a (stall_a), 30.413 - .stall_f (stall_f), 30.414 - .branch_predict_taken_d (branch_predict_taken_d), 30.415 - .valid_d (valid_d), 30.416 - .address_a (pc_a), 30.417 - .address_f (pc_f), 30.418 - .read_enable_f (icache_read_enable_f), 30.419 - .refill_ready (icache_refill_ready), 30.420 - .refill_data (icache_refill_data), 30.421 - .iflush (iflush), 30.422 - // ----- Outputs ----- 30.423 - .stall_request (icache_stall_request), 30.424 - .restart_request (icache_restart_request), 30.425 - .refill_request (icache_refill_request), 30.426 - .refill_address (icache_refill_address), 30.427 - .refilling (icache_refilling), 30.428 - .inst (icache_data_f) 30.429 - ); 30.430 -`endif 30.431 - 30.432 -///////////////////////////////////////////////////// 30.433 -// Combinational Logic 30.434 -///////////////////////////////////////////////////// 30.435 - 30.436 -`ifdef CFG_ICACHE_ENABLED 30.437 -// Generate signal that indicates when instruction cache misses are valid 30.438 -assign icache_read_enable_f = (valid_f == `TRUE) 30.439 - && (kill_f == `FALSE) 30.440 -`ifdef CFG_DCACHE_ENABLED 30.441 - && (dcache_restart_request == `FALSE) 30.442 -`endif 30.443 -`ifdef CFG_IROM_ENABLED 30.444 - && (irom_select_f == `FALSE) 30.445 -`endif 30.446 - ; 30.447 -`endif 30.448 - 30.449 -// Compute address of next instruction to fetch 30.450 -always @(*) 30.451 -begin 30.452 - // The request from the latest pipeline stage must take priority 30.453 -`ifdef CFG_DCACHE_ENABLED 30.454 - if (dcache_restart_request == `TRUE) 30.455 - pc_a = restart_address; 30.456 - else 30.457 -`endif 30.458 - if (branch_taken_m == `TRUE) 30.459 - if ((branch_mispredict_taken_m == `TRUE) && (exception_m == `FALSE)) 30.460 - pc_a = pc_x; 30.461 - else 30.462 - pc_a = branch_target_m; 30.463 -`ifdef CFG_FAST_UNCONDITIONAL_BRANCH 30.464 - else if (branch_taken_x == `TRUE) 30.465 - pc_a = branch_target_x; 30.466 -`endif 30.467 - else 30.468 - if ( (valid_d == `TRUE) && (branch_predict_taken_d == `TRUE) ) 30.469 - pc_a = branch_predict_address_d; 30.470 - else 30.471 -`ifdef CFG_ICACHE_ENABLED 30.472 - if (icache_restart_request == `TRUE) 30.473 - pc_a = restart_address; 30.474 - else 30.475 -`endif 30.476 - pc_a = pc_f + 1'b1; 30.477 -end 30.478 - 30.479 -// Select where instruction should be fetched from 30.480 -`ifdef CFG_IROM_ENABLED 30.481 -assign irom_select_a = ({pc_a, 2'b00} >= `CFG_IROM_BASE_ADDRESS) && ({pc_a, 2'b00} <= `CFG_IROM_LIMIT); 30.482 -`endif 30.483 - 30.484 -// Select instruction from selected source 30.485 -`ifdef CFG_ICACHE_ENABLED 30.486 -`ifdef CFG_IROM_ENABLED 30.487 -assign instruction_f = irom_select_f == `TRUE ? irom_data_f : icache_data_f; 30.488 -`else 30.489 -assign instruction_f = icache_data_f; 30.490 -`endif 30.491 -`else 30.492 -`ifdef CFG_IROM_ENABLED 30.493 -`ifdef CFG_IWB_ENABLED 30.494 -assign instruction_f = irom_select_f == `TRUE ? irom_data_f : wb_data_f; 30.495 -`else 30.496 -assign instruction_f = irom_data_f; 30.497 -`endif 30.498 -`else 30.499 -assign instruction_f = wb_data_f; 30.500 -`endif 30.501 -`endif 30.502 - 30.503 -// Unused/constant Wishbone signals 30.504 -`ifdef CFG_IWB_ENABLED 30.505 -`ifdef CFG_HW_DEBUG_ENABLED 30.506 -`else 30.507 -assign i_dat_o = 32'd0; 30.508 -assign i_we_o = `FALSE; 30.509 -assign i_sel_o = 4'b1111; 30.510 -`endif 30.511 -assign i_bte_o = `LM32_BTYPE_LINEAR; 30.512 -`endif 30.513 - 30.514 -`ifdef CFG_ICACHE_ENABLED 30.515 -// Determine parameters for next cache refill Wishbone access 30.516 -generate 30.517 - case (bytes_per_line) 30.518 - 4: 30.519 - begin 30.520 -assign first_cycle_type = `LM32_CTYPE_END; 30.521 -assign next_cycle_type = `LM32_CTYPE_END; 30.522 -assign last_word = `TRUE; 30.523 -assign first_address = icache_refill_address; 30.524 - end 30.525 - 8: 30.526 - begin 30.527 -assign first_cycle_type = `LM32_CTYPE_INCREMENTING; 30.528 -assign next_cycle_type = `LM32_CTYPE_END; 30.529 -assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 1'b1; 30.530 -assign first_address = {icache_refill_address[`LM32_PC_WIDTH+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}}; 30.531 - end 30.532 - 16: 30.533 - begin 30.534 -assign first_cycle_type = `LM32_CTYPE_INCREMENTING; 30.535 -assign next_cycle_type = i_adr_o[addr_offset_msb] == 1'b1 ? `LM32_CTYPE_END : `LM32_CTYPE_INCREMENTING; 30.536 -assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 2'b11; 30.537 -assign first_address = {icache_refill_address[`LM32_PC_WIDTH+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}}; 30.538 - end 30.539 - endcase 30.540 -endgenerate 30.541 -`endif 30.542 - 30.543 -///////////////////////////////////////////////////// 30.544 -// Sequential Logic 30.545 -///////////////////////////////////////////////////// 30.546 - 30.547 -// PC 30.548 -always @(posedge clk_i `CFG_RESET_SENSITIVITY) 30.549 -begin 30.550 - if (rst_i == `TRUE) 30.551 - begin 30.552 - pc_f <= (`CFG_EBA_RESET-4)/4; 30.553 - pc_d <= {`LM32_PC_WIDTH{1'b0}}; 30.554 - pc_x <= {`LM32_PC_WIDTH{1'b0}}; 30.555 - pc_m <= {`LM32_PC_WIDTH{1'b0}}; 30.556 - pc_w <= {`LM32_PC_WIDTH{1'b0}}; 30.557 - end 30.558 - else 30.559 - begin 30.560 - if (stall_f == `FALSE) 30.561 - pc_f <= pc_a; 30.562 - if (stall_d == `FALSE) 30.563 - pc_d <= pc_f; 30.564 - if (stall_x == `FALSE) 30.565 - pc_x <= pc_d; 30.566 - if (stall_m == `FALSE) 30.567 - pc_m <= pc_x; 30.568 - pc_w <= pc_m; 30.569 - end 30.570 -end 30.571 - 30.572 -`ifdef LM32_CACHE_ENABLED 30.573 -// Address to restart from after a cache miss has been handled 30.574 -always @(posedge clk_i `CFG_RESET_SENSITIVITY) 30.575 -begin 30.576 - if (rst_i == `TRUE) 30.577 - restart_address <= {`LM32_PC_WIDTH{1'b0}}; 30.578 - else 30.579 - begin 30.580 -`ifdef CFG_DCACHE_ENABLED 30.581 -`ifdef CFG_ICACHE_ENABLED 30.582 - // D-cache restart address must take priority, otherwise instructions will be lost 30.583 - if (dcache_refill_request == `TRUE) 30.584 - restart_address <= pc_w; 30.585 - else if ((icache_refill_request == `TRUE) && (!dcache_refilling) && (!dcache_restart_request)) 30.586 - restart_address <= icache_refill_address; 30.587 -`else 30.588 - if (dcache_refill_request == `TRUE) 30.589 - restart_address <= pc_w; 30.590 -`endif 30.591 -`else 30.592 -`ifdef CFG_ICACHE_ENABLED 30.593 - if (icache_refill_request == `TRUE) 30.594 - restart_address <= icache_refill_address; 30.595 -`endif 30.596 -`endif 30.597 - end 30.598 -end 30.599 -`endif 30.600 - 30.601 -// Record where instruction was fetched from 30.602 -`ifdef CFG_IROM_ENABLED 30.603 -always @(posedge clk_i `CFG_RESET_SENSITIVITY) 30.604 -begin 30.605 - if (rst_i == `TRUE) 30.606 - irom_select_f <= `FALSE; 30.607 - else 30.608 - begin 30.609 - if (stall_f == `FALSE) 30.610 - irom_select_f <= irom_select_a; 30.611 - end 30.612 -end 30.613 -`endif 30.614 - 30.615 -`ifdef CFG_HW_DEBUG_ENABLED 30.616 -assign jtag_access_complete = (i_cyc_o == `TRUE) && ((i_ack_i == `TRUE) || (i_err_i == `TRUE)) && (jtag_access == `TRUE); 30.617 -always @(*) 30.618 -begin 30.619 - case (jtag_address[1:0]) 30.620 - 2'b00: jtag_read_data = i_dat_i[`LM32_BYTE_3_RNG]; 30.621 - 2'b01: jtag_read_data = i_dat_i[`LM32_BYTE_2_RNG]; 30.622 - 2'b10: jtag_read_data = i_dat_i[`LM32_BYTE_1_RNG]; 30.623 - 2'b11: jtag_read_data = i_dat_i[`LM32_BYTE_0_RNG]; 30.624 - endcase 30.625 -end 30.626 -`endif 30.627 - 30.628 -`ifdef CFG_IWB_ENABLED 30.629 -// Instruction Wishbone interface 30.630 -`ifdef CFG_ICACHE_ENABLED 30.631 -always @(posedge clk_i `CFG_RESET_SENSITIVITY) 30.632 -begin 30.633 - if (rst_i == `TRUE) 30.634 - begin 30.635 - i_cyc_o <= `FALSE; 30.636 - i_stb_o <= `FALSE; 30.637 - i_adr_o <= {`LM32_WORD_WIDTH{1'b0}}; 30.638 - i_cti_o <= `LM32_CTYPE_END; 30.639 - i_lock_o <= `FALSE; 30.640 - icache_refill_data <= {`LM32_INSTRUCTION_WIDTH{1'b0}}; 30.641 - icache_refill_ready <= `FALSE; 30.642 -`ifdef CFG_BUS_ERRORS_ENABLED 30.643 - bus_error_f <= `FALSE; 30.644 -`endif 30.645 -`ifdef CFG_HW_DEBUG_ENABLED 30.646 - i_we_o <= `FALSE; 30.647 - i_sel_o <= 4'b1111; 30.648 - jtag_access <= `FALSE; 30.649 -`endif 30.650 - end 30.651 - else 30.652 - begin 30.653 - icache_refill_ready <= `FALSE; 30.654 - // Is a cycle in progress? 30.655 - if (i_cyc_o == `TRUE) 30.656 - begin 30.657 - // Has cycle completed? 30.658 - if ((i_ack_i == `TRUE) || (i_err_i == `TRUE)) 30.659 - begin 30.660 -`ifdef CFG_HW_DEBUG_ENABLED 30.661 - if (jtag_access == `TRUE) 30.662 - begin 30.663 - i_cyc_o <= `FALSE; 30.664 - i_stb_o <= `FALSE; 30.665 - i_we_o <= `FALSE; 30.666 - jtag_access <= `FALSE; 30.667 - end 30.668 - else 30.669 -`endif 30.670 - begin 30.671 - if (last_word == `TRUE) 30.672 - begin 30.673 - // Cache line fill complete 30.674 - i_cyc_o <= `FALSE; 30.675 - i_stb_o <= `FALSE; 30.676 - i_lock_o <= `FALSE; 30.677 - end 30.678 - // Fetch next word in cache line 30.679 - i_adr_o[addr_offset_msb:addr_offset_lsb] <= i_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1; 30.680 - i_cti_o <= next_cycle_type; 30.681 - // Write fetched data into instruction cache 30.682 - icache_refill_ready <= `TRUE; 30.683 - icache_refill_data <= i_dat_i; 30.684 - end 30.685 - end 30.686 -`ifdef CFG_BUS_ERRORS_ENABLED 30.687 - if (i_err_i == `TRUE) 30.688 - begin 30.689 - bus_error_f <= `TRUE; 30.690 - $display ("Instruction bus error. Address: %x", i_adr_o); 30.691 - end 30.692 -`endif 30.693 - end 30.694 - else 30.695 - begin 30.696 - if ((icache_refill_request == `TRUE) && (icache_refill_ready == `FALSE)) 30.697 - begin 30.698 - // Read first word of cache line 30.699 -`ifdef CFG_HW_DEBUG_ENABLED 30.700 - i_sel_o <= 4'b1111; 30.701 -`endif 30.702 - i_adr_o <= {first_address, 2'b00}; 30.703 - i_cyc_o <= `TRUE; 30.704 - i_stb_o <= `TRUE; 30.705 - i_cti_o <= first_cycle_type; 30.706 - //i_lock_o <= `TRUE; 30.707 -`ifdef CFG_BUS_ERRORS_ENABLED 30.708 - bus_error_f <= `FALSE; 30.709 -`endif 30.710 - end 30.711 -`ifdef CFG_HW_DEBUG_ENABLED 30.712 - else 30.713 - begin 30.714 - if ((jtag_read_enable == `TRUE) || (jtag_write_enable == `TRUE)) 30.715 - begin 30.716 - case (jtag_address[1:0]) 30.717 - 2'b00: i_sel_o <= 4'b1000; 30.718 - 2'b01: i_sel_o <= 4'b0100; 30.719 - 2'b10: i_sel_o <= 4'b0010; 30.720 - 2'b11: i_sel_o <= 4'b0001; 30.721 - endcase 30.722 - i_adr_o <= jtag_address; 30.723 - i_dat_o <= {4{jtag_write_data}}; 30.724 - i_cyc_o <= `TRUE; 30.725 - i_stb_o <= `TRUE; 30.726 - i_we_o <= jtag_write_enable; 30.727 - i_cti_o <= `LM32_CTYPE_END; 30.728 - jtag_access <= `TRUE; 30.729 - end 30.730 - end 30.731 -`endif 30.732 -`ifdef CFG_BUS_ERRORS_ENABLED 30.733 - // Clear bus error when exception taken, otherwise they would be 30.734 - // continually generated if exception handler is cached 30.735 -`ifdef CFG_FAST_UNCONDITIONAL_BRANCH 30.736 - if (branch_taken_x == `TRUE) 30.737 - bus_error_f <= `FALSE; 30.738 -`endif 30.739 - if (branch_taken_m == `TRUE) 30.740 - bus_error_f <= `FALSE; 30.741 -`endif 30.742 - end 30.743 - end 30.744 -end 30.745 -`else 30.746 -always @(posedge clk_i `CFG_RESET_SENSITIVITY) 30.747 -begin 30.748 - if (rst_i == `TRUE) 30.749 - begin 30.750 - i_cyc_o <= `FALSE; 30.751 - i_stb_o <= `FALSE; 30.752 - i_adr_o <= {`LM32_WORD_WIDTH{1'b0}}; 30.753 - i_cti_o <= `LM32_CTYPE_END; 30.754 - i_lock_o <= `FALSE; 30.755 - wb_data_f <= {`LM32_INSTRUCTION_WIDTH{1'b0}}; 30.756 -`ifdef CFG_BUS_ERRORS_ENABLED 30.757 - bus_error_f <= `FALSE; 30.758 -`endif 30.759 - end 30.760 - else 30.761 - begin 30.762 - // Is a cycle in progress? 30.763 - if (i_cyc_o == `TRUE) 30.764 - begin 30.765 - // Has cycle completed? 30.766 - if((i_ack_i == `TRUE) || (i_err_i == `TRUE)) 30.767 - begin 30.768 - // Cycle complete 30.769 - i_cyc_o <= `FALSE; 30.770 - i_stb_o <= `FALSE; 30.771 - // Register fetched instruction 30.772 - wb_data_f <= i_dat_i; 30.773 - end 30.774 -`ifdef CFG_BUS_ERRORS_ENABLED 30.775 - if (i_err_i == `TRUE) 30.776 - begin 30.777 - bus_error_f <= `TRUE; 30.778 - $display ("Instruction bus error. Address: %x", i_adr_o); 30.779 - end 30.780 -`endif 30.781 - end 30.782 - else 30.783 - begin 30.784 - // Wait for an instruction fetch from an external address 30.785 - if ( (stall_a == `FALSE) 30.786 -`ifdef CFG_IROM_ENABLED 30.787 - && (irom_select_a == `FALSE) 30.788 -`endif 30.789 - ) 30.790 - begin 30.791 - // Fetch instruction 30.792 -`ifdef CFG_HW_DEBUG_ENABLED 30.793 - i_sel_o <= 4'b1111; 30.794 -`endif 30.795 - i_adr_o <= {pc_a, 2'b00}; 30.796 - i_cyc_o <= `TRUE; 30.797 - i_stb_o <= `TRUE; 30.798 -`ifdef CFG_BUS_ERRORS_ENABLED 30.799 - bus_error_f <= `FALSE; 30.800 -`endif 30.801 - end 30.802 - else 30.803 - begin 30.804 - if ( (stall_a == `FALSE) 30.805 -`ifdef CFG_IROM_ENABLED 30.806 - && (irom_select_a == `TRUE) 30.807 -`endif 30.808 - ) 30.809 - begin 30.810 -`ifdef CFG_BUS_ERRORS_ENABLED 30.811 - bus_error_f <= `FALSE; 30.812 -`endif 30.813 - end 30.814 - end 30.815 - end 30.816 - end 30.817 -end 30.818 -`endif 30.819 -`endif 30.820 - 30.821 -// Instruction register 30.822 -always @(posedge clk_i `CFG_RESET_SENSITIVITY) 30.823 -begin 30.824 - if (rst_i == `TRUE) 30.825 - begin 30.826 - instruction_d <= {`LM32_INSTRUCTION_WIDTH{1'b0}}; 30.827 -`ifdef CFG_BUS_ERRORS_ENABLED 30.828 - bus_error_d <= `FALSE; 30.829 -`endif 30.830 - end 30.831 - else 30.832 - begin 30.833 - if (stall_d == `FALSE) 30.834 - begin 30.835 - instruction_d <= instruction_f; 30.836 -`ifdef CFG_BUS_ERRORS_ENABLED 30.837 - bus_error_d <= bus_error_f; 30.838 -`endif 30.839 - end 30.840 - end 30.841 -end 30.842 - 30.843 -endmodule
31.1 diff -r 252df75c8f67 -r c336e674a37e lm32_interrupt.v 31.2 --- a/lm32_interrupt.v Sun Mar 06 21:17:31 2011 +0000 31.3 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 31.4 @@ -1,335 +0,0 @@ 31.5 -// ============================================================================= 31.6 -// COPYRIGHT NOTICE 31.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 31.8 -// ALL RIGHTS RESERVED 31.9 -// This confidential and proprietary software may be used only as authorised by 31.10 -// a licensing agreement from Lattice Semiconductor Corporation. 31.11 -// The entire notice above must be reproduced on all authorized copies and 31.12 -// copies may only be made to the extent permitted by a licensing agreement from 31.13 -// Lattice Semiconductor Corporation. 31.14 -// 31.15 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 31.16 -// 5555 NE Moore Court 408-826-6000 (other locations) 31.17 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 31.18 -// U.S.A email: techsupport@latticesemi.com 31.19 -// =============================================================================/ 31.20 -// FILE DETAILS 31.21 -// Project : LatticeMico32 31.22 -// File : lm32_interrupt.v 31.23 -// Title : Interrupt logic 31.24 -// Dependencies : lm32_include.v 31.25 -// Version : 6.1.17 31.26 -// : Initial Release 31.27 -// Version : 7.0SP2, 3.0 31.28 -// : No Change 31.29 -// Version : 3.1 31.30 -// : No Change 31.31 -// ============================================================================= 31.32 - 31.33 -`include "lm32_include.v" 31.34 - 31.35 -///////////////////////////////////////////////////// 31.36 -// Module interface 31.37 -///////////////////////////////////////////////////// 31.38 - 31.39 -module lm32_interrupt ( 31.40 - // ----- Inputs ------- 31.41 - clk_i, 31.42 - rst_i, 31.43 - // From external devices 31.44 - interrupt, 31.45 - // From pipeline 31.46 - stall_x, 31.47 -`ifdef CFG_DEBUG_ENABLED 31.48 - non_debug_exception, 31.49 - debug_exception, 31.50 -`else 31.51 - exception, 31.52 -`endif 31.53 - eret_q_x, 31.54 -`ifdef CFG_DEBUG_ENABLED 31.55 - bret_q_x, 31.56 -`endif 31.57 - csr, 31.58 - csr_write_data, 31.59 - csr_write_enable, 31.60 - // ----- Outputs ------- 31.61 - interrupt_exception, 31.62 - // To pipeline 31.63 - csr_read_data 31.64 - ); 31.65 - 31.66 -///////////////////////////////////////////////////// 31.67 -// Parameters 31.68 -///////////////////////////////////////////////////// 31.69 - 31.70 -parameter interrupts = `CFG_INTERRUPTS; // Number of interrupts 31.71 - 31.72 -///////////////////////////////////////////////////// 31.73 -// Inputs 31.74 -///////////////////////////////////////////////////// 31.75 - 31.76 -input clk_i; // Clock 31.77 -input rst_i; // Reset 31.78 - 31.79 -input [interrupts-1:0] interrupt; // Interrupt pins, active-low 31.80 - 31.81 -input stall_x; // Stall X pipeline stage 31.82 - 31.83 -`ifdef CFG_DEBUG_ENABLED 31.84 -input non_debug_exception; // Non-debug related exception has been raised 31.85 -input debug_exception; // Debug-related exception has been raised 31.86 -`else 31.87 -input exception; // Exception has been raised 31.88 -`endif 31.89 -input eret_q_x; // Return from exception 31.90 -`ifdef CFG_DEBUG_ENABLED 31.91 -input bret_q_x; // Return from breakpoint 31.92 -`endif 31.93 - 31.94 -input [`LM32_CSR_RNG] csr; // CSR read/write index 31.95 -input [`LM32_WORD_RNG] csr_write_data; // Data to write to specified CSR 31.96 -input csr_write_enable; // CSR write enable 31.97 - 31.98 -///////////////////////////////////////////////////// 31.99 -// Outputs 31.100 -///////////////////////////////////////////////////// 31.101 - 31.102 -output interrupt_exception; // Request to raide an interrupt exception 31.103 -wire interrupt_exception; 31.104 - 31.105 -output [`LM32_WORD_RNG] csr_read_data; // Data read from CSR 31.106 -reg [`LM32_WORD_RNG] csr_read_data; 31.107 - 31.108 -///////////////////////////////////////////////////// 31.109 -// Internal nets and registers 31.110 -///////////////////////////////////////////////////// 31.111 - 31.112 -wire [interrupts-1:0] asserted; // Which interrupts are currently being asserted 31.113 -//pragma attribute asserted preserve_signal true 31.114 -wire [interrupts-1:0] interrupt_n_exception; 31.115 - 31.116 -// Interrupt CSRs 31.117 - 31.118 -reg ie; // Interrupt enable 31.119 -reg eie; // Exception interrupt enable 31.120 -`ifdef CFG_DEBUG_ENABLED 31.121 -reg bie; // Breakpoint interrupt enable 31.122 -`endif 31.123 -reg [interrupts-1:0] ip; // Interrupt pending 31.124 -reg [interrupts-1:0] im; // Interrupt mask 31.125 - 31.126 -///////////////////////////////////////////////////// 31.127 -// Combinational Logic 31.128 -///////////////////////////////////////////////////// 31.129 - 31.130 -// Determine which interrupts have occured and are unmasked 31.131 -assign interrupt_n_exception = ip & im; 31.132 - 31.133 -// Determine if any unmasked interrupts have occured 31.134 -assign interrupt_exception = (|interrupt_n_exception) & ie; 31.135 - 31.136 -// Determine which interrupts are currently being asserted (active-low) or are already pending 31.137 -assign asserted = ip | interrupt; 31.138 - 31.139 -assign ie_csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}}, 31.140 -`ifdef CFG_DEBUG_ENABLED 31.141 - bie, 31.142 -`else 31.143 - 1'b0, 31.144 -`endif 31.145 - eie, 31.146 - ie 31.147 - }; 31.148 -assign ip_csr_read_data = ip; 31.149 -assign im_csr_read_data = im; 31.150 -generate 31.151 - if (interrupts > 1) 31.152 - begin 31.153 -// CSR read 31.154 -always @(*) 31.155 -begin 31.156 - case (csr) 31.157 - `LM32_CSR_IE: csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}}, 31.158 -`ifdef CFG_DEBUG_ENABLED 31.159 - bie, 31.160 -`else 31.161 - 1'b0, 31.162 -`endif 31.163 - eie, 31.164 - ie 31.165 - }; 31.166 - `LM32_CSR_IP: csr_read_data = ip; 31.167 - `LM32_CSR_IM: csr_read_data = im; 31.168 - default: csr_read_data = {`LM32_WORD_WIDTH{1'bx}}; 31.169 - endcase 31.170 -end 31.171 - end 31.172 - else 31.173 - begin 31.174 -// CSR read 31.175 -always @(*) 31.176 -begin 31.177 - case (csr) 31.178 - `LM32_CSR_IE: csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}}, 31.179 -`ifdef CFG_DEBUG_ENABLED 31.180 - bie, 31.181 -`else 31.182 - 1'b0, 31.183 -`endif 31.184 - eie, 31.185 - ie 31.186 - }; 31.187 - `LM32_CSR_IP: csr_read_data = ip; 31.188 - default: csr_read_data = {`LM32_WORD_WIDTH{1'bx}}; 31.189 - endcase 31.190 -end 31.191 - end 31.192 -endgenerate 31.193 - 31.194 -///////////////////////////////////////////////////// 31.195 -// Sequential Logic 31.196 -///////////////////////////////////////////////////// 31.197 - 31.198 -generate 31.199 - if (interrupts > 1) 31.200 - begin 31.201 -// IE, IM, IP - Interrupt Enable, Interrupt Mask and Interrupt Pending CSRs 31.202 -always @(posedge clk_i `CFG_RESET_SENSITIVITY) 31.203 -begin 31.204 - if (rst_i == `TRUE) 31.205 - begin 31.206 - ie <= `FALSE; 31.207 - eie <= `FALSE; 31.208 -`ifdef CFG_DEBUG_ENABLED 31.209 - bie <= `FALSE; 31.210 -`endif 31.211 - im <= {interrupts{1'b0}}; 31.212 - ip <= {interrupts{1'b0}}; 31.213 - end 31.214 - else 31.215 - begin 31.216 - // Set IP bit when interrupt line is asserted 31.217 - ip <= asserted; 31.218 -`ifdef CFG_DEBUG_ENABLED 31.219 - if (non_debug_exception == `TRUE) 31.220 - begin 31.221 - // Save and then clear interrupt enable 31.222 - eie <= ie; 31.223 - ie <= `FALSE; 31.224 - end 31.225 - else if (debug_exception == `TRUE) 31.226 - begin 31.227 - // Save and then clear interrupt enable 31.228 - bie <= ie; 31.229 - ie <= `FALSE; 31.230 - end 31.231 -`else 31.232 - if (exception == `TRUE) 31.233 - begin 31.234 - // Save and then clear interrupt enable 31.235 - eie <= ie; 31.236 - ie <= `FALSE; 31.237 - end 31.238 -`endif 31.239 - else if (stall_x == `FALSE) 31.240 - begin 31.241 - if (eret_q_x == `TRUE) 31.242 - // Restore interrupt enable 31.243 - ie <= eie; 31.244 -`ifdef CFG_DEBUG_ENABLED 31.245 - else if (bret_q_x == `TRUE) 31.246 - // Restore interrupt enable 31.247 - ie <= bie; 31.248 -`endif 31.249 - else if (csr_write_enable == `TRUE) 31.250 - begin 31.251 - // Handle wcsr write 31.252 - if (csr == `LM32_CSR_IE) 31.253 - begin 31.254 - ie <= csr_write_data[0]; 31.255 - eie <= csr_write_data[1]; 31.256 -`ifdef CFG_DEBUG_ENABLED 31.257 - bie <= csr_write_data[2]; 31.258 -`endif 31.259 - end 31.260 - if (csr == `LM32_CSR_IM) 31.261 - im <= csr_write_data[interrupts-1:0]; 31.262 - if (csr == `LM32_CSR_IP) 31.263 - ip <= asserted & ~csr_write_data[interrupts-1:0]; 31.264 - end 31.265 - end 31.266 - end 31.267 -end 31.268 - end 31.269 -else 31.270 - begin 31.271 -// IE, IM, IP - Interrupt Enable, Interrupt Mask and Interrupt Pending CSRs 31.272 -always @(posedge clk_i `CFG_RESET_SENSITIVITY) 31.273 -begin 31.274 - if (rst_i == `TRUE) 31.275 - begin 31.276 - ie <= `FALSE; 31.277 - eie <= `FALSE; 31.278 -`ifdef CFG_DEBUG_ENABLED 31.279 - bie <= `FALSE; 31.280 -`endif 31.281 - ip <= {interrupts{1'b0}}; 31.282 - end 31.283 - else 31.284 - begin 31.285 - // Set IP bit when interrupt line is asserted 31.286 - ip <= asserted; 31.287 -`ifdef CFG_DEBUG_ENABLED 31.288 - if (non_debug_exception == `TRUE) 31.289 - begin 31.290 - // Save and then clear interrupt enable 31.291 - eie <= ie; 31.292 - ie <= `FALSE; 31.293 - end 31.294 - else if (debug_exception == `TRUE) 31.295 - begin 31.296 - // Save and then clear interrupt enable 31.297 - bie <= ie; 31.298 - ie <= `FALSE; 31.299 - end 31.300 -`else 31.301 - if (exception == `TRUE) 31.302 - begin 31.303 - // Save and then clear interrupt enable 31.304 - eie <= ie; 31.305 - ie <= `FALSE; 31.306 - end 31.307 -`endif 31.308 - else if (stall_x == `FALSE) 31.309 - begin 31.310 - if (eret_q_x == `TRUE) 31.311 - // Restore interrupt enable 31.312 - ie <= eie; 31.313 -`ifdef CFG_DEBUG_ENABLED 31.314 - else if (bret_q_x == `TRUE) 31.315 - // Restore interrupt enable 31.316 - ie <= bie; 31.317 -`endif 31.318 - else if (csr_write_enable == `TRUE) 31.319 - begin 31.320 - // Handle wcsr write 31.321 - if (csr == `LM32_CSR_IE) 31.322 - begin 31.323 - ie <= csr_write_data[0]; 31.324 - eie <= csr_write_data[1]; 31.325 -`ifdef CFG_DEBUG_ENABLED 31.326 - bie <= csr_write_data[2]; 31.327 -`endif 31.328 - end 31.329 - if (csr == `LM32_CSR_IP) 31.330 - ip <= asserted & ~csr_write_data[interrupts-1:0]; 31.331 - end 31.332 - end 31.333 - end 31.334 -end 31.335 - end 31.336 -endgenerate 31.337 - 31.338 -endmodule 31.339 -
32.1 diff -r 252df75c8f67 -r c336e674a37e lm32_jtag.v 32.2 --- a/lm32_jtag.v Sun Mar 06 21:17:31 2011 +0000 32.3 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 32.4 @@ -1,469 +0,0 @@ 32.5 -// ============================================================================= 32.6 -// COPYRIGHT NOTICE 32.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 32.8 -// ALL RIGHTS RESERVED 32.9 -// This confidential and proprietary software may be used only as authorised by 32.10 -// a licensing agreement from Lattice Semiconductor Corporation. 32.11 -// The entire notice above must be reproduced on all authorized copies and 32.12 -// copies may only be made to the extent permitted by a licensing agreement from 32.13 -// Lattice Semiconductor Corporation. 32.14 -// 32.15 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 32.16 -// 5555 NE Moore Court 408-826-6000 (other locations) 32.17 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 32.18 -// U.S.A email: techsupport@latticesemi.com 32.19 -// =============================================================================/ 32.20 -// FILE DETAILS 32.21 -// Project : LatticeMico32 32.22 -// File : lm32_jtag.v 32.23 -// Title : JTAG interface 32.24 -// Dependencies : lm32_include.v 32.25 -// Version : 6.1.17 32.26 -// : Initial Release 32.27 -// Version : 7.0SP2, 3.0 32.28 -// : No Change 32.29 -// Version : 3.1 32.30 -// : No Change 32.31 -// ============================================================================= 32.32 - 32.33 -`include "lm32_include.v" 32.34 - 32.35 -`ifdef CFG_JTAG_ENABLED 32.36 - 32.37 -`define LM32_DP 3'b000 32.38 -`define LM32_TX 3'b001 32.39 -`define LM32_RX 3'b010 32.40 - 32.41 -// LM32 Debug Protocol commands IDs 32.42 -`define LM32_DP_RNG 3:0 32.43 -`define LM32_DP_READ_MEMORY 4'b0001 32.44 -`define LM32_DP_WRITE_MEMORY 4'b0010 32.45 -`define LM32_DP_READ_SEQUENTIAL 4'b0011 32.46 -`define LM32_DP_WRITE_SEQUENTIAL 4'b0100 32.47 -`define LM32_DP_WRITE_CSR 4'b0101 32.48 -`define LM32_DP_BREAK 4'b0110 32.49 -`define LM32_DP_RESET 4'b0111 32.50 - 32.51 -// States for FSM 32.52 -`define LM32_JTAG_STATE_RNG 3:0 32.53 -`define LM32_JTAG_STATE_READ_COMMAND 4'h0 32.54 -`define LM32_JTAG_STATE_READ_BYTE_0 4'h1 32.55 -`define LM32_JTAG_STATE_READ_BYTE_1 4'h2 32.56 -`define LM32_JTAG_STATE_READ_BYTE_2 4'h3 32.57 -`define LM32_JTAG_STATE_READ_BYTE_3 4'h4 32.58 -`define LM32_JTAG_STATE_READ_BYTE_4 4'h5 32.59 -`define LM32_JTAG_STATE_PROCESS_COMMAND 4'h6 32.60 -`define LM32_JTAG_STATE_WAIT_FOR_MEMORY 4'h7 32.61 -`define LM32_JTAG_STATE_WAIT_FOR_CSR 4'h8 32.62 - 32.63 -///////////////////////////////////////////////////// 32.64 -// Module interface 32.65 -///////////////////////////////////////////////////// 32.66 - 32.67 -module lm32_jtag ( 32.68 - // ----- Inputs ------- 32.69 - clk_i, 32.70 - rst_i, 32.71 - jtag_clk, 32.72 - jtag_update, 32.73 - jtag_reg_q, 32.74 - jtag_reg_addr_q, 32.75 -`ifdef CFG_JTAG_UART_ENABLED 32.76 - csr, 32.77 - csr_write_enable, 32.78 - csr_write_data, 32.79 - stall_x, 32.80 -`endif 32.81 -`ifdef CFG_HW_DEBUG_ENABLED 32.82 - jtag_read_data, 32.83 - jtag_access_complete, 32.84 -`endif 32.85 -`ifdef CFG_DEBUG_ENABLED 32.86 - exception_q_w, 32.87 -`endif 32.88 - // ----- Outputs ------- 32.89 -`ifdef CFG_JTAG_UART_ENABLED 32.90 - jtx_csr_read_data, 32.91 - jrx_csr_read_data, 32.92 -`endif 32.93 -`ifdef CFG_HW_DEBUG_ENABLED 32.94 - jtag_csr_write_enable, 32.95 - jtag_csr_write_data, 32.96 - jtag_csr, 32.97 - jtag_read_enable, 32.98 - jtag_write_enable, 32.99 - jtag_write_data, 32.100 - jtag_address, 32.101 -`endif 32.102 -`ifdef CFG_DEBUG_ENABLED 32.103 - jtag_break, 32.104 - jtag_reset, 32.105 -`endif 32.106 - jtag_reg_d, 32.107 - jtag_reg_addr_d 32.108 - ); 32.109 - 32.110 -///////////////////////////////////////////////////// 32.111 -// Inputs 32.112 -///////////////////////////////////////////////////// 32.113 - 32.114 -input clk_i; // Clock 32.115 -input rst_i; // Reset 32.116 - 32.117 -input jtag_clk; // JTAG clock 32.118 -input jtag_update; // JTAG data register has been updated 32.119 -input [`LM32_BYTE_RNG] jtag_reg_q; // JTAG data register 32.120 -input [2:0] jtag_reg_addr_q; // JTAG data register 32.121 - 32.122 -`ifdef CFG_JTAG_UART_ENABLED 32.123 -input [`LM32_CSR_RNG] csr; // CSR to write 32.124 -input csr_write_enable; // CSR write enable 32.125 -input [`LM32_WORD_RNG] csr_write_data; // Data to write to specified CSR 32.126 -input stall_x; // Stall instruction in X stage 32.127 -`endif 32.128 -`ifdef CFG_HW_DEBUG_ENABLED 32.129 -input [`LM32_BYTE_RNG] jtag_read_data; // Data read from requested address 32.130 -input jtag_access_complete; // Memory access if complete 32.131 -`endif 32.132 -`ifdef CFG_DEBUG_ENABLED 32.133 -input exception_q_w; // Indicates an exception has occured in W stage 32.134 -`endif 32.135 - 32.136 -///////////////////////////////////////////////////// 32.137 -// Outputs 32.138 -///////////////////////////////////////////////////// 32.139 - 32.140 -`ifdef CFG_JTAG_UART_ENABLED 32.141 -output [`LM32_WORD_RNG] jtx_csr_read_data; // Value of JTX CSR for rcsr instructions 32.142 -wire [`LM32_WORD_RNG] jtx_csr_read_data; 32.143 -output [`LM32_WORD_RNG] jrx_csr_read_data; // Value of JRX CSR for rcsr instructions 32.144 -wire [`LM32_WORD_RNG] jrx_csr_read_data; 32.145 -`endif 32.146 -`ifdef CFG_HW_DEBUG_ENABLED 32.147 -output jtag_csr_write_enable; // CSR write enable 32.148 -reg jtag_csr_write_enable; 32.149 -output [`LM32_WORD_RNG] jtag_csr_write_data; // Data to write to specified CSR 32.150 -wire [`LM32_WORD_RNG] jtag_csr_write_data; 32.151 -output [`LM32_CSR_RNG] jtag_csr; // CSR to write 32.152 -wire [`LM32_CSR_RNG] jtag_csr; 32.153 -output jtag_read_enable; // Memory read enable 32.154 -reg jtag_read_enable; 32.155 -output jtag_write_enable; // Memory write enable 32.156 -reg jtag_write_enable; 32.157 -output [`LM32_BYTE_RNG] jtag_write_data; // Data to write to specified address 32.158 -wire [`LM32_BYTE_RNG] jtag_write_data; 32.159 -output [`LM32_WORD_RNG] jtag_address; // Memory read/write address 32.160 -wire [`LM32_WORD_RNG] jtag_address; 32.161 -`endif 32.162 -`ifdef CFG_DEBUG_ENABLED 32.163 -output jtag_break; // Request to raise a breakpoint exception 32.164 -reg jtag_break; 32.165 -output jtag_reset; // Request to raise a reset exception 32.166 -reg jtag_reset; 32.167 -`endif 32.168 -output [`LM32_BYTE_RNG] jtag_reg_d; 32.169 -reg [`LM32_BYTE_RNG] jtag_reg_d; 32.170 -output [2:0] jtag_reg_addr_d; 32.171 -wire [2:0] jtag_reg_addr_d; 32.172 - 32.173 -///////////////////////////////////////////////////// 32.174 -// Internal nets and registers 32.175 -///////////////////////////////////////////////////// 32.176 - 32.177 -reg rx_update; // Clock-domain crossing registers 32.178 -reg rx_update_r; // Registered version of rx_update 32.179 -reg rx_update_r_r; // Registered version of rx_update_r 32.180 -reg rx_update_r_r_r; // Registered version of rx_update_r_r 32.181 - 32.182 -// These wires come from the JTAG clock domain. 32.183 -// They have been held unchanged for an entire JTAG clock cycle before the jtag_update toggle flips 32.184 -wire [`LM32_BYTE_RNG] rx_byte; 32.185 -wire [2:0] rx_addr; 32.186 - 32.187 -`ifdef CFG_JTAG_UART_ENABLED 32.188 -reg [`LM32_BYTE_RNG] uart_tx_byte; // UART TX data 32.189 -reg uart_tx_valid; // TX data is valid 32.190 -reg [`LM32_BYTE_RNG] uart_rx_byte; // UART RX data 32.191 -reg uart_rx_valid; // RX data is valid 32.192 -`endif 32.193 - 32.194 -reg [`LM32_DP_RNG] command; // The last received command 32.195 -`ifdef CFG_HW_DEBUG_ENABLED 32.196 -reg [`LM32_BYTE_RNG] jtag_byte_0; // Registers to hold command paramaters 32.197 -reg [`LM32_BYTE_RNG] jtag_byte_1; 32.198 -reg [`LM32_BYTE_RNG] jtag_byte_2; 32.199 -reg [`LM32_BYTE_RNG] jtag_byte_3; 32.200 -reg [`LM32_BYTE_RNG] jtag_byte_4; 32.201 -reg processing; // Indicates if we're still processing a memory read/write 32.202 -`endif 32.203 - 32.204 -reg [`LM32_JTAG_STATE_RNG] state; // Current state of FSM 32.205 - 32.206 -///////////////////////////////////////////////////// 32.207 -// Combinational Logic 32.208 -///////////////////////////////////////////////////// 32.209 - 32.210 -`ifdef CFG_HW_DEBUG_ENABLED 32.211 -assign jtag_csr_write_data = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3}; 32.212 -assign jtag_csr = jtag_byte_4[`LM32_CSR_RNG]; 32.213 -assign jtag_address = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3}; 32.214 -assign jtag_write_data = jtag_byte_4; 32.215 -`endif 32.216 - 32.217 -// Generate status flags for reading via the JTAG interface 32.218 -`ifdef CFG_JTAG_UART_ENABLED 32.219 -assign jtag_reg_addr_d[1:0] = {uart_rx_valid, uart_tx_valid}; 32.220 -`else 32.221 -assign jtag_reg_addr_d[1:0] = 2'b00; 32.222 -`endif 32.223 -`ifdef CFG_HW_DEBUG_ENABLED 32.224 -assign jtag_reg_addr_d[2] = processing; 32.225 -`else 32.226 -assign jtag_reg_addr_d[2] = 1'b0; 32.227 -`endif 32.228 - 32.229 -`ifdef CFG_JTAG_UART_ENABLED 32.230 -assign jtx_csr_read_data = {{`LM32_WORD_WIDTH-9{1'b0}}, uart_tx_valid, 8'h00}; 32.231 -assign jrx_csr_read_data = {{`LM32_WORD_WIDTH-9{1'b0}}, uart_rx_valid, uart_rx_byte}; 32.232 -`endif 32.233 - 32.234 -///////////////////////////////////////////////////// 32.235 -// Sequential Logic 32.236 -///////////////////////////////////////////////////// 32.237 - 32.238 -assign rx_byte = jtag_reg_q; 32.239 -assign rx_addr = jtag_reg_addr_q; 32.240 - 32.241 -// The JTAG latched jtag_reg[_addr]_q at least one JTCK before jtag_update is raised 32.242 -// Thus, they are stable (and safe to sample) when jtag_update is high 32.243 -always @(posedge clk_i `CFG_RESET_SENSITIVITY) 32.244 -begin 32.245 - if (rst_i == `TRUE) 32.246 - begin 32.247 - rx_update <= 1'b0; 32.248 - rx_update_r <= 1'b0; 32.249 - rx_update_r_r <= 1'b0; 32.250 - rx_update_r_r_r <= 1'b0; 32.251 - end 32.252 - else 32.253 - begin 32.254 - rx_update <= jtag_update; 32.255 - rx_update_r <= rx_update; 32.256 - rx_update_r_r <= rx_update_r; 32.257 - rx_update_r_r_r <= rx_update_r_r; 32.258 - end 32.259 -end 32.260 - 32.261 -// LM32 debug protocol state machine 32.262 -always @(posedge clk_i `CFG_RESET_SENSITIVITY) 32.263 -begin 32.264 - if (rst_i == `TRUE) 32.265 - begin 32.266 - state <= `LM32_JTAG_STATE_READ_COMMAND; 32.267 - command <= 4'b0000; 32.268 - jtag_reg_d <= 8'h00; 32.269 -`ifdef CFG_HW_DEBUG_ENABLED 32.270 - processing <= `FALSE; 32.271 - jtag_csr_write_enable <= `FALSE; 32.272 - jtag_read_enable <= `FALSE; 32.273 - jtag_write_enable <= `FALSE; 32.274 -`endif 32.275 -`ifdef CFG_DEBUG_ENABLED 32.276 - jtag_break <= `FALSE; 32.277 - jtag_reset <= `FALSE; 32.278 -`endif 32.279 -`ifdef CFG_JTAG_UART_ENABLED 32.280 - uart_tx_byte <= 8'h00; 32.281 - uart_tx_valid <= `FALSE; 32.282 - uart_rx_byte <= 8'h00; 32.283 - uart_rx_valid <= `FALSE; 32.284 -`endif 32.285 - end 32.286 - else 32.287 - begin 32.288 -`ifdef CFG_JTAG_UART_ENABLED 32.289 - if ((csr_write_enable == `TRUE) && (stall_x == `FALSE)) 32.290 - begin 32.291 - case (csr) 32.292 - `LM32_CSR_JTX: 32.293 - begin 32.294 - // Set flag indicating data is available 32.295 - uart_tx_byte <= csr_write_data[`LM32_BYTE_0_RNG]; 32.296 - uart_tx_valid <= `TRUE; 32.297 - end 32.298 - `LM32_CSR_JRX: 32.299 - begin 32.300 - // Clear flag indidicating data has been received 32.301 - uart_rx_valid <= `FALSE; 32.302 - end 32.303 - endcase 32.304 - end 32.305 -`endif 32.306 -`ifdef CFG_DEBUG_ENABLED 32.307 - // When an exception has occured, clear the requests 32.308 - if (exception_q_w == `TRUE) 32.309 - begin 32.310 - jtag_break <= `FALSE; 32.311 - jtag_reset <= `FALSE; 32.312 - end 32.313 -`endif 32.314 - case (state) 32.315 - `LM32_JTAG_STATE_READ_COMMAND: 32.316 - begin 32.317 - // Wait for rx register to toggle which indicates new data is available 32.318 - if ((~rx_update_r_r_r & rx_update_r_r) == `TRUE) 32.319 - begin 32.320 - command <= rx_byte[7:4]; 32.321 - case (rx_addr) 32.322 -`ifdef CFG_DEBUG_ENABLED 32.323 - `LM32_DP: 32.324 - begin 32.325 - case (rx_byte[7:4]) 32.326 -`ifdef CFG_HW_DEBUG_ENABLED 32.327 - `LM32_DP_READ_MEMORY: 32.328 - state <= `LM32_JTAG_STATE_READ_BYTE_0; 32.329 - `LM32_DP_READ_SEQUENTIAL: 32.330 - begin 32.331 - {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1; 32.332 - state <= `LM32_JTAG_STATE_PROCESS_COMMAND; 32.333 - end 32.334 - `LM32_DP_WRITE_MEMORY: 32.335 - state <= `LM32_JTAG_STATE_READ_BYTE_0; 32.336 - `LM32_DP_WRITE_SEQUENTIAL: 32.337 - begin 32.338 - {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1; 32.339 - state <= 5; 32.340 - end 32.341 - `LM32_DP_WRITE_CSR: 32.342 - state <= `LM32_JTAG_STATE_READ_BYTE_0; 32.343 -`endif 32.344 - `LM32_DP_BREAK: 32.345 - begin 32.346 -`ifdef CFG_JTAG_UART_ENABLED 32.347 - uart_rx_valid <= `FALSE; 32.348 - uart_tx_valid <= `FALSE; 32.349 -`endif 32.350 - jtag_break <= `TRUE; 32.351 - end 32.352 - `LM32_DP_RESET: 32.353 - begin 32.354 -`ifdef CFG_JTAG_UART_ENABLED 32.355 - uart_rx_valid <= `FALSE; 32.356 - uart_tx_valid <= `FALSE; 32.357 -`endif 32.358 - jtag_reset <= `TRUE; 32.359 - end 32.360 - endcase 32.361 - end 32.362 -`endif 32.363 -`ifdef CFG_JTAG_UART_ENABLED 32.364 - `LM32_TX: 32.365 - begin 32.366 - uart_rx_byte <= rx_byte; 32.367 - uart_rx_valid <= `TRUE; 32.368 - end 32.369 - `LM32_RX: 32.370 - begin 32.371 - jtag_reg_d <= uart_tx_byte; 32.372 - uart_tx_valid <= `FALSE; 32.373 - end 32.374 -`endif 32.375 - default: 32.376 - ; 32.377 - endcase 32.378 - end 32.379 - end 32.380 -`ifdef CFG_HW_DEBUG_ENABLED 32.381 - `LM32_JTAG_STATE_READ_BYTE_0: 32.382 - begin 32.383 - if ((~rx_update_r_r_r & rx_update_r_r) == `TRUE) 32.384 - begin 32.385 - jtag_byte_0 <= rx_byte; 32.386 - state <= `LM32_JTAG_STATE_READ_BYTE_1; 32.387 - end 32.388 - end 32.389 - `LM32_JTAG_STATE_READ_BYTE_1: 32.390 - begin 32.391 - if ((~rx_update_r_r_r & rx_update_r_r) == `TRUE) 32.392 - begin 32.393 - jtag_byte_1 <= rx_byte; 32.394 - state <= `LM32_JTAG_STATE_READ_BYTE_2; 32.395 - end 32.396 - end 32.397 - `LM32_JTAG_STATE_READ_BYTE_2: 32.398 - begin 32.399 - if ((~rx_update_r_r_r & rx_update_r_r) == `TRUE) 32.400 - begin 32.401 - jtag_byte_2 <= rx_byte; 32.402 - state <= `LM32_JTAG_STATE_READ_BYTE_3; 32.403 - end 32.404 - end 32.405 - `LM32_JTAG_STATE_READ_BYTE_3: 32.406 - begin 32.407 - if ((~rx_update_r_r_r & rx_update_r_r) == `TRUE) 32.408 - begin 32.409 - jtag_byte_3 <= rx_byte; 32.410 - if (command == `LM32_DP_READ_MEMORY) 32.411 - state <= `LM32_JTAG_STATE_PROCESS_COMMAND; 32.412 - else 32.413 - state <= `LM32_JTAG_STATE_READ_BYTE_4; 32.414 - end 32.415 - end 32.416 - `LM32_JTAG_STATE_READ_BYTE_4: 32.417 - begin 32.418 - if ((~rx_update_r_r_r & rx_update_r_r) == `TRUE) 32.419 - begin 32.420 - jtag_byte_4 <= rx_byte; 32.421 - state <= `LM32_JTAG_STATE_PROCESS_COMMAND; 32.422 - end 32.423 - end 32.424 - `LM32_JTAG_STATE_PROCESS_COMMAND: 32.425 - begin 32.426 - case (command) 32.427 - `LM32_DP_READ_MEMORY, 32.428 - `LM32_DP_READ_SEQUENTIAL: 32.429 - begin 32.430 - jtag_read_enable <= `TRUE; 32.431 - processing <= `TRUE; 32.432 - state <= `LM32_JTAG_STATE_WAIT_FOR_MEMORY; 32.433 - end 32.434 - `LM32_DP_WRITE_MEMORY, 32.435 - `LM32_DP_WRITE_SEQUENTIAL: 32.436 - begin 32.437 - jtag_write_enable <= `TRUE; 32.438 - processing <= `TRUE; 32.439 - state <= `LM32_JTAG_STATE_WAIT_FOR_MEMORY; 32.440 - end 32.441 - `LM32_DP_WRITE_CSR: 32.442 - begin 32.443 - jtag_csr_write_enable <= `TRUE; 32.444 - processing <= `TRUE; 32.445 - state <= `LM32_JTAG_STATE_WAIT_FOR_CSR; 32.446 - end 32.447 - endcase 32.448 - end 32.449 - `LM32_JTAG_STATE_WAIT_FOR_MEMORY: 32.450 - begin 32.451 - if (jtag_access_complete == `TRUE) 32.452 - begin 32.453 - jtag_read_enable <= `FALSE; 32.454 - jtag_reg_d <= jtag_read_data; 32.455 - jtag_write_enable <= `FALSE; 32.456 - processing <= `FALSE; 32.457 - state <= `LM32_JTAG_STATE_READ_COMMAND; 32.458 - end 32.459 - end 32.460 - `LM32_JTAG_STATE_WAIT_FOR_CSR: 32.461 - begin 32.462 - jtag_csr_write_enable <= `FALSE; 32.463 - processing <= `FALSE; 32.464 - state <= `LM32_JTAG_STATE_READ_COMMAND; 32.465 - end 32.466 -`endif 32.467 - endcase 32.468 - end 32.469 -end 32.470 - 32.471 -endmodule 32.472 - 32.473 -`endif
33.1 diff -r 252df75c8f67 -r c336e674a37e lm32_load_store_unit.v 33.2 --- a/lm32_load_store_unit.v Sun Mar 06 21:17:31 2011 +0000 33.3 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 33.4 @@ -1,806 +0,0 @@ 33.5 -// ============================================================================= 33.6 -// COPYRIGHT NOTICE 33.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 33.8 -// ALL RIGHTS RESERVED 33.9 -// This confidential and proprietary software may be used only as authorised by 33.10 -// a licensing agreement from Lattice Semiconductor Corporation. 33.11 -// The entire notice above must be reproduced on all authorized copies and 33.12 -// copies may only be made to the extent permitted by a licensing agreement from 33.13 -// Lattice Semiconductor Corporation. 33.14 -// 33.15 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 33.16 -// 5555 NE Moore Court 408-826-6000 (other locations) 33.17 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 33.18 -// U.S.A email: techsupport@latticesemi.com 33.19 -// =============================================================================/ 33.20 -// FILE DETAILS 33.21 -// Project : LatticeMico32 33.22 -// File : lm32_load_store_unit.v 33.23 -// Title : Load and store unit 33.24 -// Dependencies : lm32_include.v 33.25 -// Version : 6.1.17 33.26 -// : Initial Release 33.27 -// Version : 7.0SP2, 3.0 33.28 -// : No Change 33.29 -// Version : 3.1 33.30 -// : Instead of disallowing an instruction cache miss on a data cache 33.31 -// : miss, both can now occur at the same time. If both occur at same 33.32 -// : time, then restart address is the address of instruction that 33.33 -// : caused data cache miss. 33.34 -// Version : 3.2 33.35 -// : EBRs use SYNC resets instead of ASYNC resets. 33.36 -// Version : 3.3 33.37 -// : Support for new non-cacheable Data Memory that is accessible by 33.38 -// : the data port and has a one cycle access latency. 33.39 -// Version : 3.4 33.40 -// : No change 33.41 -// Version : 3.5 33.42 -// : Bug fix: Inline memory is correctly generated if it is not a 33.43 -// : power-of-two 33.44 -// ============================================================================= 33.45 - 33.46 -`include "lm32_include.v" 33.47 - 33.48 -///////////////////////////////////////////////////// 33.49 -// Module interface 33.50 -///////////////////////////////////////////////////// 33.51 - 33.52 -module lm32_load_store_unit ( 33.53 - // ----- Inputs ------- 33.54 - clk_i, 33.55 - rst_i, 33.56 - // From pipeline 33.57 - stall_a, 33.58 - stall_x, 33.59 - stall_m, 33.60 - kill_m, 33.61 - exception_m, 33.62 - store_operand_x, 33.63 - load_store_address_x, 33.64 - load_store_address_m, 33.65 - load_store_address_w, 33.66 - load_x, 33.67 - store_x, 33.68 - load_q_x, 33.69 - store_q_x, 33.70 - load_q_m, 33.71 - store_q_m, 33.72 - sign_extend_x, 33.73 - size_x, 33.74 -`ifdef CFG_DCACHE_ENABLED 33.75 - dflush, 33.76 -`endif 33.77 -`ifdef CFG_IROM_ENABLED 33.78 - irom_data_m, 33.79 -`endif 33.80 - // From Wishbone 33.81 - d_dat_i, 33.82 - d_ack_i, 33.83 - d_err_i, 33.84 - d_rty_i, 33.85 - // ----- Outputs ------- 33.86 - // To pipeline 33.87 -`ifdef CFG_DCACHE_ENABLED 33.88 - dcache_refill_request, 33.89 - dcache_restart_request, 33.90 - dcache_stall_request, 33.91 - dcache_refilling, 33.92 -`endif 33.93 -`ifdef CFG_IROM_ENABLED 33.94 - irom_store_data_m, 33.95 - irom_address_xm, 33.96 - irom_we_xm, 33.97 - irom_stall_request_x, 33.98 -`endif 33.99 - load_data_w, 33.100 - stall_wb_load, 33.101 - // To Wishbone 33.102 - d_dat_o, 33.103 - d_adr_o, 33.104 - d_cyc_o, 33.105 - d_sel_o, 33.106 - d_stb_o, 33.107 - d_we_o, 33.108 - d_cti_o, 33.109 - d_lock_o, 33.110 - d_bte_o 33.111 - ); 33.112 - 33.113 -///////////////////////////////////////////////////// 33.114 -// Parameters 33.115 -///////////////////////////////////////////////////// 33.116 - 33.117 -parameter associativity = 1; // Associativity of the cache (Number of ways) 33.118 -parameter sets = 512; // Number of sets 33.119 -parameter bytes_per_line = 16; // Number of bytes per cache line 33.120 -parameter base_address = 0; // Base address of cachable memory 33.121 -parameter limit = 0; // Limit (highest address) of cachable memory 33.122 - 33.123 -// For bytes_per_line == 4, we set 1 so part-select range isn't reversed, even though not really used 33.124 -localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2; 33.125 -localparam addr_offset_lsb = 2; 33.126 -localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1); 33.127 - 33.128 -///////////////////////////////////////////////////// 33.129 -// Inputs 33.130 -///////////////////////////////////////////////////// 33.131 - 33.132 -input clk_i; // Clock 33.133 -input rst_i; // Reset 33.134 - 33.135 -input stall_a; // A stage stall 33.136 -input stall_x; // X stage stall 33.137 -input stall_m; // M stage stall 33.138 -input kill_m; // Kill instruction in M stage 33.139 -input exception_m; // An exception occured in the M stage 33.140 - 33.141 -input [`LM32_WORD_RNG] store_operand_x; // Data read from register to store 33.142 -input [`LM32_WORD_RNG] load_store_address_x; // X stage load/store address 33.143 -input [`LM32_WORD_RNG] load_store_address_m; // M stage load/store address 33.144 -input [1:0] load_store_address_w; // W stage load/store address (only least two significant bits are needed) 33.145 -input load_x; // Load instruction in X stage 33.146 -input store_x; // Store instruction in X stage 33.147 -input load_q_x; // Load instruction in X stage 33.148 -input store_q_x; // Store instruction in X stage 33.149 -input load_q_m; // Load instruction in M stage 33.150 -input store_q_m; // Store instruction in M stage 33.151 -input sign_extend_x; // Whether load instruction in X stage should sign extend or zero extend 33.152 -input [`LM32_SIZE_RNG] size_x; // Size of load or store (byte, hword, word) 33.153 - 33.154 -`ifdef CFG_DCACHE_ENABLED 33.155 -input dflush; // Flush the data cache 33.156 -`endif 33.157 - 33.158 -`ifdef CFG_IROM_ENABLED 33.159 -input [`LM32_WORD_RNG] irom_data_m; // Data from Instruction-ROM 33.160 -`endif 33.161 - 33.162 -input [`LM32_WORD_RNG] d_dat_i; // Data Wishbone interface read data 33.163 -input d_ack_i; // Data Wishbone interface acknowledgement 33.164 -input d_err_i; // Data Wishbone interface error 33.165 -input d_rty_i; // Data Wishbone interface retry 33.166 - 33.167 -///////////////////////////////////////////////////// 33.168 -// Outputs 33.169 -///////////////////////////////////////////////////// 33.170 - 33.171 -`ifdef CFG_DCACHE_ENABLED 33.172 -output dcache_refill_request; // Request to refill data cache 33.173 -wire dcache_refill_request; 33.174 -output dcache_restart_request; // Request to restart the instruction that caused a data cache miss 33.175 -wire dcache_restart_request; 33.176 -output dcache_stall_request; // Data cache stall request 33.177 -wire dcache_stall_request; 33.178 -output dcache_refilling; 33.179 -wire dcache_refilling; 33.180 -`endif 33.181 - 33.182 -`ifdef CFG_IROM_ENABLED 33.183 -output irom_store_data_m; // Store data to Instruction ROM 33.184 -wire [`LM32_WORD_RNG] irom_store_data_m; 33.185 -output [`LM32_WORD_RNG] irom_address_xm; // Load/store address to Instruction ROM 33.186 -wire [`LM32_WORD_RNG] irom_address_xm; 33.187 -output irom_we_xm; // Write-enable of 2nd port of Instruction ROM 33.188 -wire irom_we_xm; 33.189 -output irom_stall_request_x; // Stall instruction in D stage 33.190 -wire irom_stall_request_x; 33.191 -`endif 33.192 - 33.193 -output [`LM32_WORD_RNG] load_data_w; // Result of a load instruction 33.194 -reg [`LM32_WORD_RNG] load_data_w; 33.195 -output stall_wb_load; // Request to stall pipeline due to a load from the Wishbone interface 33.196 -reg stall_wb_load; 33.197 - 33.198 -output [`LM32_WORD_RNG] d_dat_o; // Data Wishbone interface write data 33.199 -reg [`LM32_WORD_RNG] d_dat_o; 33.200 -output [`LM32_WORD_RNG] d_adr_o; // Data Wishbone interface address 33.201 -reg [`LM32_WORD_RNG] d_adr_o; 33.202 -output d_cyc_o; // Data Wishbone interface cycle 33.203 -reg d_cyc_o; 33.204 -output [`LM32_BYTE_SELECT_RNG] d_sel_o; // Data Wishbone interface byte select 33.205 -reg [`LM32_BYTE_SELECT_RNG] d_sel_o; 33.206 -output d_stb_o; // Data Wishbone interface strobe 33.207 -reg d_stb_o; 33.208 -output d_we_o; // Data Wishbone interface write enable 33.209 -reg d_we_o; 33.210 -output [`LM32_CTYPE_RNG] d_cti_o; // Data Wishbone interface cycle type 33.211 -reg [`LM32_CTYPE_RNG] d_cti_o; 33.212 -output d_lock_o; // Date Wishbone interface lock bus 33.213 -reg d_lock_o; 33.214 -output [`LM32_BTYPE_RNG] d_bte_o; // Data Wishbone interface burst type 33.215 -wire [`LM32_BTYPE_RNG] d_bte_o; 33.216 - 33.217 -///////////////////////////////////////////////////// 33.218 -// Internal nets and registers 33.219 -///////////////////////////////////////////////////// 33.220 - 33.221 -// Microcode pipeline registers - See inputs for description 33.222 -reg [`LM32_SIZE_RNG] size_m; 33.223 -reg [`LM32_SIZE_RNG] size_w; 33.224 -reg sign_extend_m; 33.225 -reg sign_extend_w; 33.226 -reg [`LM32_WORD_RNG] store_data_x; 33.227 -reg [`LM32_WORD_RNG] store_data_m; 33.228 -reg [`LM32_BYTE_SELECT_RNG] byte_enable_x; 33.229 -reg [`LM32_BYTE_SELECT_RNG] byte_enable_m; 33.230 -wire [`LM32_WORD_RNG] data_m; 33.231 -reg [`LM32_WORD_RNG] data_w; 33.232 - 33.233 -`ifdef CFG_DCACHE_ENABLED 33.234 -wire dcache_select_x; // Select data cache to load from / store to 33.235 -reg dcache_select_m; 33.236 -wire [`LM32_WORD_RNG] dcache_data_m; // Data read from cache 33.237 -wire [`LM32_WORD_RNG] dcache_refill_address; // Address to refill data cache from 33.238 -reg dcache_refill_ready; // Indicates the next word of refill data is ready 33.239 -wire [`LM32_CTYPE_RNG] first_cycle_type; // First Wishbone cycle type 33.240 -wire [`LM32_CTYPE_RNG] next_cycle_type; // Next Wishbone cycle type 33.241 -wire last_word; // Indicates if this is the last word in the cache line 33.242 -wire [`LM32_WORD_RNG] first_address; // First cache refill address 33.243 -`endif 33.244 -`ifdef CFG_DRAM_ENABLED 33.245 -wire dram_select_x; // Select data RAM to load from / store to 33.246 -reg dram_select_m; 33.247 -reg dram_bypass_en; // RAW in data RAM; read latched (bypass) value rather than value from memory 33.248 -reg [`LM32_WORD_RNG] dram_bypass_data; // Latched value of store'd data to data RAM 33.249 -wire [`LM32_WORD_RNG] dram_data_out; // Data read from data RAM 33.250 -wire [`LM32_WORD_RNG] dram_data_m; // Data read from data RAM: bypass value or value from memory 33.251 -wire [`LM32_WORD_RNG] dram_store_data_m; // Data to write to RAM 33.252 -`endif 33.253 -wire wb_select_x; // Select Wishbone to load from / store to 33.254 -`ifdef CFG_IROM_ENABLED 33.255 -wire irom_select_x; // Select instruction ROM to load from / store to 33.256 -reg irom_select_m; 33.257 -`endif 33.258 -reg wb_select_m; 33.259 -reg [`LM32_WORD_RNG] wb_data_m; // Data read from Wishbone 33.260 -reg wb_load_complete; // Indicates when a Wishbone load is complete 33.261 - 33.262 -///////////////////////////////////////////////////// 33.263 -// Functions 33.264 -///////////////////////////////////////////////////// 33.265 - 33.266 -`include "lm32_functions.v" 33.267 - 33.268 -///////////////////////////////////////////////////// 33.269 -// Instantiations 33.270 -///////////////////////////////////////////////////// 33.271 - 33.272 -`ifdef CFG_DRAM_ENABLED 33.273 - // Data RAM 33.274 - pmi_ram_dp_true 33.275 - #( 33.276 - // ----- Parameters ------- 33.277 - .pmi_family (`LATTICE_FAMILY), 33.278 - 33.279 - //.pmi_addr_depth_a (1 << (clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)), 33.280 - //.pmi_addr_width_a ((clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)), 33.281 - //.pmi_data_width_a (`LM32_WORD_WIDTH), 33.282 - //.pmi_addr_depth_b (1 << (clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)), 33.283 - //.pmi_addr_width_b ((clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)), 33.284 - //.pmi_data_width_b (`LM32_WORD_WIDTH), 33.285 - 33.286 - .pmi_addr_depth_a (`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1), 33.287 - .pmi_addr_width_a (clogb2_v1(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)), 33.288 - .pmi_data_width_a (`LM32_WORD_WIDTH), 33.289 - .pmi_addr_depth_b (`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1), 33.290 - .pmi_addr_width_b (clogb2_v1(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)), 33.291 - .pmi_data_width_b (`LM32_WORD_WIDTH), 33.292 - 33.293 - .pmi_regmode_a ("noreg"), 33.294 - .pmi_regmode_b ("noreg"), 33.295 - .pmi_gsr ("enable"), 33.296 - .pmi_resetmode ("sync"), 33.297 - .pmi_init_file (`CFG_DRAM_INIT_FILE), 33.298 - .pmi_init_file_format (`CFG_DRAM_INIT_FILE_FORMAT), 33.299 - .module_type ("pmi_ram_dp_true") 33.300 - ) 33.301 - ram ( 33.302 - // ----- Inputs ------- 33.303 - .ClockA (clk_i), 33.304 - .ClockB (clk_i), 33.305 - .ResetA (rst_i), 33.306 - .ResetB (rst_i), 33.307 - .DataInA ({32{1'b0}}), 33.308 - .DataInB (dram_store_data_m), 33.309 - .AddressA (load_store_address_x[(clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)+2-1:2]), 33.310 - .AddressB (load_store_address_m[(clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)+2-1:2]), 33.311 - // .ClockEnA (!stall_x & (load_x | store_x)), 33.312 - .ClockEnA (!stall_x), 33.313 - .ClockEnB (!stall_m), 33.314 - .WrA (`FALSE), 33.315 - .WrB (store_q_m & dram_select_m), 33.316 - // ----- Outputs ------- 33.317 - .QA (dram_data_out), 33.318 - .QB () 33.319 - ); 33.320 - 33.321 - /*---------------------------------------------------------------------- 33.322 - EBRs cannot perform reads from location 'written to' on the same clock 33.323 - edge. Therefore bypass logic is required to latch the store'd value 33.324 - and use it for the load (instead of value from memory). 33.325 - ----------------------------------------------------------------------*/ 33.326 - always @(posedge clk_i `CFG_RESET_SENSITIVITY) 33.327 - if (rst_i == `TRUE) 33.328 - begin 33.329 - dram_bypass_en <= `FALSE; 33.330 - dram_bypass_data <= 0; 33.331 - end 33.332 - else 33.333 - begin 33.334 - if (stall_x == `FALSE) 33.335 - dram_bypass_data <= dram_store_data_m; 33.336 - 33.337 - if ( (stall_m == `FALSE) 33.338 - && (stall_x == `FALSE) 33.339 - && (store_q_m == `TRUE) 33.340 - && ( (load_x == `TRUE) 33.341 - || (store_x == `TRUE) 33.342 - ) 33.343 - && (load_store_address_x[(`LM32_WORD_WIDTH-1):2] == load_store_address_m[(`LM32_WORD_WIDTH-1):2]) 33.344 - ) 33.345 - dram_bypass_en <= `TRUE; 33.346 - else 33.347 - if ( (dram_bypass_en == `TRUE) 33.348 - && (stall_x == `FALSE) 33.349 - ) 33.350 - dram_bypass_en <= `FALSE; 33.351 - end 33.352 - 33.353 - assign dram_data_m = dram_bypass_en ? dram_bypass_data : dram_data_out; 33.354 -`endif 33.355 - 33.356 -`ifdef CFG_DCACHE_ENABLED 33.357 -// Data cache 33.358 -lm32_dcache #( 33.359 - .associativity (associativity), 33.360 - .sets (sets), 33.361 - .bytes_per_line (bytes_per_line), 33.362 - .base_address (base_address), 33.363 - .limit (limit) 33.364 - ) dcache ( 33.365 - // ----- Inputs ----- 33.366 - .clk_i (clk_i), 33.367 - .rst_i (rst_i), 33.368 - .stall_a (stall_a), 33.369 - .stall_x (stall_x), 33.370 - .stall_m (stall_m), 33.371 - .address_x (load_store_address_x), 33.372 - .address_m (load_store_address_m), 33.373 - .load_q_m (load_q_m & dcache_select_m), 33.374 - .store_q_m (store_q_m & dcache_select_m), 33.375 - .store_data (store_data_m), 33.376 - .store_byte_select (byte_enable_m & {4{dcache_select_m}}), 33.377 - .refill_ready (dcache_refill_ready), 33.378 - .refill_data (wb_data_m), 33.379 - .dflush (dflush), 33.380 - // ----- Outputs ----- 33.381 - .stall_request (dcache_stall_request), 33.382 - .restart_request (dcache_restart_request), 33.383 - .refill_request (dcache_refill_request), 33.384 - .refill_address (dcache_refill_address), 33.385 - .refilling (dcache_refilling), 33.386 - .load_data (dcache_data_m) 33.387 - ); 33.388 -`endif 33.389 - 33.390 -///////////////////////////////////////////////////// 33.391 -// Combinational Logic 33.392 -///////////////////////////////////////////////////// 33.393 - 33.394 -// Select where data should be loaded from / stored to 33.395 -`ifdef CFG_DRAM_ENABLED 33.396 - assign dram_select_x = (load_store_address_x >= `CFG_DRAM_BASE_ADDRESS) 33.397 - && (load_store_address_x <= `CFG_DRAM_LIMIT); 33.398 -`endif 33.399 - 33.400 -`ifdef CFG_IROM_ENABLED 33.401 - assign irom_select_x = (load_store_address_x >= `CFG_IROM_BASE_ADDRESS) 33.402 - && (load_store_address_x <= `CFG_IROM_LIMIT); 33.403 -`endif 33.404 - 33.405 -`ifdef CFG_DCACHE_ENABLED 33.406 - assign dcache_select_x = (load_store_address_x >= `CFG_DCACHE_BASE_ADDRESS) 33.407 - && (load_store_address_x <= `CFG_DCACHE_LIMIT) 33.408 -`ifdef CFG_DRAM_ENABLED 33.409 - && (dram_select_x == `FALSE) 33.410 -`endif 33.411 -`ifdef CFG_IROM_ENABLED 33.412 - && (irom_select_x == `FALSE) 33.413 -`endif 33.414 - ; 33.415 -`endif 33.416 - 33.417 - assign wb_select_x = `TRUE 33.418 -`ifdef CFG_DCACHE_ENABLED 33.419 - && !dcache_select_x 33.420 -`endif 33.421 -`ifdef CFG_DRAM_ENABLED 33.422 - && !dram_select_x 33.423 -`endif 33.424 -`ifdef CFG_IROM_ENABLED 33.425 - && !irom_select_x 33.426 -`endif 33.427 - ; 33.428 - 33.429 -// Make sure data to store is in correct byte lane 33.430 -always @(*) 33.431 -begin 33.432 - case (size_x) 33.433 - `LM32_SIZE_BYTE: store_data_x = {4{store_operand_x[7:0]}}; 33.434 - `LM32_SIZE_HWORD: store_data_x = {2{store_operand_x[15:0]}}; 33.435 - `LM32_SIZE_WORD: store_data_x = store_operand_x; 33.436 - default: store_data_x = {`LM32_WORD_WIDTH{1'bx}}; 33.437 - endcase 33.438 -end 33.439 - 33.440 -// Generate byte enable accoring to size of load or store and address being accessed 33.441 -always @(*) 33.442 -begin 33.443 - casez ({size_x, load_store_address_x[1:0]}) 33.444 - {`LM32_SIZE_BYTE, 2'b11}: byte_enable_x = 4'b0001; 33.445 - {`LM32_SIZE_BYTE, 2'b10}: byte_enable_x = 4'b0010; 33.446 - {`LM32_SIZE_BYTE, 2'b01}: byte_enable_x = 4'b0100; 33.447 - {`LM32_SIZE_BYTE, 2'b00}: byte_enable_x = 4'b1000; 33.448 - {`LM32_SIZE_HWORD, 2'b1?}: byte_enable_x = 4'b0011; 33.449 - {`LM32_SIZE_HWORD, 2'b0?}: byte_enable_x = 4'b1100; 33.450 - {`LM32_SIZE_WORD, 2'b??}: byte_enable_x = 4'b1111; 33.451 - default: byte_enable_x = 4'bxxxx; 33.452 - endcase 33.453 -end 33.454 - 33.455 -`ifdef CFG_DRAM_ENABLED 33.456 -// Only replace selected bytes 33.457 -assign dram_store_data_m[`LM32_BYTE_0_RNG] = byte_enable_m[0] ? store_data_m[`LM32_BYTE_0_RNG] : dram_data_m[`LM32_BYTE_0_RNG]; 33.458 -assign dram_store_data_m[`LM32_BYTE_1_RNG] = byte_enable_m[1] ? store_data_m[`LM32_BYTE_1_RNG] : dram_data_m[`LM32_BYTE_1_RNG]; 33.459 -assign dram_store_data_m[`LM32_BYTE_2_RNG] = byte_enable_m[2] ? store_data_m[`LM32_BYTE_2_RNG] : dram_data_m[`LM32_BYTE_2_RNG]; 33.460 -assign dram_store_data_m[`LM32_BYTE_3_RNG] = byte_enable_m[3] ? store_data_m[`LM32_BYTE_3_RNG] : dram_data_m[`LM32_BYTE_3_RNG]; 33.461 -`endif 33.462 - 33.463 -`ifdef CFG_IROM_ENABLED 33.464 -// Only replace selected bytes 33.465 -assign irom_store_data_m[`LM32_BYTE_0_RNG] = byte_enable_m[0] ? store_data_m[`LM32_BYTE_0_RNG] : irom_data_m[`LM32_BYTE_0_RNG]; 33.466 -assign irom_store_data_m[`LM32_BYTE_1_RNG] = byte_enable_m[1] ? store_data_m[`LM32_BYTE_1_RNG] : irom_data_m[`LM32_BYTE_1_RNG]; 33.467 -assign irom_store_data_m[`LM32_BYTE_2_RNG] = byte_enable_m[2] ? store_data_m[`LM32_BYTE_2_RNG] : irom_data_m[`LM32_BYTE_2_RNG]; 33.468 -assign irom_store_data_m[`LM32_BYTE_3_RNG] = byte_enable_m[3] ? store_data_m[`LM32_BYTE_3_RNG] : irom_data_m[`LM32_BYTE_3_RNG]; 33.469 -`endif 33.470 - 33.471 -`ifdef CFG_IROM_ENABLED 33.472 - // Instead of implementing a byte-addressable instruction ROM (for store byte instruction), 33.473 - // a load-and-store architecture is used wherein a 32-bit value is loaded, the requisite 33.474 - // byte is replaced, and the whole 32-bit value is written back 33.475 - 33.476 - assign irom_address_xm = ((irom_select_m == `TRUE) && (store_q_m == `TRUE)) 33.477 - ? load_store_address_m 33.478 - : load_store_address_x; 33.479 - 33.480 - // All store instructions perform a write operation in the M stage 33.481 - assign irom_we_xm = (irom_select_m == `TRUE) 33.482 - && (store_q_m == `TRUE); 33.483 - 33.484 - // A single port in instruction ROM is available to load-store unit for doing loads/stores. 33.485 - // Since every store requires a load (in X stage) and then a store (in M stage), we cannot 33.486 - // allow load (or store) instructions sequentially after the store instructions to proceed 33.487 - // until the store instruction has vacated M stage (i.e., completed the store operation) 33.488 - assign irom_stall_request_x = (irom_select_x == `TRUE) 33.489 - && (store_q_x == `TRUE); 33.490 -`endif 33.491 - 33.492 -`ifdef CFG_DCACHE_ENABLED 33.493 - `ifdef CFG_DRAM_ENABLED 33.494 - `ifdef CFG_IROM_ENABLED 33.495 - // WB + DC + DRAM + IROM 33.496 - assign data_m = wb_select_m == `TRUE 33.497 - ? wb_data_m 33.498 - : dram_select_m == `TRUE 33.499 - ? dram_data_m 33.500 - : irom_select_m == `TRUE 33.501 - ? irom_data_m 33.502 - : dcache_data_m; 33.503 - `else 33.504 - // WB + DC + DRAM 33.505 - assign data_m = wb_select_m == `TRUE 33.506 - ? wb_data_m 33.507 - : dram_select_m == `TRUE 33.508 - ? dram_data_m 33.509 - : dcache_data_m; 33.510 - `endif 33.511 - `else 33.512 - `ifdef CFG_IROM_ENABLED 33.513 - // WB + DC + IROM 33.514 - assign data_m = wb_select_m == `TRUE 33.515 - ? wb_data_m 33.516 - : irom_select_m == `TRUE 33.517 - ? irom_data_m 33.518 - : dcache_data_m; 33.519 - `else 33.520 - // WB + DC 33.521 - assign data_m = wb_select_m == `TRUE 33.522 - ? wb_data_m 33.523 - : dcache_data_m; 33.524 - `endif 33.525 - `endif 33.526 -`else 33.527 - `ifdef CFG_DRAM_ENABLED 33.528 - `ifdef CFG_IROM_ENABLED 33.529 - // WB + DRAM + IROM 33.530 - assign data_m = wb_select_m == `TRUE 33.531 - ? wb_data_m 33.532 - : dram_select_m == `TRUE 33.533 - ? dram_data_m 33.534 - : irom_data_m; 33.535 - `else 33.536 - // WB + DRAM 33.537 - assign data_m = wb_select_m == `TRUE 33.538 - ? wb_data_m 33.539 - : dram_data_m; 33.540 - `endif 33.541 - `else 33.542 - `ifdef CFG_IROM_ENABLED 33.543 - // WB + IROM 33.544 - assign data_m = wb_select_m == `TRUE 33.545 - ? wb_data_m 33.546 - : irom_data_m; 33.547 - `else 33.548 - // WB 33.549 - assign data_m = wb_data_m; 33.550 - `endif 33.551 - `endif 33.552 -`endif 33.553 - 33.554 -// Sub-word selection and sign/zero-extension for loads 33.555 -always @(*) 33.556 -begin 33.557 - casez ({size_w, load_store_address_w[1:0]}) 33.558 - {`LM32_SIZE_BYTE, 2'b11}: load_data_w = {{24{sign_extend_w & data_w[7]}}, data_w[7:0]}; 33.559 - {`LM32_SIZE_BYTE, 2'b10}: load_data_w = {{24{sign_extend_w & data_w[15]}}, data_w[15:8]}; 33.560 - {`LM32_SIZE_BYTE, 2'b01}: load_data_w = {{24{sign_extend_w & data_w[23]}}, data_w[23:16]}; 33.561 - {`LM32_SIZE_BYTE, 2'b00}: load_data_w = {{24{sign_extend_w & data_w[31]}}, data_w[31:24]}; 33.562 - {`LM32_SIZE_HWORD, 2'b1?}: load_data_w = {{16{sign_extend_w & data_w[15]}}, data_w[15:0]}; 33.563 - {`LM32_SIZE_HWORD, 2'b0?}: load_data_w = {{16{sign_extend_w & data_w[31]}}, data_w[31:16]}; 33.564 - {`LM32_SIZE_WORD, 2'b??}: load_data_w = data_w; 33.565 - default: load_data_w = {`LM32_WORD_WIDTH{1'bx}}; 33.566 - endcase 33.567 -end 33.568 - 33.569 -// Unused/constant Wishbone signals 33.570 -assign d_bte_o = `LM32_BTYPE_LINEAR; 33.571 - 33.572 -`ifdef CFG_DCACHE_ENABLED 33.573 -// Generate signal to indicate last word in cache line 33.574 -generate 33.575 - case (bytes_per_line) 33.576 - 4: 33.577 - begin 33.578 -assign first_cycle_type = `LM32_CTYPE_END; 33.579 -assign next_cycle_type = `LM32_CTYPE_END; 33.580 -assign last_word = `TRUE; 33.581 -assign first_address = {dcache_refill_address[`LM32_WORD_WIDTH-1:2], 2'b00}; 33.582 - end 33.583 - 8: 33.584 - begin 33.585 -assign first_cycle_type = `LM32_CTYPE_INCREMENTING; 33.586 -assign next_cycle_type = `LM32_CTYPE_END; 33.587 -assign last_word = (&d_adr_o[addr_offset_msb:addr_offset_lsb]) == 1'b1; 33.588 -assign first_address = {dcache_refill_address[`LM32_WORD_WIDTH-1:addr_offset_msb+1], {addr_offset_width{1'b0}}, 2'b00}; 33.589 - end 33.590 - 16: 33.591 - begin 33.592 -assign first_cycle_type = `LM32_CTYPE_INCREMENTING; 33.593 -assign next_cycle_type = d_adr_o[addr_offset_msb] == 1'b1 ? `LM32_CTYPE_END : `LM32_CTYPE_INCREMENTING; 33.594 -assign last_word = (&d_adr_o[addr_offset_msb:addr_offset_lsb]) == 1'b1; 33.595 -assign first_address = {dcache_refill_address[`LM32_WORD_WIDTH-1:addr_offset_msb+1], {addr_offset_width{1'b0}}, 2'b00}; 33.596 - end 33.597 - endcase 33.598 -endgenerate 33.599 -`endif 33.600 - 33.601 -///////////////////////////////////////////////////// 33.602 -// Sequential Logic 33.603 -///////////////////////////////////////////////////// 33.604 - 33.605 -// Data Wishbone interface 33.606 -always @(posedge clk_i `CFG_RESET_SENSITIVITY) 33.607 -begin 33.608 - if (rst_i == `TRUE) 33.609 - begin 33.610 - d_cyc_o <= `FALSE; 33.611 - d_stb_o <= `FALSE; 33.612 - d_dat_o <= {`LM32_WORD_WIDTH{1'b0}}; 33.613 - d_adr_o <= {`LM32_WORD_WIDTH{1'b0}}; 33.614 - d_sel_o <= {`LM32_BYTE_SELECT_WIDTH{`FALSE}}; 33.615 - d_we_o <= `FALSE; 33.616 - d_cti_o <= `LM32_CTYPE_END; 33.617 - d_lock_o <= `FALSE; 33.618 - wb_data_m <= {`LM32_WORD_WIDTH{1'b0}}; 33.619 - wb_load_complete <= `FALSE; 33.620 - stall_wb_load <= `FALSE; 33.621 -`ifdef CFG_DCACHE_ENABLED 33.622 - dcache_refill_ready <= `FALSE; 33.623 -`endif 33.624 - end 33.625 - else 33.626 - begin 33.627 -`ifdef CFG_DCACHE_ENABLED 33.628 - // Refill ready should only be asserted for a single cycle 33.629 - dcache_refill_ready <= `FALSE; 33.630 -`endif 33.631 - // Is a Wishbone cycle already in progress? 33.632 - if (d_cyc_o == `TRUE) 33.633 - begin 33.634 - // Is the cycle complete? 33.635 - if ((d_ack_i == `TRUE) || (d_err_i == `TRUE)) 33.636 - begin 33.637 -`ifdef CFG_DCACHE_ENABLED 33.638 - if ((dcache_refilling == `TRUE) && (!last_word)) 33.639 - begin 33.640 - // Fetch next word of cache line 33.641 - d_adr_o[addr_offset_msb:addr_offset_lsb] <= d_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1; 33.642 - end 33.643 - else 33.644 -`endif 33.645 - begin 33.646 - // Refill/access complete 33.647 - d_cyc_o <= `FALSE; 33.648 - d_stb_o <= `FALSE; 33.649 - d_lock_o <= `FALSE; 33.650 - end 33.651 -`ifdef CFG_DCACHE_ENABLED 33.652 - d_cti_o <= next_cycle_type; 33.653 - // If we are performing a refill, indicate to cache next word of data is ready 33.654 - dcache_refill_ready <= dcache_refilling; 33.655 -`endif 33.656 - // Register data read from Wishbone interface 33.657 - wb_data_m <= d_dat_i; 33.658 - // Don't set when stores complete - otherwise we'll deadlock if load in m stage 33.659 - wb_load_complete <= !d_we_o; 33.660 - end 33.661 - // synthesis translate_off 33.662 - if (d_err_i == `TRUE) 33.663 - $display ("Data bus error. Address: %x", d_adr_o); 33.664 - // synthesis translate_on 33.665 - end 33.666 - else 33.667 - begin 33.668 -`ifdef CFG_DCACHE_ENABLED 33.669 - if (dcache_refill_request == `TRUE) 33.670 - begin 33.671 - // Start cache refill 33.672 - d_adr_o <= first_address; 33.673 - d_cyc_o <= `TRUE; 33.674 - d_sel_o <= {`LM32_WORD_WIDTH/8{`TRUE}}; 33.675 - d_stb_o <= `TRUE; 33.676 - d_we_o <= `FALSE; 33.677 - d_cti_o <= first_cycle_type; 33.678 - //d_lock_o <= `TRUE; 33.679 - end 33.680 - else 33.681 -`endif 33.682 - if ( (store_q_m == `TRUE) 33.683 - && (stall_m == `FALSE) 33.684 -`ifdef CFG_DRAM_ENABLED 33.685 - && (dram_select_m == `FALSE) 33.686 -`endif 33.687 -`ifdef CFG_IROM_ENABLED 33.688 - && (irom_select_m == `FALSE) 33.689 -`endif 33.690 - ) 33.691 - begin 33.692 - // Data cache is write through, so all stores go to memory 33.693 - d_dat_o <= store_data_m; 33.694 - d_adr_o <= load_store_address_m; 33.695 - d_cyc_o <= `TRUE; 33.696 - d_sel_o <= byte_enable_m; 33.697 - d_stb_o <= `TRUE; 33.698 - d_we_o <= `TRUE; 33.699 - d_cti_o <= `LM32_CTYPE_END; 33.700 - end 33.701 - else if ( (load_q_m == `TRUE) 33.702 - && (wb_select_m == `TRUE) 33.703 - && (wb_load_complete == `FALSE) 33.704 - // stall_m will be TRUE, because stall_wb_load will be TRUE 33.705 - ) 33.706 - begin 33.707 - // Read requested address 33.708 - stall_wb_load <= `FALSE; 33.709 - d_adr_o <= load_store_address_m; 33.710 - d_cyc_o <= `TRUE; 33.711 - d_sel_o <= byte_enable_m; 33.712 - d_stb_o <= `TRUE; 33.713 - d_we_o <= `FALSE; 33.714 - d_cti_o <= `LM32_CTYPE_END; 33.715 - end 33.716 - end 33.717 - // Clear load/store complete flag when instruction leaves M stage 33.718 - if (stall_m == `FALSE) 33.719 - wb_load_complete <= `FALSE; 33.720 - // When a Wishbone load first enters the M stage, we need to stall it 33.721 - if ((load_q_x == `TRUE) && (wb_select_x == `TRUE) && (stall_x == `FALSE)) 33.722 - stall_wb_load <= `TRUE; 33.723 - // Clear stall request if load instruction is killed 33.724 - if ((kill_m == `TRUE) || (exception_m == `TRUE)) 33.725 - stall_wb_load <= `FALSE; 33.726 - end 33.727 -end 33.728 - 33.729 -// Pipeline registers 33.730 - 33.731 -// X/M stage pipeline registers 33.732 -always @(posedge clk_i `CFG_RESET_SENSITIVITY) 33.733 -begin 33.734 - if (rst_i == `TRUE) 33.735 - begin 33.736 - sign_extend_m <= `FALSE; 33.737 - size_m <= 2'b00; 33.738 - byte_enable_m <= `FALSE; 33.739 - store_data_m <= {`LM32_WORD_WIDTH{1'b0}}; 33.740 -`ifdef CFG_DCACHE_ENABLED 33.741 - dcache_select_m <= `FALSE; 33.742 -`endif 33.743 -`ifdef CFG_DRAM_ENABLED 33.744 - dram_select_m <= `FALSE; 33.745 -`endif 33.746 -`ifdef CFG_IROM_ENABLED 33.747 - irom_select_m <= `FALSE; 33.748 -`endif 33.749 - wb_select_m <= `FALSE; 33.750 - end 33.751 - else 33.752 - begin 33.753 - if (stall_m == `FALSE) 33.754 - begin 33.755 - sign_extend_m <= sign_extend_x; 33.756 - size_m <= size_x; 33.757 - byte_enable_m <= byte_enable_x; 33.758 - store_data_m <= store_data_x; 33.759 -`ifdef CFG_DCACHE_ENABLED 33.760 - dcache_select_m <= dcache_select_x; 33.761 -`endif 33.762 -`ifdef CFG_DRAM_ENABLED 33.763 - dram_select_m <= dram_select_x; 33.764 -`endif 33.765 -`ifdef CFG_IROM_ENABLED 33.766 - irom_select_m <= irom_select_x; 33.767 -`endif 33.768 - wb_select_m <= wb_select_x; 33.769 - end 33.770 - end 33.771 -end 33.772 - 33.773 -// M/W stage pipeline registers 33.774 -always @(posedge clk_i `CFG_RESET_SENSITIVITY) 33.775 -begin 33.776 - if (rst_i == `TRUE) 33.777 - begin 33.778 - size_w <= 2'b00; 33.779 - data_w <= {`LM32_WORD_WIDTH{1'b0}}; 33.780 - sign_extend_w <= `FALSE; 33.781 - end 33.782 - else 33.783 - begin 33.784 - size_w <= size_m; 33.785 - data_w <= data_m; 33.786 - sign_extend_w <= sign_extend_m; 33.787 - end 33.788 -end 33.789 - 33.790 -///////////////////////////////////////////////////// 33.791 -// Behavioural Logic 33.792 -///////////////////////////////////////////////////// 33.793 - 33.794 -// synthesis translate_off 33.795 - 33.796 -// Check for non-aligned loads or stores 33.797 -always @(posedge clk_i) 33.798 -begin 33.799 - if (((load_q_m == `TRUE) || (store_q_m == `TRUE)) && (stall_m == `FALSE)) 33.800 - begin 33.801 - if ((size_m === `LM32_SIZE_HWORD) && (load_store_address_m[0] !== 1'b0)) 33.802 - $display ("Warning: Non-aligned halfword access. Address: 0x%0x Time: %0t.", load_store_address_m, $time); 33.803 - if ((size_m === `LM32_SIZE_WORD) && (load_store_address_m[1:0] !== 2'b00)) 33.804 - $display ("Warning: Non-aligned word access. Address: 0x%0x Time: %0t.", load_store_address_m, $time); 33.805 - end 33.806 -end 33.807 - 33.808 -// synthesis translate_on 33.809 - 33.810 -endmodule
34.1 diff -r 252df75c8f67 -r c336e674a37e lm32_logic_op.v 34.2 --- a/lm32_logic_op.v Sun Mar 06 21:17:31 2011 +0000 34.3 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 34.4 @@ -1,76 +0,0 @@ 34.5 -// ============================================================================= 34.6 -// COPYRIGHT NOTICE 34.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 34.8 -// ALL RIGHTS RESERVED 34.9 -// This confidential and proprietary software may be used only as authorised by 34.10 -// a licensing agreement from Lattice Semiconductor Corporation. 34.11 -// The entire notice above must be reproduced on all authorized copies and 34.12 -// copies may only be made to the extent permitted by a licensing agreement from 34.13 -// Lattice Semiconductor Corporation. 34.14 -// 34.15 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 34.16 -// 5555 NE Moore Court 408-826-6000 (other locations) 34.17 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 34.18 -// U.S.A email: techsupport@latticesemi.com 34.19 -// =============================================================================/ 34.20 -// FILE DETAILS 34.21 -// Project : LatticeMico32 34.22 -// File : lm32_logic_op.v 34.23 -// Title : Logic operations (and / or / not etc) 34.24 -// Dependencies : lm32_include.v 34.25 -// Version : 6.1.17 34.26 -// : Initial Release 34.27 -// Version : 7.0SP2, 3.0 34.28 -// : No Change 34.29 -// Version : 3.1 34.30 -// : No Change 34.31 -// ============================================================================= 34.32 - 34.33 -`include "lm32_include.v" 34.34 - 34.35 -///////////////////////////////////////////////////// 34.36 -// Module interface 34.37 -///////////////////////////////////////////////////// 34.38 - 34.39 -module lm32_logic_op ( 34.40 - // ----- Inputs ------- 34.41 - logic_op_x, 34.42 - operand_0_x, 34.43 - operand_1_x, 34.44 - // ----- Outputs ------- 34.45 - logic_result_x 34.46 - ); 34.47 - 34.48 -///////////////////////////////////////////////////// 34.49 -// Inputs 34.50 -///////////////////////////////////////////////////// 34.51 - 34.52 -input [`LM32_LOGIC_OP_RNG] logic_op_x; 34.53 -input [`LM32_WORD_RNG] operand_0_x; 34.54 -input [`LM32_WORD_RNG] operand_1_x; 34.55 - 34.56 -///////////////////////////////////////////////////// 34.57 -// Outputs 34.58 -///////////////////////////////////////////////////// 34.59 - 34.60 -output [`LM32_WORD_RNG] logic_result_x; 34.61 -reg [`LM32_WORD_RNG] logic_result_x; 34.62 - 34.63 -///////////////////////////////////////////////////// 34.64 -// Internal nets and registers 34.65 -///////////////////////////////////////////////////// 34.66 - 34.67 -integer logic_idx; 34.68 - 34.69 -///////////////////////////////////////////////////// 34.70 -// Combinational Logic 34.71 -///////////////////////////////////////////////////// 34.72 - 34.73 -always @(*) 34.74 -begin 34.75 - for(logic_idx = 0; logic_idx < `LM32_WORD_WIDTH; logic_idx = logic_idx + 1) 34.76 - logic_result_x[logic_idx] = logic_op_x[{operand_1_x[logic_idx], operand_0_x[logic_idx]}]; 34.77 -end 34.78 - 34.79 -endmodule 34.80 -
35.1 diff -r 252df75c8f67 -r c336e674a37e lm32_mc_arithmetic.v 35.2 --- a/lm32_mc_arithmetic.v Sun Mar 06 21:17:31 2011 +0000 35.3 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 35.4 @@ -1,288 +0,0 @@ 35.5 -// ============================================================================= 35.6 -// COPYRIGHT NOTICE 35.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 35.8 -// ALL RIGHTS RESERVED 35.9 -// This confidential and proprietary software may be used only as authorised by 35.10 -// a licensing agreement from Lattice Semiconductor Corporation. 35.11 -// The entire notice above must be reproduced on all authorized copies and 35.12 -// copies may only be made to the extent permitted by a licensing agreement from 35.13 -// Lattice Semiconductor Corporation. 35.14 -// 35.15 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 35.16 -// 5555 NE Moore Court 408-826-6000 (other locations) 35.17 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 35.18 -// U.S.A email: techsupport@latticesemi.com 35.19 -// =============================================================================/ 35.20 -// FILE DETAILS 35.21 -// Project : LatticeMico32 35.22 -// File : lm_mc_arithmetic.v 35.23 -// Title : Multi-cycle arithmetic unit. 35.24 -// Dependencies : lm32_include.v 35.25 -// Version : 6.1.17 35.26 -// : Initial Release 35.27 -// Version : 7.0SP2, 3.0 35.28 -// : No Change 35.29 -// Version : 3.1 35.30 -// : No Change 35.31 -// ============================================================================= 35.32 - 35.33 -`include "lm32_include.v" 35.34 - 35.35 -`define LM32_MC_STATE_RNG 2:0 35.36 -`define LM32_MC_STATE_IDLE 3'b000 35.37 -`define LM32_MC_STATE_MULTIPLY 3'b001 35.38 -`define LM32_MC_STATE_MODULUS 3'b010 35.39 -`define LM32_MC_STATE_DIVIDE 3'b011 35.40 -`define LM32_MC_STATE_SHIFT_LEFT 3'b100 35.41 -`define LM32_MC_STATE_SHIFT_RIGHT 3'b101 35.42 - 35.43 -///////////////////////////////////////////////////// 35.44 -// Module interface 35.45 -///////////////////////////////////////////////////// 35.46 - 35.47 -module lm32_mc_arithmetic ( 35.48 - // ----- Inputs ----- 35.49 - clk_i, 35.50 - rst_i, 35.51 - stall_d, 35.52 - kill_x, 35.53 -`ifdef CFG_MC_DIVIDE_ENABLED 35.54 - divide_d, 35.55 - modulus_d, 35.56 -`endif 35.57 -`ifdef CFG_MC_MULTIPLY_ENABLED 35.58 - multiply_d, 35.59 -`endif 35.60 -`ifdef CFG_MC_BARREL_SHIFT_ENABLED 35.61 - shift_left_d, 35.62 - shift_right_d, 35.63 - sign_extend_d, 35.64 -`endif 35.65 - operand_0_d, 35.66 - operand_1_d, 35.67 - // ----- Ouputs ----- 35.68 - result_x, 35.69 -`ifdef CFG_MC_DIVIDE_ENABLED 35.70 - divide_by_zero_x, 35.71 -`endif 35.72 - stall_request_x 35.73 - ); 35.74 - 35.75 -///////////////////////////////////////////////////// 35.76 -// Inputs 35.77 -///////////////////////////////////////////////////// 35.78 - 35.79 -input clk_i; // Clock 35.80 -input rst_i; // Reset 35.81 -input stall_d; // Stall instruction in D stage 35.82 -input kill_x; // Kill instruction in X stage 35.83 -`ifdef CFG_MC_DIVIDE_ENABLED 35.84 -input divide_d; // Perform divide 35.85 -input modulus_d; // Perform modulus 35.86 -`endif 35.87 -`ifdef CFG_MC_MULTIPLY_ENABLED 35.88 -input multiply_d; // Perform multiply 35.89 -`endif 35.90 -`ifdef CFG_MC_BARREL_SHIFT_ENABLED 35.91 -input shift_left_d; // Perform left shift 35.92 -input shift_right_d; // Perform right shift 35.93 -input sign_extend_d; // Whether to sign-extend (arithmetic) or zero-extend (logical) 35.94 -`endif 35.95 -input [`LM32_WORD_RNG] operand_0_d; 35.96 -input [`LM32_WORD_RNG] operand_1_d; 35.97 - 35.98 -///////////////////////////////////////////////////// 35.99 -// Outputs 35.100 -///////////////////////////////////////////////////// 35.101 - 35.102 -output [`LM32_WORD_RNG] result_x; // Result of operation 35.103 -reg [`LM32_WORD_RNG] result_x; 35.104 -`ifdef CFG_MC_DIVIDE_ENABLED 35.105 -output divide_by_zero_x; // A divide by zero was attempted 35.106 -reg divide_by_zero_x; 35.107 -`endif 35.108 -output stall_request_x; // Request to stall pipeline from X stage back 35.109 -wire stall_request_x; 35.110 - 35.111 -///////////////////////////////////////////////////// 35.112 -// Internal nets and registers 35.113 -///////////////////////////////////////////////////// 35.114 - 35.115 -reg [`LM32_WORD_RNG] p; // Temporary registers 35.116 -reg [`LM32_WORD_RNG] a; 35.117 -reg [`LM32_WORD_RNG] b; 35.118 -`ifdef CFG_MC_DIVIDE_ENABLED 35.119 -wire [32:0] t; 35.120 -`endif 35.121 - 35.122 -reg [`LM32_MC_STATE_RNG] state; // Current state of FSM 35.123 -reg [5:0] cycles; // Number of cycles remaining in the operation 35.124 - 35.125 -`ifdef CFG_MC_BARREL_SHIFT_ENABLED 35.126 -reg sign_extend_x; // Whether to sign extend of zero extend right shifts 35.127 -wire fill_value; // Value to fill with for right barrel-shifts 35.128 -`endif 35.129 - 35.130 -///////////////////////////////////////////////////// 35.131 -// Combinational logic 35.132 -///////////////////////////////////////////////////// 35.133 - 35.134 -// Stall pipeline while any operation is being performed 35.135 -assign stall_request_x = state != `LM32_MC_STATE_IDLE; 35.136 - 35.137 -`ifdef CFG_MC_DIVIDE_ENABLED 35.138 -// Subtraction 35.139 -assign t = {p[`LM32_WORD_WIDTH-2:0], a[`LM32_WORD_WIDTH-1]} - b; 35.140 -`endif 35.141 - 35.142 -`ifdef CFG_MC_BARREL_SHIFT_ENABLED 35.143 -// Determine fill value for right shift - Sign bit for arithmetic shift, or zero for logical shift 35.144 -assign fill_value = (sign_extend_x == `TRUE) & b[`LM32_WORD_WIDTH-1]; 35.145 -`endif 35.146 - 35.147 -///////////////////////////////////////////////////// 35.148 -// Sequential logic 35.149 -///////////////////////////////////////////////////// 35.150 - 35.151 -// Perform right shift 35.152 -always @(posedge clk_i `CFG_RESET_SENSITIVITY) 35.153 -begin 35.154 - if (rst_i == `TRUE) 35.155 - begin 35.156 - cycles <= {6{1'b0}}; 35.157 - p <= {`LM32_WORD_WIDTH{1'b0}}; 35.158 - a <= {`LM32_WORD_WIDTH{1'b0}}; 35.159 - b <= {`LM32_WORD_WIDTH{1'b0}}; 35.160 -`ifdef CFG_MC_BARREL_SHIFT_ENABLED 35.161 - sign_extend_x <= 1'b0; 35.162 -`endif 35.163 -`ifdef CFG_MC_DIVIDE_ENABLED 35.164 - divide_by_zero_x <= `FALSE; 35.165 -`endif 35.166 - result_x <= {`LM32_WORD_WIDTH{1'b0}}; 35.167 - state <= `LM32_MC_STATE_IDLE; 35.168 - end 35.169 - else 35.170 - begin 35.171 -`ifdef CFG_MC_DIVIDE_ENABLED 35.172 - divide_by_zero_x <= `FALSE; 35.173 -`endif 35.174 - case (state) 35.175 - `LM32_MC_STATE_IDLE: 35.176 - begin 35.177 - if (stall_d == `FALSE) 35.178 - begin 35.179 - cycles <= `LM32_WORD_WIDTH; 35.180 - p <= 32'b0; 35.181 - a <= operand_0_d; 35.182 - b <= operand_1_d; 35.183 -`ifdef CFG_MC_DIVIDE_ENABLED 35.184 - if (divide_d == `TRUE) 35.185 - state <= `LM32_MC_STATE_DIVIDE; 35.186 - if (modulus_d == `TRUE) 35.187 - state <= `LM32_MC_STATE_MODULUS; 35.188 -`endif 35.189 -`ifdef CFG_MC_MULTIPLY_ENABLED 35.190 - if (multiply_d == `TRUE) 35.191 - state <= `LM32_MC_STATE_MULTIPLY; 35.192 -`endif 35.193 -`ifdef CFG_MC_BARREL_SHIFT_ENABLED 35.194 - if (shift_left_d == `TRUE) 35.195 - begin 35.196 - state <= `LM32_MC_STATE_SHIFT_LEFT; 35.197 - sign_extend_x <= sign_extend_d; 35.198 - cycles <= operand_1_d[4:0]; 35.199 - a <= operand_0_d; 35.200 - b <= operand_0_d; 35.201 - end 35.202 - if (shift_right_d == `TRUE) 35.203 - begin 35.204 - state <= `LM32_MC_STATE_SHIFT_RIGHT; 35.205 - sign_extend_x <= sign_extend_d; 35.206 - cycles <= operand_1_d[4:0]; 35.207 - a <= operand_0_d; 35.208 - b <= operand_0_d; 35.209 - end 35.210 -`endif 35.211 - end 35.212 - end 35.213 -`ifdef CFG_MC_DIVIDE_ENABLED 35.214 - `LM32_MC_STATE_DIVIDE: 35.215 - begin 35.216 - if (t[32] == 1'b0) 35.217 - begin 35.218 - p <= t[31:0]; 35.219 - a <= {a[`LM32_WORD_WIDTH-2:0], 1'b1}; 35.220 - end 35.221 - else 35.222 - begin 35.223 - p <= {p[`LM32_WORD_WIDTH-2:0], a[`LM32_WORD_WIDTH-1]}; 35.224 - a <= {a[`LM32_WORD_WIDTH-2:0], 1'b0}; 35.225 - end 35.226 - result_x <= a; 35.227 - if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE)) 35.228 - begin 35.229 - // Check for divide by zero 35.230 - divide_by_zero_x <= b == {`LM32_WORD_WIDTH{1'b0}}; 35.231 - state <= `LM32_MC_STATE_IDLE; 35.232 - end 35.233 - cycles <= cycles - 1'b1; 35.234 - end 35.235 - `LM32_MC_STATE_MODULUS: 35.236 - begin 35.237 - if (t[32] == 1'b0) 35.238 - begin 35.239 - p <= t[31:0]; 35.240 - a <= {a[`LM32_WORD_WIDTH-2:0], 1'b1}; 35.241 - end 35.242 - else 35.243 - begin 35.244 - p <= {p[`LM32_WORD_WIDTH-2:0], a[`LM32_WORD_WIDTH-1]}; 35.245 - a <= {a[`LM32_WORD_WIDTH-2:0], 1'b0}; 35.246 - end 35.247 - result_x <= p; 35.248 - if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE)) 35.249 - begin 35.250 - // Check for divide by zero 35.251 - divide_by_zero_x <= b == {`LM32_WORD_WIDTH{1'b0}}; 35.252 - state <= `LM32_MC_STATE_IDLE; 35.253 - end 35.254 - cycles <= cycles - 1'b1; 35.255 - end 35.256 -`endif 35.257 -`ifdef CFG_MC_MULTIPLY_ENABLED 35.258 - `LM32_MC_STATE_MULTIPLY: 35.259 - begin 35.260 - if (b[0] == 1'b1) 35.261 - p <= p + a; 35.262 - b <= {1'b0, b[`LM32_WORD_WIDTH-1:1]}; 35.263 - a <= {a[`LM32_WORD_WIDTH-2:0], 1'b0}; 35.264 - result_x <= p; 35.265 - if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE)) 35.266 - state <= `LM32_MC_STATE_IDLE; 35.267 - cycles <= cycles - 1'b1; 35.268 - end 35.269 -`endif 35.270 -`ifdef CFG_MC_BARREL_SHIFT_ENABLED 35.271 - `LM32_MC_STATE_SHIFT_LEFT: 35.272 - begin 35.273 - a <= {a[`LM32_WORD_WIDTH-2:0], 1'b0}; 35.274 - result_x <= a; 35.275 - if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE)) 35.276 - state <= `LM32_MC_STATE_IDLE; 35.277 - cycles <= cycles - 1'b1; 35.278 - end 35.279 - `LM32_MC_STATE_SHIFT_RIGHT: 35.280 - begin 35.281 - b <= {fill_value, b[`LM32_WORD_WIDTH-1:1]}; 35.282 - result_x <= b; 35.283 - if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE)) 35.284 - state <= `LM32_MC_STATE_IDLE; 35.285 - cycles <= cycles - 1'b1; 35.286 - end 35.287 -`endif 35.288 - endcase 35.289 - end 35.290 -end 35.291 - 35.292 -endmodule
36.1 diff -r 252df75c8f67 -r c336e674a37e lm32_multiplier.v 36.2 --- a/lm32_multiplier.v Sun Mar 06 21:17:31 2011 +0000 36.3 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 36.4 @@ -1,99 +0,0 @@ 36.5 -// ============================================================================= 36.6 -// COPYRIGHT NOTICE 36.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 36.8 -// ALL RIGHTS RESERVED 36.9 -// This confidential and proprietary software may be used only as authorised by 36.10 -// a licensing agreement from Lattice Semiconductor Corporation. 36.11 -// The entire notice above must be reproduced on all authorized copies and 36.12 -// copies may only be made to the extent permitted by a licensing agreement from 36.13 -// Lattice Semiconductor Corporation. 36.14 -// 36.15 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 36.16 -// 5555 NE Moore Court 408-826-6000 (other locations) 36.17 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 36.18 -// U.S.A email: techsupport@latticesemi.com 36.19 -// =============================================================================/ 36.20 -// FILE DETAILS 36.21 -// Project : LatticeMico32 36.22 -// File : lm32_multiplier.v 36.23 -// Title : Pipelined multiplier. 36.24 -// Dependencies : lm32_include.v 36.25 -// Version : 6.1.17 36.26 -// : Initial Release 36.27 -// Version : 7.0SP2, 3.0 36.28 -// : No Change 36.29 -// Version : 3.1 36.30 -// : No Change 36.31 -// ============================================================================= 36.32 - 36.33 -`include "lm32_include.v" 36.34 - 36.35 -///////////////////////////////////////////////////// 36.36 -// Module interface 36.37 -///////////////////////////////////////////////////// 36.38 - 36.39 -module lm32_multiplier ( 36.40 - // ----- Inputs ----- 36.41 - clk_i, 36.42 - rst_i, 36.43 - stall_x, 36.44 - stall_m, 36.45 - operand_0, 36.46 - operand_1, 36.47 - // ----- Ouputs ----- 36.48 - result 36.49 - ); 36.50 - 36.51 -///////////////////////////////////////////////////// 36.52 -// Inputs 36.53 -///////////////////////////////////////////////////// 36.54 - 36.55 -input clk_i; // Clock 36.56 -input rst_i; // Reset 36.57 -input stall_x; // Stall instruction in X stage 36.58 -input stall_m; // Stall instruction in M stage 36.59 -input [`LM32_WORD_RNG] operand_0; // Muliplicand 36.60 -input [`LM32_WORD_RNG] operand_1; // Multiplier 36.61 - 36.62 -///////////////////////////////////////////////////// 36.63 -// Outputs 36.64 -///////////////////////////////////////////////////// 36.65 - 36.66 -output [`LM32_WORD_RNG] result; // Product of multiplication 36.67 -reg [`LM32_WORD_RNG] result; 36.68 - 36.69 -///////////////////////////////////////////////////// 36.70 -// Internal nets and registers 36.71 -///////////////////////////////////////////////////// 36.72 - 36.73 -reg [`LM32_WORD_RNG] muliplicand; 36.74 -reg [`LM32_WORD_RNG] multiplier; 36.75 -reg [`LM32_WORD_RNG] product; 36.76 - 36.77 -///////////////////////////////////////////////////// 36.78 -// Sequential logic 36.79 -///////////////////////////////////////////////////// 36.80 - 36.81 -always @(posedge clk_i `CFG_RESET_SENSITIVITY) 36.82 -begin 36.83 - if (rst_i == `TRUE) 36.84 - begin 36.85 - muliplicand <= {`LM32_WORD_WIDTH{1'b0}}; 36.86 - multiplier <= {`LM32_WORD_WIDTH{1'b0}}; 36.87 - product <= {`LM32_WORD_WIDTH{1'b0}}; 36.88 - result <= {`LM32_WORD_WIDTH{1'b0}}; 36.89 - end 36.90 - else 36.91 - begin 36.92 - if (stall_x == `FALSE) 36.93 - begin 36.94 - muliplicand <= operand_0; 36.95 - multiplier <= operand_1; 36.96 - end 36.97 - if (stall_m == `FALSE) 36.98 - product <= muliplicand * multiplier; 36.99 - result <= product; 36.100 - end 36.101 -end 36.102 - 36.103 -endmodule
37.1 diff -r 252df75c8f67 -r c336e674a37e lm32_ram.v 37.2 --- a/lm32_ram.v Sun Mar 06 21:17:31 2011 +0000 37.3 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 37.4 @@ -1,294 +0,0 @@ 37.5 -// ============================================================================= 37.6 -// COPYRIGHT NOTICE 37.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 37.8 -// ALL RIGHTS RESERVED 37.9 -// This confidential and proprietary software may be used only as authorised by 37.10 -// a licensing agreement from Lattice Semiconductor Corporation. 37.11 -// The entire notice above must be reproduced on all authorized copies and 37.12 -// copies may only be made to the extent permitted by a licensing agreement from 37.13 -// Lattice Semiconductor Corporation. 37.14 -// 37.15 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 37.16 -// 5555 NE Moore Court 408-826-6000 (other locations) 37.17 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 37.18 -// U.S.A email: techsupport@latticesemi.com 37.19 -// =============================================================================/ 37.20 -// FILE DETAILS 37.21 -// Project : LatticeMico32 37.22 -// File : lm32_ram.v 37.23 -// Title : Pseudo dual-port RAM. 37.24 -// Version : 6.1.17 37.25 -// : Initial Release 37.26 -// Version : 7.0SP2, 3.0 37.27 -// : No Change 37.28 -// Version : 3.1 37.29 -// : Options added to select EBRs (True-DP, Psuedo-DP, DQ, or 37.30 -// : Distributed RAM). 37.31 -// Version : 3.2 37.32 -// : EBRs use SYNC resets instead of ASYNC resets. 37.33 -// Version : 3.5 37.34 -// : Added read-after-write hazard resolution when using true 37.35 -// : dual-port EBRs 37.36 -// ============================================================================= 37.37 - 37.38 -`include "lm32_include.v" 37.39 - 37.40 -///////////////////////////////////////////////////// 37.41 -// Module interface 37.42 -///////////////////////////////////////////////////// 37.43 - 37.44 -module lm32_ram 37.45 - ( 37.46 - // ----- Inputs ------- 37.47 - read_clk, 37.48 - write_clk, 37.49 - reset, 37.50 - enable_read, 37.51 - read_address, 37.52 - enable_write, 37.53 - write_address, 37.54 - write_data, 37.55 - write_enable, 37.56 - // ----- Outputs ------- 37.57 - read_data 37.58 - ); 37.59 - 37.60 - /*---------------------------------------------------------------------- 37.61 - Parameters 37.62 - ----------------------------------------------------------------------*/ 37.63 - parameter data_width = 1; // Width of the data ports 37.64 - parameter address_width = 1; // Width of the address ports 37.65 -`ifdef PLATFORM_LATTICE 37.66 - parameter RAM_IMPLEMENTATION = "AUTO"; // Implement memory in EBRs, else 37.67 - // let synthesis tool select best 37.68 - // possible solution (EBR or LUT) 37.69 - parameter RAM_TYPE = "RAM_DP"; // Type of EBR to be used 37.70 -`endif 37.71 - 37.72 - /*---------------------------------------------------------------------- 37.73 - Inputs 37.74 - ----------------------------------------------------------------------*/ 37.75 - input read_clk; // Read clock 37.76 - input write_clk; // Write clock 37.77 - input reset; // Reset 37.78 - 37.79 - input enable_read; // Access enable 37.80 - input [address_width-1:0] read_address; // Read/write address 37.81 - input enable_write; // Access enable 37.82 - input [address_width-1:0] write_address;// Read/write address 37.83 - input [data_width-1:0] write_data; // Data to write to specified address 37.84 - input write_enable; // Write enable 37.85 - 37.86 - /*---------------------------------------------------------------------- 37.87 - Outputs 37.88 - ----------------------------------------------------------------------*/ 37.89 - output [data_width-1:0] read_data; // Data read from specified addess 37.90 - wire [data_width-1:0] read_data; 37.91 - 37.92 -`ifdef PLATFORM_LATTICE 37.93 - generate 37.94 - 37.95 - if ( RAM_IMPLEMENTATION == "EBR" ) 37.96 - begin 37.97 - if ( RAM_TYPE == "RAM_DP" ) 37.98 - begin 37.99 - pmi_ram_dp 37.100 - #( 37.101 - // ----- Parameters ----- 37.102 - .pmi_wr_addr_depth(1<<address_width), 37.103 - .pmi_wr_addr_width(address_width), 37.104 - .pmi_wr_data_width(data_width), 37.105 - .pmi_rd_addr_depth(1<<address_width), 37.106 - .pmi_rd_addr_width(address_width), 37.107 - .pmi_rd_data_width(data_width), 37.108 - .pmi_regmode("noreg"), 37.109 - .pmi_gsr("enable"), 37.110 - .pmi_resetmode("sync"), 37.111 - .pmi_init_file("none"), 37.112 - .pmi_init_file_format("binary"), 37.113 - .pmi_family(`LATTICE_FAMILY), 37.114 - .module_type("pmi_ram_dp") 37.115 - ) 37.116 - lm32_ram_inst 37.117 - ( 37.118 - // ----- Inputs ----- 37.119 - .Data(write_data), 37.120 - .WrAddress(write_address), 37.121 - .RdAddress(read_address), 37.122 - .WrClock(write_clk), 37.123 - .RdClock(read_clk), 37.124 - .WrClockEn(enable_write), 37.125 - .RdClockEn(enable_read), 37.126 - .WE(write_enable), 37.127 - .Reset(reset), 37.128 - // ----- Outputs ----- 37.129 - .Q(read_data) 37.130 - ); 37.131 - end 37.132 - else 37.133 - begin 37.134 - // True Dual-Port EBR 37.135 - wire [data_width-1:0] read_data_A, read_data_B; 37.136 - reg [data_width-1:0] raw_data, raw_data_nxt; 37.137 - reg raw, raw_nxt; 37.138 - 37.139 - /*---------------------------------------------------------------------- 37.140 - Is a read being performed in the same cycle as a write? Indicate this 37.141 - event with a RAW hazard signal that is released only when a new read 37.142 - or write occurs later. 37.143 - ----------------------------------------------------------------------*/ 37.144 - always @(/*AUTOSENSE*/enable_read or enable_write 37.145 - or raw or raw_data or read_address 37.146 - or write_address or write_data 37.147 - or write_enable) 37.148 - if (// Read 37.149 - enable_read 37.150 - // Write 37.151 - && enable_write && write_enable 37.152 - // Read and write address match 37.153 - && (read_address == write_address)) 37.154 - begin 37.155 - raw_data_nxt = write_data; 37.156 - raw_nxt = 1'b1; 37.157 - end 37.158 - else 37.159 - if (raw && (enable_read == 1'b0) && (enable_write == 1'b0)) 37.160 - begin 37.161 - raw_data_nxt = raw_data; 37.162 - raw_nxt = 1'b1; 37.163 - end 37.164 - else 37.165 - begin 37.166 - raw_data_nxt = raw_data; 37.167 - raw_nxt = 1'b0; 37.168 - end 37.169 - 37.170 - // Send back write data in case of a RAW hazard; else send back 37.171 - // data from memory 37.172 - assign read_data = raw ? raw_data : read_data_B; 37.173 - 37.174 - /*---------------------------------------------------------------------- 37.175 - Sequential Logic 37.176 - ----------------------------------------------------------------------*/ 37.177 - always @(posedge read_clk) 37.178 - if (reset) 37.179 - begin 37.180 - raw_data <= #1 0; 37.181 - raw <= #1 1'b0; 37.182 - end 37.183 - else 37.184 - begin 37.185 - raw_data <= #1 raw_data_nxt; 37.186 - raw <= #1 raw_nxt; 37.187 - end 37.188 - 37.189 - pmi_ram_dp_true 37.190 - #( 37.191 - // ----- Parameters ----- 37.192 - .pmi_addr_depth_a(1<<address_width), 37.193 - .pmi_addr_width_a(address_width), 37.194 - .pmi_data_width_a(data_width), 37.195 - .pmi_addr_depth_b(1<<address_width), 37.196 - .pmi_addr_width_b(address_width), 37.197 - .pmi_data_width_b(data_width), 37.198 - .pmi_regmode_a("noreg"), 37.199 - .pmi_regmode_b("noreg"), 37.200 - .pmi_gsr("enable"), 37.201 - .pmi_resetmode("sync"), 37.202 - .pmi_init_file("none"), 37.203 - .pmi_init_file_format("binary"), 37.204 - .pmi_family(`LATTICE_FAMILY), 37.205 - .module_type("pmi_ram_dp_true") 37.206 - ) 37.207 - lm32_ram_inst 37.208 - ( 37.209 - // ----- Inputs ----- 37.210 - .DataInA(write_data), 37.211 - .DataInB(write_data), 37.212 - .AddressA(write_address), 37.213 - .AddressB(read_address), 37.214 - .ClockA(write_clk), 37.215 - .ClockB(read_clk), 37.216 - .ClockEnA(enable_write), 37.217 - .ClockEnB(enable_read), 37.218 - .WrA(write_enable), 37.219 - .WrB(`FALSE), 37.220 - .ResetA(reset), 37.221 - .ResetB(reset), 37.222 - // ----- Outputs ----- 37.223 - .QA(read_data_A), 37.224 - .QB(read_data_B) 37.225 - ); 37.226 - end 37.227 - end 37.228 - else if ( RAM_IMPLEMENTATION == "SLICE" ) 37.229 - begin 37.230 - reg [address_width-1:0] ra; // Registered read address 37.231 - 37.232 - pmi_distributed_dpram 37.233 - #( 37.234 - // ----- Parameters ----- 37.235 - .pmi_addr_depth(1<<address_width), 37.236 - .pmi_addr_width(address_width), 37.237 - .pmi_data_width(data_width), 37.238 - .pmi_regmode("noreg"), 37.239 - .pmi_init_file("none"), 37.240 - .pmi_init_file_format("binary"), 37.241 - .pmi_family(`LATTICE_FAMILY), 37.242 - .module_type("pmi_distributed_dpram") 37.243 - ) 37.244 - pmi_distributed_dpram_inst 37.245 - ( 37.246 - // ----- Inputs ----- 37.247 - .WrAddress(write_address), 37.248 - .Data(write_data), 37.249 - .WrClock(write_clk), 37.250 - .WE(write_enable), 37.251 - .WrClockEn(enable_write), 37.252 - .RdAddress(ra), 37.253 - .RdClock(read_clk), 37.254 - .RdClockEn(enable_read), 37.255 - .Reset(reset), 37.256 - // ----- Outputs ----- 37.257 - .Q(read_data) 37.258 - ); 37.259 - 37.260 - always @(posedge read_clk) 37.261 - if (enable_read) 37.262 - ra <= read_address; 37.263 - end 37.264 - 37.265 - else 37.266 - begin 37.267 -`endif 37.268 - /*---------------------------------------------------------------------- 37.269 - Internal nets and registers 37.270 - ----------------------------------------------------------------------*/ 37.271 - reg [data_width-1:0] mem[0:(1<<address_width)-1]; // The RAM 37.272 - reg [address_width-1:0] ra; // Registered read address 37.273 - 37.274 - /*---------------------------------------------------------------------- 37.275 - Combinational Logic 37.276 - ----------------------------------------------------------------------*/ 37.277 - // Read port 37.278 - assign read_data = mem[ra]; 37.279 - 37.280 - /*---------------------------------------------------------------------- 37.281 - Sequential Logic 37.282 - ----------------------------------------------------------------------*/ 37.283 - // Write port 37.284 - always @(posedge write_clk) 37.285 - if ((write_enable == `TRUE) && (enable_write == `TRUE)) 37.286 - mem[write_address] <= write_data; 37.287 - 37.288 - // Register read address for use on next cycle 37.289 - always @(posedge read_clk) 37.290 - if (enable_read) 37.291 - ra <= read_address; 37.292 - 37.293 -`ifdef PLATFORM_LATTICE 37.294 - end 37.295 - 37.296 - endgenerate 37.297 -`endif 37.298 -endmodule
38.1 diff -r 252df75c8f67 -r c336e674a37e lm32_shifter.v 38.2 --- a/lm32_shifter.v Sun Mar 06 21:17:31 2011 +0000 38.3 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 38.4 @@ -1,134 +0,0 @@ 38.5 -// ============================================================================= 38.6 -// COPYRIGHT NOTICE 38.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 38.8 -// ALL RIGHTS RESERVED 38.9 -// This confidential and proprietary software may be used only as authorised by 38.10 -// a licensing agreement from Lattice Semiconductor Corporation. 38.11 -// The entire notice above must be reproduced on all authorized copies and 38.12 -// copies may only be made to the extent permitted by a licensing agreement from 38.13 -// Lattice Semiconductor Corporation. 38.14 -// 38.15 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 38.16 -// 5555 NE Moore Court 408-826-6000 (other locations) 38.17 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 38.18 -// U.S.A email: techsupport@latticesemi.com 38.19 -// =============================================================================/ 38.20 -// FILE DETAILS 38.21 -// Project : LatticeMico32 38.22 -// File : lm32_shifter.v 38.23 -// Title : Barrel shifter 38.24 -// Dependencies : lm32_include.v 38.25 -// Version : 6.1.17 38.26 -// : Initial Release 38.27 -// Version : 7.0SP2, 3.0 38.28 -// : No Change 38.29 -// Version : 3.1 38.30 -// : No Change 38.31 -// ============================================================================= 38.32 - 38.33 -`include "lm32_include.v" 38.34 - 38.35 -///////////////////////////////////////////////////// 38.36 -// Module interface 38.37 -///////////////////////////////////////////////////// 38.38 - 38.39 -module lm32_shifter ( 38.40 - // ----- Inputs ------- 38.41 - clk_i, 38.42 - rst_i, 38.43 - stall_x, 38.44 - direction_x, 38.45 - sign_extend_x, 38.46 - operand_0_x, 38.47 - operand_1_x, 38.48 - // ----- Outputs ------- 38.49 - shifter_result_m 38.50 - ); 38.51 - 38.52 -///////////////////////////////////////////////////// 38.53 -// Inputs 38.54 -///////////////////////////////////////////////////// 38.55 - 38.56 -input clk_i; // Clock 38.57 -input rst_i; // Reset 38.58 -input stall_x; // Stall instruction in X stage 38.59 -input direction_x; // Direction to shift 38.60 -input sign_extend_x; // Whether shift is arithmetic (1'b1) or logical (1'b0) 38.61 -input [`LM32_WORD_RNG] operand_0_x; // Operand to shift 38.62 -input [`LM32_WORD_RNG] operand_1_x; // Operand that specifies how many bits to shift by 38.63 - 38.64 -///////////////////////////////////////////////////// 38.65 -// Outputs 38.66 -///////////////////////////////////////////////////// 38.67 - 38.68 -output [`LM32_WORD_RNG] shifter_result_m; // Result of shift 38.69 -wire [`LM32_WORD_RNG] shifter_result_m; 38.70 - 38.71 -///////////////////////////////////////////////////// 38.72 -// Internal nets and registers 38.73 -///////////////////////////////////////////////////// 38.74 - 38.75 -reg direction_m; 38.76 -reg [`LM32_WORD_RNG] left_shift_result; 38.77 -reg [`LM32_WORD_RNG] right_shift_result; 38.78 -reg [`LM32_WORD_RNG] left_shift_operand; 38.79 -wire [`LM32_WORD_RNG] right_shift_operand; 38.80 -wire fill_value; 38.81 -wire [`LM32_WORD_RNG] right_shift_in; 38.82 - 38.83 -integer shift_idx_0; 38.84 -integer shift_idx_1; 38.85 - 38.86 -///////////////////////////////////////////////////// 38.87 -// Combinational Logic 38.88 -///////////////////////////////////////////////////// 38.89 - 38.90 -// Select operands - To perform a left shift, we reverse the bits and perform a right shift 38.91 -always @(*) 38.92 -begin 38.93 - for (shift_idx_0 = 0; shift_idx_0 < `LM32_WORD_WIDTH; shift_idx_0 = shift_idx_0 + 1) 38.94 - left_shift_operand[`LM32_WORD_WIDTH-1-shift_idx_0] = operand_0_x[shift_idx_0]; 38.95 -end 38.96 -assign right_shift_operand = direction_x == `LM32_SHIFT_OP_LEFT ? left_shift_operand : operand_0_x; 38.97 - 38.98 -// Determine fill value for right shift - Sign bit for arithmetic shift, or zero for logical shift 38.99 -assign fill_value = (sign_extend_x == `TRUE) && (direction_x == `LM32_SHIFT_OP_RIGHT) 38.100 - ? operand_0_x[`LM32_WORD_WIDTH-1] 38.101 - : 1'b0; 38.102 - 38.103 -// Determine bits to shift in for right shift or rotate 38.104 -assign right_shift_in = {`LM32_WORD_WIDTH{fill_value}}; 38.105 - 38.106 -// Reverse bits to get left shift result 38.107 -always @(*) 38.108 -begin 38.109 - for (shift_idx_1 = 0; shift_idx_1 < `LM32_WORD_WIDTH; shift_idx_1 = shift_idx_1 + 1) 38.110 - left_shift_result[`LM32_WORD_WIDTH-1-shift_idx_1] = right_shift_result[shift_idx_1]; 38.111 -end 38.112 - 38.113 -// Select result 38.114 -assign shifter_result_m = direction_m == `LM32_SHIFT_OP_LEFT ? left_shift_result : right_shift_result; 38.115 - 38.116 -///////////////////////////////////////////////////// 38.117 -// Sequential Logic 38.118 -///////////////////////////////////////////////////// 38.119 - 38.120 -// Perform right shift 38.121 -always @(posedge clk_i `CFG_RESET_SENSITIVITY) 38.122 -begin 38.123 - if (rst_i == `TRUE) 38.124 - begin 38.125 - right_shift_result <= {`LM32_WORD_WIDTH{1'b0}}; 38.126 - direction_m <= `FALSE; 38.127 - end 38.128 - else 38.129 - begin 38.130 - if (stall_x == `FALSE) 38.131 - begin 38.132 - right_shift_result <= {right_shift_in, right_shift_operand} >> operand_1_x[`LM32_SHIFT_RNG]; 38.133 - direction_m <= direction_x; 38.134 - end 38.135 - end 38.136 -end 38.137 - 38.138 -endmodule
39.1 diff -r 252df75c8f67 -r c336e674a37e lm32_top.v 39.2 --- a/lm32_top.v Sun Mar 06 21:17:31 2011 +0000 39.3 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 39.4 @@ -1,355 +0,0 @@ 39.5 -// ============================================================================= 39.6 -// COPYRIGHT NOTICE 39.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 39.8 -// ALL RIGHTS RESERVED 39.9 -// This confidential and proprietary software may be used only as authorised by 39.10 -// a licensing agreement from Lattice Semiconductor Corporation. 39.11 -// The entire notice above must be reproduced on all authorized copies and 39.12 -// copies may only be made to the extent permitted by a licensing agreement from 39.13 -// Lattice Semiconductor Corporation. 39.14 -// 39.15 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 39.16 -// 5555 NE Moore Court 408-826-6000 (other locations) 39.17 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 39.18 -// U.S.A email: techsupport@latticesemi.com 39.19 -// =============================================================================/ 39.20 -// FILE DETAILS 39.21 -// Project : LatticeMico32 39.22 -// File : lm32_top.v 39.23 -// Title : Top-level of CPU. 39.24 -// Dependencies : lm32_include.v 39.25 -// Version : 6.1.17 39.26 -// : removed SPI - 04/12/07 39.27 -// Version : 7.0SP2, 3.0 39.28 -// : No Change 39.29 -// Version : 3.1 39.30 -// : No Change 39.31 -// ============================================================================= 39.32 - 39.33 -`include "lm32_include.v" 39.34 - 39.35 -///////////////////////////////////////////////////// 39.36 -// Module interface 39.37 -///////////////////////////////////////////////////// 39.38 - 39.39 -module lm32_top ( 39.40 - // ----- Inputs ------- 39.41 - clk_i, 39.42 - rst_i, 39.43 - // From external devices 39.44 -`ifdef CFG_INTERRUPTS_ENABLED 39.45 - interrupt, 39.46 -`endif 39.47 - // From user logic 39.48 -`ifdef CFG_USER_ENABLED 39.49 - user_result, 39.50 - user_complete, 39.51 -`endif 39.52 -`ifdef CFG_IWB_ENABLED 39.53 - // Instruction Wishbone master 39.54 - I_DAT_I, 39.55 - I_ACK_I, 39.56 - I_ERR_I, 39.57 - I_RTY_I, 39.58 -`endif 39.59 - // Data Wishbone master 39.60 - D_DAT_I, 39.61 - D_ACK_I, 39.62 - D_ERR_I, 39.63 - D_RTY_I, 39.64 - // ----- Outputs ------- 39.65 -`ifdef CFG_USER_ENABLED 39.66 - user_valid, 39.67 - user_opcode, 39.68 - user_operand_0, 39.69 - user_operand_1, 39.70 -`endif 39.71 -`ifdef CFG_IWB_ENABLED 39.72 - // Instruction Wishbone master 39.73 - I_DAT_O, 39.74 - I_ADR_O, 39.75 - I_CYC_O, 39.76 - I_SEL_O, 39.77 - I_STB_O, 39.78 - I_WE_O, 39.79 - I_CTI_O, 39.80 - I_LOCK_O, 39.81 - I_BTE_O, 39.82 -`endif 39.83 - // Data Wishbone master 39.84 - D_DAT_O, 39.85 - D_ADR_O, 39.86 - D_CYC_O, 39.87 - D_SEL_O, 39.88 - D_STB_O, 39.89 - D_WE_O, 39.90 - D_CTI_O, 39.91 - D_LOCK_O, 39.92 - D_BTE_O 39.93 - ); 39.94 - 39.95 -///////////////////////////////////////////////////// 39.96 -// Inputs 39.97 -///////////////////////////////////////////////////// 39.98 - 39.99 -input clk_i; // Clock 39.100 -input rst_i; // Reset 39.101 - 39.102 -`ifdef CFG_INTERRUPTS_ENABLED 39.103 -input [`LM32_INTERRUPT_RNG] interrupt; // Interrupt pins 39.104 -`endif 39.105 - 39.106 -`ifdef CFG_USER_ENABLED 39.107 -input [`LM32_WORD_RNG] user_result; // User-defined instruction result 39.108 -input user_complete; // Indicates the user-defined instruction result is valid 39.109 -`endif 39.110 - 39.111 -`ifdef CFG_IWB_ENABLED 39.112 -input [`LM32_WORD_RNG] I_DAT_I; // Instruction Wishbone interface read data 39.113 -input I_ACK_I; // Instruction Wishbone interface acknowledgement 39.114 -input I_ERR_I; // Instruction Wishbone interface error 39.115 -input I_RTY_I; // Instruction Wishbone interface retry 39.116 -`endif 39.117 - 39.118 -input [`LM32_WORD_RNG] D_DAT_I; // Data Wishbone interface read data 39.119 -input D_ACK_I; // Data Wishbone interface acknowledgement 39.120 -input D_ERR_I; // Data Wishbone interface error 39.121 -input D_RTY_I; // Data Wishbone interface retry 39.122 - 39.123 -///////////////////////////////////////////////////// 39.124 -// Outputs 39.125 -///////////////////////////////////////////////////// 39.126 - 39.127 -`ifdef CFG_USER_ENABLED 39.128 -output user_valid; // Indicates that user_opcode and user_operand_* are valid 39.129 -wire user_valid; 39.130 -output [`LM32_USER_OPCODE_RNG] user_opcode; // User-defined instruction opcode 39.131 -reg [`LM32_USER_OPCODE_RNG] user_opcode; 39.132 -output [`LM32_WORD_RNG] user_operand_0; // First operand for user-defined instruction 39.133 -wire [`LM32_WORD_RNG] user_operand_0; 39.134 -output [`LM32_WORD_RNG] user_operand_1; // Second operand for user-defined instruction 39.135 -wire [`LM32_WORD_RNG] user_operand_1; 39.136 -`endif 39.137 - 39.138 -`ifdef CFG_IWB_ENABLED 39.139 -output [`LM32_WORD_RNG] I_DAT_O; // Instruction Wishbone interface write data 39.140 -wire [`LM32_WORD_RNG] I_DAT_O; 39.141 -output [`LM32_WORD_RNG] I_ADR_O; // Instruction Wishbone interface address 39.142 -wire [`LM32_WORD_RNG] I_ADR_O; 39.143 -output I_CYC_O; // Instruction Wishbone interface cycle 39.144 -wire I_CYC_O; 39.145 -output [`LM32_BYTE_SELECT_RNG] I_SEL_O; // Instruction Wishbone interface byte select 39.146 -wire [`LM32_BYTE_SELECT_RNG] I_SEL_O; 39.147 -output I_STB_O; // Instruction Wishbone interface strobe 39.148 -wire I_STB_O; 39.149 -output I_WE_O; // Instruction Wishbone interface write enable 39.150 -wire I_WE_O; 39.151 -output [`LM32_CTYPE_RNG] I_CTI_O; // Instruction Wishbone interface cycle type 39.152 -wire [`LM32_CTYPE_RNG] I_CTI_O; 39.153 -output I_LOCK_O; // Instruction Wishbone interface lock bus 39.154 -wire I_LOCK_O; 39.155 -output [`LM32_BTYPE_RNG] I_BTE_O; // Instruction Wishbone interface burst type 39.156 -wire [`LM32_BTYPE_RNG] I_BTE_O; 39.157 -`endif 39.158 - 39.159 -output [`LM32_WORD_RNG] D_DAT_O; // Data Wishbone interface write data 39.160 -wire [`LM32_WORD_RNG] D_DAT_O; 39.161 -output [`LM32_WORD_RNG] D_ADR_O; // Data Wishbone interface address 39.162 -wire [`LM32_WORD_RNG] D_ADR_O; 39.163 -output D_CYC_O; // Data Wishbone interface cycle 39.164 -wire D_CYC_O; 39.165 -output [`LM32_BYTE_SELECT_RNG] D_SEL_O; // Data Wishbone interface byte select 39.166 -wire [`LM32_BYTE_SELECT_RNG] D_SEL_O; 39.167 -output D_STB_O; // Data Wishbone interface strobe 39.168 -wire D_STB_O; 39.169 -output D_WE_O; // Data Wishbone interface write enable 39.170 -wire D_WE_O; 39.171 -output [`LM32_CTYPE_RNG] D_CTI_O; // Data Wishbone interface cycle type 39.172 -wire [`LM32_CTYPE_RNG] D_CTI_O; 39.173 -output D_LOCK_O; // Date Wishbone interface lock bus 39.174 -wire D_LOCK_O; 39.175 -output [`LM32_BTYPE_RNG] D_BTE_O; // Data Wishbone interface burst type 39.176 -wire [`LM32_BTYPE_RNG] D_BTE_O; 39.177 - 39.178 -///////////////////////////////////////////////////// 39.179 -// Internal nets and registers 39.180 -///////////////////////////////////////////////////// 39.181 - 39.182 -`ifdef CFG_JTAG_ENABLED 39.183 -// Signals between JTAG interface and CPU 39.184 -wire [`LM32_BYTE_RNG] jtag_reg_d; 39.185 -wire [`LM32_BYTE_RNG] jtag_reg_q; 39.186 -wire jtag_update; 39.187 -wire [2:0] jtag_reg_addr_d; 39.188 -wire [2:0] jtag_reg_addr_q; 39.189 -wire jtck; 39.190 -wire jrstn; 39.191 -`endif 39.192 - 39.193 -// TODO: get the trace signals out 39.194 -`ifdef CFG_TRACE_ENABLED 39.195 -// PC trace signals 39.196 -wire [`LM32_PC_RNG] trace_pc; // PC to trace (address of next non-sequential instruction) 39.197 -wire trace_pc_valid; // Indicates that a new trace PC is valid 39.198 -wire trace_exception; // Indicates an exception has occured 39.199 -wire [`LM32_EID_RNG] trace_eid; // Indicates what type of exception has occured 39.200 -wire trace_eret; // Indicates an eret instruction has been executed 39.201 -`ifdef CFG_DEBUG_ENABLED 39.202 -wire trace_bret; // Indicates a bret instruction has been executed 39.203 -`endif 39.204 -`endif 39.205 - 39.206 -///////////////////////////////////////////////////// 39.207 -// Functions 39.208 -///////////////////////////////////////////////////// 39.209 - 39.210 -`include "lm32_functions.v" 39.211 -///////////////////////////////////////////////////// 39.212 -// Instantiations 39.213 -///////////////////////////////////////////////////// 39.214 - 39.215 -// LM32 CPU 39.216 -lm32_cpu cpu ( 39.217 - // ----- Inputs ------- 39.218 - .clk_i (clk_i), 39.219 -`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE 39.220 - .clk_n_i (clk_n), 39.221 -`endif 39.222 - .rst_i (rst_i), 39.223 - // From external devices 39.224 -`ifdef CFG_INTERRUPTS_ENABLED 39.225 - .interrupt (interrupt), 39.226 -`endif 39.227 - // From user logic 39.228 -`ifdef CFG_USER_ENABLED 39.229 - .user_result (user_result), 39.230 - .user_complete (user_complete), 39.231 -`endif 39.232 -`ifdef CFG_JTAG_ENABLED 39.233 - // From JTAG 39.234 - .jtag_clk (jtck), 39.235 - .jtag_update (jtag_update), 39.236 - .jtag_reg_q (jtag_reg_q), 39.237 - .jtag_reg_addr_q (jtag_reg_addr_q), 39.238 -`endif 39.239 -`ifdef CFG_IWB_ENABLED 39.240 - // Instruction Wishbone master 39.241 - .I_DAT_I (I_DAT_I), 39.242 - .I_ACK_I (I_ACK_I), 39.243 - .I_ERR_I (I_ERR_I), 39.244 - .I_RTY_I (I_RTY_I), 39.245 -`endif 39.246 - // Data Wishbone master 39.247 - .D_DAT_I (D_DAT_I), 39.248 - .D_ACK_I (D_ACK_I), 39.249 - .D_ERR_I (D_ERR_I), 39.250 - .D_RTY_I (D_RTY_I), 39.251 - // ----- Outputs ------- 39.252 -`ifdef CFG_TRACE_ENABLED 39.253 - .trace_pc (trace_pc), 39.254 - .trace_pc_valid (trace_pc_valid), 39.255 - .trace_exception (trace_exception), 39.256 - .trace_eid (trace_eid), 39.257 - .trace_eret (trace_eret), 39.258 -`ifdef CFG_DEBUG_ENABLED 39.259 - .trace_bret (trace_bret), 39.260 -`endif 39.261 -`endif 39.262 -`ifdef CFG_JTAG_ENABLED 39.263 - .jtag_reg_d (jtag_reg_d), 39.264 - .jtag_reg_addr_d (jtag_reg_addr_d), 39.265 -`endif 39.266 -`ifdef CFG_USER_ENABLED 39.267 - .user_valid (user_valid), 39.268 - .user_opcode (user_opcode), 39.269 - .user_operand_0 (user_operand_0), 39.270 - .user_operand_1 (user_operand_1), 39.271 -`endif 39.272 -`ifdef CFG_IWB_ENABLED 39.273 - // Instruction Wishbone master 39.274 - .I_DAT_O (I_DAT_O), 39.275 - .I_ADR_O (I_ADR_O), 39.276 - .I_CYC_O (I_CYC_O), 39.277 - .I_SEL_O (I_SEL_O), 39.278 - .I_STB_O (I_STB_O), 39.279 - .I_WE_O (I_WE_O), 39.280 - .I_CTI_O (I_CTI_O), 39.281 - .I_LOCK_O (I_LOCK_O), 39.282 - .I_BTE_O (I_BTE_O), 39.283 - `endif 39.284 - // Data Wishbone master 39.285 - .D_DAT_O (D_DAT_O), 39.286 - .D_ADR_O (D_ADR_O), 39.287 - .D_CYC_O (D_CYC_O), 39.288 - .D_SEL_O (D_SEL_O), 39.289 - .D_STB_O (D_STB_O), 39.290 - .D_WE_O (D_WE_O), 39.291 - .D_CTI_O (D_CTI_O), 39.292 - .D_LOCK_O (D_LOCK_O), 39.293 - .D_BTE_O (D_BTE_O) 39.294 - ); 39.295 - 39.296 - wire TRACE_ACK_O; 39.297 - wire [`LM32_WORD_RNG] TRACE_DAT_O; 39.298 -`ifdef CFG_TRACE_ENABLED 39.299 - lm32_trace trace_module (.clk_i (clk_i), 39.300 - .rst_i (rst_i), 39.301 - .stb_i (DEBUG_STB_I & DEBUG_ADR_I[13]), 39.302 - .we_i (DEBUG_WE_I), 39.303 - .sel_i (DEBUG_SEL_I), 39.304 - .dat_i (DEBUG_DAT_I), 39.305 - .adr_i (DEBUG_ADR_I), 39.306 - .trace_pc (trace_pc), 39.307 - .trace_eid (trace_eid), 39.308 - .trace_eret (trace_eret), 39.309 - .trace_bret (trace_bret), 39.310 - .trace_pc_valid (trace_pc_valid), 39.311 - .trace_exception (trace_exception), 39.312 - .ack_o (TRACE_ACK_O), 39.313 - .dat_o (TRACE_DAT_O)); 39.314 -`else 39.315 - assign TRACE_ACK_O = 0; 39.316 - assign TRACE_DAT_O = 0; 39.317 -`endif 39.318 -`ifdef DEBUG_ROM 39.319 - wire ROM_ACK_O; 39.320 - wire [`LM32_WORD_RNG] ROM_DAT_O; 39.321 - 39.322 - assign DEBUG_ACK_O = DEBUG_ADR_I[13] ? TRACE_ACK_O : ROM_ACK_O; 39.323 - assign DEBUG_DAT_O = DEBUG_ADR_I[13] ? TRACE_DAT_O : ROM_DAT_O; 39.324 - 39.325 - // ROM monitor 39.326 - lm32_monitor debug_rom ( 39.327 - // ----- Inputs ------- 39.328 - .clk_i (clk_i), 39.329 - .rst_i (rst_i), 39.330 - .MON_ADR_I (DEBUG_ADR_I[10:2]), 39.331 - .MON_STB_I (DEBUG_STB_I & ~DEBUG_ADR_I[13]), 39.332 - .MON_CYC_I (DEBUG_CYC_I & ~DEBUG_ADR_I[13]), 39.333 - .MON_WE_I (DEBUG_WE_I), 39.334 - .MON_SEL_I (DEBUG_SEL_I), 39.335 - .MON_DAT_I (DEBUG_DAT_I), 39.336 - // ----- Outputs ------ 39.337 - .MON_RTY_O (DEBUG_RTY_O), 39.338 - .MON_ERR_O (DEBUG_ERR_O), 39.339 - .MON_ACK_O (ROM_ACK_O), 39.340 - .MON_DAT_O (ROM_DAT_O) 39.341 - ); 39.342 -`endif 39.343 - 39.344 -`ifdef CFG_JTAG_ENABLED 39.345 -// JTAG cores 39.346 -jtag_cores jtag_cores ( 39.347 - // ----- Inputs ----- 39.348 - .reg_d (jtag_reg_d), 39.349 - .reg_addr_d (jtag_reg_addr_d), 39.350 - // ----- Outputs ----- 39.351 - .reg_update (jtag_update), 39.352 - .reg_q (jtag_reg_q), 39.353 - .reg_addr_q (jtag_reg_addr_q), 39.354 - .jtck (jtck), 39.355 - .jrstn (jrstn) 39.356 - ); 39.357 -`endif 39.358 - 39.359 -endmodule
40.1 diff -r 252df75c8f67 -r c336e674a37e rtl/jtag_cores.v 40.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 40.3 +++ b/rtl/jtag_cores.v Tue Mar 08 09:40:42 2011 +0000 40.4 @@ -0,0 +1,66 @@ 40.5 +// Modified by GSI to use simple positive edge clocking and the JTAG capture state 40.6 + 40.7 +module jtag_cores ( 40.8 + input [7:0] reg_d, 40.9 + input [2:0] reg_addr_d, 40.10 + output reg_update, 40.11 + output [7:0] reg_q, 40.12 + output [2:0] reg_addr_q, 40.13 + output jtck, 40.14 + output jrstn 40.15 +); 40.16 + 40.17 +wire tck; 40.18 +wire tdi; 40.19 +wire tdo; 40.20 +wire capture; 40.21 +wire shift; 40.22 +wire update; 40.23 +wire e1dr; 40.24 +wire reset; 40.25 + 40.26 +jtag_tap jtag_tap ( 40.27 + .tck(tck), 40.28 + .tdi(tdi), 40.29 + .tdo(tdo), 40.30 + .capture(capture), 40.31 + .shift(shift), 40.32 + .e1dr(e1dr), 40.33 + .update(update), 40.34 + .reset(reset) 40.35 +); 40.36 + 40.37 +reg [10:0] jtag_shift; 40.38 +reg [10:0] jtag_latched; 40.39 + 40.40 +always @(posedge tck) 40.41 +begin 40.42 + if(reset) 40.43 + jtag_shift <= 11'b0; 40.44 + else begin 40.45 + if (shift) 40.46 + jtag_shift <= {tdi, jtag_shift[10:1]}; 40.47 + else if (capture) 40.48 + jtag_shift <= {reg_d, reg_addr_d}; 40.49 + end 40.50 +end 40.51 + 40.52 +assign tdo = jtag_shift[0]; 40.53 + 40.54 +always @(posedge tck) 40.55 +begin 40.56 + if(reset) 40.57 + jtag_latched <= 11'b0; 40.58 + else begin 40.59 + if (e1dr) 40.60 + jtag_latched <= jtag_shift; 40.61 + end 40.62 +end 40.63 + 40.64 +assign reg_update = update; 40.65 +assign reg_q = jtag_latched[10:3]; 40.66 +assign reg_addr_q = jtag_latched[2:0]; 40.67 +assign jtck = tck; 40.68 +assign jrstn = ~reset; 40.69 + 40.70 +endmodule
41.1 diff -r 252df75c8f67 -r c336e674a37e rtl/jtag_tap_altera.v 41.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 41.3 +++ b/rtl/jtag_tap_altera.v Tue Mar 08 09:40:42 2011 +0000 41.4 @@ -0,0 +1,59 @@ 41.5 +module jtag_tap( 41.6 + output tck, 41.7 + output tdi, 41.8 + input tdo, 41.9 + output capture, 41.10 + output shift, 41.11 + output e1dr, 41.12 + output update, 41.13 + output reset 41.14 +); 41.15 + 41.16 +assign reset = 0; 41.17 +wire nil1, nil2, nil3, nil4; 41.18 + 41.19 +sld_virtual_jtag altera_jtag( 41.20 + .ir_in (), 41.21 + .ir_out (), 41.22 + .tck (tck), 41.23 + .tdo (tdo), 41.24 + .tdi (tdi), 41.25 + .virtual_state_cdr (capture), 41.26 + .virtual_state_sdr (shift), 41.27 + .virtual_state_e1dr (e1dr), 41.28 + .virtual_state_pdr (nil1), 41.29 + .virtual_state_e2dr (nil2), 41.30 + .virtual_state_udr (update), 41.31 + .virtual_state_cir (nil3), 41.32 + .virtual_state_uir (nil4) 41.33 + // synopsys translate_off 41.34 + , 41.35 + .jtag_state_cdr (), 41.36 + .jtag_state_cir (), 41.37 + .jtag_state_e1dr (), 41.38 + .jtag_state_e1ir (), 41.39 + .jtag_state_e2dr (), 41.40 + .jtag_state_e2ir (), 41.41 + .jtag_state_pdr (), 41.42 + .jtag_state_pir (), 41.43 + .jtag_state_rti (), 41.44 + .jtag_state_sdr (), 41.45 + .jtag_state_sdrs (), 41.46 + .jtag_state_sir (), 41.47 + .jtag_state_sirs (), 41.48 + .jtag_state_tlr (), 41.49 + .jtag_state_udr (), 41.50 + .jtag_state_uir (), 41.51 + .tms () 41.52 + // synopsys translate_on 41.53 + ); 41.54 + 41.55 +defparam 41.56 + altera_jtag.sld_auto_instance_index = "YES", 41.57 + altera_jtag.sld_instance_index = 0, 41.58 + altera_jtag.sld_ir_width = 1, 41.59 + altera_jtag.sld_sim_action = "", 41.60 + altera_jtag.sld_sim_n_scan = 0, 41.61 + altera_jtag.sld_sim_total_length = 0; 41.62 + 41.63 +endmodule
42.1 diff -r 252df75c8f67 -r c336e674a37e rtl/jtag_tap_xilinx_spartan6.v 42.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 42.3 +++ b/rtl/jtag_tap_xilinx_spartan6.v Tue Mar 08 09:40:42 2011 +0000 42.4 @@ -0,0 +1,43 @@ 42.5 + 42.6 +module jtag_tap( 42.7 + output tck, 42.8 + output tdi, 42.9 + input tdo, 42.10 + output capture, 42.11 + output shift, 42.12 + output e1dr, 42.13 + output update, 42.14 + output reset 42.15 +); 42.16 + 42.17 +// Unfortunately the exit1 state for DR (e1dr) is mising 42.18 +// We can simulate it by interpretting 'update' as e1dr and delaying 'update' 42.19 +wire g_capture; 42.20 +wire g_shift; 42.21 +wire g_update; 42.22 +reg update_delay; 42.23 + 42.24 +assign capture = g_capture & sel; 42.25 +assign shift = g_shift & sel; 42.26 +assign e1dr = g_update & sel; 42.27 +assign update = update_delay; 42.28 + 42.29 +BSCAN_SPARTAN6 #( 42.30 + .JTAG_CHAIN(1) 42.31 +) bscan ( 42.32 + .CAPTURE(g_capture), 42.33 + .DRCK(tck), 42.34 + .RESET(reset), 42.35 + .RUNTEST(), 42.36 + .SEL(sel), 42.37 + .SHIFT(g_shift), 42.38 + .TCK(), 42.39 + .TDI(tdi), 42.40 + .TMS(), 42.41 + .UPDATE(g_update), 42.42 + .TDO(tdo) 42.43 +); 42.44 + 42.45 +update_delay <= g_update; 42.46 + 42.47 +endmodule
43.1 diff -r 252df75c8f67 -r c336e674a37e rtl/lm32_adder.v 43.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 43.3 +++ b/rtl/lm32_adder.v Tue Mar 08 09:40:42 2011 +0000 43.4 @@ -0,0 +1,115 @@ 43.5 +// ============================================================================= 43.6 +// COPYRIGHT NOTICE 43.7 +// Copyright 2006 (c) Lattice Semiconductor Corporation 43.8 +// ALL RIGHTS RESERVED 43.9 +// This confidential and proprietary software may be used only as authorised by 43.10 +// a licensing agreement from Lattice Semiconductor Corporation. 43.11 +// The entire notice above must be reproduced on all authorized copies and 43.12 +// copies may only be made to the extent permitted by a licensing agreement from 43.13 +// Lattice Semiconductor Corporation. 43.14 +// 43.15 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 43.16 +// 5555 NE Moore Court 408-826-6000 (other locations) 43.17 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 43.18 +// U.S.A email: techsupport@latticesemi.com 43.19 +// ============================================================================/ 43.20 +// FILE DETAILS 43.21 +// Project : LatticeMico32 43.22 +// File : lm32_adder.v 43.23 +// Title : Integer adder / subtractor with comparison flag generation 43.24 +// Dependencies : lm32_include.v 43.25 +// Version : 6.1.17 43.26 +// : Initial Release 43.27 +// Version : 7.0SP2, 3.0 43.28 +// : No Change 43.29 +// Version : 3.1 43.30 +// : No Change 43.31 +// ============================================================================= 43.32 + 43.33 +`include "lm32_include.v" 43.34 + 43.35 +///////////////////////////////////////////////////// 43.36 +// Module interface 43.37 +///////////////////////////////////////////////////// 43.38 + 43.39 +module lm32_adder ( 43.40 + // ----- Inputs ------- 43.41 + adder_op_x, 43.42 + adder_op_x_n, 43.43 + operand_0_x, 43.44 + operand_1_x, 43.45 + // ----- Outputs ------- 43.46 + adder_result_x, 43.47 + adder_carry_n_x, 43.48 + adder_overflow_x 43.49 + ); 43.50 + 43.51 +///////////////////////////////////////////////////// 43.52 +// Inputs 43.53 +///////////////////////////////////////////////////// 43.54 + 43.55 +input adder_op_x; // Operating to perform, 0 for addition, 1 for subtraction 43.56 +input adder_op_x_n; // Inverted version of adder_op_x 43.57 +input [`LM32_WORD_RNG] operand_0_x; // Operand to add, or subtract from 43.58 +input [`LM32_WORD_RNG] operand_1_x; // Opearnd to add, or subtract by 43.59 + 43.60 +///////////////////////////////////////////////////// 43.61 +// Outputs 43.62 +///////////////////////////////////////////////////// 43.63 + 43.64 +output [`LM32_WORD_RNG] adder_result_x; // Result of addition or subtraction 43.65 +wire [`LM32_WORD_RNG] adder_result_x; 43.66 +output adder_carry_n_x; // Inverted carry 43.67 +wire adder_carry_n_x; 43.68 +output adder_overflow_x; // Indicates if overflow occured, only valid for subtractions 43.69 +reg adder_overflow_x; 43.70 + 43.71 +///////////////////////////////////////////////////// 43.72 +// Internal nets and registers 43.73 +///////////////////////////////////////////////////// 43.74 + 43.75 +wire a_sign; // Sign (i.e. positive or negative) of operand 0 43.76 +wire b_sign; // Sign of operand 1 43.77 +wire result_sign; // Sign of result 43.78 + 43.79 +///////////////////////////////////////////////////// 43.80 +// Instantiations 43.81 +///////////////////////////////////////////////////// 43.82 + 43.83 +lm32_addsub addsub ( 43.84 + // ----- Inputs ----- 43.85 + .DataA (operand_0_x), 43.86 + .DataB (operand_1_x), 43.87 + .Cin (adder_op_x), 43.88 + .Add_Sub (adder_op_x_n), 43.89 + // ----- Ouputs ----- 43.90 + .Result (adder_result_x), 43.91 + .Cout (adder_carry_n_x) 43.92 + ); 43.93 + 43.94 +///////////////////////////////////////////////////// 43.95 +// Combinational Logic 43.96 +///////////////////////////////////////////////////// 43.97 + 43.98 +// Extract signs of operands and result 43.99 + 43.100 +assign a_sign = operand_0_x[`LM32_WORD_WIDTH-1]; 43.101 +assign b_sign = operand_1_x[`LM32_WORD_WIDTH-1]; 43.102 +assign result_sign = adder_result_x[`LM32_WORD_WIDTH-1]; 43.103 + 43.104 +// Determine whether an overflow occured when performing a subtraction 43.105 + 43.106 +always @(*) 43.107 +begin 43.108 + // +ve - -ve = -ve -> overflow 43.109 + // -ve - +ve = +ve -> overflow 43.110 + if ( (!a_sign & b_sign & result_sign) 43.111 + || (a_sign & !b_sign & !result_sign) 43.112 + ) 43.113 + adder_overflow_x = `TRUE; 43.114 + else 43.115 + adder_overflow_x = `FALSE; 43.116 +end 43.117 + 43.118 +endmodule 43.119 +
44.1 diff -r 252df75c8f67 -r c336e674a37e rtl/lm32_addsub.v 44.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 44.3 +++ b/rtl/lm32_addsub.v Tue Mar 08 09:40:42 2011 +0000 44.4 @@ -0,0 +1,98 @@ 44.5 +// ============================================================================= 44.6 +// COPYRIGHT NOTICE 44.7 +// Copyright 2006 (c) Lattice Semiconductor Corporation 44.8 +// ALL RIGHTS RESERVED 44.9 +// This confidential and proprietary software may be used only as authorised by 44.10 +// a licensing agreement from Lattice Semiconductor Corporation. 44.11 +// The entire notice above must be reproduced on all authorized copies and 44.12 +// copies may only be made to the extent permitted by a licensing agreement from 44.13 +// Lattice Semiconductor Corporation. 44.14 +// 44.15 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 44.16 +// 5555 NE Moore Court 408-826-6000 (other locations) 44.17 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 44.18 +// U.S.A email: techsupport@latticesemi.com 44.19 +// =============================================================================/ 44.20 +// FILE DETAILS 44.21 +// Project : LatticeMico32 44.22 +// File : lm32_addsub.v 44.23 +// Title : PMI adder/subtractor. 44.24 +// Version : 6.1.17 44.25 +// : Initial Release 44.26 +// Version : 7.0SP2, 3.0 44.27 +// : No Change 44.28 +// Version : 3.1 44.29 +// : No Change 44.30 +// ============================================================================= 44.31 + 44.32 +`include "lm32_include.v" 44.33 + 44.34 +///////////////////////////////////////////////////// 44.35 +// Module interface 44.36 +///////////////////////////////////////////////////// 44.37 + 44.38 +module lm32_addsub ( 44.39 + // ----- Inputs ------- 44.40 + DataA, 44.41 + DataB, 44.42 + Cin, 44.43 + Add_Sub, 44.44 + // ----- Outputs ------- 44.45 + Result, 44.46 + Cout 44.47 + ); 44.48 + 44.49 +///////////////////////////////////////////////////// 44.50 +// Inputs 44.51 +///////////////////////////////////////////////////// 44.52 + 44.53 +input [31:0] DataA; 44.54 +input [31:0] DataB; 44.55 +input Cin; 44.56 +input Add_Sub; 44.57 + 44.58 +///////////////////////////////////////////////////// 44.59 +// Outputs 44.60 +///////////////////////////////////////////////////// 44.61 + 44.62 +output [31:0] Result; 44.63 +wire [31:0] Result; 44.64 +output Cout; 44.65 +wire Cout; 44.66 + 44.67 +///////////////////////////////////////////////////// 44.68 +// Instantiations 44.69 +///////////////////////////////////////////////////// 44.70 + 44.71 +// Only use Lattice specific constructs when compiling with ispLEVER 44.72 +`ifdef PLATFORM_LATTICE 44.73 + generate 44.74 + if (`LATTICE_FAMILY == "SC" || `LATTICE_FAMILY == "SCM") begin 44.75 +`endif 44.76 + wire [32:0] tmp_addResult = DataA + DataB + Cin; 44.77 + wire [32:0] tmp_subResult = DataA - DataB - !Cin; 44.78 + 44.79 + assign Result = (Add_Sub == 1) ? tmp_addResult[31:0] : tmp_subResult[31:0]; 44.80 + assign Cout = (Add_Sub == 1) ? tmp_addResult[32] : !tmp_subResult[32]; 44.81 +`ifdef PLATFORM_LATTICE 44.82 + end else begin 44.83 + pmi_addsub #(// ----- Parameters ------- 44.84 + .pmi_data_width (32), 44.85 + .pmi_result_width (32), 44.86 + .pmi_sign ("off"), 44.87 + .pmi_family (`LATTICE_FAMILY), 44.88 + .module_type ("pmi_addsub")) 44.89 + addsub (// ----- Inputs ------- 44.90 + .DataA (DataA), 44.91 + .DataB (DataB), 44.92 + .Cin (Cin), 44.93 + .Add_Sub (Add_Sub), 44.94 + // ----- Outputs ------- 44.95 + .Result (Result), 44.96 + .Cout (Cout), 44.97 + .Overflow ()); 44.98 + end 44.99 + endgenerate 44.100 +`endif 44.101 + 44.102 +endmodule
45.1 diff -r 252df75c8f67 -r c336e674a37e rtl/lm32_cpu.v 45.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 45.3 +++ b/rtl/lm32_cpu.v Tue Mar 08 09:40:42 2011 +0000 45.4 @@ -0,0 +1,2717 @@ 45.5 +// ============================================================================= 45.6 +// COPYRIGHT NOTICE 45.7 +// Copyright 2006 (c) Lattice Semiconductor Corporation 45.8 +// ALL RIGHTS RESERVED 45.9 +// This confidential and proprietary software may be used only as authorised by 45.10 +// a licensing agreement from Lattice Semiconductor Corporation. 45.11 +// The entire notice above must be reproduced on all authorized copies and 45.12 +// copies may only be made to the extent permitted by a licensing agreement from 45.13 +// Lattice Semiconductor Corporation. 45.14 +// 45.15 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 45.16 +// 5555 NE Moore Court 408-826-6000 (other locations) 45.17 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 45.18 +// U.S.A email: techsupport@latticesemi.com 45.19 +// =============================================================================/ 45.20 +// FILE DETAILS 45.21 +// Project : LatticeMico32 45.22 +// File : lm32_cpu.v 45.23 +// Title : Top-level of CPU. 45.24 +// Dependencies : lm32_include.v 45.25 +// 45.26 +// Version 3.4 45.27 +// 1. Bug Fix: In a tight infinite loop (add, sw, bi) incoming interrupts were 45.28 +// never serviced. 45.29 +// 45.30 +// Version 3.3 45.31 +// 1. Feature: Support for memory that is tightly coupled to processor core, and 45.32 +// has a single-cycle access latency (same as caches). Instruction port has 45.33 +// access to a dedicated physically-mapped memory. Data port has access to 45.34 +// a dedicated physically-mapped memory. In order to be able to manipulate 45.35 +// values in both these memories via the debugger, these memories also 45.36 +// interface with the data port of LM32. 45.37 +// 2. Feature: Extended Configuration Register 45.38 +// 3. Bug Fix: Removed port names that conflict with keywords reserved in System- 45.39 +// Verilog. 45.40 +// 45.41 +// Version 3.2 45.42 +// 1. Bug Fix: Single-stepping a load/store to invalid address causes debugger to 45.43 +// hang. At the same time CPU fails to register data bus error exception. Bug 45.44 +// is caused because (a) data bus error exception occurs after load/store has 45.45 +// passed X stage and next sequential instruction (e.g., brk) is already in X 45.46 +// stage, and (b) data bus error exception had lower priority than, say, brk 45.47 +// exception. 45.48 +// 2. Bug Fix: If a brk (or scall/eret/bret) sequentially follows a load/store to 45.49 +// invalid location, CPU will fail to register data bus error exception. The 45.50 +// solution is to stall scall/eret/bret/brk instructions in D pipeline stage 45.51 +// until load/store has completed. 45.52 +// 3. Feature: Enable precise identification of load/store that causes seg fault. 45.53 +// 4. SYNC resets used for register file when implemented in EBRs. 45.54 +// 45.55 +// Version 3.1 45.56 +// 1. Feature: LM32 Register File can now be mapped in to on-chip block RAM (EBR) 45.57 +// instead of distributed memory by enabling the option in LM32 GUI. 45.58 +// 2. Feature: LM32 also adds a static branch predictor to improve branch 45.59 +// performance. All immediate-based forward-pointing branches are predicted 45.60 +// not-taken. All immediate-based backward-pointing branches are predicted taken. 45.61 +// 45.62 +// Version 7.0SP2, 3.0 45.63 +// No Change 45.64 +// 45.65 +// Version 6.1.17 45.66 +// Initial Release 45.67 +// ============================================================================= 45.68 + 45.69 +`include "lm32_include.v" 45.70 + 45.71 +///////////////////////////////////////////////////// 45.72 +// Module interface 45.73 +///////////////////////////////////////////////////// 45.74 + 45.75 +module lm32_cpu ( 45.76 + // ----- Inputs ------- 45.77 + clk_i, 45.78 +`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE 45.79 + clk_n_i, 45.80 +`endif 45.81 + rst_i, 45.82 + // From external devices 45.83 +`ifdef CFG_INTERRUPTS_ENABLED 45.84 + interrupt, 45.85 +`endif 45.86 + // From user logic 45.87 +`ifdef CFG_USER_ENABLED 45.88 + user_result, 45.89 + user_complete, 45.90 +`endif 45.91 +`ifdef CFG_JTAG_ENABLED 45.92 + // From JTAG 45.93 + jtag_clk, 45.94 + jtag_update, 45.95 + jtag_reg_q, 45.96 + jtag_reg_addr_q, 45.97 +`endif 45.98 +`ifdef CFG_IWB_ENABLED 45.99 + // Instruction Wishbone master 45.100 + I_DAT_I, 45.101 + I_ACK_I, 45.102 + I_ERR_I, 45.103 + I_RTY_I, 45.104 +`endif 45.105 + // Data Wishbone master 45.106 + D_DAT_I, 45.107 + D_ACK_I, 45.108 + D_ERR_I, 45.109 + D_RTY_I, 45.110 + // ----- Outputs ------- 45.111 +`ifdef CFG_TRACE_ENABLED 45.112 + trace_pc, 45.113 + trace_pc_valid, 45.114 + trace_exception, 45.115 + trace_eid, 45.116 + trace_eret, 45.117 +`ifdef CFG_DEBUG_ENABLED 45.118 + trace_bret, 45.119 +`endif 45.120 +`endif 45.121 +`ifdef CFG_JTAG_ENABLED 45.122 + jtag_reg_d, 45.123 + jtag_reg_addr_d, 45.124 +`endif 45.125 +`ifdef CFG_USER_ENABLED 45.126 + user_valid, 45.127 + user_opcode, 45.128 + user_operand_0, 45.129 + user_operand_1, 45.130 +`endif 45.131 +`ifdef CFG_IWB_ENABLED 45.132 + // Instruction Wishbone master 45.133 + I_DAT_O, 45.134 + I_ADR_O, 45.135 + I_CYC_O, 45.136 + I_SEL_O, 45.137 + I_STB_O, 45.138 + I_WE_O, 45.139 + I_CTI_O, 45.140 + I_LOCK_O, 45.141 + I_BTE_O, 45.142 +`endif 45.143 + // Data Wishbone master 45.144 + D_DAT_O, 45.145 + D_ADR_O, 45.146 + D_CYC_O, 45.147 + D_SEL_O, 45.148 + D_STB_O, 45.149 + D_WE_O, 45.150 + D_CTI_O, 45.151 + D_LOCK_O, 45.152 + D_BTE_O 45.153 + ); 45.154 + 45.155 +///////////////////////////////////////////////////// 45.156 +// Parameters 45.157 +///////////////////////////////////////////////////// 45.158 + 45.159 +parameter eba_reset = `CFG_EBA_RESET; // Reset value for EBA CSR 45.160 +`ifdef CFG_DEBUG_ENABLED 45.161 +parameter deba_reset = `CFG_DEBA_RESET; // Reset value for DEBA CSR 45.162 +`endif 45.163 + 45.164 +`ifdef CFG_ICACHE_ENABLED 45.165 +parameter icache_associativity = `CFG_ICACHE_ASSOCIATIVITY; // Associativity of the cache (Number of ways) 45.166 +parameter icache_sets = `CFG_ICACHE_SETS; // Number of sets 45.167 +parameter icache_bytes_per_line = `CFG_ICACHE_BYTES_PER_LINE; // Number of bytes per cache line 45.168 +parameter icache_base_address = `CFG_ICACHE_BASE_ADDRESS; // Base address of cachable memory 45.169 +parameter icache_limit = `CFG_ICACHE_LIMIT; // Limit (highest address) of cachable memory 45.170 +`else 45.171 +parameter icache_associativity = 1; 45.172 +parameter icache_sets = 512; 45.173 +parameter icache_bytes_per_line = 16; 45.174 +parameter icache_base_address = 0; 45.175 +parameter icache_limit = 0; 45.176 +`endif 45.177 + 45.178 +`ifdef CFG_DCACHE_ENABLED 45.179 +parameter dcache_associativity = `CFG_DCACHE_ASSOCIATIVITY; // Associativity of the cache (Number of ways) 45.180 +parameter dcache_sets = `CFG_DCACHE_SETS; // Number of sets 45.181 +parameter dcache_bytes_per_line = `CFG_DCACHE_BYTES_PER_LINE; // Number of bytes per cache line 45.182 +parameter dcache_base_address = `CFG_DCACHE_BASE_ADDRESS; // Base address of cachable memory 45.183 +parameter dcache_limit = `CFG_DCACHE_LIMIT; // Limit (highest address) of cachable memory 45.184 +`else 45.185 +parameter dcache_associativity = 1; 45.186 +parameter dcache_sets = 512; 45.187 +parameter dcache_bytes_per_line = 16; 45.188 +parameter dcache_base_address = 0; 45.189 +parameter dcache_limit = 0; 45.190 +`endif 45.191 + 45.192 +`ifdef CFG_DEBUG_ENABLED 45.193 +parameter watchpoints = `CFG_WATCHPOINTS; // Number of h/w watchpoint CSRs 45.194 +`else 45.195 +parameter watchpoints = 0; 45.196 +`endif 45.197 +`ifdef CFG_ROM_DEBUG_ENABLED 45.198 +parameter breakpoints = `CFG_BREAKPOINTS; // Number of h/w breakpoint CSRs 45.199 +`else 45.200 +parameter breakpoints = 0; 45.201 +`endif 45.202 + 45.203 +`ifdef CFG_INTERRUPTS_ENABLED 45.204 +parameter interrupts = `CFG_INTERRUPTS; // Number of interrupts 45.205 +`else 45.206 +parameter interrupts = 0; 45.207 +`endif 45.208 + 45.209 +///////////////////////////////////////////////////// 45.210 +// Inputs 45.211 +///////////////////////////////////////////////////// 45.212 + 45.213 +input clk_i; // Clock 45.214 +`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE 45.215 +input clk_n_i; // Inverted clock 45.216 +`endif 45.217 +input rst_i; // Reset 45.218 + 45.219 +`ifdef CFG_INTERRUPTS_ENABLED 45.220 +input [`LM32_INTERRUPT_RNG] interrupt; // Interrupt pins 45.221 +`endif 45.222 + 45.223 +`ifdef CFG_USER_ENABLED 45.224 +input [`LM32_WORD_RNG] user_result; // User-defined instruction result 45.225 +input user_complete; // User-defined instruction execution is complete 45.226 +`endif 45.227 + 45.228 +`ifdef CFG_JTAG_ENABLED 45.229 +input jtag_clk; // JTAG clock 45.230 +input jtag_update; // JTAG state machine is in data register update state 45.231 +input [`LM32_BYTE_RNG] jtag_reg_q; 45.232 +input [2:0] jtag_reg_addr_q; 45.233 +`endif 45.234 + 45.235 +`ifdef CFG_IWB_ENABLED 45.236 +input [`LM32_WORD_RNG] I_DAT_I; // Instruction Wishbone interface read data 45.237 +input I_ACK_I; // Instruction Wishbone interface acknowledgement 45.238 +input I_ERR_I; // Instruction Wishbone interface error 45.239 +input I_RTY_I; // Instruction Wishbone interface retry 45.240 +`endif 45.241 + 45.242 +input [`LM32_WORD_RNG] D_DAT_I; // Data Wishbone interface read data 45.243 +input D_ACK_I; // Data Wishbone interface acknowledgement 45.244 +input D_ERR_I; // Data Wishbone interface error 45.245 +input D_RTY_I; // Data Wishbone interface retry 45.246 + 45.247 +///////////////////////////////////////////////////// 45.248 +// Outputs 45.249 +///////////////////////////////////////////////////// 45.250 + 45.251 +`ifdef CFG_TRACE_ENABLED 45.252 +output [`LM32_PC_RNG] trace_pc; // PC to trace 45.253 +reg [`LM32_PC_RNG] trace_pc; 45.254 +output trace_pc_valid; // Indicates that a new trace PC is valid 45.255 +reg trace_pc_valid; 45.256 +output trace_exception; // Indicates an exception has occured 45.257 +reg trace_exception; 45.258 +output [`LM32_EID_RNG] trace_eid; // Indicates what type of exception has occured 45.259 +reg [`LM32_EID_RNG] trace_eid; 45.260 +output trace_eret; // Indicates an eret instruction has been executed 45.261 +reg trace_eret; 45.262 +`ifdef CFG_DEBUG_ENABLED 45.263 +output trace_bret; // Indicates a bret instruction has been executed 45.264 +reg trace_bret; 45.265 +`endif 45.266 +`endif 45.267 + 45.268 +`ifdef CFG_JTAG_ENABLED 45.269 +output [`LM32_BYTE_RNG] jtag_reg_d; 45.270 +wire [`LM32_BYTE_RNG] jtag_reg_d; 45.271 +output [2:0] jtag_reg_addr_d; 45.272 +wire [2:0] jtag_reg_addr_d; 45.273 +`endif 45.274 + 45.275 +`ifdef CFG_USER_ENABLED 45.276 +output user_valid; // Indicates if user_opcode is valid 45.277 +wire user_valid; 45.278 +output [`LM32_USER_OPCODE_RNG] user_opcode; // User-defined instruction opcode 45.279 +reg [`LM32_USER_OPCODE_RNG] user_opcode; 45.280 +output [`LM32_WORD_RNG] user_operand_0; // First operand for user-defined instruction 45.281 +wire [`LM32_WORD_RNG] user_operand_0; 45.282 +output [`LM32_WORD_RNG] user_operand_1; // Second operand for user-defined instruction 45.283 +wire [`LM32_WORD_RNG] user_operand_1; 45.284 +`endif 45.285 + 45.286 +`ifdef CFG_IWB_ENABLED 45.287 +output [`LM32_WORD_RNG] I_DAT_O; // Instruction Wishbone interface write data 45.288 +wire [`LM32_WORD_RNG] I_DAT_O; 45.289 +output [`LM32_WORD_RNG] I_ADR_O; // Instruction Wishbone interface address 45.290 +wire [`LM32_WORD_RNG] I_ADR_O; 45.291 +output I_CYC_O; // Instruction Wishbone interface cycle 45.292 +wire I_CYC_O; 45.293 +output [`LM32_BYTE_SELECT_RNG] I_SEL_O; // Instruction Wishbone interface byte select 45.294 +wire [`LM32_BYTE_SELECT_RNG] I_SEL_O; 45.295 +output I_STB_O; // Instruction Wishbone interface strobe 45.296 +wire I_STB_O; 45.297 +output I_WE_O; // Instruction Wishbone interface write enable 45.298 +wire I_WE_O; 45.299 +output [`LM32_CTYPE_RNG] I_CTI_O; // Instruction Wishbone interface cycle type 45.300 +wire [`LM32_CTYPE_RNG] I_CTI_O; 45.301 +output I_LOCK_O; // Instruction Wishbone interface lock bus 45.302 +wire I_LOCK_O; 45.303 +output [`LM32_BTYPE_RNG] I_BTE_O; // Instruction Wishbone interface burst type 45.304 +wire [`LM32_BTYPE_RNG] I_BTE_O; 45.305 +`endif 45.306 + 45.307 +output [`LM32_WORD_RNG] D_DAT_O; // Data Wishbone interface write data 45.308 +wire [`LM32_WORD_RNG] D_DAT_O; 45.309 +output [`LM32_WORD_RNG] D_ADR_O; // Data Wishbone interface address 45.310 +wire [`LM32_WORD_RNG] D_ADR_O; 45.311 +output D_CYC_O; // Data Wishbone interface cycle 45.312 +wire D_CYC_O; 45.313 +output [`LM32_BYTE_SELECT_RNG] D_SEL_O; // Data Wishbone interface byte select 45.314 +wire [`LM32_BYTE_SELECT_RNG] D_SEL_O; 45.315 +output D_STB_O; // Data Wishbone interface strobe 45.316 +wire D_STB_O; 45.317 +output D_WE_O; // Data Wishbone interface write enable 45.318 +wire D_WE_O; 45.319 +output [`LM32_CTYPE_RNG] D_CTI_O; // Data Wishbone interface cycle type 45.320 +wire [`LM32_CTYPE_RNG] D_CTI_O; 45.321 +output D_LOCK_O; // Date Wishbone interface lock bus 45.322 +wire D_LOCK_O; 45.323 +output [`LM32_BTYPE_RNG] D_BTE_O; // Data Wishbone interface burst type 45.324 +wire [`LM32_BTYPE_RNG] D_BTE_O; 45.325 + 45.326 +///////////////////////////////////////////////////// 45.327 +// Internal nets and registers 45.328 +///////////////////////////////////////////////////// 45.329 + 45.330 +// Pipeline registers 45.331 + 45.332 +`ifdef LM32_CACHE_ENABLED 45.333 +reg valid_a; // Instruction in A stage is valid 45.334 +`endif 45.335 +reg valid_f; // Instruction in F stage is valid 45.336 +reg valid_d; // Instruction in D stage is valid 45.337 +reg valid_x; // Instruction in X stage is valid 45.338 +reg valid_m; // Instruction in M stage is valid 45.339 +reg valid_w; // Instruction in W stage is valid 45.340 + 45.341 +wire q_x; 45.342 +wire [`LM32_WORD_RNG] immediate_d; // Immediate operand 45.343 +wire load_d; // Indicates a load instruction 45.344 +reg load_x; 45.345 +reg load_m; 45.346 +wire load_q_x; 45.347 +wire store_q_x; 45.348 +wire store_d; // Indicates a store instruction 45.349 +reg store_x; 45.350 +reg store_m; 45.351 +wire [`LM32_SIZE_RNG] size_d; // Size of load/store (byte, hword, word) 45.352 +reg [`LM32_SIZE_RNG] size_x; 45.353 +wire branch_d; // Indicates a branch instruction 45.354 +wire branch_predict_d; // Indicates a branch is predicted 45.355 +wire branch_predict_taken_d; // Indicates a branch is predicted taken 45.356 +wire [`LM32_PC_RNG] branch_predict_address_d; // Address to which predicted branch jumps 45.357 +wire [`LM32_PC_RNG] branch_target_d; 45.358 +wire bi_unconditional; 45.359 +wire bi_conditional; 45.360 +reg branch_x; 45.361 +reg branch_predict_x; 45.362 +reg branch_predict_taken_x; 45.363 +reg branch_m; 45.364 +reg branch_predict_m; 45.365 +reg branch_predict_taken_m; 45.366 +wire branch_mispredict_taken_m; // Indicates a branch was mispredicted as taken 45.367 +wire branch_flushX_m; // Indicates that instruction in X stage must be squashed 45.368 +wire branch_reg_d; // Branch to register or immediate 45.369 +wire [`LM32_PC_RNG] branch_offset_d; // Branch offset for immediate branches 45.370 +reg [`LM32_PC_RNG] branch_target_x; // Address to branch to 45.371 +reg [`LM32_PC_RNG] branch_target_m; 45.372 +wire [`LM32_D_RESULT_SEL_0_RNG] d_result_sel_0_d; // Which result should be selected in D stage for operand 0 45.373 +wire [`LM32_D_RESULT_SEL_1_RNG] d_result_sel_1_d; // Which result should be selected in D stage for operand 1 45.374 + 45.375 +wire x_result_sel_csr_d; // Select X stage result from CSRs 45.376 +reg x_result_sel_csr_x; 45.377 +`ifdef LM32_MC_ARITHMETIC_ENABLED 45.378 +wire x_result_sel_mc_arith_d; // Select X stage result from multi-cycle arithmetic unit 45.379 +reg x_result_sel_mc_arith_x; 45.380 +`endif 45.381 +`ifdef LM32_NO_BARREL_SHIFT 45.382 +wire x_result_sel_shift_d; // Select X stage result from shifter 45.383 +reg x_result_sel_shift_x; 45.384 +`endif 45.385 +`ifdef CFG_SIGN_EXTEND_ENABLED 45.386 +wire x_result_sel_sext_d; // Select X stage result from sign-extend logic 45.387 +reg x_result_sel_sext_x; 45.388 +`endif 45.389 +wire x_result_sel_logic_d; // Select X stage result from logic op unit 45.390 +reg x_result_sel_logic_x; 45.391 +`ifdef CFG_USER_ENABLED 45.392 +wire x_result_sel_user_d; // Select X stage result from user-defined logic 45.393 +reg x_result_sel_user_x; 45.394 +`endif 45.395 +wire x_result_sel_add_d; // Select X stage result from adder 45.396 +reg x_result_sel_add_x; 45.397 +wire m_result_sel_compare_d; // Select M stage result from comparison logic 45.398 +reg m_result_sel_compare_x; 45.399 +reg m_result_sel_compare_m; 45.400 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 45.401 +wire m_result_sel_shift_d; // Select M stage result from shifter 45.402 +reg m_result_sel_shift_x; 45.403 +reg m_result_sel_shift_m; 45.404 +`endif 45.405 +wire w_result_sel_load_d; // Select W stage result from load/store unit 45.406 +reg w_result_sel_load_x; 45.407 +reg w_result_sel_load_m; 45.408 +reg w_result_sel_load_w; 45.409 +`ifdef CFG_PL_MULTIPLY_ENABLED 45.410 +wire w_result_sel_mul_d; // Select W stage result from multiplier 45.411 +reg w_result_sel_mul_x; 45.412 +reg w_result_sel_mul_m; 45.413 +reg w_result_sel_mul_w; 45.414 +`endif 45.415 +wire x_bypass_enable_d; // Whether result is bypassable in X stage 45.416 +reg x_bypass_enable_x; 45.417 +wire m_bypass_enable_d; // Whether result is bypassable in M stage 45.418 +reg m_bypass_enable_x; 45.419 +reg m_bypass_enable_m; 45.420 +wire sign_extend_d; // Whether to sign-extend or zero-extend 45.421 +reg sign_extend_x; 45.422 +wire write_enable_d; // Register file write enable 45.423 +reg write_enable_x; 45.424 +wire write_enable_q_x; 45.425 +reg write_enable_m; 45.426 +wire write_enable_q_m; 45.427 +reg write_enable_w; 45.428 +wire write_enable_q_w; 45.429 +wire read_enable_0_d; // Register file read enable 0 45.430 +wire [`LM32_REG_IDX_RNG] read_idx_0_d; // Register file read index 0 45.431 +wire read_enable_1_d; // Register file read enable 1 45.432 +wire [`LM32_REG_IDX_RNG] read_idx_1_d; // Register file read index 1 45.433 +wire [`LM32_REG_IDX_RNG] write_idx_d; // Register file write index 45.434 +reg [`LM32_REG_IDX_RNG] write_idx_x; 45.435 +reg [`LM32_REG_IDX_RNG] write_idx_m; 45.436 +reg [`LM32_REG_IDX_RNG] write_idx_w; 45.437 +wire [`LM32_CSR_RNG] csr_d; // CSR read/write index 45.438 +reg [`LM32_CSR_RNG] csr_x; 45.439 +wire [`LM32_CONDITION_RNG] condition_d; // Branch condition 45.440 +reg [`LM32_CONDITION_RNG] condition_x; 45.441 +`ifdef CFG_DEBUG_ENABLED 45.442 +wire break_d; // Indicates a break instruction 45.443 +reg break_x; 45.444 +`endif 45.445 +wire scall_d; // Indicates a scall instruction 45.446 +reg scall_x; 45.447 +wire eret_d; // Indicates an eret instruction 45.448 +reg eret_x; 45.449 +wire eret_q_x; 45.450 +reg eret_m; 45.451 +`ifdef CFG_TRACE_ENABLED 45.452 +reg eret_w; 45.453 +`endif 45.454 +`ifdef CFG_DEBUG_ENABLED 45.455 +wire bret_d; // Indicates a bret instruction 45.456 +reg bret_x; 45.457 +wire bret_q_x; 45.458 +reg bret_m; 45.459 +`ifdef CFG_TRACE_ENABLED 45.460 +reg bret_w; 45.461 +`endif 45.462 +`endif 45.463 +wire csr_write_enable_d; // CSR write enable 45.464 +reg csr_write_enable_x; 45.465 +wire csr_write_enable_q_x; 45.466 +`ifdef CFG_USER_ENABLED 45.467 +wire [`LM32_USER_OPCODE_RNG] user_opcode_d; // User-defined instruction opcode 45.468 +`endif 45.469 + 45.470 +`ifdef CFG_BUS_ERRORS_ENABLED 45.471 +wire bus_error_d; // Indicates an bus error occured while fetching the instruction in this pipeline stage 45.472 +reg bus_error_x; 45.473 +reg data_bus_error_exception_m; 45.474 +reg [`LM32_PC_RNG] memop_pc_w; 45.475 +`endif 45.476 + 45.477 +reg [`LM32_WORD_RNG] d_result_0; // Result of instruction in D stage (operand 0) 45.478 +reg [`LM32_WORD_RNG] d_result_1; // Result of instruction in D stage (operand 1) 45.479 +reg [`LM32_WORD_RNG] x_result; // Result of instruction in X stage 45.480 +reg [`LM32_WORD_RNG] m_result; // Result of instruction in M stage 45.481 +reg [`LM32_WORD_RNG] w_result; // Result of instruction in W stage 45.482 + 45.483 +reg [`LM32_WORD_RNG] operand_0_x; // Operand 0 for X stage instruction 45.484 +reg [`LM32_WORD_RNG] operand_1_x; // Operand 1 for X stage instruction 45.485 +reg [`LM32_WORD_RNG] store_operand_x; // Data read from register to store 45.486 +reg [`LM32_WORD_RNG] operand_m; // Operand for M stage instruction 45.487 +reg [`LM32_WORD_RNG] operand_w; // Operand for W stage instruction 45.488 + 45.489 +// To/from register file 45.490 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE 45.491 +reg [`LM32_WORD_RNG] reg_data_live_0; 45.492 +reg [`LM32_WORD_RNG] reg_data_live_1; 45.493 +reg use_buf; // Whether to use reg_data_live or reg_data_buf 45.494 +reg [`LM32_WORD_RNG] reg_data_buf_0; 45.495 +reg [`LM32_WORD_RNG] reg_data_buf_1; 45.496 +`endif 45.497 +`ifdef LM32_EBR_REGISTER_FILE 45.498 +`else 45.499 +reg [`LM32_WORD_RNG] registers[0:(1<<`LM32_REG_IDX_WIDTH)-1]; // Register file 45.500 +`endif 45.501 +wire [`LM32_WORD_RNG] reg_data_0; // Register file read port 0 data 45.502 +wire [`LM32_WORD_RNG] reg_data_1; // Register file read port 1 data 45.503 +reg [`LM32_WORD_RNG] bypass_data_0; // Register value 0 after bypassing 45.504 +reg [`LM32_WORD_RNG] bypass_data_1; // Register value 1 after bypassing 45.505 +wire reg_write_enable_q_w; 45.506 + 45.507 +reg interlock; // Indicates pipeline should be stalled because of a read-after-write hazzard 45.508 + 45.509 +wire stall_a; // Stall instruction in A pipeline stage 45.510 +wire stall_f; // Stall instruction in F pipeline stage 45.511 +wire stall_d; // Stall instruction in D pipeline stage 45.512 +wire stall_x; // Stall instruction in X pipeline stage 45.513 +wire stall_m; // Stall instruction in M pipeline stage 45.514 + 45.515 +// To/from adder 45.516 +wire adder_op_d; // Whether to add or subtract 45.517 +reg adder_op_x; 45.518 +reg adder_op_x_n; // Inverted version of adder_op_x 45.519 +wire [`LM32_WORD_RNG] adder_result_x; // Result from adder 45.520 +wire adder_overflow_x; // Whether a signed overflow occured 45.521 +wire adder_carry_n_x; // Whether a carry was generated 45.522 + 45.523 +// To/from logical operations unit 45.524 +wire [`LM32_LOGIC_OP_RNG] logic_op_d; // Which operation to perform 45.525 +reg [`LM32_LOGIC_OP_RNG] logic_op_x; 45.526 +wire [`LM32_WORD_RNG] logic_result_x; // Result of logical operation 45.527 + 45.528 +`ifdef CFG_SIGN_EXTEND_ENABLED 45.529 +// From sign-extension unit 45.530 +wire [`LM32_WORD_RNG] sextb_result_x; // Result of byte sign-extension 45.531 +wire [`LM32_WORD_RNG] sexth_result_x; // Result of half-word sign-extenstion 45.532 +wire [`LM32_WORD_RNG] sext_result_x; // Result of sign-extension specified by instruction 45.533 +`endif 45.534 + 45.535 +// To/from shifter 45.536 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 45.537 +`ifdef CFG_ROTATE_ENABLED 45.538 +wire rotate_d; // Whether we should rotate or shift 45.539 +reg rotate_x; 45.540 +`endif 45.541 +wire direction_d; // Which direction to shift in 45.542 +reg direction_x; 45.543 +wire [`LM32_WORD_RNG] shifter_result_m; // Result of shifter 45.544 +`endif 45.545 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED 45.546 +wire shift_left_d; // Indicates whether to perform a left shift or not 45.547 +wire shift_left_q_d; 45.548 +wire shift_right_d; // Indicates whether to perform a right shift or not 45.549 +wire shift_right_q_d; 45.550 +`endif 45.551 +`ifdef LM32_NO_BARREL_SHIFT 45.552 +wire [`LM32_WORD_RNG] shifter_result_x; // Result of single-bit right shifter 45.553 +`endif 45.554 + 45.555 +// To/from multiplier 45.556 +`ifdef LM32_MULTIPLY_ENABLED 45.557 +wire [`LM32_WORD_RNG] multiplier_result_w; // Result from multiplier 45.558 +`endif 45.559 +`ifdef CFG_MC_MULTIPLY_ENABLED 45.560 +wire multiply_d; // Indicates whether to perform a multiply or not 45.561 +wire multiply_q_d; 45.562 +`endif 45.563 + 45.564 +// To/from divider 45.565 +`ifdef CFG_MC_DIVIDE_ENABLED 45.566 +wire divide_d; // Indicates whether to perform a divider or not 45.567 +wire divide_q_d; 45.568 +wire modulus_d; 45.569 +wire modulus_q_d; 45.570 +wire divide_by_zero_x; // Indicates an attempt was made to divide by zero 45.571 +`endif 45.572 + 45.573 +// To from multi-cycle arithmetic unit 45.574 +`ifdef LM32_MC_ARITHMETIC_ENABLED 45.575 +wire mc_stall_request_x; // Multi-cycle arithmetic unit stall request 45.576 +wire [`LM32_WORD_RNG] mc_result_x; 45.577 +`endif 45.578 + 45.579 +// From CSRs 45.580 +`ifdef CFG_INTERRUPTS_ENABLED 45.581 +wire [`LM32_WORD_RNG] interrupt_csr_read_data_x;// Data read from interrupt CSRs 45.582 +`endif 45.583 +wire [`LM32_WORD_RNG] cfg; // Configuration CSR 45.584 +wire [`LM32_WORD_RNG] cfg2; // Extended Configuration CSR 45.585 +`ifdef CFG_CYCLE_COUNTER_ENABLED 45.586 +reg [`LM32_WORD_RNG] cc; // Cycle counter CSR 45.587 +`endif 45.588 +reg [`LM32_WORD_RNG] csr_read_data_x; // Data read from CSRs 45.589 + 45.590 +// To/from instruction unit 45.591 +wire [`LM32_PC_RNG] pc_f; // PC of instruction in F stage 45.592 +wire [`LM32_PC_RNG] pc_d; // PC of instruction in D stage 45.593 +wire [`LM32_PC_RNG] pc_x; // PC of instruction in X stage 45.594 +wire [`LM32_PC_RNG] pc_m; // PC of instruction in M stage 45.595 +wire [`LM32_PC_RNG] pc_w; // PC of instruction in W stage 45.596 +`ifdef CFG_TRACE_ENABLED 45.597 +reg [`LM32_PC_RNG] pc_c; // PC of last commited instruction 45.598 +`endif 45.599 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE 45.600 +wire [`LM32_INSTRUCTION_RNG] instruction_f; // Instruction in F stage 45.601 +`endif 45.602 +//pragma attribute instruction_d preserve_signal true 45.603 +//pragma attribute instruction_d preserve_driver true 45.604 +wire [`LM32_INSTRUCTION_RNG] instruction_d; // Instruction in D stage 45.605 +`ifdef CFG_ICACHE_ENABLED 45.606 +wire iflush; // Flush instruction cache 45.607 +wire icache_stall_request; // Stall pipeline because instruction cache is busy 45.608 +wire icache_restart_request; // Restart instruction that caused an instruction cache miss 45.609 +wire icache_refill_request; // Request to refill instruction cache 45.610 +wire icache_refilling; // Indicates the instruction cache is being refilled 45.611 +`endif 45.612 +`ifdef CFG_IROM_ENABLED 45.613 +wire [`LM32_WORD_RNG] irom_store_data_m; // Store data to instruction ROM 45.614 +wire [`LM32_WORD_RNG] irom_address_xm; // Address to instruction ROM from load-store unit 45.615 +wire [`LM32_WORD_RNG] irom_data_m; // Load data from instruction ROM 45.616 +wire irom_we_xm; // Indicates data needs to be written to instruction ROM 45.617 +wire irom_stall_request_x; // Indicates D stage needs to be stalled on a store to instruction ROM 45.618 +`endif 45.619 + 45.620 +// To/from load/store unit 45.621 +`ifdef CFG_DCACHE_ENABLED 45.622 +wire dflush_x; // Flush data cache 45.623 +reg dflush_m; 45.624 +wire dcache_stall_request; // Stall pipeline because data cache is busy 45.625 +wire dcache_restart_request; // Restart instruction that caused a data cache miss 45.626 +wire dcache_refill_request; // Request to refill data cache 45.627 +wire dcache_refilling; // Indicates the data cache is being refilled 45.628 +`endif 45.629 +wire [`LM32_WORD_RNG] load_data_w; // Result of a load instruction 45.630 +wire stall_wb_load; // Stall pipeline because of a load via the data Wishbone interface 45.631 + 45.632 +// To/from JTAG interface 45.633 +`ifdef CFG_JTAG_ENABLED 45.634 +`ifdef CFG_JTAG_UART_ENABLED 45.635 +wire [`LM32_WORD_RNG] jtx_csr_read_data; // Read data for JTX CSR 45.636 +wire [`LM32_WORD_RNG] jrx_csr_read_data; // Read data for JRX CSR 45.637 +`endif 45.638 +`ifdef CFG_HW_DEBUG_ENABLED 45.639 +wire jtag_csr_write_enable; // Debugger CSR write enable 45.640 +wire [`LM32_WORD_RNG] jtag_csr_write_data; // Data to write to specified CSR 45.641 +wire [`LM32_CSR_RNG] jtag_csr; // Which CSR to write 45.642 +wire jtag_read_enable; 45.643 +wire [`LM32_BYTE_RNG] jtag_read_data; 45.644 +wire jtag_write_enable; 45.645 +wire [`LM32_BYTE_RNG] jtag_write_data; 45.646 +wire [`LM32_WORD_RNG] jtag_address; 45.647 +wire jtag_access_complete; 45.648 +`endif 45.649 +`ifdef CFG_DEBUG_ENABLED 45.650 +wire jtag_break; // Request from debugger to raise a breakpoint 45.651 +`endif 45.652 +`endif 45.653 + 45.654 +// Hazzard detection 45.655 +wire raw_x_0; // RAW hazzard between instruction in X stage and read port 0 45.656 +wire raw_x_1; // RAW hazzard between instruction in X stage and read port 1 45.657 +wire raw_m_0; // RAW hazzard between instruction in M stage and read port 0 45.658 +wire raw_m_1; // RAW hazzard between instruction in M stage and read port 1 45.659 +wire raw_w_0; // RAW hazzard between instruction in W stage and read port 0 45.660 +wire raw_w_1; // RAW hazzard between instruction in W stage and read port 1 45.661 + 45.662 +// Control flow 45.663 +wire cmp_zero; // Result of comparison is zero 45.664 +wire cmp_negative; // Result of comparison is negative 45.665 +wire cmp_overflow; // Comparison produced an overflow 45.666 +wire cmp_carry_n; // Comparison produced a carry, inverted 45.667 +reg condition_met_x; // Condition of branch instruction is met 45.668 +reg condition_met_m; 45.669 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH 45.670 +wire branch_taken_x; // Branch is taken in X stage 45.671 +`endif 45.672 +wire branch_taken_m; // Branch is taken in M stage 45.673 + 45.674 +wire kill_f; // Kill instruction in F stage 45.675 +wire kill_d; // Kill instruction in D stage 45.676 +wire kill_x; // Kill instruction in X stage 45.677 +wire kill_m; // Kill instruction in M stage 45.678 +wire kill_w; // Kill instruction in W stage 45.679 + 45.680 +reg [`LM32_PC_WIDTH+2-1:8] eba; // Exception Base Address (EBA) CSR 45.681 +`ifdef CFG_DEBUG_ENABLED 45.682 +reg [`LM32_PC_WIDTH+2-1:8] deba; // Debug Exception Base Address (DEBA) CSR 45.683 +`endif 45.684 +reg [`LM32_EID_RNG] eid_x; // Exception ID in X stage 45.685 +`ifdef CFG_TRACE_ENABLED 45.686 +reg [`LM32_EID_RNG] eid_m; // Exception ID in M stage 45.687 +reg [`LM32_EID_RNG] eid_w; // Exception ID in W stage 45.688 +`endif 45.689 + 45.690 +`ifdef CFG_DEBUG_ENABLED 45.691 +`ifdef LM32_SINGLE_STEP_ENABLED 45.692 +wire dc_ss; // Is single-step enabled 45.693 +`endif 45.694 +wire dc_re; // Remap all exceptions 45.695 +wire exception_x; // An exception occured in the X stage 45.696 +reg exception_m; // An instruction that caused an exception is in the M stage 45.697 +wire debug_exception_x; // Indicates if a debug exception has occured 45.698 +reg debug_exception_m; 45.699 +reg debug_exception_w; 45.700 +wire debug_exception_q_w; 45.701 +wire non_debug_exception_x; // Indicates if a non debug exception has occured 45.702 +reg non_debug_exception_m; 45.703 +reg non_debug_exception_w; 45.704 +wire non_debug_exception_q_w; 45.705 +`else 45.706 +wire exception_x; // Indicates if a debug exception has occured 45.707 +reg exception_m; 45.708 +reg exception_w; 45.709 +wire exception_q_w; 45.710 +`endif 45.711 + 45.712 +`ifdef CFG_DEBUG_ENABLED 45.713 +`ifdef CFG_JTAG_ENABLED 45.714 +wire reset_exception; // Indicates if a reset exception has occured 45.715 +`endif 45.716 +`endif 45.717 +`ifdef CFG_INTERRUPTS_ENABLED 45.718 +wire interrupt_exception; // Indicates if an interrupt exception has occured 45.719 +`endif 45.720 +`ifdef CFG_DEBUG_ENABLED 45.721 +wire breakpoint_exception; // Indicates if a breakpoint exception has occured 45.722 +wire watchpoint_exception; // Indicates if a watchpoint exception has occured 45.723 +`endif 45.724 +`ifdef CFG_BUS_ERRORS_ENABLED 45.725 +wire instruction_bus_error_exception; // Indicates if an instruction bus error exception has occured 45.726 +wire data_bus_error_exception; // Indicates if a data bus error exception has occured 45.727 +`endif 45.728 +`ifdef CFG_MC_DIVIDE_ENABLED 45.729 +wire divide_by_zero_exception; // Indicates if a divide by zero exception has occured 45.730 +`endif 45.731 +wire system_call_exception; // Indicates if a system call exception has occured 45.732 + 45.733 +`ifdef CFG_BUS_ERRORS_ENABLED 45.734 +reg data_bus_error_seen; // Indicates if a data bus error was seen 45.735 +`endif 45.736 + 45.737 +///////////////////////////////////////////////////// 45.738 +// Functions 45.739 +///////////////////////////////////////////////////// 45.740 + 45.741 +`include "lm32_functions.v" 45.742 + 45.743 +///////////////////////////////////////////////////// 45.744 +// Instantiations 45.745 +///////////////////////////////////////////////////// 45.746 + 45.747 +// Instruction unit 45.748 +lm32_instruction_unit #( 45.749 + .associativity (icache_associativity), 45.750 + .sets (icache_sets), 45.751 + .bytes_per_line (icache_bytes_per_line), 45.752 + .base_address (icache_base_address), 45.753 + .limit (icache_limit) 45.754 + ) instruction_unit ( 45.755 + // ----- Inputs ------- 45.756 + .clk_i (clk_i), 45.757 + .rst_i (rst_i), 45.758 + // From pipeline 45.759 + .stall_a (stall_a), 45.760 + .stall_f (stall_f), 45.761 + .stall_d (stall_d), 45.762 + .stall_x (stall_x), 45.763 + .stall_m (stall_m), 45.764 + .valid_f (valid_f), 45.765 + .valid_d (valid_d), 45.766 + .kill_f (kill_f), 45.767 + .branch_predict_taken_d (branch_predict_taken_d), 45.768 + .branch_predict_address_d (branch_predict_address_d), 45.769 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH 45.770 + .branch_taken_x (branch_taken_x), 45.771 + .branch_target_x (branch_target_x), 45.772 +`endif 45.773 + .exception_m (exception_m), 45.774 + .branch_taken_m (branch_taken_m), 45.775 + .branch_mispredict_taken_m (branch_mispredict_taken_m), 45.776 + .branch_target_m (branch_target_m), 45.777 +`ifdef CFG_ICACHE_ENABLED 45.778 + .iflush (iflush), 45.779 +`endif 45.780 +`ifdef CFG_IROM_ENABLED 45.781 + .irom_store_data_m (irom_store_data_m), 45.782 + .irom_address_xm (irom_address_xm), 45.783 + .irom_we_xm (irom_we_xm), 45.784 +`endif 45.785 +`ifdef CFG_DCACHE_ENABLED 45.786 + .dcache_restart_request (dcache_restart_request), 45.787 + .dcache_refill_request (dcache_refill_request), 45.788 + .dcache_refilling (dcache_refilling), 45.789 +`endif 45.790 +`ifdef CFG_IWB_ENABLED 45.791 + // From Wishbone 45.792 + .i_dat_i (I_DAT_I), 45.793 + .i_ack_i (I_ACK_I), 45.794 + .i_err_i (I_ERR_I), 45.795 +`endif 45.796 +`ifdef CFG_HW_DEBUG_ENABLED 45.797 + .jtag_read_enable (jtag_read_enable), 45.798 + .jtag_write_enable (jtag_write_enable), 45.799 + .jtag_write_data (jtag_write_data), 45.800 + .jtag_address (jtag_address), 45.801 +`endif 45.802 + // ----- Outputs ------- 45.803 + // To pipeline 45.804 + .pc_f (pc_f), 45.805 + .pc_d (pc_d), 45.806 + .pc_x (pc_x), 45.807 + .pc_m (pc_m), 45.808 + .pc_w (pc_w), 45.809 +`ifdef CFG_ICACHE_ENABLED 45.810 + .icache_stall_request (icache_stall_request), 45.811 + .icache_restart_request (icache_restart_request), 45.812 + .icache_refill_request (icache_refill_request), 45.813 + .icache_refilling (icache_refilling), 45.814 +`endif 45.815 +`ifdef CFG_IROM_ENABLED 45.816 + .irom_data_m (irom_data_m), 45.817 +`endif 45.818 +`ifdef CFG_IWB_ENABLED 45.819 + // To Wishbone 45.820 + .i_dat_o (I_DAT_O), 45.821 + .i_adr_o (I_ADR_O), 45.822 + .i_cyc_o (I_CYC_O), 45.823 + .i_sel_o (I_SEL_O), 45.824 + .i_stb_o (I_STB_O), 45.825 + .i_we_o (I_WE_O), 45.826 + .i_cti_o (I_CTI_O), 45.827 + .i_lock_o (I_LOCK_O), 45.828 + .i_bte_o (I_BTE_O), 45.829 +`endif 45.830 +`ifdef CFG_HW_DEBUG_ENABLED 45.831 + .jtag_read_data (jtag_read_data), 45.832 + .jtag_access_complete (jtag_access_complete), 45.833 +`endif 45.834 +`ifdef CFG_BUS_ERRORS_ENABLED 45.835 + .bus_error_d (bus_error_d), 45.836 +`endif 45.837 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE 45.838 + .instruction_f (instruction_f), 45.839 +`endif 45.840 + .instruction_d (instruction_d) 45.841 + ); 45.842 + 45.843 +// Instruction decoder 45.844 +lm32_decoder decoder ( 45.845 + // ----- Inputs ------- 45.846 + .instruction (instruction_d), 45.847 + // ----- Outputs ------- 45.848 + .d_result_sel_0 (d_result_sel_0_d), 45.849 + .d_result_sel_1 (d_result_sel_1_d), 45.850 + .x_result_sel_csr (x_result_sel_csr_d), 45.851 +`ifdef LM32_MC_ARITHMETIC_ENABLED 45.852 + .x_result_sel_mc_arith (x_result_sel_mc_arith_d), 45.853 +`endif 45.854 +`ifdef LM32_NO_BARREL_SHIFT 45.855 + .x_result_sel_shift (x_result_sel_shift_d), 45.856 +`endif 45.857 +`ifdef CFG_SIGN_EXTEND_ENABLED 45.858 + .x_result_sel_sext (x_result_sel_sext_d), 45.859 +`endif 45.860 + .x_result_sel_logic (x_result_sel_logic_d), 45.861 +`ifdef CFG_USER_ENABLED 45.862 + .x_result_sel_user (x_result_sel_user_d), 45.863 +`endif 45.864 + .x_result_sel_add (x_result_sel_add_d), 45.865 + .m_result_sel_compare (m_result_sel_compare_d), 45.866 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 45.867 + .m_result_sel_shift (m_result_sel_shift_d), 45.868 +`endif 45.869 + .w_result_sel_load (w_result_sel_load_d), 45.870 +`ifdef CFG_PL_MULTIPLY_ENABLED 45.871 + .w_result_sel_mul (w_result_sel_mul_d), 45.872 +`endif 45.873 + .x_bypass_enable (x_bypass_enable_d), 45.874 + .m_bypass_enable (m_bypass_enable_d), 45.875 + .read_enable_0 (read_enable_0_d), 45.876 + .read_idx_0 (read_idx_0_d), 45.877 + .read_enable_1 (read_enable_1_d), 45.878 + .read_idx_1 (read_idx_1_d), 45.879 + .write_enable (write_enable_d), 45.880 + .write_idx (write_idx_d), 45.881 + .immediate (immediate_d), 45.882 + .branch_offset (branch_offset_d), 45.883 + .load (load_d), 45.884 + .store (store_d), 45.885 + .size (size_d), 45.886 + .sign_extend (sign_extend_d), 45.887 + .adder_op (adder_op_d), 45.888 + .logic_op (logic_op_d), 45.889 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 45.890 + .direction (direction_d), 45.891 +`endif 45.892 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED 45.893 + .shift_left (shift_left_d), 45.894 + .shift_right (shift_right_d), 45.895 +`endif 45.896 +`ifdef CFG_MC_MULTIPLY_ENABLED 45.897 + .multiply (multiply_d), 45.898 +`endif 45.899 +`ifdef CFG_MC_DIVIDE_ENABLED 45.900 + .divide (divide_d), 45.901 + .modulus (modulus_d), 45.902 +`endif 45.903 + .branch (branch_d), 45.904 + .bi_unconditional (bi_unconditional), 45.905 + .bi_conditional (bi_conditional), 45.906 + .branch_reg (branch_reg_d), 45.907 + .condition (condition_d), 45.908 +`ifdef CFG_DEBUG_ENABLED 45.909 + .break_opcode (break_d), 45.910 +`endif 45.911 + .scall (scall_d), 45.912 + .eret (eret_d), 45.913 +`ifdef CFG_DEBUG_ENABLED 45.914 + .bret (bret_d), 45.915 +`endif 45.916 +`ifdef CFG_USER_ENABLED 45.917 + .user_opcode (user_opcode_d), 45.918 +`endif 45.919 + .csr_write_enable (csr_write_enable_d) 45.920 + ); 45.921 + 45.922 +// Load/store unit 45.923 +lm32_load_store_unit #( 45.924 + .associativity (dcache_associativity), 45.925 + .sets (dcache_sets), 45.926 + .bytes_per_line (dcache_bytes_per_line), 45.927 + .base_address (dcache_base_address), 45.928 + .limit (dcache_limit) 45.929 + ) load_store_unit ( 45.930 + // ----- Inputs ------- 45.931 + .clk_i (clk_i), 45.932 + .rst_i (rst_i), 45.933 + // From pipeline 45.934 + .stall_a (stall_a), 45.935 + .stall_x (stall_x), 45.936 + .stall_m (stall_m), 45.937 + .kill_m (kill_m), 45.938 + .exception_m (exception_m), 45.939 + .store_operand_x (store_operand_x), 45.940 + .load_store_address_x (adder_result_x), 45.941 + .load_store_address_m (operand_m), 45.942 + .load_store_address_w (operand_w[1:0]), 45.943 + .load_x (load_x), 45.944 + .store_x (store_x), 45.945 + .load_q_x (load_q_x), 45.946 + .store_q_x (store_q_x), 45.947 + .load_q_m (load_q_m), 45.948 + .store_q_m (store_q_m), 45.949 + .sign_extend_x (sign_extend_x), 45.950 + .size_x (size_x), 45.951 +`ifdef CFG_DCACHE_ENABLED 45.952 + .dflush (dflush_m), 45.953 +`endif 45.954 +`ifdef CFG_IROM_ENABLED 45.955 + .irom_data_m (irom_data_m), 45.956 +`endif 45.957 + // From Wishbone 45.958 + .d_dat_i (D_DAT_I), 45.959 + .d_ack_i (D_ACK_I), 45.960 + .d_err_i (D_ERR_I), 45.961 + .d_rty_i (D_RTY_I), 45.962 + // ----- Outputs ------- 45.963 + // To pipeline 45.964 +`ifdef CFG_DCACHE_ENABLED 45.965 + .dcache_refill_request (dcache_refill_request), 45.966 + .dcache_restart_request (dcache_restart_request), 45.967 + .dcache_stall_request (dcache_stall_request), 45.968 + .dcache_refilling (dcache_refilling), 45.969 +`endif 45.970 +`ifdef CFG_IROM_ENABLED 45.971 + .irom_store_data_m (irom_store_data_m), 45.972 + .irom_address_xm (irom_address_xm), 45.973 + .irom_we_xm (irom_we_xm), 45.974 + .irom_stall_request_x (irom_stall_request_x), 45.975 +`endif 45.976 + .load_data_w (load_data_w), 45.977 + .stall_wb_load (stall_wb_load), 45.978 + // To Wishbone 45.979 + .d_dat_o (D_DAT_O), 45.980 + .d_adr_o (D_ADR_O), 45.981 + .d_cyc_o (D_CYC_O), 45.982 + .d_sel_o (D_SEL_O), 45.983 + .d_stb_o (D_STB_O), 45.984 + .d_we_o (D_WE_O), 45.985 + .d_cti_o (D_CTI_O), 45.986 + .d_lock_o (D_LOCK_O), 45.987 + .d_bte_o (D_BTE_O) 45.988 + ); 45.989 + 45.990 +// Adder 45.991 +lm32_adder adder ( 45.992 + // ----- Inputs ------- 45.993 + .adder_op_x (adder_op_x), 45.994 + .adder_op_x_n (adder_op_x_n), 45.995 + .operand_0_x (operand_0_x), 45.996 + .operand_1_x (operand_1_x), 45.997 + // ----- Outputs ------- 45.998 + .adder_result_x (adder_result_x), 45.999 + .adder_carry_n_x (adder_carry_n_x), 45.1000 + .adder_overflow_x (adder_overflow_x) 45.1001 + ); 45.1002 + 45.1003 +// Logic operations 45.1004 +lm32_logic_op logic_op ( 45.1005 + // ----- Inputs ------- 45.1006 + .logic_op_x (logic_op_x), 45.1007 + .operand_0_x (operand_0_x), 45.1008 + 45.1009 + .operand_1_x (operand_1_x), 45.1010 + // ----- Outputs ------- 45.1011 + .logic_result_x (logic_result_x) 45.1012 + ); 45.1013 + 45.1014 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 45.1015 +// Pipelined barrel-shifter 45.1016 +lm32_shifter shifter ( 45.1017 + // ----- Inputs ------- 45.1018 + .clk_i (clk_i), 45.1019 + .rst_i (rst_i), 45.1020 + .stall_x (stall_x), 45.1021 + .direction_x (direction_x), 45.1022 + .sign_extend_x (sign_extend_x), 45.1023 + .operand_0_x (operand_0_x), 45.1024 + .operand_1_x (operand_1_x), 45.1025 + // ----- Outputs ------- 45.1026 + .shifter_result_m (shifter_result_m) 45.1027 + ); 45.1028 +`endif 45.1029 + 45.1030 +`ifdef CFG_PL_MULTIPLY_ENABLED 45.1031 +// Pipeline fixed-point multiplier 45.1032 +lm32_multiplier multiplier ( 45.1033 + // ----- Inputs ------- 45.1034 + .clk_i (clk_i), 45.1035 + .rst_i (rst_i), 45.1036 + .stall_x (stall_x), 45.1037 + .stall_m (stall_m), 45.1038 + .operand_0 (d_result_0), 45.1039 + .operand_1 (d_result_1), 45.1040 + // ----- Outputs ------- 45.1041 + .result (multiplier_result_w) 45.1042 + ); 45.1043 +`endif 45.1044 + 45.1045 +`ifdef LM32_MC_ARITHMETIC_ENABLED 45.1046 +// Multi-cycle arithmetic 45.1047 +lm32_mc_arithmetic mc_arithmetic ( 45.1048 + // ----- Inputs ------- 45.1049 + .clk_i (clk_i), 45.1050 + .rst_i (rst_i), 45.1051 + .stall_d (stall_d), 45.1052 + .kill_x (kill_x), 45.1053 +`ifdef CFG_MC_DIVIDE_ENABLED 45.1054 + .divide_d (divide_q_d), 45.1055 + .modulus_d (modulus_q_d), 45.1056 +`endif 45.1057 +`ifdef CFG_MC_MULTIPLY_ENABLED 45.1058 + .multiply_d (multiply_q_d), 45.1059 +`endif 45.1060 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED 45.1061 + .shift_left_d (shift_left_q_d), 45.1062 + .shift_right_d (shift_right_q_d), 45.1063 + .sign_extend_d (sign_extend_d), 45.1064 +`endif 45.1065 + .operand_0_d (d_result_0), 45.1066 + .operand_1_d (d_result_1), 45.1067 + // ----- Outputs ------- 45.1068 + .result_x (mc_result_x), 45.1069 +`ifdef CFG_MC_DIVIDE_ENABLED 45.1070 + .divide_by_zero_x (divide_by_zero_x), 45.1071 +`endif 45.1072 + .stall_request_x (mc_stall_request_x) 45.1073 + ); 45.1074 +`endif 45.1075 + 45.1076 +`ifdef CFG_INTERRUPTS_ENABLED 45.1077 +// Interrupt unit 45.1078 +lm32_interrupt interrupt_unit ( 45.1079 + // ----- Inputs ------- 45.1080 + .clk_i (clk_i), 45.1081 + .rst_i (rst_i), 45.1082 + // From external devices 45.1083 + .interrupt (interrupt), 45.1084 + // From pipeline 45.1085 + .stall_x (stall_x), 45.1086 +`ifdef CFG_DEBUG_ENABLED 45.1087 + .non_debug_exception (non_debug_exception_q_w), 45.1088 + .debug_exception (debug_exception_q_w), 45.1089 +`else 45.1090 + .exception (exception_q_w), 45.1091 +`endif 45.1092 + .eret_q_x (eret_q_x), 45.1093 +`ifdef CFG_DEBUG_ENABLED 45.1094 + .bret_q_x (bret_q_x), 45.1095 +`endif 45.1096 + .csr (csr_x), 45.1097 + .csr_write_data (operand_1_x), 45.1098 + .csr_write_enable (csr_write_enable_q_x), 45.1099 + // ----- Outputs ------- 45.1100 + .interrupt_exception (interrupt_exception), 45.1101 + // To pipeline 45.1102 + .csr_read_data (interrupt_csr_read_data_x) 45.1103 + ); 45.1104 +`endif 45.1105 + 45.1106 +`ifdef CFG_JTAG_ENABLED 45.1107 +// JTAG interface 45.1108 +lm32_jtag jtag ( 45.1109 + // ----- Inputs ------- 45.1110 + .clk_i (clk_i), 45.1111 + .rst_i (rst_i), 45.1112 + // From JTAG 45.1113 + .jtag_clk (jtag_clk), 45.1114 + .jtag_update (jtag_update), 45.1115 + .jtag_reg_q (jtag_reg_q), 45.1116 + .jtag_reg_addr_q (jtag_reg_addr_q), 45.1117 + // From pipeline 45.1118 +`ifdef CFG_JTAG_UART_ENABLED 45.1119 + .csr (csr_x), 45.1120 + .csr_write_data (operand_1_x), 45.1121 + .csr_write_enable (csr_write_enable_q_x), 45.1122 + .stall_x (stall_x), 45.1123 +`endif 45.1124 +`ifdef CFG_HW_DEBUG_ENABLED 45.1125 + .jtag_read_data (jtag_read_data), 45.1126 + .jtag_access_complete (jtag_access_complete), 45.1127 +`endif 45.1128 +`ifdef CFG_DEBUG_ENABLED 45.1129 + .exception_q_w (debug_exception_q_w || non_debug_exception_q_w), 45.1130 +`endif 45.1131 + // ----- Outputs ------- 45.1132 + // To pipeline 45.1133 +`ifdef CFG_JTAG_UART_ENABLED 45.1134 + .jtx_csr_read_data (jtx_csr_read_data), 45.1135 + .jrx_csr_read_data (jrx_csr_read_data), 45.1136 +`endif 45.1137 +`ifdef CFG_HW_DEBUG_ENABLED 45.1138 + .jtag_csr_write_enable (jtag_csr_write_enable), 45.1139 + .jtag_csr_write_data (jtag_csr_write_data), 45.1140 + .jtag_csr (jtag_csr), 45.1141 + .jtag_read_enable (jtag_read_enable), 45.1142 + .jtag_write_enable (jtag_write_enable), 45.1143 + .jtag_write_data (jtag_write_data), 45.1144 + .jtag_address (jtag_address), 45.1145 +`endif 45.1146 +`ifdef CFG_DEBUG_ENABLED 45.1147 + .jtag_break (jtag_break), 45.1148 + .jtag_reset (reset_exception), 45.1149 +`endif 45.1150 + // To JTAG 45.1151 + .jtag_reg_d (jtag_reg_d), 45.1152 + .jtag_reg_addr_d (jtag_reg_addr_d) 45.1153 + ); 45.1154 +`endif 45.1155 + 45.1156 +`ifdef CFG_DEBUG_ENABLED 45.1157 +// Debug unit 45.1158 +lm32_debug #( 45.1159 + .breakpoints (breakpoints), 45.1160 + .watchpoints (watchpoints) 45.1161 + ) hw_debug ( 45.1162 + // ----- Inputs ------- 45.1163 + .clk_i (clk_i), 45.1164 + .rst_i (rst_i), 45.1165 + .pc_x (pc_x), 45.1166 + .load_x (load_x), 45.1167 + .store_x (store_x), 45.1168 + .load_store_address_x (adder_result_x), 45.1169 + .csr_write_enable_x (csr_write_enable_q_x), 45.1170 + .csr_write_data (operand_1_x), 45.1171 + .csr_x (csr_x), 45.1172 +`ifdef CFG_HW_DEBUG_ENABLED 45.1173 + .jtag_csr_write_enable (jtag_csr_write_enable), 45.1174 + .jtag_csr_write_data (jtag_csr_write_data), 45.1175 + .jtag_csr (jtag_csr), 45.1176 +`endif 45.1177 +`ifdef LM32_SINGLE_STEP_ENABLED 45.1178 + .eret_q_x (eret_q_x), 45.1179 + .bret_q_x (bret_q_x), 45.1180 + .stall_x (stall_x), 45.1181 + .exception_x (exception_x), 45.1182 + .q_x (q_x), 45.1183 +`ifdef CFG_DCACHE_ENABLED 45.1184 + .dcache_refill_request (dcache_refill_request), 45.1185 +`endif 45.1186 +`endif 45.1187 + // ----- Outputs ------- 45.1188 +`ifdef LM32_SINGLE_STEP_ENABLED 45.1189 + .dc_ss (dc_ss), 45.1190 +`endif 45.1191 + .dc_re (dc_re), 45.1192 + .bp_match (bp_match), 45.1193 + .wp_match (wp_match) 45.1194 + ); 45.1195 +`endif 45.1196 + 45.1197 +// Register file 45.1198 + 45.1199 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE 45.1200 + /*---------------------------------------------------------------------- 45.1201 + Register File is implemented using EBRs. There can be three accesses to 45.1202 + the register file in each cycle: two reads and one write. On-chip block 45.1203 + RAM has two read/write ports. To accomodate three accesses, two on-chip 45.1204 + block RAMs are used (each register file "write" is made to both block 45.1205 + RAMs). 45.1206 + 45.1207 + One limitation of the on-chip block RAMs is that one cannot perform a 45.1208 + read and write to same location in a cycle (if this is done, then the 45.1209 + data read out is indeterminate). 45.1210 + ----------------------------------------------------------------------*/ 45.1211 + wire [31:0] regfile_data_0, regfile_data_1; 45.1212 + reg [31:0] w_result_d; 45.1213 + reg regfile_raw_0, regfile_raw_0_nxt; 45.1214 + reg regfile_raw_1, regfile_raw_1_nxt; 45.1215 + 45.1216 + /*---------------------------------------------------------------------- 45.1217 + Check if read and write is being performed to same register in current 45.1218 + cycle? This is done by comparing the read and write IDXs. 45.1219 + ----------------------------------------------------------------------*/ 45.1220 + always @(reg_write_enable_q_w or write_idx_w or instruction_f) 45.1221 + begin 45.1222 + if (reg_write_enable_q_w 45.1223 + && (write_idx_w == instruction_f[25:21])) 45.1224 + regfile_raw_0_nxt = 1'b1; 45.1225 + else 45.1226 + regfile_raw_0_nxt = 1'b0; 45.1227 + 45.1228 + if (reg_write_enable_q_w 45.1229 + && (write_idx_w == instruction_f[20:16])) 45.1230 + regfile_raw_1_nxt = 1'b1; 45.1231 + else 45.1232 + regfile_raw_1_nxt = 1'b0; 45.1233 + end 45.1234 + 45.1235 + /*---------------------------------------------------------------------- 45.1236 + Select latched (delayed) write value or data from register file. If 45.1237 + read in previous cycle was performed to register written to in same 45.1238 + cycle, then latched (delayed) write value is selected. 45.1239 + ----------------------------------------------------------------------*/ 45.1240 + always @(regfile_raw_0 or w_result_d or regfile_data_0) 45.1241 + if (regfile_raw_0) 45.1242 + reg_data_live_0 = w_result_d; 45.1243 + else 45.1244 + reg_data_live_0 = regfile_data_0; 45.1245 + 45.1246 + /*---------------------------------------------------------------------- 45.1247 + Select latched (delayed) write value or data from register file. If 45.1248 + read in previous cycle was performed to register written to in same 45.1249 + cycle, then latched (delayed) write value is selected. 45.1250 + ----------------------------------------------------------------------*/ 45.1251 + always @(regfile_raw_1 or w_result_d or regfile_data_1) 45.1252 + if (regfile_raw_1) 45.1253 + reg_data_live_1 = w_result_d; 45.1254 + else 45.1255 + reg_data_live_1 = regfile_data_1; 45.1256 + 45.1257 + /*---------------------------------------------------------------------- 45.1258 + Latch value written to register file 45.1259 + ----------------------------------------------------------------------*/ 45.1260 + always @(posedge clk_i `CFG_RESET_SENSITIVITY) 45.1261 + if (rst_i == `TRUE) 45.1262 + begin 45.1263 + regfile_raw_0 <= 1'b0; 45.1264 + regfile_raw_1 <= 1'b0; 45.1265 + w_result_d <= 32'b0; 45.1266 + end 45.1267 + else 45.1268 + begin 45.1269 + regfile_raw_0 <= regfile_raw_0_nxt; 45.1270 + regfile_raw_1 <= regfile_raw_1_nxt; 45.1271 + w_result_d <= w_result; 45.1272 + end 45.1273 + 45.1274 + /*---------------------------------------------------------------------- 45.1275 + Register file instantiation as Pseudo-Dual Port EBRs. 45.1276 + ----------------------------------------------------------------------*/ 45.1277 + // Modified by GSI: removed non-portable RAM instantiation 45.1278 + lm32_dp_ram 45.1279 + #( 45.1280 + // ----- Parameters ----- 45.1281 + .addr_depth(1<<5), 45.1282 + .addr_width(5), 45.1283 + .data_width(32) 45.1284 + ) 45.1285 + reg_0 45.1286 + ( 45.1287 + // ----- Inputs ----- 45.1288 + .clk_i (clk_i), 45.1289 + .rst_i (rst_i), 45.1290 + .we_i (reg_write_enable_q_w), 45.1291 + .wdata_i (w_result), 45.1292 + .waddr_i (write_idx_w), 45.1293 + .raddr_i (instruction_f[25:21]), 45.1294 + // ----- Outputs ----- 45.1295 + .rdata_o (regfile_data_0) 45.1296 + ); 45.1297 + 45.1298 + lm32_dp_ram 45.1299 + #( 45.1300 + .addr_depth(1<<5), 45.1301 + .addr_width(5), 45.1302 + .data_width(32) 45.1303 + ) 45.1304 + reg_1 45.1305 + ( 45.1306 + // ----- Inputs ----- 45.1307 + .clk_i (clk_i), 45.1308 + .rst_i (rst_i), 45.1309 + .we_i (reg_write_enable_q_w), 45.1310 + .wdata_i (w_result), 45.1311 + .waddr_i (write_idx_w), 45.1312 + .raddr_i (instruction_f[20:16]), 45.1313 + // ----- Outputs ----- 45.1314 + .rdata_o (regfile_data_1) 45.1315 + ); 45.1316 +`endif 45.1317 + 45.1318 +`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE 45.1319 + pmi_ram_dp 45.1320 + #( 45.1321 + // ----- Parameters ----- 45.1322 + .pmi_wr_addr_depth(1<<5), 45.1323 + .pmi_wr_addr_width(5), 45.1324 + .pmi_wr_data_width(32), 45.1325 + .pmi_rd_addr_depth(1<<5), 45.1326 + .pmi_rd_addr_width(5), 45.1327 + .pmi_rd_data_width(32), 45.1328 + .pmi_regmode("noreg"), 45.1329 + .pmi_gsr("enable"), 45.1330 + .pmi_resetmode("sync"), 45.1331 + .pmi_init_file("none"), 45.1332 + .pmi_init_file_format("binary"), 45.1333 + .pmi_family(`LATTICE_FAMILY), 45.1334 + .module_type("pmi_ram_dp") 45.1335 + ) 45.1336 + reg_0 45.1337 + ( 45.1338 + // ----- Inputs ----- 45.1339 + .Data(w_result), 45.1340 + .WrAddress(write_idx_w), 45.1341 + .RdAddress(read_idx_0_d), 45.1342 + .WrClock(clk_i), 45.1343 + .RdClock(clk_n_i), 45.1344 + .WrClockEn(`TRUE), 45.1345 + .RdClockEn(stall_f == `FALSE), 45.1346 + .WE(reg_write_enable_q_w), 45.1347 + .Reset(rst_i), 45.1348 + // ----- Outputs ----- 45.1349 + .Q(reg_data_0) 45.1350 + ); 45.1351 + 45.1352 + pmi_ram_dp 45.1353 + #( 45.1354 + // ----- Parameters ----- 45.1355 + .pmi_wr_addr_depth(1<<5), 45.1356 + .pmi_wr_addr_width(5), 45.1357 + .pmi_wr_data_width(32), 45.1358 + .pmi_rd_addr_depth(1<<5), 45.1359 + .pmi_rd_addr_width(5), 45.1360 + .pmi_rd_data_width(32), 45.1361 + .pmi_regmode("noreg"), 45.1362 + .pmi_gsr("enable"), 45.1363 + .pmi_resetmode("sync"), 45.1364 + .pmi_init_file("none"), 45.1365 + .pmi_init_file_format("binary"), 45.1366 + .pmi_family(`LATTICE_FAMILY), 45.1367 + .module_type("pmi_ram_dp") 45.1368 + ) 45.1369 + reg_1 45.1370 + ( 45.1371 + // ----- Inputs ----- 45.1372 + .Data(w_result), 45.1373 + .WrAddress(write_idx_w), 45.1374 + .RdAddress(read_idx_1_d), 45.1375 + .WrClock(clk_i), 45.1376 + .RdClock(clk_n_i), 45.1377 + .WrClockEn(`TRUE), 45.1378 + .RdClockEn(stall_f == `FALSE), 45.1379 + .WE(reg_write_enable_q_w), 45.1380 + .Reset(rst_i), 45.1381 + // ----- Outputs ----- 45.1382 + .Q(reg_data_1) 45.1383 + ); 45.1384 +`endif 45.1385 + 45.1386 + 45.1387 +///////////////////////////////////////////////////// 45.1388 +// Combinational Logic 45.1389 +///////////////////////////////////////////////////// 45.1390 + 45.1391 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE 45.1392 +// Select between buffered and live data from register file 45.1393 +assign reg_data_0 = use_buf ? reg_data_buf_0 : reg_data_live_0; 45.1394 +assign reg_data_1 = use_buf ? reg_data_buf_1 : reg_data_live_1; 45.1395 +`endif 45.1396 +`ifdef LM32_EBR_REGISTER_FILE 45.1397 +`else 45.1398 +// Register file read ports 45.1399 +assign reg_data_0 = registers[read_idx_0_d]; 45.1400 +assign reg_data_1 = registers[read_idx_1_d]; 45.1401 +`endif 45.1402 + 45.1403 +// Detect read-after-write hazzards 45.1404 +assign raw_x_0 = (write_idx_x == read_idx_0_d) && (write_enable_q_x == `TRUE); 45.1405 +assign raw_m_0 = (write_idx_m == read_idx_0_d) && (write_enable_q_m == `TRUE); 45.1406 +assign raw_w_0 = (write_idx_w == read_idx_0_d) && (write_enable_q_w == `TRUE); 45.1407 +assign raw_x_1 = (write_idx_x == read_idx_1_d) && (write_enable_q_x == `TRUE); 45.1408 +assign raw_m_1 = (write_idx_m == read_idx_1_d) && (write_enable_q_m == `TRUE); 45.1409 +assign raw_w_1 = (write_idx_w == read_idx_1_d) && (write_enable_q_w == `TRUE); 45.1410 + 45.1411 +// Interlock detection - Raise an interlock for RAW hazzards 45.1412 +always @(*) 45.1413 +begin 45.1414 + if ( ( (x_bypass_enable_x == `FALSE) 45.1415 + && ( ((read_enable_0_d == `TRUE) && (raw_x_0 == `TRUE)) 45.1416 + || ((read_enable_1_d == `TRUE) && (raw_x_1 == `TRUE)) 45.1417 + ) 45.1418 + ) 45.1419 + || ( (m_bypass_enable_m == `FALSE) 45.1420 + && ( ((read_enable_0_d == `TRUE) && (raw_m_0 == `TRUE)) 45.1421 + || ((read_enable_1_d == `TRUE) && (raw_m_1 == `TRUE)) 45.1422 + ) 45.1423 + ) 45.1424 + ) 45.1425 + interlock = `TRUE; 45.1426 + else 45.1427 + interlock = `FALSE; 45.1428 +end 45.1429 + 45.1430 +// Bypass for reg port 0 45.1431 +always @(*) 45.1432 +begin 45.1433 + if (raw_x_0 == `TRUE) 45.1434 + bypass_data_0 = x_result; 45.1435 + else if (raw_m_0 == `TRUE) 45.1436 + bypass_data_0 = m_result; 45.1437 + else if (raw_w_0 == `TRUE) 45.1438 + bypass_data_0 = w_result; 45.1439 + else 45.1440 + bypass_data_0 = reg_data_0; 45.1441 +end 45.1442 + 45.1443 +// Bypass for reg port 1 45.1444 +always @(*) 45.1445 +begin 45.1446 + if (raw_x_1 == `TRUE) 45.1447 + bypass_data_1 = x_result; 45.1448 + else if (raw_m_1 == `TRUE) 45.1449 + bypass_data_1 = m_result; 45.1450 + else if (raw_w_1 == `TRUE) 45.1451 + bypass_data_1 = w_result; 45.1452 + else 45.1453 + bypass_data_1 = reg_data_1; 45.1454 +end 45.1455 + 45.1456 + /*---------------------------------------------------------------------- 45.1457 + Branch prediction is performed in D stage of pipeline. Only PC-relative 45.1458 + branches are predicted: forward-pointing conditional branches are not- 45.1459 + taken, while backward-pointing conditional branches are taken. 45.1460 + Unconditional branches are always predicted taken! 45.1461 + ----------------------------------------------------------------------*/ 45.1462 + assign branch_predict_d = bi_unconditional | bi_conditional; 45.1463 + assign branch_predict_taken_d = bi_unconditional ? 1'b1 : (bi_conditional ? instruction_d[15] : 1'b0); 45.1464 + 45.1465 + // Compute branch target address: Branch PC PLUS Offset 45.1466 + assign branch_target_d = pc_d + branch_offset_d; 45.1467 + 45.1468 + // Compute fetch address. Address of instruction sequentially after the 45.1469 + // branch if branch is not taken. Target address of branch is branch is 45.1470 + // taken 45.1471 + assign branch_predict_address_d = branch_predict_taken_d ? branch_target_d : pc_f; 45.1472 + 45.1473 +// D stage result selection 45.1474 +always @(*) 45.1475 +begin 45.1476 + d_result_0 = d_result_sel_0_d[0] ? {pc_f, 2'b00} : bypass_data_0; 45.1477 + case (d_result_sel_1_d) 45.1478 + `LM32_D_RESULT_SEL_1_ZERO: d_result_1 = {`LM32_WORD_WIDTH{1'b0}}; 45.1479 + `LM32_D_RESULT_SEL_1_REG_1: d_result_1 = bypass_data_1; 45.1480 + `LM32_D_RESULT_SEL_1_IMMEDIATE: d_result_1 = immediate_d; 45.1481 + default: d_result_1 = {`LM32_WORD_WIDTH{1'bx}}; 45.1482 + endcase 45.1483 +end 45.1484 + 45.1485 +`ifdef CFG_USER_ENABLED 45.1486 +// Operands for user-defined instructions 45.1487 +assign user_operand_0 = operand_0_x; 45.1488 +assign user_operand_1 = operand_1_x; 45.1489 +`endif 45.1490 + 45.1491 +`ifdef CFG_SIGN_EXTEND_ENABLED 45.1492 +// Sign-extension 45.1493 +assign sextb_result_x = {{24{operand_0_x[7]}}, operand_0_x[7:0]}; 45.1494 +assign sexth_result_x = {{16{operand_0_x[15]}}, operand_0_x[15:0]}; 45.1495 +assign sext_result_x = size_x == `LM32_SIZE_BYTE ? sextb_result_x : sexth_result_x; 45.1496 +`endif 45.1497 + 45.1498 +`ifdef LM32_NO_BARREL_SHIFT 45.1499 +// Only single bit shift operations are supported when barrel-shifter isn't implemented 45.1500 +assign shifter_result_x = {operand_0_x[`LM32_WORD_WIDTH-1] & sign_extend_x, operand_0_x[`LM32_WORD_WIDTH-1:1]}; 45.1501 +`endif 45.1502 + 45.1503 +// Condition evaluation 45.1504 +assign cmp_zero = operand_0_x == operand_1_x; 45.1505 +assign cmp_negative = adder_result_x[`LM32_WORD_WIDTH-1]; 45.1506 +assign cmp_overflow = adder_overflow_x; 45.1507 +assign cmp_carry_n = adder_carry_n_x; 45.1508 +always @(*) 45.1509 +begin 45.1510 + case (condition_x) 45.1511 + `LM32_CONDITION_U1: condition_met_x = `TRUE; 45.1512 + `LM32_CONDITION_U2: condition_met_x = `TRUE; 45.1513 + `LM32_CONDITION_E: condition_met_x = cmp_zero; 45.1514 + `LM32_CONDITION_NE: condition_met_x = !cmp_zero; 45.1515 + `LM32_CONDITION_G: condition_met_x = !cmp_zero && (cmp_negative == cmp_overflow); 45.1516 + `LM32_CONDITION_GU: condition_met_x = cmp_carry_n && !cmp_zero; 45.1517 + `LM32_CONDITION_GE: condition_met_x = cmp_negative == cmp_overflow; 45.1518 + `LM32_CONDITION_GEU: condition_met_x = cmp_carry_n; 45.1519 + default: condition_met_x = 1'bx; 45.1520 + endcase 45.1521 +end 45.1522 + 45.1523 +// X stage result selection 45.1524 +always @(*) 45.1525 +begin 45.1526 + x_result = x_result_sel_add_x ? adder_result_x 45.1527 + : x_result_sel_csr_x ? csr_read_data_x 45.1528 +`ifdef CFG_SIGN_EXTEND_ENABLED 45.1529 + : x_result_sel_sext_x ? sext_result_x 45.1530 +`endif 45.1531 +`ifdef CFG_USER_ENABLED 45.1532 + : x_result_sel_user_x ? user_result 45.1533 +`endif 45.1534 +`ifdef LM32_NO_BARREL_SHIFT 45.1535 + : x_result_sel_shift_x ? shifter_result_x 45.1536 +`endif 45.1537 +`ifdef LM32_MC_ARITHMETIC_ENABLED 45.1538 + : x_result_sel_mc_arith_x ? mc_result_x 45.1539 +`endif 45.1540 + : logic_result_x; 45.1541 +end 45.1542 + 45.1543 +// M stage result selection 45.1544 +always @(*) 45.1545 +begin 45.1546 + m_result = m_result_sel_compare_m ? {{`LM32_WORD_WIDTH-1{1'b0}}, condition_met_m} 45.1547 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 45.1548 + : m_result_sel_shift_m ? shifter_result_m 45.1549 +`endif 45.1550 + : operand_m; 45.1551 +end 45.1552 + 45.1553 +// W stage result selection 45.1554 +always @(*) 45.1555 +begin 45.1556 + w_result = w_result_sel_load_w ? load_data_w 45.1557 +`ifdef CFG_PL_MULTIPLY_ENABLED 45.1558 + : w_result_sel_mul_w ? multiplier_result_w 45.1559 +`endif 45.1560 + : operand_w; 45.1561 +end 45.1562 + 45.1563 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH 45.1564 +// Indicate when a branch should be taken in X stage 45.1565 +assign branch_taken_x = (stall_x == `FALSE) 45.1566 + && ( (branch_x == `TRUE) 45.1567 + && ((condition_x == `LM32_CONDITION_U1) || (condition_x == `LM32_CONDITION_U2)) 45.1568 + && (valid_x == `TRUE) 45.1569 + && (branch_predict_x == `FALSE) 45.1570 + ); 45.1571 +`endif 45.1572 + 45.1573 +// Indicate when a branch should be taken in M stage (exceptions are a type of branch) 45.1574 +assign branch_taken_m = (stall_m == `FALSE) 45.1575 + && ( ( (branch_m == `TRUE) 45.1576 + && (valid_m == `TRUE) 45.1577 + && ( ( (condition_met_m == `TRUE) 45.1578 + && (branch_predict_taken_m == `FALSE) 45.1579 + ) 45.1580 + || ( (condition_met_m == `FALSE) 45.1581 + && (branch_predict_m == `TRUE) 45.1582 + && (branch_predict_taken_m == `TRUE) 45.1583 + ) 45.1584 + ) 45.1585 + ) 45.1586 + || (exception_m == `TRUE) 45.1587 + ); 45.1588 + 45.1589 +// Indicate when a branch in M stage is mispredicted as being taken 45.1590 +assign branch_mispredict_taken_m = (condition_met_m == `FALSE) 45.1591 + && (branch_predict_m == `TRUE) 45.1592 + && (branch_predict_taken_m == `TRUE); 45.1593 + 45.1594 +// Indicate when a branch in M stage will cause flush in X stage 45.1595 +assign branch_flushX_m = (stall_m == `FALSE) 45.1596 + && ( ( (branch_m == `TRUE) 45.1597 + && (valid_m == `TRUE) 45.1598 + && ( (condition_met_m == `TRUE) 45.1599 + || ( (condition_met_m == `FALSE) 45.1600 + && (branch_predict_m == `TRUE) 45.1601 + && (branch_predict_taken_m == `TRUE) 45.1602 + ) 45.1603 + ) 45.1604 + ) 45.1605 + || (exception_m == `TRUE) 45.1606 + ); 45.1607 + 45.1608 +// Generate signal that will kill instructions in each pipeline stage when necessary 45.1609 +assign kill_f = ( (valid_d == `TRUE) 45.1610 + && (branch_predict_taken_d == `TRUE) 45.1611 + ) 45.1612 + || (branch_taken_m == `TRUE) 45.1613 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH 45.1614 + || (branch_taken_x == `TRUE) 45.1615 +`endif 45.1616 +`ifdef CFG_ICACHE_ENABLED 45.1617 + || (icache_refill_request == `TRUE) 45.1618 +`endif 45.1619 +`ifdef CFG_DCACHE_ENABLED 45.1620 + || (dcache_refill_request == `TRUE) 45.1621 +`endif 45.1622 + ; 45.1623 +assign kill_d = (branch_taken_m == `TRUE) 45.1624 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH 45.1625 + || (branch_taken_x == `TRUE) 45.1626 +`endif 45.1627 +`ifdef CFG_ICACHE_ENABLED 45.1628 + || (icache_refill_request == `TRUE) 45.1629 +`endif 45.1630 +`ifdef CFG_DCACHE_ENABLED 45.1631 + || (dcache_refill_request == `TRUE) 45.1632 +`endif 45.1633 + ; 45.1634 +assign kill_x = (branch_flushX_m == `TRUE) 45.1635 +`ifdef CFG_DCACHE_ENABLED 45.1636 + || (dcache_refill_request == `TRUE) 45.1637 +`endif 45.1638 + ; 45.1639 +assign kill_m = `FALSE 45.1640 +`ifdef CFG_DCACHE_ENABLED 45.1641 + || (dcache_refill_request == `TRUE) 45.1642 +`endif 45.1643 + ; 45.1644 +assign kill_w = `FALSE 45.1645 +`ifdef CFG_DCACHE_ENABLED 45.1646 + || (dcache_refill_request == `TRUE) 45.1647 +`endif 45.1648 + ; 45.1649 + 45.1650 +// Exceptions 45.1651 + 45.1652 +`ifdef CFG_DEBUG_ENABLED 45.1653 +assign breakpoint_exception = ( ( (break_x == `TRUE) 45.1654 + || (bp_match == `TRUE) 45.1655 + ) 45.1656 + && (valid_x == `TRUE) 45.1657 + ) 45.1658 +`ifdef CFG_JTAG_ENABLED 45.1659 + || (jtag_break == `TRUE) 45.1660 +`endif 45.1661 + ; 45.1662 +`endif 45.1663 + 45.1664 +`ifdef CFG_DEBUG_ENABLED 45.1665 +assign watchpoint_exception = wp_match == `TRUE; 45.1666 +`endif 45.1667 + 45.1668 +`ifdef CFG_BUS_ERRORS_ENABLED 45.1669 +assign instruction_bus_error_exception = ( (bus_error_x == `TRUE) 45.1670 + && (valid_x == `TRUE) 45.1671 + ); 45.1672 +assign data_bus_error_exception = data_bus_error_seen == `TRUE; 45.1673 +`endif 45.1674 + 45.1675 +`ifdef CFG_MC_DIVIDE_ENABLED 45.1676 +assign divide_by_zero_exception = divide_by_zero_x == `TRUE; 45.1677 +`endif 45.1678 + 45.1679 +assign system_call_exception = ( (scall_x == `TRUE) 45.1680 +`ifdef CFG_BUS_ERRORS_ENABLED 45.1681 + && (valid_x == `TRUE) 45.1682 +`endif 45.1683 + ); 45.1684 + 45.1685 +`ifdef CFG_DEBUG_ENABLED 45.1686 +assign debug_exception_x = (breakpoint_exception == `TRUE) 45.1687 + || (watchpoint_exception == `TRUE) 45.1688 + ; 45.1689 + 45.1690 +assign non_debug_exception_x = (system_call_exception == `TRUE) 45.1691 +`ifdef CFG_JTAG_ENABLED 45.1692 + || (reset_exception == `TRUE) 45.1693 +`endif 45.1694 +`ifdef CFG_BUS_ERRORS_ENABLED 45.1695 + || (instruction_bus_error_exception == `TRUE) 45.1696 + || (data_bus_error_exception == `TRUE) 45.1697 +`endif 45.1698 +`ifdef CFG_MC_DIVIDE_ENABLED 45.1699 + || (divide_by_zero_exception == `TRUE) 45.1700 +`endif 45.1701 +`ifdef CFG_INTERRUPTS_ENABLED 45.1702 + || ( (interrupt_exception == `TRUE) 45.1703 +`ifdef LM32_SINGLE_STEP_ENABLED 45.1704 + && (dc_ss == `FALSE) 45.1705 +`endif 45.1706 +`ifdef CFG_BUS_ERRORS_ENABLED 45.1707 + && (store_q_m == `FALSE) 45.1708 + && (D_CYC_O == `FALSE) 45.1709 +`endif 45.1710 + ) 45.1711 +`endif 45.1712 + ; 45.1713 + 45.1714 +assign exception_x = (debug_exception_x == `TRUE) || (non_debug_exception_x == `TRUE); 45.1715 +`else 45.1716 +assign exception_x = (system_call_exception == `TRUE) 45.1717 +`ifdef CFG_BUS_ERRORS_ENABLED 45.1718 + || (instruction_bus_error_exception == `TRUE) 45.1719 + || (data_bus_error_exception == `TRUE) 45.1720 +`endif 45.1721 +`ifdef CFG_MC_DIVIDE_ENABLED 45.1722 + || (divide_by_zero_exception == `TRUE) 45.1723 +`endif 45.1724 +`ifdef CFG_INTERRUPTS_ENABLED 45.1725 + || ( (interrupt_exception == `TRUE) 45.1726 +`ifdef LM32_SINGLE_STEP_ENABLED 45.1727 + && (dc_ss == `FALSE) 45.1728 +`endif 45.1729 +`ifdef CFG_BUS_ERRORS_ENABLED 45.1730 + && (store_q_m == `FALSE) 45.1731 + && (D_CYC_O == `FALSE) 45.1732 +`endif 45.1733 + ) 45.1734 +`endif 45.1735 + ; 45.1736 +`endif 45.1737 + 45.1738 +// Exception ID 45.1739 +always @(*) 45.1740 +begin 45.1741 +`ifdef CFG_DEBUG_ENABLED 45.1742 +`ifdef CFG_JTAG_ENABLED 45.1743 + if (reset_exception == `TRUE) 45.1744 + eid_x = `LM32_EID_RESET; 45.1745 + else 45.1746 +`endif 45.1747 +`ifdef CFG_BUS_ERRORS_ENABLED 45.1748 + if (data_bus_error_exception == `TRUE) 45.1749 + eid_x = `LM32_EID_DATA_BUS_ERROR; 45.1750 + else 45.1751 +`endif 45.1752 + if (breakpoint_exception == `TRUE) 45.1753 + eid_x = `LM32_EID_BREAKPOINT; 45.1754 + else 45.1755 +`endif 45.1756 +`ifdef CFG_BUS_ERRORS_ENABLED 45.1757 + if (data_bus_error_exception == `TRUE) 45.1758 + eid_x = `LM32_EID_DATA_BUS_ERROR; 45.1759 + else 45.1760 + if (instruction_bus_error_exception == `TRUE) 45.1761 + eid_x = `LM32_EID_INST_BUS_ERROR; 45.1762 + else 45.1763 +`endif 45.1764 +`ifdef CFG_DEBUG_ENABLED 45.1765 + if (watchpoint_exception == `TRUE) 45.1766 + eid_x = `LM32_EID_WATCHPOINT; 45.1767 + else 45.1768 +`endif 45.1769 +`ifdef CFG_MC_DIVIDE_ENABLED 45.1770 + if (divide_by_zero_exception == `TRUE) 45.1771 + eid_x = `LM32_EID_DIVIDE_BY_ZERO; 45.1772 + else 45.1773 +`endif 45.1774 +`ifdef CFG_INTERRUPTS_ENABLED 45.1775 + if ( (interrupt_exception == `TRUE) 45.1776 +`ifdef LM32_SINGLE_STEP_ENABLED 45.1777 + && (dc_ss == `FALSE) 45.1778 +`endif 45.1779 + ) 45.1780 + eid_x = `LM32_EID_INTERRUPT; 45.1781 + else 45.1782 +`endif 45.1783 + eid_x = `LM32_EID_SCALL; 45.1784 +end 45.1785 + 45.1786 +// Stall generation 45.1787 + 45.1788 +assign stall_a = (stall_f == `TRUE); 45.1789 + 45.1790 +assign stall_f = (stall_d == `TRUE); 45.1791 + 45.1792 +assign stall_d = (stall_x == `TRUE) 45.1793 + || ( (interlock == `TRUE) 45.1794 + && (kill_d == `FALSE) 45.1795 + ) 45.1796 + || ( ( (eret_d == `TRUE) 45.1797 + || (scall_d == `TRUE) 45.1798 +`ifdef CFG_BUS_ERRORS_ENABLED 45.1799 + || (bus_error_d == `TRUE) 45.1800 +`endif 45.1801 + ) 45.1802 + && ( (load_q_x == `TRUE) 45.1803 + || (load_q_m == `TRUE) 45.1804 + || (store_q_x == `TRUE) 45.1805 + || (store_q_m == `TRUE) 45.1806 + || (D_CYC_O == `TRUE) 45.1807 + ) 45.1808 + && (kill_d == `FALSE) 45.1809 + ) 45.1810 +`ifdef CFG_DEBUG_ENABLED 45.1811 + || ( ( (break_d == `TRUE) 45.1812 + || (bret_d == `TRUE) 45.1813 + ) 45.1814 + && ( (load_q_x == `TRUE) 45.1815 + || (store_q_x == `TRUE) 45.1816 + || (load_q_m == `TRUE) 45.1817 + || (store_q_m == `TRUE) 45.1818 + || (D_CYC_O == `TRUE) 45.1819 + ) 45.1820 + && (kill_d == `FALSE) 45.1821 + ) 45.1822 +`endif 45.1823 + || ( (csr_write_enable_d == `TRUE) 45.1824 + && (load_q_x == `TRUE) 45.1825 + ) 45.1826 + ; 45.1827 + 45.1828 +assign stall_x = (stall_m == `TRUE) 45.1829 +`ifdef LM32_MC_ARITHMETIC_ENABLED 45.1830 + || ( (mc_stall_request_x == `TRUE) 45.1831 + && (kill_x == `FALSE) 45.1832 + ) 45.1833 +`endif 45.1834 +`ifdef CFG_IROM_ENABLED 45.1835 + // Stall load/store instruction in D stage if there is an ongoing store 45.1836 + // operation to instruction ROM in M stage 45.1837 + || ( (irom_stall_request_x == `TRUE) 45.1838 + && ( (load_d == `TRUE) 45.1839 + || (store_d == `TRUE) 45.1840 + ) 45.1841 + ) 45.1842 +`endif 45.1843 + ; 45.1844 + 45.1845 +assign stall_m = (stall_wb_load == `TRUE) 45.1846 +`ifdef CFG_SIZE_OVER_SPEED 45.1847 + || (D_CYC_O == `TRUE) 45.1848 +`else 45.1849 + || ( (D_CYC_O == `TRUE) 45.1850 + && ( (store_m == `TRUE) 45.1851 + /* 45.1852 + Bug: Following loop does not allow interrupts to be services since 45.1853 + either D_CYC_O or store_m is always high during entire duration of 45.1854 + loop. 45.1855 + L1: addi r1, r1, 1 45.1856 + sw (r2,0), r1 45.1857 + bi L1 45.1858 + 45.1859 + Introduce a single-cycle stall when a wishbone cycle is in progress 45.1860 + and a new store instruction is in Execute stage and a interrupt 45.1861 + exception has occured. This stall will ensure that D_CYC_O and 45.1862 + store_m will both be low for one cycle. 45.1863 + */ 45.1864 +`ifdef CFG_INTERRUPTS_ENABLED 45.1865 + || ((store_x == `TRUE) && (interrupt_exception == `TRUE)) 45.1866 +`endif 45.1867 + || (load_m == `TRUE) 45.1868 + || (load_x == `TRUE) 45.1869 + ) 45.1870 + ) 45.1871 +`endif 45.1872 +`ifdef CFG_DCACHE_ENABLED 45.1873 + || (dcache_stall_request == `TRUE) // Need to stall in case a taken branch is in M stage and data cache is only being flush, so wont be restarted 45.1874 +`endif 45.1875 +`ifdef CFG_ICACHE_ENABLED 45.1876 + || (icache_stall_request == `TRUE) // Pipeline needs to be stalled otherwise branches may be lost 45.1877 + || ((I_CYC_O == `TRUE) && ((branch_m == `TRUE) || (exception_m == `TRUE))) 45.1878 +`else 45.1879 +`ifdef CFG_IWB_ENABLED 45.1880 + || (I_CYC_O == `TRUE) 45.1881 +`endif 45.1882 +`endif 45.1883 +`ifdef CFG_USER_ENABLED 45.1884 + || ( (user_valid == `TRUE) // Stall whole pipeline, rather than just X stage, where the instruction is, so we don't have to worry about exceptions (maybe) 45.1885 + && (user_complete == `FALSE) 45.1886 + ) 45.1887 +`endif 45.1888 + ; 45.1889 + 45.1890 +// Qualify state changing control signals 45.1891 +`ifdef LM32_MC_ARITHMETIC_ENABLED 45.1892 +assign q_d = (valid_d == `TRUE) && (kill_d == `FALSE); 45.1893 +`endif 45.1894 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED 45.1895 +assign shift_left_q_d = (shift_left_d == `TRUE) && (q_d == `TRUE); 45.1896 +assign shift_right_q_d = (shift_right_d == `TRUE) && (q_d == `TRUE); 45.1897 +`endif 45.1898 +`ifdef CFG_MC_MULTIPLY_ENABLED 45.1899 +assign multiply_q_d = (multiply_d == `TRUE) && (q_d == `TRUE); 45.1900 +`endif 45.1901 +`ifdef CFG_MC_DIVIDE_ENABLED 45.1902 +assign divide_q_d = (divide_d == `TRUE) && (q_d == `TRUE); 45.1903 +assign modulus_q_d = (modulus_d == `TRUE) && (q_d == `TRUE); 45.1904 +`endif 45.1905 +assign q_x = (valid_x == `TRUE) && (kill_x == `FALSE); 45.1906 +assign csr_write_enable_q_x = (csr_write_enable_x == `TRUE) && (q_x == `TRUE); 45.1907 +assign eret_q_x = (eret_x == `TRUE) && (q_x == `TRUE); 45.1908 +`ifdef CFG_DEBUG_ENABLED 45.1909 +assign bret_q_x = (bret_x == `TRUE) && (q_x == `TRUE); 45.1910 +`endif 45.1911 +assign load_q_x = (load_x == `TRUE) 45.1912 + && (q_x == `TRUE) 45.1913 +`ifdef CFG_DEBUG_ENABLED 45.1914 + && (bp_match == `FALSE) 45.1915 +`endif 45.1916 + ; 45.1917 +assign store_q_x = (store_x == `TRUE) 45.1918 + && (q_x == `TRUE) 45.1919 +`ifdef CFG_DEBUG_ENABLED 45.1920 + && (bp_match == `FALSE) 45.1921 +`endif 45.1922 + ; 45.1923 +`ifdef CFG_USER_ENABLED 45.1924 +assign user_valid = (x_result_sel_user_x == `TRUE) && (q_x == `TRUE); 45.1925 +`endif 45.1926 +assign q_m = (valid_m == `TRUE) && (kill_m == `FALSE) && (exception_m == `FALSE); 45.1927 +assign load_q_m = (load_m == `TRUE) && (q_m == `TRUE); 45.1928 +assign store_q_m = (store_m == `TRUE) && (q_m == `TRUE); 45.1929 +`ifdef CFG_DEBUG_ENABLED 45.1930 +assign debug_exception_q_w = ((debug_exception_w == `TRUE) && (valid_w == `TRUE)); 45.1931 +assign non_debug_exception_q_w = ((non_debug_exception_w == `TRUE) && (valid_w == `TRUE)); 45.1932 +`else 45.1933 +assign exception_q_w = ((exception_w == `TRUE) && (valid_w == `TRUE)); 45.1934 +`endif 45.1935 +// Don't qualify register write enables with kill, as the signal is needed early, and it doesn't matter if the instruction is killed (except for the actual write - but that is handled separately) 45.1936 +assign write_enable_q_x = (write_enable_x == `TRUE) && (valid_x == `TRUE) && (branch_flushX_m == `FALSE); 45.1937 +assign write_enable_q_m = (write_enable_m == `TRUE) && (valid_m == `TRUE); 45.1938 +assign write_enable_q_w = (write_enable_w == `TRUE) && (valid_w == `TRUE); 45.1939 +// The enable that actually does write the registers needs to be qualified with kill 45.1940 +assign reg_write_enable_q_w = (write_enable_w == `TRUE) && (kill_w == `FALSE) && (valid_w == `TRUE); 45.1941 + 45.1942 +// Configuration (CFG) CSR 45.1943 +assign cfg = { 45.1944 + `LM32_REVISION, 45.1945 + watchpoints[3:0], 45.1946 + breakpoints[3:0], 45.1947 + interrupts[5:0], 45.1948 +`ifdef CFG_JTAG_UART_ENABLED 45.1949 + `TRUE, 45.1950 +`else 45.1951 + `FALSE, 45.1952 +`endif 45.1953 +`ifdef CFG_ROM_DEBUG_ENABLED 45.1954 + `TRUE, 45.1955 +`else 45.1956 + `FALSE, 45.1957 +`endif 45.1958 +`ifdef CFG_HW_DEBUG_ENABLED 45.1959 + `TRUE, 45.1960 +`else 45.1961 + `FALSE, 45.1962 +`endif 45.1963 +`ifdef CFG_DEBUG_ENABLED 45.1964 + `TRUE, 45.1965 +`else 45.1966 + `FALSE, 45.1967 +`endif 45.1968 +`ifdef CFG_ICACHE_ENABLED 45.1969 + `TRUE, 45.1970 +`else 45.1971 + `FALSE, 45.1972 +`endif 45.1973 +`ifdef CFG_DCACHE_ENABLED 45.1974 + `TRUE, 45.1975 +`else 45.1976 + `FALSE, 45.1977 +`endif 45.1978 +`ifdef CFG_CYCLE_COUNTER_ENABLED 45.1979 + `TRUE, 45.1980 +`else 45.1981 + `FALSE, 45.1982 +`endif 45.1983 +`ifdef CFG_USER_ENABLED 45.1984 + `TRUE, 45.1985 +`else 45.1986 + `FALSE, 45.1987 +`endif 45.1988 +`ifdef CFG_SIGN_EXTEND_ENABLED 45.1989 + `TRUE, 45.1990 +`else 45.1991 + `FALSE, 45.1992 +`endif 45.1993 +`ifdef LM32_BARREL_SHIFT_ENABLED 45.1994 + `TRUE, 45.1995 +`else 45.1996 + `FALSE, 45.1997 +`endif 45.1998 +`ifdef CFG_MC_DIVIDE_ENABLED 45.1999 + `TRUE, 45.2000 +`else 45.2001 + `FALSE, 45.2002 +`endif 45.2003 +`ifdef LM32_MULTIPLY_ENABLED 45.2004 + `TRUE 45.2005 +`else 45.2006 + `FALSE 45.2007 +`endif 45.2008 + }; 45.2009 + 45.2010 +assign cfg2 = { 45.2011 + 30'b0, 45.2012 +`ifdef CFG_IROM_ENABLED 45.2013 + `TRUE, 45.2014 +`else 45.2015 + `FALSE, 45.2016 +`endif 45.2017 +`ifdef CFG_DRAM_ENABLED 45.2018 + `TRUE 45.2019 +`else 45.2020 + `FALSE 45.2021 +`endif 45.2022 + }; 45.2023 + 45.2024 +// Cache flush 45.2025 +`ifdef CFG_ICACHE_ENABLED 45.2026 +assign iflush = ( (csr_write_enable_d == `TRUE) 45.2027 + && (csr_d == `LM32_CSR_ICC) 45.2028 + && (stall_d == `FALSE) 45.2029 + && (kill_d == `FALSE) 45.2030 + && (valid_d == `TRUE)) 45.2031 +// Added by GSI: needed to flush cache after loading firmware per JTAG 45.2032 +`ifdef CFG_HW_DEBUG_ENABLED 45.2033 + || 45.2034 + ( (jtag_csr_write_enable == `TRUE) 45.2035 + && (jtag_csr == `LM32_CSR_ICC)) 45.2036 +`endif 45.2037 + ; 45.2038 +`endif 45.2039 +`ifdef CFG_DCACHE_ENABLED 45.2040 +assign dflush_x = ( (csr_write_enable_q_x == `TRUE) 45.2041 + && (csr_x == `LM32_CSR_DCC)) 45.2042 +// Added by GSI: needed to flush cache after loading firmware per JTAG 45.2043 +`ifdef CFG_HW_DEBUG_ENABLED 45.2044 + || 45.2045 + ( (jtag_csr_write_enable == `TRUE) 45.2046 + && (jtag_csr == `LM32_CSR_DCC)) 45.2047 +`endif 45.2048 + ; 45.2049 +`endif 45.2050 + 45.2051 +// Extract CSR index 45.2052 +assign csr_d = read_idx_0_d[`LM32_CSR_RNG]; 45.2053 + 45.2054 +// CSR reads 45.2055 +always @(*) 45.2056 +begin 45.2057 + case (csr_x) 45.2058 +`ifdef CFG_INTERRUPTS_ENABLED 45.2059 + `LM32_CSR_IE, 45.2060 + `LM32_CSR_IM, 45.2061 + `LM32_CSR_IP: csr_read_data_x = interrupt_csr_read_data_x; 45.2062 +`endif 45.2063 +`ifdef CFG_CYCLE_COUNTER_ENABLED 45.2064 + `LM32_CSR_CC: csr_read_data_x = cc; 45.2065 +`endif 45.2066 + `LM32_CSR_CFG: csr_read_data_x = cfg; 45.2067 + `LM32_CSR_EBA: csr_read_data_x = {eba, 8'h00}; 45.2068 +`ifdef CFG_DEBUG_ENABLED 45.2069 + `LM32_CSR_DEBA: csr_read_data_x = {deba, 8'h00}; 45.2070 +`endif 45.2071 +`ifdef CFG_JTAG_UART_ENABLED 45.2072 + `LM32_CSR_JTX: csr_read_data_x = jtx_csr_read_data; 45.2073 + `LM32_CSR_JRX: csr_read_data_x = jrx_csr_read_data; 45.2074 +`endif 45.2075 + `LM32_CSR_CFG2: csr_read_data_x = cfg2; 45.2076 + 45.2077 + default: csr_read_data_x = {`LM32_WORD_WIDTH{1'bx}}; 45.2078 + endcase 45.2079 +end 45.2080 + 45.2081 +///////////////////////////////////////////////////// 45.2082 +// Sequential Logic 45.2083 +///////////////////////////////////////////////////// 45.2084 + 45.2085 +// Exception Base Address (EBA) CSR 45.2086 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 45.2087 +begin 45.2088 + if (rst_i == `TRUE) 45.2089 + eba <= eba_reset[`LM32_PC_WIDTH+2-1:8]; 45.2090 + else 45.2091 + begin 45.2092 + if ((csr_write_enable_q_x == `TRUE) && (csr_x == `LM32_CSR_EBA) && (stall_x == `FALSE)) 45.2093 + eba <= operand_1_x[`LM32_PC_WIDTH+2-1:8]; 45.2094 +`ifdef CFG_HW_DEBUG_ENABLED 45.2095 + if ((jtag_csr_write_enable == `TRUE) && (jtag_csr == `LM32_CSR_EBA)) 45.2096 + eba <= jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8]; 45.2097 +`endif 45.2098 + end 45.2099 +end 45.2100 + 45.2101 +`ifdef CFG_DEBUG_ENABLED 45.2102 +// Debug Exception Base Address (DEBA) CSR 45.2103 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 45.2104 +begin 45.2105 + if (rst_i == `TRUE) 45.2106 + deba <= deba_reset[`LM32_PC_WIDTH+2-1:8]; 45.2107 + else 45.2108 + begin 45.2109 + if ((csr_write_enable_q_x == `TRUE) && (csr_x == `LM32_CSR_DEBA) && (stall_x == `FALSE)) 45.2110 + deba <= operand_1_x[`LM32_PC_WIDTH+2-1:8]; 45.2111 +`ifdef CFG_HW_DEBUG_ENABLED 45.2112 + if ((jtag_csr_write_enable == `TRUE) && (jtag_csr == `LM32_CSR_DEBA)) 45.2113 + deba <= jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8]; 45.2114 +`endif 45.2115 + end 45.2116 +end 45.2117 +`endif 45.2118 + 45.2119 +// Cycle Counter (CC) CSR 45.2120 +`ifdef CFG_CYCLE_COUNTER_ENABLED 45.2121 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 45.2122 +begin 45.2123 + if (rst_i == `TRUE) 45.2124 + cc <= {`LM32_WORD_WIDTH{1'b0}}; 45.2125 + else 45.2126 + cc <= cc + 1'b1; 45.2127 +end 45.2128 +`endif 45.2129 + 45.2130 +`ifdef CFG_BUS_ERRORS_ENABLED 45.2131 +// Watch for data bus errors 45.2132 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 45.2133 +begin 45.2134 + if (rst_i == `TRUE) 45.2135 + data_bus_error_seen <= `FALSE; 45.2136 + else 45.2137 + begin 45.2138 + // Set flag when bus error is detected 45.2139 + if ((D_ERR_I == `TRUE) && (D_CYC_O == `TRUE)) 45.2140 + data_bus_error_seen <= `TRUE; 45.2141 + // Clear flag when exception is taken 45.2142 + if ((exception_m == `TRUE) && (kill_m == `FALSE)) 45.2143 + data_bus_error_seen <= `FALSE; 45.2144 + end 45.2145 +end 45.2146 +`endif 45.2147 + 45.2148 +// Valid bits to indicate whether an instruction in a partcular pipeline stage is valid or not 45.2149 + 45.2150 +`ifdef CFG_ICACHE_ENABLED 45.2151 +`ifdef CFG_DCACHE_ENABLED 45.2152 +always @(*) 45.2153 +begin 45.2154 + if ( (icache_refill_request == `TRUE) 45.2155 + || (dcache_refill_request == `TRUE) 45.2156 + ) 45.2157 + valid_a = `FALSE; 45.2158 + else if ( (icache_restart_request == `TRUE) 45.2159 + || (dcache_restart_request == `TRUE) 45.2160 + ) 45.2161 + valid_a = `TRUE; 45.2162 + else 45.2163 + valid_a = !icache_refilling && !dcache_refilling; 45.2164 +end 45.2165 +`else 45.2166 +always @(*) 45.2167 +begin 45.2168 + if (icache_refill_request == `TRUE) 45.2169 + valid_a = `FALSE; 45.2170 + else if (icache_restart_request == `TRUE) 45.2171 + valid_a = `TRUE; 45.2172 + else 45.2173 + valid_a = !icache_refilling; 45.2174 +end 45.2175 +`endif 45.2176 +`else 45.2177 +`ifdef CFG_DCACHE_ENABLED 45.2178 +always @(*) 45.2179 +begin 45.2180 + if (dcache_refill_request == `TRUE) 45.2181 + valid_a = `FALSE; 45.2182 + else if (dcache_restart_request == `TRUE) 45.2183 + valid_a = `TRUE; 45.2184 + else 45.2185 + valid_a = !dcache_refilling; 45.2186 +end 45.2187 +`endif 45.2188 +`endif 45.2189 + 45.2190 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 45.2191 +begin 45.2192 + if (rst_i == `TRUE) 45.2193 + begin 45.2194 + valid_f <= `FALSE; 45.2195 + valid_d <= `FALSE; 45.2196 + valid_x <= `FALSE; 45.2197 + valid_m <= `FALSE; 45.2198 + valid_w <= `FALSE; 45.2199 + end 45.2200 + else 45.2201 + begin 45.2202 + if ((kill_f == `TRUE) || (stall_a == `FALSE)) 45.2203 +`ifdef LM32_CACHE_ENABLED 45.2204 + valid_f <= valid_a; 45.2205 +`else 45.2206 + valid_f <= `TRUE; 45.2207 +`endif 45.2208 + else if (stall_f == `FALSE) 45.2209 + valid_f <= `FALSE; 45.2210 + 45.2211 + if (kill_d == `TRUE) 45.2212 + valid_d <= `FALSE; 45.2213 + else if (stall_f == `FALSE) 45.2214 + valid_d <= valid_f & !kill_f; 45.2215 + else if (stall_d == `FALSE) 45.2216 + valid_d <= `FALSE; 45.2217 + 45.2218 + if (stall_d == `FALSE) 45.2219 + valid_x <= valid_d & !kill_d; 45.2220 + else if (kill_x == `TRUE) 45.2221 + valid_x <= `FALSE; 45.2222 + else if (stall_x == `FALSE) 45.2223 + valid_x <= `FALSE; 45.2224 + 45.2225 + if (kill_m == `TRUE) 45.2226 + valid_m <= `FALSE; 45.2227 + else if (stall_x == `FALSE) 45.2228 + valid_m <= valid_x & !kill_x; 45.2229 + else if (stall_m == `FALSE) 45.2230 + valid_m <= `FALSE; 45.2231 + 45.2232 + if (stall_m == `FALSE) 45.2233 + valid_w <= valid_m & !kill_m; 45.2234 + else 45.2235 + valid_w <= `FALSE; 45.2236 + end 45.2237 +end 45.2238 + 45.2239 +// Microcode pipeline registers 45.2240 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 45.2241 +begin 45.2242 + if (rst_i == `TRUE) 45.2243 + begin 45.2244 +`ifdef CFG_USER_ENABLED 45.2245 + user_opcode <= {`LM32_USER_OPCODE_WIDTH{1'b0}}; 45.2246 +`endif 45.2247 + operand_0_x <= {`LM32_WORD_WIDTH{1'b0}}; 45.2248 + operand_1_x <= {`LM32_WORD_WIDTH{1'b0}}; 45.2249 + store_operand_x <= {`LM32_WORD_WIDTH{1'b0}}; 45.2250 + branch_target_x <= {`LM32_PC_WIDTH{1'b0}}; 45.2251 + x_result_sel_csr_x <= `FALSE; 45.2252 +`ifdef LM32_MC_ARITHMETIC_ENABLED 45.2253 + x_result_sel_mc_arith_x <= `FALSE; 45.2254 +`endif 45.2255 +`ifdef LM32_NO_BARREL_SHIFT 45.2256 + x_result_sel_shift_x <= `FALSE; 45.2257 +`endif 45.2258 +`ifdef CFG_SIGN_EXTEND_ENABLED 45.2259 + x_result_sel_sext_x <= `FALSE; 45.2260 +`endif 45.2261 + x_result_sel_logic_x <= `FALSE; 45.2262 +`ifdef CFG_USER_ENABLED 45.2263 + x_result_sel_user_x <= `FALSE; 45.2264 +`endif 45.2265 + x_result_sel_add_x <= `FALSE; 45.2266 + m_result_sel_compare_x <= `FALSE; 45.2267 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 45.2268 + m_result_sel_shift_x <= `FALSE; 45.2269 +`endif 45.2270 + w_result_sel_load_x <= `FALSE; 45.2271 +`ifdef CFG_PL_MULTIPLY_ENABLED 45.2272 + w_result_sel_mul_x <= `FALSE; 45.2273 +`endif 45.2274 + x_bypass_enable_x <= `FALSE; 45.2275 + m_bypass_enable_x <= `FALSE; 45.2276 + write_enable_x <= `FALSE; 45.2277 + write_idx_x <= {`LM32_REG_IDX_WIDTH{1'b0}}; 45.2278 + csr_x <= {`LM32_CSR_WIDTH{1'b0}}; 45.2279 + load_x <= `FALSE; 45.2280 + store_x <= `FALSE; 45.2281 + size_x <= {`LM32_SIZE_WIDTH{1'b0}}; 45.2282 + sign_extend_x <= `FALSE; 45.2283 + adder_op_x <= `FALSE; 45.2284 + adder_op_x_n <= `FALSE; 45.2285 + logic_op_x <= 4'h0; 45.2286 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 45.2287 + direction_x <= `FALSE; 45.2288 +`endif 45.2289 +`ifdef CFG_ROTATE_ENABLED 45.2290 + rotate_x <= `FALSE; 45.2291 + 45.2292 +`endif 45.2293 + branch_x <= `FALSE; 45.2294 + branch_predict_x <= `FALSE; 45.2295 + branch_predict_taken_x <= `FALSE; 45.2296 + condition_x <= `LM32_CONDITION_U1; 45.2297 +`ifdef CFG_DEBUG_ENABLED 45.2298 + break_x <= `FALSE; 45.2299 +`endif 45.2300 + scall_x <= `FALSE; 45.2301 + eret_x <= `FALSE; 45.2302 +`ifdef CFG_DEBUG_ENABLED 45.2303 + bret_x <= `FALSE; 45.2304 +`endif 45.2305 +`ifdef CFG_BUS_ERRORS_ENABLED 45.2306 + bus_error_x <= `FALSE; 45.2307 + data_bus_error_exception_m <= `FALSE; 45.2308 +`endif 45.2309 + csr_write_enable_x <= `FALSE; 45.2310 + operand_m <= {`LM32_WORD_WIDTH{1'b0}}; 45.2311 + branch_target_m <= {`LM32_PC_WIDTH{1'b0}}; 45.2312 + m_result_sel_compare_m <= `FALSE; 45.2313 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 45.2314 + m_result_sel_shift_m <= `FALSE; 45.2315 +`endif 45.2316 + w_result_sel_load_m <= `FALSE; 45.2317 +`ifdef CFG_PL_MULTIPLY_ENABLED 45.2318 + w_result_sel_mul_m <= `FALSE; 45.2319 +`endif 45.2320 + m_bypass_enable_m <= `FALSE; 45.2321 + branch_m <= `FALSE; 45.2322 + branch_predict_m <= `FALSE; 45.2323 + branch_predict_taken_m <= `FALSE; 45.2324 + exception_m <= `FALSE; 45.2325 + load_m <= `FALSE; 45.2326 + store_m <= `FALSE; 45.2327 + write_enable_m <= `FALSE; 45.2328 + write_idx_m <= {`LM32_REG_IDX_WIDTH{1'b0}}; 45.2329 + condition_met_m <= `FALSE; 45.2330 +`ifdef CFG_DCACHE_ENABLED 45.2331 + dflush_m <= `FALSE; 45.2332 +`endif 45.2333 +`ifdef CFG_DEBUG_ENABLED 45.2334 + debug_exception_m <= `FALSE; 45.2335 + non_debug_exception_m <= `FALSE; 45.2336 +`endif 45.2337 + operand_w <= {`LM32_WORD_WIDTH{1'b0}}; 45.2338 + w_result_sel_load_w <= `FALSE; 45.2339 +`ifdef CFG_PL_MULTIPLY_ENABLED 45.2340 + w_result_sel_mul_w <= `FALSE; 45.2341 +`endif 45.2342 + write_idx_w <= {`LM32_REG_IDX_WIDTH{1'b0}}; 45.2343 + write_enable_w <= `FALSE; 45.2344 +`ifdef CFG_DEBUG_ENABLED 45.2345 + debug_exception_w <= `FALSE; 45.2346 + non_debug_exception_w <= `FALSE; 45.2347 +`else 45.2348 + exception_w <= `FALSE; 45.2349 +`endif 45.2350 +`ifdef CFG_BUS_ERRORS_ENABLED 45.2351 + memop_pc_w <= {`LM32_PC_WIDTH{1'b0}}; 45.2352 +`endif 45.2353 + end 45.2354 + else 45.2355 + begin 45.2356 + // D/X stage registers 45.2357 + 45.2358 + if (stall_x == `FALSE) 45.2359 + begin 45.2360 +`ifdef CFG_USER_ENABLED 45.2361 + user_opcode <= user_opcode_d; 45.2362 +`endif 45.2363 + operand_0_x <= d_result_0; 45.2364 + operand_1_x <= d_result_1; 45.2365 + store_operand_x <= bypass_data_1; 45.2366 + branch_target_x <= branch_reg_d == `TRUE ? bypass_data_0[`LM32_PC_RNG] : branch_target_d; 45.2367 + x_result_sel_csr_x <= x_result_sel_csr_d; 45.2368 +`ifdef LM32_MC_ARITHMETIC_ENABLED 45.2369 + x_result_sel_mc_arith_x <= x_result_sel_mc_arith_d; 45.2370 +`endif 45.2371 +`ifdef LM32_NO_BARREL_SHIFT 45.2372 + x_result_sel_shift_x <= x_result_sel_shift_d; 45.2373 +`endif 45.2374 +`ifdef CFG_SIGN_EXTEND_ENABLED 45.2375 + x_result_sel_sext_x <= x_result_sel_sext_d; 45.2376 +`endif 45.2377 + x_result_sel_logic_x <= x_result_sel_logic_d; 45.2378 +`ifdef CFG_USER_ENABLED 45.2379 + x_result_sel_user_x <= x_result_sel_user_d; 45.2380 +`endif 45.2381 + x_result_sel_add_x <= x_result_sel_add_d; 45.2382 + m_result_sel_compare_x <= m_result_sel_compare_d; 45.2383 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 45.2384 + m_result_sel_shift_x <= m_result_sel_shift_d; 45.2385 +`endif 45.2386 + w_result_sel_load_x <= w_result_sel_load_d; 45.2387 +`ifdef CFG_PL_MULTIPLY_ENABLED 45.2388 + w_result_sel_mul_x <= w_result_sel_mul_d; 45.2389 +`endif 45.2390 + x_bypass_enable_x <= x_bypass_enable_d; 45.2391 + m_bypass_enable_x <= m_bypass_enable_d; 45.2392 + load_x <= load_d; 45.2393 + store_x <= store_d; 45.2394 + branch_x <= branch_d; 45.2395 + branch_predict_x <= branch_predict_d; 45.2396 + branch_predict_taken_x <= branch_predict_taken_d; 45.2397 + write_idx_x <= write_idx_d; 45.2398 + csr_x <= csr_d; 45.2399 + size_x <= size_d; 45.2400 + sign_extend_x <= sign_extend_d; 45.2401 + adder_op_x <= adder_op_d; 45.2402 + adder_op_x_n <= ~adder_op_d; 45.2403 + logic_op_x <= logic_op_d; 45.2404 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 45.2405 + direction_x <= direction_d; 45.2406 +`endif 45.2407 +`ifdef CFG_ROTATE_ENABLED 45.2408 + rotate_x <= rotate_d; 45.2409 +`endif 45.2410 + condition_x <= condition_d; 45.2411 + csr_write_enable_x <= csr_write_enable_d; 45.2412 +`ifdef CFG_DEBUG_ENABLED 45.2413 + break_x <= break_d; 45.2414 +`endif 45.2415 + scall_x <= scall_d; 45.2416 +`ifdef CFG_BUS_ERRORS_ENABLED 45.2417 + bus_error_x <= bus_error_d; 45.2418 +`endif 45.2419 + eret_x <= eret_d; 45.2420 +`ifdef CFG_DEBUG_ENABLED 45.2421 + bret_x <= bret_d; 45.2422 +`endif 45.2423 + write_enable_x <= write_enable_d; 45.2424 + end 45.2425 + 45.2426 + // X/M stage registers 45.2427 + 45.2428 + if (stall_m == `FALSE) 45.2429 + begin 45.2430 + operand_m <= x_result; 45.2431 + m_result_sel_compare_m <= m_result_sel_compare_x; 45.2432 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 45.2433 + m_result_sel_shift_m <= m_result_sel_shift_x; 45.2434 +`endif 45.2435 + if (exception_x == `TRUE) 45.2436 + begin 45.2437 + w_result_sel_load_m <= `FALSE; 45.2438 +`ifdef CFG_PL_MULTIPLY_ENABLED 45.2439 + w_result_sel_mul_m <= `FALSE; 45.2440 +`endif 45.2441 + end 45.2442 + else 45.2443 + begin 45.2444 + w_result_sel_load_m <= w_result_sel_load_x; 45.2445 +`ifdef CFG_PL_MULTIPLY_ENABLED 45.2446 + w_result_sel_mul_m <= w_result_sel_mul_x; 45.2447 +`endif 45.2448 + end 45.2449 + m_bypass_enable_m <= m_bypass_enable_x; 45.2450 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 45.2451 +`endif 45.2452 + load_m <= load_x; 45.2453 + store_m <= store_x; 45.2454 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH 45.2455 + branch_m <= branch_x && !branch_taken_x; 45.2456 +`else 45.2457 + branch_m <= branch_x; 45.2458 + branch_predict_m <= branch_predict_x; 45.2459 + branch_predict_taken_m <= branch_predict_taken_x; 45.2460 +`endif 45.2461 +`ifdef CFG_DEBUG_ENABLED 45.2462 + // Data bus errors are generated by the wishbone and are 45.2463 + // made known to the processor only in next cycle (as a 45.2464 + // non-debug exception). A break instruction can be seen 45.2465 + // in same cycle (causing a debug exception). Handle non 45.2466 + // -debug exception first! 45.2467 + if (non_debug_exception_x == `TRUE) 45.2468 + write_idx_m <= `LM32_EA_REG; 45.2469 + else if (debug_exception_x == `TRUE) 45.2470 + write_idx_m <= `LM32_BA_REG; 45.2471 + else 45.2472 + write_idx_m <= write_idx_x; 45.2473 +`else 45.2474 + if (exception_x == `TRUE) 45.2475 + write_idx_m <= `LM32_EA_REG; 45.2476 + else 45.2477 + write_idx_m <= write_idx_x; 45.2478 +`endif 45.2479 + condition_met_m <= condition_met_x; 45.2480 +`ifdef CFG_DEBUG_ENABLED 45.2481 + if (exception_x == `TRUE) 45.2482 + if ((dc_re == `TRUE) 45.2483 + || ((debug_exception_x == `TRUE) 45.2484 + && (non_debug_exception_x == `FALSE))) 45.2485 + branch_target_m <= {deba, eid_x, {3{1'b0}}}; 45.2486 + else 45.2487 + branch_target_m <= {eba, eid_x, {3{1'b0}}}; 45.2488 + else 45.2489 + branch_target_m <= branch_target_x; 45.2490 +`else 45.2491 + branch_target_m <= exception_x == `TRUE ? {eba, eid_x, {3{1'b0}}} : branch_target_x; 45.2492 +`endif 45.2493 +`ifdef CFG_TRACE_ENABLED 45.2494 + eid_m <= eid_x; 45.2495 +`endif 45.2496 +`ifdef CFG_DCACHE_ENABLED 45.2497 + dflush_m <= dflush_x; 45.2498 +`endif 45.2499 + eret_m <= eret_q_x; 45.2500 +`ifdef CFG_DEBUG_ENABLED 45.2501 + bret_m <= bret_q_x; 45.2502 +`endif 45.2503 + write_enable_m <= exception_x == `TRUE ? `TRUE : write_enable_x; 45.2504 +`ifdef CFG_DEBUG_ENABLED 45.2505 + debug_exception_m <= debug_exception_x; 45.2506 + non_debug_exception_m <= non_debug_exception_x; 45.2507 +`endif 45.2508 + end 45.2509 + 45.2510 + // State changing regs 45.2511 + if (stall_m == `FALSE) 45.2512 + begin 45.2513 + if ((exception_x == `TRUE) && (q_x == `TRUE) && (stall_x == `FALSE)) 45.2514 + exception_m <= `TRUE; 45.2515 + else 45.2516 + exception_m <= `FALSE; 45.2517 +`ifdef CFG_BUS_ERRORS_ENABLED 45.2518 + data_bus_error_exception_m <= (data_bus_error_exception == `TRUE) 45.2519 +`ifdef CFG_DEBUG_ENABLED 45.2520 + && (reset_exception == `FALSE) 45.2521 +`endif 45.2522 + ; 45.2523 +`endif 45.2524 + end 45.2525 + 45.2526 + // M/W stage registers 45.2527 +`ifdef CFG_BUS_ERRORS_ENABLED 45.2528 + operand_w <= exception_m == `TRUE ? (data_bus_error_exception_m ? {memop_pc_w, 2'b00} : {pc_m, 2'b00}) : m_result; 45.2529 +`else 45.2530 + operand_w <= exception_m == `TRUE ? {pc_m, 2'b00} : m_result; 45.2531 +`endif 45.2532 + w_result_sel_load_w <= w_result_sel_load_m; 45.2533 +`ifdef CFG_PL_MULTIPLY_ENABLED 45.2534 + w_result_sel_mul_w <= w_result_sel_mul_m; 45.2535 +`endif 45.2536 + write_idx_w <= write_idx_m; 45.2537 +`ifdef CFG_TRACE_ENABLED 45.2538 + eid_w <= eid_m; 45.2539 + eret_w <= eret_m; 45.2540 +`ifdef CFG_DEBUG_ENABLED 45.2541 + bret_w <= bret_m; 45.2542 +`endif 45.2543 +`endif 45.2544 + write_enable_w <= write_enable_m; 45.2545 +`ifdef CFG_DEBUG_ENABLED 45.2546 + debug_exception_w <= debug_exception_m; 45.2547 + non_debug_exception_w <= non_debug_exception_m; 45.2548 +`else 45.2549 + exception_w <= exception_m; 45.2550 +`endif 45.2551 +`ifdef CFG_BUS_ERRORS_ENABLED 45.2552 + if ( (stall_m == `FALSE) 45.2553 + && ( (load_q_m == `TRUE) 45.2554 + || (store_q_m == `TRUE) 45.2555 + ) 45.2556 + ) 45.2557 + memop_pc_w <= pc_m; 45.2558 +`endif 45.2559 + end 45.2560 +end 45.2561 + 45.2562 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE 45.2563 +// Buffer data read from register file, in case a stall occurs, and watch for 45.2564 +// any writes to the modified registers 45.2565 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 45.2566 +begin 45.2567 + if (rst_i == `TRUE) 45.2568 + begin 45.2569 + use_buf <= `FALSE; 45.2570 + reg_data_buf_0 <= {`LM32_WORD_WIDTH{1'b0}}; 45.2571 + reg_data_buf_1 <= {`LM32_WORD_WIDTH{1'b0}}; 45.2572 + end 45.2573 + else 45.2574 + begin 45.2575 + if (stall_d == `FALSE) 45.2576 + use_buf <= `FALSE; 45.2577 + else if (use_buf == `FALSE) 45.2578 + begin 45.2579 + reg_data_buf_0 <= reg_data_live_0; 45.2580 + reg_data_buf_1 <= reg_data_live_1; 45.2581 + use_buf <= `TRUE; 45.2582 + end 45.2583 + if (reg_write_enable_q_w == `TRUE) 45.2584 + begin 45.2585 + if (write_idx_w == read_idx_0_d) 45.2586 + reg_data_buf_0 <= w_result; 45.2587 + if (write_idx_w == read_idx_1_d) 45.2588 + reg_data_buf_1 <= w_result; 45.2589 + end 45.2590 + end 45.2591 +end 45.2592 +`endif 45.2593 + 45.2594 +`ifdef LM32_EBR_REGISTER_FILE 45.2595 +`else 45.2596 +// Register file write port 45.2597 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 45.2598 +begin 45.2599 + if (rst_i == `TRUE) begin 45.2600 + registers[0] <= {`LM32_WORD_WIDTH{1'b0}}; 45.2601 + registers[1] <= {`LM32_WORD_WIDTH{1'b0}}; 45.2602 + registers[2] <= {`LM32_WORD_WIDTH{1'b0}}; 45.2603 + registers[3] <= {`LM32_WORD_WIDTH{1'b0}}; 45.2604 + registers[4] <= {`LM32_WORD_WIDTH{1'b0}}; 45.2605 + registers[5] <= {`LM32_WORD_WIDTH{1'b0}}; 45.2606 + registers[6] <= {`LM32_WORD_WIDTH{1'b0}}; 45.2607 + registers[7] <= {`LM32_WORD_WIDTH{1'b0}}; 45.2608 + registers[8] <= {`LM32_WORD_WIDTH{1'b0}}; 45.2609 + registers[9] <= {`LM32_WORD_WIDTH{1'b0}}; 45.2610 + registers[10] <= {`LM32_WORD_WIDTH{1'b0}}; 45.2611 + registers[11] <= {`LM32_WORD_WIDTH{1'b0}}; 45.2612 + registers[12] <= {`LM32_WORD_WIDTH{1'b0}}; 45.2613 + registers[13] <= {`LM32_WORD_WIDTH{1'b0}}; 45.2614 + registers[14] <= {`LM32_WORD_WIDTH{1'b0}}; 45.2615 + registers[15] <= {`LM32_WORD_WIDTH{1'b0}}; 45.2616 + registers[16] <= {`LM32_WORD_WIDTH{1'b0}}; 45.2617 + registers[17] <= {`LM32_WORD_WIDTH{1'b0}}; 45.2618 + registers[18] <= {`LM32_WORD_WIDTH{1'b0}}; 45.2619 + registers[19] <= {`LM32_WORD_WIDTH{1'b0}}; 45.2620 + registers[20] <= {`LM32_WORD_WIDTH{1'b0}}; 45.2621 + registers[21] <= {`LM32_WORD_WIDTH{1'b0}}; 45.2622 + registers[22] <= {`LM32_WORD_WIDTH{1'b0}}; 45.2623 + registers[23] <= {`LM32_WORD_WIDTH{1'b0}}; 45.2624 + registers[24] <= {`LM32_WORD_WIDTH{1'b0}}; 45.2625 + registers[25] <= {`LM32_WORD_WIDTH{1'b0}}; 45.2626 + registers[26] <= {`LM32_WORD_WIDTH{1'b0}}; 45.2627 + registers[27] <= {`LM32_WORD_WIDTH{1'b0}}; 45.2628 + registers[28] <= {`LM32_WORD_WIDTH{1'b0}}; 45.2629 + registers[29] <= {`LM32_WORD_WIDTH{1'b0}}; 45.2630 + registers[30] <= {`LM32_WORD_WIDTH{1'b0}}; 45.2631 + registers[31] <= {`LM32_WORD_WIDTH{1'b0}}; 45.2632 + end 45.2633 + else begin 45.2634 + if (reg_write_enable_q_w == `TRUE) 45.2635 + registers[write_idx_w] <= w_result; 45.2636 + end 45.2637 +end 45.2638 +`endif 45.2639 + 45.2640 +`ifdef CFG_TRACE_ENABLED 45.2641 +// PC tracing logic 45.2642 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 45.2643 +begin 45.2644 + if (rst_i == `TRUE) 45.2645 + begin 45.2646 + trace_pc_valid <= `FALSE; 45.2647 + trace_pc <= {`LM32_PC_WIDTH{1'b0}}; 45.2648 + trace_exception <= `FALSE; 45.2649 + trace_eid <= `LM32_EID_RESET; 45.2650 + trace_eret <= `FALSE; 45.2651 +`ifdef CFG_DEBUG_ENABLED 45.2652 + trace_bret <= `FALSE; 45.2653 +`endif 45.2654 + pc_c <= `CFG_EBA_RESET/4; 45.2655 + end 45.2656 + else 45.2657 + begin 45.2658 + trace_pc_valid <= `FALSE; 45.2659 + // Has an exception occured 45.2660 +`ifdef CFG_DEBUG_ENABLED 45.2661 + if ((debug_exception_q_w == `TRUE) || (non_debug_exception_q_w == `TRUE)) 45.2662 +`else 45.2663 + if (exception_q_w == `TRUE) 45.2664 +`endif 45.2665 + begin 45.2666 + trace_exception <= `TRUE; 45.2667 + trace_pc_valid <= `TRUE; 45.2668 + trace_pc <= pc_w; 45.2669 + trace_eid <= eid_w; 45.2670 + end 45.2671 + else 45.2672 + trace_exception <= `FALSE; 45.2673 + 45.2674 + if ((valid_w == `TRUE) && (!kill_w)) 45.2675 + begin 45.2676 + // An instruction is commiting. Determine if it is non-sequential 45.2677 + if (pc_c + 1'b1 != pc_w) 45.2678 + begin 45.2679 + // Non-sequential instruction 45.2680 + trace_pc_valid <= `TRUE; 45.2681 + trace_pc <= pc_w; 45.2682 + end 45.2683 + // Record PC so we can determine if next instruction is sequential or not 45.2684 + pc_c <= pc_w; 45.2685 + // Indicate if it was an eret/bret instruction 45.2686 + trace_eret <= eret_w; 45.2687 +`ifdef CFG_DEBUG_ENABLED 45.2688 + trace_bret <= bret_w; 45.2689 +`endif 45.2690 + end 45.2691 + else 45.2692 + begin 45.2693 + trace_eret <= `FALSE; 45.2694 +`ifdef CFG_DEBUG_ENABLED 45.2695 + trace_bret <= `FALSE; 45.2696 +`endif 45.2697 + end 45.2698 + end 45.2699 +end 45.2700 +`endif 45.2701 + 45.2702 +///////////////////////////////////////////////////// 45.2703 +// Behavioural Logic 45.2704 +///////////////////////////////////////////////////// 45.2705 + 45.2706 +// synthesis translate_off 45.2707 + 45.2708 +// Reset register 0. Only needed for simulation. 45.2709 +initial 45.2710 +begin 45.2711 +`ifdef LM32_EBR_REGISTER_FILE 45.2712 + reg_0.mem[0] = {`LM32_WORD_WIDTH{1'b0}}; 45.2713 + reg_1.mem[0] = {`LM32_WORD_WIDTH{1'b0}}; 45.2714 +`else 45.2715 + registers[0] = {`LM32_WORD_WIDTH{1'b0}}; 45.2716 +`endif 45.2717 +end 45.2718 + 45.2719 +// synthesis translate_on 45.2720 + 45.2721 +endmodule
46.1 diff -r 252df75c8f67 -r c336e674a37e rtl/lm32_dcache.v 46.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 46.3 +++ b/rtl/lm32_dcache.v Tue Mar 08 09:40:42 2011 +0000 46.4 @@ -0,0 +1,542 @@ 46.5 +// ============================================================================= 46.6 +// COPYRIGHT NOTICE 46.7 +// Copyright 2006 (c) Lattice Semiconductor Corporation 46.8 +// ALL RIGHTS RESERVED 46.9 +// This confidential and proprietary software may be used only as authorised by 46.10 +// a licensing agreement from Lattice Semiconductor Corporation. 46.11 +// The entire notice above must be reproduced on all authorized copies and 46.12 +// copies may only be made to the extent permitted by a licensing agreement from 46.13 +// Lattice Semiconductor Corporation. 46.14 +// 46.15 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 46.16 +// 5555 NE Moore Court 408-826-6000 (other locations) 46.17 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 46.18 +// U.S.A email: techsupport@latticesemi.com 46.19 +// =============================================================================/ 46.20 +// FILE DETAILS 46.21 +// Project : LatticeMico32 46.22 +// File : lm32_dcache.v 46.23 +// Title : Data cache 46.24 +// Dependencies : lm32_include.v 46.25 +// Version : 6.1.17 46.26 +// : Initial Release 46.27 +// Version : 7.0SP2, 3.0 46.28 +// : No Change 46.29 +// Version : 3.1 46.30 +// : Support for user-selected resource usage when implementing 46.31 +// : cache memory. Additional parameters must be defined when 46.32 +// : invoking lm32_ram.v 46.33 +// ============================================================================= 46.34 + 46.35 +`include "lm32_include.v" 46.36 + 46.37 +`ifdef CFG_DCACHE_ENABLED 46.38 + 46.39 +`define LM32_DC_ADDR_OFFSET_RNG addr_offset_msb:addr_offset_lsb 46.40 +`define LM32_DC_ADDR_SET_RNG addr_set_msb:addr_set_lsb 46.41 +`define LM32_DC_ADDR_TAG_RNG addr_tag_msb:addr_tag_lsb 46.42 +`define LM32_DC_ADDR_IDX_RNG addr_set_msb:addr_offset_lsb 46.43 + 46.44 +`define LM32_DC_TMEM_ADDR_WIDTH addr_set_width 46.45 +`define LM32_DC_TMEM_ADDR_RNG (`LM32_DC_TMEM_ADDR_WIDTH-1):0 46.46 +`define LM32_DC_DMEM_ADDR_WIDTH (addr_offset_width+addr_set_width) 46.47 +`define LM32_DC_DMEM_ADDR_RNG (`LM32_DC_DMEM_ADDR_WIDTH-1):0 46.48 + 46.49 +`define LM32_DC_TAGS_WIDTH (addr_tag_width+1) 46.50 +`define LM32_DC_TAGS_RNG (`LM32_DC_TAGS_WIDTH-1):0 46.51 +`define LM32_DC_TAGS_TAG_RNG (`LM32_DC_TAGS_WIDTH-1):1 46.52 +`define LM32_DC_TAGS_VALID_RNG 0 46.53 + 46.54 +`define LM32_DC_STATE_RNG 2:0 46.55 +`define LM32_DC_STATE_FLUSH 3'b001 46.56 +`define LM32_DC_STATE_CHECK 3'b010 46.57 +`define LM32_DC_STATE_REFILL 3'b100 46.58 + 46.59 +///////////////////////////////////////////////////// 46.60 +// Module interface 46.61 +///////////////////////////////////////////////////// 46.62 + 46.63 +module lm32_dcache ( 46.64 + // ----- Inputs ----- 46.65 + clk_i, 46.66 + rst_i, 46.67 + stall_a, 46.68 + stall_x, 46.69 + stall_m, 46.70 + address_x, 46.71 + address_m, 46.72 + load_q_m, 46.73 + store_q_m, 46.74 + store_data, 46.75 + store_byte_select, 46.76 + refill_ready, 46.77 + refill_data, 46.78 + dflush, 46.79 + // ----- Outputs ----- 46.80 + stall_request, 46.81 + restart_request, 46.82 + refill_request, 46.83 + refill_address, 46.84 + refilling, 46.85 + load_data 46.86 + ); 46.87 + 46.88 +///////////////////////////////////////////////////// 46.89 +// Parameters 46.90 +///////////////////////////////////////////////////// 46.91 + 46.92 +parameter associativity = 1; // Associativity of the cache (Number of ways) 46.93 +parameter sets = 512; // Number of sets 46.94 +parameter bytes_per_line = 16; // Number of bytes per cache line 46.95 +parameter base_address = 0; // Base address of cachable memory 46.96 +parameter limit = 0; // Limit (highest address) of cachable memory 46.97 + 46.98 +localparam addr_offset_width = clogb2(bytes_per_line)-1-2; 46.99 +localparam addr_set_width = clogb2(sets)-1; 46.100 +localparam addr_offset_lsb = 2; 46.101 +localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1); 46.102 +localparam addr_set_lsb = (addr_offset_msb+1); 46.103 +localparam addr_set_msb = (addr_set_lsb+addr_set_width-1); 46.104 +localparam addr_tag_lsb = (addr_set_msb+1); 46.105 +localparam addr_tag_msb = clogb2(`CFG_DCACHE_LIMIT-`CFG_DCACHE_BASE_ADDRESS)-1; 46.106 +localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1); 46.107 + 46.108 +///////////////////////////////////////////////////// 46.109 +// Inputs 46.110 +///////////////////////////////////////////////////// 46.111 + 46.112 +input clk_i; // Clock 46.113 +input rst_i; // Reset 46.114 + 46.115 +input stall_a; // Stall A stage 46.116 +input stall_x; // Stall X stage 46.117 +input stall_m; // Stall M stage 46.118 + 46.119 +input [`LM32_WORD_RNG] address_x; // X stage load/store address 46.120 +input [`LM32_WORD_RNG] address_m; // M stage load/store address 46.121 +input load_q_m; // Load instruction in M stage 46.122 +input store_q_m; // Store instruction in M stage 46.123 +input [`LM32_WORD_RNG] store_data; // Data to store 46.124 +input [`LM32_BYTE_SELECT_RNG] store_byte_select; // Which bytes in store data should be modified 46.125 + 46.126 +input refill_ready; // Indicates next word of refill data is ready 46.127 +input [`LM32_WORD_RNG] refill_data; // Refill data 46.128 + 46.129 +input dflush; // Indicates cache should be flushed 46.130 + 46.131 +///////////////////////////////////////////////////// 46.132 +// Outputs 46.133 +///////////////////////////////////////////////////// 46.134 + 46.135 +output stall_request; // Request pipeline be stalled because cache is busy 46.136 +wire stall_request; 46.137 +output restart_request; // Request to restart instruction that caused the cache miss 46.138 +reg restart_request; 46.139 +output refill_request; // Request a refill 46.140 +reg refill_request; 46.141 +output [`LM32_WORD_RNG] refill_address; // Address to refill from 46.142 +reg [`LM32_WORD_RNG] refill_address; 46.143 +output refilling; // Indicates if the cache is currently refilling 46.144 +reg refilling; 46.145 +output [`LM32_WORD_RNG] load_data; // Data read from cache 46.146 +wire [`LM32_WORD_RNG] load_data; 46.147 + 46.148 +///////////////////////////////////////////////////// 46.149 +// Internal nets and registers 46.150 +///////////////////////////////////////////////////// 46.151 + 46.152 +wire read_port_enable; // Cache memory read port clock enable 46.153 +wire write_port_enable; // Cache memory write port clock enable 46.154 +wire [0:associativity-1] way_tmem_we; // Tag memory write enable 46.155 +wire [0:associativity-1] way_dmem_we; // Data memory write enable 46.156 +wire [`LM32_WORD_RNG] way_data[0:associativity-1]; // Data read from data memory 46.157 +wire [`LM32_DC_TAGS_TAG_RNG] way_tag[0:associativity-1];// Tag read from tag memory 46.158 +wire [0:associativity-1] way_valid; // Indicates which ways are valid 46.159 +wire [0:associativity-1] way_match; // Indicates which ways matched 46.160 +wire miss; // Indicates no ways matched 46.161 + 46.162 +wire [`LM32_DC_TMEM_ADDR_RNG] tmem_read_address; // Tag memory read address 46.163 +wire [`LM32_DC_TMEM_ADDR_RNG] tmem_write_address; // Tag memory write address 46.164 +wire [`LM32_DC_DMEM_ADDR_RNG] dmem_read_address; // Data memory read address 46.165 +wire [`LM32_DC_DMEM_ADDR_RNG] dmem_write_address; // Data memory write address 46.166 +wire [`LM32_DC_TAGS_RNG] tmem_write_data; // Tag memory write data 46.167 +reg [`LM32_WORD_RNG] dmem_write_data; // Data memory write data 46.168 + 46.169 +reg [`LM32_DC_STATE_RNG] state; // Current state of FSM 46.170 +wire flushing; // Indicates if cache is currently flushing 46.171 +wire check; // Indicates if cache is currently checking for hits/misses 46.172 +wire refill; // Indicates if cache is currently refilling 46.173 + 46.174 +wire valid_store; // Indicates if there is a valid store instruction 46.175 +reg [associativity-1:0] refill_way_select; // Which way should be refilled 46.176 +reg [`LM32_DC_ADDR_OFFSET_RNG] refill_offset; // Which word in cache line should be refilled 46.177 +wire last_refill; // Indicates when on last cycle of cache refill 46.178 +reg [`LM32_DC_TMEM_ADDR_RNG] flush_set; // Which set is currently being flushed 46.179 + 46.180 +genvar i, j; 46.181 + 46.182 +///////////////////////////////////////////////////// 46.183 +// Functions 46.184 +///////////////////////////////////////////////////// 46.185 + 46.186 +`include "lm32_functions.v" 46.187 + 46.188 +///////////////////////////////////////////////////// 46.189 +// Instantiations 46.190 +///////////////////////////////////////////////////// 46.191 + 46.192 + generate 46.193 + for (i = 0; i < associativity; i = i + 1) 46.194 + begin : memories 46.195 + // Way data 46.196 + if (`LM32_DC_DMEM_ADDR_WIDTH < 11) 46.197 + begin : data_memories 46.198 + lm32_ram 46.199 + #( 46.200 + // ----- Parameters ------- 46.201 + .data_width (32), 46.202 + .address_width (`LM32_DC_DMEM_ADDR_WIDTH) 46.203 +`ifdef PLATFORM_LATTICE 46.204 + , 46.205 + `ifdef CFG_DCACHE_DAT_USE_DP_TRUE 46.206 + .RAM_IMPLEMENTATION ("EBR"), 46.207 + .RAM_TYPE ("RAM_DP_TRUE") 46.208 + `else 46.209 + `ifdef CFG_DCACHE_DAT_USE_SLICE 46.210 + .RAM_IMPLEMENTATION ("SLICE") 46.211 + `else 46.212 + .RAM_IMPLEMENTATION ("AUTO") 46.213 + `endif 46.214 + `endif 46.215 +`endif 46.216 + ) way_0_data_ram 46.217 + ( 46.218 + // ----- Inputs ------- 46.219 + .read_clk (clk_i), 46.220 + .write_clk (clk_i), 46.221 + .reset (rst_i), 46.222 + .read_address (dmem_read_address), 46.223 + .enable_read (read_port_enable), 46.224 + .write_address (dmem_write_address), 46.225 + .enable_write (write_port_enable), 46.226 + .write_enable (way_dmem_we[i]), 46.227 + .write_data (dmem_write_data), 46.228 + // ----- Outputs ------- 46.229 + .read_data (way_data[i]) 46.230 + ); 46.231 + end 46.232 + else 46.233 + begin 46.234 + for (j = 0; j < 4; j = j + 1) 46.235 + begin : byte_memories 46.236 + lm32_ram 46.237 + #( 46.238 + // ----- Parameters ------- 46.239 + .data_width (8), 46.240 + .address_width (`LM32_DC_DMEM_ADDR_WIDTH) 46.241 +`ifdef PLATFORM_LATTICE 46.242 + , 46.243 + `ifdef CFG_DCACHE_DAT_USE_DP_TRUE 46.244 + .RAM_IMPLEMENTATION ("EBR"), 46.245 + .RAM_TYPE ("RAM_DP_TRUE") 46.246 + `else 46.247 + `ifdef CFG_DCACHE_DAT_USE_SLICE 46.248 + .RAM_IMPLEMENTATION ("SLICE") 46.249 + `else 46.250 + .RAM_IMPLEMENTATION ("AUTO") 46.251 + `endif 46.252 + `endif 46.253 +`endif 46.254 + ) way_0_data_ram 46.255 + ( 46.256 + // ----- Inputs ------- 46.257 + .read_clk (clk_i), 46.258 + .write_clk (clk_i), 46.259 + .reset (rst_i), 46.260 + .read_address (dmem_read_address), 46.261 + .enable_read (read_port_enable), 46.262 + .write_address (dmem_write_address), 46.263 + .enable_write (write_port_enable), 46.264 + .write_enable (way_dmem_we[i] & (store_byte_select[j] | refill)), 46.265 + .write_data (dmem_write_data[(j+1)*8-1:j*8]), 46.266 + // ----- Outputs ------- 46.267 + .read_data (way_data[i][(j+1)*8-1:j*8]) 46.268 + ); 46.269 + end 46.270 + end 46.271 + 46.272 + // Way tags 46.273 + lm32_ram 46.274 + #( 46.275 + // ----- Parameters ------- 46.276 + .data_width (`LM32_DC_TAGS_WIDTH), 46.277 + .address_width (`LM32_DC_TMEM_ADDR_WIDTH) 46.278 +`ifdef PLATFORM_LATTICE 46.279 + , 46.280 + `ifdef CFG_DCACHE_DAT_USE_DP_TRUE 46.281 + .RAM_IMPLEMENTATION ("EBR"), 46.282 + .RAM_TYPE ("RAM_DP_TRUE") 46.283 + `else 46.284 + `ifdef CFG_DCACHE_DAT_USE_SLICE 46.285 + .RAM_IMPLEMENTATION ("SLICE") 46.286 + `else 46.287 + .RAM_IMPLEMENTATION ("AUTO") 46.288 + `endif 46.289 + `endif 46.290 +`endif 46.291 + ) way_0_tag_ram 46.292 + ( 46.293 + // ----- Inputs ------- 46.294 + .read_clk (clk_i), 46.295 + .write_clk (clk_i), 46.296 + .reset (rst_i), 46.297 + .read_address (tmem_read_address), 46.298 + .enable_read (read_port_enable), 46.299 + .write_address (tmem_write_address), 46.300 + .enable_write (`TRUE), 46.301 + .write_enable (way_tmem_we[i]), 46.302 + .write_data (tmem_write_data), 46.303 + // ----- Outputs ------- 46.304 + .read_data ({way_tag[i], way_valid[i]}) 46.305 + ); 46.306 + end 46.307 + 46.308 + endgenerate 46.309 + 46.310 +///////////////////////////////////////////////////// 46.311 +// Combinational logic 46.312 +///////////////////////////////////////////////////// 46.313 + 46.314 +// Compute which ways in the cache match the address being read 46.315 +generate 46.316 + for (i = 0; i < associativity; i = i + 1) 46.317 + begin : match 46.318 +assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_m[`LM32_DC_ADDR_TAG_RNG], `TRUE}); 46.319 + end 46.320 +endgenerate 46.321 + 46.322 +// Select data from way that matched the address being read 46.323 +generate 46.324 + if (associativity == 1) 46.325 + begin : data_1 46.326 +assign load_data = way_data[0]; 46.327 + end 46.328 + else if (associativity == 2) 46.329 + begin : data_2 46.330 +assign load_data = way_match[0] ? way_data[0] : way_data[1]; 46.331 + end 46.332 +endgenerate 46.333 + 46.334 +generate 46.335 + if (`LM32_DC_DMEM_ADDR_WIDTH < 11) 46.336 + begin 46.337 +// Select data to write to data memories 46.338 +always @(*) 46.339 +begin 46.340 + if (refill == `TRUE) 46.341 + dmem_write_data = refill_data; 46.342 + else 46.343 + begin 46.344 + dmem_write_data[`LM32_BYTE_0_RNG] = store_byte_select[0] ? store_data[`LM32_BYTE_0_RNG] : load_data[`LM32_BYTE_0_RNG]; 46.345 + dmem_write_data[`LM32_BYTE_1_RNG] = store_byte_select[1] ? store_data[`LM32_BYTE_1_RNG] : load_data[`LM32_BYTE_1_RNG]; 46.346 + dmem_write_data[`LM32_BYTE_2_RNG] = store_byte_select[2] ? store_data[`LM32_BYTE_2_RNG] : load_data[`LM32_BYTE_2_RNG]; 46.347 + dmem_write_data[`LM32_BYTE_3_RNG] = store_byte_select[3] ? store_data[`LM32_BYTE_3_RNG] : load_data[`LM32_BYTE_3_RNG]; 46.348 + end 46.349 +end 46.350 + end 46.351 + else 46.352 + begin 46.353 +// Select data to write to data memories - FIXME: Should use different write ports on dual port RAMs, but they don't work 46.354 +always @(*) 46.355 +begin 46.356 + if (refill == `TRUE) 46.357 + dmem_write_data = refill_data; 46.358 + else 46.359 + dmem_write_data = store_data; 46.360 +end 46.361 + end 46.362 +endgenerate 46.363 + 46.364 +// Compute address to use to index into the data memories 46.365 +generate 46.366 + if (bytes_per_line > 4) 46.367 +assign dmem_write_address = (refill == `TRUE) 46.368 + ? {refill_address[`LM32_DC_ADDR_SET_RNG], refill_offset} 46.369 + : address_m[`LM32_DC_ADDR_IDX_RNG]; 46.370 + else 46.371 +assign dmem_write_address = (refill == `TRUE) 46.372 + ? refill_address[`LM32_DC_ADDR_SET_RNG] 46.373 + : address_m[`LM32_DC_ADDR_IDX_RNG]; 46.374 +endgenerate 46.375 +assign dmem_read_address = address_x[`LM32_DC_ADDR_IDX_RNG]; 46.376 +// Compute address to use to index into the tag memories 46.377 +assign tmem_write_address = (flushing == `TRUE) 46.378 + ? flush_set 46.379 + : refill_address[`LM32_DC_ADDR_SET_RNG]; 46.380 +assign tmem_read_address = address_x[`LM32_DC_ADDR_SET_RNG]; 46.381 + 46.382 +// Compute signal to indicate when we are on the last refill accesses 46.383 +generate 46.384 + if (bytes_per_line > 4) 46.385 +assign last_refill = refill_offset == {addr_offset_width{1'b1}}; 46.386 + else 46.387 +assign last_refill = `TRUE; 46.388 +endgenerate 46.389 + 46.390 +// Compute data and tag memory access enable 46.391 +assign read_port_enable = (stall_x == `FALSE); 46.392 +assign write_port_enable = (refill_ready == `TRUE) || !stall_m; 46.393 + 46.394 +// Determine when we have a valid store 46.395 +assign valid_store = (store_q_m == `TRUE) && (check == `TRUE); 46.396 + 46.397 +// Compute data and tag memory write enables 46.398 +generate 46.399 + if (associativity == 1) 46.400 + begin : we_1 46.401 +assign way_dmem_we[0] = (refill_ready == `TRUE) || ((valid_store == `TRUE) && (way_match[0] == `TRUE)); 46.402 +assign way_tmem_we[0] = (refill_ready == `TRUE) || (flushing == `TRUE); 46.403 + end 46.404 + else 46.405 + begin : we_2 46.406 +assign way_dmem_we[0] = ((refill_ready == `TRUE) && (refill_way_select[0] == `TRUE)) || ((valid_store == `TRUE) && (way_match[0] == `TRUE)); 46.407 +assign way_dmem_we[1] = ((refill_ready == `TRUE) && (refill_way_select[1] == `TRUE)) || ((valid_store == `TRUE) && (way_match[1] == `TRUE)); 46.408 +assign way_tmem_we[0] = ((refill_ready == `TRUE) && (refill_way_select[0] == `TRUE)) || (flushing == `TRUE); 46.409 +assign way_tmem_we[1] = ((refill_ready == `TRUE) && (refill_way_select[1] == `TRUE)) || (flushing == `TRUE); 46.410 + end 46.411 +endgenerate 46.412 + 46.413 +// On the last refill cycle set the valid bit, for all other writes it should be cleared 46.414 +assign tmem_write_data[`LM32_DC_TAGS_VALID_RNG] = ((last_refill == `TRUE) || (valid_store == `TRUE)) && (flushing == `FALSE); 46.415 +assign tmem_write_data[`LM32_DC_TAGS_TAG_RNG] = refill_address[`LM32_DC_ADDR_TAG_RNG]; 46.416 + 46.417 +// Signals that indicate which state we are in 46.418 +assign flushing = state[0]; 46.419 +assign check = state[1]; 46.420 +assign refill = state[2]; 46.421 + 46.422 +assign miss = (~(|way_match)) && (load_q_m == `TRUE) && (stall_m == `FALSE); 46.423 +assign stall_request = (check == `FALSE); 46.424 + 46.425 +///////////////////////////////////////////////////// 46.426 +// Sequential logic 46.427 +///////////////////////////////////////////////////// 46.428 + 46.429 +// Record way selected for replacement on a cache miss 46.430 +generate 46.431 + if (associativity >= 2) 46.432 + begin : way_select 46.433 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 46.434 +begin 46.435 + if (rst_i == `TRUE) 46.436 + refill_way_select <= {{associativity-1{1'b0}}, 1'b1}; 46.437 + else 46.438 + begin 46.439 + if (refill_request == `TRUE) 46.440 + refill_way_select <= {refill_way_select[0], refill_way_select[1]}; 46.441 + end 46.442 +end 46.443 + end 46.444 +endgenerate 46.445 + 46.446 +// Record whether we are currently refilling 46.447 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 46.448 +begin 46.449 + if (rst_i == `TRUE) 46.450 + refilling <= `FALSE; 46.451 + else 46.452 + refilling <= refill; 46.453 +end 46.454 + 46.455 +// Instruction cache control FSM 46.456 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 46.457 +begin 46.458 + if (rst_i == `TRUE) 46.459 + begin 46.460 + state <= `LM32_DC_STATE_FLUSH; 46.461 + flush_set <= {`LM32_DC_TMEM_ADDR_WIDTH{1'b1}}; 46.462 + refill_request <= `FALSE; 46.463 + refill_address <= {`LM32_WORD_WIDTH{1'bx}}; 46.464 + restart_request <= `FALSE; 46.465 + end 46.466 + else 46.467 + begin 46.468 + case (state) 46.469 + 46.470 + // Flush the cache 46.471 + `LM32_DC_STATE_FLUSH: 46.472 + begin 46.473 + if (flush_set == {`LM32_DC_TMEM_ADDR_WIDTH{1'b0}}) 46.474 + state <= `LM32_DC_STATE_CHECK; 46.475 + flush_set <= flush_set - 1'b1; 46.476 + end 46.477 + 46.478 + // Check for cache misses 46.479 + `LM32_DC_STATE_CHECK: 46.480 + begin 46.481 + if (stall_a == `FALSE) 46.482 + restart_request <= `FALSE; 46.483 + if (miss == `TRUE) 46.484 + begin 46.485 + refill_request <= `TRUE; 46.486 + refill_address <= address_m; 46.487 + state <= `LM32_DC_STATE_REFILL; 46.488 + end 46.489 + else if (dflush == `TRUE) 46.490 + state <= `LM32_DC_STATE_FLUSH; 46.491 + end 46.492 + 46.493 + // Refill a cache line 46.494 + `LM32_DC_STATE_REFILL: 46.495 + begin 46.496 + refill_request <= `FALSE; 46.497 + if (refill_ready == `TRUE) 46.498 + begin 46.499 + if (last_refill == `TRUE) 46.500 + begin 46.501 + restart_request <= `TRUE; 46.502 + state <= `LM32_DC_STATE_CHECK; 46.503 + end 46.504 + end 46.505 + end 46.506 + 46.507 + endcase 46.508 + end 46.509 +end 46.510 + 46.511 +generate 46.512 + if (bytes_per_line > 4) 46.513 + begin 46.514 +// Refill offset 46.515 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 46.516 +begin 46.517 + if (rst_i == `TRUE) 46.518 + refill_offset <= {addr_offset_width{1'b0}}; 46.519 + else 46.520 + begin 46.521 + case (state) 46.522 + 46.523 + // Check for cache misses 46.524 + `LM32_DC_STATE_CHECK: 46.525 + begin 46.526 + if (miss == `TRUE) 46.527 + refill_offset <= {addr_offset_width{1'b0}}; 46.528 + end 46.529 + 46.530 + // Refill a cache line 46.531 + `LM32_DC_STATE_REFILL: 46.532 + begin 46.533 + if (refill_ready == `TRUE) 46.534 + refill_offset <= refill_offset + 1'b1; 46.535 + end 46.536 + 46.537 + endcase 46.538 + end 46.539 +end 46.540 + end 46.541 +endgenerate 46.542 + 46.543 +endmodule 46.544 + 46.545 +`endif 46.546 +
47.1 diff -r 252df75c8f67 -r c336e674a37e rtl/lm32_debug.v 47.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 47.3 +++ b/rtl/lm32_debug.v Tue Mar 08 09:40:42 2011 +0000 47.4 @@ -0,0 +1,348 @@ 47.5 +// ============================================================================= 47.6 +// COPYRIGHT NOTICE 47.7 +// Copyright 2006 (c) Lattice Semiconductor Corporation 47.8 +// ALL RIGHTS RESERVED 47.9 +// This confidential and proprietary software may be used only as authorised by 47.10 +// a licensing agreement from Lattice Semiconductor Corporation. 47.11 +// The entire notice above must be reproduced on all authorized copies and 47.12 +// copies may only be made to the extent permitted by a licensing agreement from 47.13 +// Lattice Semiconductor Corporation. 47.14 +// 47.15 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 47.16 +// 5555 NE Moore Court 408-826-6000 (other locations) 47.17 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 47.18 +// U.S.A email: techsupport@latticesemi.com 47.19 +// =============================================================================/ 47.20 +// FILE DETAILS 47.21 +// Project : LatticeMico32 47.22 +// File : lm32_debug.v 47.23 +// Title : Hardware debug registers and associated logic. 47.24 +// Dependencies : lm32_include.v 47.25 +// Version : 6.1.17 47.26 +// : Initial Release 47.27 +// Version : 7.0SP2, 3.0 47.28 +// : No Change 47.29 +// Version : 3.1 47.30 +// : No Change 47.31 +// Version : 3.2 47.32 +// : Fixed simulation bug which flares up when number of 47.33 +// : watchpoints is zero. 47.34 +// ============================================================================= 47.35 + 47.36 +`include "lm32_include.v" 47.37 + 47.38 +`ifdef CFG_DEBUG_ENABLED 47.39 + 47.40 +// States for single-step FSM 47.41 +`define LM32_DEBUG_SS_STATE_RNG 2:0 47.42 +`define LM32_DEBUG_SS_STATE_IDLE 3'b000 47.43 +`define LM32_DEBUG_SS_STATE_WAIT_FOR_RET 3'b001 47.44 +`define LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN 3'b010 47.45 +`define LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT 3'b011 47.46 +`define LM32_DEBUG_SS_STATE_RESTART 3'b100 47.47 + 47.48 +///////////////////////////////////////////////////// 47.49 +// Module interface 47.50 +///////////////////////////////////////////////////// 47.51 + 47.52 +module lm32_debug ( 47.53 + // ----- Inputs ------- 47.54 + clk_i, 47.55 + rst_i, 47.56 + pc_x, 47.57 + load_x, 47.58 + store_x, 47.59 + load_store_address_x, 47.60 + csr_write_enable_x, 47.61 + csr_write_data, 47.62 + csr_x, 47.63 +`ifdef CFG_HW_DEBUG_ENABLED 47.64 + jtag_csr_write_enable, 47.65 + jtag_csr_write_data, 47.66 + jtag_csr, 47.67 +`endif 47.68 +`ifdef LM32_SINGLE_STEP_ENABLED 47.69 + eret_q_x, 47.70 + bret_q_x, 47.71 + stall_x, 47.72 + exception_x, 47.73 + q_x, 47.74 +`ifdef CFG_DCACHE_ENABLED 47.75 + dcache_refill_request, 47.76 +`endif 47.77 +`endif 47.78 + // ----- Outputs ------- 47.79 +`ifdef LM32_SINGLE_STEP_ENABLED 47.80 + dc_ss, 47.81 +`endif 47.82 + dc_re, 47.83 + bp_match, 47.84 + wp_match 47.85 + ); 47.86 + 47.87 +///////////////////////////////////////////////////// 47.88 +// Parameters 47.89 +///////////////////////////////////////////////////// 47.90 + 47.91 +parameter breakpoints = 0; // Number of breakpoint CSRs 47.92 +parameter watchpoints = 0; // Number of watchpoint CSRs 47.93 + 47.94 +///////////////////////////////////////////////////// 47.95 +// Inputs 47.96 +///////////////////////////////////////////////////// 47.97 + 47.98 +input clk_i; // Clock 47.99 +input rst_i; // Reset 47.100 + 47.101 +input [`LM32_PC_RNG] pc_x; // X stage PC 47.102 +input load_x; // Load instruction in X stage 47.103 +input store_x; // Store instruction in X stage 47.104 +input [`LM32_WORD_RNG] load_store_address_x; // Load or store effective address 47.105 +input csr_write_enable_x; // wcsr instruction in X stage 47.106 +input [`LM32_WORD_RNG] csr_write_data; // Data to write to CSR 47.107 +input [`LM32_CSR_RNG] csr_x; // Which CSR to write 47.108 +`ifdef CFG_HW_DEBUG_ENABLED 47.109 +input jtag_csr_write_enable; // JTAG interface CSR write enable 47.110 +input [`LM32_WORD_RNG] jtag_csr_write_data; // Data to write to CSR 47.111 +input [`LM32_CSR_RNG] jtag_csr; // Which CSR to write 47.112 +`endif 47.113 +`ifdef LM32_SINGLE_STEP_ENABLED 47.114 +input eret_q_x; // eret instruction in X stage 47.115 +input bret_q_x; // bret instruction in X stage 47.116 +input stall_x; // Instruction in X stage is stalled 47.117 +input exception_x; // An exception has occured in X stage 47.118 +input q_x; // Indicates the instruction in the X stage is qualified 47.119 +`ifdef CFG_DCACHE_ENABLED 47.120 +input dcache_refill_request; // Indicates data cache wants to be refilled 47.121 +`endif 47.122 +`endif 47.123 + 47.124 +///////////////////////////////////////////////////// 47.125 +// Outputs 47.126 +///////////////////////////////////////////////////// 47.127 + 47.128 +`ifdef LM32_SINGLE_STEP_ENABLED 47.129 +output dc_ss; // Single-step enable 47.130 +reg dc_ss; 47.131 +`endif 47.132 +output dc_re; // Remap exceptions 47.133 +reg dc_re; 47.134 +output bp_match; // Indicates a breakpoint has matched 47.135 +wire bp_match; 47.136 +output wp_match; // Indicates a watchpoint has matched 47.137 +wire wp_match; 47.138 + 47.139 +///////////////////////////////////////////////////// 47.140 +// Internal nets and registers 47.141 +///////////////////////////////////////////////////// 47.142 + 47.143 +genvar i; // Loop index for generate statements 47.144 + 47.145 +// Debug CSRs 47.146 + 47.147 +reg [`LM32_PC_RNG] bp_a[0:breakpoints-1]; // Instruction breakpoint address 47.148 +reg bp_e[0:breakpoints-1]; // Instruction breakpoint enable 47.149 +wire [0:breakpoints-1]bp_match_n; // Indicates if a h/w instruction breakpoint matched 47.150 + 47.151 +reg [`LM32_WPC_C_RNG] wpc_c[0:watchpoints-1]; // Watchpoint enable 47.152 +reg [`LM32_WORD_RNG] wp[0:watchpoints-1]; // Watchpoint address 47.153 +wire [0:watchpoints]wp_match_n; // Indicates if a h/w data watchpoint matched 47.154 + 47.155 +wire debug_csr_write_enable; // Debug CSR write enable (from either a wcsr instruction of external debugger) 47.156 +wire [`LM32_WORD_RNG] debug_csr_write_data; // Data to write to debug CSR 47.157 +wire [`LM32_CSR_RNG] debug_csr; // Debug CSR to write to 47.158 + 47.159 +`ifdef LM32_SINGLE_STEP_ENABLED 47.160 +// FIXME: Declaring this as a reg causes ModelSim 6.1.15b to crash, so use integer for now 47.161 +//reg [`LM32_DEBUG_SS_STATE_RNG] state; // State of single-step FSM 47.162 +integer state; // State of single-step FSM 47.163 +`endif 47.164 + 47.165 +///////////////////////////////////////////////////// 47.166 +// Functions 47.167 +///////////////////////////////////////////////////// 47.168 + 47.169 +`include "lm32_functions.v" 47.170 + 47.171 +///////////////////////////////////////////////////// 47.172 +// Combinational Logic 47.173 +///////////////////////////////////////////////////// 47.174 + 47.175 +// Check for breakpoints 47.176 +generate 47.177 + for (i = 0; i < breakpoints; i = i + 1) 47.178 + begin : bp_comb 47.179 +assign bp_match_n[i] = ((bp_a[i] == pc_x) && (bp_e[i] == `TRUE)); 47.180 + end 47.181 +endgenerate 47.182 +generate 47.183 +`ifdef LM32_SINGLE_STEP_ENABLED 47.184 + if (breakpoints > 0) 47.185 +assign bp_match = (|bp_match_n) || (state == `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT); 47.186 + else 47.187 +assign bp_match = state == `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT; 47.188 +`else 47.189 + if (breakpoints > 0) 47.190 +assign bp_match = |bp_match_n; 47.191 + else 47.192 +assign bp_match = `FALSE; 47.193 +`endif 47.194 +endgenerate 47.195 + 47.196 +// Check for watchpoints 47.197 +generate 47.198 + for (i = 0; i < watchpoints; i = i + 1) 47.199 + begin : wp_comb 47.200 +assign wp_match_n[i] = (wp[i] == load_store_address_x) && ((load_x & wpc_c[i][0]) | (store_x & wpc_c[i][1])); 47.201 + end 47.202 +endgenerate 47.203 +generate 47.204 + if (watchpoints > 0) 47.205 +assign wp_match = |wp_match_n; 47.206 + else 47.207 +assign wp_match = `FALSE; 47.208 +endgenerate 47.209 + 47.210 +`ifdef CFG_HW_DEBUG_ENABLED 47.211 +// Multiplex between wcsr instruction writes and debugger writes to the debug CSRs 47.212 +assign debug_csr_write_enable = (csr_write_enable_x == `TRUE) || (jtag_csr_write_enable == `TRUE); 47.213 +assign debug_csr_write_data = jtag_csr_write_enable == `TRUE ? jtag_csr_write_data : csr_write_data; 47.214 +assign debug_csr = jtag_csr_write_enable == `TRUE ? jtag_csr : csr_x; 47.215 +`else 47.216 +assign debug_csr_write_enable = csr_write_enable_x; 47.217 +assign debug_csr_write_data = csr_write_data; 47.218 +assign debug_csr = csr_x; 47.219 +`endif 47.220 + 47.221 +///////////////////////////////////////////////////// 47.222 +// Sequential Logic 47.223 +///////////////////////////////////////////////////// 47.224 + 47.225 +// Breakpoint address and enable CSRs 47.226 +generate 47.227 + for (i = 0; i < breakpoints; i = i + 1) 47.228 + begin : bp_seq 47.229 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 47.230 +begin 47.231 + if (rst_i == `TRUE) 47.232 + begin 47.233 + bp_a[i] <= {`LM32_PC_WIDTH{1'bx}}; 47.234 + bp_e[i] <= `FALSE; 47.235 + end 47.236 + else 47.237 + begin 47.238 + if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_BP0 + i)) 47.239 + begin 47.240 + bp_a[i] <= debug_csr_write_data[`LM32_PC_RNG]; 47.241 + bp_e[i] <= debug_csr_write_data[0]; 47.242 + end 47.243 + end 47.244 +end 47.245 + end 47.246 +endgenerate 47.247 + 47.248 +// Watchpoint address and control flags CSRs 47.249 +generate 47.250 + for (i = 0; i < watchpoints; i = i + 1) 47.251 + begin : wp_seq 47.252 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 47.253 +begin 47.254 + if (rst_i == `TRUE) 47.255 + begin 47.256 + wp[i] <= {`LM32_WORD_WIDTH{1'bx}}; 47.257 + wpc_c[i] <= `LM32_WPC_C_DISABLED; 47.258 + end 47.259 + else 47.260 + begin 47.261 + if (debug_csr_write_enable == `TRUE) 47.262 + begin 47.263 + if (debug_csr == `LM32_CSR_DC) 47.264 + wpc_c[i] <= debug_csr_write_data[3+i*2:2+i*2]; 47.265 + if (debug_csr == `LM32_CSR_WP0 + i) 47.266 + wp[i] <= debug_csr_write_data; 47.267 + end 47.268 + end 47.269 +end 47.270 + end 47.271 +endgenerate 47.272 + 47.273 +// Remap exceptions control bit 47.274 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 47.275 +begin 47.276 + if (rst_i == `TRUE) 47.277 + dc_re <= `FALSE; 47.278 + else 47.279 + begin 47.280 + if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_DC)) 47.281 + dc_re <= debug_csr_write_data[1]; 47.282 + end 47.283 +end 47.284 + 47.285 +`ifdef LM32_SINGLE_STEP_ENABLED 47.286 +// Single-step control flag 47.287 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 47.288 +begin 47.289 + if (rst_i == `TRUE) 47.290 + begin 47.291 + state <= `LM32_DEBUG_SS_STATE_IDLE; 47.292 + dc_ss <= `FALSE; 47.293 + end 47.294 + else 47.295 + begin 47.296 + if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_DC)) 47.297 + begin 47.298 + dc_ss <= debug_csr_write_data[0]; 47.299 + if (debug_csr_write_data[0] == `FALSE) 47.300 + state <= `LM32_DEBUG_SS_STATE_IDLE; 47.301 + else 47.302 + state <= `LM32_DEBUG_SS_STATE_WAIT_FOR_RET; 47.303 + end 47.304 + case (state) 47.305 + `LM32_DEBUG_SS_STATE_WAIT_FOR_RET: 47.306 + begin 47.307 + // Wait for eret or bret instruction to be executed 47.308 + if ( ( (eret_q_x == `TRUE) 47.309 + || (bret_q_x == `TRUE) 47.310 + ) 47.311 + && (stall_x == `FALSE) 47.312 + ) 47.313 + state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 47.314 + end 47.315 + `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN: 47.316 + begin 47.317 + // Wait for an instruction to be executed 47.318 + if ((q_x == `TRUE) && (stall_x == `FALSE)) 47.319 + state <= `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT; 47.320 + end 47.321 + `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT: 47.322 + begin 47.323 + // Wait for exception to be raised 47.324 +`ifdef CFG_DCACHE_ENABLED 47.325 + if (dcache_refill_request == `TRUE) 47.326 + state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 47.327 + else 47.328 +`endif 47.329 + if ((exception_x == `TRUE) && (q_x == `TRUE) && (stall_x == `FALSE)) 47.330 + begin 47.331 + dc_ss <= `FALSE; 47.332 + state <= `LM32_DEBUG_SS_STATE_RESTART; 47.333 + end 47.334 + end 47.335 + `LM32_DEBUG_SS_STATE_RESTART: 47.336 + begin 47.337 + // Watch to see if stepped instruction is restarted due to a cache miss 47.338 +`ifdef CFG_DCACHE_ENABLED 47.339 + if (dcache_refill_request == `TRUE) 47.340 + state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 47.341 + else 47.342 +`endif 47.343 + state <= `LM32_DEBUG_SS_STATE_IDLE; 47.344 + end 47.345 + endcase 47.346 + end 47.347 +end 47.348 +`endif 47.349 + 47.350 +endmodule 47.351 + 47.352 +`endif
48.1 diff -r 252df75c8f67 -r c336e674a37e rtl/lm32_decoder.v 48.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 48.3 +++ b/rtl/lm32_decoder.v Tue Mar 08 09:40:42 2011 +0000 48.4 @@ -0,0 +1,583 @@ 48.5 +// ============================================================================= 48.6 +// COPYRIGHT NOTICE 48.7 +// Copyright 2006 (c) Lattice Semiconductor Corporation 48.8 +// ALL RIGHTS RESERVED 48.9 +// This confidential and proprietary software may be used only as authorised by 48.10 +// a licensing agreement from Lattice Semiconductor Corporation. 48.11 +// The entire notice above must be reproduced on all authorized copies and 48.12 +// copies may only be made to the extent permitted by a licensing agreement from 48.13 +// Lattice Semiconductor Corporation. 48.14 +// 48.15 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 48.16 +// 5555 NE Moore Court 408-826-6000 (other locations) 48.17 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 48.18 +// U.S.A email: techsupport@latticesemi.com 48.19 +// =============================================================================/ 48.20 +// FILE DETAILS 48.21 +// Project : LatticeMico32 48.22 +// File : lm32_decoder.v 48.23 +// Title : Instruction decoder 48.24 +// Dependencies : lm32_include.v 48.25 +// Version : 6.1.17 48.26 +// : Initial Release 48.27 +// Version : 7.0SP2, 3.0 48.28 +// : No Change 48.29 +// Version : 3.1 48.30 +// : Support for static branch prediction. Information about 48.31 +// : branch type is generated and passed on to the predictor. 48.32 +// Version : 3.2 48.33 +// : No change 48.34 +// Version : 3.3 48.35 +// : Renamed port names that conflict with keywords reserved 48.36 +// : in System-Verilog. 48.37 +// ============================================================================= 48.38 + 48.39 +`include "lm32_include.v" 48.40 + 48.41 +// Index of opcode field in an instruction 48.42 +`define LM32_OPCODE_RNG 31:26 48.43 +`define LM32_OP_RNG 30:26 48.44 + 48.45 +// Opcodes - Some are only listed as 5 bits as their MSB is a don't care 48.46 +`define LM32_OPCODE_ADD 5'b01101 48.47 +`define LM32_OPCODE_AND 5'b01000 48.48 +`define LM32_OPCODE_ANDHI 6'b011000 48.49 +`define LM32_OPCODE_B 6'b110000 48.50 +`define LM32_OPCODE_BI 6'b111000 48.51 +`define LM32_OPCODE_BE 6'b010001 48.52 +`define LM32_OPCODE_BG 6'b010010 48.53 +`define LM32_OPCODE_BGE 6'b010011 48.54 +`define LM32_OPCODE_BGEU 6'b010100 48.55 +`define LM32_OPCODE_BGU 6'b010101 48.56 +`define LM32_OPCODE_BNE 6'b010111 48.57 +`define LM32_OPCODE_CALL 6'b110110 48.58 +`define LM32_OPCODE_CALLI 6'b111110 48.59 +`define LM32_OPCODE_CMPE 5'b11001 48.60 +`define LM32_OPCODE_CMPG 5'b11010 48.61 +`define LM32_OPCODE_CMPGE 5'b11011 48.62 +`define LM32_OPCODE_CMPGEU 5'b11100 48.63 +`define LM32_OPCODE_CMPGU 5'b11101 48.64 +`define LM32_OPCODE_CMPNE 5'b11111 48.65 +`define LM32_OPCODE_DIVU 6'b100011 48.66 +`define LM32_OPCODE_LB 6'b000100 48.67 +`define LM32_OPCODE_LBU 6'b010000 48.68 +`define LM32_OPCODE_LH 6'b000111 48.69 +`define LM32_OPCODE_LHU 6'b001011 48.70 +`define LM32_OPCODE_LW 6'b001010 48.71 +`define LM32_OPCODE_MODU 6'b110001 48.72 +`define LM32_OPCODE_MUL 5'b00010 48.73 +`define LM32_OPCODE_NOR 5'b00001 48.74 +`define LM32_OPCODE_OR 5'b01110 48.75 +`define LM32_OPCODE_ORHI 6'b011110 48.76 +`define LM32_OPCODE_RAISE 6'b101011 48.77 +`define LM32_OPCODE_RCSR 6'b100100 48.78 +`define LM32_OPCODE_SB 6'b001100 48.79 +`define LM32_OPCODE_SEXTB 6'b101100 48.80 +`define LM32_OPCODE_SEXTH 6'b110111 48.81 +`define LM32_OPCODE_SH 6'b000011 48.82 +`define LM32_OPCODE_SL 5'b01111 48.83 +`define LM32_OPCODE_SR 5'b00101 48.84 +`define LM32_OPCODE_SRU 5'b00000 48.85 +`define LM32_OPCODE_SUB 6'b110010 48.86 +`define LM32_OPCODE_SW 6'b010110 48.87 +`define LM32_OPCODE_USER 6'b110011 48.88 +`define LM32_OPCODE_WCSR 6'b110100 48.89 +`define LM32_OPCODE_XNOR 5'b01001 48.90 +`define LM32_OPCODE_XOR 5'b00110 48.91 + 48.92 +///////////////////////////////////////////////////// 48.93 +// Module interface 48.94 +///////////////////////////////////////////////////// 48.95 + 48.96 +module lm32_decoder ( 48.97 + // ----- Inputs ------- 48.98 + instruction, 48.99 + // ----- Outputs ------- 48.100 + d_result_sel_0, 48.101 + d_result_sel_1, 48.102 + x_result_sel_csr, 48.103 +`ifdef LM32_MC_ARITHMETIC_ENABLED 48.104 + x_result_sel_mc_arith, 48.105 +`endif 48.106 +`ifdef LM32_NO_BARREL_SHIFT 48.107 + x_result_sel_shift, 48.108 +`endif 48.109 +`ifdef CFG_SIGN_EXTEND_ENABLED 48.110 + x_result_sel_sext, 48.111 +`endif 48.112 + x_result_sel_logic, 48.113 +`ifdef CFG_USER_ENABLED 48.114 + x_result_sel_user, 48.115 +`endif 48.116 + x_result_sel_add, 48.117 + m_result_sel_compare, 48.118 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 48.119 + m_result_sel_shift, 48.120 +`endif 48.121 + w_result_sel_load, 48.122 +`ifdef CFG_PL_MULTIPLY_ENABLED 48.123 + w_result_sel_mul, 48.124 +`endif 48.125 + x_bypass_enable, 48.126 + m_bypass_enable, 48.127 + read_enable_0, 48.128 + read_idx_0, 48.129 + read_enable_1, 48.130 + read_idx_1, 48.131 + write_enable, 48.132 + write_idx, 48.133 + immediate, 48.134 + branch_offset, 48.135 + load, 48.136 + store, 48.137 + size, 48.138 + sign_extend, 48.139 + adder_op, 48.140 + logic_op, 48.141 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 48.142 + direction, 48.143 +`endif 48.144 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED 48.145 + shift_left, 48.146 + shift_right, 48.147 +`endif 48.148 +`ifdef CFG_MC_MULTIPLY_ENABLED 48.149 + multiply, 48.150 +`endif 48.151 +`ifdef CFG_MC_DIVIDE_ENABLED 48.152 + divide, 48.153 + modulus, 48.154 +`endif 48.155 + branch, 48.156 + branch_reg, 48.157 + condition, 48.158 + bi_conditional, 48.159 + bi_unconditional, 48.160 +`ifdef CFG_DEBUG_ENABLED 48.161 + break_opcode, 48.162 +`endif 48.163 + scall, 48.164 + eret, 48.165 +`ifdef CFG_DEBUG_ENABLED 48.166 + bret, 48.167 +`endif 48.168 +`ifdef CFG_USER_ENABLED 48.169 + user_opcode, 48.170 +`endif 48.171 + csr_write_enable 48.172 + ); 48.173 + 48.174 +///////////////////////////////////////////////////// 48.175 +// Inputs 48.176 +///////////////////////////////////////////////////// 48.177 + 48.178 +input [`LM32_INSTRUCTION_RNG] instruction; // Instruction to decode 48.179 + 48.180 +///////////////////////////////////////////////////// 48.181 +// Outputs 48.182 +///////////////////////////////////////////////////// 48.183 + 48.184 +output [`LM32_D_RESULT_SEL_0_RNG] d_result_sel_0; 48.185 +reg [`LM32_D_RESULT_SEL_0_RNG] d_result_sel_0; 48.186 +output [`LM32_D_RESULT_SEL_1_RNG] d_result_sel_1; 48.187 +reg [`LM32_D_RESULT_SEL_1_RNG] d_result_sel_1; 48.188 +output x_result_sel_csr; 48.189 +reg x_result_sel_csr; 48.190 +`ifdef LM32_MC_ARITHMETIC_ENABLED 48.191 +output x_result_sel_mc_arith; 48.192 +reg x_result_sel_mc_arith; 48.193 +`endif 48.194 +`ifdef LM32_NO_BARREL_SHIFT 48.195 +output x_result_sel_shift; 48.196 +reg x_result_sel_shift; 48.197 +`endif 48.198 +`ifdef CFG_SIGN_EXTEND_ENABLED 48.199 +output x_result_sel_sext; 48.200 +reg x_result_sel_sext; 48.201 +`endif 48.202 +output x_result_sel_logic; 48.203 +reg x_result_sel_logic; 48.204 +`ifdef CFG_USER_ENABLED 48.205 +output x_result_sel_user; 48.206 +reg x_result_sel_user; 48.207 +`endif 48.208 +output x_result_sel_add; 48.209 +reg x_result_sel_add; 48.210 +output m_result_sel_compare; 48.211 +reg m_result_sel_compare; 48.212 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 48.213 +output m_result_sel_shift; 48.214 +reg m_result_sel_shift; 48.215 +`endif 48.216 +output w_result_sel_load; 48.217 +reg w_result_sel_load; 48.218 +`ifdef CFG_PL_MULTIPLY_ENABLED 48.219 +output w_result_sel_mul; 48.220 +reg w_result_sel_mul; 48.221 +`endif 48.222 +output x_bypass_enable; 48.223 +wire x_bypass_enable; 48.224 +output m_bypass_enable; 48.225 +wire m_bypass_enable; 48.226 +output read_enable_0; 48.227 +wire read_enable_0; 48.228 +output [`LM32_REG_IDX_RNG] read_idx_0; 48.229 +wire [`LM32_REG_IDX_RNG] read_idx_0; 48.230 +output read_enable_1; 48.231 +wire read_enable_1; 48.232 +output [`LM32_REG_IDX_RNG] read_idx_1; 48.233 +wire [`LM32_REG_IDX_RNG] read_idx_1; 48.234 +output write_enable; 48.235 +wire write_enable; 48.236 +output [`LM32_REG_IDX_RNG] write_idx; 48.237 +wire [`LM32_REG_IDX_RNG] write_idx; 48.238 +output [`LM32_WORD_RNG] immediate; 48.239 +wire [`LM32_WORD_RNG] immediate; 48.240 +output [`LM32_PC_RNG] branch_offset; 48.241 +wire [`LM32_PC_RNG] branch_offset; 48.242 +output load; 48.243 +wire load; 48.244 +output store; 48.245 +wire store; 48.246 +output [`LM32_SIZE_RNG] size; 48.247 +wire [`LM32_SIZE_RNG] size; 48.248 +output sign_extend; 48.249 +wire sign_extend; 48.250 +output adder_op; 48.251 +wire adder_op; 48.252 +output [`LM32_LOGIC_OP_RNG] logic_op; 48.253 +wire [`LM32_LOGIC_OP_RNG] logic_op; 48.254 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 48.255 +output direction; 48.256 +wire direction; 48.257 +`endif 48.258 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED 48.259 +output shift_left; 48.260 +wire shift_left; 48.261 +output shift_right; 48.262 +wire shift_right; 48.263 +`endif 48.264 +`ifdef CFG_MC_MULTIPLY_ENABLED 48.265 +output multiply; 48.266 +wire multiply; 48.267 +`endif 48.268 +`ifdef CFG_MC_DIVIDE_ENABLED 48.269 +output divide; 48.270 +wire divide; 48.271 +output modulus; 48.272 +wire modulus; 48.273 +`endif 48.274 +output branch; 48.275 +wire branch; 48.276 +output branch_reg; 48.277 +wire branch_reg; 48.278 +output [`LM32_CONDITION_RNG] condition; 48.279 +wire [`LM32_CONDITION_RNG] condition; 48.280 +output bi_conditional; 48.281 +wire bi_conditional; 48.282 +output bi_unconditional; 48.283 +wire bi_unconditional; 48.284 +`ifdef CFG_DEBUG_ENABLED 48.285 +output break_opcode; 48.286 +wire break_opcode; 48.287 +`endif 48.288 +output scall; 48.289 +wire scall; 48.290 +output eret; 48.291 +wire eret; 48.292 +`ifdef CFG_DEBUG_ENABLED 48.293 +output bret; 48.294 +wire bret; 48.295 +`endif 48.296 +`ifdef CFG_USER_ENABLED 48.297 +output [`LM32_USER_OPCODE_RNG] user_opcode; 48.298 +wire [`LM32_USER_OPCODE_RNG] user_opcode; 48.299 +`endif 48.300 +output csr_write_enable; 48.301 +wire csr_write_enable; 48.302 + 48.303 +///////////////////////////////////////////////////// 48.304 +// Internal nets and registers 48.305 +///////////////////////////////////////////////////// 48.306 + 48.307 +wire [`LM32_WORD_RNG] extended_immediate; // Zero or sign extended immediate 48.308 +wire [`LM32_WORD_RNG] high_immediate; // Immediate as high 16 bits 48.309 +wire [`LM32_WORD_RNG] call_immediate; // Call immediate 48.310 +wire [`LM32_WORD_RNG] branch_immediate; // Conditional branch immediate 48.311 +wire sign_extend_immediate; // Whether the immediate should be sign extended (`TRUE) or zero extended (`FALSE) 48.312 +wire select_high_immediate; // Whether to select the high immediate 48.313 +wire select_call_immediate; // Whether to select the call immediate 48.314 + 48.315 +///////////////////////////////////////////////////// 48.316 +// Functions 48.317 +///////////////////////////////////////////////////// 48.318 + 48.319 +`include "lm32_functions.v" 48.320 + 48.321 +///////////////////////////////////////////////////// 48.322 +// Combinational logic 48.323 +///////////////////////////////////////////////////// 48.324 + 48.325 +// Determine opcode 48.326 +assign op_add = instruction[`LM32_OP_RNG] == `LM32_OPCODE_ADD; 48.327 +assign op_and = instruction[`LM32_OP_RNG] == `LM32_OPCODE_AND; 48.328 +assign op_andhi = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_ANDHI; 48.329 +assign op_b = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_B; 48.330 +assign op_bi = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BI; 48.331 +assign op_be = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BE; 48.332 +assign op_bg = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BG; 48.333 +assign op_bge = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BGE; 48.334 +assign op_bgeu = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BGEU; 48.335 +assign op_bgu = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BGU; 48.336 +assign op_bne = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BNE; 48.337 +assign op_call = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_CALL; 48.338 +assign op_calli = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_CALLI; 48.339 +assign op_cmpe = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPE; 48.340 +assign op_cmpg = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPG; 48.341 +assign op_cmpge = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPGE; 48.342 +assign op_cmpgeu = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPGEU; 48.343 +assign op_cmpgu = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPGU; 48.344 +assign op_cmpne = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPNE; 48.345 +`ifdef CFG_MC_DIVIDE_ENABLED 48.346 +assign op_divu = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_DIVU; 48.347 +`endif 48.348 +assign op_lb = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LB; 48.349 +assign op_lbu = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LBU; 48.350 +assign op_lh = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LH; 48.351 +assign op_lhu = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LHU; 48.352 +assign op_lw = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LW; 48.353 +`ifdef CFG_MC_DIVIDE_ENABLED 48.354 +assign op_modu = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_MODU; 48.355 +`endif 48.356 +`ifdef LM32_MULTIPLY_ENABLED 48.357 +assign op_mul = instruction[`LM32_OP_RNG] == `LM32_OPCODE_MUL; 48.358 +`endif 48.359 +assign op_nor = instruction[`LM32_OP_RNG] == `LM32_OPCODE_NOR; 48.360 +assign op_or = instruction[`LM32_OP_RNG] == `LM32_OPCODE_OR; 48.361 +assign op_orhi = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_ORHI; 48.362 +assign op_raise = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_RAISE; 48.363 +assign op_rcsr = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_RCSR; 48.364 +assign op_sb = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SB; 48.365 +`ifdef CFG_SIGN_EXTEND_ENABLED 48.366 +assign op_sextb = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SEXTB; 48.367 +assign op_sexth = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SEXTH; 48.368 +`endif 48.369 +assign op_sh = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SH; 48.370 +`ifdef LM32_BARREL_SHIFT_ENABLED 48.371 +assign op_sl = instruction[`LM32_OP_RNG] == `LM32_OPCODE_SL; 48.372 +`endif 48.373 +assign op_sr = instruction[`LM32_OP_RNG] == `LM32_OPCODE_SR; 48.374 +assign op_sru = instruction[`LM32_OP_RNG] == `LM32_OPCODE_SRU; 48.375 +assign op_sub = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SUB; 48.376 +assign op_sw = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SW; 48.377 +assign op_user = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_USER; 48.378 +assign op_wcsr = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_WCSR; 48.379 +assign op_xnor = instruction[`LM32_OP_RNG] == `LM32_OPCODE_XNOR; 48.380 +assign op_xor = instruction[`LM32_OP_RNG] == `LM32_OPCODE_XOR; 48.381 + 48.382 +// Group opcodes by function 48.383 +assign arith = op_add | op_sub; 48.384 +assign logical = op_and | op_andhi | op_nor | op_or | op_orhi | op_xor | op_xnor; 48.385 +assign cmp = op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne; 48.386 +assign bi_conditional = op_be | op_bg | op_bge | op_bgeu | op_bgu | op_bne; 48.387 +assign bi_unconditional = op_bi; 48.388 +assign bra = op_b | bi_unconditional | bi_conditional; 48.389 +assign call = op_call | op_calli; 48.390 +`ifdef LM32_BARREL_SHIFT_ENABLED 48.391 +assign shift = op_sl | op_sr | op_sru; 48.392 +`endif 48.393 +`ifdef LM32_NO_BARREL_SHIFT 48.394 +assign shift = op_sr | op_sru; 48.395 +`endif 48.396 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED 48.397 +assign shift_left = op_sl; 48.398 +assign shift_right = op_sr | op_sru; 48.399 +`endif 48.400 +`ifdef CFG_SIGN_EXTEND_ENABLED 48.401 +assign sext = op_sextb | op_sexth; 48.402 +`endif 48.403 +`ifdef LM32_MULTIPLY_ENABLED 48.404 +assign multiply = op_mul; 48.405 +`endif 48.406 +`ifdef CFG_MC_DIVIDE_ENABLED 48.407 +assign divide = op_divu; 48.408 +assign modulus = op_modu; 48.409 +`endif 48.410 +assign load = op_lb | op_lbu | op_lh | op_lhu | op_lw; 48.411 +assign store = op_sb | op_sh | op_sw; 48.412 + 48.413 +// Select pipeline multiplexor controls 48.414 +always @(*) 48.415 +begin 48.416 + // D stage 48.417 + if (call) 48.418 + d_result_sel_0 = `LM32_D_RESULT_SEL_0_NEXT_PC; 48.419 + else 48.420 + d_result_sel_0 = `LM32_D_RESULT_SEL_0_REG_0; 48.421 + if (call) 48.422 + d_result_sel_1 = `LM32_D_RESULT_SEL_1_ZERO; 48.423 + else if ((instruction[31] == 1'b0) && !bra) 48.424 + d_result_sel_1 = `LM32_D_RESULT_SEL_1_IMMEDIATE; 48.425 + else 48.426 + d_result_sel_1 = `LM32_D_RESULT_SEL_1_REG_1; 48.427 + // X stage 48.428 + x_result_sel_csr = `FALSE; 48.429 +`ifdef LM32_MC_ARITHMETIC_ENABLED 48.430 + x_result_sel_mc_arith = `FALSE; 48.431 +`endif 48.432 +`ifdef LM32_NO_BARREL_SHIFT 48.433 + x_result_sel_shift = `FALSE; 48.434 +`endif 48.435 +`ifdef CFG_SIGN_EXTEND_ENABLED 48.436 + x_result_sel_sext = `FALSE; 48.437 +`endif 48.438 + x_result_sel_logic = `FALSE; 48.439 +`ifdef CFG_USER_ENABLED 48.440 + x_result_sel_user = `FALSE; 48.441 +`endif 48.442 + x_result_sel_add = `FALSE; 48.443 + if (op_rcsr) 48.444 + x_result_sel_csr = `TRUE; 48.445 +`ifdef LM32_MC_ARITHMETIC_ENABLED 48.446 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED 48.447 + else if (shift_left | shift_right) 48.448 + x_result_sel_mc_arith = `TRUE; 48.449 +`endif 48.450 +`ifdef CFG_MC_DIVIDE_ENABLED 48.451 + else if (divide | modulus) 48.452 + x_result_sel_mc_arith = `TRUE; 48.453 +`endif 48.454 +`ifdef CFG_MC_MULTIPLY_ENABLED 48.455 + else if (multiply) 48.456 + x_result_sel_mc_arith = `TRUE; 48.457 +`endif 48.458 +`endif 48.459 +`ifdef LM32_NO_BARREL_SHIFT 48.460 + else if (shift) 48.461 + x_result_sel_shift = `TRUE; 48.462 +`endif 48.463 +`ifdef CFG_SIGN_EXTEND_ENABLED 48.464 + else if (sext) 48.465 + x_result_sel_sext = `TRUE; 48.466 +`endif 48.467 + else if (logical) 48.468 + x_result_sel_logic = `TRUE; 48.469 +`ifdef CFG_USER_ENABLED 48.470 + else if (op_user) 48.471 + x_result_sel_user = `TRUE; 48.472 +`endif 48.473 + else 48.474 + x_result_sel_add = `TRUE; 48.475 + 48.476 + // M stage 48.477 + 48.478 + m_result_sel_compare = cmp; 48.479 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 48.480 + m_result_sel_shift = shift; 48.481 +`endif 48.482 + 48.483 + // W stage 48.484 + w_result_sel_load = load; 48.485 +`ifdef CFG_PL_MULTIPLY_ENABLED 48.486 + w_result_sel_mul = op_mul; 48.487 +`endif 48.488 +end 48.489 + 48.490 +// Set if result is valid at end of X stage 48.491 +assign x_bypass_enable = arith 48.492 + | logical 48.493 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED 48.494 + | shift_left 48.495 + | shift_right 48.496 +`endif 48.497 +`ifdef CFG_MC_MULTIPLY_ENABLED 48.498 + | multiply 48.499 +`endif 48.500 +`ifdef CFG_MC_DIVIDE_ENABLED 48.501 + | divide 48.502 + | modulus 48.503 +`endif 48.504 +`ifdef LM32_NO_BARREL_SHIFT 48.505 + | shift 48.506 +`endif 48.507 +`ifdef CFG_SIGN_EXTEND_ENABLED 48.508 + | sext 48.509 +`endif 48.510 +`ifdef CFG_USER_ENABLED 48.511 + | op_user 48.512 +`endif 48.513 + | op_rcsr 48.514 + ; 48.515 +// Set if result is valid at end of M stage 48.516 +assign m_bypass_enable = x_bypass_enable 48.517 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 48.518 + | shift 48.519 +`endif 48.520 + | cmp 48.521 + ; 48.522 +// Register file read port 0 48.523 +assign read_enable_0 = ~(op_bi | op_calli); 48.524 +assign read_idx_0 = instruction[25:21]; 48.525 +// Register file read port 1 48.526 +assign read_enable_1 = ~(op_bi | op_calli | load); 48.527 +assign read_idx_1 = instruction[20:16]; 48.528 +// Register file write port 48.529 +assign write_enable = ~(bra | op_raise | store | op_wcsr); 48.530 +assign write_idx = call 48.531 + ? 5'd29 48.532 + : instruction[31] == 1'b0 48.533 + ? instruction[20:16] 48.534 + : instruction[15:11]; 48.535 + 48.536 +// Size of load/stores 48.537 +assign size = instruction[27:26]; 48.538 +// Whether to sign or zero extend 48.539 +assign sign_extend = instruction[28]; 48.540 +// Set adder_op to 1 to perform a subtraction 48.541 +assign adder_op = op_sub | op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne | bra; 48.542 +// Logic operation (and, or, etc) 48.543 +assign logic_op = instruction[29:26]; 48.544 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 48.545 +// Shift direction 48.546 +assign direction = instruction[29]; 48.547 +`endif 48.548 +// Control flow microcodes 48.549 +assign branch = bra | call; 48.550 +assign branch_reg = op_call | op_b; 48.551 +assign condition = instruction[28:26]; 48.552 +`ifdef CFG_DEBUG_ENABLED 48.553 +assign break_opcode = op_raise & ~instruction[2]; 48.554 +`endif 48.555 +assign scall = op_raise & instruction[2]; 48.556 +assign eret = op_b & (instruction[25:21] == 5'd30); 48.557 +`ifdef CFG_DEBUG_ENABLED 48.558 +assign bret = op_b & (instruction[25:21] == 5'd31); 48.559 +`endif 48.560 +`ifdef CFG_USER_ENABLED 48.561 +// Extract user opcode 48.562 +assign user_opcode = instruction[10:0]; 48.563 +`endif 48.564 +// CSR read/write 48.565 +assign csr_write_enable = op_wcsr; 48.566 + 48.567 +// Extract immediate from instruction 48.568 + 48.569 +assign sign_extend_immediate = ~(op_and | op_cmpgeu | op_cmpgu | op_nor | op_or | op_xnor | op_xor); 48.570 +assign select_high_immediate = op_andhi | op_orhi; 48.571 +assign select_call_immediate = instruction[31]; 48.572 + 48.573 +assign high_immediate = {instruction[15:0], 16'h0000}; 48.574 +assign extended_immediate = {{16{sign_extend_immediate & instruction[15]}}, instruction[15:0]}; 48.575 +assign call_immediate = {{6{instruction[25]}}, instruction[25:0]}; 48.576 +assign branch_immediate = {{16{instruction[15]}}, instruction[15:0]}; 48.577 + 48.578 +assign immediate = select_high_immediate == `TRUE 48.579 + ? high_immediate 48.580 + : extended_immediate; 48.581 + 48.582 +assign branch_offset = select_call_immediate == `TRUE 48.583 + ? call_immediate 48.584 + : branch_immediate; 48.585 + 48.586 +endmodule 48.587 +
49.1 diff -r 252df75c8f67 -r c336e674a37e rtl/lm32_dp_ram.v 49.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 49.3 +++ b/rtl/lm32_dp_ram.v Tue Mar 08 09:40:42 2011 +0000 49.4 @@ -0,0 +1,35 @@ 49.5 +module lm32_dp_ram( 49.6 + clk_i, 49.7 + rst_i, 49.8 + we_i, 49.9 + waddr_i, 49.10 + wdata_i, 49.11 + raddr_i, 49.12 + rdata_o); 49.13 + 49.14 +parameter addr_width = 32; 49.15 +parameter addr_depth = 1024; 49.16 +parameter data_width = 8; 49.17 + 49.18 +input clk_i; 49.19 +input rst_i; 49.20 +input we_i; 49.21 +input [addr_width-1:0] waddr_i; 49.22 +input [data_width-1:0] wdata_i; 49.23 +input [addr_width-1:0] raddr_i; 49.24 +output [data_width-1:0] rdata_o; 49.25 + 49.26 +reg [data_width-1:0] ram[addr_depth-1:0]; 49.27 + 49.28 +reg [addr_width-1:0] raddr_r; 49.29 +assign rdata_o = ram[raddr_r]; 49.30 + 49.31 +always @ (posedge clk_i) 49.32 +begin 49.33 + if (we_i) 49.34 + ram[waddr_i] <= wdata_i; 49.35 + raddr_r <= raddr_i; 49.36 +end 49.37 + 49.38 +endmodule 49.39 +
50.1 diff -r 252df75c8f67 -r c336e674a37e rtl/lm32_functions.v 50.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 50.3 +++ b/rtl/lm32_functions.v Tue Mar 08 09:40:42 2011 +0000 50.4 @@ -0,0 +1,49 @@ 50.5 +// ============================================================================= 50.6 +// COPYRIGHT NOTICE 50.7 +// Copyright 2006 (c) Lattice Semiconductor Corporation 50.8 +// ALL RIGHTS RESERVED 50.9 +// This confidential and proprietary software may be used only as authorised by 50.10 +// a licensing agreement from Lattice Semiconductor Corporation. 50.11 +// The entire notice above must be reproduced on all authorized copies and 50.12 +// copies may only be made to the extent permitted by a licensing agreement from 50.13 +// Lattice Semiconductor Corporation. 50.14 +// 50.15 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 50.16 +// 5555 NE Moore Court 408-826-6000 (other locations) 50.17 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 50.18 +// U.S.A email: techsupport@latticesemi.com 50.19 +// =============================================================================/ 50.20 +// FILE DETAILS 50.21 +// Project : LatticeMico32 50.22 +// File : lm32_functions.v 50.23 +// Title : Common functions 50.24 +// Version : 6.1.17 50.25 +// : Initial Release 50.26 +// Version : 7.0SP2, 3.0 50.27 +// : No Change 50.28 +// Version : 3.5 50.29 +// : Added function to generate log-of-two that rounds-up to 50.30 +// : power-of-two 50.31 +// ============================================================================= 50.32 + 50.33 +function integer clogb2; 50.34 +input [31:0] value; 50.35 +begin 50.36 + for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) 50.37 + value = value >> 1; 50.38 +end 50.39 +endfunction 50.40 + 50.41 +function integer clogb2_v1; 50.42 +input [31:0] value; 50.43 +reg [31:0] i; 50.44 +reg [31:0] temp; 50.45 +begin 50.46 + temp = 0; 50.47 + i = 0; 50.48 + for (i = 0; temp < value; i = i + 1) 50.49 + temp = 1<<i; 50.50 + clogb2_v1 = i-1; 50.51 +end 50.52 +endfunction 50.53 +
51.1 diff -r 252df75c8f67 -r c336e674a37e rtl/lm32_icache.v 51.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 51.3 +++ b/rtl/lm32_icache.v Tue Mar 08 09:40:42 2011 +0000 51.4 @@ -0,0 +1,494 @@ 51.5 +// ============================================================================= 51.6 +// COPYRIGHT NOTICE 51.7 +// Copyright 2006 (c) Lattice Semiconductor Corporation 51.8 +// ALL RIGHTS RESERVED 51.9 +// This confidential and proprietary software may be used only as authorised by 51.10 +// a licensing agreement from Lattice Semiconductor Corporation. 51.11 +// The entire notice above must be reproduced on all authorized copies and 51.12 +// copies may only be made to the extent permitted by a licensing agreement from 51.13 +// Lattice Semiconductor Corporation. 51.14 +// 51.15 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 51.16 +// 5555 NE Moore Court 408-826-6000 (other locations) 51.17 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 51.18 +// U.S.A email: techsupport@latticesemi.com 51.19 +// =============================================================================/ 51.20 +// FILE DETAILS 51.21 +// Project : LatticeMico32 51.22 +// File : lm32_icache.v 51.23 +// Title : Instruction cache 51.24 +// Dependencies : lm32_include.v 51.25 +// 51.26 +// Version 3.5 51.27 +// 1. Bug Fix: Instruction cache flushes issued from Instruction Inline Memory 51.28 +// cause segmentation fault due to incorrect fetches. 51.29 +// 51.30 +// Version 3.1 51.31 +// 1. Feature: Support for user-selected resource usage when implementing 51.32 +// cache memory. Additional parameters must be defined when invoking module 51.33 +// lm32_ram. Instruction cache miss mechanism is dependent on branch 51.34 +// prediction being performed in D stage of pipeline. 51.35 +// 51.36 +// Version 7.0SP2, 3.0 51.37 +// No change 51.38 +// ============================================================================= 51.39 + 51.40 +`include "lm32_include.v" 51.41 + 51.42 +`ifdef CFG_ICACHE_ENABLED 51.43 + 51.44 +`define LM32_IC_ADDR_OFFSET_RNG addr_offset_msb:addr_offset_lsb 51.45 +`define LM32_IC_ADDR_SET_RNG addr_set_msb:addr_set_lsb 51.46 +`define LM32_IC_ADDR_TAG_RNG addr_tag_msb:addr_tag_lsb 51.47 +`define LM32_IC_ADDR_IDX_RNG addr_set_msb:addr_offset_lsb 51.48 + 51.49 +`define LM32_IC_TMEM_ADDR_WIDTH addr_set_width 51.50 +`define LM32_IC_TMEM_ADDR_RNG (`LM32_IC_TMEM_ADDR_WIDTH-1):0 51.51 +`define LM32_IC_DMEM_ADDR_WIDTH (addr_offset_width+addr_set_width) 51.52 +`define LM32_IC_DMEM_ADDR_RNG (`LM32_IC_DMEM_ADDR_WIDTH-1):0 51.53 + 51.54 +`define LM32_IC_TAGS_WIDTH (addr_tag_width+1) 51.55 +`define LM32_IC_TAGS_RNG (`LM32_IC_TAGS_WIDTH-1):0 51.56 +`define LM32_IC_TAGS_TAG_RNG (`LM32_IC_TAGS_WIDTH-1):1 51.57 +`define LM32_IC_TAGS_VALID_RNG 0 51.58 + 51.59 +`define LM32_IC_STATE_RNG 3:0 51.60 +`define LM32_IC_STATE_FLUSH_INIT 4'b0001 51.61 +`define LM32_IC_STATE_FLUSH 4'b0010 51.62 +`define LM32_IC_STATE_CHECK 4'b0100 51.63 +`define LM32_IC_STATE_REFILL 4'b1000 51.64 + 51.65 +///////////////////////////////////////////////////// 51.66 +// Module interface 51.67 +///////////////////////////////////////////////////// 51.68 + 51.69 +module lm32_icache ( 51.70 + // ----- Inputs ----- 51.71 + clk_i, 51.72 + rst_i, 51.73 + stall_a, 51.74 + stall_f, 51.75 + address_a, 51.76 + address_f, 51.77 + read_enable_f, 51.78 + refill_ready, 51.79 + refill_data, 51.80 + iflush, 51.81 +`ifdef CFG_IROM_ENABLED 51.82 + select_f, 51.83 +`endif 51.84 + valid_d, 51.85 + branch_predict_taken_d, 51.86 + // ----- Outputs ----- 51.87 + stall_request, 51.88 + restart_request, 51.89 + refill_request, 51.90 + refill_address, 51.91 + refilling, 51.92 + inst 51.93 + ); 51.94 + 51.95 +///////////////////////////////////////////////////// 51.96 +// Parameters 51.97 +///////////////////////////////////////////////////// 51.98 + 51.99 +parameter associativity = 1; // Associativity of the cache (Number of ways) 51.100 +parameter sets = 512; // Number of sets 51.101 +parameter bytes_per_line = 16; // Number of bytes per cache line 51.102 +parameter base_address = 0; // Base address of cachable memory 51.103 +parameter limit = 0; // Limit (highest address) of cachable memory 51.104 + 51.105 +localparam addr_offset_width = clogb2(bytes_per_line)-1-2; 51.106 +localparam addr_set_width = clogb2(sets)-1; 51.107 +localparam addr_offset_lsb = 2; 51.108 +localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1); 51.109 +localparam addr_set_lsb = (addr_offset_msb+1); 51.110 +localparam addr_set_msb = (addr_set_lsb+addr_set_width-1); 51.111 +localparam addr_tag_lsb = (addr_set_msb+1); 51.112 +localparam addr_tag_msb = clogb2(`CFG_ICACHE_LIMIT-`CFG_ICACHE_BASE_ADDRESS)-1; 51.113 +localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1); 51.114 + 51.115 +///////////////////////////////////////////////////// 51.116 +// Inputs 51.117 +///////////////////////////////////////////////////// 51.118 + 51.119 +input clk_i; // Clock 51.120 +input rst_i; // Reset 51.121 + 51.122 +input stall_a; // Stall instruction in A stage 51.123 +input stall_f; // Stall instruction in F stage 51.124 + 51.125 +input valid_d; // Valid instruction in D stage 51.126 +input branch_predict_taken_d; // Instruction in D stage is a branch and is predicted taken 51.127 + 51.128 +input [`LM32_PC_RNG] address_a; // Address of instruction in A stage 51.129 +input [`LM32_PC_RNG] address_f; // Address of instruction in F stage 51.130 +input read_enable_f; // Indicates if cache access is valid 51.131 + 51.132 +input refill_ready; // Next word of refill data is ready 51.133 +input [`LM32_INSTRUCTION_RNG] refill_data; // Data to refill the cache with 51.134 + 51.135 +input iflush; // Flush the cache 51.136 +`ifdef CFG_IROM_ENABLED 51.137 +input select_f; // Instruction in F stage is mapped through instruction cache 51.138 +`endif 51.139 + 51.140 +///////////////////////////////////////////////////// 51.141 +// Outputs 51.142 +///////////////////////////////////////////////////// 51.143 + 51.144 +output stall_request; // Request to stall the pipeline 51.145 +wire stall_request; 51.146 +output restart_request; // Request to restart instruction that caused the cache miss 51.147 +reg restart_request; 51.148 +output refill_request; // Request to refill a cache line 51.149 +wire refill_request; 51.150 +output [`LM32_PC_RNG] refill_address; // Base address of cache refill 51.151 +reg [`LM32_PC_RNG] refill_address; 51.152 +output refilling; // Indicates the instruction cache is currently refilling 51.153 +reg refilling; 51.154 +output [`LM32_INSTRUCTION_RNG] inst; // Instruction read from cache 51.155 +wire [`LM32_INSTRUCTION_RNG] inst; 51.156 + 51.157 +///////////////////////////////////////////////////// 51.158 +// Internal nets and registers 51.159 +///////////////////////////////////////////////////// 51.160 + 51.161 +wire enable; 51.162 +wire [0:associativity-1] way_mem_we; 51.163 +wire [`LM32_INSTRUCTION_RNG] way_data[0:associativity-1]; 51.164 +wire [`LM32_IC_TAGS_TAG_RNG] way_tag[0:associativity-1]; 51.165 +wire [0:associativity-1] way_valid; 51.166 +wire [0:associativity-1] way_match; 51.167 +wire miss; 51.168 + 51.169 +wire [`LM32_IC_TMEM_ADDR_RNG] tmem_read_address; 51.170 +wire [`LM32_IC_TMEM_ADDR_RNG] tmem_write_address; 51.171 +wire [`LM32_IC_DMEM_ADDR_RNG] dmem_read_address; 51.172 +wire [`LM32_IC_DMEM_ADDR_RNG] dmem_write_address; 51.173 +wire [`LM32_IC_TAGS_RNG] tmem_write_data; 51.174 + 51.175 +reg [`LM32_IC_STATE_RNG] state; 51.176 +wire flushing; 51.177 +wire check; 51.178 +wire refill; 51.179 + 51.180 +reg [associativity-1:0] refill_way_select; 51.181 +reg [`LM32_IC_ADDR_OFFSET_RNG] refill_offset; 51.182 +wire last_refill; 51.183 +reg [`LM32_IC_TMEM_ADDR_RNG] flush_set; 51.184 + 51.185 +genvar i; 51.186 + 51.187 +///////////////////////////////////////////////////// 51.188 +// Functions 51.189 +///////////////////////////////////////////////////// 51.190 + 51.191 +`include "lm32_functions.v" 51.192 + 51.193 +///////////////////////////////////////////////////// 51.194 +// Instantiations 51.195 +///////////////////////////////////////////////////// 51.196 + 51.197 + generate 51.198 + for (i = 0; i < associativity; i = i + 1) 51.199 + begin : memories 51.200 + 51.201 + lm32_ram 51.202 + #( 51.203 + // ----- Parameters ------- 51.204 + .data_width (32), 51.205 + .address_width (`LM32_IC_DMEM_ADDR_WIDTH) 51.206 +`ifdef PLATFORM_LATTICE 51.207 + , 51.208 + `ifdef CFG_ICACHE_DAT_USE_DP_TRUE 51.209 + .RAM_IMPLEMENTATION ("EBR"), 51.210 + .RAM_TYPE ("RAM_DP_TRUE") 51.211 + `else 51.212 + `ifdef CFG_ICACHE_DAT_USE_DP 51.213 + .RAM_IMPLEMENTATION ("EBR"), 51.214 + .RAM_TYPE ("RAM_DP") 51.215 + `else 51.216 + `ifdef CFG_ICACHE_DAT_USE_SLICE 51.217 + .RAM_IMPLEMENTATION ("SLICE") 51.218 + `else 51.219 + .RAM_IMPLEMENTATION ("AUTO") 51.220 + `endif 51.221 + `endif 51.222 + `endif 51.223 +`endif 51.224 + ) 51.225 + way_0_data_ram 51.226 + ( 51.227 + // ----- Inputs ------- 51.228 + .read_clk (clk_i), 51.229 + .write_clk (clk_i), 51.230 + .reset (rst_i), 51.231 + .read_address (dmem_read_address), 51.232 + .enable_read (enable), 51.233 + .write_address (dmem_write_address), 51.234 + .enable_write (`TRUE), 51.235 + .write_enable (way_mem_we[i]), 51.236 + .write_data (refill_data), 51.237 + // ----- Outputs ------- 51.238 + .read_data (way_data[i]) 51.239 + ); 51.240 + 51.241 + lm32_ram 51.242 + #( 51.243 + // ----- Parameters ------- 51.244 + .data_width (`LM32_IC_TAGS_WIDTH), 51.245 + .address_width (`LM32_IC_TMEM_ADDR_WIDTH) 51.246 +`ifdef PLATFORM_LATTICE 51.247 + , 51.248 + `ifdef CFG_ICACHE_DAT_USE_DP_TRUE 51.249 + .RAM_IMPLEMENTATION ("EBR"), 51.250 + .RAM_TYPE ("RAM_DP_TRUE") 51.251 + `else 51.252 + `ifdef CFG_ICACHE_DAT_USE_DP 51.253 + .RAM_IMPLEMENTATION ("EBR"), 51.254 + .RAM_TYPE ("RAM_DP") 51.255 + `else 51.256 + `ifdef CFG_ICACHE_DAT_USE_SLICE 51.257 + .RAM_IMPLEMENTATION ("SLICE") 51.258 + `else 51.259 + .RAM_IMPLEMENTATION ("AUTO") 51.260 + `endif 51.261 + `endif 51.262 + `endif 51.263 +`endif 51.264 + ) 51.265 + way_0_tag_ram 51.266 + ( 51.267 + // ----- Inputs ------- 51.268 + .read_clk (clk_i), 51.269 + .write_clk (clk_i), 51.270 + .reset (rst_i), 51.271 + .read_address (tmem_read_address), 51.272 + .enable_read (enable), 51.273 + .write_address (tmem_write_address), 51.274 + .enable_write (`TRUE), 51.275 + .write_enable (way_mem_we[i] | flushing), 51.276 + .write_data (tmem_write_data), 51.277 + // ----- Outputs ------- 51.278 + .read_data ({way_tag[i], way_valid[i]}) 51.279 + ); 51.280 + 51.281 + end 51.282 +endgenerate 51.283 + 51.284 +///////////////////////////////////////////////////// 51.285 +// Combinational logic 51.286 +///////////////////////////////////////////////////// 51.287 + 51.288 +// Compute which ways in the cache match the address address being read 51.289 +generate 51.290 + for (i = 0; i < associativity; i = i + 1) 51.291 + begin : match 51.292 +assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_f[`LM32_IC_ADDR_TAG_RNG], `TRUE}); 51.293 + end 51.294 +endgenerate 51.295 + 51.296 +// Select data from way that matched the address being read 51.297 +generate 51.298 + if (associativity == 1) 51.299 + begin : inst_1 51.300 +assign inst = way_match[0] ? way_data[0] : 32'b0; 51.301 + end 51.302 + else if (associativity == 2) 51.303 + begin : inst_2 51.304 +assign inst = way_match[0] ? way_data[0] : (way_match[1] ? way_data[1] : 32'b0); 51.305 + end 51.306 +endgenerate 51.307 + 51.308 +// Compute address to use to index into the data memories 51.309 +generate 51.310 + if (bytes_per_line > 4) 51.311 +assign dmem_write_address = {refill_address[`LM32_IC_ADDR_SET_RNG], refill_offset}; 51.312 + else 51.313 +assign dmem_write_address = refill_address[`LM32_IC_ADDR_SET_RNG]; 51.314 +endgenerate 51.315 + 51.316 +assign dmem_read_address = address_a[`LM32_IC_ADDR_IDX_RNG]; 51.317 + 51.318 +// Compute address to use to index into the tag memories 51.319 +assign tmem_read_address = address_a[`LM32_IC_ADDR_SET_RNG]; 51.320 +assign tmem_write_address = flushing 51.321 + ? flush_set 51.322 + : refill_address[`LM32_IC_ADDR_SET_RNG]; 51.323 + 51.324 +// Compute signal to indicate when we are on the last refill accesses 51.325 +generate 51.326 + if (bytes_per_line > 4) 51.327 +assign last_refill = refill_offset == {addr_offset_width{1'b1}}; 51.328 + else 51.329 +assign last_refill = `TRUE; 51.330 +endgenerate 51.331 + 51.332 +// Compute data and tag memory access enable 51.333 +assign enable = (stall_a == `FALSE); 51.334 + 51.335 +// Compute data and tag memory write enables 51.336 +generate 51.337 + if (associativity == 1) 51.338 + begin : we_1 51.339 +assign way_mem_we[0] = (refill_ready == `TRUE); 51.340 + end 51.341 + else 51.342 + begin : we_2 51.343 +assign way_mem_we[0] = (refill_ready == `TRUE) && (refill_way_select[0] == `TRUE); 51.344 +assign way_mem_we[1] = (refill_ready == `TRUE) && (refill_way_select[1] == `TRUE); 51.345 + end 51.346 +endgenerate 51.347 + 51.348 +// On the last refill cycle set the valid bit, for all other writes it should be cleared 51.349 +assign tmem_write_data[`LM32_IC_TAGS_VALID_RNG] = last_refill & !flushing; 51.350 +assign tmem_write_data[`LM32_IC_TAGS_TAG_RNG] = refill_address[`LM32_IC_ADDR_TAG_RNG]; 51.351 + 51.352 +// Signals that indicate which state we are in 51.353 +assign flushing = |state[1:0]; 51.354 +assign check = state[2]; 51.355 +assign refill = state[3]; 51.356 + 51.357 +assign miss = (~(|way_match)) && (read_enable_f == `TRUE) && (stall_f == `FALSE) && !(valid_d && branch_predict_taken_d); 51.358 +assign stall_request = (check == `FALSE); 51.359 +assign refill_request = (refill == `TRUE); 51.360 + 51.361 +///////////////////////////////////////////////////// 51.362 +// Sequential logic 51.363 +///////////////////////////////////////////////////// 51.364 + 51.365 +// Record way selected for replacement on a cache miss 51.366 +generate 51.367 + if (associativity >= 2) 51.368 + begin : way_select 51.369 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 51.370 +begin 51.371 + if (rst_i == `TRUE) 51.372 + refill_way_select <= {{associativity-1{1'b0}}, 1'b1}; 51.373 + else 51.374 + begin 51.375 + if (miss == `TRUE) 51.376 + refill_way_select <= {refill_way_select[0], refill_way_select[1]}; 51.377 + end 51.378 +end 51.379 + end 51.380 +endgenerate 51.381 + 51.382 +// Record whether we are refilling 51.383 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 51.384 +begin 51.385 + if (rst_i == `TRUE) 51.386 + refilling <= `FALSE; 51.387 + else 51.388 + refilling <= refill; 51.389 +end 51.390 + 51.391 +// Instruction cache control FSM 51.392 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 51.393 +begin 51.394 + if (rst_i == `TRUE) 51.395 + begin 51.396 + state <= `LM32_IC_STATE_FLUSH_INIT; 51.397 + flush_set <= {`LM32_IC_TMEM_ADDR_WIDTH{1'b1}}; 51.398 + refill_address <= {`LM32_PC_WIDTH{1'bx}}; 51.399 + restart_request <= `FALSE; 51.400 + end 51.401 + else 51.402 + begin 51.403 + case (state) 51.404 + 51.405 + // Flush the cache for the first time after reset 51.406 + `LM32_IC_STATE_FLUSH_INIT: 51.407 + begin 51.408 + if (flush_set == {`LM32_IC_TMEM_ADDR_WIDTH{1'b0}}) 51.409 + state <= `LM32_IC_STATE_CHECK; 51.410 + flush_set <= flush_set - 1'b1; 51.411 + end 51.412 + 51.413 + // Flush the cache in response to an write to the ICC CSR 51.414 + `LM32_IC_STATE_FLUSH: 51.415 + begin 51.416 + if (flush_set == {`LM32_IC_TMEM_ADDR_WIDTH{1'b0}}) 51.417 +`ifdef CFG_IROM_ENABLED 51.418 + if (select_f) 51.419 + state <= `LM32_IC_STATE_REFILL; 51.420 + else 51.421 +`endif 51.422 + state <= `LM32_IC_STATE_CHECK; 51.423 + 51.424 + flush_set <= flush_set - 1'b1; 51.425 + end 51.426 + 51.427 + // Check for cache misses 51.428 + `LM32_IC_STATE_CHECK: 51.429 + begin 51.430 + if (stall_a == `FALSE) 51.431 + restart_request <= `FALSE; 51.432 + if (iflush == `TRUE) 51.433 + begin 51.434 + refill_address <= address_f; 51.435 + state <= `LM32_IC_STATE_FLUSH; 51.436 + end 51.437 + else if (miss == `TRUE) 51.438 + begin 51.439 + refill_address <= address_f; 51.440 + state <= `LM32_IC_STATE_REFILL; 51.441 + end 51.442 + end 51.443 + 51.444 + // Refill a cache line 51.445 + `LM32_IC_STATE_REFILL: 51.446 + begin 51.447 + if (refill_ready == `TRUE) 51.448 + begin 51.449 + if (last_refill == `TRUE) 51.450 + begin 51.451 + restart_request <= `TRUE; 51.452 + state <= `LM32_IC_STATE_CHECK; 51.453 + end 51.454 + end 51.455 + end 51.456 + 51.457 + endcase 51.458 + end 51.459 +end 51.460 + 51.461 +generate 51.462 + if (bytes_per_line > 4) 51.463 + begin 51.464 +// Refill offset 51.465 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 51.466 +begin 51.467 + if (rst_i == `TRUE) 51.468 + refill_offset <= {addr_offset_width{1'b0}}; 51.469 + else 51.470 + begin 51.471 + case (state) 51.472 + 51.473 + // Check for cache misses 51.474 + `LM32_IC_STATE_CHECK: 51.475 + begin 51.476 + if (iflush == `TRUE) 51.477 + refill_offset <= {addr_offset_width{1'b0}}; 51.478 + else if (miss == `TRUE) 51.479 + refill_offset <= {addr_offset_width{1'b0}}; 51.480 + end 51.481 + 51.482 + // Refill a cache line 51.483 + `LM32_IC_STATE_REFILL: 51.484 + begin 51.485 + if (refill_ready == `TRUE) 51.486 + refill_offset <= refill_offset + 1'b1; 51.487 + end 51.488 + 51.489 + endcase 51.490 + end 51.491 +end 51.492 + end 51.493 +endgenerate 51.494 + 51.495 +endmodule 51.496 + 51.497 +`endif 51.498 +
52.1 diff -r 252df75c8f67 -r c336e674a37e rtl/lm32_include.v 52.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 52.3 +++ b/rtl/lm32_include.v Tue Mar 08 09:40:42 2011 +0000 52.4 @@ -0,0 +1,368 @@ 52.5 +// ============================================================================= 52.6 +// COPYRIGHT NOTICE 52.7 +// Copyright 2006 (c) Lattice Semiconductor Corporation 52.8 +// ALL RIGHTS RESERVED 52.9 +// This confidential and proprietary software may be used only as authorised by 52.10 +// a licensing agreement from Lattice Semiconductor Corporation. 52.11 +// The entire notice above must be reproduced on all authorized copies and 52.12 +// copies may only be made to the extent permitted by a licensing agreement from 52.13 +// Lattice Semiconductor Corporation. 52.14 +// 52.15 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 52.16 +// 5555 NE Moore Court 408-826-6000 (other locations) 52.17 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 52.18 +// U.S.A email: techsupport@latticesemi.com 52.19 +// =============================================================================/ 52.20 +// FILE DETAILS 52.21 +// Project : LatticeMico32 52.22 +// File : lm32_include.v 52.23 +// Title : CPU global macros 52.24 +// Version : 6.1.17 52.25 +// : Initial Release 52.26 +// Version : 7.0SP2, 3.0 52.27 +// : No Change 52.28 +// Version : 3.1 52.29 +// : No Change 52.30 +// Version : 3.2 52.31 +// : No Change 52.32 +// Version : 3.3 52.33 +// : Support for extended configuration register 52.34 +// ============================================================================= 52.35 + 52.36 +`ifdef LM32_INCLUDE_V 52.37 +`else 52.38 +`define LM32_INCLUDE_V 52.39 + 52.40 +// 52.41 +// Common configuration options 52.42 +// 52.43 + 52.44 +`define CFG_EBA_RESET 32'h00000000 52.45 +`define CFG_DEBA_RESET 32'h10000000 52.46 + 52.47 +`define CFG_PL_MULTIPLY_ENABLED 52.48 +`define CFG_PL_BARREL_SHIFT_ENABLED 52.49 +`define CFG_SIGN_EXTEND_ENABLED 52.50 +`define CFG_MC_DIVIDE_ENABLED 52.51 +`define CFG_EBR_POSEDGE_REGISTER_FILE 52.52 + 52.53 +// [found by Milkymist dev'rs] 52.54 +// Bug in Xst: 52.55 +// CFG_ICACHE_ASSOCIATIVITY=2 => works in most cases (random crash on complex software) 52.56 +// CFG_ICACHE_ASSOCIATIVITY=1 => disaster, CPU will not work at all 52.57 +// Works 100% OK with expensive synthesizers. 52.58 +`define CFG_ICACHE_ENABLED 52.59 +`define CFG_ICACHE_ASSOCIATIVITY 1 52.60 +`define CFG_ICACHE_SETS 256 52.61 +`define CFG_ICACHE_BYTES_PER_LINE 16 52.62 +`define CFG_ICACHE_BASE_ADDRESS 32'h0 52.63 +`define CFG_ICACHE_LIMIT 32'h7FFF_FFFF 52.64 + 52.65 +`define CFG_DCACHE_ENABLED 52.66 +`define CFG_DCACHE_ASSOCIATIVITY 1 52.67 +`define CFG_DCACHE_SETS 256 52.68 +`define CFG_DCACHE_BYTES_PER_LINE 16 52.69 +`define CFG_DCACHE_BASE_ADDRESS 32'h0 52.70 +`define CFG_DCACHE_LIMIT 32'h0FFF_FFFF 52.71 + 52.72 +// Enable Debugging 52.73 +//`define CFG_JTAG_ENABLED 52.74 +//`define CFG_JTAG_UART_ENABLED 52.75 +//`define CFG_DEBUG_ENABLED 52.76 +//`define CFG_HW_DEBUG_ENABLED 52.77 +//`define CFG_ROM_DEBUG_ENABLED 52.78 +//`define CFG_BREAKPOINTS 32'h0 52.79 +//`define CFG_WATCHPOINTS 32'h0 52.80 + 52.81 +// 52.82 +// End of common configuration options 52.83 +// 52.84 + 52.85 +`ifdef TRUE 52.86 +`else 52.87 +`define TRUE 1'b1 52.88 +`define FALSE 1'b0 52.89 +`define TRUE_N 1'b0 52.90 +`define FALSE_N 1'b1 52.91 +`endif 52.92 + 52.93 +// Wishbone configuration 52.94 +`define CFG_IWB_ENABLED 52.95 +`define CFG_DWB_ENABLED 52.96 + 52.97 +// Data-path width 52.98 +`define LM32_WORD_WIDTH 32 52.99 +`define LM32_WORD_RNG (`LM32_WORD_WIDTH-1):0 52.100 +`define LM32_SHIFT_WIDTH 5 52.101 +`define LM32_SHIFT_RNG (`LM32_SHIFT_WIDTH-1):0 52.102 +`define LM32_BYTE_SELECT_WIDTH 4 52.103 +`define LM32_BYTE_SELECT_RNG (`LM32_BYTE_SELECT_WIDTH-1):0 52.104 + 52.105 +// Register file size 52.106 +`define LM32_REGISTERS 32 52.107 +`define LM32_REG_IDX_WIDTH 5 52.108 +`define LM32_REG_IDX_RNG (`LM32_REG_IDX_WIDTH-1):0 52.109 + 52.110 +// Standard register numbers 52.111 +`define LM32_RA_REG `LM32_REG_IDX_WIDTH'd29 52.112 +`define LM32_EA_REG `LM32_REG_IDX_WIDTH'd30 52.113 +`define LM32_BA_REG `LM32_REG_IDX_WIDTH'd31 52.114 + 52.115 +// Range of Program Counter. Two LSBs are always 0. 52.116 +// `ifdef CFG_ICACHE_ENABLED 52.117 +// `define LM32_PC_WIDTH (clogb2(`CFG_ICACHE_LIMIT-`CFG_ICACHE_BASE_ADDRESS)-2) 52.118 +// `else 52.119 +// `ifdef CFG_IWB_ENABLED 52.120 +`define LM32_PC_WIDTH (`LM32_WORD_WIDTH-2) 52.121 +// `else 52.122 +// `define LM32_PC_WIDTH `LM32_IROM_ADDRESS_WIDTH 52.123 +// `endif 52.124 +// `endif 52.125 +`define LM32_PC_RNG (`LM32_PC_WIDTH+2-1):2 52.126 + 52.127 +// Range of an instruction 52.128 +`define LM32_INSTRUCTION_WIDTH 32 52.129 +`define LM32_INSTRUCTION_RNG (`LM32_INSTRUCTION_WIDTH-1):0 52.130 + 52.131 +// Adder operation 52.132 +`define LM32_ADDER_OP_ADD 1'b0 52.133 +`define LM32_ADDER_OP_SUBTRACT 1'b1 52.134 + 52.135 +// Shift direction 52.136 +`define LM32_SHIFT_OP_RIGHT 1'b0 52.137 +`define LM32_SHIFT_OP_LEFT 1'b1 52.138 + 52.139 +// Bus errors 52.140 +//`define CFG_BUS_ERRORS_ENABLED 52.141 + 52.142 +// Derive macro that indicates whether we have single-stepping or not 52.143 +`ifdef CFG_ROM_DEBUG_ENABLED 52.144 +`define LM32_SINGLE_STEP_ENABLED 52.145 +`else 52.146 +`ifdef CFG_HW_DEBUG_ENABLED 52.147 +`define LM32_SINGLE_STEP_ENABLED 52.148 +`endif 52.149 +`endif 52.150 + 52.151 +// Derive macro that indicates whether JTAG interface is required 52.152 +`ifdef CFG_JTAG_UART_ENABLED 52.153 +`define LM32_JTAG_ENABLED 52.154 +`else 52.155 +`ifdef CFG_DEBUG_ENABLED 52.156 +`define LM32_JTAG_ENABLED 52.157 +`else 52.158 +`endif 52.159 +`endif 52.160 + 52.161 +// Derive macro that indicates whether we have a barrel-shifter or not 52.162 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 52.163 +`define LM32_BARREL_SHIFT_ENABLED 52.164 +`else // CFG_PL_BARREL_SHIFT_ENABLED 52.165 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED 52.166 +`define LM32_BARREL_SHIFT_ENABLED 52.167 +`else 52.168 +`define LM32_NO_BARREL_SHIFT 52.169 +`endif 52.170 +`endif // CFG_PL_BARREL_SHIFT_ENABLED 52.171 + 52.172 +// Derive macro that indicates whether we have a multiplier or not 52.173 +`ifdef CFG_PL_MULTIPLY_ENABLED 52.174 +`define LM32_MULTIPLY_ENABLED 52.175 +`else 52.176 +`ifdef CFG_MC_MULTIPLY_ENABLED 52.177 +`define LM32_MULTIPLY_ENABLED 52.178 +`endif 52.179 +`endif 52.180 + 52.181 +// Derive a macro that indicates whether or not the multi-cycle arithmetic unit is required 52.182 +`ifdef CFG_MC_DIVIDE_ENABLED 52.183 +`define LM32_MC_ARITHMETIC_ENABLED 52.184 +`endif 52.185 +`ifdef CFG_MC_MULTIPLY_ENABLED 52.186 +`define LM32_MC_ARITHMETIC_ENABLED 52.187 +`endif 52.188 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED 52.189 +`define LM32_MC_ARITHMETIC_ENABLED 52.190 +`endif 52.191 + 52.192 +// Derive macro that indicates if we are using an EBR register file 52.193 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE 52.194 +`define LM32_EBR_REGISTER_FILE 52.195 +`endif 52.196 +`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE 52.197 +`define LM32_EBR_REGISTER_FILE 52.198 +`endif 52.199 + 52.200 +// Revision number 52.201 +`define LM32_REVISION 6'h02 52.202 + 52.203 +// Logical operations - Function encoded directly in instruction 52.204 +`define LM32_LOGIC_OP_RNG 3:0 52.205 + 52.206 +// Conditions for conditional branches 52.207 +`define LM32_CONDITION_WIDTH 3 52.208 +`define LM32_CONDITION_RNG (`LM32_CONDITION_WIDTH-1):0 52.209 +`define LM32_CONDITION_E 3'b001 52.210 +`define LM32_CONDITION_G 3'b010 52.211 +`define LM32_CONDITION_GE 3'b011 52.212 +`define LM32_CONDITION_GEU 3'b100 52.213 +`define LM32_CONDITION_GU 3'b101 52.214 +`define LM32_CONDITION_NE 3'b111 52.215 +`define LM32_CONDITION_U1 3'b000 52.216 +`define LM32_CONDITION_U2 3'b110 52.217 + 52.218 +// Size of load or store instruction - Encoding corresponds to opcode 52.219 +`define LM32_SIZE_WIDTH 2 52.220 +`define LM32_SIZE_RNG 1:0 52.221 +`define LM32_SIZE_BYTE 2'b00 52.222 +`define LM32_SIZE_HWORD 2'b11 52.223 +`define LM32_SIZE_WORD 2'b10 52.224 +`define LM32_ADDRESS_LSBS_WIDTH 2 52.225 + 52.226 +// Width and range of a CSR index 52.227 +`ifdef CFG_DEBUG_ENABLED 52.228 +`define LM32_CSR_WIDTH 5 52.229 +`define LM32_CSR_RNG (`LM32_CSR_WIDTH-1):0 52.230 +`else 52.231 +`ifdef CFG_JTAG_ENABLED 52.232 +`define LM32_CSR_WIDTH 4 52.233 +`define LM32_CSR_RNG (`LM32_CSR_WIDTH-1):0 52.234 +`else 52.235 +`define LM32_CSR_WIDTH 3 52.236 +`define LM32_CSR_RNG (`LM32_CSR_WIDTH-1):0 52.237 +`endif 52.238 +`endif 52.239 + 52.240 +// CSR indices 52.241 +`define LM32_CSR_IE `LM32_CSR_WIDTH'h0 52.242 +`define LM32_CSR_IM `LM32_CSR_WIDTH'h1 52.243 +`define LM32_CSR_IP `LM32_CSR_WIDTH'h2 52.244 +`define LM32_CSR_ICC `LM32_CSR_WIDTH'h3 52.245 +`define LM32_CSR_DCC `LM32_CSR_WIDTH'h4 52.246 +`define LM32_CSR_CC `LM32_CSR_WIDTH'h5 52.247 +`define LM32_CSR_CFG `LM32_CSR_WIDTH'h6 52.248 +`define LM32_CSR_EBA `LM32_CSR_WIDTH'h7 52.249 +`ifdef CFG_DEBUG_ENABLED 52.250 +`define LM32_CSR_DC `LM32_CSR_WIDTH'h8 52.251 +`define LM32_CSR_DEBA `LM32_CSR_WIDTH'h9 52.252 +`endif 52.253 +`define LM32_CSR_CFG2 `LM32_CSR_WIDTH'ha 52.254 +`ifdef CFG_JTAG_ENABLED 52.255 +`define LM32_CSR_JTX `LM32_CSR_WIDTH'he 52.256 +`define LM32_CSR_JRX `LM32_CSR_WIDTH'hf 52.257 +`endif 52.258 +`ifdef CFG_DEBUG_ENABLED 52.259 +`define LM32_CSR_BP0 `LM32_CSR_WIDTH'h10 52.260 +`define LM32_CSR_BP1 `LM32_CSR_WIDTH'h11 52.261 +`define LM32_CSR_BP2 `LM32_CSR_WIDTH'h12 52.262 +`define LM32_CSR_BP3 `LM32_CSR_WIDTH'h13 52.263 +`define LM32_CSR_WP0 `LM32_CSR_WIDTH'h18 52.264 +`define LM32_CSR_WP1 `LM32_CSR_WIDTH'h19 52.265 +`define LM32_CSR_WP2 `LM32_CSR_WIDTH'h1a 52.266 +`define LM32_CSR_WP3 `LM32_CSR_WIDTH'h1b 52.267 +`endif 52.268 + 52.269 +// Values for WPC CSR 52.270 +`define LM32_WPC_C_RNG 1:0 52.271 +`define LM32_WPC_C_DISABLED 2'b00 52.272 +`define LM32_WPC_C_READ 2'b01 52.273 +`define LM32_WPC_C_WRITE 2'b10 52.274 +`define LM32_WPC_C_READ_WRITE 2'b11 52.275 + 52.276 +// Exception IDs 52.277 +`define LM32_EID_WIDTH 3 52.278 +`define LM32_EID_RNG (`LM32_EID_WIDTH-1):0 52.279 +`define LM32_EID_RESET 3'h0 52.280 +`define LM32_EID_BREAKPOINT 3'd1 52.281 +`define LM32_EID_INST_BUS_ERROR 3'h2 52.282 +`define LM32_EID_WATCHPOINT 3'd3 52.283 +`define LM32_EID_DATA_BUS_ERROR 3'h4 52.284 +`define LM32_EID_DIVIDE_BY_ZERO 3'h5 52.285 +`define LM32_EID_INTERRUPT 3'h6 52.286 +`define LM32_EID_SCALL 3'h7 52.287 + 52.288 +// Pipeline result selection mux controls 52.289 + 52.290 +`define LM32_D_RESULT_SEL_0_RNG 0:0 52.291 +`define LM32_D_RESULT_SEL_0_REG_0 1'b0 52.292 +`define LM32_D_RESULT_SEL_0_NEXT_PC 1'b1 52.293 + 52.294 +`define LM32_D_RESULT_SEL_1_RNG 1:0 52.295 +`define LM32_D_RESULT_SEL_1_ZERO 2'b00 52.296 +`define LM32_D_RESULT_SEL_1_REG_1 2'b01 52.297 +`define LM32_D_RESULT_SEL_1_IMMEDIATE 2'b10 52.298 + 52.299 +`define LM32_USER_OPCODE_WIDTH 11 52.300 +`define LM32_USER_OPCODE_RNG (`LM32_USER_OPCODE_WIDTH-1):0 52.301 + 52.302 +// Derive a macro to indicate if either of the caches are implemented 52.303 +`ifdef CFG_ICACHE_ENABLED 52.304 +`define LM32_CACHE_ENABLED 52.305 +`else 52.306 +`ifdef CFG_DCACHE_ENABLED 52.307 +`define LM32_CACHE_ENABLED 52.308 +`endif 52.309 +`endif 52.310 + 52.311 +///////////////////////////////////////////////////// 52.312 +// Interrupts 52.313 +///////////////////////////////////////////////////// 52.314 + 52.315 +// Always enable interrupts 52.316 +`define CFG_INTERRUPTS_ENABLED 52.317 + 52.318 +// Currently this is fixed to 32 and should not be changed 52.319 +`define CFG_INTERRUPTS 32 52.320 +`define LM32_INTERRUPT_WIDTH `CFG_INTERRUPTS 52.321 +`define LM32_INTERRUPT_RNG (`LM32_INTERRUPT_WIDTH-1):0 52.322 + 52.323 +///////////////////////////////////////////////////// 52.324 +// General 52.325 +///////////////////////////////////////////////////// 52.326 + 52.327 +// Sub-word range types 52.328 +`define LM32_BYTE_WIDTH 8 52.329 +`define LM32_BYTE_RNG 7:0 52.330 +`define LM32_HWORD_WIDTH 16 52.331 +`define LM32_HWORD_RNG 15:0 52.332 + 52.333 +// Word sub-byte indicies 52.334 +`define LM32_BYTE_0_RNG 7:0 52.335 +`define LM32_BYTE_1_RNG 15:8 52.336 +`define LM32_BYTE_2_RNG 23:16 52.337 +`define LM32_BYTE_3_RNG 31:24 52.338 + 52.339 +// Word sub-halfword indices 52.340 +`define LM32_HWORD_0_RNG 15:0 52.341 +`define LM32_HWORD_1_RNG 31:16 52.342 + 52.343 +// Use an asynchronous reset 52.344 +// To use a synchronous reset, define this macro as nothing 52.345 +//`define CFG_RESET_SENSITIVITY or posedge rst_i 52.346 +`define CFG_RESET_SENSITIVITY 52.347 + 52.348 +// Whether to include context registers for debug exceptions 52.349 +// in addition to standard exception handling registers 52.350 +`define CFG_DEBUG_EXCEPTIONS_ENABLED 52.351 + 52.352 +// Wishbone defines 52.353 +// Refer to Wishbone System-on-Chip Interconnection Architecture 52.354 +// These should probably be moved to a Wishbone common file 52.355 + 52.356 +// Wishbone cycle types 52.357 +`define LM32_CTYPE_WIDTH 3 52.358 +`define LM32_CTYPE_RNG (`LM32_CTYPE_WIDTH-1):0 52.359 +`define LM32_CTYPE_CLASSIC 3'b000 52.360 +`define LM32_CTYPE_CONSTANT 3'b001 52.361 +`define LM32_CTYPE_INCREMENTING 3'b010 52.362 +`define LM32_CTYPE_END 3'b111 52.363 + 52.364 +// Wishbone burst types 52.365 +`define LM32_BTYPE_WIDTH 2 52.366 +`define LM32_BTYPE_RNG (`LM32_BTYPE_WIDTH-1):0 52.367 +`define LM32_BTYPE_LINEAR 2'b00 52.368 +`define LM32_BTYPE_4_BEAT 2'b01 52.369 +`define LM32_BTYPE_8_BEAT 2'b10 52.370 +`define LM32_BTYPE_16_BEAT 2'b11 52.371 + 52.372 +`endif
53.1 diff -r 252df75c8f67 -r c336e674a37e rtl/lm32_instruction_unit.v 53.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 53.3 +++ b/rtl/lm32_instruction_unit.v Tue Mar 08 09:40:42 2011 +0000 53.4 @@ -0,0 +1,839 @@ 53.5 +// ============================================================================= 53.6 +// COPYRIGHT NOTICE 53.7 +// Copyright 2006 (c) Lattice Semiconductor Corporation 53.8 +// ALL RIGHTS RESERVED 53.9 +// This confidential and proprietary software may be used only as authorised by 53.10 +// a licensing agreement from Lattice Semiconductor Corporation. 53.11 +// The entire notice above must be reproduced on all authorized copies and 53.12 +// copies may only be made to the extent permitted by a licensing agreement from 53.13 +// Lattice Semiconductor Corporation. 53.14 +// 53.15 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 53.16 +// 5555 NE Moore Court 408-826-6000 (other locations) 53.17 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 53.18 +// U.S.A email: techsupport@latticesemi.com 53.19 +// =============================================================================/ 53.20 +// FILE DETAILS 53.21 +// Project : LatticeMico32 53.22 +// File : lm32_instruction_unit.v 53.23 +// Title : Instruction unit 53.24 +// Dependencies : lm32_include.v 53.25 +// Version : 6.1.17 53.26 +// : Initial Release 53.27 +// Version : 7.0SP2, 3.0 53.28 +// : No Change 53.29 +// Version : 3.1 53.30 +// : Support for static branch prediction is added. Fetching of 53.31 +// : instructions can also be altered by branches predicted in D 53.32 +// : stage of pipeline, and mispredicted branches in the X and M 53.33 +// : stages of the pipeline. 53.34 +// Version : 3.2 53.35 +// : EBRs use SYNC resets instead of ASYNC resets. 53.36 +// Version : 3.3 53.37 +// : Support for a non-cacheable Instruction Memory that has a 53.38 +// : single-cycle access latency. This memory can be accessed by 53.39 +// : data port of LM32 (so that debugger has access to it). 53.40 +// Version : 3.4 53.41 +// : No change 53.42 +// Version : 3.5 53.43 +// : Bug fix: Inline memory is correctly generated if it is not a 53.44 +// : power-of-two. 53.45 +// : Bug fix: Fixed a bug that caused LM32 (configured without 53.46 +// : instruction cache) to lock up in to an infinite loop due to a 53.47 +// : instruction bus error when EBA was set to instruction inline 53.48 +// : memory. 53.49 +// ============================================================================= 53.50 + 53.51 +`include "lm32_include.v" 53.52 + 53.53 +///////////////////////////////////////////////////// 53.54 +// Module interface 53.55 +///////////////////////////////////////////////////// 53.56 + 53.57 +module lm32_instruction_unit ( 53.58 + // ----- Inputs ------- 53.59 + clk_i, 53.60 + rst_i, 53.61 + // From pipeline 53.62 + stall_a, 53.63 + stall_f, 53.64 + stall_d, 53.65 + stall_x, 53.66 + stall_m, 53.67 + valid_f, 53.68 + valid_d, 53.69 + kill_f, 53.70 + branch_predict_taken_d, 53.71 + branch_predict_address_d, 53.72 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH 53.73 + branch_taken_x, 53.74 + branch_target_x, 53.75 +`endif 53.76 + exception_m, 53.77 + branch_taken_m, 53.78 + branch_mispredict_taken_m, 53.79 + branch_target_m, 53.80 +`ifdef CFG_ICACHE_ENABLED 53.81 + iflush, 53.82 +`endif 53.83 +`ifdef CFG_DCACHE_ENABLED 53.84 + dcache_restart_request, 53.85 + dcache_refill_request, 53.86 + dcache_refilling, 53.87 +`endif 53.88 +`ifdef CFG_IROM_ENABLED 53.89 + irom_store_data_m, 53.90 + irom_address_xm, 53.91 + irom_we_xm, 53.92 +`endif 53.93 +`ifdef CFG_IWB_ENABLED 53.94 + // From Wishbone 53.95 + i_dat_i, 53.96 + i_ack_i, 53.97 + i_err_i, 53.98 +`endif 53.99 +`ifdef CFG_HW_DEBUG_ENABLED 53.100 + jtag_read_enable, 53.101 + jtag_write_enable, 53.102 + jtag_write_data, 53.103 + jtag_address, 53.104 +`endif 53.105 + // ----- Outputs ------- 53.106 + // To pipeline 53.107 + pc_f, 53.108 + pc_d, 53.109 + pc_x, 53.110 + pc_m, 53.111 + pc_w, 53.112 +`ifdef CFG_ICACHE_ENABLED 53.113 + icache_stall_request, 53.114 + icache_restart_request, 53.115 + icache_refill_request, 53.116 + icache_refilling, 53.117 +`endif 53.118 +`ifdef CFG_IROM_ENABLED 53.119 + irom_data_m, 53.120 +`endif 53.121 +`ifdef CFG_IWB_ENABLED 53.122 + // To Wishbone 53.123 + i_dat_o, 53.124 + i_adr_o, 53.125 + i_cyc_o, 53.126 + i_sel_o, 53.127 + i_stb_o, 53.128 + i_we_o, 53.129 + i_cti_o, 53.130 + i_lock_o, 53.131 + i_bte_o, 53.132 +`endif 53.133 +`ifdef CFG_HW_DEBUG_ENABLED 53.134 + jtag_read_data, 53.135 + jtag_access_complete, 53.136 +`endif 53.137 +`ifdef CFG_BUS_ERRORS_ENABLED 53.138 + bus_error_d, 53.139 +`endif 53.140 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE 53.141 + instruction_f, 53.142 +`endif 53.143 + instruction_d 53.144 + ); 53.145 + 53.146 +///////////////////////////////////////////////////// 53.147 +// Parameters 53.148 +///////////////////////////////////////////////////// 53.149 + 53.150 +parameter associativity = 1; // Associativity of the cache (Number of ways) 53.151 +parameter sets = 512; // Number of sets 53.152 +parameter bytes_per_line = 16; // Number of bytes per cache line 53.153 +parameter base_address = 0; // Base address of cachable memory 53.154 +parameter limit = 0; // Limit (highest address) of cachable memory 53.155 + 53.156 +// For bytes_per_line == 4, we set 1 so part-select range isn't reversed, even though not really used 53.157 +localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2; 53.158 +localparam addr_offset_lsb = 2; 53.159 +localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1); 53.160 + 53.161 +///////////////////////////////////////////////////// 53.162 +// Inputs 53.163 +///////////////////////////////////////////////////// 53.164 + 53.165 +input clk_i; // Clock 53.166 +input rst_i; // Reset 53.167 + 53.168 +input stall_a; // Stall A stage instruction 53.169 +input stall_f; // Stall F stage instruction 53.170 +input stall_d; // Stall D stage instruction 53.171 +input stall_x; // Stall X stage instruction 53.172 +input stall_m; // Stall M stage instruction 53.173 +input valid_f; // Instruction in F stage is valid 53.174 +input valid_d; // Instruction in D stage is valid 53.175 +input kill_f; // Kill instruction in F stage 53.176 + 53.177 +input branch_predict_taken_d; // Branch is predicted taken in D stage 53.178 +input [`LM32_PC_RNG] branch_predict_address_d; // Branch target address 53.179 + 53.180 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH 53.181 +input branch_taken_x; // Branch instruction in X stage is taken 53.182 +input [`LM32_PC_RNG] branch_target_x; // Target PC of X stage branch instruction 53.183 +`endif 53.184 +input exception_m; 53.185 +input branch_taken_m; // Branch instruction in M stage is taken 53.186 +input branch_mispredict_taken_m; // Branch instruction in M stage is mispredicted as taken 53.187 +input [`LM32_PC_RNG] branch_target_m; // Target PC of M stage branch instruction 53.188 + 53.189 +`ifdef CFG_ICACHE_ENABLED 53.190 +input iflush; // Flush instruction cache 53.191 +`endif 53.192 +`ifdef CFG_DCACHE_ENABLED 53.193 +input dcache_restart_request; // Restart instruction that caused a data cache miss 53.194 +input dcache_refill_request; // Request to refill data cache 53.195 +input dcache_refilling; 53.196 +`endif 53.197 + 53.198 +`ifdef CFG_IROM_ENABLED 53.199 +input [`LM32_WORD_RNG] irom_store_data_m; // Data from load-store unit 53.200 +input [`LM32_WORD_RNG] irom_address_xm; // Address from load-store unit 53.201 +input irom_we_xm; // Indicates if memory operation is load or store 53.202 +`endif 53.203 + 53.204 +`ifdef CFG_IWB_ENABLED 53.205 +input [`LM32_WORD_RNG] i_dat_i; // Instruction Wishbone interface read data 53.206 +input i_ack_i; // Instruction Wishbone interface acknowledgement 53.207 +input i_err_i; // Instruction Wishbone interface error 53.208 +`endif 53.209 + 53.210 +`ifdef CFG_HW_DEBUG_ENABLED 53.211 +input jtag_read_enable; // JTAG read memory request 53.212 +input jtag_write_enable; // JTAG write memory request 53.213 +input [`LM32_BYTE_RNG] jtag_write_data; // JTAG wrirte data 53.214 +input [`LM32_WORD_RNG] jtag_address; // JTAG read/write address 53.215 +`endif 53.216 + 53.217 +///////////////////////////////////////////////////// 53.218 +// Outputs 53.219 +///////////////////////////////////////////////////// 53.220 + 53.221 +output [`LM32_PC_RNG] pc_f; // F stage PC 53.222 +reg [`LM32_PC_RNG] pc_f; 53.223 +output [`LM32_PC_RNG] pc_d; // D stage PC 53.224 +reg [`LM32_PC_RNG] pc_d; 53.225 +output [`LM32_PC_RNG] pc_x; // X stage PC 53.226 +reg [`LM32_PC_RNG] pc_x; 53.227 +output [`LM32_PC_RNG] pc_m; // M stage PC 53.228 +reg [`LM32_PC_RNG] pc_m; 53.229 +output [`LM32_PC_RNG] pc_w; // W stage PC 53.230 +reg [`LM32_PC_RNG] pc_w; 53.231 + 53.232 +`ifdef CFG_ICACHE_ENABLED 53.233 +output icache_stall_request; // Instruction cache stall request 53.234 +wire icache_stall_request; 53.235 +output icache_restart_request; // Request to restart instruction that cached instruction cache miss 53.236 +wire icache_restart_request; 53.237 +output icache_refill_request; // Instruction cache refill request 53.238 +wire icache_refill_request; 53.239 +output icache_refilling; // Indicates the icache is refilling 53.240 +wire icache_refilling; 53.241 +`endif 53.242 + 53.243 +`ifdef CFG_IROM_ENABLED 53.244 +output [`LM32_WORD_RNG] irom_data_m; // Data to load-store unit on load 53.245 +wire [`LM32_WORD_RNG] irom_data_m; 53.246 +`endif 53.247 + 53.248 +`ifdef CFG_IWB_ENABLED 53.249 +output [`LM32_WORD_RNG] i_dat_o; // Instruction Wishbone interface write data 53.250 +`ifdef CFG_HW_DEBUG_ENABLED 53.251 +reg [`LM32_WORD_RNG] i_dat_o; 53.252 +`else 53.253 +wire [`LM32_WORD_RNG] i_dat_o; 53.254 +`endif 53.255 +output [`LM32_WORD_RNG] i_adr_o; // Instruction Wishbone interface address 53.256 +reg [`LM32_WORD_RNG] i_adr_o; 53.257 +output i_cyc_o; // Instruction Wishbone interface cycle 53.258 +reg i_cyc_o; 53.259 +output [`LM32_BYTE_SELECT_RNG] i_sel_o; // Instruction Wishbone interface byte select 53.260 +`ifdef CFG_HW_DEBUG_ENABLED 53.261 +reg [`LM32_BYTE_SELECT_RNG] i_sel_o; 53.262 +`else 53.263 +wire [`LM32_BYTE_SELECT_RNG] i_sel_o; 53.264 +`endif 53.265 +output i_stb_o; // Instruction Wishbone interface strobe 53.266 +reg i_stb_o; 53.267 +output i_we_o; // Instruction Wishbone interface write enable 53.268 +`ifdef CFG_HW_DEBUG_ENABLED 53.269 +reg i_we_o; 53.270 +`else 53.271 +wire i_we_o; 53.272 +`endif 53.273 +output [`LM32_CTYPE_RNG] i_cti_o; // Instruction Wishbone interface cycle type 53.274 +reg [`LM32_CTYPE_RNG] i_cti_o; 53.275 +output i_lock_o; // Instruction Wishbone interface lock bus 53.276 +reg i_lock_o; 53.277 +output [`LM32_BTYPE_RNG] i_bte_o; // Instruction Wishbone interface burst type 53.278 +wire [`LM32_BTYPE_RNG] i_bte_o; 53.279 +`endif 53.280 + 53.281 +`ifdef CFG_HW_DEBUG_ENABLED 53.282 +output [`LM32_BYTE_RNG] jtag_read_data; // Data read for JTAG interface 53.283 +reg [`LM32_BYTE_RNG] jtag_read_data; 53.284 +output jtag_access_complete; // Requested memory access by JTAG interface is complete 53.285 +wire jtag_access_complete; 53.286 +`endif 53.287 + 53.288 +`ifdef CFG_BUS_ERRORS_ENABLED 53.289 +output bus_error_d; // Indicates a bus error occured while fetching the instruction 53.290 +reg bus_error_d; 53.291 +`endif 53.292 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE 53.293 +output [`LM32_INSTRUCTION_RNG] instruction_f; // F stage instruction (only to have register indices extracted from) 53.294 +wire [`LM32_INSTRUCTION_RNG] instruction_f; 53.295 +`endif 53.296 +output [`LM32_INSTRUCTION_RNG] instruction_d; // D stage instruction to be decoded 53.297 +reg [`LM32_INSTRUCTION_RNG] instruction_d; 53.298 + 53.299 +///////////////////////////////////////////////////// 53.300 +// Internal nets and registers 53.301 +///////////////////////////////////////////////////// 53.302 + 53.303 +reg [`LM32_PC_RNG] pc_a; // A stage PC 53.304 + 53.305 +`ifdef LM32_CACHE_ENABLED 53.306 +reg [`LM32_PC_RNG] restart_address; // Address to restart from after a cache miss 53.307 +`endif 53.308 + 53.309 +`ifdef CFG_ICACHE_ENABLED 53.310 +wire icache_read_enable_f; // Indicates if instruction cache miss is valid 53.311 +wire [`LM32_PC_RNG] icache_refill_address; // Address that caused cache miss 53.312 +reg icache_refill_ready; // Indicates when next word of refill data is ready to be written to cache 53.313 +reg [`LM32_INSTRUCTION_RNG] icache_refill_data; // Next word of refill data, fetched from Wishbone 53.314 +wire [`LM32_INSTRUCTION_RNG] icache_data_f; // Instruction fetched from instruction cache 53.315 +wire [`LM32_CTYPE_RNG] first_cycle_type; // First Wishbone cycle type 53.316 +wire [`LM32_CTYPE_RNG] next_cycle_type; // Next Wishbone cycle type 53.317 +wire last_word; // Indicates if this is the last word in the cache line 53.318 +wire [`LM32_PC_RNG] first_address; // First cache refill address 53.319 +`else 53.320 +`ifdef CFG_IWB_ENABLED 53.321 +reg [`LM32_INSTRUCTION_RNG] wb_data_f; // Instruction fetched from Wishbone 53.322 +`endif 53.323 +`endif 53.324 +`ifdef CFG_IROM_ENABLED 53.325 +wire irom_select_a; // Indicates if A stage PC maps to a ROM address 53.326 +reg irom_select_f; // Indicates if F stage PC maps to a ROM address 53.327 +wire [`LM32_INSTRUCTION_RNG] irom_data_f; // Instruction fetched from ROM 53.328 +`endif 53.329 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE 53.330 +`else 53.331 +wire [`LM32_INSTRUCTION_RNG] instruction_f; // F stage instruction 53.332 +`endif 53.333 +`ifdef CFG_BUS_ERRORS_ENABLED 53.334 +reg bus_error_f; // Indicates if a bus error occured while fetching the instruction in the F stage 53.335 +`endif 53.336 + 53.337 +`ifdef CFG_HW_DEBUG_ENABLED 53.338 +reg jtag_access; // Indicates if a JTAG WB access is in progress 53.339 +`endif 53.340 + 53.341 +///////////////////////////////////////////////////// 53.342 +// Functions 53.343 +///////////////////////////////////////////////////// 53.344 + 53.345 +`include "lm32_functions.v" 53.346 + 53.347 +///////////////////////////////////////////////////// 53.348 +// Instantiations 53.349 +///////////////////////////////////////////////////// 53.350 + 53.351 +// Instruction ROM 53.352 +`ifdef CFG_IROM_ENABLED 53.353 + pmi_ram_dp_true 53.354 + #( 53.355 + // ----- Parameters ------- 53.356 + .pmi_family (`LATTICE_FAMILY), 53.357 + 53.358 + //.pmi_addr_depth_a (1 << (clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)), 53.359 + //.pmi_addr_width_a ((clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)), 53.360 + //.pmi_data_width_a (`LM32_WORD_WIDTH), 53.361 + //.pmi_addr_depth_b (1 << (clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)), 53.362 + //.pmi_addr_width_b ((clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)), 53.363 + //.pmi_data_width_b (`LM32_WORD_WIDTH), 53.364 + 53.365 + .pmi_addr_depth_a (`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1), 53.366 + .pmi_addr_width_a (clogb2_v1(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)), 53.367 + .pmi_data_width_a (`LM32_WORD_WIDTH), 53.368 + .pmi_addr_depth_b (`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1), 53.369 + .pmi_addr_width_b (clogb2_v1(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)), 53.370 + .pmi_data_width_b (`LM32_WORD_WIDTH), 53.371 + 53.372 + .pmi_regmode_a ("noreg"), 53.373 + .pmi_regmode_b ("noreg"), 53.374 + .pmi_gsr ("enable"), 53.375 + .pmi_resetmode ("sync"), 53.376 + .pmi_init_file (`CFG_IROM_INIT_FILE), 53.377 + .pmi_init_file_format (`CFG_IROM_INIT_FILE_FORMAT), 53.378 + .module_type ("pmi_ram_dp_true") 53.379 + ) 53.380 + ram ( 53.381 + // ----- Inputs ------- 53.382 + .ClockA (clk_i), 53.383 + .ClockB (clk_i), 53.384 + .ResetA (rst_i), 53.385 + .ResetB (rst_i), 53.386 + .DataInA ({32{1'b0}}), 53.387 + .DataInB (irom_store_data_m), 53.388 + .AddressA (pc_a[(clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)+2-1:2]), 53.389 + .AddressB (irom_address_xm[(clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)+2-1:2]), 53.390 + .ClockEnA (!stall_a), 53.391 + .ClockEnB (!stall_x || !stall_m), 53.392 + .WrA (`FALSE), 53.393 + .WrB (irom_we_xm), 53.394 + // ----- Outputs ------- 53.395 + .QA (irom_data_f), 53.396 + .QB (irom_data_m) 53.397 + ); 53.398 +`endif 53.399 + 53.400 +`ifdef CFG_ICACHE_ENABLED 53.401 +// Instruction cache 53.402 +lm32_icache #( 53.403 + .associativity (associativity), 53.404 + .sets (sets), 53.405 + .bytes_per_line (bytes_per_line), 53.406 + .base_address (base_address), 53.407 + .limit (limit) 53.408 + ) icache ( 53.409 + // ----- Inputs ----- 53.410 + .clk_i (clk_i), 53.411 + .rst_i (rst_i), 53.412 + .stall_a (stall_a), 53.413 + .stall_f (stall_f), 53.414 + .branch_predict_taken_d (branch_predict_taken_d), 53.415 + .valid_d (valid_d), 53.416 + .address_a (pc_a), 53.417 + .address_f (pc_f), 53.418 + .read_enable_f (icache_read_enable_f), 53.419 + .refill_ready (icache_refill_ready), 53.420 + .refill_data (icache_refill_data), 53.421 + .iflush (iflush), 53.422 + // ----- Outputs ----- 53.423 + .stall_request (icache_stall_request), 53.424 + .restart_request (icache_restart_request), 53.425 + .refill_request (icache_refill_request), 53.426 + .refill_address (icache_refill_address), 53.427 + .refilling (icache_refilling), 53.428 + .inst (icache_data_f) 53.429 + ); 53.430 +`endif 53.431 + 53.432 +///////////////////////////////////////////////////// 53.433 +// Combinational Logic 53.434 +///////////////////////////////////////////////////// 53.435 + 53.436 +`ifdef CFG_ICACHE_ENABLED 53.437 +// Generate signal that indicates when instruction cache misses are valid 53.438 +assign icache_read_enable_f = (valid_f == `TRUE) 53.439 + && (kill_f == `FALSE) 53.440 +`ifdef CFG_DCACHE_ENABLED 53.441 + && (dcache_restart_request == `FALSE) 53.442 +`endif 53.443 +`ifdef CFG_IROM_ENABLED 53.444 + && (irom_select_f == `FALSE) 53.445 +`endif 53.446 + ; 53.447 +`endif 53.448 + 53.449 +// Compute address of next instruction to fetch 53.450 +always @(*) 53.451 +begin 53.452 + // The request from the latest pipeline stage must take priority 53.453 +`ifdef CFG_DCACHE_ENABLED 53.454 + if (dcache_restart_request == `TRUE) 53.455 + pc_a = restart_address; 53.456 + else 53.457 +`endif 53.458 + if (branch_taken_m == `TRUE) 53.459 + if ((branch_mispredict_taken_m == `TRUE) && (exception_m == `FALSE)) 53.460 + pc_a = pc_x; 53.461 + else 53.462 + pc_a = branch_target_m; 53.463 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH 53.464 + else if (branch_taken_x == `TRUE) 53.465 + pc_a = branch_target_x; 53.466 +`endif 53.467 + else 53.468 + if ( (valid_d == `TRUE) && (branch_predict_taken_d == `TRUE) ) 53.469 + pc_a = branch_predict_address_d; 53.470 + else 53.471 +`ifdef CFG_ICACHE_ENABLED 53.472 + if (icache_restart_request == `TRUE) 53.473 + pc_a = restart_address; 53.474 + else 53.475 +`endif 53.476 + pc_a = pc_f + 1'b1; 53.477 +end 53.478 + 53.479 +// Select where instruction should be fetched from 53.480 +`ifdef CFG_IROM_ENABLED 53.481 +assign irom_select_a = ({pc_a, 2'b00} >= `CFG_IROM_BASE_ADDRESS) && ({pc_a, 2'b00} <= `CFG_IROM_LIMIT); 53.482 +`endif 53.483 + 53.484 +// Select instruction from selected source 53.485 +`ifdef CFG_ICACHE_ENABLED 53.486 +`ifdef CFG_IROM_ENABLED 53.487 +assign instruction_f = irom_select_f == `TRUE ? irom_data_f : icache_data_f; 53.488 +`else 53.489 +assign instruction_f = icache_data_f; 53.490 +`endif 53.491 +`else 53.492 +`ifdef CFG_IROM_ENABLED 53.493 +`ifdef CFG_IWB_ENABLED 53.494 +assign instruction_f = irom_select_f == `TRUE ? irom_data_f : wb_data_f; 53.495 +`else 53.496 +assign instruction_f = irom_data_f; 53.497 +`endif 53.498 +`else 53.499 +assign instruction_f = wb_data_f; 53.500 +`endif 53.501 +`endif 53.502 + 53.503 +// Unused/constant Wishbone signals 53.504 +`ifdef CFG_IWB_ENABLED 53.505 +`ifdef CFG_HW_DEBUG_ENABLED 53.506 +`else 53.507 +assign i_dat_o = 32'd0; 53.508 +assign i_we_o = `FALSE; 53.509 +assign i_sel_o = 4'b1111; 53.510 +`endif 53.511 +assign i_bte_o = `LM32_BTYPE_LINEAR; 53.512 +`endif 53.513 + 53.514 +`ifdef CFG_ICACHE_ENABLED 53.515 +// Determine parameters for next cache refill Wishbone access 53.516 +generate 53.517 + case (bytes_per_line) 53.518 + 4: 53.519 + begin 53.520 +assign first_cycle_type = `LM32_CTYPE_END; 53.521 +assign next_cycle_type = `LM32_CTYPE_END; 53.522 +assign last_word = `TRUE; 53.523 +assign first_address = icache_refill_address; 53.524 + end 53.525 + 8: 53.526 + begin 53.527 +assign first_cycle_type = `LM32_CTYPE_INCREMENTING; 53.528 +assign next_cycle_type = `LM32_CTYPE_END; 53.529 +assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 1'b1; 53.530 +assign first_address = {icache_refill_address[`LM32_PC_WIDTH+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}}; 53.531 + end 53.532 + 16: 53.533 + begin 53.534 +assign first_cycle_type = `LM32_CTYPE_INCREMENTING; 53.535 +assign next_cycle_type = i_adr_o[addr_offset_msb] == 1'b1 ? `LM32_CTYPE_END : `LM32_CTYPE_INCREMENTING; 53.536 +assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 2'b11; 53.537 +assign first_address = {icache_refill_address[`LM32_PC_WIDTH+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}}; 53.538 + end 53.539 + endcase 53.540 +endgenerate 53.541 +`endif 53.542 + 53.543 +///////////////////////////////////////////////////// 53.544 +// Sequential Logic 53.545 +///////////////////////////////////////////////////// 53.546 + 53.547 +// PC 53.548 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 53.549 +begin 53.550 + if (rst_i == `TRUE) 53.551 + begin 53.552 + pc_f <= (`CFG_EBA_RESET-4)/4; 53.553 + pc_d <= {`LM32_PC_WIDTH{1'b0}}; 53.554 + pc_x <= {`LM32_PC_WIDTH{1'b0}}; 53.555 + pc_m <= {`LM32_PC_WIDTH{1'b0}}; 53.556 + pc_w <= {`LM32_PC_WIDTH{1'b0}}; 53.557 + end 53.558 + else 53.559 + begin 53.560 + if (stall_f == `FALSE) 53.561 + pc_f <= pc_a; 53.562 + if (stall_d == `FALSE) 53.563 + pc_d <= pc_f; 53.564 + if (stall_x == `FALSE) 53.565 + pc_x <= pc_d; 53.566 + if (stall_m == `FALSE) 53.567 + pc_m <= pc_x; 53.568 + pc_w <= pc_m; 53.569 + end 53.570 +end 53.571 + 53.572 +`ifdef LM32_CACHE_ENABLED 53.573 +// Address to restart from after a cache miss has been handled 53.574 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 53.575 +begin 53.576 + if (rst_i == `TRUE) 53.577 + restart_address <= {`LM32_PC_WIDTH{1'b0}}; 53.578 + else 53.579 + begin 53.580 +`ifdef CFG_DCACHE_ENABLED 53.581 +`ifdef CFG_ICACHE_ENABLED 53.582 + // D-cache restart address must take priority, otherwise instructions will be lost 53.583 + if (dcache_refill_request == `TRUE) 53.584 + restart_address <= pc_w; 53.585 + else if ((icache_refill_request == `TRUE) && (!dcache_refilling) && (!dcache_restart_request)) 53.586 + restart_address <= icache_refill_address; 53.587 +`else 53.588 + if (dcache_refill_request == `TRUE) 53.589 + restart_address <= pc_w; 53.590 +`endif 53.591 +`else 53.592 +`ifdef CFG_ICACHE_ENABLED 53.593 + if (icache_refill_request == `TRUE) 53.594 + restart_address <= icache_refill_address; 53.595 +`endif 53.596 +`endif 53.597 + end 53.598 +end 53.599 +`endif 53.600 + 53.601 +// Record where instruction was fetched from 53.602 +`ifdef CFG_IROM_ENABLED 53.603 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 53.604 +begin 53.605 + if (rst_i == `TRUE) 53.606 + irom_select_f <= `FALSE; 53.607 + else 53.608 + begin 53.609 + if (stall_f == `FALSE) 53.610 + irom_select_f <= irom_select_a; 53.611 + end 53.612 +end 53.613 +`endif 53.614 + 53.615 +`ifdef CFG_HW_DEBUG_ENABLED 53.616 +assign jtag_access_complete = (i_cyc_o == `TRUE) && ((i_ack_i == `TRUE) || (i_err_i == `TRUE)) && (jtag_access == `TRUE); 53.617 +always @(*) 53.618 +begin 53.619 + case (jtag_address[1:0]) 53.620 + 2'b00: jtag_read_data = i_dat_i[`LM32_BYTE_3_RNG]; 53.621 + 2'b01: jtag_read_data = i_dat_i[`LM32_BYTE_2_RNG]; 53.622 + 2'b10: jtag_read_data = i_dat_i[`LM32_BYTE_1_RNG]; 53.623 + 2'b11: jtag_read_data = i_dat_i[`LM32_BYTE_0_RNG]; 53.624 + endcase 53.625 +end 53.626 +`endif 53.627 + 53.628 +`ifdef CFG_IWB_ENABLED 53.629 +// Instruction Wishbone interface 53.630 +`ifdef CFG_ICACHE_ENABLED 53.631 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 53.632 +begin 53.633 + if (rst_i == `TRUE) 53.634 + begin 53.635 + i_cyc_o <= `FALSE; 53.636 + i_stb_o <= `FALSE; 53.637 + i_adr_o <= {`LM32_WORD_WIDTH{1'b0}}; 53.638 + i_cti_o <= `LM32_CTYPE_END; 53.639 + i_lock_o <= `FALSE; 53.640 + icache_refill_data <= {`LM32_INSTRUCTION_WIDTH{1'b0}}; 53.641 + icache_refill_ready <= `FALSE; 53.642 +`ifdef CFG_BUS_ERRORS_ENABLED 53.643 + bus_error_f <= `FALSE; 53.644 +`endif 53.645 +`ifdef CFG_HW_DEBUG_ENABLED 53.646 + i_we_o <= `FALSE; 53.647 + i_sel_o <= 4'b1111; 53.648 + jtag_access <= `FALSE; 53.649 +`endif 53.650 + end 53.651 + else 53.652 + begin 53.653 + icache_refill_ready <= `FALSE; 53.654 + // Is a cycle in progress? 53.655 + if (i_cyc_o == `TRUE) 53.656 + begin 53.657 + // Has cycle completed? 53.658 + if ((i_ack_i == `TRUE) || (i_err_i == `TRUE)) 53.659 + begin 53.660 +`ifdef CFG_HW_DEBUG_ENABLED 53.661 + if (jtag_access == `TRUE) 53.662 + begin 53.663 + i_cyc_o <= `FALSE; 53.664 + i_stb_o <= `FALSE; 53.665 + i_we_o <= `FALSE; 53.666 + jtag_access <= `FALSE; 53.667 + end 53.668 + else 53.669 +`endif 53.670 + begin 53.671 + if (last_word == `TRUE) 53.672 + begin 53.673 + // Cache line fill complete 53.674 + i_cyc_o <= `FALSE; 53.675 + i_stb_o <= `FALSE; 53.676 + i_lock_o <= `FALSE; 53.677 + end 53.678 + // Fetch next word in cache line 53.679 + i_adr_o[addr_offset_msb:addr_offset_lsb] <= i_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1; 53.680 + i_cti_o <= next_cycle_type; 53.681 + // Write fetched data into instruction cache 53.682 + icache_refill_ready <= `TRUE; 53.683 + icache_refill_data <= i_dat_i; 53.684 + end 53.685 + end 53.686 +`ifdef CFG_BUS_ERRORS_ENABLED 53.687 + if (i_err_i == `TRUE) 53.688 + begin 53.689 + bus_error_f <= `TRUE; 53.690 + $display ("Instruction bus error. Address: %x", i_adr_o); 53.691 + end 53.692 +`endif 53.693 + end 53.694 + else 53.695 + begin 53.696 + if ((icache_refill_request == `TRUE) && (icache_refill_ready == `FALSE)) 53.697 + begin 53.698 + // Read first word of cache line 53.699 +`ifdef CFG_HW_DEBUG_ENABLED 53.700 + i_sel_o <= 4'b1111; 53.701 +`endif 53.702 + i_adr_o <= {first_address, 2'b00}; 53.703 + i_cyc_o <= `TRUE; 53.704 + i_stb_o <= `TRUE; 53.705 + i_cti_o <= first_cycle_type; 53.706 + //i_lock_o <= `TRUE; 53.707 +`ifdef CFG_BUS_ERRORS_ENABLED 53.708 + bus_error_f <= `FALSE; 53.709 +`endif 53.710 + end 53.711 +`ifdef CFG_HW_DEBUG_ENABLED 53.712 + else 53.713 + begin 53.714 + if ((jtag_read_enable == `TRUE) || (jtag_write_enable == `TRUE)) 53.715 + begin 53.716 + case (jtag_address[1:0]) 53.717 + 2'b00: i_sel_o <= 4'b1000; 53.718 + 2'b01: i_sel_o <= 4'b0100; 53.719 + 2'b10: i_sel_o <= 4'b0010; 53.720 + 2'b11: i_sel_o <= 4'b0001; 53.721 + endcase 53.722 + i_adr_o <= jtag_address; 53.723 + i_dat_o <= {4{jtag_write_data}}; 53.724 + i_cyc_o <= `TRUE; 53.725 + i_stb_o <= `TRUE; 53.726 + i_we_o <= jtag_write_enable; 53.727 + i_cti_o <= `LM32_CTYPE_END; 53.728 + jtag_access <= `TRUE; 53.729 + end 53.730 + end 53.731 +`endif 53.732 +`ifdef CFG_BUS_ERRORS_ENABLED 53.733 + // Clear bus error when exception taken, otherwise they would be 53.734 + // continually generated if exception handler is cached 53.735 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH 53.736 + if (branch_taken_x == `TRUE) 53.737 + bus_error_f <= `FALSE; 53.738 +`endif 53.739 + if (branch_taken_m == `TRUE) 53.740 + bus_error_f <= `FALSE; 53.741 +`endif 53.742 + end 53.743 + end 53.744 +end 53.745 +`else 53.746 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 53.747 +begin 53.748 + if (rst_i == `TRUE) 53.749 + begin 53.750 + i_cyc_o <= `FALSE; 53.751 + i_stb_o <= `FALSE; 53.752 + i_adr_o <= {`LM32_WORD_WIDTH{1'b0}}; 53.753 + i_cti_o <= `LM32_CTYPE_END; 53.754 + i_lock_o <= `FALSE; 53.755 + wb_data_f <= {`LM32_INSTRUCTION_WIDTH{1'b0}}; 53.756 +`ifdef CFG_BUS_ERRORS_ENABLED 53.757 + bus_error_f <= `FALSE; 53.758 +`endif 53.759 + end 53.760 + else 53.761 + begin 53.762 + // Is a cycle in progress? 53.763 + if (i_cyc_o == `TRUE) 53.764 + begin 53.765 + // Has cycle completed? 53.766 + if((i_ack_i == `TRUE) || (i_err_i == `TRUE)) 53.767 + begin 53.768 + // Cycle complete 53.769 + i_cyc_o <= `FALSE; 53.770 + i_stb_o <= `FALSE; 53.771 + // Register fetched instruction 53.772 + wb_data_f <= i_dat_i; 53.773 + end 53.774 +`ifdef CFG_BUS_ERRORS_ENABLED 53.775 + if (i_err_i == `TRUE) 53.776 + begin 53.777 + bus_error_f <= `TRUE; 53.778 + $display ("Instruction bus error. Address: %x", i_adr_o); 53.779 + end 53.780 +`endif 53.781 + end 53.782 + else 53.783 + begin 53.784 + // Wait for an instruction fetch from an external address 53.785 + if ( (stall_a == `FALSE) 53.786 +`ifdef CFG_IROM_ENABLED 53.787 + && (irom_select_a == `FALSE) 53.788 +`endif 53.789 + ) 53.790 + begin 53.791 + // Fetch instruction 53.792 +`ifdef CFG_HW_DEBUG_ENABLED 53.793 + i_sel_o <= 4'b1111; 53.794 +`endif 53.795 + i_adr_o <= {pc_a, 2'b00}; 53.796 + i_cyc_o <= `TRUE; 53.797 + i_stb_o <= `TRUE; 53.798 +`ifdef CFG_BUS_ERRORS_ENABLED 53.799 + bus_error_f <= `FALSE; 53.800 +`endif 53.801 + end 53.802 + else 53.803 + begin 53.804 + if ( (stall_a == `FALSE) 53.805 +`ifdef CFG_IROM_ENABLED 53.806 + && (irom_select_a == `TRUE) 53.807 +`endif 53.808 + ) 53.809 + begin 53.810 +`ifdef CFG_BUS_ERRORS_ENABLED 53.811 + bus_error_f <= `FALSE; 53.812 +`endif 53.813 + end 53.814 + end 53.815 + end 53.816 + end 53.817 +end 53.818 +`endif 53.819 +`endif 53.820 + 53.821 +// Instruction register 53.822 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 53.823 +begin 53.824 + if (rst_i == `TRUE) 53.825 + begin 53.826 + instruction_d <= {`LM32_INSTRUCTION_WIDTH{1'b0}}; 53.827 +`ifdef CFG_BUS_ERRORS_ENABLED 53.828 + bus_error_d <= `FALSE; 53.829 +`endif 53.830 + end 53.831 + else 53.832 + begin 53.833 + if (stall_d == `FALSE) 53.834 + begin 53.835 + instruction_d <= instruction_f; 53.836 +`ifdef CFG_BUS_ERRORS_ENABLED 53.837 + bus_error_d <= bus_error_f; 53.838 +`endif 53.839 + end 53.840 + end 53.841 +end 53.842 + 53.843 +endmodule
54.1 diff -r 252df75c8f67 -r c336e674a37e rtl/lm32_interrupt.v 54.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 54.3 +++ b/rtl/lm32_interrupt.v Tue Mar 08 09:40:42 2011 +0000 54.4 @@ -0,0 +1,335 @@ 54.5 +// ============================================================================= 54.6 +// COPYRIGHT NOTICE 54.7 +// Copyright 2006 (c) Lattice Semiconductor Corporation 54.8 +// ALL RIGHTS RESERVED 54.9 +// This confidential and proprietary software may be used only as authorised by 54.10 +// a licensing agreement from Lattice Semiconductor Corporation. 54.11 +// The entire notice above must be reproduced on all authorized copies and 54.12 +// copies may only be made to the extent permitted by a licensing agreement from 54.13 +// Lattice Semiconductor Corporation. 54.14 +// 54.15 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 54.16 +// 5555 NE Moore Court 408-826-6000 (other locations) 54.17 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 54.18 +// U.S.A email: techsupport@latticesemi.com 54.19 +// =============================================================================/ 54.20 +// FILE DETAILS 54.21 +// Project : LatticeMico32 54.22 +// File : lm32_interrupt.v 54.23 +// Title : Interrupt logic 54.24 +// Dependencies : lm32_include.v 54.25 +// Version : 6.1.17 54.26 +// : Initial Release 54.27 +// Version : 7.0SP2, 3.0 54.28 +// : No Change 54.29 +// Version : 3.1 54.30 +// : No Change 54.31 +// ============================================================================= 54.32 + 54.33 +`include "lm32_include.v" 54.34 + 54.35 +///////////////////////////////////////////////////// 54.36 +// Module interface 54.37 +///////////////////////////////////////////////////// 54.38 + 54.39 +module lm32_interrupt ( 54.40 + // ----- Inputs ------- 54.41 + clk_i, 54.42 + rst_i, 54.43 + // From external devices 54.44 + interrupt, 54.45 + // From pipeline 54.46 + stall_x, 54.47 +`ifdef CFG_DEBUG_ENABLED 54.48 + non_debug_exception, 54.49 + debug_exception, 54.50 +`else 54.51 + exception, 54.52 +`endif 54.53 + eret_q_x, 54.54 +`ifdef CFG_DEBUG_ENABLED 54.55 + bret_q_x, 54.56 +`endif 54.57 + csr, 54.58 + csr_write_data, 54.59 + csr_write_enable, 54.60 + // ----- Outputs ------- 54.61 + interrupt_exception, 54.62 + // To pipeline 54.63 + csr_read_data 54.64 + ); 54.65 + 54.66 +///////////////////////////////////////////////////// 54.67 +// Parameters 54.68 +///////////////////////////////////////////////////// 54.69 + 54.70 +parameter interrupts = `CFG_INTERRUPTS; // Number of interrupts 54.71 + 54.72 +///////////////////////////////////////////////////// 54.73 +// Inputs 54.74 +///////////////////////////////////////////////////// 54.75 + 54.76 +input clk_i; // Clock 54.77 +input rst_i; // Reset 54.78 + 54.79 +input [interrupts-1:0] interrupt; // Interrupt pins, active-low 54.80 + 54.81 +input stall_x; // Stall X pipeline stage 54.82 + 54.83 +`ifdef CFG_DEBUG_ENABLED 54.84 +input non_debug_exception; // Non-debug related exception has been raised 54.85 +input debug_exception; // Debug-related exception has been raised 54.86 +`else 54.87 +input exception; // Exception has been raised 54.88 +`endif 54.89 +input eret_q_x; // Return from exception 54.90 +`ifdef CFG_DEBUG_ENABLED 54.91 +input bret_q_x; // Return from breakpoint 54.92 +`endif 54.93 + 54.94 +input [`LM32_CSR_RNG] csr; // CSR read/write index 54.95 +input [`LM32_WORD_RNG] csr_write_data; // Data to write to specified CSR 54.96 +input csr_write_enable; // CSR write enable 54.97 + 54.98 +///////////////////////////////////////////////////// 54.99 +// Outputs 54.100 +///////////////////////////////////////////////////// 54.101 + 54.102 +output interrupt_exception; // Request to raide an interrupt exception 54.103 +wire interrupt_exception; 54.104 + 54.105 +output [`LM32_WORD_RNG] csr_read_data; // Data read from CSR 54.106 +reg [`LM32_WORD_RNG] csr_read_data; 54.107 + 54.108 +///////////////////////////////////////////////////// 54.109 +// Internal nets and registers 54.110 +///////////////////////////////////////////////////// 54.111 + 54.112 +wire [interrupts-1:0] asserted; // Which interrupts are currently being asserted 54.113 +//pragma attribute asserted preserve_signal true 54.114 +wire [interrupts-1:0] interrupt_n_exception; 54.115 + 54.116 +// Interrupt CSRs 54.117 + 54.118 +reg ie; // Interrupt enable 54.119 +reg eie; // Exception interrupt enable 54.120 +`ifdef CFG_DEBUG_ENABLED 54.121 +reg bie; // Breakpoint interrupt enable 54.122 +`endif 54.123 +reg [interrupts-1:0] ip; // Interrupt pending 54.124 +reg [interrupts-1:0] im; // Interrupt mask 54.125 + 54.126 +///////////////////////////////////////////////////// 54.127 +// Combinational Logic 54.128 +///////////////////////////////////////////////////// 54.129 + 54.130 +// Determine which interrupts have occured and are unmasked 54.131 +assign interrupt_n_exception = ip & im; 54.132 + 54.133 +// Determine if any unmasked interrupts have occured 54.134 +assign interrupt_exception = (|interrupt_n_exception) & ie; 54.135 + 54.136 +// Determine which interrupts are currently being asserted (active-low) or are already pending 54.137 +assign asserted = ip | interrupt; 54.138 + 54.139 +assign ie_csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}}, 54.140 +`ifdef CFG_DEBUG_ENABLED 54.141 + bie, 54.142 +`else 54.143 + 1'b0, 54.144 +`endif 54.145 + eie, 54.146 + ie 54.147 + }; 54.148 +assign ip_csr_read_data = ip; 54.149 +assign im_csr_read_data = im; 54.150 +generate 54.151 + if (interrupts > 1) 54.152 + begin 54.153 +// CSR read 54.154 +always @(*) 54.155 +begin 54.156 + case (csr) 54.157 + `LM32_CSR_IE: csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}}, 54.158 +`ifdef CFG_DEBUG_ENABLED 54.159 + bie, 54.160 +`else 54.161 + 1'b0, 54.162 +`endif 54.163 + eie, 54.164 + ie 54.165 + }; 54.166 + `LM32_CSR_IP: csr_read_data = ip; 54.167 + `LM32_CSR_IM: csr_read_data = im; 54.168 + default: csr_read_data = {`LM32_WORD_WIDTH{1'bx}}; 54.169 + endcase 54.170 +end 54.171 + end 54.172 + else 54.173 + begin 54.174 +// CSR read 54.175 +always @(*) 54.176 +begin 54.177 + case (csr) 54.178 + `LM32_CSR_IE: csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}}, 54.179 +`ifdef CFG_DEBUG_ENABLED 54.180 + bie, 54.181 +`else 54.182 + 1'b0, 54.183 +`endif 54.184 + eie, 54.185 + ie 54.186 + }; 54.187 + `LM32_CSR_IP: csr_read_data = ip; 54.188 + default: csr_read_data = {`LM32_WORD_WIDTH{1'bx}}; 54.189 + endcase 54.190 +end 54.191 + end 54.192 +endgenerate 54.193 + 54.194 +///////////////////////////////////////////////////// 54.195 +// Sequential Logic 54.196 +///////////////////////////////////////////////////// 54.197 + 54.198 +generate 54.199 + if (interrupts > 1) 54.200 + begin 54.201 +// IE, IM, IP - Interrupt Enable, Interrupt Mask and Interrupt Pending CSRs 54.202 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 54.203 +begin 54.204 + if (rst_i == `TRUE) 54.205 + begin 54.206 + ie <= `FALSE; 54.207 + eie <= `FALSE; 54.208 +`ifdef CFG_DEBUG_ENABLED 54.209 + bie <= `FALSE; 54.210 +`endif 54.211 + im <= {interrupts{1'b0}}; 54.212 + ip <= {interrupts{1'b0}}; 54.213 + end 54.214 + else 54.215 + begin 54.216 + // Set IP bit when interrupt line is asserted 54.217 + ip <= asserted; 54.218 +`ifdef CFG_DEBUG_ENABLED 54.219 + if (non_debug_exception == `TRUE) 54.220 + begin 54.221 + // Save and then clear interrupt enable 54.222 + eie <= ie; 54.223 + ie <= `FALSE; 54.224 + end 54.225 + else if (debug_exception == `TRUE) 54.226 + begin 54.227 + // Save and then clear interrupt enable 54.228 + bie <= ie; 54.229 + ie <= `FALSE; 54.230 + end 54.231 +`else 54.232 + if (exception == `TRUE) 54.233 + begin 54.234 + // Save and then clear interrupt enable 54.235 + eie <= ie; 54.236 + ie <= `FALSE; 54.237 + end 54.238 +`endif 54.239 + else if (stall_x == `FALSE) 54.240 + begin 54.241 + if (eret_q_x == `TRUE) 54.242 + // Restore interrupt enable 54.243 + ie <= eie; 54.244 +`ifdef CFG_DEBUG_ENABLED 54.245 + else if (bret_q_x == `TRUE) 54.246 + // Restore interrupt enable 54.247 + ie <= bie; 54.248 +`endif 54.249 + else if (csr_write_enable == `TRUE) 54.250 + begin 54.251 + // Handle wcsr write 54.252 + if (csr == `LM32_CSR_IE) 54.253 + begin 54.254 + ie <= csr_write_data[0]; 54.255 + eie <= csr_write_data[1]; 54.256 +`ifdef CFG_DEBUG_ENABLED 54.257 + bie <= csr_write_data[2]; 54.258 +`endif 54.259 + end 54.260 + if (csr == `LM32_CSR_IM) 54.261 + im <= csr_write_data[interrupts-1:0]; 54.262 + if (csr == `LM32_CSR_IP) 54.263 + ip <= asserted & ~csr_write_data[interrupts-1:0]; 54.264 + end 54.265 + end 54.266 + end 54.267 +end 54.268 + end 54.269 +else 54.270 + begin 54.271 +// IE, IM, IP - Interrupt Enable, Interrupt Mask and Interrupt Pending CSRs 54.272 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 54.273 +begin 54.274 + if (rst_i == `TRUE) 54.275 + begin 54.276 + ie <= `FALSE; 54.277 + eie <= `FALSE; 54.278 +`ifdef CFG_DEBUG_ENABLED 54.279 + bie <= `FALSE; 54.280 +`endif 54.281 + ip <= {interrupts{1'b0}}; 54.282 + end 54.283 + else 54.284 + begin 54.285 + // Set IP bit when interrupt line is asserted 54.286 + ip <= asserted; 54.287 +`ifdef CFG_DEBUG_ENABLED 54.288 + if (non_debug_exception == `TRUE) 54.289 + begin 54.290 + // Save and then clear interrupt enable 54.291 + eie <= ie; 54.292 + ie <= `FALSE; 54.293 + end 54.294 + else if (debug_exception == `TRUE) 54.295 + begin 54.296 + // Save and then clear interrupt enable 54.297 + bie <= ie; 54.298 + ie <= `FALSE; 54.299 + end 54.300 +`else 54.301 + if (exception == `TRUE) 54.302 + begin 54.303 + // Save and then clear interrupt enable 54.304 + eie <= ie; 54.305 + ie <= `FALSE; 54.306 + end 54.307 +`endif 54.308 + else if (stall_x == `FALSE) 54.309 + begin 54.310 + if (eret_q_x == `TRUE) 54.311 + // Restore interrupt enable 54.312 + ie <= eie; 54.313 +`ifdef CFG_DEBUG_ENABLED 54.314 + else if (bret_q_x == `TRUE) 54.315 + // Restore interrupt enable 54.316 + ie <= bie; 54.317 +`endif 54.318 + else if (csr_write_enable == `TRUE) 54.319 + begin 54.320 + // Handle wcsr write 54.321 + if (csr == `LM32_CSR_IE) 54.322 + begin 54.323 + ie <= csr_write_data[0]; 54.324 + eie <= csr_write_data[1]; 54.325 +`ifdef CFG_DEBUG_ENABLED 54.326 + bie <= csr_write_data[2]; 54.327 +`endif 54.328 + end 54.329 + if (csr == `LM32_CSR_IP) 54.330 + ip <= asserted & ~csr_write_data[interrupts-1:0]; 54.331 + end 54.332 + end 54.333 + end 54.334 +end 54.335 + end 54.336 +endgenerate 54.337 + 54.338 +endmodule 54.339 +
55.1 diff -r 252df75c8f67 -r c336e674a37e rtl/lm32_jtag.v 55.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 55.3 +++ b/rtl/lm32_jtag.v Tue Mar 08 09:40:42 2011 +0000 55.4 @@ -0,0 +1,469 @@ 55.5 +// ============================================================================= 55.6 +// COPYRIGHT NOTICE 55.7 +// Copyright 2006 (c) Lattice Semiconductor Corporation 55.8 +// ALL RIGHTS RESERVED 55.9 +// This confidential and proprietary software may be used only as authorised by 55.10 +// a licensing agreement from Lattice Semiconductor Corporation. 55.11 +// The entire notice above must be reproduced on all authorized copies and 55.12 +// copies may only be made to the extent permitted by a licensing agreement from 55.13 +// Lattice Semiconductor Corporation. 55.14 +// 55.15 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 55.16 +// 5555 NE Moore Court 408-826-6000 (other locations) 55.17 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 55.18 +// U.S.A email: techsupport@latticesemi.com 55.19 +// =============================================================================/ 55.20 +// FILE DETAILS 55.21 +// Project : LatticeMico32 55.22 +// File : lm32_jtag.v 55.23 +// Title : JTAG interface 55.24 +// Dependencies : lm32_include.v 55.25 +// Version : 6.1.17 55.26 +// : Initial Release 55.27 +// Version : 7.0SP2, 3.0 55.28 +// : No Change 55.29 +// Version : 3.1 55.30 +// : No Change 55.31 +// ============================================================================= 55.32 + 55.33 +`include "lm32_include.v" 55.34 + 55.35 +`ifdef CFG_JTAG_ENABLED 55.36 + 55.37 +`define LM32_DP 3'b000 55.38 +`define LM32_TX 3'b001 55.39 +`define LM32_RX 3'b010 55.40 + 55.41 +// LM32 Debug Protocol commands IDs 55.42 +`define LM32_DP_RNG 3:0 55.43 +`define LM32_DP_READ_MEMORY 4'b0001 55.44 +`define LM32_DP_WRITE_MEMORY 4'b0010 55.45 +`define LM32_DP_READ_SEQUENTIAL 4'b0011 55.46 +`define LM32_DP_WRITE_SEQUENTIAL 4'b0100 55.47 +`define LM32_DP_WRITE_CSR 4'b0101 55.48 +`define LM32_DP_BREAK 4'b0110 55.49 +`define LM32_DP_RESET 4'b0111 55.50 + 55.51 +// States for FSM 55.52 +`define LM32_JTAG_STATE_RNG 3:0 55.53 +`define LM32_JTAG_STATE_READ_COMMAND 4'h0 55.54 +`define LM32_JTAG_STATE_READ_BYTE_0 4'h1 55.55 +`define LM32_JTAG_STATE_READ_BYTE_1 4'h2 55.56 +`define LM32_JTAG_STATE_READ_BYTE_2 4'h3 55.57 +`define LM32_JTAG_STATE_READ_BYTE_3 4'h4 55.58 +`define LM32_JTAG_STATE_READ_BYTE_4 4'h5 55.59 +`define LM32_JTAG_STATE_PROCESS_COMMAND 4'h6 55.60 +`define LM32_JTAG_STATE_WAIT_FOR_MEMORY 4'h7 55.61 +`define LM32_JTAG_STATE_WAIT_FOR_CSR 4'h8 55.62 + 55.63 +///////////////////////////////////////////////////// 55.64 +// Module interface 55.65 +///////////////////////////////////////////////////// 55.66 + 55.67 +module lm32_jtag ( 55.68 + // ----- Inputs ------- 55.69 + clk_i, 55.70 + rst_i, 55.71 + jtag_clk, 55.72 + jtag_update, 55.73 + jtag_reg_q, 55.74 + jtag_reg_addr_q, 55.75 +`ifdef CFG_JTAG_UART_ENABLED 55.76 + csr, 55.77 + csr_write_enable, 55.78 + csr_write_data, 55.79 + stall_x, 55.80 +`endif 55.81 +`ifdef CFG_HW_DEBUG_ENABLED 55.82 + jtag_read_data, 55.83 + jtag_access_complete, 55.84 +`endif 55.85 +`ifdef CFG_DEBUG_ENABLED 55.86 + exception_q_w, 55.87 +`endif 55.88 + // ----- Outputs ------- 55.89 +`ifdef CFG_JTAG_UART_ENABLED 55.90 + jtx_csr_read_data, 55.91 + jrx_csr_read_data, 55.92 +`endif 55.93 +`ifdef CFG_HW_DEBUG_ENABLED 55.94 + jtag_csr_write_enable, 55.95 + jtag_csr_write_data, 55.96 + jtag_csr, 55.97 + jtag_read_enable, 55.98 + jtag_write_enable, 55.99 + jtag_write_data, 55.100 + jtag_address, 55.101 +`endif 55.102 +`ifdef CFG_DEBUG_ENABLED 55.103 + jtag_break, 55.104 + jtag_reset, 55.105 +`endif 55.106 + jtag_reg_d, 55.107 + jtag_reg_addr_d 55.108 + ); 55.109 + 55.110 +///////////////////////////////////////////////////// 55.111 +// Inputs 55.112 +///////////////////////////////////////////////////// 55.113 + 55.114 +input clk_i; // Clock 55.115 +input rst_i; // Reset 55.116 + 55.117 +input jtag_clk; // JTAG clock 55.118 +input jtag_update; // JTAG data register has been updated 55.119 +input [`LM32_BYTE_RNG] jtag_reg_q; // JTAG data register 55.120 +input [2:0] jtag_reg_addr_q; // JTAG data register 55.121 + 55.122 +`ifdef CFG_JTAG_UART_ENABLED 55.123 +input [`LM32_CSR_RNG] csr; // CSR to write 55.124 +input csr_write_enable; // CSR write enable 55.125 +input [`LM32_WORD_RNG] csr_write_data; // Data to write to specified CSR 55.126 +input stall_x; // Stall instruction in X stage 55.127 +`endif 55.128 +`ifdef CFG_HW_DEBUG_ENABLED 55.129 +input [`LM32_BYTE_RNG] jtag_read_data; // Data read from requested address 55.130 +input jtag_access_complete; // Memory access if complete 55.131 +`endif 55.132 +`ifdef CFG_DEBUG_ENABLED 55.133 +input exception_q_w; // Indicates an exception has occured in W stage 55.134 +`endif 55.135 + 55.136 +///////////////////////////////////////////////////// 55.137 +// Outputs 55.138 +///////////////////////////////////////////////////// 55.139 + 55.140 +`ifdef CFG_JTAG_UART_ENABLED 55.141 +output [`LM32_WORD_RNG] jtx_csr_read_data; // Value of JTX CSR for rcsr instructions 55.142 +wire [`LM32_WORD_RNG] jtx_csr_read_data; 55.143 +output [`LM32_WORD_RNG] jrx_csr_read_data; // Value of JRX CSR for rcsr instructions 55.144 +wire [`LM32_WORD_RNG] jrx_csr_read_data; 55.145 +`endif 55.146 +`ifdef CFG_HW_DEBUG_ENABLED 55.147 +output jtag_csr_write_enable; // CSR write enable 55.148 +reg jtag_csr_write_enable; 55.149 +output [`LM32_WORD_RNG] jtag_csr_write_data; // Data to write to specified CSR 55.150 +wire [`LM32_WORD_RNG] jtag_csr_write_data; 55.151 +output [`LM32_CSR_RNG] jtag_csr; // CSR to write 55.152 +wire [`LM32_CSR_RNG] jtag_csr; 55.153 +output jtag_read_enable; // Memory read enable 55.154 +reg jtag_read_enable; 55.155 +output jtag_write_enable; // Memory write enable 55.156 +reg jtag_write_enable; 55.157 +output [`LM32_BYTE_RNG] jtag_write_data; // Data to write to specified address 55.158 +wire [`LM32_BYTE_RNG] jtag_write_data; 55.159 +output [`LM32_WORD_RNG] jtag_address; // Memory read/write address 55.160 +wire [`LM32_WORD_RNG] jtag_address; 55.161 +`endif 55.162 +`ifdef CFG_DEBUG_ENABLED 55.163 +output jtag_break; // Request to raise a breakpoint exception 55.164 +reg jtag_break; 55.165 +output jtag_reset; // Request to raise a reset exception 55.166 +reg jtag_reset; 55.167 +`endif 55.168 +output [`LM32_BYTE_RNG] jtag_reg_d; 55.169 +reg [`LM32_BYTE_RNG] jtag_reg_d; 55.170 +output [2:0] jtag_reg_addr_d; 55.171 +wire [2:0] jtag_reg_addr_d; 55.172 + 55.173 +///////////////////////////////////////////////////// 55.174 +// Internal nets and registers 55.175 +///////////////////////////////////////////////////// 55.176 + 55.177 +reg rx_update; // Clock-domain crossing registers 55.178 +reg rx_update_r; // Registered version of rx_update 55.179 +reg rx_update_r_r; // Registered version of rx_update_r 55.180 +reg rx_update_r_r_r; // Registered version of rx_update_r_r 55.181 + 55.182 +// These wires come from the JTAG clock domain. 55.183 +// They have been held unchanged for an entire JTAG clock cycle before the jtag_update toggle flips 55.184 +wire [`LM32_BYTE_RNG] rx_byte; 55.185 +wire [2:0] rx_addr; 55.186 + 55.187 +`ifdef CFG_JTAG_UART_ENABLED 55.188 +reg [`LM32_BYTE_RNG] uart_tx_byte; // UART TX data 55.189 +reg uart_tx_valid; // TX data is valid 55.190 +reg [`LM32_BYTE_RNG] uart_rx_byte; // UART RX data 55.191 +reg uart_rx_valid; // RX data is valid 55.192 +`endif 55.193 + 55.194 +reg [`LM32_DP_RNG] command; // The last received command 55.195 +`ifdef CFG_HW_DEBUG_ENABLED 55.196 +reg [`LM32_BYTE_RNG] jtag_byte_0; // Registers to hold command paramaters 55.197 +reg [`LM32_BYTE_RNG] jtag_byte_1; 55.198 +reg [`LM32_BYTE_RNG] jtag_byte_2; 55.199 +reg [`LM32_BYTE_RNG] jtag_byte_3; 55.200 +reg [`LM32_BYTE_RNG] jtag_byte_4; 55.201 +reg processing; // Indicates if we're still processing a memory read/write 55.202 +`endif 55.203 + 55.204 +reg [`LM32_JTAG_STATE_RNG] state; // Current state of FSM 55.205 + 55.206 +///////////////////////////////////////////////////// 55.207 +// Combinational Logic 55.208 +///////////////////////////////////////////////////// 55.209 + 55.210 +`ifdef CFG_HW_DEBUG_ENABLED 55.211 +assign jtag_csr_write_data = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3}; 55.212 +assign jtag_csr = jtag_byte_4[`LM32_CSR_RNG]; 55.213 +assign jtag_address = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3}; 55.214 +assign jtag_write_data = jtag_byte_4; 55.215 +`endif 55.216 + 55.217 +// Generate status flags for reading via the JTAG interface 55.218 +`ifdef CFG_JTAG_UART_ENABLED 55.219 +assign jtag_reg_addr_d[1:0] = {uart_rx_valid, uart_tx_valid}; 55.220 +`else 55.221 +assign jtag_reg_addr_d[1:0] = 2'b00; 55.222 +`endif 55.223 +`ifdef CFG_HW_DEBUG_ENABLED 55.224 +assign jtag_reg_addr_d[2] = processing; 55.225 +`else 55.226 +assign jtag_reg_addr_d[2] = 1'b0; 55.227 +`endif 55.228 + 55.229 +`ifdef CFG_JTAG_UART_ENABLED 55.230 +assign jtx_csr_read_data = {{`LM32_WORD_WIDTH-9{1'b0}}, uart_tx_valid, 8'h00}; 55.231 +assign jrx_csr_read_data = {{`LM32_WORD_WIDTH-9{1'b0}}, uart_rx_valid, uart_rx_byte}; 55.232 +`endif 55.233 + 55.234 +///////////////////////////////////////////////////// 55.235 +// Sequential Logic 55.236 +///////////////////////////////////////////////////// 55.237 + 55.238 +assign rx_byte = jtag_reg_q; 55.239 +assign rx_addr = jtag_reg_addr_q; 55.240 + 55.241 +// The JTAG latched jtag_reg[_addr]_q at least one JTCK before jtag_update is raised 55.242 +// Thus, they are stable (and safe to sample) when jtag_update is high 55.243 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 55.244 +begin 55.245 + if (rst_i == `TRUE) 55.246 + begin 55.247 + rx_update <= 1'b0; 55.248 + rx_update_r <= 1'b0; 55.249 + rx_update_r_r <= 1'b0; 55.250 + rx_update_r_r_r <= 1'b0; 55.251 + end 55.252 + else 55.253 + begin 55.254 + rx_update <= jtag_update; 55.255 + rx_update_r <= rx_update; 55.256 + rx_update_r_r <= rx_update_r; 55.257 + rx_update_r_r_r <= rx_update_r_r; 55.258 + end 55.259 +end 55.260 + 55.261 +// LM32 debug protocol state machine 55.262 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 55.263 +begin 55.264 + if (rst_i == `TRUE) 55.265 + begin 55.266 + state <= `LM32_JTAG_STATE_READ_COMMAND; 55.267 + command <= 4'b0000; 55.268 + jtag_reg_d <= 8'h00; 55.269 +`ifdef CFG_HW_DEBUG_ENABLED 55.270 + processing <= `FALSE; 55.271 + jtag_csr_write_enable <= `FALSE; 55.272 + jtag_read_enable <= `FALSE; 55.273 + jtag_write_enable <= `FALSE; 55.274 +`endif 55.275 +`ifdef CFG_DEBUG_ENABLED 55.276 + jtag_break <= `FALSE; 55.277 + jtag_reset <= `FALSE; 55.278 +`endif 55.279 +`ifdef CFG_JTAG_UART_ENABLED 55.280 + uart_tx_byte <= 8'h00; 55.281 + uart_tx_valid <= `FALSE; 55.282 + uart_rx_byte <= 8'h00; 55.283 + uart_rx_valid <= `FALSE; 55.284 +`endif 55.285 + end 55.286 + else 55.287 + begin 55.288 +`ifdef CFG_JTAG_UART_ENABLED 55.289 + if ((csr_write_enable == `TRUE) && (stall_x == `FALSE)) 55.290 + begin 55.291 + case (csr) 55.292 + `LM32_CSR_JTX: 55.293 + begin 55.294 + // Set flag indicating data is available 55.295 + uart_tx_byte <= csr_write_data[`LM32_BYTE_0_RNG]; 55.296 + uart_tx_valid <= `TRUE; 55.297 + end 55.298 + `LM32_CSR_JRX: 55.299 + begin 55.300 + // Clear flag indidicating data has been received 55.301 + uart_rx_valid <= `FALSE; 55.302 + end 55.303 + endcase 55.304 + end 55.305 +`endif 55.306 +`ifdef CFG_DEBUG_ENABLED 55.307 + // When an exception has occured, clear the requests 55.308 + if (exception_q_w == `TRUE) 55.309 + begin 55.310 + jtag_break <= `FALSE; 55.311 + jtag_reset <= `FALSE; 55.312 + end 55.313 +`endif 55.314 + case (state) 55.315 + `LM32_JTAG_STATE_READ_COMMAND: 55.316 + begin 55.317 + // Wait for rx register to toggle which indicates new data is available 55.318 + if ((~rx_update_r_r_r & rx_update_r_r) == `TRUE) 55.319 + begin 55.320 + command <= rx_byte[7:4]; 55.321 + case (rx_addr) 55.322 +`ifdef CFG_DEBUG_ENABLED 55.323 + `LM32_DP: 55.324 + begin 55.325 + case (rx_byte[7:4]) 55.326 +`ifdef CFG_HW_DEBUG_ENABLED 55.327 + `LM32_DP_READ_MEMORY: 55.328 + state <= `LM32_JTAG_STATE_READ_BYTE_0; 55.329 + `LM32_DP_READ_SEQUENTIAL: 55.330 + begin 55.331 + {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1; 55.332 + state <= `LM32_JTAG_STATE_PROCESS_COMMAND; 55.333 + end 55.334 + `LM32_DP_WRITE_MEMORY: 55.335 + state <= `LM32_JTAG_STATE_READ_BYTE_0; 55.336 + `LM32_DP_WRITE_SEQUENTIAL: 55.337 + begin 55.338 + {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1; 55.339 + state <= 5; 55.340 + end 55.341 + `LM32_DP_WRITE_CSR: 55.342 + state <= `LM32_JTAG_STATE_READ_BYTE_0; 55.343 +`endif 55.344 + `LM32_DP_BREAK: 55.345 + begin 55.346 +`ifdef CFG_JTAG_UART_ENABLED 55.347 + uart_rx_valid <= `FALSE; 55.348 + uart_tx_valid <= `FALSE; 55.349 +`endif 55.350 + jtag_break <= `TRUE; 55.351 + end 55.352 + `LM32_DP_RESET: 55.353 + begin 55.354 +`ifdef CFG_JTAG_UART_ENABLED 55.355 + uart_rx_valid <= `FALSE; 55.356 + uart_tx_valid <= `FALSE; 55.357 +`endif 55.358 + jtag_reset <= `TRUE; 55.359 + end 55.360 + endcase 55.361 + end 55.362 +`endif 55.363 +`ifdef CFG_JTAG_UART_ENABLED 55.364 + `LM32_TX: 55.365 + begin 55.366 + uart_rx_byte <= rx_byte; 55.367 + uart_rx_valid <= `TRUE; 55.368 + end 55.369 + `LM32_RX: 55.370 + begin 55.371 + jtag_reg_d <= uart_tx_byte; 55.372 + uart_tx_valid <= `FALSE; 55.373 + end 55.374 +`endif 55.375 + default: 55.376 + ; 55.377 + endcase 55.378 + end 55.379 + end 55.380 +`ifdef CFG_HW_DEBUG_ENABLED 55.381 + `LM32_JTAG_STATE_READ_BYTE_0: 55.382 + begin 55.383 + if ((~rx_update_r_r_r & rx_update_r_r) == `TRUE) 55.384 + begin 55.385 + jtag_byte_0 <= rx_byte; 55.386 + state <= `LM32_JTAG_STATE_READ_BYTE_1; 55.387 + end 55.388 + end 55.389 + `LM32_JTAG_STATE_READ_BYTE_1: 55.390 + begin 55.391 + if ((~rx_update_r_r_r & rx_update_r_r) == `TRUE) 55.392 + begin 55.393 + jtag_byte_1 <= rx_byte; 55.394 + state <= `LM32_JTAG_STATE_READ_BYTE_2; 55.395 + end 55.396 + end 55.397 + `LM32_JTAG_STATE_READ_BYTE_2: 55.398 + begin 55.399 + if ((~rx_update_r_r_r & rx_update_r_r) == `TRUE) 55.400 + begin 55.401 + jtag_byte_2 <= rx_byte; 55.402 + state <= `LM32_JTAG_STATE_READ_BYTE_3; 55.403 + end 55.404 + end 55.405 + `LM32_JTAG_STATE_READ_BYTE_3: 55.406 + begin 55.407 + if ((~rx_update_r_r_r & rx_update_r_r) == `TRUE) 55.408 + begin 55.409 + jtag_byte_3 <= rx_byte; 55.410 + if (command == `LM32_DP_READ_MEMORY) 55.411 + state <= `LM32_JTAG_STATE_PROCESS_COMMAND; 55.412 + else 55.413 + state <= `LM32_JTAG_STATE_READ_BYTE_4; 55.414 + end 55.415 + end 55.416 + `LM32_JTAG_STATE_READ_BYTE_4: 55.417 + begin 55.418 + if ((~rx_update_r_r_r & rx_update_r_r) == `TRUE) 55.419 + begin 55.420 + jtag_byte_4 <= rx_byte; 55.421 + state <= `LM32_JTAG_STATE_PROCESS_COMMAND; 55.422 + end 55.423 + end 55.424 + `LM32_JTAG_STATE_PROCESS_COMMAND: 55.425 + begin 55.426 + case (command) 55.427 + `LM32_DP_READ_MEMORY, 55.428 + `LM32_DP_READ_SEQUENTIAL: 55.429 + begin 55.430 + jtag_read_enable <= `TRUE; 55.431 + processing <= `TRUE; 55.432 + state <= `LM32_JTAG_STATE_WAIT_FOR_MEMORY; 55.433 + end 55.434 + `LM32_DP_WRITE_MEMORY, 55.435 + `LM32_DP_WRITE_SEQUENTIAL: 55.436 + begin 55.437 + jtag_write_enable <= `TRUE; 55.438 + processing <= `TRUE; 55.439 + state <= `LM32_JTAG_STATE_WAIT_FOR_MEMORY; 55.440 + end 55.441 + `LM32_DP_WRITE_CSR: 55.442 + begin 55.443 + jtag_csr_write_enable <= `TRUE; 55.444 + processing <= `TRUE; 55.445 + state <= `LM32_JTAG_STATE_WAIT_FOR_CSR; 55.446 + end 55.447 + endcase 55.448 + end 55.449 + `LM32_JTAG_STATE_WAIT_FOR_MEMORY: 55.450 + begin 55.451 + if (jtag_access_complete == `TRUE) 55.452 + begin 55.453 + jtag_read_enable <= `FALSE; 55.454 + jtag_reg_d <= jtag_read_data; 55.455 + jtag_write_enable <= `FALSE; 55.456 + processing <= `FALSE; 55.457 + state <= `LM32_JTAG_STATE_READ_COMMAND; 55.458 + end 55.459 + end 55.460 + `LM32_JTAG_STATE_WAIT_FOR_CSR: 55.461 + begin 55.462 + jtag_csr_write_enable <= `FALSE; 55.463 + processing <= `FALSE; 55.464 + state <= `LM32_JTAG_STATE_READ_COMMAND; 55.465 + end 55.466 +`endif 55.467 + endcase 55.468 + end 55.469 +end 55.470 + 55.471 +endmodule 55.472 + 55.473 +`endif
56.1 diff -r 252df75c8f67 -r c336e674a37e rtl/lm32_load_store_unit.v 56.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 56.3 +++ b/rtl/lm32_load_store_unit.v Tue Mar 08 09:40:42 2011 +0000 56.4 @@ -0,0 +1,806 @@ 56.5 +// ============================================================================= 56.6 +// COPYRIGHT NOTICE 56.7 +// Copyright 2006 (c) Lattice Semiconductor Corporation 56.8 +// ALL RIGHTS RESERVED 56.9 +// This confidential and proprietary software may be used only as authorised by 56.10 +// a licensing agreement from Lattice Semiconductor Corporation. 56.11 +// The entire notice above must be reproduced on all authorized copies and 56.12 +// copies may only be made to the extent permitted by a licensing agreement from 56.13 +// Lattice Semiconductor Corporation. 56.14 +// 56.15 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 56.16 +// 5555 NE Moore Court 408-826-6000 (other locations) 56.17 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 56.18 +// U.S.A email: techsupport@latticesemi.com 56.19 +// =============================================================================/ 56.20 +// FILE DETAILS 56.21 +// Project : LatticeMico32 56.22 +// File : lm32_load_store_unit.v 56.23 +// Title : Load and store unit 56.24 +// Dependencies : lm32_include.v 56.25 +// Version : 6.1.17 56.26 +// : Initial Release 56.27 +// Version : 7.0SP2, 3.0 56.28 +// : No Change 56.29 +// Version : 3.1 56.30 +// : Instead of disallowing an instruction cache miss on a data cache 56.31 +// : miss, both can now occur at the same time. If both occur at same 56.32 +// : time, then restart address is the address of instruction that 56.33 +// : caused data cache miss. 56.34 +// Version : 3.2 56.35 +// : EBRs use SYNC resets instead of ASYNC resets. 56.36 +// Version : 3.3 56.37 +// : Support for new non-cacheable Data Memory that is accessible by 56.38 +// : the data port and has a one cycle access latency. 56.39 +// Version : 3.4 56.40 +// : No change 56.41 +// Version : 3.5 56.42 +// : Bug fix: Inline memory is correctly generated if it is not a 56.43 +// : power-of-two 56.44 +// ============================================================================= 56.45 + 56.46 +`include "lm32_include.v" 56.47 + 56.48 +///////////////////////////////////////////////////// 56.49 +// Module interface 56.50 +///////////////////////////////////////////////////// 56.51 + 56.52 +module lm32_load_store_unit ( 56.53 + // ----- Inputs ------- 56.54 + clk_i, 56.55 + rst_i, 56.56 + // From pipeline 56.57 + stall_a, 56.58 + stall_x, 56.59 + stall_m, 56.60 + kill_m, 56.61 + exception_m, 56.62 + store_operand_x, 56.63 + load_store_address_x, 56.64 + load_store_address_m, 56.65 + load_store_address_w, 56.66 + load_x, 56.67 + store_x, 56.68 + load_q_x, 56.69 + store_q_x, 56.70 + load_q_m, 56.71 + store_q_m, 56.72 + sign_extend_x, 56.73 + size_x, 56.74 +`ifdef CFG_DCACHE_ENABLED 56.75 + dflush, 56.76 +`endif 56.77 +`ifdef CFG_IROM_ENABLED 56.78 + irom_data_m, 56.79 +`endif 56.80 + // From Wishbone 56.81 + d_dat_i, 56.82 + d_ack_i, 56.83 + d_err_i, 56.84 + d_rty_i, 56.85 + // ----- Outputs ------- 56.86 + // To pipeline 56.87 +`ifdef CFG_DCACHE_ENABLED 56.88 + dcache_refill_request, 56.89 + dcache_restart_request, 56.90 + dcache_stall_request, 56.91 + dcache_refilling, 56.92 +`endif 56.93 +`ifdef CFG_IROM_ENABLED 56.94 + irom_store_data_m, 56.95 + irom_address_xm, 56.96 + irom_we_xm, 56.97 + irom_stall_request_x, 56.98 +`endif 56.99 + load_data_w, 56.100 + stall_wb_load, 56.101 + // To Wishbone 56.102 + d_dat_o, 56.103 + d_adr_o, 56.104 + d_cyc_o, 56.105 + d_sel_o, 56.106 + d_stb_o, 56.107 + d_we_o, 56.108 + d_cti_o, 56.109 + d_lock_o, 56.110 + d_bte_o 56.111 + ); 56.112 + 56.113 +///////////////////////////////////////////////////// 56.114 +// Parameters 56.115 +///////////////////////////////////////////////////// 56.116 + 56.117 +parameter associativity = 1; // Associativity of the cache (Number of ways) 56.118 +parameter sets = 512; // Number of sets 56.119 +parameter bytes_per_line = 16; // Number of bytes per cache line 56.120 +parameter base_address = 0; // Base address of cachable memory 56.121 +parameter limit = 0; // Limit (highest address) of cachable memory 56.122 + 56.123 +// For bytes_per_line == 4, we set 1 so part-select range isn't reversed, even though not really used 56.124 +localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2; 56.125 +localparam addr_offset_lsb = 2; 56.126 +localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1); 56.127 + 56.128 +///////////////////////////////////////////////////// 56.129 +// Inputs 56.130 +///////////////////////////////////////////////////// 56.131 + 56.132 +input clk_i; // Clock 56.133 +input rst_i; // Reset 56.134 + 56.135 +input stall_a; // A stage stall 56.136 +input stall_x; // X stage stall 56.137 +input stall_m; // M stage stall 56.138 +input kill_m; // Kill instruction in M stage 56.139 +input exception_m; // An exception occured in the M stage 56.140 + 56.141 +input [`LM32_WORD_RNG] store_operand_x; // Data read from register to store 56.142 +input [`LM32_WORD_RNG] load_store_address_x; // X stage load/store address 56.143 +input [`LM32_WORD_RNG] load_store_address_m; // M stage load/store address 56.144 +input [1:0] load_store_address_w; // W stage load/store address (only least two significant bits are needed) 56.145 +input load_x; // Load instruction in X stage 56.146 +input store_x; // Store instruction in X stage 56.147 +input load_q_x; // Load instruction in X stage 56.148 +input store_q_x; // Store instruction in X stage 56.149 +input load_q_m; // Load instruction in M stage 56.150 +input store_q_m; // Store instruction in M stage 56.151 +input sign_extend_x; // Whether load instruction in X stage should sign extend or zero extend 56.152 +input [`LM32_SIZE_RNG] size_x; // Size of load or store (byte, hword, word) 56.153 + 56.154 +`ifdef CFG_DCACHE_ENABLED 56.155 +input dflush; // Flush the data cache 56.156 +`endif 56.157 + 56.158 +`ifdef CFG_IROM_ENABLED 56.159 +input [`LM32_WORD_RNG] irom_data_m; // Data from Instruction-ROM 56.160 +`endif 56.161 + 56.162 +input [`LM32_WORD_RNG] d_dat_i; // Data Wishbone interface read data 56.163 +input d_ack_i; // Data Wishbone interface acknowledgement 56.164 +input d_err_i; // Data Wishbone interface error 56.165 +input d_rty_i; // Data Wishbone interface retry 56.166 + 56.167 +///////////////////////////////////////////////////// 56.168 +// Outputs 56.169 +///////////////////////////////////////////////////// 56.170 + 56.171 +`ifdef CFG_DCACHE_ENABLED 56.172 +output dcache_refill_request; // Request to refill data cache 56.173 +wire dcache_refill_request; 56.174 +output dcache_restart_request; // Request to restart the instruction that caused a data cache miss 56.175 +wire dcache_restart_request; 56.176 +output dcache_stall_request; // Data cache stall request 56.177 +wire dcache_stall_request; 56.178 +output dcache_refilling; 56.179 +wire dcache_refilling; 56.180 +`endif 56.181 + 56.182 +`ifdef CFG_IROM_ENABLED 56.183 +output irom_store_data_m; // Store data to Instruction ROM 56.184 +wire [`LM32_WORD_RNG] irom_store_data_m; 56.185 +output [`LM32_WORD_RNG] irom_address_xm; // Load/store address to Instruction ROM 56.186 +wire [`LM32_WORD_RNG] irom_address_xm; 56.187 +output irom_we_xm; // Write-enable of 2nd port of Instruction ROM 56.188 +wire irom_we_xm; 56.189 +output irom_stall_request_x; // Stall instruction in D stage 56.190 +wire irom_stall_request_x; 56.191 +`endif 56.192 + 56.193 +output [`LM32_WORD_RNG] load_data_w; // Result of a load instruction 56.194 +reg [`LM32_WORD_RNG] load_data_w; 56.195 +output stall_wb_load; // Request to stall pipeline due to a load from the Wishbone interface 56.196 +reg stall_wb_load; 56.197 + 56.198 +output [`LM32_WORD_RNG] d_dat_o; // Data Wishbone interface write data 56.199 +reg [`LM32_WORD_RNG] d_dat_o; 56.200 +output [`LM32_WORD_RNG] d_adr_o; // Data Wishbone interface address 56.201 +reg [`LM32_WORD_RNG] d_adr_o; 56.202 +output d_cyc_o; // Data Wishbone interface cycle 56.203 +reg d_cyc_o; 56.204 +output [`LM32_BYTE_SELECT_RNG] d_sel_o; // Data Wishbone interface byte select 56.205 +reg [`LM32_BYTE_SELECT_RNG] d_sel_o; 56.206 +output d_stb_o; // Data Wishbone interface strobe 56.207 +reg d_stb_o; 56.208 +output d_we_o; // Data Wishbone interface write enable 56.209 +reg d_we_o; 56.210 +output [`LM32_CTYPE_RNG] d_cti_o; // Data Wishbone interface cycle type 56.211 +reg [`LM32_CTYPE_RNG] d_cti_o; 56.212 +output d_lock_o; // Date Wishbone interface lock bus 56.213 +reg d_lock_o; 56.214 +output [`LM32_BTYPE_RNG] d_bte_o; // Data Wishbone interface burst type 56.215 +wire [`LM32_BTYPE_RNG] d_bte_o; 56.216 + 56.217 +///////////////////////////////////////////////////// 56.218 +// Internal nets and registers 56.219 +///////////////////////////////////////////////////// 56.220 + 56.221 +// Microcode pipeline registers - See inputs for description 56.222 +reg [`LM32_SIZE_RNG] size_m; 56.223 +reg [`LM32_SIZE_RNG] size_w; 56.224 +reg sign_extend_m; 56.225 +reg sign_extend_w; 56.226 +reg [`LM32_WORD_RNG] store_data_x; 56.227 +reg [`LM32_WORD_RNG] store_data_m; 56.228 +reg [`LM32_BYTE_SELECT_RNG] byte_enable_x; 56.229 +reg [`LM32_BYTE_SELECT_RNG] byte_enable_m; 56.230 +wire [`LM32_WORD_RNG] data_m; 56.231 +reg [`LM32_WORD_RNG] data_w; 56.232 + 56.233 +`ifdef CFG_DCACHE_ENABLED 56.234 +wire dcache_select_x; // Select data cache to load from / store to 56.235 +reg dcache_select_m; 56.236 +wire [`LM32_WORD_RNG] dcache_data_m; // Data read from cache 56.237 +wire [`LM32_WORD_RNG] dcache_refill_address; // Address to refill data cache from 56.238 +reg dcache_refill_ready; // Indicates the next word of refill data is ready 56.239 +wire [`LM32_CTYPE_RNG] first_cycle_type; // First Wishbone cycle type 56.240 +wire [`LM32_CTYPE_RNG] next_cycle_type; // Next Wishbone cycle type 56.241 +wire last_word; // Indicates if this is the last word in the cache line 56.242 +wire [`LM32_WORD_RNG] first_address; // First cache refill address 56.243 +`endif 56.244 +`ifdef CFG_DRAM_ENABLED 56.245 +wire dram_select_x; // Select data RAM to load from / store to 56.246 +reg dram_select_m; 56.247 +reg dram_bypass_en; // RAW in data RAM; read latched (bypass) value rather than value from memory 56.248 +reg [`LM32_WORD_RNG] dram_bypass_data; // Latched value of store'd data to data RAM 56.249 +wire [`LM32_WORD_RNG] dram_data_out; // Data read from data RAM 56.250 +wire [`LM32_WORD_RNG] dram_data_m; // Data read from data RAM: bypass value or value from memory 56.251 +wire [`LM32_WORD_RNG] dram_store_data_m; // Data to write to RAM 56.252 +`endif 56.253 +wire wb_select_x; // Select Wishbone to load from / store to 56.254 +`ifdef CFG_IROM_ENABLED 56.255 +wire irom_select_x; // Select instruction ROM to load from / store to 56.256 +reg irom_select_m; 56.257 +`endif 56.258 +reg wb_select_m; 56.259 +reg [`LM32_WORD_RNG] wb_data_m; // Data read from Wishbone 56.260 +reg wb_load_complete; // Indicates when a Wishbone load is complete 56.261 + 56.262 +///////////////////////////////////////////////////// 56.263 +// Functions 56.264 +///////////////////////////////////////////////////// 56.265 + 56.266 +`include "lm32_functions.v" 56.267 + 56.268 +///////////////////////////////////////////////////// 56.269 +// Instantiations 56.270 +///////////////////////////////////////////////////// 56.271 + 56.272 +`ifdef CFG_DRAM_ENABLED 56.273 + // Data RAM 56.274 + pmi_ram_dp_true 56.275 + #( 56.276 + // ----- Parameters ------- 56.277 + .pmi_family (`LATTICE_FAMILY), 56.278 + 56.279 + //.pmi_addr_depth_a (1 << (clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)), 56.280 + //.pmi_addr_width_a ((clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)), 56.281 + //.pmi_data_width_a (`LM32_WORD_WIDTH), 56.282 + //.pmi_addr_depth_b (1 << (clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)), 56.283 + //.pmi_addr_width_b ((clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)), 56.284 + //.pmi_data_width_b (`LM32_WORD_WIDTH), 56.285 + 56.286 + .pmi_addr_depth_a (`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1), 56.287 + .pmi_addr_width_a (clogb2_v1(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)), 56.288 + .pmi_data_width_a (`LM32_WORD_WIDTH), 56.289 + .pmi_addr_depth_b (`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1), 56.290 + .pmi_addr_width_b (clogb2_v1(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)), 56.291 + .pmi_data_width_b (`LM32_WORD_WIDTH), 56.292 + 56.293 + .pmi_regmode_a ("noreg"), 56.294 + .pmi_regmode_b ("noreg"), 56.295 + .pmi_gsr ("enable"), 56.296 + .pmi_resetmode ("sync"), 56.297 + .pmi_init_file (`CFG_DRAM_INIT_FILE), 56.298 + .pmi_init_file_format (`CFG_DRAM_INIT_FILE_FORMAT), 56.299 + .module_type ("pmi_ram_dp_true") 56.300 + ) 56.301 + ram ( 56.302 + // ----- Inputs ------- 56.303 + .ClockA (clk_i), 56.304 + .ClockB (clk_i), 56.305 + .ResetA (rst_i), 56.306 + .ResetB (rst_i), 56.307 + .DataInA ({32{1'b0}}), 56.308 + .DataInB (dram_store_data_m), 56.309 + .AddressA (load_store_address_x[(clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)+2-1:2]), 56.310 + .AddressB (load_store_address_m[(clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)+2-1:2]), 56.311 + // .ClockEnA (!stall_x & (load_x | store_x)), 56.312 + .ClockEnA (!stall_x), 56.313 + .ClockEnB (!stall_m), 56.314 + .WrA (`FALSE), 56.315 + .WrB (store_q_m & dram_select_m), 56.316 + // ----- Outputs ------- 56.317 + .QA (dram_data_out), 56.318 + .QB () 56.319 + ); 56.320 + 56.321 + /*---------------------------------------------------------------------- 56.322 + EBRs cannot perform reads from location 'written to' on the same clock 56.323 + edge. Therefore bypass logic is required to latch the store'd value 56.324 + and use it for the load (instead of value from memory). 56.325 + ----------------------------------------------------------------------*/ 56.326 + always @(posedge clk_i `CFG_RESET_SENSITIVITY) 56.327 + if (rst_i == `TRUE) 56.328 + begin 56.329 + dram_bypass_en <= `FALSE; 56.330 + dram_bypass_data <= 0; 56.331 + end 56.332 + else 56.333 + begin 56.334 + if (stall_x == `FALSE) 56.335 + dram_bypass_data <= dram_store_data_m; 56.336 + 56.337 + if ( (stall_m == `FALSE) 56.338 + && (stall_x == `FALSE) 56.339 + && (store_q_m == `TRUE) 56.340 + && ( (load_x == `TRUE) 56.341 + || (store_x == `TRUE) 56.342 + ) 56.343 + && (load_store_address_x[(`LM32_WORD_WIDTH-1):2] == load_store_address_m[(`LM32_WORD_WIDTH-1):2]) 56.344 + ) 56.345 + dram_bypass_en <= `TRUE; 56.346 + else 56.347 + if ( (dram_bypass_en == `TRUE) 56.348 + && (stall_x == `FALSE) 56.349 + ) 56.350 + dram_bypass_en <= `FALSE; 56.351 + end 56.352 + 56.353 + assign dram_data_m = dram_bypass_en ? dram_bypass_data : dram_data_out; 56.354 +`endif 56.355 + 56.356 +`ifdef CFG_DCACHE_ENABLED 56.357 +// Data cache 56.358 +lm32_dcache #( 56.359 + .associativity (associativity), 56.360 + .sets (sets), 56.361 + .bytes_per_line (bytes_per_line), 56.362 + .base_address (base_address), 56.363 + .limit (limit) 56.364 + ) dcache ( 56.365 + // ----- Inputs ----- 56.366 + .clk_i (clk_i), 56.367 + .rst_i (rst_i), 56.368 + .stall_a (stall_a), 56.369 + .stall_x (stall_x), 56.370 + .stall_m (stall_m), 56.371 + .address_x (load_store_address_x), 56.372 + .address_m (load_store_address_m), 56.373 + .load_q_m (load_q_m & dcache_select_m), 56.374 + .store_q_m (store_q_m & dcache_select_m), 56.375 + .store_data (store_data_m), 56.376 + .store_byte_select (byte_enable_m & {4{dcache_select_m}}), 56.377 + .refill_ready (dcache_refill_ready), 56.378 + .refill_data (wb_data_m), 56.379 + .dflush (dflush), 56.380 + // ----- Outputs ----- 56.381 + .stall_request (dcache_stall_request), 56.382 + .restart_request (dcache_restart_request), 56.383 + .refill_request (dcache_refill_request), 56.384 + .refill_address (dcache_refill_address), 56.385 + .refilling (dcache_refilling), 56.386 + .load_data (dcache_data_m) 56.387 + ); 56.388 +`endif 56.389 + 56.390 +///////////////////////////////////////////////////// 56.391 +// Combinational Logic 56.392 +///////////////////////////////////////////////////// 56.393 + 56.394 +// Select where data should be loaded from / stored to 56.395 +`ifdef CFG_DRAM_ENABLED 56.396 + assign dram_select_x = (load_store_address_x >= `CFG_DRAM_BASE_ADDRESS) 56.397 + && (load_store_address_x <= `CFG_DRAM_LIMIT); 56.398 +`endif 56.399 + 56.400 +`ifdef CFG_IROM_ENABLED 56.401 + assign irom_select_x = (load_store_address_x >= `CFG_IROM_BASE_ADDRESS) 56.402 + && (load_store_address_x <= `CFG_IROM_LIMIT); 56.403 +`endif 56.404 + 56.405 +`ifdef CFG_DCACHE_ENABLED 56.406 + assign dcache_select_x = (load_store_address_x >= `CFG_DCACHE_BASE_ADDRESS) 56.407 + && (load_store_address_x <= `CFG_DCACHE_LIMIT) 56.408 +`ifdef CFG_DRAM_ENABLED 56.409 + && (dram_select_x == `FALSE) 56.410 +`endif 56.411 +`ifdef CFG_IROM_ENABLED 56.412 + && (irom_select_x == `FALSE) 56.413 +`endif 56.414 + ; 56.415 +`endif 56.416 + 56.417 + assign wb_select_x = `TRUE 56.418 +`ifdef CFG_DCACHE_ENABLED 56.419 + && !dcache_select_x 56.420 +`endif 56.421 +`ifdef CFG_DRAM_ENABLED 56.422 + && !dram_select_x 56.423 +`endif 56.424 +`ifdef CFG_IROM_ENABLED 56.425 + && !irom_select_x 56.426 +`endif 56.427 + ; 56.428 + 56.429 +// Make sure data to store is in correct byte lane 56.430 +always @(*) 56.431 +begin 56.432 + case (size_x) 56.433 + `LM32_SIZE_BYTE: store_data_x = {4{store_operand_x[7:0]}}; 56.434 + `LM32_SIZE_HWORD: store_data_x = {2{store_operand_x[15:0]}}; 56.435 + `LM32_SIZE_WORD: store_data_x = store_operand_x; 56.436 + default: store_data_x = {`LM32_WORD_WIDTH{1'bx}}; 56.437 + endcase 56.438 +end 56.439 + 56.440 +// Generate byte enable accoring to size of load or store and address being accessed 56.441 +always @(*) 56.442 +begin 56.443 + casez ({size_x, load_store_address_x[1:0]}) 56.444 + {`LM32_SIZE_BYTE, 2'b11}: byte_enable_x = 4'b0001; 56.445 + {`LM32_SIZE_BYTE, 2'b10}: byte_enable_x = 4'b0010; 56.446 + {`LM32_SIZE_BYTE, 2'b01}: byte_enable_x = 4'b0100; 56.447 + {`LM32_SIZE_BYTE, 2'b00}: byte_enable_x = 4'b1000; 56.448 + {`LM32_SIZE_HWORD, 2'b1?}: byte_enable_x = 4'b0011; 56.449 + {`LM32_SIZE_HWORD, 2'b0?}: byte_enable_x = 4'b1100; 56.450 + {`LM32_SIZE_WORD, 2'b??}: byte_enable_x = 4'b1111; 56.451 + default: byte_enable_x = 4'bxxxx; 56.452 + endcase 56.453 +end 56.454 + 56.455 +`ifdef CFG_DRAM_ENABLED 56.456 +// Only replace selected bytes 56.457 +assign dram_store_data_m[`LM32_BYTE_0_RNG] = byte_enable_m[0] ? store_data_m[`LM32_BYTE_0_RNG] : dram_data_m[`LM32_BYTE_0_RNG]; 56.458 +assign dram_store_data_m[`LM32_BYTE_1_RNG] = byte_enable_m[1] ? store_data_m[`LM32_BYTE_1_RNG] : dram_data_m[`LM32_BYTE_1_RNG]; 56.459 +assign dram_store_data_m[`LM32_BYTE_2_RNG] = byte_enable_m[2] ? store_data_m[`LM32_BYTE_2_RNG] : dram_data_m[`LM32_BYTE_2_RNG]; 56.460 +assign dram_store_data_m[`LM32_BYTE_3_RNG] = byte_enable_m[3] ? store_data_m[`LM32_BYTE_3_RNG] : dram_data_m[`LM32_BYTE_3_RNG]; 56.461 +`endif 56.462 + 56.463 +`ifdef CFG_IROM_ENABLED 56.464 +// Only replace selected bytes 56.465 +assign irom_store_data_m[`LM32_BYTE_0_RNG] = byte_enable_m[0] ? store_data_m[`LM32_BYTE_0_RNG] : irom_data_m[`LM32_BYTE_0_RNG]; 56.466 +assign irom_store_data_m[`LM32_BYTE_1_RNG] = byte_enable_m[1] ? store_data_m[`LM32_BYTE_1_RNG] : irom_data_m[`LM32_BYTE_1_RNG]; 56.467 +assign irom_store_data_m[`LM32_BYTE_2_RNG] = byte_enable_m[2] ? store_data_m[`LM32_BYTE_2_RNG] : irom_data_m[`LM32_BYTE_2_RNG]; 56.468 +assign irom_store_data_m[`LM32_BYTE_3_RNG] = byte_enable_m[3] ? store_data_m[`LM32_BYTE_3_RNG] : irom_data_m[`LM32_BYTE_3_RNG]; 56.469 +`endif 56.470 + 56.471 +`ifdef CFG_IROM_ENABLED 56.472 + // Instead of implementing a byte-addressable instruction ROM (for store byte instruction), 56.473 + // a load-and-store architecture is used wherein a 32-bit value is loaded, the requisite 56.474 + // byte is replaced, and the whole 32-bit value is written back 56.475 + 56.476 + assign irom_address_xm = ((irom_select_m == `TRUE) && (store_q_m == `TRUE)) 56.477 + ? load_store_address_m 56.478 + : load_store_address_x; 56.479 + 56.480 + // All store instructions perform a write operation in the M stage 56.481 + assign irom_we_xm = (irom_select_m == `TRUE) 56.482 + && (store_q_m == `TRUE); 56.483 + 56.484 + // A single port in instruction ROM is available to load-store unit for doing loads/stores. 56.485 + // Since every store requires a load (in X stage) and then a store (in M stage), we cannot 56.486 + // allow load (or store) instructions sequentially after the store instructions to proceed 56.487 + // until the store instruction has vacated M stage (i.e., completed the store operation) 56.488 + assign irom_stall_request_x = (irom_select_x == `TRUE) 56.489 + && (store_q_x == `TRUE); 56.490 +`endif 56.491 + 56.492 +`ifdef CFG_DCACHE_ENABLED 56.493 + `ifdef CFG_DRAM_ENABLED 56.494 + `ifdef CFG_IROM_ENABLED 56.495 + // WB + DC + DRAM + IROM 56.496 + assign data_m = wb_select_m == `TRUE 56.497 + ? wb_data_m 56.498 + : dram_select_m == `TRUE 56.499 + ? dram_data_m 56.500 + : irom_select_m == `TRUE 56.501 + ? irom_data_m 56.502 + : dcache_data_m; 56.503 + `else 56.504 + // WB + DC + DRAM 56.505 + assign data_m = wb_select_m == `TRUE 56.506 + ? wb_data_m 56.507 + : dram_select_m == `TRUE 56.508 + ? dram_data_m 56.509 + : dcache_data_m; 56.510 + `endif 56.511 + `else 56.512 + `ifdef CFG_IROM_ENABLED 56.513 + // WB + DC + IROM 56.514 + assign data_m = wb_select_m == `TRUE 56.515 + ? wb_data_m 56.516 + : irom_select_m == `TRUE 56.517 + ? irom_data_m 56.518 + : dcache_data_m; 56.519 + `else 56.520 + // WB + DC 56.521 + assign data_m = wb_select_m == `TRUE 56.522 + ? wb_data_m 56.523 + : dcache_data_m; 56.524 + `endif 56.525 + `endif 56.526 +`else 56.527 + `ifdef CFG_DRAM_ENABLED 56.528 + `ifdef CFG_IROM_ENABLED 56.529 + // WB + DRAM + IROM 56.530 + assign data_m = wb_select_m == `TRUE 56.531 + ? wb_data_m 56.532 + : dram_select_m == `TRUE 56.533 + ? dram_data_m 56.534 + : irom_data_m; 56.535 + `else 56.536 + // WB + DRAM 56.537 + assign data_m = wb_select_m == `TRUE 56.538 + ? wb_data_m 56.539 + : dram_data_m; 56.540 + `endif 56.541 + `else 56.542 + `ifdef CFG_IROM_ENABLED 56.543 + // WB + IROM 56.544 + assign data_m = wb_select_m == `TRUE 56.545 + ? wb_data_m 56.546 + : irom_data_m; 56.547 + `else 56.548 + // WB 56.549 + assign data_m = wb_data_m; 56.550 + `endif 56.551 + `endif 56.552 +`endif 56.553 + 56.554 +// Sub-word selection and sign/zero-extension for loads 56.555 +always @(*) 56.556 +begin 56.557 + casez ({size_w, load_store_address_w[1:0]}) 56.558 + {`LM32_SIZE_BYTE, 2'b11}: load_data_w = {{24{sign_extend_w & data_w[7]}}, data_w[7:0]}; 56.559 + {`LM32_SIZE_BYTE, 2'b10}: load_data_w = {{24{sign_extend_w & data_w[15]}}, data_w[15:8]}; 56.560 + {`LM32_SIZE_BYTE, 2'b01}: load_data_w = {{24{sign_extend_w & data_w[23]}}, data_w[23:16]}; 56.561 + {`LM32_SIZE_BYTE, 2'b00}: load_data_w = {{24{sign_extend_w & data_w[31]}}, data_w[31:24]}; 56.562 + {`LM32_SIZE_HWORD, 2'b1?}: load_data_w = {{16{sign_extend_w & data_w[15]}}, data_w[15:0]}; 56.563 + {`LM32_SIZE_HWORD, 2'b0?}: load_data_w = {{16{sign_extend_w & data_w[31]}}, data_w[31:16]}; 56.564 + {`LM32_SIZE_WORD, 2'b??}: load_data_w = data_w; 56.565 + default: load_data_w = {`LM32_WORD_WIDTH{1'bx}}; 56.566 + endcase 56.567 +end 56.568 + 56.569 +// Unused/constant Wishbone signals 56.570 +assign d_bte_o = `LM32_BTYPE_LINEAR; 56.571 + 56.572 +`ifdef CFG_DCACHE_ENABLED 56.573 +// Generate signal to indicate last word in cache line 56.574 +generate 56.575 + case (bytes_per_line) 56.576 + 4: 56.577 + begin 56.578 +assign first_cycle_type = `LM32_CTYPE_END; 56.579 +assign next_cycle_type = `LM32_CTYPE_END; 56.580 +assign last_word = `TRUE; 56.581 +assign first_address = {dcache_refill_address[`LM32_WORD_WIDTH-1:2], 2'b00}; 56.582 + end 56.583 + 8: 56.584 + begin 56.585 +assign first_cycle_type = `LM32_CTYPE_INCREMENTING; 56.586 +assign next_cycle_type = `LM32_CTYPE_END; 56.587 +assign last_word = (&d_adr_o[addr_offset_msb:addr_offset_lsb]) == 1'b1; 56.588 +assign first_address = {dcache_refill_address[`LM32_WORD_WIDTH-1:addr_offset_msb+1], {addr_offset_width{1'b0}}, 2'b00}; 56.589 + end 56.590 + 16: 56.591 + begin 56.592 +assign first_cycle_type = `LM32_CTYPE_INCREMENTING; 56.593 +assign next_cycle_type = d_adr_o[addr_offset_msb] == 1'b1 ? `LM32_CTYPE_END : `LM32_CTYPE_INCREMENTING; 56.594 +assign last_word = (&d_adr_o[addr_offset_msb:addr_offset_lsb]) == 1'b1; 56.595 +assign first_address = {dcache_refill_address[`LM32_WORD_WIDTH-1:addr_offset_msb+1], {addr_offset_width{1'b0}}, 2'b00}; 56.596 + end 56.597 + endcase 56.598 +endgenerate 56.599 +`endif 56.600 + 56.601 +///////////////////////////////////////////////////// 56.602 +// Sequential Logic 56.603 +///////////////////////////////////////////////////// 56.604 + 56.605 +// Data Wishbone interface 56.606 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 56.607 +begin 56.608 + if (rst_i == `TRUE) 56.609 + begin 56.610 + d_cyc_o <= `FALSE; 56.611 + d_stb_o <= `FALSE; 56.612 + d_dat_o <= {`LM32_WORD_WIDTH{1'b0}}; 56.613 + d_adr_o <= {`LM32_WORD_WIDTH{1'b0}}; 56.614 + d_sel_o <= {`LM32_BYTE_SELECT_WIDTH{`FALSE}}; 56.615 + d_we_o <= `FALSE; 56.616 + d_cti_o <= `LM32_CTYPE_END; 56.617 + d_lock_o <= `FALSE; 56.618 + wb_data_m <= {`LM32_WORD_WIDTH{1'b0}}; 56.619 + wb_load_complete <= `FALSE; 56.620 + stall_wb_load <= `FALSE; 56.621 +`ifdef CFG_DCACHE_ENABLED 56.622 + dcache_refill_ready <= `FALSE; 56.623 +`endif 56.624 + end 56.625 + else 56.626 + begin 56.627 +`ifdef CFG_DCACHE_ENABLED 56.628 + // Refill ready should only be asserted for a single cycle 56.629 + dcache_refill_ready <= `FALSE; 56.630 +`endif 56.631 + // Is a Wishbone cycle already in progress? 56.632 + if (d_cyc_o == `TRUE) 56.633 + begin 56.634 + // Is the cycle complete? 56.635 + if ((d_ack_i == `TRUE) || (d_err_i == `TRUE)) 56.636 + begin 56.637 +`ifdef CFG_DCACHE_ENABLED 56.638 + if ((dcache_refilling == `TRUE) && (!last_word)) 56.639 + begin 56.640 + // Fetch next word of cache line 56.641 + d_adr_o[addr_offset_msb:addr_offset_lsb] <= d_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1; 56.642 + end 56.643 + else 56.644 +`endif 56.645 + begin 56.646 + // Refill/access complete 56.647 + d_cyc_o <= `FALSE; 56.648 + d_stb_o <= `FALSE; 56.649 + d_lock_o <= `FALSE; 56.650 + end 56.651 +`ifdef CFG_DCACHE_ENABLED 56.652 + d_cti_o <= next_cycle_type; 56.653 + // If we are performing a refill, indicate to cache next word of data is ready 56.654 + dcache_refill_ready <= dcache_refilling; 56.655 +`endif 56.656 + // Register data read from Wishbone interface 56.657 + wb_data_m <= d_dat_i; 56.658 + // Don't set when stores complete - otherwise we'll deadlock if load in m stage 56.659 + wb_load_complete <= !d_we_o; 56.660 + end 56.661 + // synthesis translate_off 56.662 + if (d_err_i == `TRUE) 56.663 + $display ("Data bus error. Address: %x", d_adr_o); 56.664 + // synthesis translate_on 56.665 + end 56.666 + else 56.667 + begin 56.668 +`ifdef CFG_DCACHE_ENABLED 56.669 + if (dcache_refill_request == `TRUE) 56.670 + begin 56.671 + // Start cache refill 56.672 + d_adr_o <= first_address; 56.673 + d_cyc_o <= `TRUE; 56.674 + d_sel_o <= {`LM32_WORD_WIDTH/8{`TRUE}}; 56.675 + d_stb_o <= `TRUE; 56.676 + d_we_o <= `FALSE; 56.677 + d_cti_o <= first_cycle_type; 56.678 + //d_lock_o <= `TRUE; 56.679 + end 56.680 + else 56.681 +`endif 56.682 + if ( (store_q_m == `TRUE) 56.683 + && (stall_m == `FALSE) 56.684 +`ifdef CFG_DRAM_ENABLED 56.685 + && (dram_select_m == `FALSE) 56.686 +`endif 56.687 +`ifdef CFG_IROM_ENABLED 56.688 + && (irom_select_m == `FALSE) 56.689 +`endif 56.690 + ) 56.691 + begin 56.692 + // Data cache is write through, so all stores go to memory 56.693 + d_dat_o <= store_data_m; 56.694 + d_adr_o <= load_store_address_m; 56.695 + d_cyc_o <= `TRUE; 56.696 + d_sel_o <= byte_enable_m; 56.697 + d_stb_o <= `TRUE; 56.698 + d_we_o <= `TRUE; 56.699 + d_cti_o <= `LM32_CTYPE_END; 56.700 + end 56.701 + else if ( (load_q_m == `TRUE) 56.702 + && (wb_select_m == `TRUE) 56.703 + && (wb_load_complete == `FALSE) 56.704 + // stall_m will be TRUE, because stall_wb_load will be TRUE 56.705 + ) 56.706 + begin 56.707 + // Read requested address 56.708 + stall_wb_load <= `FALSE; 56.709 + d_adr_o <= load_store_address_m; 56.710 + d_cyc_o <= `TRUE; 56.711 + d_sel_o <= byte_enable_m; 56.712 + d_stb_o <= `TRUE; 56.713 + d_we_o <= `FALSE; 56.714 + d_cti_o <= `LM32_CTYPE_END; 56.715 + end 56.716 + end 56.717 + // Clear load/store complete flag when instruction leaves M stage 56.718 + if (stall_m == `FALSE) 56.719 + wb_load_complete <= `FALSE; 56.720 + // When a Wishbone load first enters the M stage, we need to stall it 56.721 + if ((load_q_x == `TRUE) && (wb_select_x == `TRUE) && (stall_x == `FALSE)) 56.722 + stall_wb_load <= `TRUE; 56.723 + // Clear stall request if load instruction is killed 56.724 + if ((kill_m == `TRUE) || (exception_m == `TRUE)) 56.725 + stall_wb_load <= `FALSE; 56.726 + end 56.727 +end 56.728 + 56.729 +// Pipeline registers 56.730 + 56.731 +// X/M stage pipeline registers 56.732 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 56.733 +begin 56.734 + if (rst_i == `TRUE) 56.735 + begin 56.736 + sign_extend_m <= `FALSE; 56.737 + size_m <= 2'b00; 56.738 + byte_enable_m <= `FALSE; 56.739 + store_data_m <= {`LM32_WORD_WIDTH{1'b0}}; 56.740 +`ifdef CFG_DCACHE_ENABLED 56.741 + dcache_select_m <= `FALSE; 56.742 +`endif 56.743 +`ifdef CFG_DRAM_ENABLED 56.744 + dram_select_m <= `FALSE; 56.745 +`endif 56.746 +`ifdef CFG_IROM_ENABLED 56.747 + irom_select_m <= `FALSE; 56.748 +`endif 56.749 + wb_select_m <= `FALSE; 56.750 + end 56.751 + else 56.752 + begin 56.753 + if (stall_m == `FALSE) 56.754 + begin 56.755 + sign_extend_m <= sign_extend_x; 56.756 + size_m <= size_x; 56.757 + byte_enable_m <= byte_enable_x; 56.758 + store_data_m <= store_data_x; 56.759 +`ifdef CFG_DCACHE_ENABLED 56.760 + dcache_select_m <= dcache_select_x; 56.761 +`endif 56.762 +`ifdef CFG_DRAM_ENABLED 56.763 + dram_select_m <= dram_select_x; 56.764 +`endif 56.765 +`ifdef CFG_IROM_ENABLED 56.766 + irom_select_m <= irom_select_x; 56.767 +`endif 56.768 + wb_select_m <= wb_select_x; 56.769 + end 56.770 + end 56.771 +end 56.772 + 56.773 +// M/W stage pipeline registers 56.774 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 56.775 +begin 56.776 + if (rst_i == `TRUE) 56.777 + begin 56.778 + size_w <= 2'b00; 56.779 + data_w <= {`LM32_WORD_WIDTH{1'b0}}; 56.780 + sign_extend_w <= `FALSE; 56.781 + end 56.782 + else 56.783 + begin 56.784 + size_w <= size_m; 56.785 + data_w <= data_m; 56.786 + sign_extend_w <= sign_extend_m; 56.787 + end 56.788 +end 56.789 + 56.790 +///////////////////////////////////////////////////// 56.791 +// Behavioural Logic 56.792 +///////////////////////////////////////////////////// 56.793 + 56.794 +// synthesis translate_off 56.795 + 56.796 +// Check for non-aligned loads or stores 56.797 +always @(posedge clk_i) 56.798 +begin 56.799 + if (((load_q_m == `TRUE) || (store_q_m == `TRUE)) && (stall_m == `FALSE)) 56.800 + begin 56.801 + if ((size_m === `LM32_SIZE_HWORD) && (load_store_address_m[0] !== 1'b0)) 56.802 + $display ("Warning: Non-aligned halfword access. Address: 0x%0x Time: %0t.", load_store_address_m, $time); 56.803 + if ((size_m === `LM32_SIZE_WORD) && (load_store_address_m[1:0] !== 2'b00)) 56.804 + $display ("Warning: Non-aligned word access. Address: 0x%0x Time: %0t.", load_store_address_m, $time); 56.805 + end 56.806 +end 56.807 + 56.808 +// synthesis translate_on 56.809 + 56.810 +endmodule
57.1 diff -r 252df75c8f67 -r c336e674a37e rtl/lm32_logic_op.v 57.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 57.3 +++ b/rtl/lm32_logic_op.v Tue Mar 08 09:40:42 2011 +0000 57.4 @@ -0,0 +1,76 @@ 57.5 +// ============================================================================= 57.6 +// COPYRIGHT NOTICE 57.7 +// Copyright 2006 (c) Lattice Semiconductor Corporation 57.8 +// ALL RIGHTS RESERVED 57.9 +// This confidential and proprietary software may be used only as authorised by 57.10 +// a licensing agreement from Lattice Semiconductor Corporation. 57.11 +// The entire notice above must be reproduced on all authorized copies and 57.12 +// copies may only be made to the extent permitted by a licensing agreement from 57.13 +// Lattice Semiconductor Corporation. 57.14 +// 57.15 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 57.16 +// 5555 NE Moore Court 408-826-6000 (other locations) 57.17 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 57.18 +// U.S.A email: techsupport@latticesemi.com 57.19 +// =============================================================================/ 57.20 +// FILE DETAILS 57.21 +// Project : LatticeMico32 57.22 +// File : lm32_logic_op.v 57.23 +// Title : Logic operations (and / or / not etc) 57.24 +// Dependencies : lm32_include.v 57.25 +// Version : 6.1.17 57.26 +// : Initial Release 57.27 +// Version : 7.0SP2, 3.0 57.28 +// : No Change 57.29 +// Version : 3.1 57.30 +// : No Change 57.31 +// ============================================================================= 57.32 + 57.33 +`include "lm32_include.v" 57.34 + 57.35 +///////////////////////////////////////////////////// 57.36 +// Module interface 57.37 +///////////////////////////////////////////////////// 57.38 + 57.39 +module lm32_logic_op ( 57.40 + // ----- Inputs ------- 57.41 + logic_op_x, 57.42 + operand_0_x, 57.43 + operand_1_x, 57.44 + // ----- Outputs ------- 57.45 + logic_result_x 57.46 + ); 57.47 + 57.48 +///////////////////////////////////////////////////// 57.49 +// Inputs 57.50 +///////////////////////////////////////////////////// 57.51 + 57.52 +input [`LM32_LOGIC_OP_RNG] logic_op_x; 57.53 +input [`LM32_WORD_RNG] operand_0_x; 57.54 +input [`LM32_WORD_RNG] operand_1_x; 57.55 + 57.56 +///////////////////////////////////////////////////// 57.57 +// Outputs 57.58 +///////////////////////////////////////////////////// 57.59 + 57.60 +output [`LM32_WORD_RNG] logic_result_x; 57.61 +reg [`LM32_WORD_RNG] logic_result_x; 57.62 + 57.63 +///////////////////////////////////////////////////// 57.64 +// Internal nets and registers 57.65 +///////////////////////////////////////////////////// 57.66 + 57.67 +integer logic_idx; 57.68 + 57.69 +///////////////////////////////////////////////////// 57.70 +// Combinational Logic 57.71 +///////////////////////////////////////////////////// 57.72 + 57.73 +always @(*) 57.74 +begin 57.75 + for(logic_idx = 0; logic_idx < `LM32_WORD_WIDTH; logic_idx = logic_idx + 1) 57.76 + logic_result_x[logic_idx] = logic_op_x[{operand_1_x[logic_idx], operand_0_x[logic_idx]}]; 57.77 +end 57.78 + 57.79 +endmodule 57.80 +
58.1 diff -r 252df75c8f67 -r c336e674a37e rtl/lm32_mc_arithmetic.v 58.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 58.3 +++ b/rtl/lm32_mc_arithmetic.v Tue Mar 08 09:40:42 2011 +0000 58.4 @@ -0,0 +1,288 @@ 58.5 +// ============================================================================= 58.6 +// COPYRIGHT NOTICE 58.7 +// Copyright 2006 (c) Lattice Semiconductor Corporation 58.8 +// ALL RIGHTS RESERVED 58.9 +// This confidential and proprietary software may be used only as authorised by 58.10 +// a licensing agreement from Lattice Semiconductor Corporation. 58.11 +// The entire notice above must be reproduced on all authorized copies and 58.12 +// copies may only be made to the extent permitted by a licensing agreement from 58.13 +// Lattice Semiconductor Corporation. 58.14 +// 58.15 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 58.16 +// 5555 NE Moore Court 408-826-6000 (other locations) 58.17 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 58.18 +// U.S.A email: techsupport@latticesemi.com 58.19 +// =============================================================================/ 58.20 +// FILE DETAILS 58.21 +// Project : LatticeMico32 58.22 +// File : lm_mc_arithmetic.v 58.23 +// Title : Multi-cycle arithmetic unit. 58.24 +// Dependencies : lm32_include.v 58.25 +// Version : 6.1.17 58.26 +// : Initial Release 58.27 +// Version : 7.0SP2, 3.0 58.28 +// : No Change 58.29 +// Version : 3.1 58.30 +// : No Change 58.31 +// ============================================================================= 58.32 + 58.33 +`include "lm32_include.v" 58.34 + 58.35 +`define LM32_MC_STATE_RNG 2:0 58.36 +`define LM32_MC_STATE_IDLE 3'b000 58.37 +`define LM32_MC_STATE_MULTIPLY 3'b001 58.38 +`define LM32_MC_STATE_MODULUS 3'b010 58.39 +`define LM32_MC_STATE_DIVIDE 3'b011 58.40 +`define LM32_MC_STATE_SHIFT_LEFT 3'b100 58.41 +`define LM32_MC_STATE_SHIFT_RIGHT 3'b101 58.42 + 58.43 +///////////////////////////////////////////////////// 58.44 +// Module interface 58.45 +///////////////////////////////////////////////////// 58.46 + 58.47 +module lm32_mc_arithmetic ( 58.48 + // ----- Inputs ----- 58.49 + clk_i, 58.50 + rst_i, 58.51 + stall_d, 58.52 + kill_x, 58.53 +`ifdef CFG_MC_DIVIDE_ENABLED 58.54 + divide_d, 58.55 + modulus_d, 58.56 +`endif 58.57 +`ifdef CFG_MC_MULTIPLY_ENABLED 58.58 + multiply_d, 58.59 +`endif 58.60 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED 58.61 + shift_left_d, 58.62 + shift_right_d, 58.63 + sign_extend_d, 58.64 +`endif 58.65 + operand_0_d, 58.66 + operand_1_d, 58.67 + // ----- Ouputs ----- 58.68 + result_x, 58.69 +`ifdef CFG_MC_DIVIDE_ENABLED 58.70 + divide_by_zero_x, 58.71 +`endif 58.72 + stall_request_x 58.73 + ); 58.74 + 58.75 +///////////////////////////////////////////////////// 58.76 +// Inputs 58.77 +///////////////////////////////////////////////////// 58.78 + 58.79 +input clk_i; // Clock 58.80 +input rst_i; // Reset 58.81 +input stall_d; // Stall instruction in D stage 58.82 +input kill_x; // Kill instruction in X stage 58.83 +`ifdef CFG_MC_DIVIDE_ENABLED 58.84 +input divide_d; // Perform divide 58.85 +input modulus_d; // Perform modulus 58.86 +`endif 58.87 +`ifdef CFG_MC_MULTIPLY_ENABLED 58.88 +input multiply_d; // Perform multiply 58.89 +`endif 58.90 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED 58.91 +input shift_left_d; // Perform left shift 58.92 +input shift_right_d; // Perform right shift 58.93 +input sign_extend_d; // Whether to sign-extend (arithmetic) or zero-extend (logical) 58.94 +`endif 58.95 +input [`LM32_WORD_RNG] operand_0_d; 58.96 +input [`LM32_WORD_RNG] operand_1_d; 58.97 + 58.98 +///////////////////////////////////////////////////// 58.99 +// Outputs 58.100 +///////////////////////////////////////////////////// 58.101 + 58.102 +output [`LM32_WORD_RNG] result_x; // Result of operation 58.103 +reg [`LM32_WORD_RNG] result_x; 58.104 +`ifdef CFG_MC_DIVIDE_ENABLED 58.105 +output divide_by_zero_x; // A divide by zero was attempted 58.106 +reg divide_by_zero_x; 58.107 +`endif 58.108 +output stall_request_x; // Request to stall pipeline from X stage back 58.109 +wire stall_request_x; 58.110 + 58.111 +///////////////////////////////////////////////////// 58.112 +// Internal nets and registers 58.113 +///////////////////////////////////////////////////// 58.114 + 58.115 +reg [`LM32_WORD_RNG] p; // Temporary registers 58.116 +reg [`LM32_WORD_RNG] a; 58.117 +reg [`LM32_WORD_RNG] b; 58.118 +`ifdef CFG_MC_DIVIDE_ENABLED 58.119 +wire [32:0] t; 58.120 +`endif 58.121 + 58.122 +reg [`LM32_MC_STATE_RNG] state; // Current state of FSM 58.123 +reg [5:0] cycles; // Number of cycles remaining in the operation 58.124 + 58.125 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED 58.126 +reg sign_extend_x; // Whether to sign extend of zero extend right shifts 58.127 +wire fill_value; // Value to fill with for right barrel-shifts 58.128 +`endif 58.129 + 58.130 +///////////////////////////////////////////////////// 58.131 +// Combinational logic 58.132 +///////////////////////////////////////////////////// 58.133 + 58.134 +// Stall pipeline while any operation is being performed 58.135 +assign stall_request_x = state != `LM32_MC_STATE_IDLE; 58.136 + 58.137 +`ifdef CFG_MC_DIVIDE_ENABLED 58.138 +// Subtraction 58.139 +assign t = {p[`LM32_WORD_WIDTH-2:0], a[`LM32_WORD_WIDTH-1]} - b; 58.140 +`endif 58.141 + 58.142 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED 58.143 +// Determine fill value for right shift - Sign bit for arithmetic shift, or zero for logical shift 58.144 +assign fill_value = (sign_extend_x == `TRUE) & b[`LM32_WORD_WIDTH-1]; 58.145 +`endif 58.146 + 58.147 +///////////////////////////////////////////////////// 58.148 +// Sequential logic 58.149 +///////////////////////////////////////////////////// 58.150 + 58.151 +// Perform right shift 58.152 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 58.153 +begin 58.154 + if (rst_i == `TRUE) 58.155 + begin 58.156 + cycles <= {6{1'b0}}; 58.157 + p <= {`LM32_WORD_WIDTH{1'b0}}; 58.158 + a <= {`LM32_WORD_WIDTH{1'b0}}; 58.159 + b <= {`LM32_WORD_WIDTH{1'b0}}; 58.160 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED 58.161 + sign_extend_x <= 1'b0; 58.162 +`endif 58.163 +`ifdef CFG_MC_DIVIDE_ENABLED 58.164 + divide_by_zero_x <= `FALSE; 58.165 +`endif 58.166 + result_x <= {`LM32_WORD_WIDTH{1'b0}}; 58.167 + state <= `LM32_MC_STATE_IDLE; 58.168 + end 58.169 + else 58.170 + begin 58.171 +`ifdef CFG_MC_DIVIDE_ENABLED 58.172 + divide_by_zero_x <= `FALSE; 58.173 +`endif 58.174 + case (state) 58.175 + `LM32_MC_STATE_IDLE: 58.176 + begin 58.177 + if (stall_d == `FALSE) 58.178 + begin 58.179 + cycles <= `LM32_WORD_WIDTH; 58.180 + p <= 32'b0; 58.181 + a <= operand_0_d; 58.182 + b <= operand_1_d; 58.183 +`ifdef CFG_MC_DIVIDE_ENABLED 58.184 + if (divide_d == `TRUE) 58.185 + state <= `LM32_MC_STATE_DIVIDE; 58.186 + if (modulus_d == `TRUE) 58.187 + state <= `LM32_MC_STATE_MODULUS; 58.188 +`endif 58.189 +`ifdef CFG_MC_MULTIPLY_ENABLED 58.190 + if (multiply_d == `TRUE) 58.191 + state <= `LM32_MC_STATE_MULTIPLY; 58.192 +`endif 58.193 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED 58.194 + if (shift_left_d == `TRUE) 58.195 + begin 58.196 + state <= `LM32_MC_STATE_SHIFT_LEFT; 58.197 + sign_extend_x <= sign_extend_d; 58.198 + cycles <= operand_1_d[4:0]; 58.199 + a <= operand_0_d; 58.200 + b <= operand_0_d; 58.201 + end 58.202 + if (shift_right_d == `TRUE) 58.203 + begin 58.204 + state <= `LM32_MC_STATE_SHIFT_RIGHT; 58.205 + sign_extend_x <= sign_extend_d; 58.206 + cycles <= operand_1_d[4:0]; 58.207 + a <= operand_0_d; 58.208 + b <= operand_0_d; 58.209 + end 58.210 +`endif 58.211 + end 58.212 + end 58.213 +`ifdef CFG_MC_DIVIDE_ENABLED 58.214 + `LM32_MC_STATE_DIVIDE: 58.215 + begin 58.216 + if (t[32] == 1'b0) 58.217 + begin 58.218 + p <= t[31:0]; 58.219 + a <= {a[`LM32_WORD_WIDTH-2:0], 1'b1}; 58.220 + end 58.221 + else 58.222 + begin 58.223 + p <= {p[`LM32_WORD_WIDTH-2:0], a[`LM32_WORD_WIDTH-1]}; 58.224 + a <= {a[`LM32_WORD_WIDTH-2:0], 1'b0}; 58.225 + end 58.226 + result_x <= a; 58.227 + if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE)) 58.228 + begin 58.229 + // Check for divide by zero 58.230 + divide_by_zero_x <= b == {`LM32_WORD_WIDTH{1'b0}}; 58.231 + state <= `LM32_MC_STATE_IDLE; 58.232 + end 58.233 + cycles <= cycles - 1'b1; 58.234 + end 58.235 + `LM32_MC_STATE_MODULUS: 58.236 + begin 58.237 + if (t[32] == 1'b0) 58.238 + begin 58.239 + p <= t[31:0]; 58.240 + a <= {a[`LM32_WORD_WIDTH-2:0], 1'b1}; 58.241 + end 58.242 + else 58.243 + begin 58.244 + p <= {p[`LM32_WORD_WIDTH-2:0], a[`LM32_WORD_WIDTH-1]}; 58.245 + a <= {a[`LM32_WORD_WIDTH-2:0], 1'b0}; 58.246 + end 58.247 + result_x <= p; 58.248 + if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE)) 58.249 + begin 58.250 + // Check for divide by zero 58.251 + divide_by_zero_x <= b == {`LM32_WORD_WIDTH{1'b0}}; 58.252 + state <= `LM32_MC_STATE_IDLE; 58.253 + end 58.254 + cycles <= cycles - 1'b1; 58.255 + end 58.256 +`endif 58.257 +`ifdef CFG_MC_MULTIPLY_ENABLED 58.258 + `LM32_MC_STATE_MULTIPLY: 58.259 + begin 58.260 + if (b[0] == 1'b1) 58.261 + p <= p + a; 58.262 + b <= {1'b0, b[`LM32_WORD_WIDTH-1:1]}; 58.263 + a <= {a[`LM32_WORD_WIDTH-2:0], 1'b0}; 58.264 + result_x <= p; 58.265 + if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE)) 58.266 + state <= `LM32_MC_STATE_IDLE; 58.267 + cycles <= cycles - 1'b1; 58.268 + end 58.269 +`endif 58.270 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED 58.271 + `LM32_MC_STATE_SHIFT_LEFT: 58.272 + begin 58.273 + a <= {a[`LM32_WORD_WIDTH-2:0], 1'b0}; 58.274 + result_x <= a; 58.275 + if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE)) 58.276 + state <= `LM32_MC_STATE_IDLE; 58.277 + cycles <= cycles - 1'b1; 58.278 + end 58.279 + `LM32_MC_STATE_SHIFT_RIGHT: 58.280 + begin 58.281 + b <= {fill_value, b[`LM32_WORD_WIDTH-1:1]}; 58.282 + result_x <= b; 58.283 + if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE)) 58.284 + state <= `LM32_MC_STATE_IDLE; 58.285 + cycles <= cycles - 1'b1; 58.286 + end 58.287 +`endif 58.288 + endcase 58.289 + end 58.290 +end 58.291 + 58.292 +endmodule
59.1 diff -r 252df75c8f67 -r c336e674a37e rtl/lm32_multiplier.v 59.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 59.3 +++ b/rtl/lm32_multiplier.v Tue Mar 08 09:40:42 2011 +0000 59.4 @@ -0,0 +1,99 @@ 59.5 +// ============================================================================= 59.6 +// COPYRIGHT NOTICE 59.7 +// Copyright 2006 (c) Lattice Semiconductor Corporation 59.8 +// ALL RIGHTS RESERVED 59.9 +// This confidential and proprietary software may be used only as authorised by 59.10 +// a licensing agreement from Lattice Semiconductor Corporation. 59.11 +// The entire notice above must be reproduced on all authorized copies and 59.12 +// copies may only be made to the extent permitted by a licensing agreement from 59.13 +// Lattice Semiconductor Corporation. 59.14 +// 59.15 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 59.16 +// 5555 NE Moore Court 408-826-6000 (other locations) 59.17 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 59.18 +// U.S.A email: techsupport@latticesemi.com 59.19 +// =============================================================================/ 59.20 +// FILE DETAILS 59.21 +// Project : LatticeMico32 59.22 +// File : lm32_multiplier.v 59.23 +// Title : Pipelined multiplier. 59.24 +// Dependencies : lm32_include.v 59.25 +// Version : 6.1.17 59.26 +// : Initial Release 59.27 +// Version : 7.0SP2, 3.0 59.28 +// : No Change 59.29 +// Version : 3.1 59.30 +// : No Change 59.31 +// ============================================================================= 59.32 + 59.33 +`include "lm32_include.v" 59.34 + 59.35 +///////////////////////////////////////////////////// 59.36 +// Module interface 59.37 +///////////////////////////////////////////////////// 59.38 + 59.39 +module lm32_multiplier ( 59.40 + // ----- Inputs ----- 59.41 + clk_i, 59.42 + rst_i, 59.43 + stall_x, 59.44 + stall_m, 59.45 + operand_0, 59.46 + operand_1, 59.47 + // ----- Ouputs ----- 59.48 + result 59.49 + ); 59.50 + 59.51 +///////////////////////////////////////////////////// 59.52 +// Inputs 59.53 +///////////////////////////////////////////////////// 59.54 + 59.55 +input clk_i; // Clock 59.56 +input rst_i; // Reset 59.57 +input stall_x; // Stall instruction in X stage 59.58 +input stall_m; // Stall instruction in M stage 59.59 +input [`LM32_WORD_RNG] operand_0; // Muliplicand 59.60 +input [`LM32_WORD_RNG] operand_1; // Multiplier 59.61 + 59.62 +///////////////////////////////////////////////////// 59.63 +// Outputs 59.64 +///////////////////////////////////////////////////// 59.65 + 59.66 +output [`LM32_WORD_RNG] result; // Product of multiplication 59.67 +reg [`LM32_WORD_RNG] result; 59.68 + 59.69 +///////////////////////////////////////////////////// 59.70 +// Internal nets and registers 59.71 +///////////////////////////////////////////////////// 59.72 + 59.73 +reg [`LM32_WORD_RNG] muliplicand; 59.74 +reg [`LM32_WORD_RNG] multiplier; 59.75 +reg [`LM32_WORD_RNG] product; 59.76 + 59.77 +///////////////////////////////////////////////////// 59.78 +// Sequential logic 59.79 +///////////////////////////////////////////////////// 59.80 + 59.81 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 59.82 +begin 59.83 + if (rst_i == `TRUE) 59.84 + begin 59.85 + muliplicand <= {`LM32_WORD_WIDTH{1'b0}}; 59.86 + multiplier <= {`LM32_WORD_WIDTH{1'b0}}; 59.87 + product <= {`LM32_WORD_WIDTH{1'b0}}; 59.88 + result <= {`LM32_WORD_WIDTH{1'b0}}; 59.89 + end 59.90 + else 59.91 + begin 59.92 + if (stall_x == `FALSE) 59.93 + begin 59.94 + muliplicand <= operand_0; 59.95 + multiplier <= operand_1; 59.96 + end 59.97 + if (stall_m == `FALSE) 59.98 + product <= muliplicand * multiplier; 59.99 + result <= product; 59.100 + end 59.101 +end 59.102 + 59.103 +endmodule
60.1 diff -r 252df75c8f67 -r c336e674a37e rtl/lm32_ram.v 60.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 60.3 +++ b/rtl/lm32_ram.v Tue Mar 08 09:40:42 2011 +0000 60.4 @@ -0,0 +1,294 @@ 60.5 +// ============================================================================= 60.6 +// COPYRIGHT NOTICE 60.7 +// Copyright 2006 (c) Lattice Semiconductor Corporation 60.8 +// ALL RIGHTS RESERVED 60.9 +// This confidential and proprietary software may be used only as authorised by 60.10 +// a licensing agreement from Lattice Semiconductor Corporation. 60.11 +// The entire notice above must be reproduced on all authorized copies and 60.12 +// copies may only be made to the extent permitted by a licensing agreement from 60.13 +// Lattice Semiconductor Corporation. 60.14 +// 60.15 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 60.16 +// 5555 NE Moore Court 408-826-6000 (other locations) 60.17 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 60.18 +// U.S.A email: techsupport@latticesemi.com 60.19 +// =============================================================================/ 60.20 +// FILE DETAILS 60.21 +// Project : LatticeMico32 60.22 +// File : lm32_ram.v 60.23 +// Title : Pseudo dual-port RAM. 60.24 +// Version : 6.1.17 60.25 +// : Initial Release 60.26 +// Version : 7.0SP2, 3.0 60.27 +// : No Change 60.28 +// Version : 3.1 60.29 +// : Options added to select EBRs (True-DP, Psuedo-DP, DQ, or 60.30 +// : Distributed RAM). 60.31 +// Version : 3.2 60.32 +// : EBRs use SYNC resets instead of ASYNC resets. 60.33 +// Version : 3.5 60.34 +// : Added read-after-write hazard resolution when using true 60.35 +// : dual-port EBRs 60.36 +// ============================================================================= 60.37 + 60.38 +`include "lm32_include.v" 60.39 + 60.40 +///////////////////////////////////////////////////// 60.41 +// Module interface 60.42 +///////////////////////////////////////////////////// 60.43 + 60.44 +module lm32_ram 60.45 + ( 60.46 + // ----- Inputs ------- 60.47 + read_clk, 60.48 + write_clk, 60.49 + reset, 60.50 + enable_read, 60.51 + read_address, 60.52 + enable_write, 60.53 + write_address, 60.54 + write_data, 60.55 + write_enable, 60.56 + // ----- Outputs ------- 60.57 + read_data 60.58 + ); 60.59 + 60.60 + /*---------------------------------------------------------------------- 60.61 + Parameters 60.62 + ----------------------------------------------------------------------*/ 60.63 + parameter data_width = 1; // Width of the data ports 60.64 + parameter address_width = 1; // Width of the address ports 60.65 +`ifdef PLATFORM_LATTICE 60.66 + parameter RAM_IMPLEMENTATION = "AUTO"; // Implement memory in EBRs, else 60.67 + // let synthesis tool select best 60.68 + // possible solution (EBR or LUT) 60.69 + parameter RAM_TYPE = "RAM_DP"; // Type of EBR to be used 60.70 +`endif 60.71 + 60.72 + /*---------------------------------------------------------------------- 60.73 + Inputs 60.74 + ----------------------------------------------------------------------*/ 60.75 + input read_clk; // Read clock 60.76 + input write_clk; // Write clock 60.77 + input reset; // Reset 60.78 + 60.79 + input enable_read; // Access enable 60.80 + input [address_width-1:0] read_address; // Read/write address 60.81 + input enable_write; // Access enable 60.82 + input [address_width-1:0] write_address;// Read/write address 60.83 + input [data_width-1:0] write_data; // Data to write to specified address 60.84 + input write_enable; // Write enable 60.85 + 60.86 + /*---------------------------------------------------------------------- 60.87 + Outputs 60.88 + ----------------------------------------------------------------------*/ 60.89 + output [data_width-1:0] read_data; // Data read from specified addess 60.90 + wire [data_width-1:0] read_data; 60.91 + 60.92 +`ifdef PLATFORM_LATTICE 60.93 + generate 60.94 + 60.95 + if ( RAM_IMPLEMENTATION == "EBR" ) 60.96 + begin 60.97 + if ( RAM_TYPE == "RAM_DP" ) 60.98 + begin 60.99 + pmi_ram_dp 60.100 + #( 60.101 + // ----- Parameters ----- 60.102 + .pmi_wr_addr_depth(1<<address_width), 60.103 + .pmi_wr_addr_width(address_width), 60.104 + .pmi_wr_data_width(data_width), 60.105 + .pmi_rd_addr_depth(1<<address_width), 60.106 + .pmi_rd_addr_width(address_width), 60.107 + .pmi_rd_data_width(data_width), 60.108 + .pmi_regmode("noreg"), 60.109 + .pmi_gsr("enable"), 60.110 + .pmi_resetmode("sync"), 60.111 + .pmi_init_file("none"), 60.112 + .pmi_init_file_format("binary"), 60.113 + .pmi_family(`LATTICE_FAMILY), 60.114 + .module_type("pmi_ram_dp") 60.115 + ) 60.116 + lm32_ram_inst 60.117 + ( 60.118 + // ----- Inputs ----- 60.119 + .Data(write_data), 60.120 + .WrAddress(write_address), 60.121 + .RdAddress(read_address), 60.122 + .WrClock(write_clk), 60.123 + .RdClock(read_clk), 60.124 + .WrClockEn(enable_write), 60.125 + .RdClockEn(enable_read), 60.126 + .WE(write_enable), 60.127 + .Reset(reset), 60.128 + // ----- Outputs ----- 60.129 + .Q(read_data) 60.130 + ); 60.131 + end 60.132 + else 60.133 + begin 60.134 + // True Dual-Port EBR 60.135 + wire [data_width-1:0] read_data_A, read_data_B; 60.136 + reg [data_width-1:0] raw_data, raw_data_nxt; 60.137 + reg raw, raw_nxt; 60.138 + 60.139 + /*---------------------------------------------------------------------- 60.140 + Is a read being performed in the same cycle as a write? Indicate this 60.141 + event with a RAW hazard signal that is released only when a new read 60.142 + or write occurs later. 60.143 + ----------------------------------------------------------------------*/ 60.144 + always @(/*AUTOSENSE*/enable_read or enable_write 60.145 + or raw or raw_data or read_address 60.146 + or write_address or write_data 60.147 + or write_enable) 60.148 + if (// Read 60.149 + enable_read 60.150 + // Write 60.151 + && enable_write && write_enable 60.152 + // Read and write address match 60.153 + && (read_address == write_address)) 60.154 + begin 60.155 + raw_data_nxt = write_data; 60.156 + raw_nxt = 1'b1; 60.157 + end 60.158 + else 60.159 + if (raw && (enable_read == 1'b0) && (enable_write == 1'b0)) 60.160 + begin 60.161 + raw_data_nxt = raw_data; 60.162 + raw_nxt = 1'b1; 60.163 + end 60.164 + else 60.165 + begin 60.166 + raw_data_nxt = raw_data; 60.167 + raw_nxt = 1'b0; 60.168 + end 60.169 + 60.170 + // Send back write data in case of a RAW hazard; else send back 60.171 + // data from memory 60.172 + assign read_data = raw ? raw_data : read_data_B; 60.173 + 60.174 + /*---------------------------------------------------------------------- 60.175 + Sequential Logic 60.176 + ----------------------------------------------------------------------*/ 60.177 + always @(posedge read_clk) 60.178 + if (reset) 60.179 + begin 60.180 + raw_data <= #1 0; 60.181 + raw <= #1 1'b0; 60.182 + end 60.183 + else 60.184 + begin 60.185 + raw_data <= #1 raw_data_nxt; 60.186 + raw <= #1 raw_nxt; 60.187 + end 60.188 + 60.189 + pmi_ram_dp_true 60.190 + #( 60.191 + // ----- Parameters ----- 60.192 + .pmi_addr_depth_a(1<<address_width), 60.193 + .pmi_addr_width_a(address_width), 60.194 + .pmi_data_width_a(data_width), 60.195 + .pmi_addr_depth_b(1<<address_width), 60.196 + .pmi_addr_width_b(address_width), 60.197 + .pmi_data_width_b(data_width), 60.198 + .pmi_regmode_a("noreg"), 60.199 + .pmi_regmode_b("noreg"), 60.200 + .pmi_gsr("enable"), 60.201 + .pmi_resetmode("sync"), 60.202 + .pmi_init_file("none"), 60.203 + .pmi_init_file_format("binary"), 60.204 + .pmi_family(`LATTICE_FAMILY), 60.205 + .module_type("pmi_ram_dp_true") 60.206 + ) 60.207 + lm32_ram_inst 60.208 + ( 60.209 + // ----- Inputs ----- 60.210 + .DataInA(write_data), 60.211 + .DataInB(write_data), 60.212 + .AddressA(write_address), 60.213 + .AddressB(read_address), 60.214 + .ClockA(write_clk), 60.215 + .ClockB(read_clk), 60.216 + .ClockEnA(enable_write), 60.217 + .ClockEnB(enable_read), 60.218 + .WrA(write_enable), 60.219 + .WrB(`FALSE), 60.220 + .ResetA(reset), 60.221 + .ResetB(reset), 60.222 + // ----- Outputs ----- 60.223 + .QA(read_data_A), 60.224 + .QB(read_data_B) 60.225 + ); 60.226 + end 60.227 + end 60.228 + else if ( RAM_IMPLEMENTATION == "SLICE" ) 60.229 + begin 60.230 + reg [address_width-1:0] ra; // Registered read address 60.231 + 60.232 + pmi_distributed_dpram 60.233 + #( 60.234 + // ----- Parameters ----- 60.235 + .pmi_addr_depth(1<<address_width), 60.236 + .pmi_addr_width(address_width), 60.237 + .pmi_data_width(data_width), 60.238 + .pmi_regmode("noreg"), 60.239 + .pmi_init_file("none"), 60.240 + .pmi_init_file_format("binary"), 60.241 + .pmi_family(`LATTICE_FAMILY), 60.242 + .module_type("pmi_distributed_dpram") 60.243 + ) 60.244 + pmi_distributed_dpram_inst 60.245 + ( 60.246 + // ----- Inputs ----- 60.247 + .WrAddress(write_address), 60.248 + .Data(write_data), 60.249 + .WrClock(write_clk), 60.250 + .WE(write_enable), 60.251 + .WrClockEn(enable_write), 60.252 + .RdAddress(ra), 60.253 + .RdClock(read_clk), 60.254 + .RdClockEn(enable_read), 60.255 + .Reset(reset), 60.256 + // ----- Outputs ----- 60.257 + .Q(read_data) 60.258 + ); 60.259 + 60.260 + always @(posedge read_clk) 60.261 + if (enable_read) 60.262 + ra <= read_address; 60.263 + end 60.264 + 60.265 + else 60.266 + begin 60.267 +`endif 60.268 + /*---------------------------------------------------------------------- 60.269 + Internal nets and registers 60.270 + ----------------------------------------------------------------------*/ 60.271 + reg [data_width-1:0] mem[0:(1<<address_width)-1]; // The RAM 60.272 + reg [address_width-1:0] ra; // Registered read address 60.273 + 60.274 + /*---------------------------------------------------------------------- 60.275 + Combinational Logic 60.276 + ----------------------------------------------------------------------*/ 60.277 + // Read port 60.278 + assign read_data = mem[ra]; 60.279 + 60.280 + /*---------------------------------------------------------------------- 60.281 + Sequential Logic 60.282 + ----------------------------------------------------------------------*/ 60.283 + // Write port 60.284 + always @(posedge write_clk) 60.285 + if ((write_enable == `TRUE) && (enable_write == `TRUE)) 60.286 + mem[write_address] <= write_data; 60.287 + 60.288 + // Register read address for use on next cycle 60.289 + always @(posedge read_clk) 60.290 + if (enable_read) 60.291 + ra <= read_address; 60.292 + 60.293 +`ifdef PLATFORM_LATTICE 60.294 + end 60.295 + 60.296 + endgenerate 60.297 +`endif 60.298 +endmodule
61.1 diff -r 252df75c8f67 -r c336e674a37e rtl/lm32_shifter.v 61.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 61.3 +++ b/rtl/lm32_shifter.v Tue Mar 08 09:40:42 2011 +0000 61.4 @@ -0,0 +1,134 @@ 61.5 +// ============================================================================= 61.6 +// COPYRIGHT NOTICE 61.7 +// Copyright 2006 (c) Lattice Semiconductor Corporation 61.8 +// ALL RIGHTS RESERVED 61.9 +// This confidential and proprietary software may be used only as authorised by 61.10 +// a licensing agreement from Lattice Semiconductor Corporation. 61.11 +// The entire notice above must be reproduced on all authorized copies and 61.12 +// copies may only be made to the extent permitted by a licensing agreement from 61.13 +// Lattice Semiconductor Corporation. 61.14 +// 61.15 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 61.16 +// 5555 NE Moore Court 408-826-6000 (other locations) 61.17 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 61.18 +// U.S.A email: techsupport@latticesemi.com 61.19 +// =============================================================================/ 61.20 +// FILE DETAILS 61.21 +// Project : LatticeMico32 61.22 +// File : lm32_shifter.v 61.23 +// Title : Barrel shifter 61.24 +// Dependencies : lm32_include.v 61.25 +// Version : 6.1.17 61.26 +// : Initial Release 61.27 +// Version : 7.0SP2, 3.0 61.28 +// : No Change 61.29 +// Version : 3.1 61.30 +// : No Change 61.31 +// ============================================================================= 61.32 + 61.33 +`include "lm32_include.v" 61.34 + 61.35 +///////////////////////////////////////////////////// 61.36 +// Module interface 61.37 +///////////////////////////////////////////////////// 61.38 + 61.39 +module lm32_shifter ( 61.40 + // ----- Inputs ------- 61.41 + clk_i, 61.42 + rst_i, 61.43 + stall_x, 61.44 + direction_x, 61.45 + sign_extend_x, 61.46 + operand_0_x, 61.47 + operand_1_x, 61.48 + // ----- Outputs ------- 61.49 + shifter_result_m 61.50 + ); 61.51 + 61.52 +///////////////////////////////////////////////////// 61.53 +// Inputs 61.54 +///////////////////////////////////////////////////// 61.55 + 61.56 +input clk_i; // Clock 61.57 +input rst_i; // Reset 61.58 +input stall_x; // Stall instruction in X stage 61.59 +input direction_x; // Direction to shift 61.60 +input sign_extend_x; // Whether shift is arithmetic (1'b1) or logical (1'b0) 61.61 +input [`LM32_WORD_RNG] operand_0_x; // Operand to shift 61.62 +input [`LM32_WORD_RNG] operand_1_x; // Operand that specifies how many bits to shift by 61.63 + 61.64 +///////////////////////////////////////////////////// 61.65 +// Outputs 61.66 +///////////////////////////////////////////////////// 61.67 + 61.68 +output [`LM32_WORD_RNG] shifter_result_m; // Result of shift 61.69 +wire [`LM32_WORD_RNG] shifter_result_m; 61.70 + 61.71 +///////////////////////////////////////////////////// 61.72 +// Internal nets and registers 61.73 +///////////////////////////////////////////////////// 61.74 + 61.75 +reg direction_m; 61.76 +reg [`LM32_WORD_RNG] left_shift_result; 61.77 +reg [`LM32_WORD_RNG] right_shift_result; 61.78 +reg [`LM32_WORD_RNG] left_shift_operand; 61.79 +wire [`LM32_WORD_RNG] right_shift_operand; 61.80 +wire fill_value; 61.81 +wire [`LM32_WORD_RNG] right_shift_in; 61.82 + 61.83 +integer shift_idx_0; 61.84 +integer shift_idx_1; 61.85 + 61.86 +///////////////////////////////////////////////////// 61.87 +// Combinational Logic 61.88 +///////////////////////////////////////////////////// 61.89 + 61.90 +// Select operands - To perform a left shift, we reverse the bits and perform a right shift 61.91 +always @(*) 61.92 +begin 61.93 + for (shift_idx_0 = 0; shift_idx_0 < `LM32_WORD_WIDTH; shift_idx_0 = shift_idx_0 + 1) 61.94 + left_shift_operand[`LM32_WORD_WIDTH-1-shift_idx_0] = operand_0_x[shift_idx_0]; 61.95 +end 61.96 +assign right_shift_operand = direction_x == `LM32_SHIFT_OP_LEFT ? left_shift_operand : operand_0_x; 61.97 + 61.98 +// Determine fill value for right shift - Sign bit for arithmetic shift, or zero for logical shift 61.99 +assign fill_value = (sign_extend_x == `TRUE) && (direction_x == `LM32_SHIFT_OP_RIGHT) 61.100 + ? operand_0_x[`LM32_WORD_WIDTH-1] 61.101 + : 1'b0; 61.102 + 61.103 +// Determine bits to shift in for right shift or rotate 61.104 +assign right_shift_in = {`LM32_WORD_WIDTH{fill_value}}; 61.105 + 61.106 +// Reverse bits to get left shift result 61.107 +always @(*) 61.108 +begin 61.109 + for (shift_idx_1 = 0; shift_idx_1 < `LM32_WORD_WIDTH; shift_idx_1 = shift_idx_1 + 1) 61.110 + left_shift_result[`LM32_WORD_WIDTH-1-shift_idx_1] = right_shift_result[shift_idx_1]; 61.111 +end 61.112 + 61.113 +// Select result 61.114 +assign shifter_result_m = direction_m == `LM32_SHIFT_OP_LEFT ? left_shift_result : right_shift_result; 61.115 + 61.116 +///////////////////////////////////////////////////// 61.117 +// Sequential Logic 61.118 +///////////////////////////////////////////////////// 61.119 + 61.120 +// Perform right shift 61.121 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 61.122 +begin 61.123 + if (rst_i == `TRUE) 61.124 + begin 61.125 + right_shift_result <= {`LM32_WORD_WIDTH{1'b0}}; 61.126 + direction_m <= `FALSE; 61.127 + end 61.128 + else 61.129 + begin 61.130 + if (stall_x == `FALSE) 61.131 + begin 61.132 + right_shift_result <= {right_shift_in, right_shift_operand} >> operand_1_x[`LM32_SHIFT_RNG]; 61.133 + direction_m <= direction_x; 61.134 + end 61.135 + end 61.136 +end 61.137 + 61.138 +endmodule
62.1 diff -r 252df75c8f67 -r c336e674a37e rtl/lm32_top.v 62.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 62.3 +++ b/rtl/lm32_top.v Tue Mar 08 09:40:42 2011 +0000 62.4 @@ -0,0 +1,355 @@ 62.5 +// ============================================================================= 62.6 +// COPYRIGHT NOTICE 62.7 +// Copyright 2006 (c) Lattice Semiconductor Corporation 62.8 +// ALL RIGHTS RESERVED 62.9 +// This confidential and proprietary software may be used only as authorised by 62.10 +// a licensing agreement from Lattice Semiconductor Corporation. 62.11 +// The entire notice above must be reproduced on all authorized copies and 62.12 +// copies may only be made to the extent permitted by a licensing agreement from 62.13 +// Lattice Semiconductor Corporation. 62.14 +// 62.15 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 62.16 +// 5555 NE Moore Court 408-826-6000 (other locations) 62.17 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 62.18 +// U.S.A email: techsupport@latticesemi.com 62.19 +// =============================================================================/ 62.20 +// FILE DETAILS 62.21 +// Project : LatticeMico32 62.22 +// File : lm32_top.v 62.23 +// Title : Top-level of CPU. 62.24 +// Dependencies : lm32_include.v 62.25 +// Version : 6.1.17 62.26 +// : removed SPI - 04/12/07 62.27 +// Version : 7.0SP2, 3.0 62.28 +// : No Change 62.29 +// Version : 3.1 62.30 +// : No Change 62.31 +// ============================================================================= 62.32 + 62.33 +`include "lm32_include.v" 62.34 + 62.35 +///////////////////////////////////////////////////// 62.36 +// Module interface 62.37 +///////////////////////////////////////////////////// 62.38 + 62.39 +module lm32_top ( 62.40 + // ----- Inputs ------- 62.41 + clk_i, 62.42 + rst_i, 62.43 + // From external devices 62.44 +`ifdef CFG_INTERRUPTS_ENABLED 62.45 + interrupt, 62.46 +`endif 62.47 + // From user logic 62.48 +`ifdef CFG_USER_ENABLED 62.49 + user_result, 62.50 + user_complete, 62.51 +`endif 62.52 +`ifdef CFG_IWB_ENABLED 62.53 + // Instruction Wishbone master 62.54 + I_DAT_I, 62.55 + I_ACK_I, 62.56 + I_ERR_I, 62.57 + I_RTY_I, 62.58 +`endif 62.59 + // Data Wishbone master 62.60 + D_DAT_I, 62.61 + D_ACK_I, 62.62 + D_ERR_I, 62.63 + D_RTY_I, 62.64 + // ----- Outputs ------- 62.65 +`ifdef CFG_USER_ENABLED 62.66 + user_valid, 62.67 + user_opcode, 62.68 + user_operand_0, 62.69 + user_operand_1, 62.70 +`endif 62.71 +`ifdef CFG_IWB_ENABLED 62.72 + // Instruction Wishbone master 62.73 + I_DAT_O, 62.74 + I_ADR_O, 62.75 + I_CYC_O, 62.76 + I_SEL_O, 62.77 + I_STB_O, 62.78 + I_WE_O, 62.79 + I_CTI_O, 62.80 + I_LOCK_O, 62.81 + I_BTE_O, 62.82 +`endif 62.83 + // Data Wishbone master 62.84 + D_DAT_O, 62.85 + D_ADR_O, 62.86 + D_CYC_O, 62.87 + D_SEL_O, 62.88 + D_STB_O, 62.89 + D_WE_O, 62.90 + D_CTI_O, 62.91 + D_LOCK_O, 62.92 + D_BTE_O 62.93 + ); 62.94 + 62.95 +///////////////////////////////////////////////////// 62.96 +// Inputs 62.97 +///////////////////////////////////////////////////// 62.98 + 62.99 +input clk_i; // Clock 62.100 +input rst_i; // Reset 62.101 + 62.102 +`ifdef CFG_INTERRUPTS_ENABLED 62.103 +input [`LM32_INTERRUPT_RNG] interrupt; // Interrupt pins 62.104 +`endif 62.105 + 62.106 +`ifdef CFG_USER_ENABLED 62.107 +input [`LM32_WORD_RNG] user_result; // User-defined instruction result 62.108 +input user_complete; // Indicates the user-defined instruction result is valid 62.109 +`endif 62.110 + 62.111 +`ifdef CFG_IWB_ENABLED 62.112 +input [`LM32_WORD_RNG] I_DAT_I; // Instruction Wishbone interface read data 62.113 +input I_ACK_I; // Instruction Wishbone interface acknowledgement 62.114 +input I_ERR_I; // Instruction Wishbone interface error 62.115 +input I_RTY_I; // Instruction Wishbone interface retry 62.116 +`endif 62.117 + 62.118 +input [`LM32_WORD_RNG] D_DAT_I; // Data Wishbone interface read data 62.119 +input D_ACK_I; // Data Wishbone interface acknowledgement 62.120 +input D_ERR_I; // Data Wishbone interface error 62.121 +input D_RTY_I; // Data Wishbone interface retry 62.122 + 62.123 +///////////////////////////////////////////////////// 62.124 +// Outputs 62.125 +///////////////////////////////////////////////////// 62.126 + 62.127 +`ifdef CFG_USER_ENABLED 62.128 +output user_valid; // Indicates that user_opcode and user_operand_* are valid 62.129 +wire user_valid; 62.130 +output [`LM32_USER_OPCODE_RNG] user_opcode; // User-defined instruction opcode 62.131 +reg [`LM32_USER_OPCODE_RNG] user_opcode; 62.132 +output [`LM32_WORD_RNG] user_operand_0; // First operand for user-defined instruction 62.133 +wire [`LM32_WORD_RNG] user_operand_0; 62.134 +output [`LM32_WORD_RNG] user_operand_1; // Second operand for user-defined instruction 62.135 +wire [`LM32_WORD_RNG] user_operand_1; 62.136 +`endif 62.137 + 62.138 +`ifdef CFG_IWB_ENABLED 62.139 +output [`LM32_WORD_RNG] I_DAT_O; // Instruction Wishbone interface write data 62.140 +wire [`LM32_WORD_RNG] I_DAT_O; 62.141 +output [`LM32_WORD_RNG] I_ADR_O; // Instruction Wishbone interface address 62.142 +wire [`LM32_WORD_RNG] I_ADR_O; 62.143 +output I_CYC_O; // Instruction Wishbone interface cycle 62.144 +wire I_CYC_O; 62.145 +output [`LM32_BYTE_SELECT_RNG] I_SEL_O; // Instruction Wishbone interface byte select 62.146 +wire [`LM32_BYTE_SELECT_RNG] I_SEL_O; 62.147 +output I_STB_O; // Instruction Wishbone interface strobe 62.148 +wire I_STB_O; 62.149 +output I_WE_O; // Instruction Wishbone interface write enable 62.150 +wire I_WE_O; 62.151 +output [`LM32_CTYPE_RNG] I_CTI_O; // Instruction Wishbone interface cycle type 62.152 +wire [`LM32_CTYPE_RNG] I_CTI_O; 62.153 +output I_LOCK_O; // Instruction Wishbone interface lock bus 62.154 +wire I_LOCK_O; 62.155 +output [`LM32_BTYPE_RNG] I_BTE_O; // Instruction Wishbone interface burst type 62.156 +wire [`LM32_BTYPE_RNG] I_BTE_O; 62.157 +`endif 62.158 + 62.159 +output [`LM32_WORD_RNG] D_DAT_O; // Data Wishbone interface write data 62.160 +wire [`LM32_WORD_RNG] D_DAT_O; 62.161 +output [`LM32_WORD_RNG] D_ADR_O; // Data Wishbone interface address 62.162 +wire [`LM32_WORD_RNG] D_ADR_O; 62.163 +output D_CYC_O; // Data Wishbone interface cycle 62.164 +wire D_CYC_O; 62.165 +output [`LM32_BYTE_SELECT_RNG] D_SEL_O; // Data Wishbone interface byte select 62.166 +wire [`LM32_BYTE_SELECT_RNG] D_SEL_O; 62.167 +output D_STB_O; // Data Wishbone interface strobe 62.168 +wire D_STB_O; 62.169 +output D_WE_O; // Data Wishbone interface write enable 62.170 +wire D_WE_O; 62.171 +output [`LM32_CTYPE_RNG] D_CTI_O; // Data Wishbone interface cycle type 62.172 +wire [`LM32_CTYPE_RNG] D_CTI_O; 62.173 +output D_LOCK_O; // Date Wishbone interface lock bus 62.174 +wire D_LOCK_O; 62.175 +output [`LM32_BTYPE_RNG] D_BTE_O; // Data Wishbone interface burst type 62.176 +wire [`LM32_BTYPE_RNG] D_BTE_O; 62.177 + 62.178 +///////////////////////////////////////////////////// 62.179 +// Internal nets and registers 62.180 +///////////////////////////////////////////////////// 62.181 + 62.182 +`ifdef CFG_JTAG_ENABLED 62.183 +// Signals between JTAG interface and CPU 62.184 +wire [`LM32_BYTE_RNG] jtag_reg_d; 62.185 +wire [`LM32_BYTE_RNG] jtag_reg_q; 62.186 +wire jtag_update; 62.187 +wire [2:0] jtag_reg_addr_d; 62.188 +wire [2:0] jtag_reg_addr_q; 62.189 +wire jtck; 62.190 +wire jrstn; 62.191 +`endif 62.192 + 62.193 +// TODO: get the trace signals out 62.194 +`ifdef CFG_TRACE_ENABLED 62.195 +// PC trace signals 62.196 +wire [`LM32_PC_RNG] trace_pc; // PC to trace (address of next non-sequential instruction) 62.197 +wire trace_pc_valid; // Indicates that a new trace PC is valid 62.198 +wire trace_exception; // Indicates an exception has occured 62.199 +wire [`LM32_EID_RNG] trace_eid; // Indicates what type of exception has occured 62.200 +wire trace_eret; // Indicates an eret instruction has been executed 62.201 +`ifdef CFG_DEBUG_ENABLED 62.202 +wire trace_bret; // Indicates a bret instruction has been executed 62.203 +`endif 62.204 +`endif 62.205 + 62.206 +///////////////////////////////////////////////////// 62.207 +// Functions 62.208 +///////////////////////////////////////////////////// 62.209 + 62.210 +`include "lm32_functions.v" 62.211 +///////////////////////////////////////////////////// 62.212 +// Instantiations 62.213 +///////////////////////////////////////////////////// 62.214 + 62.215 +// LM32 CPU 62.216 +lm32_cpu cpu ( 62.217 + // ----- Inputs ------- 62.218 + .clk_i (clk_i), 62.219 +`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE 62.220 + .clk_n_i (clk_n), 62.221 +`endif 62.222 + .rst_i (rst_i), 62.223 + // From external devices 62.224 +`ifdef CFG_INTERRUPTS_ENABLED 62.225 + .interrupt (interrupt), 62.226 +`endif 62.227 + // From user logic 62.228 +`ifdef CFG_USER_ENABLED 62.229 + .user_result (user_result), 62.230 + .user_complete (user_complete), 62.231 +`endif 62.232 +`ifdef CFG_JTAG_ENABLED 62.233 + // From JTAG 62.234 + .jtag_clk (jtck), 62.235 + .jtag_update (jtag_update), 62.236 + .jtag_reg_q (jtag_reg_q), 62.237 + .jtag_reg_addr_q (jtag_reg_addr_q), 62.238 +`endif 62.239 +`ifdef CFG_IWB_ENABLED 62.240 + // Instruction Wishbone master 62.241 + .I_DAT_I (I_DAT_I), 62.242 + .I_ACK_I (I_ACK_I), 62.243 + .I_ERR_I (I_ERR_I), 62.244 + .I_RTY_I (I_RTY_I), 62.245 +`endif 62.246 + // Data Wishbone master 62.247 + .D_DAT_I (D_DAT_I), 62.248 + .D_ACK_I (D_ACK_I), 62.249 + .D_ERR_I (D_ERR_I), 62.250 + .D_RTY_I (D_RTY_I), 62.251 + // ----- Outputs ------- 62.252 +`ifdef CFG_TRACE_ENABLED 62.253 + .trace_pc (trace_pc), 62.254 + .trace_pc_valid (trace_pc_valid), 62.255 + .trace_exception (trace_exception), 62.256 + .trace_eid (trace_eid), 62.257 + .trace_eret (trace_eret), 62.258 +`ifdef CFG_DEBUG_ENABLED 62.259 + .trace_bret (trace_bret), 62.260 +`endif 62.261 +`endif 62.262 +`ifdef CFG_JTAG_ENABLED 62.263 + .jtag_reg_d (jtag_reg_d), 62.264 + .jtag_reg_addr_d (jtag_reg_addr_d), 62.265 +`endif 62.266 +`ifdef CFG_USER_ENABLED 62.267 + .user_valid (user_valid), 62.268 + .user_opcode (user_opcode), 62.269 + .user_operand_0 (user_operand_0), 62.270 + .user_operand_1 (user_operand_1), 62.271 +`endif 62.272 +`ifdef CFG_IWB_ENABLED 62.273 + // Instruction Wishbone master 62.274 + .I_DAT_O (I_DAT_O), 62.275 + .I_ADR_O (I_ADR_O), 62.276 + .I_CYC_O (I_CYC_O), 62.277 + .I_SEL_O (I_SEL_O), 62.278 + .I_STB_O (I_STB_O), 62.279 + .I_WE_O (I_WE_O), 62.280 + .I_CTI_O (I_CTI_O), 62.281 + .I_LOCK_O (I_LOCK_O), 62.282 + .I_BTE_O (I_BTE_O), 62.283 + `endif 62.284 + // Data Wishbone master 62.285 + .D_DAT_O (D_DAT_O), 62.286 + .D_ADR_O (D_ADR_O), 62.287 + .D_CYC_O (D_CYC_O), 62.288 + .D_SEL_O (D_SEL_O), 62.289 + .D_STB_O (D_STB_O), 62.290 + .D_WE_O (D_WE_O), 62.291 + .D_CTI_O (D_CTI_O), 62.292 + .D_LOCK_O (D_LOCK_O), 62.293 + .D_BTE_O (D_BTE_O) 62.294 + ); 62.295 + 62.296 + wire TRACE_ACK_O; 62.297 + wire [`LM32_WORD_RNG] TRACE_DAT_O; 62.298 +`ifdef CFG_TRACE_ENABLED 62.299 + lm32_trace trace_module (.clk_i (clk_i), 62.300 + .rst_i (rst_i), 62.301 + .stb_i (DEBUG_STB_I & DEBUG_ADR_I[13]), 62.302 + .we_i (DEBUG_WE_I), 62.303 + .sel_i (DEBUG_SEL_I), 62.304 + .dat_i (DEBUG_DAT_I), 62.305 + .adr_i (DEBUG_ADR_I), 62.306 + .trace_pc (trace_pc), 62.307 + .trace_eid (trace_eid), 62.308 + .trace_eret (trace_eret), 62.309 + .trace_bret (trace_bret), 62.310 + .trace_pc_valid (trace_pc_valid), 62.311 + .trace_exception (trace_exception), 62.312 + .ack_o (TRACE_ACK_O), 62.313 + .dat_o (TRACE_DAT_O)); 62.314 +`else 62.315 + assign TRACE_ACK_O = 0; 62.316 + assign TRACE_DAT_O = 0; 62.317 +`endif 62.318 +`ifdef DEBUG_ROM 62.319 + wire ROM_ACK_O; 62.320 + wire [`LM32_WORD_RNG] ROM_DAT_O; 62.321 + 62.322 + assign DEBUG_ACK_O = DEBUG_ADR_I[13] ? TRACE_ACK_O : ROM_ACK_O; 62.323 + assign DEBUG_DAT_O = DEBUG_ADR_I[13] ? TRACE_DAT_O : ROM_DAT_O; 62.324 + 62.325 + // ROM monitor 62.326 + lm32_monitor debug_rom ( 62.327 + // ----- Inputs ------- 62.328 + .clk_i (clk_i), 62.329 + .rst_i (rst_i), 62.330 + .MON_ADR_I (DEBUG_ADR_I[10:2]), 62.331 + .MON_STB_I (DEBUG_STB_I & ~DEBUG_ADR_I[13]), 62.332 + .MON_CYC_I (DEBUG_CYC_I & ~DEBUG_ADR_I[13]), 62.333 + .MON_WE_I (DEBUG_WE_I), 62.334 + .MON_SEL_I (DEBUG_SEL_I), 62.335 + .MON_DAT_I (DEBUG_DAT_I), 62.336 + // ----- Outputs ------ 62.337 + .MON_RTY_O (DEBUG_RTY_O), 62.338 + .MON_ERR_O (DEBUG_ERR_O), 62.339 + .MON_ACK_O (ROM_ACK_O), 62.340 + .MON_DAT_O (ROM_DAT_O) 62.341 + ); 62.342 +`endif 62.343 + 62.344 +`ifdef CFG_JTAG_ENABLED 62.345 +// JTAG cores 62.346 +jtag_cores jtag_cores ( 62.347 + // ----- Inputs ----- 62.348 + .reg_d (jtag_reg_d), 62.349 + .reg_addr_d (jtag_reg_addr_d), 62.350 + // ----- Outputs ----- 62.351 + .reg_update (jtag_update), 62.352 + .reg_q (jtag_reg_q), 62.353 + .reg_addr_q (jtag_reg_addr_q), 62.354 + .jtck (jtck), 62.355 + .jrstn (jrstn) 62.356 + ); 62.357 +`endif 62.358 + 62.359 +endmodule
