1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 1.2 +++ b/lm32_top.v Sun Apr 04 20:40:03 2010 +0100 1.3 @@ -0,0 +1,395 @@ 1.4 +// ============================================================================= 1.5 +// COPYRIGHT NOTICE 1.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation 1.7 +// ALL RIGHTS RESERVED 1.8 +// This confidential and proprietary software may be used only as authorised by 1.9 +// a licensing agreement from Lattice Semiconductor Corporation. 1.10 +// The entire notice above must be reproduced on all authorized copies and 1.11 +// copies may only be made to the extent permitted by a licensing agreement from 1.12 +// Lattice Semiconductor Corporation. 1.13 +// 1.14 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 1.15 +// 5555 NE Moore Court 408-826-6000 (other locations) 1.16 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 1.17 +// U.S.A email: techsupport@latticesemi.com 1.18 +// =============================================================================/ 1.19 +// FILE DETAILS 1.20 +// Project : LatticeMico32 1.21 +// File : lm32_top.v 1.22 +// Title : Top-level of CPU. 1.23 +// Dependencies : lm32_include.v 1.24 +// Version : 6.1.17 1.25 +// : removed SPI - 04/12/07 1.26 +// Version : 7.0SP2, 3.0 1.27 +// : No Change 1.28 +// Version : 3.1 1.29 +// : No Change 1.30 +// ============================================================================= 1.31 + 1.32 +`include "lm32_include.v" 1.33 + 1.34 +///////////////////////////////////////////////////// 1.35 +// Module interface 1.36 +///////////////////////////////////////////////////// 1.37 + 1.38 +module lm32_top ( 1.39 + // ----- Inputs ------- 1.40 + clk_i, 1.41 + rst_i, 1.42 + // From external devices 1.43 +`ifdef CFG_INTERRUPTS_ENABLED 1.44 + interrupt_n, 1.45 +`endif 1.46 + // From user logic 1.47 +`ifdef CFG_USER_ENABLED 1.48 + user_result, 1.49 + user_complete, 1.50 +`endif 1.51 +`ifdef CFG_IWB_ENABLED 1.52 + // Instruction Wishbone master 1.53 + I_DAT_I, 1.54 + I_ACK_I, 1.55 + I_ERR_I, 1.56 + I_RTY_I, 1.57 +`endif 1.58 + // Data Wishbone master 1.59 + D_DAT_I, 1.60 + D_ACK_I, 1.61 + D_ERR_I, 1.62 + D_RTY_I, 1.63 + // Debug Slave port WishboneInterface 1.64 + DEBUG_ADR_I, 1.65 + DEBUG_DAT_I, 1.66 + DEBUG_SEL_I, 1.67 + DEBUG_WE_I, 1.68 + DEBUG_CTI_I, 1.69 + DEBUG_BTE_I, 1.70 + DEBUG_LOCK_I, 1.71 + DEBUG_CYC_I, 1.72 + DEBUG_STB_I, 1.73 + // ----- Outputs ------- 1.74 +`ifdef CFG_USER_ENABLED 1.75 + user_valid, 1.76 + user_opcode, 1.77 + user_operand_0, 1.78 + user_operand_1, 1.79 +`endif 1.80 +`ifdef CFG_IWB_ENABLED 1.81 + // Instruction Wishbone master 1.82 + I_DAT_O, 1.83 + I_ADR_O, 1.84 + I_CYC_O, 1.85 + I_SEL_O, 1.86 + I_STB_O, 1.87 + I_WE_O, 1.88 + I_CTI_O, 1.89 + I_LOCK_O, 1.90 + I_BTE_O, 1.91 +`endif 1.92 + // Data Wishbone master 1.93 + D_DAT_O, 1.94 + D_ADR_O, 1.95 + D_CYC_O, 1.96 + D_SEL_O, 1.97 + D_STB_O, 1.98 + D_WE_O, 1.99 + D_CTI_O, 1.100 + D_LOCK_O, 1.101 + D_BTE_O, 1.102 + // Debug Slave port WishboneInterface 1.103 + DEBUG_ACK_O, 1.104 + DEBUG_ERR_O, 1.105 + DEBUG_RTY_O, 1.106 + DEBUG_DAT_O 1.107 + ); 1.108 + 1.109 +///////////////////////////////////////////////////// 1.110 +// Inputs 1.111 +///////////////////////////////////////////////////// 1.112 + 1.113 +input clk_i; // Clock 1.114 +input rst_i; // Reset 1.115 + 1.116 +`ifdef CFG_INTERRUPTS_ENABLED 1.117 +input [`LM32_INTERRUPT_RNG] interrupt_n; // Interrupt pins, active-low 1.118 +`endif 1.119 + 1.120 +`ifdef CFG_USER_ENABLED 1.121 +input [`LM32_WORD_RNG] user_result; // User-defined instruction result 1.122 +input user_complete; // Indicates the user-defined instruction result is valid 1.123 +`endif 1.124 + 1.125 +`ifdef CFG_IWB_ENABLED 1.126 +input [`LM32_WORD_RNG] I_DAT_I; // Instruction Wishbone interface read data 1.127 +input I_ACK_I; // Instruction Wishbone interface acknowledgement 1.128 +input I_ERR_I; // Instruction Wishbone interface error 1.129 +input I_RTY_I; // Instruction Wishbone interface retry 1.130 +`endif 1.131 + 1.132 +input [`LM32_WORD_RNG] D_DAT_I; // Data Wishbone interface read data 1.133 +input D_ACK_I; // Data Wishbone interface acknowledgement 1.134 +input D_ERR_I; // Data Wishbone interface error 1.135 +input D_RTY_I; // Data Wishbone interface retry 1.136 + 1.137 +input [`LM32_WORD_RNG] DEBUG_ADR_I; // Debug monitor Wishbone interface address 1.138 +input [`LM32_WORD_RNG] DEBUG_DAT_I; // Debug monitor Wishbone interface write data 1.139 +input [`LM32_BYTE_SELECT_RNG] DEBUG_SEL_I; // Debug monitor Wishbone interface byte select 1.140 +input DEBUG_WE_I; // Debug monitor Wishbone interface write enable 1.141 +input [`LM32_CTYPE_RNG] DEBUG_CTI_I; // Debug monitor Wishbone interface cycle type 1.142 +input [`LM32_BTYPE_RNG] DEBUG_BTE_I; // Debug monitor Wishbone interface burst type 1.143 +input DEBUG_LOCK_I; // Debug monitor Wishbone interface locked transfer 1.144 +input DEBUG_CYC_I; // Debug monitor Wishbone interface cycle 1.145 +input DEBUG_STB_I; // Debug monitor Wishbone interface strobe 1.146 + 1.147 +///////////////////////////////////////////////////// 1.148 +// Outputs 1.149 +///////////////////////////////////////////////////// 1.150 + 1.151 +`ifdef CFG_USER_ENABLED 1.152 +output user_valid; // Indicates that user_opcode and user_operand_* are valid 1.153 +wire user_valid; 1.154 +output [`LM32_USER_OPCODE_RNG] user_opcode; // User-defined instruction opcode 1.155 +reg [`LM32_USER_OPCODE_RNG] user_opcode; 1.156 +output [`LM32_WORD_RNG] user_operand_0; // First operand for user-defined instruction 1.157 +wire [`LM32_WORD_RNG] user_operand_0; 1.158 +output [`LM32_WORD_RNG] user_operand_1; // Second operand for user-defined instruction 1.159 +wire [`LM32_WORD_RNG] user_operand_1; 1.160 +`endif 1.161 + 1.162 +`ifdef CFG_IWB_ENABLED 1.163 +output [`LM32_WORD_RNG] I_DAT_O; // Instruction Wishbone interface write data 1.164 +wire [`LM32_WORD_RNG] I_DAT_O; 1.165 +output [`LM32_WORD_RNG] I_ADR_O; // Instruction Wishbone interface address 1.166 +wire [`LM32_WORD_RNG] I_ADR_O; 1.167 +output I_CYC_O; // Instruction Wishbone interface cycle 1.168 +wire I_CYC_O; 1.169 +output [`LM32_BYTE_SELECT_RNG] I_SEL_O; // Instruction Wishbone interface byte select 1.170 +wire [`LM32_BYTE_SELECT_RNG] I_SEL_O; 1.171 +output I_STB_O; // Instruction Wishbone interface strobe 1.172 +wire I_STB_O; 1.173 +output I_WE_O; // Instruction Wishbone interface write enable 1.174 +wire I_WE_O; 1.175 +output [`LM32_CTYPE_RNG] I_CTI_O; // Instruction Wishbone interface cycle type 1.176 +wire [`LM32_CTYPE_RNG] I_CTI_O; 1.177 +output I_LOCK_O; // Instruction Wishbone interface lock bus 1.178 +wire I_LOCK_O; 1.179 +output [`LM32_BTYPE_RNG] I_BTE_O; // Instruction Wishbone interface burst type 1.180 +wire [`LM32_BTYPE_RNG] I_BTE_O; 1.181 +`endif 1.182 + 1.183 +output [`LM32_WORD_RNG] D_DAT_O; // Data Wishbone interface write data 1.184 +wire [`LM32_WORD_RNG] D_DAT_O; 1.185 +output [`LM32_WORD_RNG] D_ADR_O; // Data Wishbone interface address 1.186 +wire [`LM32_WORD_RNG] D_ADR_O; 1.187 +output D_CYC_O; // Data Wishbone interface cycle 1.188 +wire D_CYC_O; 1.189 +output [`LM32_BYTE_SELECT_RNG] D_SEL_O; // Data Wishbone interface byte select 1.190 +wire [`LM32_BYTE_SELECT_RNG] D_SEL_O; 1.191 +output D_STB_O; // Data Wishbone interface strobe 1.192 +wire D_STB_O; 1.193 +output D_WE_O; // Data Wishbone interface write enable 1.194 +wire D_WE_O; 1.195 +output [`LM32_CTYPE_RNG] D_CTI_O; // Data Wishbone interface cycle type 1.196 +wire [`LM32_CTYPE_RNG] D_CTI_O; 1.197 +output D_LOCK_O; // Date Wishbone interface lock bus 1.198 +wire D_LOCK_O; 1.199 +output [`LM32_BTYPE_RNG] D_BTE_O; // Data Wishbone interface burst type 1.200 +wire [`LM32_BTYPE_RNG] D_BTE_O; 1.201 + 1.202 +output DEBUG_ACK_O; // Debug monitor Wishbone ack 1.203 +wire DEBUG_ACK_O; 1.204 +output DEBUG_ERR_O; // Debug monitor Wishbone error 1.205 +wire DEBUG_ERR_O; 1.206 +output DEBUG_RTY_O; // Debug monitor Wishbone retry 1.207 +wire DEBUG_RTY_O; 1.208 +output [`LM32_WORD_RNG] DEBUG_DAT_O; // Debug monitor Wishbone read data 1.209 +wire [`LM32_WORD_RNG] DEBUG_DAT_O; 1.210 + 1.211 +///////////////////////////////////////////////////// 1.212 +// Internal nets and registers 1.213 +///////////////////////////////////////////////////// 1.214 + 1.215 +`ifdef CFG_JTAG_ENABLED 1.216 +// Signals between JTAG interface and CPU 1.217 +wire [`LM32_BYTE_RNG] jtag_reg_d; 1.218 +wire [`LM32_BYTE_RNG] jtag_reg_q; 1.219 +wire jtag_update; 1.220 +wire [2:0] jtag_reg_addr_d; 1.221 +wire [2:0] jtag_reg_addr_q; 1.222 +wire jtck; 1.223 +wire jrstn; 1.224 +`endif 1.225 + 1.226 +`ifdef CFG_TRACE_ENABLED 1.227 +// PC trace signals 1.228 +wire [`LM32_PC_RNG] trace_pc; // PC to trace (address of next non-sequential instruction) 1.229 +wire trace_pc_valid; // Indicates that a new trace PC is valid 1.230 +wire trace_exception; // Indicates an exception has occured 1.231 +wire [`LM32_EID_RNG] trace_eid; // Indicates what type of exception has occured 1.232 +wire trace_eret; // Indicates an eret instruction has been executed 1.233 +`ifdef CFG_DEBUG_ENABLED 1.234 +wire trace_bret; // Indicates a bret instruction has been executed 1.235 +`endif 1.236 +`endif 1.237 + 1.238 +///////////////////////////////////////////////////// 1.239 +// Functions 1.240 +///////////////////////////////////////////////////// 1.241 + 1.242 +`include "lm32_functions.v" 1.243 +///////////////////////////////////////////////////// 1.244 +// Instantiations 1.245 +///////////////////////////////////////////////////// 1.246 + 1.247 +// LM32 CPU 1.248 +lm32_cpu cpu ( 1.249 + // ----- Inputs ------- 1.250 + .clk_i (clk_i), 1.251 +`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE 1.252 + .clk_n_i (clk_n), 1.253 +`endif 1.254 + .rst_i (rst_i), 1.255 + // From external devices 1.256 +`ifdef CFG_INTERRUPTS_ENABLED 1.257 + .interrupt_n (interrupt_n), 1.258 +`endif 1.259 + // From user logic 1.260 +`ifdef CFG_USER_ENABLED 1.261 + .user_result (user_result), 1.262 + .user_complete (user_complete), 1.263 +`endif 1.264 +`ifdef CFG_JTAG_ENABLED 1.265 + // From JTAG 1.266 + .jtag_clk (jtck), 1.267 + .jtag_update (jtag_update), 1.268 + .jtag_reg_q (jtag_reg_q), 1.269 + .jtag_reg_addr_q (jtag_reg_addr_q), 1.270 +`endif 1.271 +`ifdef CFG_IWB_ENABLED 1.272 + // Instruction Wishbone master 1.273 + .I_DAT_I (I_DAT_I), 1.274 + .I_ACK_I (I_ACK_I), 1.275 + .I_ERR_I (I_ERR_I), 1.276 + .I_RTY_I (I_RTY_I), 1.277 +`endif 1.278 + // Data Wishbone master 1.279 + .D_DAT_I (D_DAT_I), 1.280 + .D_ACK_I (D_ACK_I), 1.281 + .D_ERR_I (D_ERR_I), 1.282 + .D_RTY_I (D_RTY_I), 1.283 + // ----- Outputs ------- 1.284 +`ifdef CFG_TRACE_ENABLED 1.285 + .trace_pc (trace_pc), 1.286 + .trace_pc_valid (trace_pc_valid), 1.287 + .trace_exception (trace_exception), 1.288 + .trace_eid (trace_eid), 1.289 + .trace_eret (trace_eret), 1.290 +`ifdef CFG_DEBUG_ENABLED 1.291 + .trace_bret (trace_bret), 1.292 +`endif 1.293 +`endif 1.294 +`ifdef CFG_JTAG_ENABLED 1.295 + .jtag_reg_d (jtag_reg_d), 1.296 + .jtag_reg_addr_d (jtag_reg_addr_d), 1.297 +`endif 1.298 +`ifdef CFG_USER_ENABLED 1.299 + .user_valid (user_valid), 1.300 + .user_opcode (user_opcode), 1.301 + .user_operand_0 (user_operand_0), 1.302 + .user_operand_1 (user_operand_1), 1.303 +`endif 1.304 +`ifdef CFG_IWB_ENABLED 1.305 + // Instruction Wishbone master 1.306 + .I_DAT_O (I_DAT_O), 1.307 + .I_ADR_O (I_ADR_O), 1.308 + .I_CYC_O (I_CYC_O), 1.309 + .I_SEL_O (I_SEL_O), 1.310 + .I_STB_O (I_STB_O), 1.311 + .I_WE_O (I_WE_O), 1.312 + .I_CTI_O (I_CTI_O), 1.313 + .I_LOCK_O (I_LOCK_O), 1.314 + .I_BTE_O (I_BTE_O), 1.315 + `endif 1.316 + // Data Wishbone master 1.317 + .D_DAT_O (D_DAT_O), 1.318 + .D_ADR_O (D_ADR_O), 1.319 + .D_CYC_O (D_CYC_O), 1.320 + .D_SEL_O (D_SEL_O), 1.321 + .D_STB_O (D_STB_O), 1.322 + .D_WE_O (D_WE_O), 1.323 + .D_CTI_O (D_CTI_O), 1.324 + .D_LOCK_O (D_LOCK_O), 1.325 + .D_BTE_O (D_BTE_O) 1.326 + ); 1.327 + 1.328 + wire TRACE_ACK_O; 1.329 + wire [`LM32_WORD_RNG] TRACE_DAT_O; 1.330 +`ifdef CFG_TRACE_ENABLED 1.331 + lm32_trace trace_module (.clk_i (clk_i), 1.332 + .rst_i (rst_i), 1.333 + .stb_i (DEBUG_STB_I & DEBUG_ADR_I[13]), 1.334 + .we_i (DEBUG_WE_I), 1.335 + .sel_i (DEBUG_SEL_I), 1.336 + .dat_i (DEBUG_DAT_I), 1.337 + .adr_i (DEBUG_ADR_I), 1.338 + .trace_pc (trace_pc), 1.339 + .trace_eid (trace_eid), 1.340 + .trace_eret (trace_eret), 1.341 + .trace_bret (trace_bret), 1.342 + .trace_pc_valid (trace_pc_valid), 1.343 + .trace_exception (trace_exception), 1.344 + .ack_o (TRACE_ACK_O), 1.345 + .dat_o (TRACE_DAT_O)); 1.346 +`else 1.347 + assign TRACE_ACK_O = 0; 1.348 + assign TRACE_DAT_O = 0; 1.349 +`endif 1.350 +`ifdef DEBUG_ROM 1.351 + wire ROM_ACK_O; 1.352 + wire [`LM32_WORD_RNG] ROM_DAT_O; 1.353 + 1.354 + assign DEBUG_ACK_O = DEBUG_ADR_I[13] ? TRACE_ACK_O : ROM_ACK_O; 1.355 + assign DEBUG_DAT_O = DEBUG_ADR_I[13] ? TRACE_DAT_O : ROM_DAT_O; 1.356 + 1.357 + // ROM monitor 1.358 + lm32_monitor debug_rom ( 1.359 + // ----- Inputs ------- 1.360 + .clk_i (clk_i), 1.361 + .rst_i (rst_i), 1.362 + .MON_ADR_I (DEBUG_ADR_I), 1.363 + .MON_STB_I (DEBUG_STB_I & ~DEBUG_ADR_I[13]), 1.364 + .MON_CYC_I (DEBUG_CYC_I & ~DEBUG_ADR_I[13]), 1.365 + .MON_WE_I (DEBUG_WE_I), 1.366 + .MON_SEL_I (DEBUG_SEL_I), 1.367 + .MON_DAT_I (DEBUG_DAT_I), 1.368 + .MON_CTI_I (DEBUG_CTI_I), 1.369 + .MON_BTE_I (DEBUG_BTE_I), 1.370 + .MON_LOCK_I (DEBUG_LOCK_I), 1.371 + // ----- Outputs ------ 1.372 + .MON_RTY_O (DEBUG_RTY_O), 1.373 + .MON_ERR_O (DEBUG_ERR_O), 1.374 + .MON_ACK_O (ROM_ACK_O), 1.375 + .MON_DAT_O (ROM_DAT_O) 1.376 + ); 1.377 +`endif 1.378 + 1.379 +`ifdef CFG_JTAG_ENABLED 1.380 +// JTAG cores 1.381 +jtag_cores jtag_cores ( 1.382 + // ----- Inputs ----- 1.383 +`ifdef INCLUDE_LM32 1.384 + .reg_d (jtag_reg_d), 1.385 + .reg_addr_d (jtag_reg_addr_d), 1.386 +`endif 1.387 + // ----- Outputs ----- 1.388 +`ifdef INCLUDE_LM32 1.389 + .reg_update (jtag_update), 1.390 + .reg_q (jtag_reg_q), 1.391 + .reg_addr_q (jtag_reg_addr_q), 1.392 +`endif 1.393 + .jtck (jtck), 1.394 + .jrstn (jrstn) 1.395 + ); 1.396 +`endif 1.397 + 1.398 +endmodule