IPCores/lm32_cpu / files

     1.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     1.2 +++ b/JTAGB.v	Sun Apr 04 20:40:03 2010 +0100
     1.3 @@ -0,0 +1,42 @@
     1.4 +// =============================================================================
     1.5 +//                           COPYRIGHT NOTICE
     1.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation
     1.7 +// ALL RIGHTS RESERVED
     1.8 +// This confidential and proprietary software may be used only as authorised by
     1.9 +// a licensing agreement from Lattice Semiconductor Corporation.
    1.10 +// The entire notice above must be reproduced on all authorized copies and
    1.11 +// copies may only be made to the extent permitted by a licensing agreement from
    1.12 +// Lattice Semiconductor Corporation.
    1.13 +//
    1.14 +// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
    1.15 +// 5555 NE Moore Court                            408-826-6000 (other locations)
    1.16 +// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
    1.17 +// U.S.A                                   email: techsupport@latticesemi.com
    1.18 +// =============================================================================/
    1.19 +//                         FILE DETAILS
    1.20 +// Project          : LatticeMico32
    1.21 +// File             : JTAGB.v
    1.22 +// Title            : JTAGB Black Box
    1.23 +// Dependencies     : None
    1.24 +// Version          : 6.0.14
    1.25 +//                  : Initial Release
    1.26 +// Version          : 7.0SP2, 3.0
    1.27 +//                  : No Change
    1.28 +// Version          : 3.1
    1.29 +//                  : No Change
    1.30 +// =============================================================================
    1.31 +module JTAGB (
    1.32 +         output JTCK,
    1.33 +         output JRTI1,
    1.34 +         output JRTI2,
    1.35 +         output JTDI,
    1.36 +         output JSHIFT,
    1.37 +         output JUPDATE,
    1.38 +         output JRSTN,
    1.39 +         output JCE1,
    1.40 +         output JCE2,
    1.41 +         input JTDO1,
    1.42 +         input JTDO2
    1.43 +      ) /*synthesis syn_black_box */; 
    1.44 +      
    1.45 +endmodule

     2.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     2.2 +++ b/er1.v	Sun Apr 04 20:40:03 2010 +0100
     2.3 @@ -0,0 +1,230 @@
     2.4 +// =============================================================================
     2.5 +//                           COPYRIGHT NOTICE
     2.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation
     2.7 +// ALL RIGHTS RESERVED
     2.8 +// This confidential and proprietary software may be used only as authorised by
     2.9 +// a licensing agreement from Lattice Semiconductor Corporation.
    2.10 +// The entire notice above must be reproduced on all authorized copies and
    2.11 +// copies may only be made to the extent permitted by a licensing agreement from
    2.12 +// Lattice Semiconductor Corporation.
    2.13 +//
    2.14 +// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
    2.15 +// 5555 NE Moore Court                            408-826-6000 (other locations)
    2.16 +// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
    2.17 +// U.S.A                                   email: techsupport@latticesemi.com
    2.18 +// =============================================================================/
    2.19 +//                         FILE DETAILS
    2.20 +// Project          : LatticeMico32
    2.21 +// File             : er1.v
    2.22 +// Description:
    2.23 +//    This module is where the ER1 register implemented. ER1 and ER2 registers
    2.24 +//    can be registers implemented in Lattice FPGAs using normal FPGA's
    2.25 +//    programmable logic resources.  Once they are implemented, they can be
    2.26 +//    accessed as if they are JTAG data registers through the FPGA JTAG port.
    2.27 +//    In order to accessing these registers, JTAG instructions ER1(0x32) or
    2.28 +//    ER2(0x38) needs to be written to the JTAG IR register for enabling the
    2.29 +//    ER1/ER2 accessing logic.  The ER1 or ER2 accessing logic can only be
    2.30 +//    enabled one at a time.  Once they are enabled, they will be disabled if
    2.31 +//    another JTAG instruction is written into the JTAG instruction register.
    2.32 +//    The registers allow dynamically accessing the FPGA internal information
    2.33 +//    even when the device is running.  Therefore, they are very useful for some
    2.34 +//    of the IP cores.  In order to let ER1/ER2 registers shared by multiple IP
    2.35 +//    cores or other designs, there is a ER1/ER2 structure patterned by Lattice.
    2.36 +//    The ER1/ER2 structure allows only one ER1 register but more than one ER2
    2.37 +//    registers in an FPGA device.  Please refer to the related document for
    2.38 +//    this patterned ER1/ER2 structure.
    2.39 +// Dependencies     : None
    2.40 +// Version          : 6.0.14
    2.41 +//                  : Initial Version
    2.42 +// Version          : 7.0SP2, 3.0
    2.43 +//                  : No Change
    2.44 +// Version          : 3.1
    2.45 +//                  : No Change
    2.46 +// =============================================================================
    2.47 +module ER1 (input  JTCK,
    2.48 +	    input  JTDI,
    2.49 +	    output JTDO1,
    2.50 +	    output reg JTDO2,
    2.51 +	    input  JSHIFT,
    2.52 +	    input  JUPDATE,
    2.53 +	    input  JRSTN,
    2.54 +	    input  JCE1,
    2.55 +	    input [14:0] ER2_TDO,
    2.56 +	    output reg [14:0] IP_ENABLE,
    2.57 +	    input  ISPTRACY_ER2_TDO,
    2.58 +	    output ISPTRACY_ENABLE,
    2.59 +	    output CONTROL_DATAN)/* synthesis syn_hier = hard */;
    2.60 +
    2.61 +
    2.62 +   wire 	   controlDataNBit;
    2.63 +   wire 	   ispTracyEnableBit;
    2.64 +   wire [3:0] 	   encodedIpEnableBits;
    2.65 +   wire [9:0] 	   er1TdiBit;
    2.66 +   wire 	   captureDrER1;
    2.67 +   
    2.68 +
    2.69 +   assign 	   JTDO1 = er1TdiBit[0];
    2.70 +   
    2.71 +   TYPEB BIT0 (.CLK(JTCK),
    2.72 +	       .RESET_N(JRSTN),
    2.73 +	       .CLKEN(JCE1),
    2.74 +	       .TDI(er1TdiBit[1]),
    2.75 +	       .TDO(er1TdiBit[0]),
    2.76 +	       .DATA_IN(1'b0),
    2.77 +	       .CAPTURE_DR(captureDrER1));
    2.78 +
    2.79 +   TYPEB BIT1 (.CLK(JTCK),
    2.80 +	       .RESET_N(JRSTN),
    2.81 +	       .CLKEN(JCE1),
    2.82 +	       .TDI(er1TdiBit[2]),
    2.83 +	       .TDO(er1TdiBit[1]),
    2.84 +	       .DATA_IN(1'b0),
    2.85 +	       .CAPTURE_DR(captureDrER1));
    2.86 +
    2.87 +   TYPEB BIT2 (.CLK(JTCK),
    2.88 +	       .RESET_N(JRSTN),
    2.89 +	       .CLKEN(JCE1),
    2.90 +	       .TDI(er1TdiBit[3]),
    2.91 +	       .TDO(er1TdiBit[2]),
    2.92 +	       .DATA_IN(1'b1),
    2.93 +	       .CAPTURE_DR(captureDrER1));
    2.94 +   
    2.95 +   TYPEA BIT3 (.CLK(JTCK),
    2.96 +	       .RESET_N(JRSTN),
    2.97 +	       .CLKEN(JCE1),
    2.98 +	       .TDI(er1TdiBit[4]),
    2.99 +	       .TDO(er1TdiBit[3]),
   2.100 +	       .DATA_OUT(controlDataNBit),
   2.101 +	       .DATA_IN(controlDataNBit),
   2.102 +	       .CAPTURE_DR(captureDrER1),
   2.103 +	       .UPDATE_DR(JUPDATE));
   2.104 +
   2.105 +   assign CONTROL_DATAN = controlDataNBit;
   2.106 +
   2.107 +   TYPEA BIT4 (.CLK(JTCK),
   2.108 +	       .RESET_N(JRSTN),
   2.109 +	       .CLKEN(JCE1),
   2.110 +	       .TDI(er1TdiBit[5]),
   2.111 +	       .TDO(er1TdiBit[4]),
   2.112 +	       .DATA_OUT(ispTracyEnableBit),
   2.113 +	       .DATA_IN(ispTracyEnableBit),
   2.114 +	       .CAPTURE_DR(captureDrER1),
   2.115 +	       .UPDATE_DR(JUPDATE)
   2.116 +	       );
   2.117 +
   2.118 +   assign ISPTRACY_ENABLE = ispTracyEnableBit;
   2.119 +
   2.120 +   TYPEA BIT5 (.CLK(JTCK),
   2.121 +	       .RESET_N(JRSTN),
   2.122 +	       .CLKEN(JCE1),
   2.123 +	       .TDI(er1TdiBit[6]),
   2.124 +	       .TDO(er1TdiBit[5]),
   2.125 +	       .DATA_OUT(encodedIpEnableBits[0]),
   2.126 +	       .DATA_IN(encodedIpEnableBits[0]),
   2.127 +	       .CAPTURE_DR(captureDrER1),
   2.128 +	       .UPDATE_DR(JUPDATE));
   2.129 +   
   2.130 +   TYPEA BIT6 (.CLK(JTCK),
   2.131 +	       .RESET_N(JRSTN),
   2.132 +	       .CLKEN(JCE1),
   2.133 +	       .TDI(er1TdiBit[7]),
   2.134 +	       .TDO(er1TdiBit[6]),
   2.135 +	       .DATA_OUT(encodedIpEnableBits[1]),
   2.136 +	       .DATA_IN(encodedIpEnableBits[1]),
   2.137 +	       .CAPTURE_DR(captureDrER1),
   2.138 +	       .UPDATE_DR(JUPDATE));
   2.139 +   
   2.140 +   TYPEA BIT7 (.CLK(JTCK),
   2.141 +	       .RESET_N(JRSTN),
   2.142 +	       .CLKEN(JCE1),
   2.143 +	       .TDI(er1TdiBit[8]),
   2.144 +	       .TDO(er1TdiBit[7]),
   2.145 +	       .DATA_OUT(encodedIpEnableBits[2]),
   2.146 +	       .DATA_IN(encodedIpEnableBits[2]),
   2.147 +	       .CAPTURE_DR(captureDrER1),
   2.148 +	       .UPDATE_DR(JUPDATE));
   2.149 +   
   2.150 +   TYPEA BIT8 (.CLK(JTCK),
   2.151 +	       .RESET_N(JRSTN),
   2.152 +	       .CLKEN(JCE1),
   2.153 +	       .TDI(er1TdiBit[9]),
   2.154 +	       .TDO(er1TdiBit[8]),
   2.155 +	       .DATA_OUT(encodedIpEnableBits[3]),
   2.156 +	       .DATA_IN(encodedIpEnableBits[3]),
   2.157 +	       .CAPTURE_DR(captureDrER1),
   2.158 +	       .UPDATE_DR(JUPDATE)
   2.159 +	       );
   2.160 +   
   2.161 +   assign er1TdiBit[9] = JTDI;
   2.162 +   assign captureDrER1  = !JSHIFT & JCE1;
   2.163 +   
   2.164 +   always @ (encodedIpEnableBits,ISPTRACY_ER2_TDO, ER2_TDO)
   2.165 +   begin
   2.166 +    case (encodedIpEnableBits)
   2.167 +      4'h0: begin 
   2.168 +      		IP_ENABLE <= 15'b000000000000000;
   2.169 +      		JTDO2 <= ISPTRACY_ER2_TDO;
   2.170 +      	    end
   2.171 +      4'h1: begin
   2.172 +      		IP_ENABLE <= 15'b000000000000001;
   2.173 +      		JTDO2 <= ER2_TDO[0];
   2.174 +      	    end	
   2.175 +      4'h2: begin
   2.176 +      		IP_ENABLE <= 15'b000000000000010;
   2.177 +      		JTDO2 <= ER2_TDO[1];
   2.178 +      	    end
   2.179 +      4'h3: begin
   2.180 +      		IP_ENABLE <= 15'b000000000000100;
   2.181 +      		JTDO2 <= ER2_TDO[2];
   2.182 +      	    end
   2.183 +      4'h4: begin
   2.184 +      		IP_ENABLE <= 15'b000000000001000;
   2.185 +      		JTDO2 <= ER2_TDO[3];
   2.186 +      	    end
   2.187 +      4'h5: begin
   2.188 +      		IP_ENABLE <= 15'b000000000010000;
   2.189 +      		JTDO2 <= ER2_TDO[4];
   2.190 +      	    end
   2.191 +      4'h6: begin
   2.192 +      		IP_ENABLE <= 15'b000000000100000;
   2.193 +      		JTDO2 <= ER2_TDO[5];
   2.194 +      	    end
   2.195 +      4'h7: begin
   2.196 +      		IP_ENABLE <= 15'b000000001000000;
   2.197 +      		JTDO2 <= ER2_TDO[6];
   2.198 +      	    end
   2.199 +      4'h8: begin
   2.200 +      		IP_ENABLE <= 15'b000000010000000;
   2.201 +      		JTDO2 <= ER2_TDO[7];
   2.202 +      	    end
   2.203 +      4'h9: begin
   2.204 +      		IP_ENABLE <= 15'b000000100000000;
   2.205 +      		JTDO2 <= ER2_TDO[8];
   2.206 +      	    end
   2.207 +      4'hA: begin
   2.208 +      		IP_ENABLE <= 15'b000001000000000;
   2.209 +      		JTDO2 <= ER2_TDO[9];
   2.210 +      	    end
   2.211 +      4'hB: begin
   2.212 +      		IP_ENABLE <= 15'b000010000000000;
   2.213 +      		JTDO2 <= ER2_TDO[10];
   2.214 +      	    end
   2.215 +      4'hC: begin
   2.216 +      		IP_ENABLE <= 15'b000100000000000;
   2.217 +      		JTDO2 <= ER2_TDO[11];
   2.218 +      	    end
   2.219 +      4'hD: begin
   2.220 +      		IP_ENABLE <= 15'b001000000000000;
   2.221 +      		JTDO2 <= ER2_TDO[12];
   2.222 +      	    end
   2.223 +      4'hE: begin
   2.224 +      		IP_ENABLE <= 15'b010000000000000;
   2.225 +      		JTDO2 <= ER2_TDO[13];
   2.226 +      	    end
   2.227 +      4'hF: begin
   2.228 +      		IP_ENABLE <= 15'b100000000000000;
   2.229 +      		JTDO2 <= ER2_TDO[14];
   2.230 +      	    end
   2.231 +    endcase
   2.232 +  end
   2.233 +endmodule

     3.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     3.2 +++ b/jtag_cores.v	Sun Apr 04 20:40:03 2010 +0100
     3.3 @@ -0,0 +1,125 @@
     3.4 +// ============================================================================
     3.5 +//                           COPYRIGHT NOTICE
     3.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation
     3.7 +// ALL RIGHTS RESERVED
     3.8 +// This confidential and proprietary software may be used only as authorised by
     3.9 +// a licensing agreement from Lattice Semiconductor Corporation.
    3.10 +// The entire notice above must be reproduced on all authorized copies and
    3.11 +// copies may only be made to the extent permitted by a licensing agreement from
    3.12 +// Lattice Semiconductor Corporation.
    3.13 +//
    3.14 +// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
    3.15 +// 5555 NE Moore Court                            408-826-6000 (other locations)
    3.16 +// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
    3.17 +// U.S.A                                   email: techsupport@latticesemi.com
    3.18 +// ============================================================================/
    3.19 +//                         FILE DETAILS
    3.20 +// Project          : LatticeMico32
    3.21 +// File             : jtag_cores.v
    3.22 +// Title            : Instantiates all IP cores on JTAG chain.
    3.23 +// Dependencies     : system_conf.v
    3.24 +// Version          : 6.0.14
    3.25 +//                  : modified to use jtagconn for LM32,
    3.26 +//                  : all technologies 7/10/07
    3.27 +// Version          : 7.0SP2, 3.0
    3.28 +//                  : No Change
    3.29 +// Version          : 3.1
    3.30 +//                  : No Change
    3.31 +// ============================================================================
    3.32 +
    3.33 +`include "system_conf.v"
    3.34 +
    3.35 +/////////////////////////////////////////////////////
    3.36 +// jtagconn16 Module Definition
    3.37 +/////////////////////////////////////////////////////
    3.38 +
    3.39 +module jtagconn16 (er2_tdo, jtck, jtdi, jshift, jupdate, jrstn, jce2, ip_enable) ;
    3.40 +    input  er2_tdo ; 
    3.41 +    output jtck ; 
    3.42 +    output jtdi ; 
    3.43 +    output jshift ; 
    3.44 +    output jupdate ; 
    3.45 +    output jrstn ; 
    3.46 +    output jce2 ; 
    3.47 +    output ip_enable ; 
    3.48 +endmodule
    3.49 +
    3.50 +/////////////////////////////////////////////////////
    3.51 +// Module interface
    3.52 +/////////////////////////////////////////////////////
    3.53 +
    3.54 +(* syn_hier="hard" *) module jtag_cores (
    3.55 +    // ----- Inputs -------
    3.56 +    reg_d,
    3.57 +    reg_addr_d,
    3.58 +    // ----- Outputs -------    
    3.59 +    reg_update,
    3.60 +    reg_q,
    3.61 +    reg_addr_q,
    3.62 +    jtck,
    3.63 +    jrstn
    3.64 +    );
    3.65 +    
    3.66 +/////////////////////////////////////////////////////
    3.67 +// Inputs
    3.68 +/////////////////////////////////////////////////////
    3.69 +
    3.70 +input [7:0] reg_d;
    3.71 +input [2:0] reg_addr_d;
    3.72 +
    3.73 +/////////////////////////////////////////////////////
    3.74 +// Outputs
    3.75 +/////////////////////////////////////////////////////
    3.76 +   
    3.77 +output reg_update;
    3.78 +wire   reg_update;
    3.79 +output [7:0] reg_q;
    3.80 +wire   [7:0] reg_q;
    3.81 +output [2:0] reg_addr_q;
    3.82 +wire   [2:0] reg_addr_q;
    3.83 +
    3.84 +output jtck;
    3.85 +wire   jtck; 	/* synthesis syn_keep=1 */
    3.86 +output jrstn;
    3.87 +wire   jrstn;  /* synthesis syn_keep=1 */	
    3.88 +
    3.89 +/////////////////////////////////////////////////////
    3.90 +// Instantiations
    3.91 +/////////////////////////////////////////////////////
    3.92 +
    3.93 +wire jtdi;          /* synthesis syn_keep=1 */
    3.94 +wire er2_tdo2;      /* synthesis syn_keep=1 */
    3.95 +wire jshift;        /* synthesis syn_keep=1 */
    3.96 +wire jupdate;       /* synthesis syn_keep=1 */
    3.97 +wire jce2;          /* synthesis syn_keep=1 */
    3.98 +wire ip_enable;     /* synthesis syn_keep=1 */
    3.99 +    
   3.100 +(* JTAG_IP="LM32", IP_ID="0", HUB_ID="0", syn_noprune=1 *) jtagconn16 jtagconn16_lm32_inst (
   3.101 +    .er2_tdo        (er2_tdo2),
   3.102 +    .jtck           (jtck),
   3.103 +    .jtdi           (jtdi),
   3.104 +    .jshift         (jshift),
   3.105 +    .jupdate        (jupdate),
   3.106 +    .jrstn          (jrstn),
   3.107 +    .jce2           (jce2),
   3.108 +    .ip_enable      (ip_enable)
   3.109 +);
   3.110 +    
   3.111 +(* syn_noprune=1 *) jtag_lm32 jtag_lm32_inst (
   3.112 +    .JTCK           (jtck),
   3.113 +    .JTDI           (jtdi),
   3.114 +    .JTDO2          (er2_tdo2),
   3.115 +    .JSHIFT         (jshift),
   3.116 +    .JUPDATE        (jupdate),
   3.117 +    .JRSTN          (jrstn),
   3.118 +    .JCE2           (jce2),
   3.119 +    .JTAGREG_ENABLE (ip_enable),
   3.120 +    .CONTROL_DATAN  (),
   3.121 +    .REG_UPDATE     (reg_update),
   3.122 +    .REG_D          (reg_d),
   3.123 +    .REG_ADDR_D     (reg_addr_d),
   3.124 +    .REG_Q          (reg_q),
   3.125 +    .REG_ADDR_Q     (reg_addr_q)
   3.126 +    );
   3.127 +    
   3.128 +endmodule

     4.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     4.2 +++ b/jtag_lm32.v	Sun Apr 04 20:40:03 2010 +0100
     4.3 @@ -0,0 +1,200 @@
     4.4 +// =============================================================================
     4.5 +//                           COPYRIGHT NOTICE
     4.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation
     4.7 +// ALL RIGHTS RESERVED
     4.8 +// This confidential and proprietary software may be used only as authorised by
     4.9 +// a licensing agreement from Lattice Semiconductor Corporation.
    4.10 +// The entire notice above must be reproduced on all authorized copies and
    4.11 +// copies may only be made to the extent permitted by a licensing agreement from
    4.12 +// Lattice Semiconductor Corporation.
    4.13 +//
    4.14 +// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
    4.15 +// 5555 NE Moore Court                            408-826-6000 (other locations)
    4.16 +// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
    4.17 +// U.S.A                                   email: techsupport@latticesemi.com
    4.18 +// =============================================================================/
    4.19 +//                         FILE DETAILS
    4.20 +// Project          : LatticeMico32
    4.21 +// File             : jtag_lm32.v
    4.22 +// Title            : JTAG data register for LM32 CPU debug interface
    4.23 +// Version          : 6.0.13
    4.24 +//                  : Initial Release
    4.25 +// Version          : 7.0SP2, 3.0
    4.26 +//                  : No Change
    4.27 +// Version          : 3.1
    4.28 +//                  : No Change
    4.29 +// =============================================================================
    4.30 +
    4.31 +/////////////////////////////////////////////////////
    4.32 +// Module interface
    4.33 +/////////////////////////////////////////////////////
    4.34 +
    4.35 +module jtag_lm32 (
    4.36 +	input JTCK,
    4.37 +	input JTDI,
    4.38 +	output JTDO2,
    4.39 +	input JSHIFT,
    4.40 +	input JUPDATE,
    4.41 +	input JRSTN,
    4.42 +	input JCE2,
    4.43 +	input JTAGREG_ENABLE,
    4.44 +	input CONTROL_DATAN,
    4.45 +	output REG_UPDATE,
    4.46 +	input [7:0] REG_D,
    4.47 +	input [2:0] REG_ADDR_D,
    4.48 +	output [7:0] REG_Q,
    4.49 +	output [2:0] REG_ADDR_Q
    4.50 +	);
    4.51 +
    4.52 +/////////////////////////////////////////////////////
    4.53 +// Internal nets and registers 
    4.54 +/////////////////////////////////////////////////////
    4.55 +
    4.56 +wire [9:0] tdibus;
    4.57 +
    4.58 +/////////////////////////////////////////////////////
    4.59 +// Instantiations
    4.60 +/////////////////////////////////////////////////////
    4.61 +   
    4.62 +TYPEA DATA_BIT0 (
    4.63 +    .CLK(JTCK),
    4.64 +    .RESET_N(JRSTN),
    4.65 +    .CLKEN(clk_enable),
    4.66 +    .TDI(JTDI),
    4.67 +    .TDO(tdibus[0]),
    4.68 +    .DATA_OUT(REG_Q[0]),
    4.69 +    .DATA_IN(REG_D[0]),
    4.70 +    .CAPTURE_DR(captureDr),
    4.71 +    .UPDATE_DR(JUPDATE)
    4.72 +    );
    4.73 +
    4.74 +TYPEA DATA_BIT1 (
    4.75 +    .CLK(JTCK),
    4.76 +    .RESET_N(JRSTN),
    4.77 +    .CLKEN(clk_enable),
    4.78 +    .TDI(tdibus[0]),
    4.79 +    .TDO(tdibus[1]),
    4.80 +    .DATA_OUT(REG_Q[1]),
    4.81 +    .DATA_IN(REG_D[1]),
    4.82 +    .CAPTURE_DR(captureDr),
    4.83 +    .UPDATE_DR(JUPDATE)
    4.84 +    );
    4.85 +
    4.86 +TYPEA DATA_BIT2 (
    4.87 +    .CLK(JTCK),
    4.88 +    .RESET_N(JRSTN),
    4.89 +    .CLKEN(clk_enable),
    4.90 +    .TDI(tdibus[1]),
    4.91 +    .TDO(tdibus[2]),
    4.92 +    .DATA_OUT(REG_Q[2]),
    4.93 +    .DATA_IN(REG_D[2]),
    4.94 +    .CAPTURE_DR(captureDr),
    4.95 +    .UPDATE_DR(JUPDATE)
    4.96 +    );
    4.97 +
    4.98 +TYPEA DATA_BIT3 (
    4.99 +    .CLK(JTCK),
   4.100 +    .RESET_N(JRSTN),
   4.101 +    .CLKEN(clk_enable),
   4.102 +    .TDI(tdibus[2]),
   4.103 +    .TDO(tdibus[3]),
   4.104 +    .DATA_OUT(REG_Q[3]),
   4.105 +    .DATA_IN(REG_D[3]),
   4.106 +    .CAPTURE_DR(captureDr),
   4.107 +    .UPDATE_DR(JUPDATE)
   4.108 +    );
   4.109 +
   4.110 +TYPEA DATA_BIT4 (
   4.111 +    .CLK(JTCK),
   4.112 +    .RESET_N(JRSTN),
   4.113 +    .CLKEN(clk_enable),
   4.114 +    .TDI(tdibus[3]),
   4.115 +    .TDO(tdibus[4]),
   4.116 +    .DATA_OUT(REG_Q[4]),
   4.117 +    .DATA_IN(REG_D[4]),
   4.118 +    .CAPTURE_DR(captureDr),
   4.119 +    .UPDATE_DR(JUPDATE)
   4.120 +    );
   4.121 +
   4.122 +TYPEA DATA_BIT5 (
   4.123 +    .CLK(JTCK),
   4.124 +    .RESET_N(JRSTN),
   4.125 +    .CLKEN(clk_enable),
   4.126 +    .TDI(tdibus[4]),
   4.127 +    .TDO(tdibus[5]),
   4.128 +    .DATA_OUT(REG_Q[5]),
   4.129 +    .DATA_IN(REG_D[5]),
   4.130 +    .CAPTURE_DR(captureDr),
   4.131 +    .UPDATE_DR(JUPDATE)
   4.132 +    );
   4.133 +
   4.134 +TYPEA DATA_BIT6 (
   4.135 +    .CLK(JTCK),
   4.136 +    .RESET_N(JRSTN),
   4.137 +    .CLKEN(clk_enable),
   4.138 +    .TDI(tdibus[5]),
   4.139 +    .TDO(tdibus[6]),
   4.140 +    .DATA_OUT(REG_Q[6]),
   4.141 +    .DATA_IN(REG_D[6]),
   4.142 +    .CAPTURE_DR(captureDr),
   4.143 +    .UPDATE_DR(JUPDATE)
   4.144 +    );
   4.145 +
   4.146 +TYPEA DATA_BIT7 (
   4.147 +    .CLK(JTCK),
   4.148 +    .RESET_N(JRSTN),
   4.149 +    .CLKEN(clk_enable),
   4.150 +    .TDI(tdibus[6]),
   4.151 +    .TDO(tdibus[7]),
   4.152 +    .DATA_OUT(REG_Q[7]),
   4.153 +    .DATA_IN(REG_D[7]),
   4.154 +    .CAPTURE_DR(captureDr),
   4.155 +    .UPDATE_DR(JUPDATE)
   4.156 +    );
   4.157 +
   4.158 +TYPEA ADDR_BIT0 (
   4.159 +    .CLK(JTCK),
   4.160 +    .RESET_N(JRSTN),
   4.161 +    .CLKEN(clk_enable),
   4.162 +    .TDI(tdibus[7]),
   4.163 +    .TDO(tdibus[8]),
   4.164 +    .DATA_OUT(REG_ADDR_Q[0]),
   4.165 +    .DATA_IN(REG_ADDR_D[0]),
   4.166 +    .CAPTURE_DR(captureDr),
   4.167 +    .UPDATE_DR(JUPDATE)
   4.168 +    );
   4.169 +
   4.170 +TYPEA ADDR_BIT1 (
   4.171 +    .CLK(JTCK),
   4.172 +    .RESET_N(JRSTN),
   4.173 +    .CLKEN(clk_enable),
   4.174 +    .TDI(tdibus[8]),
   4.175 +    .TDO(tdibus[9]),
   4.176 +    .DATA_OUT(REG_ADDR_Q[1]),
   4.177 +    .DATA_IN(REG_ADDR_D[1]),
   4.178 +    .CAPTURE_DR(captureDr),
   4.179 +    .UPDATE_DR(JUPDATE)
   4.180 +    );
   4.181 +
   4.182 +TYPEA ADDR_BIT2 (
   4.183 +    .CLK(JTCK),
   4.184 +    .RESET_N(JRSTN),
   4.185 +    .CLKEN(clk_enable),
   4.186 +    .TDI(tdibus[9]),
   4.187 +    .TDO(JTDO2),
   4.188 +    .DATA_OUT(REG_ADDR_Q[2]),
   4.189 +    .DATA_IN(REG_ADDR_D[2]),
   4.190 +    .CAPTURE_DR(captureDr),
   4.191 +    .UPDATE_DR(JUPDATE)
   4.192 +    );
   4.193 +
   4.194 +/////////////////////////////////////////////////////
   4.195 +// Combinational logic
   4.196 +/////////////////////////////////////////////////////
   4.197 +
   4.198 +assign clk_enable = JTAGREG_ENABLE & JCE2;
   4.199 +assign captureDr = !JSHIFT & JCE2;
   4.200 +// JCE2 is only active during shift
   4.201 +assign REG_UPDATE = JTAGREG_ENABLE & JUPDATE;
   4.202 + 
   4.203 +endmodule

     5.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     5.2 +++ b/lm32_adder.v	Sun Apr 04 20:40:03 2010 +0100
     5.3 @@ -0,0 +1,115 @@
     5.4 +// =============================================================================
     5.5 +//                           COPYRIGHT NOTICE
     5.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation
     5.7 +// ALL RIGHTS RESERVED
     5.8 +// This confidential and proprietary software may be used only as authorised by
     5.9 +// a licensing agreement from Lattice Semiconductor Corporation.
    5.10 +// The entire notice above must be reproduced on all authorized copies and
    5.11 +// copies may only be made to the extent permitted by a licensing agreement from
    5.12 +// Lattice Semiconductor Corporation.
    5.13 +//
    5.14 +// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
    5.15 +// 5555 NE Moore Court                            408-826-6000 (other locations)
    5.16 +// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
    5.17 +// U.S.A                                   email: techsupport@latticesemi.com
    5.18 +// ============================================================================/
    5.19 +//                         FILE DETAILS
    5.20 +// Project          : LatticeMico32
    5.21 +// File             : lm32_adder.v
    5.22 +// Title            : Integer adder / subtractor with comparison flag generation 
    5.23 +// Dependencies     : lm32_include.v
    5.24 +// Version          : 6.1.17
    5.25 +//                  : Initial Release
    5.26 +// Version          : 7.0SP2, 3.0
    5.27 +//                  : No Change
    5.28 +// Version          : 3.1
    5.29 +//                  : No Change
    5.30 +// =============================================================================
    5.31 +
    5.32 +`include "lm32_include.v"
    5.33 +
    5.34 +/////////////////////////////////////////////////////
    5.35 +// Module interface
    5.36 +/////////////////////////////////////////////////////
    5.37 +
    5.38 +module lm32_adder (
    5.39 +    // ----- Inputs -------
    5.40 +    adder_op_x,
    5.41 +    adder_op_x_n,
    5.42 +    operand_0_x,
    5.43 +    operand_1_x,
    5.44 +    // ----- Outputs -------
    5.45 +    adder_result_x,
    5.46 +    adder_carry_n_x,
    5.47 +    adder_overflow_x
    5.48 +    );
    5.49 +
    5.50 +/////////////////////////////////////////////////////
    5.51 +// Inputs
    5.52 +/////////////////////////////////////////////////////
    5.53 +
    5.54 +input adder_op_x;                                       // Operating to perform, 0 for addition, 1 for subtraction
    5.55 +input adder_op_x_n;                                     // Inverted version of adder_op_x
    5.56 +input [`LM32_WORD_RNG] operand_0_x;                     // Operand to add, or subtract from
    5.57 +input [`LM32_WORD_RNG] operand_1_x;                     // Opearnd to add, or subtract by
    5.58 +
    5.59 +/////////////////////////////////////////////////////
    5.60 +// Outputs
    5.61 +/////////////////////////////////////////////////////
    5.62 +
    5.63 +output [`LM32_WORD_RNG] adder_result_x;                 // Result of addition or subtraction
    5.64 +wire   [`LM32_WORD_RNG] adder_result_x;
    5.65 +output adder_carry_n_x;                                 // Inverted carry
    5.66 +wire   adder_carry_n_x;
    5.67 +output adder_overflow_x;                                // Indicates if overflow occured, only valid for subtractions
    5.68 +reg    adder_overflow_x;
    5.69 +    
    5.70 +/////////////////////////////////////////////////////
    5.71 +// Internal nets and registers 
    5.72 +/////////////////////////////////////////////////////
    5.73 +
    5.74 +wire a_sign;                                            // Sign (i.e. positive or negative) of operand 0
    5.75 +wire b_sign;                                            // Sign of operand 1
    5.76 +wire result_sign;                                       // Sign of result
    5.77 +
    5.78 +/////////////////////////////////////////////////////
    5.79 +// Instantiations 
    5.80 +/////////////////////////////////////////////////////
    5.81 +
    5.82 +lm32_addsub addsub (
    5.83 +    // ----- Inputs -----
    5.84 +    .DataA          (operand_0_x), 
    5.85 +    .DataB          (operand_1_x), 
    5.86 +    .Cin            (adder_op_x), 
    5.87 +    .Add_Sub        (adder_op_x_n), 
    5.88 +    // ----- Ouputs -----
    5.89 +    .Result         (adder_result_x), 
    5.90 +    .Cout           (adder_carry_n_x)
    5.91 +    );
    5.92 +
    5.93 +/////////////////////////////////////////////////////
    5.94 +// Combinational Logic
    5.95 +/////////////////////////////////////////////////////
    5.96 +
    5.97 +// Extract signs of operands and result
    5.98 +
    5.99 +assign a_sign = operand_0_x[`LM32_WORD_WIDTH-1];
   5.100 +assign b_sign = operand_1_x[`LM32_WORD_WIDTH-1];
   5.101 +assign result_sign = adder_result_x[`LM32_WORD_WIDTH-1];
   5.102 +
   5.103 +// Determine whether an overflow occured when performing a subtraction
   5.104 +
   5.105 +always @(*)
   5.106 +begin    
   5.107 +    //  +ve - -ve = -ve -> overflow
   5.108 +    //  -ve - +ve = +ve -> overflow
   5.109 +    if  (   (!a_sign & b_sign & result_sign)
   5.110 +         || (a_sign & !b_sign & !result_sign)
   5.111 +        )
   5.112 +        adder_overflow_x = `TRUE;
   5.113 +    else
   5.114 +        adder_overflow_x = `FALSE;
   5.115 +end
   5.116 +    
   5.117 +endmodule
   5.118 +

     6.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     6.2 +++ b/lm32_addsub.v	Sun Apr 04 20:40:03 2010 +0100
     6.3 @@ -0,0 +1,93 @@
     6.4 +// =============================================================================
     6.5 +//                           COPYRIGHT NOTICE
     6.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation
     6.7 +// ALL RIGHTS RESERVED
     6.8 +// This confidential and proprietary software may be used only as authorised by
     6.9 +// a licensing agreement from Lattice Semiconductor Corporation.
    6.10 +// The entire notice above must be reproduced on all authorized copies and
    6.11 +// copies may only be made to the extent permitted by a licensing agreement from
    6.12 +// Lattice Semiconductor Corporation.
    6.13 +//
    6.14 +// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
    6.15 +// 5555 NE Moore Court                            408-826-6000 (other locations)
    6.16 +// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
    6.17 +// U.S.A                                   email: techsupport@latticesemi.com
    6.18 +// =============================================================================/
    6.19 +//                         FILE DETAILS
    6.20 +// Project          : LatticeMico32
    6.21 +// File             : lm32_addsub.v
    6.22 +// Title            : PMI adder/subtractor.
    6.23 +// Version          : 6.1.17
    6.24 +//                  : Initial Release
    6.25 +// Version          : 7.0SP2, 3.0
    6.26 +//                  : No Change
    6.27 +// Version          : 3.1
    6.28 +//                  : No Change
    6.29 +// =============================================================================
    6.30 +
    6.31 +`include "lm32_include.v"
    6.32 +
    6.33 +/////////////////////////////////////////////////////
    6.34 +// Module interface
    6.35 +/////////////////////////////////////////////////////
    6.36 +
    6.37 +module lm32_addsub (
    6.38 +    // ----- Inputs -------
    6.39 +    DataA, 
    6.40 +    DataB, 
    6.41 +    Cin, 
    6.42 +    Add_Sub, 
    6.43 +    // ----- Outputs -------
    6.44 +    Result, 
    6.45 +    Cout
    6.46 +    );
    6.47 +
    6.48 +/////////////////////////////////////////////////////
    6.49 +// Inputs
    6.50 +/////////////////////////////////////////////////////
    6.51 +
    6.52 +input [31:0] DataA;
    6.53 +input [31:0] DataB;
    6.54 +input Cin;
    6.55 +input Add_Sub;
    6.56 +
    6.57 +/////////////////////////////////////////////////////
    6.58 +// Outputs
    6.59 +/////////////////////////////////////////////////////
    6.60 +
    6.61 +output [31:0] Result;
    6.62 +wire   [31:0] Result;
    6.63 +output Cout;
    6.64 +wire   Cout;
    6.65 +
    6.66 +/////////////////////////////////////////////////////
    6.67 +// Instantiations
    6.68 +///////////////////////////////////////////////////// 
    6.69 +
    6.70 +       generate
    6.71 +	  if (`LATTICE_FAMILY == "SC" || `LATTICE_FAMILY == "SCM") begin
    6.72 +	     wire [32:0] tmp_addResult = DataA + DataB + Cin;
    6.73 +	     wire [32:0] tmp_subResult = DataA - DataB - !Cin;   
    6.74 +   
    6.75 +	     assign  Result = (Add_Sub == 1) ? tmp_addResult[31:0] : tmp_subResult[31:0];
    6.76 +	     assign  Cout = (Add_Sub == 1) ? tmp_addResult[32] : !tmp_subResult[32];
    6.77 +	  end else begin
    6.78 +	    pmi_addsub #(// ----- Parameters -------
    6.79 +			 .pmi_data_width     (32),
    6.80 +			 .pmi_result_width   (32),
    6.81 +			 .pmi_sign           ("off"),
    6.82 +			 .pmi_family         (`LATTICE_FAMILY),
    6.83 +			 .module_type        ("pmi_addsub")) 
    6.84 +	      addsub    (// ----- Inputs -------
    6.85 +			 .DataA              (DataA),
    6.86 +			 .DataB              (DataB),
    6.87 +			 .Cin                (Cin),
    6.88 +			 .Add_Sub            (Add_Sub),
    6.89 +			 // ----- Outputs -------
    6.90 +			 .Result             (Result),
    6.91 +			 .Cout               (Cout),
    6.92 +			 .Overflow           ());
    6.93 +	  end
    6.94 +       endgenerate 
    6.95 +
    6.96 +endmodule

     7.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     7.2 +++ b/lm32_cpu.v	Sun Apr 04 20:40:03 2010 +0100
     7.3 @@ -0,0 +1,2732 @@
     7.4 +// =============================================================================
     7.5 +//                           COPYRIGHT NOTICE
     7.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation
     7.7 +// ALL RIGHTS RESERVED
     7.8 +// This confidential and proprietary software may be used only as authorised by
     7.9 +// a licensing agreement from Lattice Semiconductor Corporation.
    7.10 +// The entire notice above must be reproduced on all authorized copies and
    7.11 +// copies may only be made to the extent permitted by a licensing agreement from
    7.12 +// Lattice Semiconductor Corporation.
    7.13 +//
    7.14 +// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
    7.15 +// 5555 NE Moore Court                            408-826-6000 (other locations)
    7.16 +// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
    7.17 +// U.S.A                                   email: techsupport@latticesemi.com
    7.18 +// =============================================================================/
    7.19 +//                         FILE DETAILS
    7.20 +// Project          : LatticeMico32
    7.21 +// File             : lm32_cpu.v
    7.22 +// Title            : Top-level of CPU.
    7.23 +// Dependencies     : lm32_include.v
    7.24 +//
    7.25 +// Version 3.4
    7.26 +// 1. Bug Fix: In a tight infinite loop (add, sw, bi) incoming interrupts were 
    7.27 +//    never serviced.
    7.28 +//    
    7.29 +// Version 3.3
    7.30 +// 1. Feature: Support for memory that is tightly coupled to processor core, and 
    7.31 +//    has a single-cycle access latency (same as caches). Instruction port has
    7.32 +//    access to a dedicated physically-mapped memory. Data port has access to
    7.33 +//    a dedicated physically-mapped memory. In order to be able to manipulate
    7.34 +//    values in both these memories via the debugger, these memories also
    7.35 +//    interface with the data port of LM32.
    7.36 +// 2. Feature: Extended Configuration Register
    7.37 +// 3. Bug Fix: Removed port names that conflict with keywords reserved in System-
    7.38 +//    Verilog.
    7.39 +//
    7.40 +// Version 3.2
    7.41 +// 1. Bug Fix: Single-stepping a load/store to invalid address causes debugger to
    7.42 +//    hang. At the same time CPU fails to register data bus error exception. Bug
    7.43 +//    is caused because (a) data bus error exception occurs after load/store has
    7.44 +//    passed X stage and next sequential instruction (e.g., brk) is already in X
    7.45 +//    stage, and (b) data bus error exception had lower priority than, say, brk
    7.46 +//    exception.
    7.47 +// 2. Bug Fix: If a brk (or scall/eret/bret) sequentially follows a load/store to
    7.48 +//    invalid location, CPU will fail to register data bus error exception. The
    7.49 +//    solution is to stall scall/eret/bret/brk instructions in D pipeline stage
    7.50 +//    until load/store has completed.
    7.51 +// 3. Feature: Enable precise identification of load/store that causes seg fault.
    7.52 +// 4. SYNC resets used for register file when implemented in EBRs.
    7.53 +//
    7.54 +// Version 3.1
    7.55 +// 1. Feature: LM32 Register File can now be mapped in to on-chip block RAM (EBR)
    7.56 +//    instead of distributed memory by enabling the option in LM32 GUI. 
    7.57 +// 2. Feature: LM32 also adds a static branch predictor to improve branch 
    7.58 +//    performance. All immediate-based forward-pointing branches are predicted 
    7.59 +//    not-taken. All immediate-based backward-pointing branches are predicted taken.
    7.60 +// 
    7.61 +// Version 7.0SP2, 3.0
    7.62 +// No Change
    7.63 +//
    7.64 +// Version 6.1.17
    7.65 +// Initial Release
    7.66 +// =============================================================================
    7.67 +
    7.68 +`include "lm32_include.v"
    7.69 +
    7.70 +/////////////////////////////////////////////////////
    7.71 +// Module interface
    7.72 +/////////////////////////////////////////////////////
    7.73 +
    7.74 +module lm32_cpu (
    7.75 +    // ----- Inputs -------
    7.76 +    clk_i,
    7.77 +`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
    7.78 +    clk_n_i,
    7.79 +`endif    
    7.80 +    rst_i,
    7.81 +    // From external devices
    7.82 +`ifdef CFG_INTERRUPTS_ENABLED
    7.83 +    interrupt_n,
    7.84 +`endif
    7.85 +    // From user logic
    7.86 +`ifdef CFG_USER_ENABLED
    7.87 +    user_result,
    7.88 +    user_complete,
    7.89 +`endif     
    7.90 +`ifdef CFG_JTAG_ENABLED
    7.91 +    // From JTAG
    7.92 +    jtag_clk,
    7.93 +    jtag_update, 
    7.94 +    jtag_reg_q,
    7.95 +    jtag_reg_addr_q,
    7.96 +`endif
    7.97 +`ifdef CFG_IWB_ENABLED
    7.98 +    // Instruction Wishbone master
    7.99 +    I_DAT_I,
   7.100 +    I_ACK_I,
   7.101 +    I_ERR_I,
   7.102 +    I_RTY_I,
   7.103 +`endif
   7.104 +    // Data Wishbone master
   7.105 +    D_DAT_I,
   7.106 +    D_ACK_I,
   7.107 +    D_ERR_I,
   7.108 +    D_RTY_I,
   7.109 +    // ----- Outputs -------
   7.110 +`ifdef CFG_TRACE_ENABLED
   7.111 +    trace_pc,
   7.112 +    trace_pc_valid,
   7.113 +    trace_exception,
   7.114 +    trace_eid,
   7.115 +    trace_eret,
   7.116 +`ifdef CFG_DEBUG_ENABLED
   7.117 +    trace_bret,
   7.118 +`endif
   7.119 +`endif
   7.120 +`ifdef CFG_JTAG_ENABLED
   7.121 +    jtag_reg_d,
   7.122 +    jtag_reg_addr_d,
   7.123 +`endif
   7.124 +`ifdef CFG_USER_ENABLED    
   7.125 +    user_valid,
   7.126 +    user_opcode,
   7.127 +    user_operand_0,
   7.128 +    user_operand_1,
   7.129 +`endif    
   7.130 +`ifdef CFG_IWB_ENABLED
   7.131 +    // Instruction Wishbone master
   7.132 +    I_DAT_O,
   7.133 +    I_ADR_O,
   7.134 +    I_CYC_O,
   7.135 +    I_SEL_O,
   7.136 +    I_STB_O,
   7.137 +    I_WE_O,
   7.138 +    I_CTI_O,
   7.139 +    I_LOCK_O,
   7.140 +    I_BTE_O,
   7.141 +`endif
   7.142 +    // Data Wishbone master
   7.143 +    D_DAT_O,
   7.144 +    D_ADR_O,
   7.145 +    D_CYC_O,
   7.146 +    D_SEL_O,
   7.147 +    D_STB_O,
   7.148 +    D_WE_O,
   7.149 +    D_CTI_O,
   7.150 +    D_LOCK_O,
   7.151 +    D_BTE_O
   7.152 +    );
   7.153 +
   7.154 +/////////////////////////////////////////////////////
   7.155 +// Parameters
   7.156 +/////////////////////////////////////////////////////
   7.157 +
   7.158 +parameter eba_reset = `CFG_EBA_RESET;                           // Reset value for EBA CSR
   7.159 +`ifdef CFG_DEBUG_ENABLED
   7.160 +parameter deba_reset = `CFG_DEBA_RESET;                         // Reset value for DEBA CSR
   7.161 +`endif
   7.162 +
   7.163 +`ifdef CFG_ICACHE_ENABLED
   7.164 +parameter icache_associativity = `CFG_ICACHE_ASSOCIATIVITY;     // Associativity of the cache (Number of ways)
   7.165 +parameter icache_sets = `CFG_ICACHE_SETS;                       // Number of sets
   7.166 +parameter icache_bytes_per_line = `CFG_ICACHE_BYTES_PER_LINE;   // Number of bytes per cache line
   7.167 +parameter icache_base_address = `CFG_ICACHE_BASE_ADDRESS;       // Base address of cachable memory
   7.168 +parameter icache_limit = `CFG_ICACHE_LIMIT;                     // Limit (highest address) of cachable memory
   7.169 +`else
   7.170 +parameter icache_associativity = 1;    
   7.171 +parameter icache_sets = 512;                      
   7.172 +parameter icache_bytes_per_line = 16;  
   7.173 +parameter icache_base_address = 0;      
   7.174 +parameter icache_limit = 0;                    
   7.175 +`endif
   7.176 +
   7.177 +`ifdef CFG_DCACHE_ENABLED
   7.178 +parameter dcache_associativity = `CFG_DCACHE_ASSOCIATIVITY;     // Associativity of the cache (Number of ways)
   7.179 +parameter dcache_sets = `CFG_DCACHE_SETS;                       // Number of sets
   7.180 +parameter dcache_bytes_per_line = `CFG_DCACHE_BYTES_PER_LINE;   // Number of bytes per cache line
   7.181 +parameter dcache_base_address = `CFG_DCACHE_BASE_ADDRESS;       // Base address of cachable memory
   7.182 +parameter dcache_limit = `CFG_DCACHE_LIMIT;                     // Limit (highest address) of cachable memory
   7.183 +`else
   7.184 +parameter dcache_associativity = 1;    
   7.185 +parameter dcache_sets = 512;                      
   7.186 +parameter dcache_bytes_per_line = 16;  
   7.187 +parameter dcache_base_address = 0;      
   7.188 +parameter dcache_limit = 0;                    
   7.189 +`endif
   7.190 +
   7.191 +`ifdef CFG_DEBUG_ENABLED
   7.192 +parameter watchpoints = `CFG_WATCHPOINTS;                       // Number of h/w watchpoint CSRs
   7.193 +`else
   7.194 +parameter watchpoints = 0;
   7.195 +`endif
   7.196 +`ifdef CFG_ROM_DEBUG_ENABLED
   7.197 +parameter breakpoints = `CFG_BREAKPOINTS;                       // Number of h/w breakpoint CSRs
   7.198 +`else
   7.199 +parameter breakpoints = 0;
   7.200 +`endif
   7.201 +
   7.202 +`ifdef CFG_INTERRUPTS_ENABLED
   7.203 +parameter interrupts = `CFG_INTERRUPTS;                         // Number of interrupts
   7.204 +`else
   7.205 +parameter interrupts = 0;
   7.206 +`endif
   7.207 +
   7.208 +/////////////////////////////////////////////////////
   7.209 +// Inputs
   7.210 +/////////////////////////////////////////////////////
   7.211 +
   7.212 +input clk_i;                                    // Clock
   7.213 +`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
   7.214 +input clk_n_i;                                  // Inverted clock
   7.215 +`endif    
   7.216 +input rst_i;                                    // Reset
   7.217 +
   7.218 +`ifdef CFG_INTERRUPTS_ENABLED
   7.219 +input [`LM32_INTERRUPT_RNG] interrupt_n;        // Interrupt pins, active-low
   7.220 +`endif
   7.221 +
   7.222 +`ifdef CFG_USER_ENABLED
   7.223 +input [`LM32_WORD_RNG] user_result;             // User-defined instruction result
   7.224 +input user_complete;                            // User-defined instruction execution is complete
   7.225 +`endif    
   7.226 +
   7.227 +`ifdef CFG_JTAG_ENABLED
   7.228 +input jtag_clk;                                 // JTAG clock
   7.229 +input jtag_update;                              // JTAG state machine is in data register update state
   7.230 +input [`LM32_BYTE_RNG] jtag_reg_q;              
   7.231 +input [2:0] jtag_reg_addr_q;
   7.232 +`endif
   7.233 +
   7.234 +`ifdef CFG_IWB_ENABLED
   7.235 +input [`LM32_WORD_RNG] I_DAT_I;                 // Instruction Wishbone interface read data
   7.236 +input I_ACK_I;                                  // Instruction Wishbone interface acknowledgement
   7.237 +input I_ERR_I;                                  // Instruction Wishbone interface error
   7.238 +input I_RTY_I;                                  // Instruction Wishbone interface retry
   7.239 +`endif
   7.240 +
   7.241 +input [`LM32_WORD_RNG] D_DAT_I;                 // Data Wishbone interface read data
   7.242 +input D_ACK_I;                                  // Data Wishbone interface acknowledgement
   7.243 +input D_ERR_I;                                  // Data Wishbone interface error
   7.244 +input D_RTY_I;                                  // Data Wishbone interface retry
   7.245 +
   7.246 +/////////////////////////////////////////////////////
   7.247 +// Outputs
   7.248 +/////////////////////////////////////////////////////
   7.249 +
   7.250 +`ifdef CFG_TRACE_ENABLED
   7.251 +output [`LM32_PC_RNG] trace_pc;                 // PC to trace
   7.252 +reg    [`LM32_PC_RNG] trace_pc;
   7.253 +output trace_pc_valid;                          // Indicates that a new trace PC is valid
   7.254 +reg    trace_pc_valid;
   7.255 +output trace_exception;                         // Indicates an exception has occured
   7.256 +reg    trace_exception;
   7.257 +output [`LM32_EID_RNG] trace_eid;               // Indicates what type of exception has occured
   7.258 +reg    [`LM32_EID_RNG] trace_eid;
   7.259 +output trace_eret;                              // Indicates an eret instruction has been executed
   7.260 +reg    trace_eret;
   7.261 +`ifdef CFG_DEBUG_ENABLED
   7.262 +output trace_bret;                              // Indicates a bret instruction has been executed
   7.263 +reg    trace_bret;
   7.264 +`endif
   7.265 +`endif
   7.266 +
   7.267 +`ifdef CFG_JTAG_ENABLED
   7.268 +output [`LM32_BYTE_RNG] jtag_reg_d;
   7.269 +wire   [`LM32_BYTE_RNG] jtag_reg_d;
   7.270 +output [2:0] jtag_reg_addr_d;
   7.271 +wire   [2:0] jtag_reg_addr_d;
   7.272 +`endif
   7.273 +
   7.274 +`ifdef CFG_USER_ENABLED
   7.275 +output user_valid;                              // Indicates if user_opcode is valid
   7.276 +wire   user_valid;
   7.277 +output [`LM32_USER_OPCODE_RNG] user_opcode;     // User-defined instruction opcode
   7.278 +reg    [`LM32_USER_OPCODE_RNG] user_opcode;
   7.279 +output [`LM32_WORD_RNG] user_operand_0;         // First operand for user-defined instruction
   7.280 +wire   [`LM32_WORD_RNG] user_operand_0;
   7.281 +output [`LM32_WORD_RNG] user_operand_1;         // Second operand for user-defined instruction
   7.282 +wire   [`LM32_WORD_RNG] user_operand_1;
   7.283 +`endif
   7.284 +
   7.285 +`ifdef CFG_IWB_ENABLED
   7.286 +output [`LM32_WORD_RNG] I_DAT_O;                // Instruction Wishbone interface write data
   7.287 +wire   [`LM32_WORD_RNG] I_DAT_O;
   7.288 +output [`LM32_WORD_RNG] I_ADR_O;                // Instruction Wishbone interface address
   7.289 +wire   [`LM32_WORD_RNG] I_ADR_O;
   7.290 +output I_CYC_O;                                 // Instruction Wishbone interface cycle
   7.291 +wire   I_CYC_O;
   7.292 +output [`LM32_BYTE_SELECT_RNG] I_SEL_O;         // Instruction Wishbone interface byte select
   7.293 +wire   [`LM32_BYTE_SELECT_RNG] I_SEL_O;
   7.294 +output I_STB_O;                                 // Instruction Wishbone interface strobe
   7.295 +wire   I_STB_O;
   7.296 +output I_WE_O;                                  // Instruction Wishbone interface write enable
   7.297 +wire   I_WE_O;
   7.298 +output [`LM32_CTYPE_RNG] I_CTI_O;               // Instruction Wishbone interface cycle type 
   7.299 +wire   [`LM32_CTYPE_RNG] I_CTI_O;
   7.300 +output I_LOCK_O;                                // Instruction Wishbone interface lock bus
   7.301 +wire   I_LOCK_O;
   7.302 +output [`LM32_BTYPE_RNG] I_BTE_O;               // Instruction Wishbone interface burst type 
   7.303 +wire   [`LM32_BTYPE_RNG] I_BTE_O;
   7.304 +`endif
   7.305 +
   7.306 +output [`LM32_WORD_RNG] D_DAT_O;                // Data Wishbone interface write data
   7.307 +wire   [`LM32_WORD_RNG] D_DAT_O;
   7.308 +output [`LM32_WORD_RNG] D_ADR_O;                // Data Wishbone interface address
   7.309 +wire   [`LM32_WORD_RNG] D_ADR_O;
   7.310 +output D_CYC_O;                                 // Data Wishbone interface cycle
   7.311 +wire   D_CYC_O;
   7.312 +output [`LM32_BYTE_SELECT_RNG] D_SEL_O;         // Data Wishbone interface byte select
   7.313 +wire   [`LM32_BYTE_SELECT_RNG] D_SEL_O;
   7.314 +output D_STB_O;                                 // Data Wishbone interface strobe
   7.315 +wire   D_STB_O;
   7.316 +output D_WE_O;                                  // Data Wishbone interface write enable
   7.317 +wire   D_WE_O;
   7.318 +output [`LM32_CTYPE_RNG] D_CTI_O;               // Data Wishbone interface cycle type 
   7.319 +wire   [`LM32_CTYPE_RNG] D_CTI_O;
   7.320 +output D_LOCK_O;                                // Date Wishbone interface lock bus
   7.321 +wire   D_LOCK_O;
   7.322 +output [`LM32_BTYPE_RNG] D_BTE_O;               // Data Wishbone interface burst type 
   7.323 +wire   [`LM32_BTYPE_RNG] D_BTE_O;
   7.324 +
   7.325 +/////////////////////////////////////////////////////
   7.326 +// Internal nets and registers 
   7.327 +/////////////////////////////////////////////////////
   7.328 +
   7.329 +// Pipeline registers
   7.330 +
   7.331 +`ifdef LM32_CACHE_ENABLED
   7.332 +reg valid_a;                                    // Instruction in A stage is valid
   7.333 +`endif
   7.334 +reg valid_f;                                    // Instruction in F stage is valid
   7.335 +reg valid_d;                                    // Instruction in D stage is valid
   7.336 +reg valid_x;                                    // Instruction in X stage is valid
   7.337 +reg valid_m;                                    // Instruction in M stage is valid
   7.338 +reg valid_w;                                    // Instruction in W stage is valid
   7.339 +   
   7.340 +wire q_x;
   7.341 +wire [`LM32_WORD_RNG] immediate_d;              // Immediate operand
   7.342 +wire load_d;                                    // Indicates a load instruction
   7.343 +reg load_x;                                     
   7.344 +reg load_m;
   7.345 +wire load_q_x;
   7.346 +wire store_q_x;
   7.347 +wire store_d;                                   // Indicates a store instruction
   7.348 +reg store_x;
   7.349 +reg store_m;
   7.350 +wire [`LM32_SIZE_RNG] size_d;                   // Size of load/store (byte, hword, word)
   7.351 +reg [`LM32_SIZE_RNG] size_x;
   7.352 +wire branch_d;                                  // Indicates a branch instruction
   7.353 +wire branch_predict_d;                          // Indicates a branch is predicted
   7.354 +wire branch_predict_taken_d;                    // Indicates a branch is predicted taken
   7.355 +wire [`LM32_PC_RNG] branch_predict_address_d;   // Address to which predicted branch jumps
   7.356 +wire [`LM32_PC_RNG] branch_target_d;
   7.357 +wire bi_unconditional;
   7.358 +wire bi_conditional;
   7.359 +reg branch_x;                                   
   7.360 +reg branch_predict_x;
   7.361 +reg branch_predict_taken_x;
   7.362 +reg branch_m;
   7.363 +reg branch_predict_m;
   7.364 +reg branch_predict_taken_m;
   7.365 +wire branch_mispredict_taken_m;                 // Indicates a branch was mispredicted as taken
   7.366 +wire branch_flushX_m;                           // Indicates that instruction in X stage must be squashed
   7.367 +wire branch_reg_d;                              // Branch to register or immediate
   7.368 +wire [`LM32_PC_RNG] branch_offset_d;            // Branch offset for immediate branches
   7.369 +reg [`LM32_PC_RNG] branch_target_x;             // Address to branch to
   7.370 +reg [`LM32_PC_RNG] branch_target_m;
   7.371 +wire [`LM32_D_RESULT_SEL_0_RNG] d_result_sel_0_d; // Which result should be selected in D stage for operand 0
   7.372 +wire [`LM32_D_RESULT_SEL_1_RNG] d_result_sel_1_d; // Which result should be selected in D stage for operand 1
   7.373 +
   7.374 +wire x_result_sel_csr_d;                        // Select X stage result from CSRs
   7.375 +reg x_result_sel_csr_x;
   7.376 +`ifdef LM32_MC_ARITHMETIC_ENABLED
   7.377 +wire x_result_sel_mc_arith_d;                   // Select X stage result from multi-cycle arithmetic unit
   7.378 +reg x_result_sel_mc_arith_x;
   7.379 +`endif
   7.380 +`ifdef LM32_NO_BARREL_SHIFT    
   7.381 +wire x_result_sel_shift_d;                      // Select X stage result from shifter
   7.382 +reg x_result_sel_shift_x;
   7.383 +`endif
   7.384 +`ifdef CFG_SIGN_EXTEND_ENABLED
   7.385 +wire x_result_sel_sext_d;                       // Select X stage result from sign-extend logic
   7.386 +reg x_result_sel_sext_x;
   7.387 +`endif
   7.388 +wire x_result_sel_logic_d;                      // Select X stage result from logic op unit
   7.389 +reg x_result_sel_logic_x;
   7.390 +`ifdef CFG_USER_ENABLED
   7.391 +wire x_result_sel_user_d;                       // Select X stage result from user-defined logic
   7.392 +reg x_result_sel_user_x;
   7.393 +`endif
   7.394 +wire x_result_sel_add_d;                        // Select X stage result from adder
   7.395 +reg x_result_sel_add_x;
   7.396 +wire m_result_sel_compare_d;                    // Select M stage result from comparison logic
   7.397 +reg m_result_sel_compare_x;
   7.398 +reg m_result_sel_compare_m;
   7.399 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
   7.400 +wire m_result_sel_shift_d;                      // Select M stage result from shifter
   7.401 +reg m_result_sel_shift_x;
   7.402 +reg m_result_sel_shift_m;
   7.403 +`endif
   7.404 +wire w_result_sel_load_d;                       // Select W stage result from load/store unit
   7.405 +reg w_result_sel_load_x;
   7.406 +reg w_result_sel_load_m;
   7.407 +reg w_result_sel_load_w;
   7.408 +`ifdef CFG_PL_MULTIPLY_ENABLED
   7.409 +wire w_result_sel_mul_d;                        // Select W stage result from multiplier
   7.410 +reg w_result_sel_mul_x;
   7.411 +reg w_result_sel_mul_m;
   7.412 +reg w_result_sel_mul_w;
   7.413 +`endif
   7.414 +wire x_bypass_enable_d;                         // Whether result is bypassable in X stage
   7.415 +reg x_bypass_enable_x;                          
   7.416 +wire m_bypass_enable_d;                         // Whether result is bypassable in M stage
   7.417 +reg m_bypass_enable_x;                          
   7.418 +reg m_bypass_enable_m;
   7.419 +wire sign_extend_d;                             // Whether to sign-extend or zero-extend
   7.420 +reg sign_extend_x;
   7.421 +wire write_enable_d;                            // Register file write enable
   7.422 +reg write_enable_x;
   7.423 +wire write_enable_q_x;
   7.424 +reg write_enable_m;
   7.425 +wire write_enable_q_m;
   7.426 +reg write_enable_w;
   7.427 +wire write_enable_q_w;
   7.428 +wire read_enable_0_d;                           // Register file read enable 0
   7.429 +wire [`LM32_REG_IDX_RNG] read_idx_0_d;          // Register file read index 0
   7.430 +wire read_enable_1_d;                           // Register file read enable 1
   7.431 +wire [`LM32_REG_IDX_RNG] read_idx_1_d;          // Register file read index 1
   7.432 +wire [`LM32_REG_IDX_RNG] write_idx_d;           // Register file write index
   7.433 +reg [`LM32_REG_IDX_RNG] write_idx_x;            
   7.434 +reg [`LM32_REG_IDX_RNG] write_idx_m;
   7.435 +reg [`LM32_REG_IDX_RNG] write_idx_w;
   7.436 +wire [`LM32_CSR_RNG] csr_d;                     // CSR read/write index
   7.437 +reg  [`LM32_CSR_RNG] csr_x;                  
   7.438 +wire [`LM32_CONDITION_RNG] condition_d;         // Branch condition
   7.439 +reg [`LM32_CONDITION_RNG] condition_x;          
   7.440 +`ifdef CFG_DEBUG_ENABLED
   7.441 +wire break_d;                                   // Indicates a break instruction
   7.442 +reg break_x;                                    
   7.443 +`endif
   7.444 +wire scall_d;                                   // Indicates a scall instruction
   7.445 +reg scall_x;    
   7.446 +wire eret_d;                                    // Indicates an eret instruction
   7.447 +reg eret_x;
   7.448 +wire eret_q_x;
   7.449 +reg eret_m;
   7.450 +`ifdef CFG_TRACE_ENABLED
   7.451 +reg eret_w;
   7.452 +`endif
   7.453 +`ifdef CFG_DEBUG_ENABLED
   7.454 +wire bret_d;                                    // Indicates a bret instruction
   7.455 +reg bret_x;
   7.456 +wire bret_q_x;
   7.457 +reg bret_m;
   7.458 +`ifdef CFG_TRACE_ENABLED
   7.459 +reg bret_w;
   7.460 +`endif
   7.461 +`endif
   7.462 +wire csr_write_enable_d;                        // CSR write enable
   7.463 +reg csr_write_enable_x;
   7.464 +wire csr_write_enable_q_x;
   7.465 +`ifdef CFG_USER_ENABLED
   7.466 +wire [`LM32_USER_OPCODE_RNG] user_opcode_d;     // User-defined instruction opcode
   7.467 +`endif
   7.468 +
   7.469 +`ifdef CFG_BUS_ERRORS_ENABLED
   7.470 +wire bus_error_d;                               // Indicates an bus error occured while fetching the instruction in this pipeline stage
   7.471 +reg bus_error_x;
   7.472 +reg data_bus_error_exception_m;
   7.473 +reg [`LM32_PC_RNG] memop_pc_w;
   7.474 +`endif
   7.475 +
   7.476 +reg [`LM32_WORD_RNG] d_result_0;                // Result of instruction in D stage (operand 0)
   7.477 +reg [`LM32_WORD_RNG] d_result_1;                // Result of instruction in D stage (operand 1)
   7.478 +reg [`LM32_WORD_RNG] x_result;                  // Result of instruction in X stage
   7.479 +reg [`LM32_WORD_RNG] m_result;                  // Result of instruction in M stage
   7.480 +reg [`LM32_WORD_RNG] w_result;                  // Result of instruction in W stage
   7.481 +
   7.482 +reg [`LM32_WORD_RNG] operand_0_x;               // Operand 0 for X stage instruction
   7.483 +reg [`LM32_WORD_RNG] operand_1_x;               // Operand 1 for X stage instruction
   7.484 +reg [`LM32_WORD_RNG] store_operand_x;           // Data read from register to store
   7.485 +reg [`LM32_WORD_RNG] operand_m;                 // Operand for M stage instruction
   7.486 +reg [`LM32_WORD_RNG] operand_w;                 // Operand for W stage instruction
   7.487 +
   7.488 +// To/from register file
   7.489 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
   7.490 +reg [`LM32_WORD_RNG] reg_data_live_0;          
   7.491 +reg [`LM32_WORD_RNG] reg_data_live_1;  
   7.492 +reg use_buf;                                    // Whether to use reg_data_live or reg_data_buf
   7.493 +reg [`LM32_WORD_RNG] reg_data_buf_0;
   7.494 +reg [`LM32_WORD_RNG] reg_data_buf_1;
   7.495 +`endif
   7.496 +`ifdef LM32_EBR_REGISTER_FILE
   7.497 +`else
   7.498 +reg [`LM32_WORD_RNG] registers[0:(1<<`LM32_REG_IDX_WIDTH)-1];   // Register file
   7.499 +`endif
   7.500 +wire [`LM32_WORD_RNG] reg_data_0;               // Register file read port 0 data         
   7.501 +wire [`LM32_WORD_RNG] reg_data_1;               // Register file read port 1 data
   7.502 +reg [`LM32_WORD_RNG] bypass_data_0;             // Register value 0 after bypassing
   7.503 +reg [`LM32_WORD_RNG] bypass_data_1;             // Register value 1 after bypassing
   7.504 +wire reg_write_enable_q_w;
   7.505 +
   7.506 +reg interlock;                                  // Indicates pipeline should be stalled because of a read-after-write hazzard
   7.507 +
   7.508 +wire stall_a;                                   // Stall instruction in A pipeline stage
   7.509 +wire stall_f;                                   // Stall instruction in F pipeline stage
   7.510 +wire stall_d;                                   // Stall instruction in D pipeline stage
   7.511 +wire stall_x;                                   // Stall instruction in X pipeline stage
   7.512 +wire stall_m;                                   // Stall instruction in M pipeline stage
   7.513 +
   7.514 +// To/from adder
   7.515 +wire adder_op_d;                                // Whether to add or subtract
   7.516 +reg adder_op_x;                                 
   7.517 +reg adder_op_x_n;                               // Inverted version of adder_op_x
   7.518 +wire [`LM32_WORD_RNG] adder_result_x;           // Result from adder
   7.519 +wire adder_overflow_x;                          // Whether a signed overflow occured
   7.520 +wire adder_carry_n_x;                           // Whether a carry was generated
   7.521 +
   7.522 +// To/from logical operations unit
   7.523 +wire [`LM32_LOGIC_OP_RNG] logic_op_d;           // Which operation to perform
   7.524 +reg [`LM32_LOGIC_OP_RNG] logic_op_x;            
   7.525 +wire [`LM32_WORD_RNG] logic_result_x;           // Result of logical operation
   7.526 +
   7.527 +`ifdef CFG_SIGN_EXTEND_ENABLED
   7.528 +// From sign-extension unit
   7.529 +wire [`LM32_WORD_RNG] sextb_result_x;           // Result of byte sign-extension
   7.530 +wire [`LM32_WORD_RNG] sexth_result_x;           // Result of half-word sign-extenstion
   7.531 +wire [`LM32_WORD_RNG] sext_result_x;            // Result of sign-extension specified by instruction
   7.532 +`endif
   7.533 +
   7.534 +// To/from shifter
   7.535 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
   7.536 +`ifdef CFG_ROTATE_ENABLED
   7.537 +wire rotate_d;                                  // Whether we should rotate or shift
   7.538 +reg rotate_x;                                    
   7.539 +`endif
   7.540 +wire direction_d;                               // Which direction to shift in
   7.541 +reg direction_x;                                        
   7.542 +reg direction_m;
   7.543 +wire [`LM32_WORD_RNG] shifter_result_m;         // Result of shifter
   7.544 +`endif
   7.545 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED
   7.546 +wire shift_left_d;                              // Indicates whether to perform a left shift or not
   7.547 +wire shift_left_q_d;
   7.548 +wire shift_right_d;                             // Indicates whether to perform a right shift or not
   7.549 +wire shift_right_q_d;
   7.550 +`endif
   7.551 +`ifdef LM32_NO_BARREL_SHIFT
   7.552 +wire [`LM32_WORD_RNG] shifter_result_x;         // Result of single-bit right shifter
   7.553 +`endif
   7.554 +
   7.555 +// To/from multiplier
   7.556 +`ifdef LM32_MULTIPLY_ENABLED
   7.557 +wire [`LM32_WORD_RNG] multiplier_result_w;      // Result from multiplier
   7.558 +`endif
   7.559 +`ifdef CFG_MC_MULTIPLY_ENABLED
   7.560 +wire multiply_d;                                // Indicates whether to perform a multiply or not
   7.561 +wire multiply_q_d;
   7.562 +`endif
   7.563 +
   7.564 +// To/from divider
   7.565 +`ifdef CFG_MC_DIVIDE_ENABLED
   7.566 +wire divide_d;                                  // Indicates whether to perform a divider or not
   7.567 +wire divide_q_d;
   7.568 +wire modulus_d;
   7.569 +wire modulus_q_d;
   7.570 +wire divide_by_zero_x;                          // Indicates an attempt was made to divide by zero
   7.571 +`endif
   7.572 +
   7.573 +// To from multi-cycle arithmetic unit
   7.574 +`ifdef LM32_MC_ARITHMETIC_ENABLED
   7.575 +wire mc_stall_request_x;                        // Multi-cycle arithmetic unit stall request
   7.576 +wire [`LM32_WORD_RNG] mc_result_x;
   7.577 +`endif
   7.578 +
   7.579 +// From CSRs
   7.580 +`ifdef CFG_INTERRUPTS_ENABLED
   7.581 +wire [`LM32_WORD_RNG] interrupt_csr_read_data_x;// Data read from interrupt CSRs
   7.582 +`endif
   7.583 +wire [`LM32_WORD_RNG] cfg;                      // Configuration CSR
   7.584 +wire [`LM32_WORD_RNG] cfg2;                     // Extended Configuration CSR
   7.585 +`ifdef CFG_CYCLE_COUNTER_ENABLED
   7.586 +reg [`LM32_WORD_RNG] cc;                        // Cycle counter CSR
   7.587 +`endif
   7.588 +reg [`LM32_WORD_RNG] csr_read_data_x;           // Data read from CSRs
   7.589 +
   7.590 +// To/from instruction unit
   7.591 +wire [`LM32_PC_RNG] pc_f;                       // PC of instruction in F stage
   7.592 +wire [`LM32_PC_RNG] pc_d;                       // PC of instruction in D stage
   7.593 +wire [`LM32_PC_RNG] pc_x;                       // PC of instruction in X stage
   7.594 +wire [`LM32_PC_RNG] pc_m;                       // PC of instruction in M stage
   7.595 +wire [`LM32_PC_RNG] pc_w;                       // PC of instruction in W stage
   7.596 +`ifdef CFG_TRACE_ENABLED
   7.597 +reg [`LM32_PC_RNG] pc_c;                        // PC of last commited instruction
   7.598 +`endif
   7.599 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
   7.600 +wire [`LM32_INSTRUCTION_RNG] instruction_f;     // Instruction in F stage
   7.601 +`endif
   7.602 +//pragma attribute instruction_d preserve_signal true
   7.603 +//pragma attribute instruction_d preserve_driver true
   7.604 +wire [`LM32_INSTRUCTION_RNG] instruction_d;     // Instruction in D stage
   7.605 +`ifdef CFG_ICACHE_ENABLED
   7.606 +wire iflush;                                    // Flush instruction cache
   7.607 +wire icache_stall_request;                      // Stall pipeline because instruction cache is busy
   7.608 +wire icache_restart_request;                    // Restart instruction that caused an instruction cache miss
   7.609 +wire icache_refill_request;                     // Request to refill instruction cache
   7.610 +wire icache_refilling;                          // Indicates the instruction cache is being refilled
   7.611 +`endif
   7.612 +`ifdef CFG_IROM_ENABLED
   7.613 +wire [`LM32_WORD_RNG] irom_store_data_m;        // Store data to instruction ROM
   7.614 +wire [`LM32_WORD_RNG] irom_address_xm;          // Address to instruction ROM from load-store unit
   7.615 +wire [`LM32_WORD_RNG] irom_data_m;              // Load data from instruction ROM
   7.616 +wire irom_we_xm;                                // Indicates data needs to be written to instruction ROM
   7.617 +wire irom_stall_request_x;                      // Indicates D stage needs to be stalled on a store to instruction ROM
   7.618 +`endif
   7.619 +
   7.620 +// To/from load/store unit
   7.621 +`ifdef CFG_DCACHE_ENABLED
   7.622 +wire dflush_x;                                  // Flush data cache    
   7.623 +reg dflush_m;                                    
   7.624 +wire dcache_stall_request;                      // Stall pipeline because data cache is busy
   7.625 +wire dcache_restart_request;                    // Restart instruction that caused a data cache miss
   7.626 +wire dcache_refill_request;                     // Request to refill data cache
   7.627 +wire dcache_refilling;                          // Indicates the data cache is being refilled
   7.628 +`endif
   7.629 +wire [`LM32_WORD_RNG] load_data_w;              // Result of a load instruction
   7.630 +wire stall_wb_load;                             // Stall pipeline because of a load via the data Wishbone interface
   7.631 +
   7.632 +// To/from JTAG interface
   7.633 +`ifdef CFG_JTAG_ENABLED
   7.634 +`ifdef CFG_JTAG_UART_ENABLED
   7.635 +wire [`LM32_WORD_RNG] jtx_csr_read_data;        // Read data for JTX CSR
   7.636 +wire [`LM32_WORD_RNG] jrx_csr_read_data;        // Read data for JRX CSR
   7.637 +`endif
   7.638 +`ifdef CFG_HW_DEBUG_ENABLED
   7.639 +wire jtag_csr_write_enable;                     // Debugger CSR write enable
   7.640 +wire [`LM32_WORD_RNG] jtag_csr_write_data;      // Data to write to specified CSR
   7.641 +wire [`LM32_CSR_RNG] jtag_csr;                  // Which CSR to write
   7.642 +wire jtag_read_enable;                          
   7.643 +wire [`LM32_BYTE_RNG] jtag_read_data;
   7.644 +wire jtag_write_enable;
   7.645 +wire [`LM32_BYTE_RNG] jtag_write_data;
   7.646 +wire [`LM32_WORD_RNG] jtag_address;
   7.647 +wire jtag_access_complete;
   7.648 +`endif
   7.649 +`ifdef CFG_DEBUG_ENABLED
   7.650 +wire jtag_break;                                // Request from debugger to raise a breakpoint
   7.651 +`endif
   7.652 +`endif
   7.653 +
   7.654 +// Hazzard detection
   7.655 +wire raw_x_0;                                   // RAW hazzard between instruction in X stage and read port 0
   7.656 +wire raw_x_1;                                   // RAW hazzard between instruction in X stage and read port 1
   7.657 +wire raw_m_0;                                   // RAW hazzard between instruction in M stage and read port 0
   7.658 +wire raw_m_1;                                   // RAW hazzard between instruction in M stage and read port 1
   7.659 +wire raw_w_0;                                   // RAW hazzard between instruction in W stage and read port 0
   7.660 +wire raw_w_1;                                   // RAW hazzard between instruction in W stage and read port 1
   7.661 +
   7.662 +// Control flow
   7.663 +wire cmp_zero;                                  // Result of comparison is zero
   7.664 +wire cmp_negative;                              // Result of comparison is negative
   7.665 +wire cmp_overflow;                              // Comparison produced an overflow
   7.666 +wire cmp_carry_n;                               // Comparison produced a carry, inverted
   7.667 +reg condition_met_x;                            // Condition of branch instruction is met
   7.668 +reg condition_met_m;
   7.669 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
   7.670 +wire branch_taken_x;                            // Branch is taken in X stage
   7.671 +`endif
   7.672 +wire branch_taken_m;                            // Branch is taken in M stage
   7.673 +
   7.674 +wire kill_f;                                    // Kill instruction in F stage
   7.675 +wire kill_d;                                    // Kill instruction in D stage
   7.676 +wire kill_x;                                    // Kill instruction in X stage
   7.677 +wire kill_m;                                    // Kill instruction in M stage
   7.678 +wire kill_w;                                    // Kill instruction in W stage
   7.679 +
   7.680 +reg [`LM32_PC_WIDTH+2-1:8] eba;                 // Exception Base Address (EBA) CSR
   7.681 +`ifdef CFG_DEBUG_ENABLED
   7.682 +reg [`LM32_PC_WIDTH+2-1:8] deba;                // Debug Exception Base Address (DEBA) CSR
   7.683 +`endif
   7.684 +reg [`LM32_EID_RNG] eid_x;                      // Exception ID in X stage
   7.685 +`ifdef CFG_TRACE_ENABLED
   7.686 +reg [`LM32_EID_RNG] eid_m;                      // Exception ID in M stage
   7.687 +reg [`LM32_EID_RNG] eid_w;                      // Exception ID in W stage
   7.688 +`endif
   7.689 +
   7.690 +`ifdef CFG_DEBUG_ENABLED
   7.691 +`ifdef LM32_SINGLE_STEP_ENABLED
   7.692 +wire dc_ss;                                     // Is single-step enabled
   7.693 +`endif
   7.694 +wire dc_re;                                     // Remap all exceptions
   7.695 +wire exception_x;                               // An exception occured in the X stage
   7.696 +reg exception_m;                                // An instruction that caused an exception is in the M stage
   7.697 +wire debug_exception_x;                         // Indicates if a debug exception has occured
   7.698 +reg debug_exception_m;
   7.699 +reg debug_exception_w;
   7.700 +wire debug_exception_q_w;
   7.701 +wire non_debug_exception_x;                     // Indicates if a non debug exception has occured
   7.702 +reg non_debug_exception_m;
   7.703 +reg non_debug_exception_w;
   7.704 +wire non_debug_exception_q_w;
   7.705 +`else
   7.706 +wire exception_x;                               // Indicates if a debug exception has occured
   7.707 +reg exception_m;
   7.708 +reg exception_w;
   7.709 +wire exception_q_w;
   7.710 +`endif
   7.711 +
   7.712 +`ifdef CFG_DEBUG_ENABLED
   7.713 +`ifdef CFG_JTAG_ENABLED
   7.714 +wire reset_exception;                           // Indicates if a reset exception has occured
   7.715 +`endif
   7.716 +`endif
   7.717 +`ifdef CFG_INTERRUPTS_ENABLED
   7.718 +wire interrupt_exception;                       // Indicates if an interrupt exception has occured
   7.719 +`endif
   7.720 +`ifdef CFG_DEBUG_ENABLED
   7.721 +wire breakpoint_exception;                      // Indicates if a breakpoint exception has occured
   7.722 +wire watchpoint_exception;                      // Indicates if a watchpoint exception has occured
   7.723 +`endif
   7.724 +`ifdef CFG_BUS_ERRORS_ENABLED
   7.725 +wire instruction_bus_error_exception;           // Indicates if an instruction bus error exception has occured
   7.726 +wire data_bus_error_exception;                  // Indicates if a data bus error exception has occured
   7.727 +`endif
   7.728 +`ifdef CFG_MC_DIVIDE_ENABLED
   7.729 +wire divide_by_zero_exception;                  // Indicates if a divide by zero exception has occured
   7.730 +`endif
   7.731 +wire system_call_exception;                     // Indicates if a system call exception has occured
   7.732 +
   7.733 +`ifdef CFG_BUS_ERRORS_ENABLED
   7.734 +reg data_bus_error_seen;                        // Indicates if a data bus error was seen
   7.735 +`endif
   7.736 +
   7.737 +/////////////////////////////////////////////////////
   7.738 +// Functions
   7.739 +/////////////////////////////////////////////////////
   7.740 +
   7.741 +`include "lm32_functions.v"
   7.742 +
   7.743 +/////////////////////////////////////////////////////
   7.744 +// Instantiations
   7.745 +///////////////////////////////////////////////////// 
   7.746 +
   7.747 +// Instruction unit
   7.748 +lm32_instruction_unit #(
   7.749 +    .associativity          (icache_associativity),
   7.750 +    .sets                   (icache_sets),
   7.751 +    .bytes_per_line         (icache_bytes_per_line),
   7.752 +    .base_address           (icache_base_address),
   7.753 +    .limit                  (icache_limit)
   7.754 +  ) instruction_unit (
   7.755 +    // ----- Inputs -------
   7.756 +    .clk_i                  (clk_i),
   7.757 +    .rst_i                  (rst_i),
   7.758 +    // From pipeline
   7.759 +    .stall_a                (stall_a),
   7.760 +    .stall_f                (stall_f),
   7.761 +    .stall_d                (stall_d),
   7.762 +    .stall_x                (stall_x),
   7.763 +    .stall_m                (stall_m),
   7.764 +    .valid_f                (valid_f),
   7.765 +    .valid_d                (valid_d),
   7.766 +    .kill_f                 (kill_f),
   7.767 +    .branch_predict_taken_d (branch_predict_taken_d),
   7.768 +    .branch_predict_address_d (branch_predict_address_d),
   7.769 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
   7.770 +    .branch_taken_x         (branch_taken_x),
   7.771 +    .branch_target_x        (branch_target_x),
   7.772 +`endif
   7.773 +    .exception_m            (exception_m),
   7.774 +    .branch_taken_m         (branch_taken_m),
   7.775 +    .branch_mispredict_taken_m (branch_mispredict_taken_m),
   7.776 +    .branch_target_m        (branch_target_m),
   7.777 +`ifdef CFG_ICACHE_ENABLED
   7.778 +    .iflush                 (iflush),
   7.779 +`endif
   7.780 +`ifdef CFG_IROM_ENABLED
   7.781 +    .irom_store_data_m      (irom_store_data_m),
   7.782 +    .irom_address_xm        (irom_address_xm),
   7.783 +    .irom_we_xm             (irom_we_xm),
   7.784 +`endif
   7.785 +`ifdef CFG_DCACHE_ENABLED
   7.786 +    .dcache_restart_request (dcache_restart_request),
   7.787 +    .dcache_refill_request  (dcache_refill_request),
   7.788 +    .dcache_refilling       (dcache_refilling),
   7.789 +`endif        
   7.790 +`ifdef CFG_IWB_ENABLED
   7.791 +    // From Wishbone
   7.792 +    .i_dat_i                (I_DAT_I),
   7.793 +    .i_ack_i                (I_ACK_I),
   7.794 +    .i_err_i                (I_ERR_I),
   7.795 +    .i_rty_i                (I_RTY_I),
   7.796 +`endif
   7.797 +`ifdef CFG_HW_DEBUG_ENABLED
   7.798 +    .jtag_read_enable       (jtag_read_enable),
   7.799 +    .jtag_write_enable      (jtag_write_enable),
   7.800 +    .jtag_write_data        (jtag_write_data),
   7.801 +    .jtag_address           (jtag_address),
   7.802 +`endif
   7.803 +    // ----- Outputs -------
   7.804 +    // To pipeline
   7.805 +    .pc_f                   (pc_f),
   7.806 +    .pc_d                   (pc_d),
   7.807 +    .pc_x                   (pc_x),
   7.808 +    .pc_m                   (pc_m),
   7.809 +    .pc_w                   (pc_w),
   7.810 +`ifdef CFG_ICACHE_ENABLED
   7.811 +    .icache_stall_request   (icache_stall_request),
   7.812 +    .icache_restart_request (icache_restart_request),
   7.813 +    .icache_refill_request  (icache_refill_request),
   7.814 +    .icache_refilling       (icache_refilling),
   7.815 +`endif
   7.816 +`ifdef CFG_IROM_ENABLED
   7.817 +    .irom_data_m            (irom_data_m),
   7.818 +`endif
   7.819 +`ifdef CFG_IWB_ENABLED
   7.820 +    // To Wishbone
   7.821 +    .i_dat_o                (I_DAT_O),
   7.822 +    .i_adr_o                (I_ADR_O),
   7.823 +    .i_cyc_o                (I_CYC_O),
   7.824 +    .i_sel_o                (I_SEL_O),
   7.825 +    .i_stb_o                (I_STB_O),
   7.826 +    .i_we_o                 (I_WE_O),
   7.827 +    .i_cti_o                (I_CTI_O),
   7.828 +    .i_lock_o               (I_LOCK_O),
   7.829 +    .i_bte_o                (I_BTE_O),
   7.830 +`endif
   7.831 +`ifdef CFG_HW_DEBUG_ENABLED
   7.832 +    .jtag_read_data         (jtag_read_data),
   7.833 +    .jtag_access_complete   (jtag_access_complete),
   7.834 +`endif
   7.835 +`ifdef CFG_BUS_ERRORS_ENABLED
   7.836 +    .bus_error_d            (bus_error_d),
   7.837 +`endif
   7.838 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
   7.839 +    .instruction_f          (instruction_f),
   7.840 +`endif
   7.841 +    .instruction_d          (instruction_d)
   7.842 +    );
   7.843 +
   7.844 +// Instruction decoder
   7.845 +lm32_decoder decoder (
   7.846 +    // ----- Inputs -------
   7.847 +    .instruction            (instruction_d),
   7.848 +    // ----- Outputs -------
   7.849 +    .d_result_sel_0         (d_result_sel_0_d),
   7.850 +    .d_result_sel_1         (d_result_sel_1_d),
   7.851 +    .x_result_sel_csr       (x_result_sel_csr_d),
   7.852 +`ifdef LM32_MC_ARITHMETIC_ENABLED
   7.853 +    .x_result_sel_mc_arith  (x_result_sel_mc_arith_d),
   7.854 +`endif
   7.855 +`ifdef LM32_NO_BARREL_SHIFT    
   7.856 +    .x_result_sel_shift     (x_result_sel_shift_d),
   7.857 +`endif
   7.858 +`ifdef CFG_SIGN_EXTEND_ENABLED
   7.859 +    .x_result_sel_sext      (x_result_sel_sext_d),
   7.860 +`endif    
   7.861 +    .x_result_sel_logic     (x_result_sel_logic_d),
   7.862 +`ifdef CFG_USER_ENABLED
   7.863 +    .x_result_sel_user      (x_result_sel_user_d),
   7.864 +`endif
   7.865 +    .x_result_sel_add       (x_result_sel_add_d),
   7.866 +    .m_result_sel_compare   (m_result_sel_compare_d),
   7.867 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
   7.868 +    .m_result_sel_shift     (m_result_sel_shift_d),  
   7.869 +`endif    
   7.870 +    .w_result_sel_load      (w_result_sel_load_d),
   7.871 +`ifdef CFG_PL_MULTIPLY_ENABLED
   7.872 +    .w_result_sel_mul       (w_result_sel_mul_d),
   7.873 +`endif
   7.874 +    .x_bypass_enable        (x_bypass_enable_d),
   7.875 +    .m_bypass_enable        (m_bypass_enable_d),
   7.876 +    .read_enable_0          (read_enable_0_d),
   7.877 +    .read_idx_0             (read_idx_0_d),
   7.878 +    .read_enable_1          (read_enable_1_d),
   7.879 +    .read_idx_1             (read_idx_1_d),
   7.880 +    .write_enable           (write_enable_d),
   7.881 +    .write_idx              (write_idx_d),
   7.882 +    .immediate              (immediate_d),
   7.883 +    .branch_offset          (branch_offset_d),
   7.884 +    .load                   (load_d),
   7.885 +    .store                  (store_d),
   7.886 +    .size                   (size_d),
   7.887 +    .sign_extend            (sign_extend_d),
   7.888 +    .adder_op               (adder_op_d),
   7.889 +    .logic_op               (logic_op_d),
   7.890 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
   7.891 +    .direction              (direction_d),
   7.892 +`endif
   7.893 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED
   7.894 +    .shift_left             (shift_left_d),
   7.895 +    .shift_right            (shift_right_d),
   7.896 +`endif
   7.897 +`ifdef CFG_MC_MULTIPLY_ENABLED
   7.898 +    .multiply               (multiply_d),
   7.899 +`endif
   7.900 +`ifdef CFG_MC_DIVIDE_ENABLED
   7.901 +    .divide                 (divide_d),
   7.902 +    .modulus                (modulus_d),
   7.903 +`endif
   7.904 +    .branch                 (branch_d),
   7.905 +    .bi_unconditional       (bi_unconditional),
   7.906 +    .bi_conditional         (bi_conditional),
   7.907 +    .branch_reg             (branch_reg_d),
   7.908 +    .condition              (condition_d),
   7.909 +`ifdef CFG_DEBUG_ENABLED
   7.910 +    .break_opcode           (break_d),
   7.911 +`endif
   7.912 +    .scall                  (scall_d),
   7.913 +    .eret                   (eret_d),
   7.914 +`ifdef CFG_DEBUG_ENABLED
   7.915 +    .bret                   (bret_d),
   7.916 +`endif
   7.917 +`ifdef CFG_USER_ENABLED
   7.918 +    .user_opcode            (user_opcode_d),
   7.919 +`endif
   7.920 +    .csr_write_enable       (csr_write_enable_d)
   7.921 +    ); 
   7.922 +
   7.923 +// Load/store unit       
   7.924 +lm32_load_store_unit #(
   7.925 +    .associativity          (dcache_associativity),
   7.926 +    .sets                   (dcache_sets),
   7.927 +    .bytes_per_line         (dcache_bytes_per_line),
   7.928 +    .base_address           (dcache_base_address),
   7.929 +    .limit                  (dcache_limit)
   7.930 +  ) load_store_unit (
   7.931 +    // ----- Inputs -------
   7.932 +    .clk_i                  (clk_i),
   7.933 +    .rst_i                  (rst_i),
   7.934 +    // From pipeline
   7.935 +    .stall_a                (stall_a),
   7.936 +    .stall_x                (stall_x),
   7.937 +    .stall_m                (stall_m),
   7.938 +    .kill_x                 (kill_x),
   7.939 +    .kill_m                 (kill_m),
   7.940 +    .exception_m            (exception_m),
   7.941 +    .store_operand_x        (store_operand_x),
   7.942 +    .load_store_address_x   (adder_result_x),
   7.943 +    .load_store_address_m   (operand_m),
   7.944 +    .load_store_address_w   (operand_w[1:0]),
   7.945 +    .load_x                 (load_x),
   7.946 +    .store_x                (store_x),
   7.947 +    .load_q_x               (load_q_x),
   7.948 +    .store_q_x              (store_q_x),
   7.949 +    .load_q_m               (load_q_m),
   7.950 +    .store_q_m              (store_q_m),
   7.951 +    .sign_extend_x          (sign_extend_x),
   7.952 +    .size_x                 (size_x),
   7.953 +`ifdef CFG_DCACHE_ENABLED
   7.954 +    .dflush                 (dflush_m),
   7.955 +`endif
   7.956 +`ifdef CFG_IROM_ENABLED
   7.957 +    .irom_data_m            (irom_data_m),
   7.958 +`endif
   7.959 +    // From Wishbone
   7.960 +    .d_dat_i                (D_DAT_I),
   7.961 +    .d_ack_i                (D_ACK_I),
   7.962 +    .d_err_i                (D_ERR_I),
   7.963 +    .d_rty_i                (D_RTY_I),
   7.964 +    // ----- Outputs -------
   7.965 +    // To pipeline
   7.966 +`ifdef CFG_DCACHE_ENABLED
   7.967 +    .dcache_refill_request  (dcache_refill_request),
   7.968 +    .dcache_restart_request (dcache_restart_request),
   7.969 +    .dcache_stall_request   (dcache_stall_request),
   7.970 +    .dcache_refilling       (dcache_refilling),
   7.971 +`endif    
   7.972 +`ifdef CFG_IROM_ENABLED
   7.973 +    .irom_store_data_m      (irom_store_data_m),
   7.974 +    .irom_address_xm        (irom_address_xm),
   7.975 +    .irom_we_xm             (irom_we_xm),
   7.976 +    .irom_stall_request_x   (irom_stall_request_x),
   7.977 +`endif
   7.978 +    .load_data_w            (load_data_w),
   7.979 +    .stall_wb_load          (stall_wb_load),
   7.980 +    // To Wishbone
   7.981 +    .d_dat_o                (D_DAT_O),
   7.982 +    .d_adr_o                (D_ADR_O),
   7.983 +    .d_cyc_o                (D_CYC_O),
   7.984 +    .d_sel_o                (D_SEL_O),
   7.985 +    .d_stb_o                (D_STB_O),
   7.986 +    .d_we_o                 (D_WE_O),
   7.987 +    .d_cti_o                (D_CTI_O),
   7.988 +    .d_lock_o               (D_LOCK_O),
   7.989 +    .d_bte_o                (D_BTE_O)
   7.990 +    );      
   7.991 +       
   7.992 +// Adder       
   7.993 +lm32_adder adder (
   7.994 +    // ----- Inputs -------
   7.995 +    .adder_op_x             (adder_op_x),
   7.996 +    .adder_op_x_n           (adder_op_x_n),
   7.997 +    .operand_0_x            (operand_0_x),
   7.998 +    .operand_1_x            (operand_1_x),
   7.999 +    // ----- Outputs -------
  7.1000 +    .adder_result_x         (adder_result_x),
  7.1001 +    .adder_carry_n_x        (adder_carry_n_x),
  7.1002 +    .adder_overflow_x       (adder_overflow_x)
  7.1003 +    );
  7.1004 +
  7.1005 +// Logic operations
  7.1006 +lm32_logic_op logic_op (
  7.1007 +    // ----- Inputs -------
  7.1008 +    .logic_op_x             (logic_op_x),
  7.1009 +    .operand_0_x            (operand_0_x),
  7.1010 +
  7.1011 +    .operand_1_x            (operand_1_x),
  7.1012 +    // ----- Outputs -------
  7.1013 +    .logic_result_x         (logic_result_x)
  7.1014 +    );
  7.1015 +              
  7.1016 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  7.1017 +// Pipelined barrel-shifter
  7.1018 +lm32_shifter shifter (
  7.1019 +    // ----- Inputs -------
  7.1020 +    .clk_i                  (clk_i),
  7.1021 +    .rst_i                  (rst_i),
  7.1022 +    .stall_x                (stall_x),
  7.1023 +    .direction_x            (direction_x),
  7.1024 +    .sign_extend_x          (sign_extend_x),
  7.1025 +    .operand_0_x            (operand_0_x),
  7.1026 +    .operand_1_x            (operand_1_x),
  7.1027 +    // ----- Outputs -------
  7.1028 +    .shifter_result_m       (shifter_result_m)
  7.1029 +    );
  7.1030 +`endif
  7.1031 +
  7.1032 +`ifdef CFG_PL_MULTIPLY_ENABLED
  7.1033 +// Pipeline fixed-point multiplier
  7.1034 +lm32_multiplier multiplier (
  7.1035 +    // ----- Inputs -------
  7.1036 +    .clk_i                  (clk_i),
  7.1037 +    .rst_i                  (rst_i),
  7.1038 +    .stall_x                (stall_x),
  7.1039 +    .stall_m                (stall_m),
  7.1040 +    .operand_0              (d_result_0),
  7.1041 +    .operand_1              (d_result_1),
  7.1042 +    // ----- Outputs -------
  7.1043 +    .result                 (multiplier_result_w)    
  7.1044 +    );
  7.1045 +`endif
  7.1046 +
  7.1047 +`ifdef LM32_MC_ARITHMETIC_ENABLED
  7.1048 +// Multi-cycle arithmetic
  7.1049 +lm32_mc_arithmetic mc_arithmetic (
  7.1050 +    // ----- Inputs -------
  7.1051 +    .clk_i                  (clk_i),
  7.1052 +    .rst_i                  (rst_i),
  7.1053 +    .stall_d                (stall_d),
  7.1054 +    .kill_x                 (kill_x),
  7.1055 +`ifdef CFG_MC_DIVIDE_ENABLED                  
  7.1056 +    .divide_d               (divide_q_d),
  7.1057 +    .modulus_d              (modulus_q_d),
  7.1058 +`endif
  7.1059 +`ifdef CFG_MC_MULTIPLY_ENABLED        
  7.1060 +    .multiply_d             (multiply_q_d),
  7.1061 +`endif
  7.1062 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED
  7.1063 +    .shift_left_d           (shift_left_q_d),
  7.1064 +    .shift_right_d          (shift_right_q_d),
  7.1065 +    .sign_extend_d          (sign_extend_d),
  7.1066 +`endif    
  7.1067 +    .operand_0_d            (d_result_0),
  7.1068 +    .operand_1_d            (d_result_1),
  7.1069 +    // ----- Outputs -------
  7.1070 +    .result_x               (mc_result_x),
  7.1071 +`ifdef CFG_MC_DIVIDE_ENABLED                  
  7.1072 +    .divide_by_zero_x       (divide_by_zero_x),
  7.1073 +`endif
  7.1074 +    .stall_request_x        (mc_stall_request_x)
  7.1075 +    );
  7.1076 +`endif
  7.1077 +              
  7.1078 +`ifdef CFG_INTERRUPTS_ENABLED
  7.1079 +// Interrupt unit
  7.1080 +lm32_interrupt interrupt (
  7.1081 +    // ----- Inputs -------
  7.1082 +    .clk_i                  (clk_i), 
  7.1083 +    .rst_i                  (rst_i),
  7.1084 +    // From external devices
  7.1085 +    .interrupt_n            (interrupt_n),
  7.1086 +    // From pipeline
  7.1087 +    .stall_x                (stall_x),
  7.1088 +`ifdef CFG_DEBUG_ENABLED
  7.1089 +    .non_debug_exception    (non_debug_exception_q_w), 
  7.1090 +    .debug_exception        (debug_exception_q_w),
  7.1091 +`else
  7.1092 +    .exception              (exception_q_w), 
  7.1093 +`endif
  7.1094 +    .eret_q_x               (eret_q_x),
  7.1095 +`ifdef CFG_DEBUG_ENABLED
  7.1096 +    .bret_q_x               (bret_q_x),
  7.1097 +`endif
  7.1098 +    .csr                    (csr_x),
  7.1099 +    .csr_write_data         (operand_1_x),
  7.1100 +    .csr_write_enable       (csr_write_enable_q_x),
  7.1101 +    // ----- Outputs -------
  7.1102 +    .interrupt_exception    (interrupt_exception),
  7.1103 +    // To pipeline
  7.1104 +    .csr_read_data          (interrupt_csr_read_data_x)
  7.1105 +    );
  7.1106 +`endif
  7.1107 +
  7.1108 +`ifdef CFG_JTAG_ENABLED
  7.1109 +// JTAG interface
  7.1110 +lm32_jtag jtag (
  7.1111 +    // ----- Inputs -------
  7.1112 +    .clk_i                  (clk_i),
  7.1113 +    .rst_i                  (rst_i),
  7.1114 +    // From JTAG
  7.1115 +    .jtag_clk               (jtag_clk),
  7.1116 +    .jtag_update            (jtag_update),
  7.1117 +    .jtag_reg_q             (jtag_reg_q),
  7.1118 +    .jtag_reg_addr_q        (jtag_reg_addr_q),
  7.1119 +    // From pipeline
  7.1120 +`ifdef CFG_JTAG_UART_ENABLED
  7.1121 +    .csr                    (csr_x),
  7.1122 +    .csr_write_data         (operand_1_x),
  7.1123 +    .csr_write_enable       (csr_write_enable_q_x),
  7.1124 +    .stall_x                (stall_x),
  7.1125 +`endif
  7.1126 +`ifdef CFG_HW_DEBUG_ENABLED
  7.1127 +    .jtag_read_data         (jtag_read_data),
  7.1128 +    .jtag_access_complete   (jtag_access_complete),
  7.1129 +`endif
  7.1130 +`ifdef CFG_DEBUG_ENABLED
  7.1131 +    .exception_q_w          (debug_exception_q_w || non_debug_exception_q_w),
  7.1132 +`endif    
  7.1133 +    // ----- Outputs -------
  7.1134 +    // To pipeline
  7.1135 +`ifdef CFG_JTAG_UART_ENABLED
  7.1136 +    .jtx_csr_read_data      (jtx_csr_read_data),
  7.1137 +    .jrx_csr_read_data      (jrx_csr_read_data),
  7.1138 +`endif
  7.1139 +`ifdef CFG_HW_DEBUG_ENABLED
  7.1140 +    .jtag_csr_write_enable  (jtag_csr_write_enable),
  7.1141 +    .jtag_csr_write_data    (jtag_csr_write_data),
  7.1142 +    .jtag_csr               (jtag_csr),
  7.1143 +    .jtag_read_enable       (jtag_read_enable),
  7.1144 +    .jtag_write_enable      (jtag_write_enable),
  7.1145 +    .jtag_write_data        (jtag_write_data),
  7.1146 +    .jtag_address           (jtag_address),
  7.1147 +`endif
  7.1148 +`ifdef CFG_DEBUG_ENABLED
  7.1149 +    .jtag_break             (jtag_break),
  7.1150 +    .jtag_reset             (reset_exception),
  7.1151 +`endif
  7.1152 +    // To JTAG 
  7.1153 +    .jtag_reg_d             (jtag_reg_d),
  7.1154 +    .jtag_reg_addr_d        (jtag_reg_addr_d)
  7.1155 +    );
  7.1156 +`endif
  7.1157 +
  7.1158 +`ifdef CFG_DEBUG_ENABLED
  7.1159 +// Debug unit
  7.1160 +lm32_debug #(
  7.1161 +    .breakpoints            (breakpoints),
  7.1162 +    .watchpoints            (watchpoints)
  7.1163 +  ) hw_debug (
  7.1164 +    // ----- Inputs -------
  7.1165 +    .clk_i                  (clk_i), 
  7.1166 +    .rst_i                  (rst_i),
  7.1167 +    .pc_x                   (pc_x),
  7.1168 +    .load_x                 (load_x),
  7.1169 +    .store_x                (store_x),
  7.1170 +    .load_store_address_x   (adder_result_x),
  7.1171 +    .csr_write_enable_x     (csr_write_enable_q_x),
  7.1172 +    .csr_write_data         (operand_1_x),
  7.1173 +    .csr_x                  (csr_x),
  7.1174 +`ifdef CFG_HW_DEBUG_ENABLED
  7.1175 +    .jtag_csr_write_enable  (jtag_csr_write_enable),
  7.1176 +    .jtag_csr_write_data    (jtag_csr_write_data),
  7.1177 +    .jtag_csr               (jtag_csr),
  7.1178 +`endif
  7.1179 +`ifdef LM32_SINGLE_STEP_ENABLED
  7.1180 +    .eret_q_x               (eret_q_x),
  7.1181 +    .bret_q_x               (bret_q_x),
  7.1182 +    .stall_x                (stall_x),
  7.1183 +    .exception_x            (exception_x),
  7.1184 +    .q_x                    (q_x),
  7.1185 +`ifdef CFG_DCACHE_ENABLED
  7.1186 +    .dcache_refill_request  (dcache_refill_request),
  7.1187 +`endif
  7.1188 +`endif
  7.1189 +    // ----- Outputs -------
  7.1190 +`ifdef LM32_SINGLE_STEP_ENABLED
  7.1191 +    .dc_ss                  (dc_ss),
  7.1192 +`endif
  7.1193 +    .dc_re                  (dc_re),
  7.1194 +    .bp_match               (bp_match),
  7.1195 +    .wp_match               (wp_match)
  7.1196 +    );
  7.1197 +`endif
  7.1198 +
  7.1199 +// Register file
  7.1200 +
  7.1201 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
  7.1202 +   /*----------------------------------------------------------------------
  7.1203 +    Register File is implemented using EBRs. There can be three accesses to
  7.1204 +    the register file in each cycle: two reads and one write. On-chip block
  7.1205 +    RAM has two read/write ports. To accomodate three accesses, two on-chip
  7.1206 +    block RAMs are used (each register file "write" is made to both block
  7.1207 +    RAMs).
  7.1208 +    
  7.1209 +    One limitation of the on-chip block RAMs is that one cannot perform a 
  7.1210 +    read and write to same location in a cycle (if this is done, then the
  7.1211 +    data read out is indeterminate).
  7.1212 +    ----------------------------------------------------------------------*/
  7.1213 +   wire [31:0] regfile_data_0, regfile_data_1;
  7.1214 +   reg [31:0]  w_result_d;
  7.1215 +   reg 	       regfile_raw_0, regfile_raw_0_nxt;
  7.1216 +   reg 	       regfile_raw_1, regfile_raw_1_nxt;
  7.1217 +   
  7.1218 +   /*----------------------------------------------------------------------
  7.1219 +    Check if read and write is being performed to same register in current 
  7.1220 +    cycle? This is done by comparing the read and write IDXs.
  7.1221 +    ----------------------------------------------------------------------*/
  7.1222 +   always @(reg_write_enable_q_w or write_idx_w or instruction_f)
  7.1223 +     begin
  7.1224 +	if (reg_write_enable_q_w
  7.1225 +	    && (write_idx_w == instruction_f[25:21]))
  7.1226 +	  regfile_raw_0_nxt = 1'b1;
  7.1227 +	else
  7.1228 +	  regfile_raw_0_nxt = 1'b0;
  7.1229 +	
  7.1230 +	if (reg_write_enable_q_w
  7.1231 +	    && (write_idx_w == instruction_f[20:16]))
  7.1232 +	  regfile_raw_1_nxt = 1'b1;
  7.1233 +	else
  7.1234 +	  regfile_raw_1_nxt = 1'b0;
  7.1235 +     end
  7.1236 +   
  7.1237 +   /*----------------------------------------------------------------------
  7.1238 +    Select latched (delayed) write value or data from register file. If 
  7.1239 +    read in previous cycle was performed to register written to in same
  7.1240 +    cycle, then latched (delayed) write value is selected.
  7.1241 +    ----------------------------------------------------------------------*/
  7.1242 +   always @(regfile_raw_0 or w_result_d or regfile_data_0)
  7.1243 +     if (regfile_raw_0)
  7.1244 +       reg_data_live_0 = w_result_d;
  7.1245 +     else
  7.1246 +       reg_data_live_0 = regfile_data_0;
  7.1247 +   
  7.1248 +   /*----------------------------------------------------------------------
  7.1249 +    Select latched (delayed) write value or data from register file. If 
  7.1250 +    read in previous cycle was performed to register written to in same
  7.1251 +    cycle, then latched (delayed) write value is selected.
  7.1252 +    ----------------------------------------------------------------------*/
  7.1253 +   always @(regfile_raw_1 or w_result_d or regfile_data_1)
  7.1254 +     if (regfile_raw_1)
  7.1255 +       reg_data_live_1 = w_result_d;
  7.1256 +     else
  7.1257 +       reg_data_live_1 = regfile_data_1;
  7.1258 +   
  7.1259 +   /*----------------------------------------------------------------------
  7.1260 +    Latch value written to register file
  7.1261 +    ----------------------------------------------------------------------*/
  7.1262 +   always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  7.1263 +     if (rst_i == `TRUE)
  7.1264 +       begin
  7.1265 +	  regfile_raw_0 <= 1'b0;
  7.1266 +	  regfile_raw_1 <= 1'b0;
  7.1267 +	  w_result_d <= 32'b0;
  7.1268 +       end
  7.1269 +     else
  7.1270 +       begin
  7.1271 +	  regfile_raw_0 <= regfile_raw_0_nxt;
  7.1272 +	  regfile_raw_1 <= regfile_raw_1_nxt;
  7.1273 +	  w_result_d <= w_result;
  7.1274 +       end
  7.1275 +   
  7.1276 +   /*----------------------------------------------------------------------
  7.1277 +    Register file instantiation as Pseudo-Dual Port EBRs.
  7.1278 +    ----------------------------------------------------------------------*/
  7.1279 +   pmi_ram_dp
  7.1280 +     #(
  7.1281 +       // ----- Parameters -----
  7.1282 +       .pmi_wr_addr_depth(1<<5),
  7.1283 +       .pmi_wr_addr_width(5),
  7.1284 +       .pmi_wr_data_width(32),
  7.1285 +       .pmi_rd_addr_depth(1<<5),
  7.1286 +       .pmi_rd_addr_width(5),
  7.1287 +       .pmi_rd_data_width(32),
  7.1288 +       .pmi_regmode("noreg"),
  7.1289 +       .pmi_gsr("enable"),
  7.1290 +       .pmi_resetmode("sync"),
  7.1291 +       .pmi_init_file("none"),
  7.1292 +       .pmi_init_file_format("binary"),
  7.1293 +       .pmi_family(`LATTICE_FAMILY),
  7.1294 +       .module_type("pmi_ram_dp")
  7.1295 +       )
  7.1296 +   reg_0
  7.1297 +     (
  7.1298 +      // ----- Inputs -----
  7.1299 +      .Data(w_result),
  7.1300 +      .WrAddress(write_idx_w),
  7.1301 +      .RdAddress(instruction_f[25:21]),
  7.1302 +      .WrClock(clk_i),
  7.1303 +      .RdClock(clk_i),
  7.1304 +      .WrClockEn(`TRUE),
  7.1305 +      .RdClockEn(`TRUE),
  7.1306 +      .WE(reg_write_enable_q_w),
  7.1307 +      .Reset(rst_i), 
  7.1308 +      // ----- Outputs -----
  7.1309 +      .Q(regfile_data_0)
  7.1310 +      );
  7.1311 +
  7.1312 +   pmi_ram_dp
  7.1313 +     #(
  7.1314 +       // ----- Parameters -----
  7.1315 +       .pmi_wr_addr_depth(1<<5),
  7.1316 +       .pmi_wr_addr_width(5),
  7.1317 +       .pmi_wr_data_width(32),
  7.1318 +       .pmi_rd_addr_depth(1<<5),
  7.1319 +       .pmi_rd_addr_width(5),
  7.1320 +       .pmi_rd_data_width(32),
  7.1321 +       .pmi_regmode("noreg"),
  7.1322 +       .pmi_gsr("enable"),
  7.1323 +       .pmi_resetmode("sync"),
  7.1324 +       .pmi_init_file("none"),
  7.1325 +       .pmi_init_file_format("binary"),
  7.1326 +       .pmi_family(`LATTICE_FAMILY),
  7.1327 +       .module_type("pmi_ram_dp")
  7.1328 +       )
  7.1329 +   reg_1
  7.1330 +     (
  7.1331 +      // ----- Inputs -----
  7.1332 +      .Data(w_result),
  7.1333 +      .WrAddress(write_idx_w),
  7.1334 +      .RdAddress(instruction_f[20:16]),
  7.1335 +      .WrClock(clk_i),
  7.1336 +      .RdClock(clk_i),
  7.1337 +      .WrClockEn(`TRUE),
  7.1338 +      .RdClockEn(`TRUE),
  7.1339 +      .WE(reg_write_enable_q_w),
  7.1340 +      .Reset(rst_i), 
  7.1341 +      // ----- Outputs -----
  7.1342 +      .Q(regfile_data_1)
  7.1343 +      );
  7.1344 +`endif
  7.1345 +
  7.1346 +`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
  7.1347 +   pmi_ram_dp
  7.1348 +     #(
  7.1349 +       // ----- Parameters -----
  7.1350 +       .pmi_wr_addr_depth(1<<5),
  7.1351 +       .pmi_wr_addr_width(5),
  7.1352 +       .pmi_wr_data_width(32),
  7.1353 +       .pmi_rd_addr_depth(1<<5),
  7.1354 +       .pmi_rd_addr_width(5),
  7.1355 +       .pmi_rd_data_width(32),
  7.1356 +       .pmi_regmode("noreg"),
  7.1357 +       .pmi_gsr("enable"),
  7.1358 +       .pmi_resetmode("sync"),
  7.1359 +       .pmi_init_file("none"),
  7.1360 +       .pmi_init_file_format("binary"),
  7.1361 +       .pmi_family(`LATTICE_FAMILY),
  7.1362 +       .module_type("pmi_ram_dp")
  7.1363 +       )
  7.1364 +   reg_0
  7.1365 +     (
  7.1366 +      // ----- Inputs -----
  7.1367 +      .Data(w_result),
  7.1368 +      .WrAddress(write_idx_w),
  7.1369 +      .RdAddress(read_idx_0_d),
  7.1370 +      .WrClock(clk_i),
  7.1371 +      .RdClock(clk_n_i),
  7.1372 +      .WrClockEn(`TRUE),
  7.1373 +      .RdClockEn(stall_f == `FALSE),
  7.1374 +      .WE(reg_write_enable_q_w),
  7.1375 +      .Reset(rst_i), 
  7.1376 +      // ----- Outputs -----
  7.1377 +      .Q(reg_data_0)
  7.1378 +      );
  7.1379 +   
  7.1380 +   pmi_ram_dp
  7.1381 +     #(
  7.1382 +       // ----- Parameters -----
  7.1383 +       .pmi_wr_addr_depth(1<<5),
  7.1384 +       .pmi_wr_addr_width(5),
  7.1385 +       .pmi_wr_data_width(32),
  7.1386 +       .pmi_rd_addr_depth(1<<5),
  7.1387 +       .pmi_rd_addr_width(5),
  7.1388 +       .pmi_rd_data_width(32),
  7.1389 +       .pmi_regmode("noreg"),
  7.1390 +       .pmi_gsr("enable"),
  7.1391 +       .pmi_resetmode("sync"),
  7.1392 +       .pmi_init_file("none"),
  7.1393 +       .pmi_init_file_format("binary"),
  7.1394 +       .pmi_family(`LATTICE_FAMILY),
  7.1395 +       .module_type("pmi_ram_dp")
  7.1396 +       )
  7.1397 +   reg_1
  7.1398 +     (
  7.1399 +      // ----- Inputs -----
  7.1400 +      .Data(w_result),
  7.1401 +      .WrAddress(write_idx_w),
  7.1402 +      .RdAddress(read_idx_1_d),
  7.1403 +      .WrClock(clk_i),
  7.1404 +      .RdClock(clk_n_i),
  7.1405 +      .WrClockEn(`TRUE),
  7.1406 +      .RdClockEn(stall_f == `FALSE),
  7.1407 +      .WE(reg_write_enable_q_w),
  7.1408 +      .Reset(rst_i), 
  7.1409 +      // ----- Outputs -----
  7.1410 +      .Q(reg_data_1)
  7.1411 +      );
  7.1412 +`endif
  7.1413 +
  7.1414 +
  7.1415 +/////////////////////////////////////////////////////
  7.1416 +// Combinational Logic
  7.1417 +/////////////////////////////////////////////////////
  7.1418 +
  7.1419 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
  7.1420 +// Select between buffered and live data from register file
  7.1421 +assign reg_data_0 = use_buf ? reg_data_buf_0 : reg_data_live_0;
  7.1422 +assign reg_data_1 = use_buf ? reg_data_buf_1 : reg_data_live_1;
  7.1423 +`endif
  7.1424 +`ifdef LM32_EBR_REGISTER_FILE
  7.1425 +`else
  7.1426 +// Register file read ports
  7.1427 +assign reg_data_0 = registers[read_idx_0_d];
  7.1428 +assign reg_data_1 = registers[read_idx_1_d];
  7.1429 +`endif
  7.1430 +
  7.1431 +// Detect read-after-write hazzards
  7.1432 +assign raw_x_0 = (write_idx_x == read_idx_0_d) && (write_enable_q_x == `TRUE);
  7.1433 +assign raw_m_0 = (write_idx_m == read_idx_0_d) && (write_enable_q_m == `TRUE);
  7.1434 +assign raw_w_0 = (write_idx_w == read_idx_0_d) && (write_enable_q_w == `TRUE);
  7.1435 +assign raw_x_1 = (write_idx_x == read_idx_1_d) && (write_enable_q_x == `TRUE);
  7.1436 +assign raw_m_1 = (write_idx_m == read_idx_1_d) && (write_enable_q_m == `TRUE);
  7.1437 +assign raw_w_1 = (write_idx_w == read_idx_1_d) && (write_enable_q_w == `TRUE);
  7.1438 +
  7.1439 +// Interlock detection - Raise an interlock for RAW hazzards 
  7.1440 +always @(*)
  7.1441 +begin
  7.1442 +    if (   (   (x_bypass_enable_x == `FALSE)
  7.1443 +            && (   ((read_enable_0_d == `TRUE) && (raw_x_0 == `TRUE))
  7.1444 +                || ((read_enable_1_d == `TRUE) && (raw_x_1 == `TRUE))
  7.1445 +               )
  7.1446 +           )
  7.1447 +        || (   (m_bypass_enable_m == `FALSE)
  7.1448 +            && (   ((read_enable_0_d == `TRUE) && (raw_m_0 == `TRUE))
  7.1449 +                || ((read_enable_1_d == `TRUE) && (raw_m_1 == `TRUE))
  7.1450 +               )
  7.1451 +           )
  7.1452 +       )
  7.1453 +        interlock = `TRUE;
  7.1454 +    else
  7.1455 +        interlock = `FALSE;
  7.1456 +end
  7.1457 +
  7.1458 +// Bypass for reg port 0
  7.1459 +always @(*)
  7.1460 +begin
  7.1461 +    if (raw_x_0 == `TRUE)        
  7.1462 +        bypass_data_0 = x_result;
  7.1463 +    else if (raw_m_0 == `TRUE)
  7.1464 +        bypass_data_0 = m_result;
  7.1465 +    else if (raw_w_0 == `TRUE)
  7.1466 +        bypass_data_0 = w_result;
  7.1467 +    else
  7.1468 +        bypass_data_0 = reg_data_0;
  7.1469 +end
  7.1470 +
  7.1471 +// Bypass for reg port 1
  7.1472 +always @(*)
  7.1473 +begin
  7.1474 +    if (raw_x_1 == `TRUE)
  7.1475 +        bypass_data_1 = x_result;
  7.1476 +    else if (raw_m_1 == `TRUE)
  7.1477 +        bypass_data_1 = m_result;
  7.1478 +    else if (raw_w_1 == `TRUE)
  7.1479 +        bypass_data_1 = w_result;
  7.1480 +    else
  7.1481 +        bypass_data_1 = reg_data_1;
  7.1482 +end
  7.1483 +
  7.1484 +   /*----------------------------------------------------------------------
  7.1485 +    Branch prediction is performed in D stage of pipeline. Only PC-relative
  7.1486 +    branches are predicted: forward-pointing conditional branches are not-
  7.1487 +    taken, while backward-pointing conditional branches are taken. 
  7.1488 +    Unconditional branches are always predicted taken!
  7.1489 +    ----------------------------------------------------------------------*/
  7.1490 +   assign branch_predict_d = bi_unconditional | bi_conditional;
  7.1491 +   assign branch_predict_taken_d = bi_unconditional ? 1'b1 : (bi_conditional ? instruction_d[15] : 1'b0);
  7.1492 +   
  7.1493 +   // Compute branch target address: Branch PC PLUS Offset
  7.1494 +   assign branch_target_d = pc_d + branch_offset_d;
  7.1495 +
  7.1496 +   // Compute fetch address. Address of instruction sequentially after the
  7.1497 +   // branch if branch is not taken. Target address of branch is branch is
  7.1498 +   // taken
  7.1499 +   assign branch_predict_address_d = branch_predict_taken_d ? branch_target_d : pc_f;
  7.1500 +
  7.1501 +// D stage result selection
  7.1502 +always @(*)
  7.1503 +begin
  7.1504 +    d_result_0 = d_result_sel_0_d[0] ? {pc_f, 2'b00} : bypass_data_0; 
  7.1505 +    case (d_result_sel_1_d)
  7.1506 +    `LM32_D_RESULT_SEL_1_ZERO:      d_result_1 = {`LM32_WORD_WIDTH{1'b0}};
  7.1507 +    `LM32_D_RESULT_SEL_1_REG_1:     d_result_1 = bypass_data_1;
  7.1508 +    `LM32_D_RESULT_SEL_1_IMMEDIATE: d_result_1 = immediate_d;
  7.1509 +    default:                        d_result_1 = {`LM32_WORD_WIDTH{1'bx}};
  7.1510 +    endcase
  7.1511 +end
  7.1512 +
  7.1513 +`ifdef CFG_USER_ENABLED    
  7.1514 +// Operands for user-defined instructions
  7.1515 +assign user_operand_0 = operand_0_x;
  7.1516 +assign user_operand_1 = operand_1_x;
  7.1517 +`endif
  7.1518 +
  7.1519 +`ifdef CFG_SIGN_EXTEND_ENABLED
  7.1520 +// Sign-extension
  7.1521 +assign sextb_result_x = {{24{operand_0_x[7]}}, operand_0_x[7:0]};
  7.1522 +assign sexth_result_x = {{16{operand_0_x[15]}}, operand_0_x[15:0]};
  7.1523 +assign sext_result_x = size_x == `LM32_SIZE_BYTE ? sextb_result_x : sexth_result_x;
  7.1524 +`endif
  7.1525 +
  7.1526 +`ifdef LM32_NO_BARREL_SHIFT
  7.1527 +// Only single bit shift operations are supported when barrel-shifter isn't implemented
  7.1528 +assign shifter_result_x = {operand_0_x[`LM32_WORD_WIDTH-1] & sign_extend_x, operand_0_x[`LM32_WORD_WIDTH-1:1]};
  7.1529 +`endif
  7.1530 +
  7.1531 +// Condition evaluation
  7.1532 +assign cmp_zero = operand_0_x == operand_1_x;
  7.1533 +assign cmp_negative = adder_result_x[`LM32_WORD_WIDTH-1];
  7.1534 +assign cmp_overflow = adder_overflow_x;
  7.1535 +assign cmp_carry_n = adder_carry_n_x;
  7.1536 +always @(*)
  7.1537 +begin
  7.1538 +    case (condition_x)
  7.1539 +    `LM32_CONDITION_U1:   condition_met_x = `TRUE;
  7.1540 +    `LM32_CONDITION_U2:   condition_met_x = `TRUE;
  7.1541 +    `LM32_CONDITION_E:    condition_met_x = cmp_zero;
  7.1542 +    `LM32_CONDITION_NE:   condition_met_x = !cmp_zero;
  7.1543 +    `LM32_CONDITION_G:    condition_met_x = !cmp_zero && (cmp_negative == cmp_overflow);
  7.1544 +    `LM32_CONDITION_GU:   condition_met_x = cmp_carry_n && !cmp_zero;
  7.1545 +    `LM32_CONDITION_GE:   condition_met_x = cmp_negative == cmp_overflow;
  7.1546 +    `LM32_CONDITION_GEU:  condition_met_x = cmp_carry_n;
  7.1547 +    default:              condition_met_x = 1'bx;
  7.1548 +    endcase 
  7.1549 +end
  7.1550 +
  7.1551 +// X stage result selection
  7.1552 +always @(*)
  7.1553 +begin
  7.1554 +    x_result =   x_result_sel_add_x ? adder_result_x 
  7.1555 +               : x_result_sel_csr_x ? csr_read_data_x
  7.1556 +`ifdef CFG_SIGN_EXTEND_ENABLED
  7.1557 +               : x_result_sel_sext_x ? sext_result_x
  7.1558 +`endif
  7.1559 +`ifdef CFG_USER_ENABLED
  7.1560 +               : x_result_sel_user_x ? user_result
  7.1561 +`endif
  7.1562 +`ifdef LM32_NO_BARREL_SHIFT
  7.1563 +               : x_result_sel_shift_x ? shifter_result_x
  7.1564 +`endif
  7.1565 +`ifdef LM32_MC_ARITHMETIC_ENABLED
  7.1566 +               : x_result_sel_mc_arith_x ? mc_result_x
  7.1567 +`endif
  7.1568 +               : logic_result_x;
  7.1569 +end
  7.1570 +
  7.1571 +// M stage result selection
  7.1572 +always @(*)
  7.1573 +begin
  7.1574 +    m_result =   m_result_sel_compare_m ? {{`LM32_WORD_WIDTH-1{1'b0}}, condition_met_m}
  7.1575 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  7.1576 +               : m_result_sel_shift_m ? shifter_result_m
  7.1577 +`endif
  7.1578 +               : operand_m; 
  7.1579 +end
  7.1580 +
  7.1581 +// W stage result selection
  7.1582 +always @(*)
  7.1583 +begin
  7.1584 +    w_result =    w_result_sel_load_w ? load_data_w
  7.1585 +`ifdef CFG_PL_MULTIPLY_ENABLED
  7.1586 +                : w_result_sel_mul_w ? multiplier_result_w
  7.1587 +`endif
  7.1588 +                : operand_w;
  7.1589 +end
  7.1590 +
  7.1591 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
  7.1592 +// Indicate when a branch should be taken in X stage
  7.1593 +assign branch_taken_x =      (stall_x == `FALSE)
  7.1594 +                          && (   (branch_x == `TRUE)
  7.1595 +                              && ((condition_x == `LM32_CONDITION_U1) || (condition_x == `LM32_CONDITION_U2))
  7.1596 +                              && (valid_x == `TRUE)
  7.1597 +                              && (branch_predict_x == `FALSE)
  7.1598 +                             ); 
  7.1599 +`endif
  7.1600 +
  7.1601 +// Indicate when a branch should be taken in M stage (exceptions are a type of branch)
  7.1602 +assign branch_taken_m =      (stall_m == `FALSE) 
  7.1603 +                          && (   (   (branch_m == `TRUE) 
  7.1604 +                                  && (valid_m == `TRUE)
  7.1605 +                                  && (   (   (condition_met_m == `TRUE)
  7.1606 +					  && (branch_predict_taken_m == `FALSE)
  7.1607 +					 )
  7.1608 +				      || (   (condition_met_m == `FALSE)
  7.1609 +					  && (branch_predict_m == `TRUE)
  7.1610 +					  && (branch_predict_taken_m == `TRUE)
  7.1611 +					 )
  7.1612 +				     )
  7.1613 +                                 ) 
  7.1614 +                              || (exception_m == `TRUE)
  7.1615 +                             );
  7.1616 +
  7.1617 +// Indicate when a branch in M stage is mispredicted as being taken
  7.1618 +assign branch_mispredict_taken_m =    (condition_met_m == `FALSE)
  7.1619 +                                   && (branch_predict_m == `TRUE)
  7.1620 +	   			   && (branch_predict_taken_m == `TRUE);
  7.1621 +   
  7.1622 +// Indicate when a branch in M stage will cause flush in X stage
  7.1623 +assign branch_flushX_m =    (stall_m == `FALSE)
  7.1624 +                         && (   (   (branch_m == `TRUE) 
  7.1625 +                                 && (valid_m == `TRUE)
  7.1626 +			         && (   (condition_met_m == `TRUE)
  7.1627 +				     || (   (condition_met_m == `FALSE)
  7.1628 +					 && (branch_predict_m == `TRUE)
  7.1629 +					 && (branch_predict_taken_m == `TRUE)
  7.1630 +					)
  7.1631 +				    )
  7.1632 +			        )
  7.1633 +			     || (exception_m == `TRUE)
  7.1634 +			    );
  7.1635 +
  7.1636 +// Generate signal that will kill instructions in each pipeline stage when necessary
  7.1637 +assign kill_f =    (   (valid_d == `TRUE)
  7.1638 +                    && (branch_predict_taken_d == `TRUE)
  7.1639 +		   )
  7.1640 +                || (branch_taken_m == `TRUE) 
  7.1641 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
  7.1642 +                || (branch_taken_x == `TRUE)
  7.1643 +`endif
  7.1644 +`ifdef CFG_ICACHE_ENABLED
  7.1645 +                || (icache_refill_request == `TRUE) 
  7.1646 +`endif
  7.1647 +`ifdef CFG_DCACHE_ENABLED                
  7.1648 +                || (dcache_refill_request == `TRUE)
  7.1649 +`endif
  7.1650 +                ;
  7.1651 +assign kill_d =    (branch_taken_m == `TRUE) 
  7.1652 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
  7.1653 +                || (branch_taken_x == `TRUE)
  7.1654 +`endif
  7.1655 +`ifdef CFG_ICACHE_ENABLED
  7.1656 +                || (icache_refill_request == `TRUE)     
  7.1657 +`endif                
  7.1658 +`ifdef CFG_DCACHE_ENABLED                
  7.1659 +                || (dcache_refill_request == `TRUE)
  7.1660 +`endif
  7.1661 +                ;
  7.1662 +assign kill_x =    (branch_flushX_m == `TRUE) 
  7.1663 +`ifdef CFG_DCACHE_ENABLED                
  7.1664 +                || (dcache_refill_request == `TRUE)
  7.1665 +`endif
  7.1666 +                ;
  7.1667 +assign kill_m =    `FALSE
  7.1668 +`ifdef CFG_DCACHE_ENABLED                
  7.1669 +                || (dcache_refill_request == `TRUE)
  7.1670 +`endif
  7.1671 +                ;                
  7.1672 +assign kill_w =    `FALSE
  7.1673 +`ifdef CFG_DCACHE_ENABLED                
  7.1674 +                || (dcache_refill_request == `TRUE)
  7.1675 +`endif                
  7.1676 +                ;
  7.1677 +
  7.1678 +// Exceptions
  7.1679 +
  7.1680 +`ifdef CFG_DEBUG_ENABLED
  7.1681 +assign breakpoint_exception =    (   (   (break_x == `TRUE)
  7.1682 +				      || (bp_match == `TRUE)
  7.1683 +				     )
  7.1684 +				  && (valid_x == `TRUE)
  7.1685 +				 )
  7.1686 +`ifdef CFG_JTAG_ENABLED
  7.1687 +                              || (jtag_break == `TRUE)
  7.1688 +`endif
  7.1689 +                              ;
  7.1690 +`endif
  7.1691 +
  7.1692 +`ifdef CFG_DEBUG_ENABLED
  7.1693 +assign watchpoint_exception = wp_match == `TRUE;
  7.1694 +`endif
  7.1695 +
  7.1696 +`ifdef CFG_BUS_ERRORS_ENABLED
  7.1697 +assign instruction_bus_error_exception = (   (bus_error_x == `TRUE)
  7.1698 +                                          && (valid_x == `TRUE)
  7.1699 +                                         );
  7.1700 +assign data_bus_error_exception = data_bus_error_seen == `TRUE;
  7.1701 +`endif
  7.1702 +
  7.1703 +`ifdef CFG_MC_DIVIDE_ENABLED
  7.1704 +assign divide_by_zero_exception = divide_by_zero_x == `TRUE;
  7.1705 +`endif
  7.1706 +
  7.1707 +assign system_call_exception = (   (scall_x == `TRUE)
  7.1708 +`ifdef CFG_BUS_ERRORS_ENABLED
  7.1709 +                                && (valid_x == `TRUE)
  7.1710 +`endif
  7.1711 +			       );
  7.1712 +
  7.1713 +`ifdef CFG_DEBUG_ENABLED
  7.1714 +assign debug_exception_x =  (breakpoint_exception == `TRUE)
  7.1715 +                         || (watchpoint_exception == `TRUE)
  7.1716 +                         ;
  7.1717 +
  7.1718 +assign non_debug_exception_x = (system_call_exception == `TRUE)
  7.1719 +`ifdef CFG_JTAG_ENABLED
  7.1720 +                            || (reset_exception == `TRUE)
  7.1721 +`endif
  7.1722 +`ifdef CFG_BUS_ERRORS_ENABLED
  7.1723 +                            || (instruction_bus_error_exception == `TRUE)
  7.1724 +                            || (data_bus_error_exception == `TRUE)
  7.1725 +`endif
  7.1726 +`ifdef CFG_MC_DIVIDE_ENABLED
  7.1727 +                            || (divide_by_zero_exception == `TRUE)
  7.1728 +`endif
  7.1729 +`ifdef CFG_INTERRUPTS_ENABLED
  7.1730 +                            || (   (interrupt_exception == `TRUE)
  7.1731 +`ifdef LM32_SINGLE_STEP_ENABLED
  7.1732 +                                && (dc_ss == `FALSE)
  7.1733 +`endif                            
  7.1734 +`ifdef CFG_BUS_ERRORS_ENABLED
  7.1735 + 				&& (store_q_m == `FALSE)
  7.1736 +				&& (D_CYC_O == `FALSE)
  7.1737 +`endif
  7.1738 +                               )
  7.1739 +`endif
  7.1740 +                            ;
  7.1741 +
  7.1742 +assign exception_x = (debug_exception_x == `TRUE) || (non_debug_exception_x == `TRUE);
  7.1743 +`else
  7.1744 +assign exception_x =           (system_call_exception == `TRUE)
  7.1745 +`ifdef CFG_BUS_ERRORS_ENABLED
  7.1746 +                            || (instruction_bus_error_exception == `TRUE)
  7.1747 +                            || (data_bus_error_exception == `TRUE)
  7.1748 +`endif
  7.1749 +`ifdef CFG_MC_DIVIDE_ENABLED
  7.1750 +                            || (divide_by_zero_exception == `TRUE)
  7.1751 +`endif
  7.1752 +`ifdef CFG_INTERRUPTS_ENABLED
  7.1753 +                            || (   (interrupt_exception == `TRUE)
  7.1754 +`ifdef LM32_SINGLE_STEP_ENABLED
  7.1755 +                                && (dc_ss == `FALSE)
  7.1756 +`endif                            
  7.1757 +`ifdef CFG_BUS_ERRORS_ENABLED
  7.1758 + 				&& (store_q_m == `FALSE)
  7.1759 +				&& (D_CYC_O == `FALSE)
  7.1760 +`endif
  7.1761 +                               )
  7.1762 +`endif
  7.1763 +                            ;
  7.1764 +`endif
  7.1765 +
  7.1766 +// Exception ID
  7.1767 +always @(*)
  7.1768 +begin
  7.1769 +`ifdef CFG_DEBUG_ENABLED
  7.1770 +`ifdef CFG_JTAG_ENABLED
  7.1771 +    if (reset_exception == `TRUE)
  7.1772 +        eid_x = `LM32_EID_RESET;
  7.1773 +    else
  7.1774 +`endif     
  7.1775 +`ifdef CFG_BUS_ERRORS_ENABLED
  7.1776 +         if (data_bus_error_exception == `TRUE)
  7.1777 +        eid_x = `LM32_EID_DATA_BUS_ERROR;
  7.1778 +    else
  7.1779 +`endif
  7.1780 +         if (breakpoint_exception == `TRUE)
  7.1781 +        eid_x = `LM32_EID_BREAKPOINT;
  7.1782 +    else
  7.1783 +`endif
  7.1784 +`ifdef CFG_BUS_ERRORS_ENABLED
  7.1785 +         if (data_bus_error_exception == `TRUE)
  7.1786 +        eid_x = `LM32_EID_DATA_BUS_ERROR;
  7.1787 +    else
  7.1788 +         if (instruction_bus_error_exception == `TRUE)
  7.1789 +        eid_x = `LM32_EID_INST_BUS_ERROR;
  7.1790 +    else
  7.1791 +`endif
  7.1792 +`ifdef CFG_DEBUG_ENABLED
  7.1793 +         if (watchpoint_exception == `TRUE)
  7.1794 +        eid_x = `LM32_EID_WATCHPOINT;
  7.1795 +    else 
  7.1796 +`endif
  7.1797 +`ifdef CFG_MC_DIVIDE_ENABLED
  7.1798 +         if (divide_by_zero_exception == `TRUE)
  7.1799 +        eid_x = `LM32_EID_DIVIDE_BY_ZERO;
  7.1800 +    else
  7.1801 +`endif
  7.1802 +`ifdef CFG_INTERRUPTS_ENABLED
  7.1803 +         if (   (interrupt_exception == `TRUE)
  7.1804 +`ifdef LM32_SINGLE_STEP_ENABLED
  7.1805 +             && (dc_ss == `FALSE)
  7.1806 +`endif                            
  7.1807 +            )
  7.1808 +        eid_x = `LM32_EID_INTERRUPT;
  7.1809 +    else
  7.1810 +`endif
  7.1811 +        eid_x = `LM32_EID_SCALL;
  7.1812 +end
  7.1813 +
  7.1814 +// Stall generation
  7.1815 +
  7.1816 +assign stall_a = (stall_f == `TRUE);
  7.1817 +                
  7.1818 +assign stall_f = (stall_d == `TRUE);
  7.1819 +                
  7.1820 +assign stall_d =   (stall_x == `TRUE) 
  7.1821 +                || (   (interlock == `TRUE)
  7.1822 +                    && (kill_d == `FALSE)
  7.1823 +                   ) 
  7.1824 +		|| (   (   (eret_d == `TRUE)
  7.1825 +			|| (scall_d == `TRUE)
  7.1826 +			|| (bus_error_d == `TRUE)
  7.1827 +		       )
  7.1828 +		    && (   (load_q_x == `TRUE)
  7.1829 +			|| (load_q_m == `TRUE)
  7.1830 +			|| (store_q_x == `TRUE)
  7.1831 +			|| (store_q_m == `TRUE)
  7.1832 +			|| (D_CYC_O == `TRUE)
  7.1833 +		       )
  7.1834 +                    && (kill_d == `FALSE)
  7.1835 +		   )
  7.1836 +`ifdef CFG_DEBUG_ENABLED
  7.1837 +		|| (   (   (break_d == `TRUE)
  7.1838 +			|| (bret_d == `TRUE)
  7.1839 +		       )
  7.1840 +		    && (   (load_q_x == `TRUE)
  7.1841 +			|| (store_q_x == `TRUE)
  7.1842 +			|| (load_q_m == `TRUE)
  7.1843 +			|| (store_q_m == `TRUE)
  7.1844 +			|| (D_CYC_O == `TRUE)
  7.1845 +		       )
  7.1846 +                    && (kill_d == `FALSE)
  7.1847 +		   )
  7.1848 +`endif                   
  7.1849 +                || (   (csr_write_enable_d == `TRUE)
  7.1850 +                    && (load_q_x == `TRUE)
  7.1851 +                   )                      
  7.1852 +                ;
  7.1853 +                
  7.1854 +assign stall_x =    (stall_m == `TRUE)
  7.1855 +`ifdef LM32_MC_ARITHMETIC_ENABLED
  7.1856 +                 || (   (mc_stall_request_x == `TRUE)
  7.1857 +                     && (kill_x == `FALSE)
  7.1858 +                    ) 
  7.1859 +`endif
  7.1860 +`ifdef CFG_IROM_ENABLED
  7.1861 +                 // Stall load/store instruction in D stage if there is an ongoing store
  7.1862 +                 // operation to instruction ROM in M stage
  7.1863 +                 || (   (irom_stall_request_x == `TRUE)
  7.1864 +		     && (   (load_d == `TRUE)
  7.1865 +			 || (store_d == `TRUE)
  7.1866 +			)
  7.1867 +		    )
  7.1868 +`endif
  7.1869 +                 ;
  7.1870 +
  7.1871 +assign stall_m =    (stall_wb_load == `TRUE)
  7.1872 +`ifdef CFG_SIZE_OVER_SPEED
  7.1873 +                 || (D_CYC_O == `TRUE)
  7.1874 +`else
  7.1875 +                 || (   (D_CYC_O == `TRUE)
  7.1876 +                     && (   (store_m == `TRUE)
  7.1877 +		         /*
  7.1878 +			  Bug: Following loop does not allow interrupts to be services since
  7.1879 +			  either D_CYC_O or store_m is always high during entire duration of
  7.1880 +			  loop.
  7.1881 +		          L1:	addi	r1, r1, 1
  7.1882 +			  	sw	(r2,0), r1
  7.1883 +			  	bi	L1
  7.1884 +			  
  7.1885 +			  Introduce a single-cycle stall when a wishbone cycle is in progress
  7.1886 +			  and a new store instruction is in Execute stage and a interrupt
  7.1887 +			  exception has occured. This stall will ensure that D_CYC_O and 
  7.1888 +			  store_m will both be low for one cycle.
  7.1889 +			  */
  7.1890 +		         || ((store_x == `TRUE) && (interrupt_exception == `TRUE))
  7.1891 +                         || (load_m == `TRUE)
  7.1892 +                         || (load_x == `TRUE)
  7.1893 +                        ) 
  7.1894 +                    ) 
  7.1895 +`endif                 
  7.1896 +`ifdef CFG_DCACHE_ENABLED
  7.1897 +                 || (dcache_stall_request == `TRUE)     // Need to stall in case a taken branch is in M stage and data cache is only being flush, so wont be restarted
  7.1898 +`endif                                    
  7.1899 +`ifdef CFG_ICACHE_ENABLED
  7.1900 +                 || (icache_stall_request == `TRUE)     // Pipeline needs to be stalled otherwise branches may be lost
  7.1901 +                 || ((I_CYC_O == `TRUE) && ((branch_m == `TRUE) || (exception_m == `TRUE))) 
  7.1902 +`else
  7.1903 +`ifdef CFG_IWB_ENABLED
  7.1904 +                 || (I_CYC_O == `TRUE)            
  7.1905 +`endif
  7.1906 +`endif                               
  7.1907 +`ifdef CFG_USER_ENABLED
  7.1908 +                 || (   (user_valid == `TRUE)           // Stall whole pipeline, rather than just X stage, where the instruction is, so we don't have to worry about exceptions (maybe)
  7.1909 +                     && (user_complete == `FALSE)
  7.1910 +                    )
  7.1911 +`endif
  7.1912 +                 ;      
  7.1913 +
  7.1914 +// Qualify state changing control signals
  7.1915 +`ifdef LM32_MC_ARITHMETIC_ENABLED
  7.1916 +assign q_d = (valid_d == `TRUE) && (kill_d == `FALSE);
  7.1917 +`endif
  7.1918 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED
  7.1919 +assign shift_left_q_d = (shift_left_d == `TRUE) && (q_d == `TRUE);
  7.1920 +assign shift_right_q_d = (shift_right_d == `TRUE) && (q_d == `TRUE);
  7.1921 +`endif
  7.1922 +`ifdef CFG_MC_MULTIPLY_ENABLED
  7.1923 +assign multiply_q_d = (multiply_d == `TRUE) && (q_d == `TRUE);
  7.1924 +`endif
  7.1925 +`ifdef CFG_MC_DIVIDE_ENABLED
  7.1926 +assign divide_q_d = (divide_d == `TRUE) && (q_d == `TRUE);
  7.1927 +assign modulus_q_d = (modulus_d == `TRUE) && (q_d == `TRUE);
  7.1928 +`endif
  7.1929 +assign q_x = (valid_x == `TRUE) && (kill_x == `FALSE);
  7.1930 +assign csr_write_enable_q_x = (csr_write_enable_x == `TRUE) && (q_x == `TRUE);
  7.1931 +assign eret_q_x = (eret_x == `TRUE) && (q_x == `TRUE);
  7.1932 +`ifdef CFG_DEBUG_ENABLED
  7.1933 +assign bret_q_x = (bret_x == `TRUE) && (q_x == `TRUE);
  7.1934 +`endif
  7.1935 +assign load_q_x = (load_x == `TRUE) 
  7.1936 +               && (q_x == `TRUE)
  7.1937 +`ifdef CFG_DEBUG_ENABLED
  7.1938 +               && (bp_match == `FALSE)
  7.1939 +`endif
  7.1940 +                  ;
  7.1941 +assign store_q_x = (store_x == `TRUE) 
  7.1942 +               && (q_x == `TRUE)
  7.1943 +`ifdef CFG_DEBUG_ENABLED
  7.1944 +               && (bp_match == `FALSE)
  7.1945 +`endif
  7.1946 +                  ;
  7.1947 +`ifdef CFG_USER_ENABLED
  7.1948 +assign user_valid = (x_result_sel_user_x == `TRUE) && (q_x == `TRUE);
  7.1949 +`endif                              
  7.1950 +assign q_m = (valid_m == `TRUE) && (kill_m == `FALSE) && (exception_m == `FALSE);
  7.1951 +assign load_q_m = (load_m == `TRUE) && (q_m == `TRUE);
  7.1952 +assign store_q_m = (store_m == `TRUE) && (q_m == `TRUE);
  7.1953 +`ifdef CFG_DEBUG_ENABLED
  7.1954 +assign debug_exception_q_w = ((debug_exception_w == `TRUE) && (valid_w == `TRUE));
  7.1955 +assign non_debug_exception_q_w = ((non_debug_exception_w == `TRUE) && (valid_w == `TRUE));        
  7.1956 +`else
  7.1957 +assign exception_q_w = ((exception_w == `TRUE) && (valid_w == `TRUE));        
  7.1958 +`endif
  7.1959 +// Don't qualify register write enables with kill, as the signal is needed early, and it doesn't matter if the instruction is killed (except for the actual write - but that is handled separately)
  7.1960 +assign write_enable_q_x = (write_enable_x == `TRUE) && (valid_x == `TRUE) && (branch_flushX_m == `FALSE);
  7.1961 +assign write_enable_q_m = (write_enable_m == `TRUE) && (valid_m == `TRUE);
  7.1962 +assign write_enable_q_w = (write_enable_w == `TRUE) && (valid_w == `TRUE);
  7.1963 +// The enable that actually does write the registers needs to be qualified with kill
  7.1964 +assign reg_write_enable_q_w = (write_enable_w == `TRUE) && (kill_w == `FALSE) && (valid_w == `TRUE);
  7.1965 +
  7.1966 +// Configuration (CFG) CSR
  7.1967 +assign cfg = {
  7.1968 +              `LM32_REVISION,
  7.1969 +              watchpoints[3:0],
  7.1970 +              breakpoints[3:0],
  7.1971 +              interrupts[5:0],
  7.1972 +`ifdef CFG_JTAG_UART_ENABLED
  7.1973 +              `TRUE,
  7.1974 +`else
  7.1975 +              `FALSE,
  7.1976 +`endif
  7.1977 +`ifdef CFG_ROM_DEBUG_ENABLED
  7.1978 +              `TRUE,
  7.1979 +`else
  7.1980 +              `FALSE,
  7.1981 +`endif
  7.1982 +`ifdef CFG_HW_DEBUG_ENABLED
  7.1983 +              `TRUE,
  7.1984 +`else
  7.1985 +              `FALSE,
  7.1986 +`endif
  7.1987 +`ifdef CFG_DEBUG_ENABLED
  7.1988 +              `TRUE,
  7.1989 +`else
  7.1990 +              `FALSE,
  7.1991 +`endif
  7.1992 +`ifdef CFG_ICACHE_ENABLED
  7.1993 +              `TRUE,
  7.1994 +`else
  7.1995 +              `FALSE,
  7.1996 +`endif
  7.1997 +`ifdef CFG_DCACHE_ENABLED
  7.1998 +              `TRUE,
  7.1999 +`else
  7.2000 +              `FALSE,
  7.2001 +`endif
  7.2002 +`ifdef CFG_CYCLE_COUNTER_ENABLED
  7.2003 +              `TRUE,
  7.2004 +`else
  7.2005 +              `FALSE,
  7.2006 +`endif
  7.2007 +`ifdef CFG_USER_ENABLED
  7.2008 +              `TRUE,
  7.2009 +`else
  7.2010 +              `FALSE,
  7.2011 +`endif
  7.2012 +`ifdef CFG_SIGN_EXTEND_ENABLED
  7.2013 +              `TRUE,
  7.2014 +`else
  7.2015 +              `FALSE,
  7.2016 +`endif
  7.2017 +`ifdef LM32_BARREL_SHIFT_ENABLED
  7.2018 +              `TRUE,
  7.2019 +`else
  7.2020 +              `FALSE,
  7.2021 +`endif
  7.2022 +`ifdef CFG_MC_DIVIDE_ENABLED
  7.2023 +              `TRUE,
  7.2024 +`else
  7.2025 +              `FALSE,
  7.2026 +`endif
  7.2027 +`ifdef LM32_MULTIPLY_ENABLED 
  7.2028 +              `TRUE
  7.2029 +`else
  7.2030 +              `FALSE
  7.2031 +`endif
  7.2032 +              };
  7.2033 +
  7.2034 +assign cfg2 = {
  7.2035 +		     30'b0,
  7.2036 +`ifdef CFG_IROM_ENABLED
  7.2037 +		     `TRUE,
  7.2038 +`else
  7.2039 +		     `FALSE,
  7.2040 +`endif
  7.2041 +`ifdef CFG_DRAM_ENABLED
  7.2042 +		     `TRUE
  7.2043 +`else
  7.2044 +		     `FALSE
  7.2045 +`endif
  7.2046 +		     };
  7.2047 +   
  7.2048 +// Cache flush
  7.2049 +`ifdef CFG_ICACHE_ENABLED
  7.2050 +assign iflush =    (csr_write_enable_d == `TRUE) 
  7.2051 +                && (csr_d == `LM32_CSR_ICC)
  7.2052 +                && (stall_d == `FALSE)
  7.2053 +                && (kill_d == `FALSE)
  7.2054 +                && (valid_d == `TRUE);
  7.2055 +`endif 
  7.2056 +`ifdef CFG_DCACHE_ENABLED
  7.2057 +assign dflush_x =  (csr_write_enable_q_x == `TRUE) 
  7.2058 +                && (csr_x == `LM32_CSR_DCC);
  7.2059 +`endif 
  7.2060 +
  7.2061 +// Extract CSR index
  7.2062 +assign csr_d = read_idx_0_d[`LM32_CSR_RNG];
  7.2063 +
  7.2064 +// CSR reads
  7.2065 +always @(*)
  7.2066 +begin
  7.2067 +    case (csr_x)
  7.2068 +`ifdef CFG_INTERRUPTS_ENABLED
  7.2069 +    `LM32_CSR_IE,
  7.2070 +    `LM32_CSR_IM,
  7.2071 +    `LM32_CSR_IP:   csr_read_data_x = interrupt_csr_read_data_x;  
  7.2072 +`endif
  7.2073 +`ifdef CFG_CYCLE_COUNTER_ENABLED
  7.2074 +    `LM32_CSR_CC:   csr_read_data_x = cc;
  7.2075 +`endif
  7.2076 +    `LM32_CSR_CFG:  csr_read_data_x = cfg;
  7.2077 +    `LM32_CSR_EBA:  csr_read_data_x = {eba, 8'h00};
  7.2078 +`ifdef CFG_DEBUG_ENABLED
  7.2079 +    `LM32_CSR_DEBA: csr_read_data_x = {deba, 8'h00};
  7.2080 +`endif
  7.2081 +`ifdef CFG_JTAG_UART_ENABLED
  7.2082 +    `LM32_CSR_JTX:  csr_read_data_x = jtx_csr_read_data;  
  7.2083 +    `LM32_CSR_JRX:  csr_read_data_x = jrx_csr_read_data;
  7.2084 +`endif
  7.2085 +    `LM32_CSR_CFG2: csr_read_data_x = cfg2;
  7.2086 +      
  7.2087 +    default:        csr_read_data_x = {`LM32_WORD_WIDTH{1'bx}};
  7.2088 +    endcase
  7.2089 +end
  7.2090 +
  7.2091 +/////////////////////////////////////////////////////
  7.2092 +// Sequential Logic
  7.2093 +/////////////////////////////////////////////////////
  7.2094 +
  7.2095 +// Exception Base Address (EBA) CSR
  7.2096 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  7.2097 +begin
  7.2098 +    if (rst_i == `TRUE)
  7.2099 +        eba <= eba_reset[`LM32_PC_WIDTH+2-1:8];
  7.2100 +    else
  7.2101 +    begin
  7.2102 +        if ((csr_write_enable_q_x == `TRUE) && (csr_x == `LM32_CSR_EBA) && (stall_x == `FALSE))
  7.2103 +            eba <= operand_1_x[`LM32_PC_WIDTH+2-1:8];
  7.2104 +`ifdef CFG_HW_DEBUG_ENABLED
  7.2105 +        if ((jtag_csr_write_enable == `TRUE) && (jtag_csr == `LM32_CSR_EBA))
  7.2106 +            eba <= jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8];
  7.2107 +`endif
  7.2108 +    end
  7.2109 +end
  7.2110 +
  7.2111 +`ifdef CFG_DEBUG_ENABLED
  7.2112 +// Debug Exception Base Address (DEBA) CSR
  7.2113 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  7.2114 +begin
  7.2115 +    if (rst_i == `TRUE)
  7.2116 +        deba <= deba_reset[`LM32_PC_WIDTH+2-1:8];
  7.2117 +    else
  7.2118 +    begin
  7.2119 +        if ((csr_write_enable_q_x == `TRUE) && (csr_x == `LM32_CSR_DEBA) && (stall_x == `FALSE))
  7.2120 +            deba <= operand_1_x[`LM32_PC_WIDTH+2-1:8];
  7.2121 +`ifdef CFG_HW_DEBUG_ENABLED
  7.2122 +        if ((jtag_csr_write_enable == `TRUE) && (jtag_csr == `LM32_CSR_DEBA))
  7.2123 +            deba <= jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8];
  7.2124 +`endif
  7.2125 +    end
  7.2126 +end
  7.2127 +`endif
  7.2128 +
  7.2129 +// Cycle Counter (CC) CSR
  7.2130 +`ifdef CFG_CYCLE_COUNTER_ENABLED
  7.2131 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  7.2132 +begin
  7.2133 +    if (rst_i == `TRUE)
  7.2134 +        cc <= {`LM32_WORD_WIDTH{1'b0}};
  7.2135 +    else
  7.2136 +        cc <= cc + 1'b1;
  7.2137 +end
  7.2138 +`endif
  7.2139 +
  7.2140 +`ifdef CFG_BUS_ERRORS_ENABLED
  7.2141 +// Watch for data bus errors
  7.2142 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  7.2143 +begin
  7.2144 +    if (rst_i == `TRUE)
  7.2145 +        data_bus_error_seen <= `FALSE;
  7.2146 +    else
  7.2147 +    begin
  7.2148 +        // Set flag when bus error is detected
  7.2149 +        if ((D_ERR_I == `TRUE) && (D_CYC_O == `TRUE))
  7.2150 +            data_bus_error_seen <= `TRUE;
  7.2151 +        // Clear flag when exception is taken
  7.2152 +        if ((exception_m == `TRUE) && (kill_m == `FALSE))
  7.2153 +            data_bus_error_seen <= `FALSE;
  7.2154 +    end
  7.2155 +end
  7.2156 +`endif
  7.2157 + 
  7.2158 +// Valid bits to indicate whether an instruction in a partcular pipeline stage is valid or not  
  7.2159 +
  7.2160 +`ifdef CFG_ICACHE_ENABLED
  7.2161 +`ifdef CFG_DCACHE_ENABLED
  7.2162 +always @(*)
  7.2163 +begin
  7.2164 +    if (   (icache_refill_request == `TRUE) 
  7.2165 +        || (dcache_refill_request == `TRUE)
  7.2166 +       )
  7.2167 +        valid_a = `FALSE;
  7.2168 +    else if (   (icache_restart_request == `TRUE) 
  7.2169 +             || (dcache_restart_request == `TRUE) 
  7.2170 +            ) 
  7.2171 +        valid_a = `TRUE;
  7.2172 +    else 
  7.2173 +        valid_a = !icache_refilling && !dcache_refilling;
  7.2174 +end 
  7.2175 +`else
  7.2176 +always @(*)
  7.2177 +begin
  7.2178 +    if (icache_refill_request == `TRUE) 
  7.2179 +        valid_a = `FALSE;
  7.2180 +    else if (icache_restart_request == `TRUE) 
  7.2181 +        valid_a = `TRUE;
  7.2182 +    else 
  7.2183 +        valid_a = !icache_refilling;
  7.2184 +end 
  7.2185 +`endif
  7.2186 +`else
  7.2187 +`ifdef CFG_DCACHE_ENABLED
  7.2188 +always @(*)
  7.2189 +begin
  7.2190 +    if (dcache_refill_request == `TRUE) 
  7.2191 +        valid_a = `FALSE;
  7.2192 +    else if (dcache_restart_request == `TRUE) 
  7.2193 +        valid_a = `TRUE;
  7.2194 +    else 
  7.2195 +        valid_a = !dcache_refilling;
  7.2196 +end 
  7.2197 +`endif
  7.2198 +`endif
  7.2199 +
  7.2200 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  7.2201 +begin
  7.2202 +    if (rst_i == `TRUE)
  7.2203 +    begin
  7.2204 +        valid_f <= `FALSE;
  7.2205 +        valid_d <= `FALSE;
  7.2206 +        valid_x <= `FALSE;
  7.2207 +        valid_m <= `FALSE;
  7.2208 +        valid_w <= `FALSE;
  7.2209 +    end
  7.2210 +    else
  7.2211 +    begin    
  7.2212 +        if ((kill_f == `TRUE) || (stall_a == `FALSE))
  7.2213 +`ifdef LM32_CACHE_ENABLED
  7.2214 +            valid_f <= valid_a;    
  7.2215 +`else
  7.2216 +            valid_f <= `TRUE;
  7.2217 +`endif            
  7.2218 +        else if (stall_f == `FALSE)
  7.2219 +            valid_f <= `FALSE;            
  7.2220 +
  7.2221 +        if (kill_d == `TRUE)
  7.2222 +            valid_d <= `FALSE;
  7.2223 +        else if (stall_f == `FALSE)
  7.2224 +            valid_d <= valid_f & !kill_f;
  7.2225 +        else if (stall_d == `FALSE)
  7.2226 +            valid_d <= `FALSE;
  7.2227 +       
  7.2228 +        if (stall_d == `FALSE)
  7.2229 +            valid_x <= valid_d & !kill_d;
  7.2230 +        else if (kill_x == `TRUE)
  7.2231 +            valid_x <= `FALSE;
  7.2232 +        else if (stall_x == `FALSE)
  7.2233 +            valid_x <= `FALSE;
  7.2234 +
  7.2235 +        if (kill_m == `TRUE)
  7.2236 +            valid_m <= `FALSE;
  7.2237 +        else if (stall_x == `FALSE)
  7.2238 +            valid_m <= valid_x & !kill_x;
  7.2239 +        else if (stall_m == `FALSE)
  7.2240 +            valid_m <= `FALSE;
  7.2241 +
  7.2242 +        if (stall_m == `FALSE)
  7.2243 +            valid_w <= valid_m & !kill_m;
  7.2244 +        else 
  7.2245 +            valid_w <= `FALSE;        
  7.2246 +    end
  7.2247 +end
  7.2248 +
  7.2249 +// Microcode pipeline registers
  7.2250 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  7.2251 +begin
  7.2252 +    if (rst_i == `TRUE)
  7.2253 +    begin
  7.2254 +`ifdef CFG_USER_ENABLED
  7.2255 +        user_opcode <= {`LM32_USER_OPCODE_WIDTH{1'b0}};       
  7.2256 +`endif        
  7.2257 +        operand_0_x <= {`LM32_WORD_WIDTH{1'b0}};
  7.2258 +        operand_1_x <= {`LM32_WORD_WIDTH{1'b0}};
  7.2259 +        store_operand_x <= {`LM32_WORD_WIDTH{1'b0}};
  7.2260 +        branch_target_x <= {`LM32_WORD_WIDTH{1'b0}};        
  7.2261 +        x_result_sel_csr_x <= `FALSE;
  7.2262 +`ifdef LM32_MC_ARITHMETIC_ENABLED
  7.2263 +        x_result_sel_mc_arith_x <= `FALSE;
  7.2264 +`endif
  7.2265 +`ifdef LM32_NO_BARREL_SHIFT    
  7.2266 +        x_result_sel_shift_x <= `FALSE;
  7.2267 +`endif
  7.2268 +`ifdef CFG_SIGN_EXTEND_ENABLED
  7.2269 +        x_result_sel_sext_x <= `FALSE;
  7.2270 +`endif    
  7.2271 +        x_result_sel_logic_x <= `FALSE;
  7.2272 +`ifdef CFG_USER_ENABLED
  7.2273 +        x_result_sel_user_x <= `FALSE;
  7.2274 +`endif
  7.2275 +        x_result_sel_add_x <= `FALSE;
  7.2276 +        m_result_sel_compare_x <= `FALSE;
  7.2277 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  7.2278 +        m_result_sel_shift_x <= `FALSE;
  7.2279 +`endif    
  7.2280 +        w_result_sel_load_x <= `FALSE;
  7.2281 +`ifdef CFG_PL_MULTIPLY_ENABLED
  7.2282 +        w_result_sel_mul_x <= `FALSE;
  7.2283 +`endif
  7.2284 +        x_bypass_enable_x <= `FALSE;
  7.2285 +        m_bypass_enable_x <= `FALSE;
  7.2286 +        write_enable_x <= `FALSE;
  7.2287 +        write_idx_x <= {`LM32_REG_IDX_WIDTH{1'b0}};
  7.2288 +        csr_x <= {`LM32_CSR_WIDTH{1'b0}};
  7.2289 +        load_x <= `FALSE;
  7.2290 +        store_x <= `FALSE;
  7.2291 +        size_x <= {`LM32_SIZE_WIDTH{1'b0}};
  7.2292 +        sign_extend_x <= `FALSE;
  7.2293 +        adder_op_x <= `FALSE;
  7.2294 +        adder_op_x_n <= `FALSE;
  7.2295 +        logic_op_x <= 4'h0;
  7.2296 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  7.2297 +        direction_x <= `FALSE;
  7.2298 +`endif
  7.2299 +`ifdef CFG_ROTATE_ENABLED
  7.2300 +        rotate_x <= `FALSE;
  7.2301 +
  7.2302 +`endif
  7.2303 +        branch_x <= `FALSE;
  7.2304 +        branch_predict_x <= `FALSE;
  7.2305 +        branch_predict_taken_x <= `FALSE;
  7.2306 +        condition_x <= `LM32_CONDITION_U1;
  7.2307 +`ifdef CFG_DEBUG_ENABLED
  7.2308 +        break_x <= `FALSE;
  7.2309 +`endif
  7.2310 +        scall_x <= `FALSE;
  7.2311 +        eret_x <= `FALSE;
  7.2312 +`ifdef CFG_DEBUG_ENABLED
  7.2313 +        bret_x <= `FALSE;
  7.2314 +`endif
  7.2315 +`ifdef CFG_BUS_ERRORS_ENABLED
  7.2316 +        bus_error_x <= `FALSE;
  7.2317 +        data_bus_error_exception_m <= `FALSE;
  7.2318 +`endif
  7.2319 +        csr_write_enable_x <= `FALSE;
  7.2320 +        operand_m <= {`LM32_WORD_WIDTH{1'b0}};
  7.2321 +        branch_target_m <= {`LM32_WORD_WIDTH{1'b0}};
  7.2322 +        m_result_sel_compare_m <= `FALSE;
  7.2323 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  7.2324 +        m_result_sel_shift_m <= `FALSE;
  7.2325 +`endif    
  7.2326 +        w_result_sel_load_m <= `FALSE;
  7.2327 +`ifdef CFG_PL_MULTIPLY_ENABLED
  7.2328 +        w_result_sel_mul_m <= `FALSE;
  7.2329 +`endif
  7.2330 +        m_bypass_enable_m <= `FALSE;
  7.2331 +        branch_m <= `FALSE;
  7.2332 +        branch_predict_m <= `FALSE;
  7.2333 +	branch_predict_taken_m <= `FALSE;
  7.2334 +        exception_m <= `FALSE;
  7.2335 +        load_m <= `FALSE;
  7.2336 +        store_m <= `FALSE;
  7.2337 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  7.2338 +        direction_m <= `FALSE;
  7.2339 +`endif
  7.2340 +        write_enable_m <= `FALSE;            
  7.2341 +        write_idx_m <= {`LM32_REG_IDX_WIDTH{1'b0}};
  7.2342 +        condition_met_m <= `FALSE;
  7.2343 +`ifdef CFG_DCACHE_ENABLED
  7.2344 +        dflush_m <= `FALSE;
  7.2345 +`endif
  7.2346 +`ifdef CFG_DEBUG_ENABLED
  7.2347 +        debug_exception_m <= `FALSE;
  7.2348 +        non_debug_exception_m <= `FALSE;        
  7.2349 +`endif
  7.2350 +        operand_w <= {`LM32_WORD_WIDTH{1'b0}};        
  7.2351 +        w_result_sel_load_w <= `FALSE;
  7.2352 +`ifdef CFG_PL_MULTIPLY_ENABLED
  7.2353 +        w_result_sel_mul_w <= `FALSE;
  7.2354 +`endif
  7.2355 +        write_idx_w <= {`LM32_REG_IDX_WIDTH{1'b0}};        
  7.2356 +        write_enable_w <= `FALSE;
  7.2357 +`ifdef CFG_DEBUG_ENABLED
  7.2358 +        debug_exception_w <= `FALSE;
  7.2359 +        non_debug_exception_w <= `FALSE;        
  7.2360 +`else
  7.2361 +        exception_w <= `FALSE;
  7.2362 +`endif
  7.2363 +`ifdef CFG_BUS_ERRORS_ENABLED
  7.2364 +        memop_pc_w <= {`LM32_PC_WIDTH{1'b0}};
  7.2365 +`endif
  7.2366 +    end
  7.2367 +    else
  7.2368 +    begin
  7.2369 +        // D/X stage registers
  7.2370 +       
  7.2371 +        if (stall_x == `FALSE)
  7.2372 +        begin
  7.2373 +`ifdef CFG_USER_ENABLED
  7.2374 +            user_opcode <= user_opcode_d;       
  7.2375 +`endif        
  7.2376 +            operand_0_x <= d_result_0;
  7.2377 +            operand_1_x <= d_result_1;
  7.2378 +            store_operand_x <= bypass_data_1;
  7.2379 +            branch_target_x <= branch_reg_d == `TRUE ? bypass_data_0[`LM32_PC_RNG] : branch_target_d;            
  7.2380 +            x_result_sel_csr_x <= x_result_sel_csr_d;
  7.2381 +`ifdef LM32_MC_ARITHMETIC_ENABLED
  7.2382 +            x_result_sel_mc_arith_x <= x_result_sel_mc_arith_d;
  7.2383 +`endif
  7.2384 +`ifdef LM32_NO_BARREL_SHIFT    
  7.2385 +            x_result_sel_shift_x <= x_result_sel_shift_d;
  7.2386 +`endif
  7.2387 +`ifdef CFG_SIGN_EXTEND_ENABLED
  7.2388 +            x_result_sel_sext_x <= x_result_sel_sext_d;
  7.2389 +`endif    
  7.2390 +            x_result_sel_logic_x <= x_result_sel_logic_d;
  7.2391 +`ifdef CFG_USER_ENABLED
  7.2392 +            x_result_sel_user_x <= x_result_sel_user_d;
  7.2393 +`endif
  7.2394 +            x_result_sel_add_x <= x_result_sel_add_d;
  7.2395 +            m_result_sel_compare_x <= m_result_sel_compare_d;
  7.2396 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  7.2397 +            m_result_sel_shift_x <= m_result_sel_shift_d;
  7.2398 +`endif    
  7.2399 +            w_result_sel_load_x <= w_result_sel_load_d;
  7.2400 +`ifdef CFG_PL_MULTIPLY_ENABLED
  7.2401 +            w_result_sel_mul_x <= w_result_sel_mul_d;
  7.2402 +`endif
  7.2403 +            x_bypass_enable_x <= x_bypass_enable_d;
  7.2404 +            m_bypass_enable_x <= m_bypass_enable_d;
  7.2405 +            load_x <= load_d;
  7.2406 +            store_x <= store_d;
  7.2407 +            branch_x <= branch_d;
  7.2408 +	    branch_predict_x <= branch_predict_d;
  7.2409 +	    branch_predict_taken_x <= branch_predict_taken_d;
  7.2410 +	    write_idx_x <= write_idx_d;
  7.2411 +            csr_x <= csr_d;
  7.2412 +            size_x <= size_d;
  7.2413 +            sign_extend_x <= sign_extend_d;
  7.2414 +            adder_op_x <= adder_op_d;
  7.2415 +            adder_op_x_n <= ~adder_op_d;
  7.2416 +            logic_op_x <= logic_op_d;
  7.2417 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  7.2418 +            direction_x <= direction_d;
  7.2419 +`endif
  7.2420 +`ifdef CFG_ROTATE_ENABLED
  7.2421 +            rotate_x <= rotate_d;
  7.2422 +`endif
  7.2423 +            condition_x <= condition_d;
  7.2424 +            csr_write_enable_x <= csr_write_enable_d;
  7.2425 +`ifdef CFG_DEBUG_ENABLED
  7.2426 +            break_x <= break_d;
  7.2427 +`endif
  7.2428 +            scall_x <= scall_d;
  7.2429 +`ifdef CFG_BUS_ERRORS_ENABLED
  7.2430 +            bus_error_x <= bus_error_d;
  7.2431 +`endif
  7.2432 +            eret_x <= eret_d;
  7.2433 +`ifdef CFG_DEBUG_ENABLED
  7.2434 +            bret_x <= bret_d; 
  7.2435 +`endif
  7.2436 +            write_enable_x <= write_enable_d;
  7.2437 +        end
  7.2438 +        
  7.2439 +        // X/M stage registers
  7.2440 +
  7.2441 +        if (stall_m == `FALSE)
  7.2442 +        begin
  7.2443 +            operand_m <= x_result;
  7.2444 +            m_result_sel_compare_m <= m_result_sel_compare_x;
  7.2445 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  7.2446 +            m_result_sel_shift_m <= m_result_sel_shift_x;
  7.2447 +`endif    
  7.2448 +            if (exception_x == `TRUE)
  7.2449 +            begin
  7.2450 +                w_result_sel_load_m <= `FALSE;
  7.2451 +`ifdef CFG_PL_MULTIPLY_ENABLED
  7.2452 +                w_result_sel_mul_m <= `FALSE;
  7.2453 +`endif
  7.2454 +            end
  7.2455 +            else
  7.2456 +            begin
  7.2457 +                w_result_sel_load_m <= w_result_sel_load_x;
  7.2458 +`ifdef CFG_PL_MULTIPLY_ENABLED
  7.2459 +                w_result_sel_mul_m <= w_result_sel_mul_x;
  7.2460 +`endif
  7.2461 +            end
  7.2462 +            m_bypass_enable_m <= m_bypass_enable_x;
  7.2463 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  7.2464 +            direction_m <= direction_x;
  7.2465 +`endif
  7.2466 +            load_m <= load_x;
  7.2467 +            store_m <= store_x;
  7.2468 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
  7.2469 +            branch_m <= branch_x && !branch_taken_x;
  7.2470 +`else
  7.2471 +            branch_m <= branch_x;
  7.2472 +	    branch_predict_m <= branch_predict_x;
  7.2473 +	    branch_predict_taken_m <= branch_predict_taken_x;
  7.2474 +`endif
  7.2475 +`ifdef CFG_DEBUG_ENABLED
  7.2476 +	   // Data bus errors are generated by the wishbone and are
  7.2477 +	   // made known to the processor only in next cycle (as a
  7.2478 +	   // non-debug exception). A break instruction can be seen
  7.2479 +	   // in same cycle (causing a debug exception). Handle non
  7.2480 +	   // -debug exception first!
  7.2481 +            if (non_debug_exception_x == `TRUE) 
  7.2482 +                write_idx_m <= `LM32_EA_REG;
  7.2483 +            else if (debug_exception_x == `TRUE)
  7.2484 +                write_idx_m <= `LM32_BA_REG;
  7.2485 +            else 
  7.2486 +                write_idx_m <= write_idx_x;
  7.2487 +`else
  7.2488 +            if (exception_x == `TRUE)
  7.2489 +                write_idx_m <= `LM32_EA_REG;
  7.2490 +            else 
  7.2491 +                write_idx_m <= write_idx_x;
  7.2492 +`endif
  7.2493 +            condition_met_m <= condition_met_x;
  7.2494 +`ifdef CFG_DEBUG_ENABLED
  7.2495 +	   if (exception_x == `TRUE)
  7.2496 +	     if ((dc_re == `TRUE)
  7.2497 +		 || ((debug_exception_x == `TRUE) 
  7.2498 +		     && (non_debug_exception_x == `FALSE)))
  7.2499 +	       branch_target_m <= {deba, eid_x, {3{1'b0}}};
  7.2500 +	     else
  7.2501 +	       branch_target_m <= {eba, eid_x, {3{1'b0}}};
  7.2502 +	   else
  7.2503 +	     branch_target_m <= branch_target_x;
  7.2504 +`else
  7.2505 +            branch_target_m <= exception_x == `TRUE ? {eba, eid_x, {3{1'b0}}} : branch_target_x;
  7.2506 +`endif
  7.2507 +`ifdef CFG_TRACE_ENABLED
  7.2508 +            eid_m <= eid_x;
  7.2509 +`endif
  7.2510 +`ifdef CFG_DCACHE_ENABLED
  7.2511 +            dflush_m <= dflush_x;
  7.2512 +`endif
  7.2513 +            eret_m <= eret_q_x;
  7.2514 +`ifdef CFG_DEBUG_ENABLED
  7.2515 +            bret_m <= bret_q_x; 
  7.2516 +`endif
  7.2517 +            write_enable_m <= exception_x == `TRUE ? `TRUE : write_enable_x;            
  7.2518 +`ifdef CFG_DEBUG_ENABLED
  7.2519 +            debug_exception_m <= debug_exception_x;
  7.2520 +            non_debug_exception_m <= non_debug_exception_x;        
  7.2521 +`endif
  7.2522 +        end
  7.2523 +        
  7.2524 +        // State changing regs
  7.2525 +        if (stall_m == `FALSE)
  7.2526 +        begin
  7.2527 +            if ((exception_x == `TRUE) && (q_x == `TRUE) && (stall_x == `FALSE))
  7.2528 +                exception_m <= `TRUE;
  7.2529 +            else 
  7.2530 +                exception_m <= `FALSE;
  7.2531 +`ifdef CFG_BUS_ERRORS_ENABLED
  7.2532 +	   data_bus_error_exception_m <=    (data_bus_error_exception == `TRUE) 
  7.2533 +`ifdef CFG_DEBUG_ENABLED
  7.2534 +					 && (reset_exception == `FALSE)
  7.2535 +`endif
  7.2536 +					 ;
  7.2537 +`endif
  7.2538 +	end
  7.2539 +                
  7.2540 +        // M/W stage registers
  7.2541 +`ifdef CFG_BUS_ERRORS_ENABLED
  7.2542 +        operand_w <= exception_m == `TRUE ? (data_bus_error_exception_m ? {memop_pc_w, 2'b00} : {pc_m, 2'b00}) : m_result;
  7.2543 +`else
  7.2544 +        operand_w <= exception_m == `TRUE ? {pc_m, 2'b00} : m_result;
  7.2545 +`endif
  7.2546 +        w_result_sel_load_w <= w_result_sel_load_m;
  7.2547 +`ifdef CFG_PL_MULTIPLY_ENABLED
  7.2548 +        w_result_sel_mul_w <= w_result_sel_mul_m;
  7.2549 +`endif
  7.2550 +        write_idx_w <= write_idx_m;
  7.2551 +`ifdef CFG_TRACE_ENABLED
  7.2552 +        eid_w <= eid_m;
  7.2553 +        eret_w <= eret_m;
  7.2554 +`ifdef CFG_DEBUG_ENABLED
  7.2555 +        bret_w <= bret_m; 
  7.2556 +`endif
  7.2557 +`endif
  7.2558 +        write_enable_w <= write_enable_m;
  7.2559 +`ifdef CFG_DEBUG_ENABLED
  7.2560 +        debug_exception_w <= debug_exception_m;
  7.2561 +        non_debug_exception_w <= non_debug_exception_m;
  7.2562 +`else
  7.2563 +        exception_w <= exception_m;
  7.2564 +`endif
  7.2565 +`ifdef CFG_BUS_ERRORS_ENABLED
  7.2566 +        if (   (stall_m == `FALSE)
  7.2567 +            && (   (load_q_m == `TRUE) 
  7.2568 +                || (store_q_m == `TRUE)
  7.2569 +               )
  7.2570 +	   )
  7.2571 +          memop_pc_w <= pc_m;
  7.2572 +`endif
  7.2573 +    end
  7.2574 +end
  7.2575 +
  7.2576 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
  7.2577 +// Buffer data read from register file, in case a stall occurs, and watch for
  7.2578 +// any writes to the modified registers
  7.2579 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  7.2580 +begin
  7.2581 +    if (rst_i == `TRUE)
  7.2582 +    begin
  7.2583 +        use_buf <= `FALSE;
  7.2584 +        reg_data_buf_0 <= {`LM32_WORD_WIDTH{1'b0}};
  7.2585 +        reg_data_buf_1 <= {`LM32_WORD_WIDTH{1'b0}};
  7.2586 +    end
  7.2587 +    else
  7.2588 +    begin
  7.2589 +        if (stall_d == `FALSE)
  7.2590 +            use_buf <= `FALSE;
  7.2591 +        else if (use_buf == `FALSE)
  7.2592 +        begin        
  7.2593 +            reg_data_buf_0 <= reg_data_live_0;
  7.2594 +            reg_data_buf_1 <= reg_data_live_1;
  7.2595 +            use_buf <= `TRUE;
  7.2596 +        end        
  7.2597 +        if (reg_write_enable_q_w == `TRUE)
  7.2598 +        begin
  7.2599 +            if (write_idx_w == read_idx_0_d)
  7.2600 +                reg_data_buf_0 <= w_result;
  7.2601 +            if (write_idx_w == read_idx_1_d)
  7.2602 +                reg_data_buf_1 <= w_result;
  7.2603 +        end
  7.2604 +    end
  7.2605 +end
  7.2606 +`endif
  7.2607 +
  7.2608 +`ifdef LM32_EBR_REGISTER_FILE
  7.2609 +`else
  7.2610 +// Register file write port
  7.2611 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  7.2612 +begin
  7.2613 +    if (rst_i == `TRUE) begin
  7.2614 +        registers[0] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2615 +        registers[1] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2616 +        registers[2] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2617 +        registers[3] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2618 +        registers[4] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2619 +        registers[5] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2620 +        registers[6] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2621 +        registers[7] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2622 +        registers[8] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2623 +        registers[9] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2624 +        registers[10] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2625 +        registers[11] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2626 +        registers[12] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2627 +        registers[13] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2628 +        registers[14] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2629 +        registers[15] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2630 +        registers[16] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2631 +        registers[17] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2632 +        registers[18] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2633 +        registers[19] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2634 +        registers[20] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2635 +        registers[21] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2636 +        registers[22] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2637 +        registers[23] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2638 +        registers[24] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2639 +        registers[25] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2640 +        registers[26] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2641 +        registers[27] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2642 +        registers[28] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2643 +        registers[29] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2644 +        registers[30] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2645 +        registers[31] <= {`LM32_WORD_WIDTH{1'b0}}; 
  7.2646 +        end
  7.2647 +    else begin
  7.2648 +        if (reg_write_enable_q_w == `TRUE)
  7.2649 +          registers[write_idx_w] <= w_result;
  7.2650 +        end
  7.2651 +end
  7.2652 +`endif
  7.2653 +
  7.2654 +`ifdef CFG_TRACE_ENABLED
  7.2655 +// PC tracing logic
  7.2656 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  7.2657 +begin
  7.2658 +    if (rst_i == `TRUE)
  7.2659 +    begin
  7.2660 +        trace_pc_valid <= `FALSE;
  7.2661 +        trace_pc <= {`LM32_PC_WIDTH{1'b0}};
  7.2662 +        trace_exception <= `FALSE;
  7.2663 +        trace_eid <= `LM32_EID_RESET;
  7.2664 +        trace_eret <= `FALSE;
  7.2665 +`ifdef CFG_DEBUG_ENABLED
  7.2666 +        trace_bret <= `FALSE;
  7.2667 +`endif
  7.2668 +        pc_c <= `CFG_EBA_RESET/4;
  7.2669 +    end
  7.2670 +    else
  7.2671 +    begin
  7.2672 +        trace_pc_valid <= `FALSE;
  7.2673 +        // Has an exception occured
  7.2674 +`ifdef CFG_DEBUG_ENABLED
  7.2675 +        if ((debug_exception_q_w == `TRUE) || (non_debug_exception_q_w == `TRUE))
  7.2676 +`else
  7.2677 +        if (exception_q_w == `TRUE)
  7.2678 +`endif
  7.2679 +        begin        
  7.2680 +            trace_exception <= `TRUE;
  7.2681 +            trace_pc_valid <= `TRUE;
  7.2682 +            trace_pc <= pc_w;
  7.2683 +            trace_eid <= eid_w;
  7.2684 +        end
  7.2685 +        else
  7.2686 +            trace_exception <= `FALSE;
  7.2687 +        
  7.2688 +        if ((valid_w == `TRUE) && (!kill_w))
  7.2689 +        begin
  7.2690 +            // An instruction is commiting. Determine if it is non-sequential
  7.2691 +            if (pc_c + 1'b1 != pc_w)
  7.2692 +            begin
  7.2693 +                // Non-sequential instruction
  7.2694 +                trace_pc_valid <= `TRUE;
  7.2695 +                trace_pc <= pc_w;
  7.2696 +            end
  7.2697 +            // Record PC so we can determine if next instruction is sequential or not
  7.2698 +            pc_c <= pc_w;
  7.2699 +            // Indicate if it was an eret/bret instruction
  7.2700 +            trace_eret <= eret_w;
  7.2701 +`ifdef CFG_DEBUG_ENABLED
  7.2702 +            trace_bret <= bret_w;
  7.2703 +`endif
  7.2704 +        end
  7.2705 +        else
  7.2706 +        begin
  7.2707 +            trace_eret <= `FALSE;
  7.2708 +`ifdef CFG_DEBUG_ENABLED
  7.2709 +            trace_bret <= `FALSE;
  7.2710 +`endif
  7.2711 +        end
  7.2712 +    end
  7.2713 +end
  7.2714 +`endif
  7.2715 +      
  7.2716 +/////////////////////////////////////////////////////
  7.2717 +// Behavioural Logic
  7.2718 +/////////////////////////////////////////////////////
  7.2719 +
  7.2720 +// synthesis translate_off            
  7.2721 +
  7.2722 +// Reset register 0. Only needed for simulation. 
  7.2723 +initial
  7.2724 +begin
  7.2725 +`ifdef LM32_EBR_REGISTER_FILE
  7.2726 +    reg_0.mem[0] = {`LM32_WORD_WIDTH{1'b0}};
  7.2727 +    reg_1.mem[0] = {`LM32_WORD_WIDTH{1'b0}};
  7.2728 +`else
  7.2729 +    registers[0] = {`LM32_WORD_WIDTH{1'b0}};
  7.2730 +`endif
  7.2731 +end
  7.2732 +
  7.2733 +// synthesis translate_on
  7.2734 +        
  7.2735 +endmodule 

     8.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     8.2 +++ b/lm32_dcache.v	Sun Apr 04 20:40:03 2010 +0100
     8.3 @@ -0,0 +1,533 @@
     8.4 +// =============================================================================
     8.5 +//                           COPYRIGHT NOTICE
     8.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation
     8.7 +// ALL RIGHTS RESERVED
     8.8 +// This confidential and proprietary software may be used only as authorised by
     8.9 +// a licensing agreement from Lattice Semiconductor Corporation.
    8.10 +// The entire notice above must be reproduced on all authorized copies and
    8.11 +// copies may only be made to the extent permitted by a licensing agreement from
    8.12 +// Lattice Semiconductor Corporation.
    8.13 +//
    8.14 +// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
    8.15 +// 5555 NE Moore Court                            408-826-6000 (other locations)
    8.16 +// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
    8.17 +// U.S.A                                   email: techsupport@latticesemi.com
    8.18 +// =============================================================================/
    8.19 +//                         FILE DETAILS
    8.20 +// Project          : LatticeMico32
    8.21 +// File             : lm32_dcache.v
    8.22 +// Title            : Data cache
    8.23 +// Dependencies     : lm32_include.v
    8.24 +// Version          : 6.1.17
    8.25 +//                  : Initial Release
    8.26 +// Version          : 7.0SP2, 3.0
    8.27 +//                  : No Change
    8.28 +// Version	    : 3.1
    8.29 +//                  : Support for user-selected resource usage when implementing
    8.30 +//                  : cache memory. Additional parameters must be defined when
    8.31 +//                  : invoking lm32_ram.v
    8.32 +// =============================================================================
    8.33 +								 
    8.34 +`include "lm32_include.v"
    8.35 +
    8.36 +`ifdef CFG_DCACHE_ENABLED
    8.37 +
    8.38 +`define LM32_DC_ADDR_OFFSET_RNG          addr_offset_msb:addr_offset_lsb
    8.39 +`define LM32_DC_ADDR_SET_RNG             addr_set_msb:addr_set_lsb
    8.40 +`define LM32_DC_ADDR_TAG_RNG             addr_tag_msb:addr_tag_lsb
    8.41 +`define LM32_DC_ADDR_IDX_RNG             addr_set_msb:addr_offset_lsb
    8.42 +
    8.43 +`define LM32_DC_TMEM_ADDR_WIDTH          addr_set_width
    8.44 +`define LM32_DC_TMEM_ADDR_RNG            (`LM32_DC_TMEM_ADDR_WIDTH-1):0
    8.45 +`define LM32_DC_DMEM_ADDR_WIDTH          (addr_offset_width+addr_set_width)
    8.46 +`define LM32_DC_DMEM_ADDR_RNG            (`LM32_DC_DMEM_ADDR_WIDTH-1):0
    8.47 +
    8.48 +`define LM32_DC_TAGS_WIDTH               (addr_tag_width+1)
    8.49 +`define LM32_DC_TAGS_RNG                 (`LM32_DC_TAGS_WIDTH-1):0
    8.50 +`define LM32_DC_TAGS_TAG_RNG             (`LM32_DC_TAGS_WIDTH-1):1
    8.51 +`define LM32_DC_TAGS_VALID_RNG           0
    8.52 +
    8.53 +`define LM32_DC_STATE_RNG                2:0
    8.54 +`define LM32_DC_STATE_FLUSH              3'b001
    8.55 +`define LM32_DC_STATE_CHECK              3'b010
    8.56 +`define LM32_DC_STATE_REFILL             3'b100
    8.57 +
    8.58 +/////////////////////////////////////////////////////
    8.59 +// Module interface
    8.60 +/////////////////////////////////////////////////////
    8.61 +
    8.62 +module lm32_dcache ( 
    8.63 +    // ----- Inputs -----
    8.64 +    clk_i,
    8.65 +    rst_i,    
    8.66 +    stall_a,
    8.67 +    stall_x,
    8.68 +    stall_m,
    8.69 +    address_x,
    8.70 +    address_m,
    8.71 +    load_q_m,
    8.72 +    store_q_m,
    8.73 +    store_data,
    8.74 +    store_byte_select,
    8.75 +    refill_ready,
    8.76 +    refill_data,
    8.77 +    dflush,
    8.78 +    // ----- Outputs -----
    8.79 +    stall_request,
    8.80 +    restart_request,
    8.81 +    refill_request,
    8.82 +    refill_address,
    8.83 +    refilling,
    8.84 +    load_data
    8.85 +    );
    8.86 +
    8.87 +/////////////////////////////////////////////////////
    8.88 +// Parameters
    8.89 +/////////////////////////////////////////////////////
    8.90 +
    8.91 +parameter associativity = 1;                            // Associativity of the cache (Number of ways)
    8.92 +parameter sets = 512;                                   // Number of sets
    8.93 +parameter bytes_per_line = 16;                          // Number of bytes per cache line
    8.94 +parameter base_address = 0;                             // Base address of cachable memory
    8.95 +parameter limit = 0;                                    // Limit (highest address) of cachable memory
    8.96 +
    8.97 +localparam addr_offset_width = clogb2(bytes_per_line)-1-2;
    8.98 +localparam addr_set_width = clogb2(sets)-1;
    8.99 +localparam addr_offset_lsb = 2;
   8.100 +localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
   8.101 +localparam addr_set_lsb = (addr_offset_msb+1);
   8.102 +localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
   8.103 +localparam addr_tag_lsb = (addr_set_msb+1);
   8.104 +localparam addr_tag_msb = clogb2(`CFG_DCACHE_LIMIT-`CFG_DCACHE_BASE_ADDRESS)-1;
   8.105 +localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);
   8.106 +
   8.107 +/////////////////////////////////////////////////////
   8.108 +// Inputs
   8.109 +/////////////////////////////////////////////////////
   8.110 +
   8.111 +input clk_i;                                            // Clock
   8.112 +input rst_i;                                            // Reset
   8.113 +
   8.114 +input stall_a;                                          // Stall A stage
   8.115 +input stall_x;                                          // Stall X stage
   8.116 +input stall_m;                                          // Stall M stage
   8.117 +
   8.118 +input [`LM32_WORD_RNG] address_x;                       // X stage load/store address
   8.119 +input [`LM32_WORD_RNG] address_m;                       // M stage load/store address
   8.120 +input load_q_m;                                         // Load instruction in M stage
   8.121 +input store_q_m;                                        // Store instruction in M stage
   8.122 +input [`LM32_WORD_RNG] store_data;                      // Data to store
   8.123 +input [`LM32_BYTE_SELECT_RNG] store_byte_select;        // Which bytes in store data should be modified
   8.124 +
   8.125 +input refill_ready;                                     // Indicates next word of refill data is ready
   8.126 +input [`LM32_WORD_RNG] refill_data;                     // Refill data
   8.127 +
   8.128 +input dflush;                                           // Indicates cache should be flushed
   8.129 +
   8.130 +/////////////////////////////////////////////////////
   8.131 +// Outputs
   8.132 +/////////////////////////////////////////////////////
   8.133 +
   8.134 +output stall_request;                                   // Request pipeline be stalled because cache is busy
   8.135 +wire   stall_request;
   8.136 +output restart_request;                                 // Request to restart instruction that caused the cache miss
   8.137 +reg    restart_request;
   8.138 +output refill_request;                                  // Request a refill 
   8.139 +reg    refill_request;
   8.140 +output [`LM32_WORD_RNG] refill_address;                 // Address to refill from
   8.141 +reg    [`LM32_WORD_RNG] refill_address;
   8.142 +output refilling;                                       // Indicates if the cache is currently refilling
   8.143 +reg    refilling;
   8.144 +output [`LM32_WORD_RNG] load_data;                      // Data read from cache
   8.145 +wire   [`LM32_WORD_RNG] load_data;
   8.146 +
   8.147 +/////////////////////////////////////////////////////
   8.148 +// Internal nets and registers 
   8.149 +/////////////////////////////////////////////////////
   8.150 +
   8.151 +wire read_port_enable;                                  // Cache memory read port clock enable
   8.152 +wire write_port_enable;                                 // Cache memory write port clock enable
   8.153 +wire [0:associativity-1] way_tmem_we;                   // Tag memory write enable
   8.154 +wire [0:associativity-1] way_dmem_we;                   // Data memory write enable
   8.155 +wire [`LM32_WORD_RNG] way_data[0:associativity-1];      // Data read from data memory
   8.156 +wire [`LM32_DC_TAGS_TAG_RNG] way_tag[0:associativity-1];// Tag read from tag memory
   8.157 +wire [0:associativity-1] way_valid;                     // Indicates which ways are valid
   8.158 +wire [0:associativity-1] way_match;                     // Indicates which ways matched
   8.159 +wire miss;                                              // Indicates no ways matched
   8.160 +
   8.161 +wire [`LM32_DC_TMEM_ADDR_RNG] tmem_read_address;        // Tag memory read address
   8.162 +wire [`LM32_DC_TMEM_ADDR_RNG] tmem_write_address;       // Tag memory write address
   8.163 +wire [`LM32_DC_DMEM_ADDR_RNG] dmem_read_address;        // Data memory read address
   8.164 +wire [`LM32_DC_DMEM_ADDR_RNG] dmem_write_address;       // Data memory write address
   8.165 +wire [`LM32_DC_TAGS_RNG] tmem_write_data;               // Tag memory write data        
   8.166 +reg [`LM32_WORD_RNG] dmem_write_data;                   // Data memory write data
   8.167 +
   8.168 +reg [`LM32_DC_STATE_RNG] state;                         // Current state of FSM
   8.169 +wire flushing;                                          // Indicates if cache is currently flushing
   8.170 +wire check;                                             // Indicates if cache is currently checking for hits/misses
   8.171 +wire refill;                                            // Indicates if cache is currently refilling
   8.172 +
   8.173 +wire valid_store;                                       // Indicates if there is a valid store instruction
   8.174 +reg [associativity-1:0] refill_way_select;              // Which way should be refilled
   8.175 +reg [`LM32_DC_ADDR_OFFSET_RNG] refill_offset;           // Which word in cache line should be refilled
   8.176 +wire last_refill;                                       // Indicates when on last cycle of cache refill
   8.177 +reg [`LM32_DC_TMEM_ADDR_RNG] flush_set;                 // Which set is currently being flushed
   8.178 +
   8.179 +genvar i, j;
   8.180 +
   8.181 +/////////////////////////////////////////////////////
   8.182 +// Functions
   8.183 +/////////////////////////////////////////////////////
   8.184 +
   8.185 +`include "lm32_functions.v"
   8.186 +
   8.187 +/////////////////////////////////////////////////////
   8.188 +// Instantiations
   8.189 +/////////////////////////////////////////////////////
   8.190 +
   8.191 +   generate
   8.192 +      for (i = 0; i < associativity; i = i + 1)    
   8.193 +	begin : memories
   8.194 +	   // Way data
   8.195 +           if (`LM32_DC_DMEM_ADDR_WIDTH < 11)
   8.196 +             begin : data_memories
   8.197 +		lm32_ram 
   8.198 +		  #(
   8.199 +		    // ----- Parameters -------
   8.200 +		    .data_width (32),
   8.201 +		    .address_width (`LM32_DC_DMEM_ADDR_WIDTH),
   8.202 +`ifdef CFG_DCACHE_DAT_USE_DP_TRUE
   8.203 +		    .RAM_IMPLEMENTATION ("EBR"),
   8.204 +		    .RAM_TYPE ("RAM_DP_TRUE")
   8.205 +`else
   8.206 + `ifdef CFG_DCACHE_DAT_USE_SLICE
   8.207 +		    .RAM_IMPLEMENTATION ("SLICE")
   8.208 + `else
   8.209 +		    .RAM_IMPLEMENTATION ("AUTO")
   8.210 + `endif
   8.211 +`endif
   8.212 +		    ) way_0_data_ram 
   8.213 +		    (
   8.214 +		     // ----- Inputs -------
   8.215 +		     .read_clk (clk_i),
   8.216 +		     .write_clk (clk_i),
   8.217 +		     .reset (rst_i),
   8.218 +		     .read_address (dmem_read_address),
   8.219 +		     .enable_read (read_port_enable),
   8.220 +		     .write_address (dmem_write_address),
   8.221 +		     .enable_write (write_port_enable),
   8.222 +		     .write_enable (way_dmem_we[i]),
   8.223 +		     .write_data (dmem_write_data),    
   8.224 +		     // ----- Outputs -------
   8.225 +		     .read_data (way_data[i])
   8.226 +		     );    
   8.227 +             end
   8.228 +           else
   8.229 +             begin
   8.230 +		for (j = 0; j < 4; j = j + 1)    
   8.231 +		  begin : byte_memories
   8.232 +		     lm32_ram 
   8.233 +		       #(
   8.234 +			 // ----- Parameters -------
   8.235 +			 .data_width (8),
   8.236 +			 .address_width (`LM32_DC_DMEM_ADDR_WIDTH),
   8.237 +`ifdef CFG_DCACHE_DAT_USE_DP_TRUE
   8.238 +			 .RAM_IMPLEMENTATION ("EBR"),
   8.239 +			 .RAM_TYPE ("RAM_DP_TRUE")
   8.240 +`else
   8.241 + `ifdef CFG_DCACHE_DAT_USE_SLICE
   8.242 +			 .RAM_IMPLEMENTATION ("SLICE")
   8.243 + `else
   8.244 +			 .RAM_IMPLEMENTATION ("AUTO")
   8.245 + `endif
   8.246 +`endif
   8.247 +			 ) way_0_data_ram 
   8.248 +			 (
   8.249 +			  // ----- Inputs -------
   8.250 +			  .read_clk (clk_i),
   8.251 +			  .write_clk (clk_i),
   8.252 +			  .reset (rst_i),
   8.253 +			  .read_address (dmem_read_address),
   8.254 +			  .enable_read (read_port_enable),
   8.255 +			  .write_address (dmem_write_address),
   8.256 +			  .enable_write (write_port_enable),
   8.257 +			  .write_enable (way_dmem_we[i] & (store_byte_select[j] | refill)),
   8.258 +			  .write_data (dmem_write_data[(j+1)*8-1:j*8]),    
   8.259 +			  // ----- Outputs -------
   8.260 +			  .read_data (way_data[i][(j+1)*8-1:j*8])
   8.261 +			  );
   8.262 +		  end
   8.263 +             end
   8.264 +	   
   8.265 +	   // Way tags
   8.266 +	   lm32_ram 
   8.267 +	     #(
   8.268 +	       // ----- Parameters -------
   8.269 +	       .data_width (`LM32_DC_TAGS_WIDTH),
   8.270 +	       .address_width (`LM32_DC_TMEM_ADDR_WIDTH),
   8.271 +`ifdef CFG_DCACHE_DAT_USE_DP_TRUE
   8.272 +	       .RAM_IMPLEMENTATION ("EBR"),
   8.273 +	       .RAM_TYPE ("RAM_DP_TRUE")
   8.274 +`else
   8.275 + `ifdef CFG_DCACHE_DAT_USE_SLICE
   8.276 +	       .RAM_IMPLEMENTATION ("SLICE")
   8.277 + `else
   8.278 +	       .RAM_IMPLEMENTATION ("AUTO")
   8.279 + `endif
   8.280 +`endif
   8.281 +	       ) way_0_tag_ram 
   8.282 +	       (
   8.283 +		// ----- Inputs -------
   8.284 +		.read_clk (clk_i),
   8.285 +		.write_clk (clk_i),
   8.286 +		.reset (rst_i),
   8.287 +		.read_address (tmem_read_address),
   8.288 +		.enable_read (read_port_enable),
   8.289 +		.write_address (tmem_write_address),
   8.290 +		.enable_write (`TRUE),
   8.291 +		.write_enable (way_tmem_we[i]),
   8.292 +		.write_data (tmem_write_data),
   8.293 +		// ----- Outputs -------
   8.294 +		.read_data ({way_tag[i], way_valid[i]})
   8.295 +		);
   8.296 +	end
   8.297 +      
   8.298 +   endgenerate
   8.299 +
   8.300 +/////////////////////////////////////////////////////
   8.301 +// Combinational logic
   8.302 +/////////////////////////////////////////////////////
   8.303 +
   8.304 +// Compute which ways in the cache match the address being read
   8.305 +generate
   8.306 +    for (i = 0; i < associativity; i = i + 1)
   8.307 +    begin : match
   8.308 +assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_m[`LM32_DC_ADDR_TAG_RNG], `TRUE});
   8.309 +    end
   8.310 +endgenerate
   8.311 +
   8.312 +// Select data from way that matched the address being read     
   8.313 +generate
   8.314 +    if (associativity == 1)    
   8.315 +	 begin : data_1
   8.316 +assign load_data = way_data[0];
   8.317 +    end
   8.318 +    else if (associativity == 2)
   8.319 +	 begin : data_2
   8.320 +assign load_data = way_match[0] ? way_data[0] : way_data[1]; 
   8.321 +    end
   8.322 +endgenerate
   8.323 +
   8.324 +generate
   8.325 +    if (`LM32_DC_DMEM_ADDR_WIDTH < 11)
   8.326 +    begin
   8.327 +// Select data to write to data memories
   8.328 +always @(*)
   8.329 +begin
   8.330 +    if (refill == `TRUE)
   8.331 +        dmem_write_data = refill_data;
   8.332 +    else
   8.333 +    begin
   8.334 +        dmem_write_data[`LM32_BYTE_0_RNG] = store_byte_select[0] ? store_data[`LM32_BYTE_0_RNG] : load_data[`LM32_BYTE_0_RNG];
   8.335 +        dmem_write_data[`LM32_BYTE_1_RNG] = store_byte_select[1] ? store_data[`LM32_BYTE_1_RNG] : load_data[`LM32_BYTE_1_RNG];
   8.336 +        dmem_write_data[`LM32_BYTE_2_RNG] = store_byte_select[2] ? store_data[`LM32_BYTE_2_RNG] : load_data[`LM32_BYTE_2_RNG];
   8.337 +        dmem_write_data[`LM32_BYTE_3_RNG] = store_byte_select[3] ? store_data[`LM32_BYTE_3_RNG] : load_data[`LM32_BYTE_3_RNG];
   8.338 +    end
   8.339 +end
   8.340 +    end
   8.341 +    else
   8.342 +    begin
   8.343 +// Select data to write to data memories - FIXME: Should use different write ports on dual port RAMs, but they don't work
   8.344 +always @(*)
   8.345 +begin
   8.346 +    if (refill == `TRUE)
   8.347 +        dmem_write_data = refill_data;
   8.348 +    else
   8.349 +        dmem_write_data = store_data;
   8.350 +end
   8.351 +    end
   8.352 +endgenerate
   8.353 +
   8.354 +// Compute address to use to index into the data memories
   8.355 +generate 
   8.356 +     if (bytes_per_line > 4)
   8.357 +assign dmem_write_address = (refill == `TRUE) 
   8.358 +                            ? {refill_address[`LM32_DC_ADDR_SET_RNG], refill_offset}
   8.359 +                            : address_m[`LM32_DC_ADDR_IDX_RNG];
   8.360 +    else
   8.361 +assign dmem_write_address = (refill == `TRUE) 
   8.362 +                            ? refill_address[`LM32_DC_ADDR_SET_RNG]
   8.363 +                            : address_m[`LM32_DC_ADDR_IDX_RNG];
   8.364 +endgenerate
   8.365 +assign dmem_read_address = address_x[`LM32_DC_ADDR_IDX_RNG];
   8.366 +// Compute address to use to index into the tag memories   
   8.367 +assign tmem_write_address = (flushing == `TRUE)
   8.368 +                            ? flush_set
   8.369 +                            : refill_address[`LM32_DC_ADDR_SET_RNG];
   8.370 +assign tmem_read_address = address_x[`LM32_DC_ADDR_SET_RNG];
   8.371 +
   8.372 +// Compute signal to indicate when we are on the last refill accesses
   8.373 +generate 
   8.374 +    if (bytes_per_line > 4)                            
   8.375 +assign last_refill = refill_offset == {addr_offset_width{1'b1}};
   8.376 +    else
   8.377 +assign last_refill = `TRUE;
   8.378 +endgenerate
   8.379 +
   8.380 +// Compute data and tag memory access enable
   8.381 +assign read_port_enable = (stall_x == `FALSE);
   8.382 +assign write_port_enable = (refill_ready == `TRUE) || !stall_m;
   8.383 +
   8.384 +// Determine when we have a valid store
   8.385 +assign valid_store = (store_q_m == `TRUE) && (check == `TRUE);
   8.386 +
   8.387 +// Compute data and tag memory write enables
   8.388 +generate
   8.389 +    if (associativity == 1) 
   8.390 +    begin : we_1     
   8.391 +assign way_dmem_we[0] = (refill_ready == `TRUE) || ((valid_store == `TRUE) && (way_match[0] == `TRUE));
   8.392 +assign way_tmem_we[0] = (refill_ready == `TRUE) || (flushing == `TRUE);
   8.393 +    end 
   8.394 +    else 
   8.395 +    begin : we_2
   8.396 +assign way_dmem_we[0] = ((refill_ready == `TRUE) && (refill_way_select[0] == `TRUE)) || ((valid_store == `TRUE) && (way_match[0] == `TRUE));
   8.397 +assign way_dmem_we[1] = ((refill_ready == `TRUE) && (refill_way_select[1] == `TRUE)) || ((valid_store == `TRUE) && (way_match[1] == `TRUE));
   8.398 +assign way_tmem_we[0] = ((refill_ready == `TRUE) && (refill_way_select[0] == `TRUE)) || (flushing == `TRUE);
   8.399 +assign way_tmem_we[1] = ((refill_ready == `TRUE) && (refill_way_select[1] == `TRUE)) || (flushing == `TRUE);
   8.400 +    end
   8.401 +endgenerate
   8.402 +
   8.403 +// On the last refill cycle set the valid bit, for all other writes it should be cleared
   8.404 +assign tmem_write_data[`LM32_DC_TAGS_VALID_RNG] = ((last_refill == `TRUE) || (valid_store == `TRUE)) && (flushing == `FALSE);
   8.405 +assign tmem_write_data[`LM32_DC_TAGS_TAG_RNG] = refill_address[`LM32_DC_ADDR_TAG_RNG];
   8.406 +
   8.407 +// Signals that indicate which state we are in
   8.408 +assign flushing = state[0];
   8.409 +assign check = state[1];
   8.410 +assign refill = state[2];
   8.411 +
   8.412 +assign miss = (~(|way_match)) && (load_q_m == `TRUE) && (stall_m == `FALSE);
   8.413 +assign stall_request = (check == `FALSE);
   8.414 +                      
   8.415 +/////////////////////////////////////////////////////
   8.416 +// Sequential logic
   8.417 +/////////////////////////////////////////////////////
   8.418 +
   8.419 +// Record way selected for replacement on a cache miss
   8.420 +generate
   8.421 +    if (associativity >= 2) 
   8.422 +    begin : way_select      
   8.423 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
   8.424 +begin
   8.425 +    if (rst_i == `TRUE)
   8.426 +        refill_way_select <= {{associativity-1{1'b0}}, 1'b1};
   8.427 +    else
   8.428 +    begin        
   8.429 +        if (refill_request == `TRUE)
   8.430 +            refill_way_select <= {refill_way_select[0], refill_way_select[1]};
   8.431 +    end
   8.432 +end
   8.433 +    end 
   8.434 +endgenerate   
   8.435 +
   8.436 +// Record whether we are currently refilling
   8.437 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
   8.438 +begin
   8.439 +    if (rst_i == `TRUE)
   8.440 +        refilling <= `FALSE;
   8.441 +    else 
   8.442 +        refilling <= refill;
   8.443 +end
   8.444 +
   8.445 +// Instruction cache control FSM
   8.446 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
   8.447 +begin
   8.448 +    if (rst_i == `TRUE)
   8.449 +    begin
   8.450 +        state <= `LM32_DC_STATE_FLUSH;
   8.451 +        flush_set <= {`LM32_DC_TMEM_ADDR_WIDTH{1'b1}};
   8.452 +        refill_request <= `FALSE;
   8.453 +        refill_address <= {`LM32_WORD_WIDTH{1'bx}};
   8.454 +        restart_request <= `FALSE;
   8.455 +    end
   8.456 +    else 
   8.457 +    begin
   8.458 +        case (state)
   8.459 +
   8.460 +        // Flush the cache 
   8.461 +        `LM32_DC_STATE_FLUSH:
   8.462 +        begin
   8.463 +            if (flush_set == {`LM32_DC_TMEM_ADDR_WIDTH{1'b0}})
   8.464 +                state <= `LM32_DC_STATE_CHECK;
   8.465 +            flush_set <= flush_set - 1'b1;
   8.466 +        end
   8.467 +        
   8.468 +        // Check for cache misses
   8.469 +        `LM32_DC_STATE_CHECK:
   8.470 +        begin
   8.471 +            if (stall_a == `FALSE)
   8.472 +                restart_request <= `FALSE;
   8.473 +            if (miss == `TRUE)
   8.474 +            begin
   8.475 +                refill_request <= `TRUE;
   8.476 +                refill_address <= address_m;
   8.477 +                state <= `LM32_DC_STATE_REFILL;
   8.478 +            end
   8.479 +            else if (dflush == `TRUE)
   8.480 +                state <= `LM32_DC_STATE_FLUSH;
   8.481 +        end
   8.482 +
   8.483 +        // Refill a cache line
   8.484 +        `LM32_DC_STATE_REFILL:
   8.485 +        begin
   8.486 +            refill_request <= `FALSE;
   8.487 +            if (refill_ready == `TRUE)
   8.488 +            begin
   8.489 +                if (last_refill == `TRUE)
   8.490 +                begin
   8.491 +                    restart_request <= `TRUE;
   8.492 +                    state <= `LM32_DC_STATE_CHECK;
   8.493 +                end
   8.494 +            end
   8.495 +        end
   8.496 +        
   8.497 +        endcase        
   8.498 +    end
   8.499 +end
   8.500 +
   8.501 +generate
   8.502 +    if (bytes_per_line > 4)
   8.503 +    begin
   8.504 +// Refill offset
   8.505 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
   8.506 +begin
   8.507 +    if (rst_i == `TRUE)
   8.508 +        refill_offset <= {addr_offset_width{1'b0}};
   8.509 +    else 
   8.510 +    begin
   8.511 +        case (state)
   8.512 +        
   8.513 +        // Check for cache misses
   8.514 +        `LM32_DC_STATE_CHECK:
   8.515 +        begin
   8.516 +            if (miss == `TRUE)
   8.517 +                refill_offset <= {addr_offset_width{1'b0}};
   8.518 +        end
   8.519 +
   8.520 +        // Refill a cache line
   8.521 +        `LM32_DC_STATE_REFILL:
   8.522 +        begin
   8.523 +            if (refill_ready == `TRUE)
   8.524 +                refill_offset <= refill_offset + 1'b1;
   8.525 +        end
   8.526 +        
   8.527 +        endcase        
   8.528 +    end
   8.529 +end
   8.530 +    end
   8.531 +endgenerate
   8.532 +
   8.533 +endmodule
   8.534 +
   8.535 +`endif
   8.536 +