1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 1.2 +++ b/lm32_icache.v Sun Apr 04 20:40:03 2010 +0100 1.3 @@ -0,0 +1,488 @@ 1.4 +// ============================================================================= 1.5 +// COPYRIGHT NOTICE 1.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation 1.7 +// ALL RIGHTS RESERVED 1.8 +// This confidential and proprietary software may be used only as authorised by 1.9 +// a licensing agreement from Lattice Semiconductor Corporation. 1.10 +// The entire notice above must be reproduced on all authorized copies and 1.11 +// copies may only be made to the extent permitted by a licensing agreement from 1.12 +// Lattice Semiconductor Corporation. 1.13 +// 1.14 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 1.15 +// 5555 NE Moore Court 408-826-6000 (other locations) 1.16 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 1.17 +// U.S.A email: techsupport@latticesemi.com 1.18 +// =============================================================================/ 1.19 +// FILE DETAILS 1.20 +// Project : LatticeMico32 1.21 +// File : lm32_icache.v 1.22 +// Title : Instruction cache 1.23 +// Dependencies : lm32_include.v 1.24 +// 1.25 +// Version 3.5 1.26 +// 1. Bug Fix: Instruction cache flushes issued from Instruction Inline Memory 1.27 +// cause segmentation fault due to incorrect fetches. 1.28 +// 1.29 +// Version 3.1 1.30 +// 1. Feature: Support for user-selected resource usage when implementing 1.31 +// cache memory. Additional parameters must be defined when invoking module 1.32 +// lm32_ram. Instruction cache miss mechanism is dependent on branch 1.33 +// prediction being performed in D stage of pipeline. 1.34 +// 1.35 +// Version 7.0SP2, 3.0 1.36 +// No change 1.37 +// ============================================================================= 1.38 + 1.39 +`include "lm32_include.v" 1.40 + 1.41 +`ifdef CFG_ICACHE_ENABLED 1.42 + 1.43 +`define LM32_IC_ADDR_OFFSET_RNG addr_offset_msb:addr_offset_lsb 1.44 +`define LM32_IC_ADDR_SET_RNG addr_set_msb:addr_set_lsb 1.45 +`define LM32_IC_ADDR_TAG_RNG addr_tag_msb:addr_tag_lsb 1.46 +`define LM32_IC_ADDR_IDX_RNG addr_set_msb:addr_offset_lsb 1.47 + 1.48 +`define LM32_IC_TMEM_ADDR_WIDTH addr_set_width 1.49 +`define LM32_IC_TMEM_ADDR_RNG (`LM32_IC_TMEM_ADDR_WIDTH-1):0 1.50 +`define LM32_IC_DMEM_ADDR_WIDTH (addr_offset_width+addr_set_width) 1.51 +`define LM32_IC_DMEM_ADDR_RNG (`LM32_IC_DMEM_ADDR_WIDTH-1):0 1.52 + 1.53 +`define LM32_IC_TAGS_WIDTH (addr_tag_width+1) 1.54 +`define LM32_IC_TAGS_RNG (`LM32_IC_TAGS_WIDTH-1):0 1.55 +`define LM32_IC_TAGS_TAG_RNG (`LM32_IC_TAGS_WIDTH-1):1 1.56 +`define LM32_IC_TAGS_VALID_RNG 0 1.57 + 1.58 +`define LM32_IC_STATE_RNG 3:0 1.59 +`define LM32_IC_STATE_FLUSH_INIT 4'b0001 1.60 +`define LM32_IC_STATE_FLUSH 4'b0010 1.61 +`define LM32_IC_STATE_CHECK 4'b0100 1.62 +`define LM32_IC_STATE_REFILL 4'b1000 1.63 + 1.64 +///////////////////////////////////////////////////// 1.65 +// Module interface 1.66 +///////////////////////////////////////////////////// 1.67 + 1.68 +module lm32_icache ( 1.69 + // ----- Inputs ----- 1.70 + clk_i, 1.71 + rst_i, 1.72 + stall_a, 1.73 + stall_f, 1.74 + address_a, 1.75 + address_f, 1.76 + read_enable_f, 1.77 + refill_ready, 1.78 + refill_data, 1.79 + iflush, 1.80 +`ifdef CFG_IROM_ENABLED 1.81 + select_f, 1.82 +`endif 1.83 + valid_d, 1.84 + branch_predict_taken_d, 1.85 + // ----- Outputs ----- 1.86 + stall_request, 1.87 + restart_request, 1.88 + refill_request, 1.89 + refill_address, 1.90 + refilling, 1.91 + inst 1.92 + ); 1.93 + 1.94 +///////////////////////////////////////////////////// 1.95 +// Parameters 1.96 +///////////////////////////////////////////////////// 1.97 + 1.98 +parameter associativity = 1; // Associativity of the cache (Number of ways) 1.99 +parameter sets = 512; // Number of sets 1.100 +parameter bytes_per_line = 16; // Number of bytes per cache line 1.101 +parameter base_address = 0; // Base address of cachable memory 1.102 +parameter limit = 0; // Limit (highest address) of cachable memory 1.103 + 1.104 +localparam addr_offset_width = clogb2(bytes_per_line)-1-2; 1.105 +localparam addr_set_width = clogb2(sets)-1; 1.106 +localparam addr_offset_lsb = 2; 1.107 +localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1); 1.108 +localparam addr_set_lsb = (addr_offset_msb+1); 1.109 +localparam addr_set_msb = (addr_set_lsb+addr_set_width-1); 1.110 +localparam addr_tag_lsb = (addr_set_msb+1); 1.111 +localparam addr_tag_msb = clogb2(`CFG_ICACHE_LIMIT-`CFG_ICACHE_BASE_ADDRESS)-1; 1.112 +localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1); 1.113 + 1.114 +///////////////////////////////////////////////////// 1.115 +// Inputs 1.116 +///////////////////////////////////////////////////// 1.117 + 1.118 +input clk_i; // Clock 1.119 +input rst_i; // Reset 1.120 + 1.121 +input stall_a; // Stall instruction in A stage 1.122 +input stall_f; // Stall instruction in F stage 1.123 + 1.124 +input valid_d; // Valid instruction in D stage 1.125 +input branch_predict_taken_d; // Instruction in D stage is a branch and is predicted taken 1.126 + 1.127 +input [`LM32_PC_RNG] address_a; // Address of instruction in A stage 1.128 +input [`LM32_PC_RNG] address_f; // Address of instruction in F stage 1.129 +input read_enable_f; // Indicates if cache access is valid 1.130 + 1.131 +input refill_ready; // Next word of refill data is ready 1.132 +input [`LM32_INSTRUCTION_RNG] refill_data; // Data to refill the cache with 1.133 + 1.134 +input iflush; // Flush the cache 1.135 +`ifdef CFG_IROM_ENABLED 1.136 +input select_f; // Instruction in F stage is mapped through instruction cache 1.137 +`endif 1.138 + 1.139 +///////////////////////////////////////////////////// 1.140 +// Outputs 1.141 +///////////////////////////////////////////////////// 1.142 + 1.143 +output stall_request; // Request to stall the pipeline 1.144 +wire stall_request; 1.145 +output restart_request; // Request to restart instruction that caused the cache miss 1.146 +reg restart_request; 1.147 +output refill_request; // Request to refill a cache line 1.148 +wire refill_request; 1.149 +output [`LM32_PC_RNG] refill_address; // Base address of cache refill 1.150 +reg [`LM32_PC_RNG] refill_address; 1.151 +output refilling; // Indicates the instruction cache is currently refilling 1.152 +reg refilling; 1.153 +output [`LM32_INSTRUCTION_RNG] inst; // Instruction read from cache 1.154 +wire [`LM32_INSTRUCTION_RNG] inst; 1.155 + 1.156 +///////////////////////////////////////////////////// 1.157 +// Internal nets and registers 1.158 +///////////////////////////////////////////////////// 1.159 + 1.160 +wire enable; 1.161 +wire [0:associativity-1] way_mem_we; 1.162 +wire [`LM32_INSTRUCTION_RNG] way_data[0:associativity-1]; 1.163 +wire [`LM32_IC_TAGS_TAG_RNG] way_tag[0:associativity-1]; 1.164 +wire [0:associativity-1] way_valid; 1.165 +wire [0:associativity-1] way_match; 1.166 +wire miss; 1.167 + 1.168 +wire [`LM32_IC_TMEM_ADDR_RNG] tmem_read_address; 1.169 +wire [`LM32_IC_TMEM_ADDR_RNG] tmem_write_address; 1.170 +wire [`LM32_IC_DMEM_ADDR_RNG] dmem_read_address; 1.171 +wire [`LM32_IC_DMEM_ADDR_RNG] dmem_write_address; 1.172 +wire [`LM32_IC_TAGS_RNG] tmem_write_data; 1.173 + 1.174 +reg [`LM32_IC_STATE_RNG] state; 1.175 +wire flushing; 1.176 +wire check; 1.177 +wire refill; 1.178 + 1.179 +reg [associativity-1:0] refill_way_select; 1.180 +reg [`LM32_IC_ADDR_OFFSET_RNG] refill_offset; 1.181 +wire last_refill; 1.182 +reg [`LM32_IC_TMEM_ADDR_RNG] flush_set; 1.183 + 1.184 +genvar i; 1.185 + 1.186 +///////////////////////////////////////////////////// 1.187 +// Functions 1.188 +///////////////////////////////////////////////////// 1.189 + 1.190 +`include "lm32_functions.v" 1.191 + 1.192 +///////////////////////////////////////////////////// 1.193 +// Instantiations 1.194 +///////////////////////////////////////////////////// 1.195 + 1.196 + generate 1.197 + for (i = 0; i < associativity; i = i + 1) 1.198 + begin : memories 1.199 + 1.200 + lm32_ram 1.201 + #( 1.202 + // ----- Parameters ------- 1.203 + .data_width (32), 1.204 + .address_width (`LM32_IC_DMEM_ADDR_WIDTH), 1.205 +`ifdef CFG_ICACHE_DAT_USE_DP_TRUE 1.206 + .RAM_IMPLEMENTATION ("EBR"), 1.207 + .RAM_TYPE ("RAM_DP_TRUE") 1.208 +`else 1.209 + `ifdef CFG_ICACHE_DAT_USE_DP 1.210 + .RAM_IMPLEMENTATION ("EBR"), 1.211 + .RAM_TYPE ("RAM_DP") 1.212 + `else 1.213 + `ifdef CFG_ICACHE_DAT_USE_SLICE 1.214 + .RAM_IMPLEMENTATION ("SLICE") 1.215 + `else 1.216 + .RAM_IMPLEMENTATION ("AUTO") 1.217 + `endif 1.218 + `endif 1.219 +`endif 1.220 + ) 1.221 + way_0_data_ram 1.222 + ( 1.223 + // ----- Inputs ------- 1.224 + .read_clk (clk_i), 1.225 + .write_clk (clk_i), 1.226 + .reset (rst_i), 1.227 + .read_address (dmem_read_address), 1.228 + .enable_read (enable), 1.229 + .write_address (dmem_write_address), 1.230 + .enable_write (`TRUE), 1.231 + .write_enable (way_mem_we[i]), 1.232 + .write_data (refill_data), 1.233 + // ----- Outputs ------- 1.234 + .read_data (way_data[i]) 1.235 + ); 1.236 + 1.237 + lm32_ram 1.238 + #( 1.239 + // ----- Parameters ------- 1.240 + .data_width (`LM32_IC_TAGS_WIDTH), 1.241 + .address_width (`LM32_IC_TMEM_ADDR_WIDTH), 1.242 +`ifdef CFG_ICACHE_DAT_USE_DP_TRUE 1.243 + .RAM_IMPLEMENTATION ("EBR"), 1.244 + .RAM_TYPE ("RAM_DP_TRUE") 1.245 +`else 1.246 + `ifdef CFG_ICACHE_DAT_USE_DP 1.247 + .RAM_IMPLEMENTATION ("EBR"), 1.248 + .RAM_TYPE ("RAM_DP") 1.249 + `else 1.250 + `ifdef CFG_ICACHE_DAT_USE_SLICE 1.251 + .RAM_IMPLEMENTATION ("SLICE") 1.252 + `else 1.253 + .RAM_IMPLEMENTATION ("AUTO") 1.254 + `endif 1.255 + `endif 1.256 +`endif 1.257 + ) 1.258 + way_0_tag_ram 1.259 + ( 1.260 + // ----- Inputs ------- 1.261 + .read_clk (clk_i), 1.262 + .write_clk (clk_i), 1.263 + .reset (rst_i), 1.264 + .read_address (tmem_read_address), 1.265 + .enable_read (enable), 1.266 + .write_address (tmem_write_address), 1.267 + .enable_write (`TRUE), 1.268 + .write_enable (way_mem_we[i] | flushing), 1.269 + .write_data (tmem_write_data), 1.270 + // ----- Outputs ------- 1.271 + .read_data ({way_tag[i], way_valid[i]}) 1.272 + ); 1.273 + 1.274 + end 1.275 +endgenerate 1.276 + 1.277 +///////////////////////////////////////////////////// 1.278 +// Combinational logic 1.279 +///////////////////////////////////////////////////// 1.280 + 1.281 +// Compute which ways in the cache match the address address being read 1.282 +generate 1.283 + for (i = 0; i < associativity; i = i + 1) 1.284 + begin : match 1.285 +assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_f[`LM32_IC_ADDR_TAG_RNG], `TRUE}); 1.286 + end 1.287 +endgenerate 1.288 + 1.289 +// Select data from way that matched the address being read 1.290 +generate 1.291 + if (associativity == 1) 1.292 + begin : inst_1 1.293 +assign inst = way_match[0] ? way_data[0] : 32'b0; 1.294 + end 1.295 + else if (associativity == 2) 1.296 + begin : inst_2 1.297 +assign inst = way_match[0] ? way_data[0] : (way_match[1] ? way_data[1] : 32'b0); 1.298 + end 1.299 +endgenerate 1.300 + 1.301 +// Compute address to use to index into the data memories 1.302 +generate 1.303 + if (bytes_per_line > 4) 1.304 +assign dmem_write_address = {refill_address[`LM32_IC_ADDR_SET_RNG], refill_offset}; 1.305 + else 1.306 +assign dmem_write_address = refill_address[`LM32_IC_ADDR_SET_RNG]; 1.307 +endgenerate 1.308 + 1.309 +assign dmem_read_address = address_a[`LM32_IC_ADDR_IDX_RNG]; 1.310 + 1.311 +// Compute address to use to index into the tag memories 1.312 +assign tmem_read_address = address_a[`LM32_IC_ADDR_SET_RNG]; 1.313 +assign tmem_write_address = flushing 1.314 + ? flush_set 1.315 + : refill_address[`LM32_IC_ADDR_SET_RNG]; 1.316 + 1.317 +// Compute signal to indicate when we are on the last refill accesses 1.318 +generate 1.319 + if (bytes_per_line > 4) 1.320 +assign last_refill = refill_offset == {addr_offset_width{1'b1}}; 1.321 + else 1.322 +assign last_refill = `TRUE; 1.323 +endgenerate 1.324 + 1.325 +// Compute data and tag memory access enable 1.326 +assign enable = (stall_a == `FALSE); 1.327 + 1.328 +// Compute data and tag memory write enables 1.329 +generate 1.330 + if (associativity == 1) 1.331 + begin : we_1 1.332 +assign way_mem_we[0] = (refill_ready == `TRUE); 1.333 + end 1.334 + else 1.335 + begin : we_2 1.336 +assign way_mem_we[0] = (refill_ready == `TRUE) && (refill_way_select[0] == `TRUE); 1.337 +assign way_mem_we[1] = (refill_ready == `TRUE) && (refill_way_select[1] == `TRUE); 1.338 + end 1.339 +endgenerate 1.340 + 1.341 +// On the last refill cycle set the valid bit, for all other writes it should be cleared 1.342 +assign tmem_write_data[`LM32_IC_TAGS_VALID_RNG] = last_refill & !flushing; 1.343 +assign tmem_write_data[`LM32_IC_TAGS_TAG_RNG] = refill_address[`LM32_IC_ADDR_TAG_RNG]; 1.344 + 1.345 +// Signals that indicate which state we are in 1.346 +assign flushing = |state[1:0]; 1.347 +assign check = state[2]; 1.348 +assign refill = state[3]; 1.349 + 1.350 +assign miss = (~(|way_match)) && (read_enable_f == `TRUE) && (stall_f == `FALSE) && !(valid_d && branch_predict_taken_d); 1.351 +assign stall_request = (check == `FALSE); 1.352 +assign refill_request = (refill == `TRUE); 1.353 + 1.354 +///////////////////////////////////////////////////// 1.355 +// Sequential logic 1.356 +///////////////////////////////////////////////////// 1.357 + 1.358 +// Record way selected for replacement on a cache miss 1.359 +generate 1.360 + if (associativity >= 2) 1.361 + begin : way_select 1.362 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.363 +begin 1.364 + if (rst_i == `TRUE) 1.365 + refill_way_select <= {{associativity-1{1'b0}}, 1'b1}; 1.366 + else 1.367 + begin 1.368 + if (miss == `TRUE) 1.369 + refill_way_select <= {refill_way_select[0], refill_way_select[1]}; 1.370 + end 1.371 +end 1.372 + end 1.373 +endgenerate 1.374 + 1.375 +// Record whether we are refilling 1.376 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.377 +begin 1.378 + if (rst_i == `TRUE) 1.379 + refilling <= `FALSE; 1.380 + else 1.381 + refilling <= refill; 1.382 +end 1.383 + 1.384 +// Instruction cache control FSM 1.385 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.386 +begin 1.387 + if (rst_i == `TRUE) 1.388 + begin 1.389 + state <= `LM32_IC_STATE_FLUSH_INIT; 1.390 + flush_set <= {`LM32_IC_TMEM_ADDR_WIDTH{1'b1}}; 1.391 + refill_address <= {`LM32_PC_WIDTH{1'bx}}; 1.392 + restart_request <= `FALSE; 1.393 + end 1.394 + else 1.395 + begin 1.396 + case (state) 1.397 + 1.398 + // Flush the cache for the first time after reset 1.399 + `LM32_IC_STATE_FLUSH_INIT: 1.400 + begin 1.401 + if (flush_set == {`LM32_IC_TMEM_ADDR_WIDTH{1'b0}}) 1.402 + state <= `LM32_IC_STATE_CHECK; 1.403 + flush_set <= flush_set - 1'b1; 1.404 + end 1.405 + 1.406 + // Flush the cache in response to an write to the ICC CSR 1.407 + `LM32_IC_STATE_FLUSH: 1.408 + begin 1.409 + if (flush_set == {`LM32_IC_TMEM_ADDR_WIDTH{1'b0}}) 1.410 +`ifdef CFG_IROM_ENABLED 1.411 + if (select_f) 1.412 + state <= `LM32_IC_STATE_REFILL; 1.413 + else 1.414 +`endif 1.415 + state <= `LM32_IC_STATE_CHECK; 1.416 + 1.417 + flush_set <= flush_set - 1'b1; 1.418 + end 1.419 + 1.420 + // Check for cache misses 1.421 + `LM32_IC_STATE_CHECK: 1.422 + begin 1.423 + if (stall_a == `FALSE) 1.424 + restart_request <= `FALSE; 1.425 + if (iflush == `TRUE) 1.426 + begin 1.427 + refill_address <= address_f; 1.428 + state <= `LM32_IC_STATE_FLUSH; 1.429 + end 1.430 + else if (miss == `TRUE) 1.431 + begin 1.432 + refill_address <= address_f; 1.433 + state <= `LM32_IC_STATE_REFILL; 1.434 + end 1.435 + end 1.436 + 1.437 + // Refill a cache line 1.438 + `LM32_IC_STATE_REFILL: 1.439 + begin 1.440 + if (refill_ready == `TRUE) 1.441 + begin 1.442 + if (last_refill == `TRUE) 1.443 + begin 1.444 + restart_request <= `TRUE; 1.445 + state <= `LM32_IC_STATE_CHECK; 1.446 + end 1.447 + end 1.448 + end 1.449 + 1.450 + endcase 1.451 + end 1.452 +end 1.453 + 1.454 +generate 1.455 + if (bytes_per_line > 4) 1.456 + begin 1.457 +// Refill offset 1.458 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.459 +begin 1.460 + if (rst_i == `TRUE) 1.461 + refill_offset <= {addr_offset_width{1'b0}}; 1.462 + else 1.463 + begin 1.464 + case (state) 1.465 + 1.466 + // Check for cache misses 1.467 + `LM32_IC_STATE_CHECK: 1.468 + begin 1.469 + if (iflush == `TRUE) 1.470 + refill_offset <= {addr_offset_width{1'b0}}; 1.471 + else if (miss == `TRUE) 1.472 + refill_offset <= {addr_offset_width{1'b0}}; 1.473 + end 1.474 + 1.475 + // Refill a cache line 1.476 + `LM32_IC_STATE_REFILL: 1.477 + begin 1.478 + if (refill_ready == `TRUE) 1.479 + refill_offset <= refill_offset + 1'b1; 1.480 + end 1.481 + 1.482 + endcase 1.483 + end 1.484 +end 1.485 + end 1.486 +endgenerate 1.487 + 1.488 +endmodule 1.489 + 1.490 +`endif 1.491 +