Sun, 04 Apr 2010 20:40:03 +0100
add lm32 source
1 // =============================================================================
2 // COPYRIGHT NOTICE
3 // Copyright 2006 (c) Lattice Semiconductor Corporation
4 // ALL RIGHTS RESERVED
5 // This confidential and proprietary software may be used only as authorised by
6 // a licensing agreement from Lattice Semiconductor Corporation.
7 // The entire notice above must be reproduced on all authorized copies and
8 // copies may only be made to the extent permitted by a licensing agreement from
9 // Lattice Semiconductor Corporation.
10 //
11 // Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
12 // 5555 NE Moore Court 408-826-6000 (other locations)
13 // Hillsboro, OR 97124 web : http://www.latticesemi.com/
14 // U.S.A email: techsupport@latticesemi.com
15 // =============================================================================/
16 // FILE DETAILS
17 // Project : LatticeMico32
18 // File : lm32_icache.v
19 // Title : Instruction cache
20 // Dependencies : lm32_include.v
21 //
22 // Version 3.5
23 // 1. Bug Fix: Instruction cache flushes issued from Instruction Inline Memory
24 // cause segmentation fault due to incorrect fetches.
25 //
26 // Version 3.1
27 // 1. Feature: Support for user-selected resource usage when implementing
28 // cache memory. Additional parameters must be defined when invoking module
29 // lm32_ram. Instruction cache miss mechanism is dependent on branch
30 // prediction being performed in D stage of pipeline.
31 //
32 // Version 7.0SP2, 3.0
33 // No change
34 // =============================================================================
36 `include "lm32_include.v"
38 `ifdef CFG_ICACHE_ENABLED
40 `define LM32_IC_ADDR_OFFSET_RNG addr_offset_msb:addr_offset_lsb
41 `define LM32_IC_ADDR_SET_RNG addr_set_msb:addr_set_lsb
42 `define LM32_IC_ADDR_TAG_RNG addr_tag_msb:addr_tag_lsb
43 `define LM32_IC_ADDR_IDX_RNG addr_set_msb:addr_offset_lsb
45 `define LM32_IC_TMEM_ADDR_WIDTH addr_set_width
46 `define LM32_IC_TMEM_ADDR_RNG (`LM32_IC_TMEM_ADDR_WIDTH-1):0
47 `define LM32_IC_DMEM_ADDR_WIDTH (addr_offset_width+addr_set_width)
48 `define LM32_IC_DMEM_ADDR_RNG (`LM32_IC_DMEM_ADDR_WIDTH-1):0
50 `define LM32_IC_TAGS_WIDTH (addr_tag_width+1)
51 `define LM32_IC_TAGS_RNG (`LM32_IC_TAGS_WIDTH-1):0
52 `define LM32_IC_TAGS_TAG_RNG (`LM32_IC_TAGS_WIDTH-1):1
53 `define LM32_IC_TAGS_VALID_RNG 0
55 `define LM32_IC_STATE_RNG 3:0
56 `define LM32_IC_STATE_FLUSH_INIT 4'b0001
57 `define LM32_IC_STATE_FLUSH 4'b0010
58 `define LM32_IC_STATE_CHECK 4'b0100
59 `define LM32_IC_STATE_REFILL 4'b1000
61 /////////////////////////////////////////////////////
62 // Module interface
63 /////////////////////////////////////////////////////
65 module lm32_icache (
66 // ----- Inputs -----
67 clk_i,
68 rst_i,
69 stall_a,
70 stall_f,
71 address_a,
72 address_f,
73 read_enable_f,
74 refill_ready,
75 refill_data,
76 iflush,
77 `ifdef CFG_IROM_ENABLED
78 select_f,
79 `endif
80 valid_d,
81 branch_predict_taken_d,
82 // ----- Outputs -----
83 stall_request,
84 restart_request,
85 refill_request,
86 refill_address,
87 refilling,
88 inst
89 );
91 /////////////////////////////////////////////////////
92 // Parameters
93 /////////////////////////////////////////////////////
95 parameter associativity = 1; // Associativity of the cache (Number of ways)
96 parameter sets = 512; // Number of sets
97 parameter bytes_per_line = 16; // Number of bytes per cache line
98 parameter base_address = 0; // Base address of cachable memory
99 parameter limit = 0; // Limit (highest address) of cachable memory
101 localparam addr_offset_width = clogb2(bytes_per_line)-1-2;
102 localparam addr_set_width = clogb2(sets)-1;
103 localparam addr_offset_lsb = 2;
104 localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
105 localparam addr_set_lsb = (addr_offset_msb+1);
106 localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
107 localparam addr_tag_lsb = (addr_set_msb+1);
108 localparam addr_tag_msb = clogb2(`CFG_ICACHE_LIMIT-`CFG_ICACHE_BASE_ADDRESS)-1;
109 localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);
111 /////////////////////////////////////////////////////
112 // Inputs
113 /////////////////////////////////////////////////////
115 input clk_i; // Clock
116 input rst_i; // Reset
118 input stall_a; // Stall instruction in A stage
119 input stall_f; // Stall instruction in F stage
121 input valid_d; // Valid instruction in D stage
122 input branch_predict_taken_d; // Instruction in D stage is a branch and is predicted taken
124 input [`LM32_PC_RNG] address_a; // Address of instruction in A stage
125 input [`LM32_PC_RNG] address_f; // Address of instruction in F stage
126 input read_enable_f; // Indicates if cache access is valid
128 input refill_ready; // Next word of refill data is ready
129 input [`LM32_INSTRUCTION_RNG] refill_data; // Data to refill the cache with
131 input iflush; // Flush the cache
132 `ifdef CFG_IROM_ENABLED
133 input select_f; // Instruction in F stage is mapped through instruction cache
134 `endif
136 /////////////////////////////////////////////////////
137 // Outputs
138 /////////////////////////////////////////////////////
140 output stall_request; // Request to stall the pipeline
141 wire stall_request;
142 output restart_request; // Request to restart instruction that caused the cache miss
143 reg restart_request;
144 output refill_request; // Request to refill a cache line
145 wire refill_request;
146 output [`LM32_PC_RNG] refill_address; // Base address of cache refill
147 reg [`LM32_PC_RNG] refill_address;
148 output refilling; // Indicates the instruction cache is currently refilling
149 reg refilling;
150 output [`LM32_INSTRUCTION_RNG] inst; // Instruction read from cache
151 wire [`LM32_INSTRUCTION_RNG] inst;
153 /////////////////////////////////////////////////////
154 // Internal nets and registers
155 /////////////////////////////////////////////////////
157 wire enable;
158 wire [0:associativity-1] way_mem_we;
159 wire [`LM32_INSTRUCTION_RNG] way_data[0:associativity-1];
160 wire [`LM32_IC_TAGS_TAG_RNG] way_tag[0:associativity-1];
161 wire [0:associativity-1] way_valid;
162 wire [0:associativity-1] way_match;
163 wire miss;
165 wire [`LM32_IC_TMEM_ADDR_RNG] tmem_read_address;
166 wire [`LM32_IC_TMEM_ADDR_RNG] tmem_write_address;
167 wire [`LM32_IC_DMEM_ADDR_RNG] dmem_read_address;
168 wire [`LM32_IC_DMEM_ADDR_RNG] dmem_write_address;
169 wire [`LM32_IC_TAGS_RNG] tmem_write_data;
171 reg [`LM32_IC_STATE_RNG] state;
172 wire flushing;
173 wire check;
174 wire refill;
176 reg [associativity-1:0] refill_way_select;
177 reg [`LM32_IC_ADDR_OFFSET_RNG] refill_offset;
178 wire last_refill;
179 reg [`LM32_IC_TMEM_ADDR_RNG] flush_set;
181 genvar i;
183 /////////////////////////////////////////////////////
184 // Functions
185 /////////////////////////////////////////////////////
187 `include "lm32_functions.v"
189 /////////////////////////////////////////////////////
190 // Instantiations
191 /////////////////////////////////////////////////////
193 generate
194 for (i = 0; i < associativity; i = i + 1)
195 begin : memories
197 lm32_ram
198 #(
199 // ----- Parameters -------
200 .data_width (32),
201 .address_width (`LM32_IC_DMEM_ADDR_WIDTH),
202 `ifdef CFG_ICACHE_DAT_USE_DP_TRUE
203 .RAM_IMPLEMENTATION ("EBR"),
204 .RAM_TYPE ("RAM_DP_TRUE")
205 `else
206 `ifdef CFG_ICACHE_DAT_USE_DP
207 .RAM_IMPLEMENTATION ("EBR"),
208 .RAM_TYPE ("RAM_DP")
209 `else
210 `ifdef CFG_ICACHE_DAT_USE_SLICE
211 .RAM_IMPLEMENTATION ("SLICE")
212 `else
213 .RAM_IMPLEMENTATION ("AUTO")
214 `endif
215 `endif
216 `endif
217 )
218 way_0_data_ram
219 (
220 // ----- Inputs -------
221 .read_clk (clk_i),
222 .write_clk (clk_i),
223 .reset (rst_i),
224 .read_address (dmem_read_address),
225 .enable_read (enable),
226 .write_address (dmem_write_address),
227 .enable_write (`TRUE),
228 .write_enable (way_mem_we[i]),
229 .write_data (refill_data),
230 // ----- Outputs -------
231 .read_data (way_data[i])
232 );
234 lm32_ram
235 #(
236 // ----- Parameters -------
237 .data_width (`LM32_IC_TAGS_WIDTH),
238 .address_width (`LM32_IC_TMEM_ADDR_WIDTH),
239 `ifdef CFG_ICACHE_DAT_USE_DP_TRUE
240 .RAM_IMPLEMENTATION ("EBR"),
241 .RAM_TYPE ("RAM_DP_TRUE")
242 `else
243 `ifdef CFG_ICACHE_DAT_USE_DP
244 .RAM_IMPLEMENTATION ("EBR"),
245 .RAM_TYPE ("RAM_DP")
246 `else
247 `ifdef CFG_ICACHE_DAT_USE_SLICE
248 .RAM_IMPLEMENTATION ("SLICE")
249 `else
250 .RAM_IMPLEMENTATION ("AUTO")
251 `endif
252 `endif
253 `endif
254 )
255 way_0_tag_ram
256 (
257 // ----- Inputs -------
258 .read_clk (clk_i),
259 .write_clk (clk_i),
260 .reset (rst_i),
261 .read_address (tmem_read_address),
262 .enable_read (enable),
263 .write_address (tmem_write_address),
264 .enable_write (`TRUE),
265 .write_enable (way_mem_we[i] | flushing),
266 .write_data (tmem_write_data),
267 // ----- Outputs -------
268 .read_data ({way_tag[i], way_valid[i]})
269 );
271 end
272 endgenerate
274 /////////////////////////////////////////////////////
275 // Combinational logic
276 /////////////////////////////////////////////////////
278 // Compute which ways in the cache match the address address being read
279 generate
280 for (i = 0; i < associativity; i = i + 1)
281 begin : match
282 assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_f[`LM32_IC_ADDR_TAG_RNG], `TRUE});
283 end
284 endgenerate
286 // Select data from way that matched the address being read
287 generate
288 if (associativity == 1)
289 begin : inst_1
290 assign inst = way_match[0] ? way_data[0] : 32'b0;
291 end
292 else if (associativity == 2)
293 begin : inst_2
294 assign inst = way_match[0] ? way_data[0] : (way_match[1] ? way_data[1] : 32'b0);
295 end
296 endgenerate
298 // Compute address to use to index into the data memories
299 generate
300 if (bytes_per_line > 4)
301 assign dmem_write_address = {refill_address[`LM32_IC_ADDR_SET_RNG], refill_offset};
302 else
303 assign dmem_write_address = refill_address[`LM32_IC_ADDR_SET_RNG];
304 endgenerate
306 assign dmem_read_address = address_a[`LM32_IC_ADDR_IDX_RNG];
308 // Compute address to use to index into the tag memories
309 assign tmem_read_address = address_a[`LM32_IC_ADDR_SET_RNG];
310 assign tmem_write_address = flushing
311 ? flush_set
312 : refill_address[`LM32_IC_ADDR_SET_RNG];
314 // Compute signal to indicate when we are on the last refill accesses
315 generate
316 if (bytes_per_line > 4)
317 assign last_refill = refill_offset == {addr_offset_width{1'b1}};
318 else
319 assign last_refill = `TRUE;
320 endgenerate
322 // Compute data and tag memory access enable
323 assign enable = (stall_a == `FALSE);
325 // Compute data and tag memory write enables
326 generate
327 if (associativity == 1)
328 begin : we_1
329 assign way_mem_we[0] = (refill_ready == `TRUE);
330 end
331 else
332 begin : we_2
333 assign way_mem_we[0] = (refill_ready == `TRUE) && (refill_way_select[0] == `TRUE);
334 assign way_mem_we[1] = (refill_ready == `TRUE) && (refill_way_select[1] == `TRUE);
335 end
336 endgenerate
338 // On the last refill cycle set the valid bit, for all other writes it should be cleared
339 assign tmem_write_data[`LM32_IC_TAGS_VALID_RNG] = last_refill & !flushing;
340 assign tmem_write_data[`LM32_IC_TAGS_TAG_RNG] = refill_address[`LM32_IC_ADDR_TAG_RNG];
342 // Signals that indicate which state we are in
343 assign flushing = |state[1:0];
344 assign check = state[2];
345 assign refill = state[3];
347 assign miss = (~(|way_match)) && (read_enable_f == `TRUE) && (stall_f == `FALSE) && !(valid_d && branch_predict_taken_d);
348 assign stall_request = (check == `FALSE);
349 assign refill_request = (refill == `TRUE);
351 /////////////////////////////////////////////////////
352 // Sequential logic
353 /////////////////////////////////////////////////////
355 // Record way selected for replacement on a cache miss
356 generate
357 if (associativity >= 2)
358 begin : way_select
359 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
360 begin
361 if (rst_i == `TRUE)
362 refill_way_select <= {{associativity-1{1'b0}}, 1'b1};
363 else
364 begin
365 if (miss == `TRUE)
366 refill_way_select <= {refill_way_select[0], refill_way_select[1]};
367 end
368 end
369 end
370 endgenerate
372 // Record whether we are refilling
373 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
374 begin
375 if (rst_i == `TRUE)
376 refilling <= `FALSE;
377 else
378 refilling <= refill;
379 end
381 // Instruction cache control FSM
382 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
383 begin
384 if (rst_i == `TRUE)
385 begin
386 state <= `LM32_IC_STATE_FLUSH_INIT;
387 flush_set <= {`LM32_IC_TMEM_ADDR_WIDTH{1'b1}};
388 refill_address <= {`LM32_PC_WIDTH{1'bx}};
389 restart_request <= `FALSE;
390 end
391 else
392 begin
393 case (state)
395 // Flush the cache for the first time after reset
396 `LM32_IC_STATE_FLUSH_INIT:
397 begin
398 if (flush_set == {`LM32_IC_TMEM_ADDR_WIDTH{1'b0}})
399 state <= `LM32_IC_STATE_CHECK;
400 flush_set <= flush_set - 1'b1;
401 end
403 // Flush the cache in response to an write to the ICC CSR
404 `LM32_IC_STATE_FLUSH:
405 begin
406 if (flush_set == {`LM32_IC_TMEM_ADDR_WIDTH{1'b0}})
407 `ifdef CFG_IROM_ENABLED
408 if (select_f)
409 state <= `LM32_IC_STATE_REFILL;
410 else
411 `endif
412 state <= `LM32_IC_STATE_CHECK;
414 flush_set <= flush_set - 1'b1;
415 end
417 // Check for cache misses
418 `LM32_IC_STATE_CHECK:
419 begin
420 if (stall_a == `FALSE)
421 restart_request <= `FALSE;
422 if (iflush == `TRUE)
423 begin
424 refill_address <= address_f;
425 state <= `LM32_IC_STATE_FLUSH;
426 end
427 else if (miss == `TRUE)
428 begin
429 refill_address <= address_f;
430 state <= `LM32_IC_STATE_REFILL;
431 end
432 end
434 // Refill a cache line
435 `LM32_IC_STATE_REFILL:
436 begin
437 if (refill_ready == `TRUE)
438 begin
439 if (last_refill == `TRUE)
440 begin
441 restart_request <= `TRUE;
442 state <= `LM32_IC_STATE_CHECK;
443 end
444 end
445 end
447 endcase
448 end
449 end
451 generate
452 if (bytes_per_line > 4)
453 begin
454 // Refill offset
455 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
456 begin
457 if (rst_i == `TRUE)
458 refill_offset <= {addr_offset_width{1'b0}};
459 else
460 begin
461 case (state)
463 // Check for cache misses
464 `LM32_IC_STATE_CHECK:
465 begin
466 if (iflush == `TRUE)
467 refill_offset <= {addr_offset_width{1'b0}};
468 else if (miss == `TRUE)
469 refill_offset <= {addr_offset_width{1'b0}};
470 end
472 // Refill a cache line
473 `LM32_IC_STATE_REFILL:
474 begin
475 if (refill_ready == `TRUE)
476 refill_offset <= refill_offset + 1'b1;
477 end
479 endcase
480 end
481 end
482 end
483 endgenerate
485 endmodule
487 `endif