Sun, 04 Apr 2010 20:40:03 +0100
add lm32 source
1.1 diff -r 000000000000 -r cd0b58aa6f83 JTAGB.v 1.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 1.3 +++ b/JTAGB.v Sun Apr 04 20:40:03 2010 +0100 1.4 @@ -0,0 +1,42 @@ 1.5 +// ============================================================================= 1.6 +// COPYRIGHT NOTICE 1.7 +// Copyright 2006 (c) Lattice Semiconductor Corporation 1.8 +// ALL RIGHTS RESERVED 1.9 +// This confidential and proprietary software may be used only as authorised by 1.10 +// a licensing agreement from Lattice Semiconductor Corporation. 1.11 +// The entire notice above must be reproduced on all authorized copies and 1.12 +// copies may only be made to the extent permitted by a licensing agreement from 1.13 +// Lattice Semiconductor Corporation. 1.14 +// 1.15 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 1.16 +// 5555 NE Moore Court 408-826-6000 (other locations) 1.17 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 1.18 +// U.S.A email: techsupport@latticesemi.com 1.19 +// =============================================================================/ 1.20 +// FILE DETAILS 1.21 +// Project : LatticeMico32 1.22 +// File : JTAGB.v 1.23 +// Title : JTAGB Black Box 1.24 +// Dependencies : None 1.25 +// Version : 6.0.14 1.26 +// : Initial Release 1.27 +// Version : 7.0SP2, 3.0 1.28 +// : No Change 1.29 +// Version : 3.1 1.30 +// : No Change 1.31 +// ============================================================================= 1.32 +module JTAGB ( 1.33 + output JTCK, 1.34 + output JRTI1, 1.35 + output JRTI2, 1.36 + output JTDI, 1.37 + output JSHIFT, 1.38 + output JUPDATE, 1.39 + output JRSTN, 1.40 + output JCE1, 1.41 + output JCE2, 1.42 + input JTDO1, 1.43 + input JTDO2 1.44 + ) /*synthesis syn_black_box */; 1.45 + 1.46 +endmodule
2.1 diff -r 000000000000 -r cd0b58aa6f83 er1.v 2.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 2.3 +++ b/er1.v Sun Apr 04 20:40:03 2010 +0100 2.4 @@ -0,0 +1,230 @@ 2.5 +// ============================================================================= 2.6 +// COPYRIGHT NOTICE 2.7 +// Copyright 2006 (c) Lattice Semiconductor Corporation 2.8 +// ALL RIGHTS RESERVED 2.9 +// This confidential and proprietary software may be used only as authorised by 2.10 +// a licensing agreement from Lattice Semiconductor Corporation. 2.11 +// The entire notice above must be reproduced on all authorized copies and 2.12 +// copies may only be made to the extent permitted by a licensing agreement from 2.13 +// Lattice Semiconductor Corporation. 2.14 +// 2.15 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 2.16 +// 5555 NE Moore Court 408-826-6000 (other locations) 2.17 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 2.18 +// U.S.A email: techsupport@latticesemi.com 2.19 +// =============================================================================/ 2.20 +// FILE DETAILS 2.21 +// Project : LatticeMico32 2.22 +// File : er1.v 2.23 +// Description: 2.24 +// This module is where the ER1 register implemented. ER1 and ER2 registers 2.25 +// can be registers implemented in Lattice FPGAs using normal FPGA's 2.26 +// programmable logic resources. Once they are implemented, they can be 2.27 +// accessed as if they are JTAG data registers through the FPGA JTAG port. 2.28 +// In order to accessing these registers, JTAG instructions ER1(0x32) or 2.29 +// ER2(0x38) needs to be written to the JTAG IR register for enabling the 2.30 +// ER1/ER2 accessing logic. The ER1 or ER2 accessing logic can only be 2.31 +// enabled one at a time. Once they are enabled, they will be disabled if 2.32 +// another JTAG instruction is written into the JTAG instruction register. 2.33 +// The registers allow dynamically accessing the FPGA internal information 2.34 +// even when the device is running. Therefore, they are very useful for some 2.35 +// of the IP cores. In order to let ER1/ER2 registers shared by multiple IP 2.36 +// cores or other designs, there is a ER1/ER2 structure patterned by Lattice. 2.37 +// The ER1/ER2 structure allows only one ER1 register but more than one ER2 2.38 +// registers in an FPGA device. Please refer to the related document for 2.39 +// this patterned ER1/ER2 structure. 2.40 +// Dependencies : None 2.41 +// Version : 6.0.14 2.42 +// : Initial Version 2.43 +// Version : 7.0SP2, 3.0 2.44 +// : No Change 2.45 +// Version : 3.1 2.46 +// : No Change 2.47 +// ============================================================================= 2.48 +module ER1 (input JTCK, 2.49 + input JTDI, 2.50 + output JTDO1, 2.51 + output reg JTDO2, 2.52 + input JSHIFT, 2.53 + input JUPDATE, 2.54 + input JRSTN, 2.55 + input JCE1, 2.56 + input [14:0] ER2_TDO, 2.57 + output reg [14:0] IP_ENABLE, 2.58 + input ISPTRACY_ER2_TDO, 2.59 + output ISPTRACY_ENABLE, 2.60 + output CONTROL_DATAN)/* synthesis syn_hier = hard */; 2.61 + 2.62 + 2.63 + wire controlDataNBit; 2.64 + wire ispTracyEnableBit; 2.65 + wire [3:0] encodedIpEnableBits; 2.66 + wire [9:0] er1TdiBit; 2.67 + wire captureDrER1; 2.68 + 2.69 + 2.70 + assign JTDO1 = er1TdiBit[0]; 2.71 + 2.72 + TYPEB BIT0 (.CLK(JTCK), 2.73 + .RESET_N(JRSTN), 2.74 + .CLKEN(JCE1), 2.75 + .TDI(er1TdiBit[1]), 2.76 + .TDO(er1TdiBit[0]), 2.77 + .DATA_IN(1'b0), 2.78 + .CAPTURE_DR(captureDrER1)); 2.79 + 2.80 + TYPEB BIT1 (.CLK(JTCK), 2.81 + .RESET_N(JRSTN), 2.82 + .CLKEN(JCE1), 2.83 + .TDI(er1TdiBit[2]), 2.84 + .TDO(er1TdiBit[1]), 2.85 + .DATA_IN(1'b0), 2.86 + .CAPTURE_DR(captureDrER1)); 2.87 + 2.88 + TYPEB BIT2 (.CLK(JTCK), 2.89 + .RESET_N(JRSTN), 2.90 + .CLKEN(JCE1), 2.91 + .TDI(er1TdiBit[3]), 2.92 + .TDO(er1TdiBit[2]), 2.93 + .DATA_IN(1'b1), 2.94 + .CAPTURE_DR(captureDrER1)); 2.95 + 2.96 + TYPEA BIT3 (.CLK(JTCK), 2.97 + .RESET_N(JRSTN), 2.98 + .CLKEN(JCE1), 2.99 + .TDI(er1TdiBit[4]), 2.100 + .TDO(er1TdiBit[3]), 2.101 + .DATA_OUT(controlDataNBit), 2.102 + .DATA_IN(controlDataNBit), 2.103 + .CAPTURE_DR(captureDrER1), 2.104 + .UPDATE_DR(JUPDATE)); 2.105 + 2.106 + assign CONTROL_DATAN = controlDataNBit; 2.107 + 2.108 + TYPEA BIT4 (.CLK(JTCK), 2.109 + .RESET_N(JRSTN), 2.110 + .CLKEN(JCE1), 2.111 + .TDI(er1TdiBit[5]), 2.112 + .TDO(er1TdiBit[4]), 2.113 + .DATA_OUT(ispTracyEnableBit), 2.114 + .DATA_IN(ispTracyEnableBit), 2.115 + .CAPTURE_DR(captureDrER1), 2.116 + .UPDATE_DR(JUPDATE) 2.117 + ); 2.118 + 2.119 + assign ISPTRACY_ENABLE = ispTracyEnableBit; 2.120 + 2.121 + TYPEA BIT5 (.CLK(JTCK), 2.122 + .RESET_N(JRSTN), 2.123 + .CLKEN(JCE1), 2.124 + .TDI(er1TdiBit[6]), 2.125 + .TDO(er1TdiBit[5]), 2.126 + .DATA_OUT(encodedIpEnableBits[0]), 2.127 + .DATA_IN(encodedIpEnableBits[0]), 2.128 + .CAPTURE_DR(captureDrER1), 2.129 + .UPDATE_DR(JUPDATE)); 2.130 + 2.131 + TYPEA BIT6 (.CLK(JTCK), 2.132 + .RESET_N(JRSTN), 2.133 + .CLKEN(JCE1), 2.134 + .TDI(er1TdiBit[7]), 2.135 + .TDO(er1TdiBit[6]), 2.136 + .DATA_OUT(encodedIpEnableBits[1]), 2.137 + .DATA_IN(encodedIpEnableBits[1]), 2.138 + .CAPTURE_DR(captureDrER1), 2.139 + .UPDATE_DR(JUPDATE)); 2.140 + 2.141 + TYPEA BIT7 (.CLK(JTCK), 2.142 + .RESET_N(JRSTN), 2.143 + .CLKEN(JCE1), 2.144 + .TDI(er1TdiBit[8]), 2.145 + .TDO(er1TdiBit[7]), 2.146 + .DATA_OUT(encodedIpEnableBits[2]), 2.147 + .DATA_IN(encodedIpEnableBits[2]), 2.148 + .CAPTURE_DR(captureDrER1), 2.149 + .UPDATE_DR(JUPDATE)); 2.150 + 2.151 + TYPEA BIT8 (.CLK(JTCK), 2.152 + .RESET_N(JRSTN), 2.153 + .CLKEN(JCE1), 2.154 + .TDI(er1TdiBit[9]), 2.155 + .TDO(er1TdiBit[8]), 2.156 + .DATA_OUT(encodedIpEnableBits[3]), 2.157 + .DATA_IN(encodedIpEnableBits[3]), 2.158 + .CAPTURE_DR(captureDrER1), 2.159 + .UPDATE_DR(JUPDATE) 2.160 + ); 2.161 + 2.162 + assign er1TdiBit[9] = JTDI; 2.163 + assign captureDrER1 = !JSHIFT & JCE1; 2.164 + 2.165 + always @ (encodedIpEnableBits,ISPTRACY_ER2_TDO, ER2_TDO) 2.166 + begin 2.167 + case (encodedIpEnableBits) 2.168 + 4'h0: begin 2.169 + IP_ENABLE <= 15'b000000000000000; 2.170 + JTDO2 <= ISPTRACY_ER2_TDO; 2.171 + end 2.172 + 4'h1: begin 2.173 + IP_ENABLE <= 15'b000000000000001; 2.174 + JTDO2 <= ER2_TDO[0]; 2.175 + end 2.176 + 4'h2: begin 2.177 + IP_ENABLE <= 15'b000000000000010; 2.178 + JTDO2 <= ER2_TDO[1]; 2.179 + end 2.180 + 4'h3: begin 2.181 + IP_ENABLE <= 15'b000000000000100; 2.182 + JTDO2 <= ER2_TDO[2]; 2.183 + end 2.184 + 4'h4: begin 2.185 + IP_ENABLE <= 15'b000000000001000; 2.186 + JTDO2 <= ER2_TDO[3]; 2.187 + end 2.188 + 4'h5: begin 2.189 + IP_ENABLE <= 15'b000000000010000; 2.190 + JTDO2 <= ER2_TDO[4]; 2.191 + end 2.192 + 4'h6: begin 2.193 + IP_ENABLE <= 15'b000000000100000; 2.194 + JTDO2 <= ER2_TDO[5]; 2.195 + end 2.196 + 4'h7: begin 2.197 + IP_ENABLE <= 15'b000000001000000; 2.198 + JTDO2 <= ER2_TDO[6]; 2.199 + end 2.200 + 4'h8: begin 2.201 + IP_ENABLE <= 15'b000000010000000; 2.202 + JTDO2 <= ER2_TDO[7]; 2.203 + end 2.204 + 4'h9: begin 2.205 + IP_ENABLE <= 15'b000000100000000; 2.206 + JTDO2 <= ER2_TDO[8]; 2.207 + end 2.208 + 4'hA: begin 2.209 + IP_ENABLE <= 15'b000001000000000; 2.210 + JTDO2 <= ER2_TDO[9]; 2.211 + end 2.212 + 4'hB: begin 2.213 + IP_ENABLE <= 15'b000010000000000; 2.214 + JTDO2 <= ER2_TDO[10]; 2.215 + end 2.216 + 4'hC: begin 2.217 + IP_ENABLE <= 15'b000100000000000; 2.218 + JTDO2 <= ER2_TDO[11]; 2.219 + end 2.220 + 4'hD: begin 2.221 + IP_ENABLE <= 15'b001000000000000; 2.222 + JTDO2 <= ER2_TDO[12]; 2.223 + end 2.224 + 4'hE: begin 2.225 + IP_ENABLE <= 15'b010000000000000; 2.226 + JTDO2 <= ER2_TDO[13]; 2.227 + end 2.228 + 4'hF: begin 2.229 + IP_ENABLE <= 15'b100000000000000; 2.230 + JTDO2 <= ER2_TDO[14]; 2.231 + end 2.232 + endcase 2.233 + end 2.234 +endmodule
3.1 diff -r 000000000000 -r cd0b58aa6f83 jtag_cores.v 3.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 3.3 +++ b/jtag_cores.v Sun Apr 04 20:40:03 2010 +0100 3.4 @@ -0,0 +1,125 @@ 3.5 +// ============================================================================ 3.6 +// COPYRIGHT NOTICE 3.7 +// Copyright 2006 (c) Lattice Semiconductor Corporation 3.8 +// ALL RIGHTS RESERVED 3.9 +// This confidential and proprietary software may be used only as authorised by 3.10 +// a licensing agreement from Lattice Semiconductor Corporation. 3.11 +// The entire notice above must be reproduced on all authorized copies and 3.12 +// copies may only be made to the extent permitted by a licensing agreement from 3.13 +// Lattice Semiconductor Corporation. 3.14 +// 3.15 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 3.16 +// 5555 NE Moore Court 408-826-6000 (other locations) 3.17 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 3.18 +// U.S.A email: techsupport@latticesemi.com 3.19 +// ============================================================================/ 3.20 +// FILE DETAILS 3.21 +// Project : LatticeMico32 3.22 +// File : jtag_cores.v 3.23 +// Title : Instantiates all IP cores on JTAG chain. 3.24 +// Dependencies : system_conf.v 3.25 +// Version : 6.0.14 3.26 +// : modified to use jtagconn for LM32, 3.27 +// : all technologies 7/10/07 3.28 +// Version : 7.0SP2, 3.0 3.29 +// : No Change 3.30 +// Version : 3.1 3.31 +// : No Change 3.32 +// ============================================================================ 3.33 + 3.34 +`include "system_conf.v" 3.35 + 3.36 +///////////////////////////////////////////////////// 3.37 +// jtagconn16 Module Definition 3.38 +///////////////////////////////////////////////////// 3.39 + 3.40 +module jtagconn16 (er2_tdo, jtck, jtdi, jshift, jupdate, jrstn, jce2, ip_enable) ; 3.41 + input er2_tdo ; 3.42 + output jtck ; 3.43 + output jtdi ; 3.44 + output jshift ; 3.45 + output jupdate ; 3.46 + output jrstn ; 3.47 + output jce2 ; 3.48 + output ip_enable ; 3.49 +endmodule 3.50 + 3.51 +///////////////////////////////////////////////////// 3.52 +// Module interface 3.53 +///////////////////////////////////////////////////// 3.54 + 3.55 +(* syn_hier="hard" *) module jtag_cores ( 3.56 + // ----- Inputs ------- 3.57 + reg_d, 3.58 + reg_addr_d, 3.59 + // ----- Outputs ------- 3.60 + reg_update, 3.61 + reg_q, 3.62 + reg_addr_q, 3.63 + jtck, 3.64 + jrstn 3.65 + ); 3.66 + 3.67 +///////////////////////////////////////////////////// 3.68 +// Inputs 3.69 +///////////////////////////////////////////////////// 3.70 + 3.71 +input [7:0] reg_d; 3.72 +input [2:0] reg_addr_d; 3.73 + 3.74 +///////////////////////////////////////////////////// 3.75 +// Outputs 3.76 +///////////////////////////////////////////////////// 3.77 + 3.78 +output reg_update; 3.79 +wire reg_update; 3.80 +output [7:0] reg_q; 3.81 +wire [7:0] reg_q; 3.82 +output [2:0] reg_addr_q; 3.83 +wire [2:0] reg_addr_q; 3.84 + 3.85 +output jtck; 3.86 +wire jtck; /* synthesis syn_keep=1 */ 3.87 +output jrstn; 3.88 +wire jrstn; /* synthesis syn_keep=1 */ 3.89 + 3.90 +///////////////////////////////////////////////////// 3.91 +// Instantiations 3.92 +///////////////////////////////////////////////////// 3.93 + 3.94 +wire jtdi; /* synthesis syn_keep=1 */ 3.95 +wire er2_tdo2; /* synthesis syn_keep=1 */ 3.96 +wire jshift; /* synthesis syn_keep=1 */ 3.97 +wire jupdate; /* synthesis syn_keep=1 */ 3.98 +wire jce2; /* synthesis syn_keep=1 */ 3.99 +wire ip_enable; /* synthesis syn_keep=1 */ 3.100 + 3.101 +(* JTAG_IP="LM32", IP_ID="0", HUB_ID="0", syn_noprune=1 *) jtagconn16 jtagconn16_lm32_inst ( 3.102 + .er2_tdo (er2_tdo2), 3.103 + .jtck (jtck), 3.104 + .jtdi (jtdi), 3.105 + .jshift (jshift), 3.106 + .jupdate (jupdate), 3.107 + .jrstn (jrstn), 3.108 + .jce2 (jce2), 3.109 + .ip_enable (ip_enable) 3.110 +); 3.111 + 3.112 +(* syn_noprune=1 *) jtag_lm32 jtag_lm32_inst ( 3.113 + .JTCK (jtck), 3.114 + .JTDI (jtdi), 3.115 + .JTDO2 (er2_tdo2), 3.116 + .JSHIFT (jshift), 3.117 + .JUPDATE (jupdate), 3.118 + .JRSTN (jrstn), 3.119 + .JCE2 (jce2), 3.120 + .JTAGREG_ENABLE (ip_enable), 3.121 + .CONTROL_DATAN (), 3.122 + .REG_UPDATE (reg_update), 3.123 + .REG_D (reg_d), 3.124 + .REG_ADDR_D (reg_addr_d), 3.125 + .REG_Q (reg_q), 3.126 + .REG_ADDR_Q (reg_addr_q) 3.127 + ); 3.128 + 3.129 +endmodule
4.1 diff -r 000000000000 -r cd0b58aa6f83 jtag_lm32.v 4.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 4.3 +++ b/jtag_lm32.v Sun Apr 04 20:40:03 2010 +0100 4.4 @@ -0,0 +1,200 @@ 4.5 +// ============================================================================= 4.6 +// COPYRIGHT NOTICE 4.7 +// Copyright 2006 (c) Lattice Semiconductor Corporation 4.8 +// ALL RIGHTS RESERVED 4.9 +// This confidential and proprietary software may be used only as authorised by 4.10 +// a licensing agreement from Lattice Semiconductor Corporation. 4.11 +// The entire notice above must be reproduced on all authorized copies and 4.12 +// copies may only be made to the extent permitted by a licensing agreement from 4.13 +// Lattice Semiconductor Corporation. 4.14 +// 4.15 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 4.16 +// 5555 NE Moore Court 408-826-6000 (other locations) 4.17 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 4.18 +// U.S.A email: techsupport@latticesemi.com 4.19 +// =============================================================================/ 4.20 +// FILE DETAILS 4.21 +// Project : LatticeMico32 4.22 +// File : jtag_lm32.v 4.23 +// Title : JTAG data register for LM32 CPU debug interface 4.24 +// Version : 6.0.13 4.25 +// : Initial Release 4.26 +// Version : 7.0SP2, 3.0 4.27 +// : No Change 4.28 +// Version : 3.1 4.29 +// : No Change 4.30 +// ============================================================================= 4.31 + 4.32 +///////////////////////////////////////////////////// 4.33 +// Module interface 4.34 +///////////////////////////////////////////////////// 4.35 + 4.36 +module jtag_lm32 ( 4.37 + input JTCK, 4.38 + input JTDI, 4.39 + output JTDO2, 4.40 + input JSHIFT, 4.41 + input JUPDATE, 4.42 + input JRSTN, 4.43 + input JCE2, 4.44 + input JTAGREG_ENABLE, 4.45 + input CONTROL_DATAN, 4.46 + output REG_UPDATE, 4.47 + input [7:0] REG_D, 4.48 + input [2:0] REG_ADDR_D, 4.49 + output [7:0] REG_Q, 4.50 + output [2:0] REG_ADDR_Q 4.51 + ); 4.52 + 4.53 +///////////////////////////////////////////////////// 4.54 +// Internal nets and registers 4.55 +///////////////////////////////////////////////////// 4.56 + 4.57 +wire [9:0] tdibus; 4.58 + 4.59 +///////////////////////////////////////////////////// 4.60 +// Instantiations 4.61 +///////////////////////////////////////////////////// 4.62 + 4.63 +TYPEA DATA_BIT0 ( 4.64 + .CLK(JTCK), 4.65 + .RESET_N(JRSTN), 4.66 + .CLKEN(clk_enable), 4.67 + .TDI(JTDI), 4.68 + .TDO(tdibus[0]), 4.69 + .DATA_OUT(REG_Q[0]), 4.70 + .DATA_IN(REG_D[0]), 4.71 + .CAPTURE_DR(captureDr), 4.72 + .UPDATE_DR(JUPDATE) 4.73 + ); 4.74 + 4.75 +TYPEA DATA_BIT1 ( 4.76 + .CLK(JTCK), 4.77 + .RESET_N(JRSTN), 4.78 + .CLKEN(clk_enable), 4.79 + .TDI(tdibus[0]), 4.80 + .TDO(tdibus[1]), 4.81 + .DATA_OUT(REG_Q[1]), 4.82 + .DATA_IN(REG_D[1]), 4.83 + .CAPTURE_DR(captureDr), 4.84 + .UPDATE_DR(JUPDATE) 4.85 + ); 4.86 + 4.87 +TYPEA DATA_BIT2 ( 4.88 + .CLK(JTCK), 4.89 + .RESET_N(JRSTN), 4.90 + .CLKEN(clk_enable), 4.91 + .TDI(tdibus[1]), 4.92 + .TDO(tdibus[2]), 4.93 + .DATA_OUT(REG_Q[2]), 4.94 + .DATA_IN(REG_D[2]), 4.95 + .CAPTURE_DR(captureDr), 4.96 + .UPDATE_DR(JUPDATE) 4.97 + ); 4.98 + 4.99 +TYPEA DATA_BIT3 ( 4.100 + .CLK(JTCK), 4.101 + .RESET_N(JRSTN), 4.102 + .CLKEN(clk_enable), 4.103 + .TDI(tdibus[2]), 4.104 + .TDO(tdibus[3]), 4.105 + .DATA_OUT(REG_Q[3]), 4.106 + .DATA_IN(REG_D[3]), 4.107 + .CAPTURE_DR(captureDr), 4.108 + .UPDATE_DR(JUPDATE) 4.109 + ); 4.110 + 4.111 +TYPEA DATA_BIT4 ( 4.112 + .CLK(JTCK), 4.113 + .RESET_N(JRSTN), 4.114 + .CLKEN(clk_enable), 4.115 + .TDI(tdibus[3]), 4.116 + .TDO(tdibus[4]), 4.117 + .DATA_OUT(REG_Q[4]), 4.118 + .DATA_IN(REG_D[4]), 4.119 + .CAPTURE_DR(captureDr), 4.120 + .UPDATE_DR(JUPDATE) 4.121 + ); 4.122 + 4.123 +TYPEA DATA_BIT5 ( 4.124 + .CLK(JTCK), 4.125 + .RESET_N(JRSTN), 4.126 + .CLKEN(clk_enable), 4.127 + .TDI(tdibus[4]), 4.128 + .TDO(tdibus[5]), 4.129 + .DATA_OUT(REG_Q[5]), 4.130 + .DATA_IN(REG_D[5]), 4.131 + .CAPTURE_DR(captureDr), 4.132 + .UPDATE_DR(JUPDATE) 4.133 + ); 4.134 + 4.135 +TYPEA DATA_BIT6 ( 4.136 + .CLK(JTCK), 4.137 + .RESET_N(JRSTN), 4.138 + .CLKEN(clk_enable), 4.139 + .TDI(tdibus[5]), 4.140 + .TDO(tdibus[6]), 4.141 + .DATA_OUT(REG_Q[6]), 4.142 + .DATA_IN(REG_D[6]), 4.143 + .CAPTURE_DR(captureDr), 4.144 + .UPDATE_DR(JUPDATE) 4.145 + ); 4.146 + 4.147 +TYPEA DATA_BIT7 ( 4.148 + .CLK(JTCK), 4.149 + .RESET_N(JRSTN), 4.150 + .CLKEN(clk_enable), 4.151 + .TDI(tdibus[6]), 4.152 + .TDO(tdibus[7]), 4.153 + .DATA_OUT(REG_Q[7]), 4.154 + .DATA_IN(REG_D[7]), 4.155 + .CAPTURE_DR(captureDr), 4.156 + .UPDATE_DR(JUPDATE) 4.157 + ); 4.158 + 4.159 +TYPEA ADDR_BIT0 ( 4.160 + .CLK(JTCK), 4.161 + .RESET_N(JRSTN), 4.162 + .CLKEN(clk_enable), 4.163 + .TDI(tdibus[7]), 4.164 + .TDO(tdibus[8]), 4.165 + .DATA_OUT(REG_ADDR_Q[0]), 4.166 + .DATA_IN(REG_ADDR_D[0]), 4.167 + .CAPTURE_DR(captureDr), 4.168 + .UPDATE_DR(JUPDATE) 4.169 + ); 4.170 + 4.171 +TYPEA ADDR_BIT1 ( 4.172 + .CLK(JTCK), 4.173 + .RESET_N(JRSTN), 4.174 + .CLKEN(clk_enable), 4.175 + .TDI(tdibus[8]), 4.176 + .TDO(tdibus[9]), 4.177 + .DATA_OUT(REG_ADDR_Q[1]), 4.178 + .DATA_IN(REG_ADDR_D[1]), 4.179 + .CAPTURE_DR(captureDr), 4.180 + .UPDATE_DR(JUPDATE) 4.181 + ); 4.182 + 4.183 +TYPEA ADDR_BIT2 ( 4.184 + .CLK(JTCK), 4.185 + .RESET_N(JRSTN), 4.186 + .CLKEN(clk_enable), 4.187 + .TDI(tdibus[9]), 4.188 + .TDO(JTDO2), 4.189 + .DATA_OUT(REG_ADDR_Q[2]), 4.190 + .DATA_IN(REG_ADDR_D[2]), 4.191 + .CAPTURE_DR(captureDr), 4.192 + .UPDATE_DR(JUPDATE) 4.193 + ); 4.194 + 4.195 +///////////////////////////////////////////////////// 4.196 +// Combinational logic 4.197 +///////////////////////////////////////////////////// 4.198 + 4.199 +assign clk_enable = JTAGREG_ENABLE & JCE2; 4.200 +assign captureDr = !JSHIFT & JCE2; 4.201 +// JCE2 is only active during shift 4.202 +assign REG_UPDATE = JTAGREG_ENABLE & JUPDATE; 4.203 + 4.204 +endmodule
5.1 diff -r 000000000000 -r cd0b58aa6f83 lm32_adder.v 5.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 5.3 +++ b/lm32_adder.v Sun Apr 04 20:40:03 2010 +0100 5.4 @@ -0,0 +1,115 @@ 5.5 +// ============================================================================= 5.6 +// COPYRIGHT NOTICE 5.7 +// Copyright 2006 (c) Lattice Semiconductor Corporation 5.8 +// ALL RIGHTS RESERVED 5.9 +// This confidential and proprietary software may be used only as authorised by 5.10 +// a licensing agreement from Lattice Semiconductor Corporation. 5.11 +// The entire notice above must be reproduced on all authorized copies and 5.12 +// copies may only be made to the extent permitted by a licensing agreement from 5.13 +// Lattice Semiconductor Corporation. 5.14 +// 5.15 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 5.16 +// 5555 NE Moore Court 408-826-6000 (other locations) 5.17 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 5.18 +// U.S.A email: techsupport@latticesemi.com 5.19 +// ============================================================================/ 5.20 +// FILE DETAILS 5.21 +// Project : LatticeMico32 5.22 +// File : lm32_adder.v 5.23 +// Title : Integer adder / subtractor with comparison flag generation 5.24 +// Dependencies : lm32_include.v 5.25 +// Version : 6.1.17 5.26 +// : Initial Release 5.27 +// Version : 7.0SP2, 3.0 5.28 +// : No Change 5.29 +// Version : 3.1 5.30 +// : No Change 5.31 +// ============================================================================= 5.32 + 5.33 +`include "lm32_include.v" 5.34 + 5.35 +///////////////////////////////////////////////////// 5.36 +// Module interface 5.37 +///////////////////////////////////////////////////// 5.38 + 5.39 +module lm32_adder ( 5.40 + // ----- Inputs ------- 5.41 + adder_op_x, 5.42 + adder_op_x_n, 5.43 + operand_0_x, 5.44 + operand_1_x, 5.45 + // ----- Outputs ------- 5.46 + adder_result_x, 5.47 + adder_carry_n_x, 5.48 + adder_overflow_x 5.49 + ); 5.50 + 5.51 +///////////////////////////////////////////////////// 5.52 +// Inputs 5.53 +///////////////////////////////////////////////////// 5.54 + 5.55 +input adder_op_x; // Operating to perform, 0 for addition, 1 for subtraction 5.56 +input adder_op_x_n; // Inverted version of adder_op_x 5.57 +input [`LM32_WORD_RNG] operand_0_x; // Operand to add, or subtract from 5.58 +input [`LM32_WORD_RNG] operand_1_x; // Opearnd to add, or subtract by 5.59 + 5.60 +///////////////////////////////////////////////////// 5.61 +// Outputs 5.62 +///////////////////////////////////////////////////// 5.63 + 5.64 +output [`LM32_WORD_RNG] adder_result_x; // Result of addition or subtraction 5.65 +wire [`LM32_WORD_RNG] adder_result_x; 5.66 +output adder_carry_n_x; // Inverted carry 5.67 +wire adder_carry_n_x; 5.68 +output adder_overflow_x; // Indicates if overflow occured, only valid for subtractions 5.69 +reg adder_overflow_x; 5.70 + 5.71 +///////////////////////////////////////////////////// 5.72 +// Internal nets and registers 5.73 +///////////////////////////////////////////////////// 5.74 + 5.75 +wire a_sign; // Sign (i.e. positive or negative) of operand 0 5.76 +wire b_sign; // Sign of operand 1 5.77 +wire result_sign; // Sign of result 5.78 + 5.79 +///////////////////////////////////////////////////// 5.80 +// Instantiations 5.81 +///////////////////////////////////////////////////// 5.82 + 5.83 +lm32_addsub addsub ( 5.84 + // ----- Inputs ----- 5.85 + .DataA (operand_0_x), 5.86 + .DataB (operand_1_x), 5.87 + .Cin (adder_op_x), 5.88 + .Add_Sub (adder_op_x_n), 5.89 + // ----- Ouputs ----- 5.90 + .Result (adder_result_x), 5.91 + .Cout (adder_carry_n_x) 5.92 + ); 5.93 + 5.94 +///////////////////////////////////////////////////// 5.95 +// Combinational Logic 5.96 +///////////////////////////////////////////////////// 5.97 + 5.98 +// Extract signs of operands and result 5.99 + 5.100 +assign a_sign = operand_0_x[`LM32_WORD_WIDTH-1]; 5.101 +assign b_sign = operand_1_x[`LM32_WORD_WIDTH-1]; 5.102 +assign result_sign = adder_result_x[`LM32_WORD_WIDTH-1]; 5.103 + 5.104 +// Determine whether an overflow occured when performing a subtraction 5.105 + 5.106 +always @(*) 5.107 +begin 5.108 + // +ve - -ve = -ve -> overflow 5.109 + // -ve - +ve = +ve -> overflow 5.110 + if ( (!a_sign & b_sign & result_sign) 5.111 + || (a_sign & !b_sign & !result_sign) 5.112 + ) 5.113 + adder_overflow_x = `TRUE; 5.114 + else 5.115 + adder_overflow_x = `FALSE; 5.116 +end 5.117 + 5.118 +endmodule 5.119 +
6.1 diff -r 000000000000 -r cd0b58aa6f83 lm32_addsub.v 6.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 6.3 +++ b/lm32_addsub.v Sun Apr 04 20:40:03 2010 +0100 6.4 @@ -0,0 +1,93 @@ 6.5 +// ============================================================================= 6.6 +// COPYRIGHT NOTICE 6.7 +// Copyright 2006 (c) Lattice Semiconductor Corporation 6.8 +// ALL RIGHTS RESERVED 6.9 +// This confidential and proprietary software may be used only as authorised by 6.10 +// a licensing agreement from Lattice Semiconductor Corporation. 6.11 +// The entire notice above must be reproduced on all authorized copies and 6.12 +// copies may only be made to the extent permitted by a licensing agreement from 6.13 +// Lattice Semiconductor Corporation. 6.14 +// 6.15 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 6.16 +// 5555 NE Moore Court 408-826-6000 (other locations) 6.17 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 6.18 +// U.S.A email: techsupport@latticesemi.com 6.19 +// =============================================================================/ 6.20 +// FILE DETAILS 6.21 +// Project : LatticeMico32 6.22 +// File : lm32_addsub.v 6.23 +// Title : PMI adder/subtractor. 6.24 +// Version : 6.1.17 6.25 +// : Initial Release 6.26 +// Version : 7.0SP2, 3.0 6.27 +// : No Change 6.28 +// Version : 3.1 6.29 +// : No Change 6.30 +// ============================================================================= 6.31 + 6.32 +`include "lm32_include.v" 6.33 + 6.34 +///////////////////////////////////////////////////// 6.35 +// Module interface 6.36 +///////////////////////////////////////////////////// 6.37 + 6.38 +module lm32_addsub ( 6.39 + // ----- Inputs ------- 6.40 + DataA, 6.41 + DataB, 6.42 + Cin, 6.43 + Add_Sub, 6.44 + // ----- Outputs ------- 6.45 + Result, 6.46 + Cout 6.47 + ); 6.48 + 6.49 +///////////////////////////////////////////////////// 6.50 +// Inputs 6.51 +///////////////////////////////////////////////////// 6.52 + 6.53 +input [31:0] DataA; 6.54 +input [31:0] DataB; 6.55 +input Cin; 6.56 +input Add_Sub; 6.57 + 6.58 +///////////////////////////////////////////////////// 6.59 +// Outputs 6.60 +///////////////////////////////////////////////////// 6.61 + 6.62 +output [31:0] Result; 6.63 +wire [31:0] Result; 6.64 +output Cout; 6.65 +wire Cout; 6.66 + 6.67 +///////////////////////////////////////////////////// 6.68 +// Instantiations 6.69 +///////////////////////////////////////////////////// 6.70 + 6.71 + generate 6.72 + if (`LATTICE_FAMILY == "SC" || `LATTICE_FAMILY == "SCM") begin 6.73 + wire [32:0] tmp_addResult = DataA + DataB + Cin; 6.74 + wire [32:0] tmp_subResult = DataA - DataB - !Cin; 6.75 + 6.76 + assign Result = (Add_Sub == 1) ? tmp_addResult[31:0] : tmp_subResult[31:0]; 6.77 + assign Cout = (Add_Sub == 1) ? tmp_addResult[32] : !tmp_subResult[32]; 6.78 + end else begin 6.79 + pmi_addsub #(// ----- Parameters ------- 6.80 + .pmi_data_width (32), 6.81 + .pmi_result_width (32), 6.82 + .pmi_sign ("off"), 6.83 + .pmi_family (`LATTICE_FAMILY), 6.84 + .module_type ("pmi_addsub")) 6.85 + addsub (// ----- Inputs ------- 6.86 + .DataA (DataA), 6.87 + .DataB (DataB), 6.88 + .Cin (Cin), 6.89 + .Add_Sub (Add_Sub), 6.90 + // ----- Outputs ------- 6.91 + .Result (Result), 6.92 + .Cout (Cout), 6.93 + .Overflow ()); 6.94 + end 6.95 + endgenerate 6.96 + 6.97 +endmodule
7.1 diff -r 000000000000 -r cd0b58aa6f83 lm32_cpu.v 7.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 7.3 +++ b/lm32_cpu.v Sun Apr 04 20:40:03 2010 +0100 7.4 @@ -0,0 +1,2732 @@ 7.5 +// ============================================================================= 7.6 +// COPYRIGHT NOTICE 7.7 +// Copyright 2006 (c) Lattice Semiconductor Corporation 7.8 +// ALL RIGHTS RESERVED 7.9 +// This confidential and proprietary software may be used only as authorised by 7.10 +// a licensing agreement from Lattice Semiconductor Corporation. 7.11 +// The entire notice above must be reproduced on all authorized copies and 7.12 +// copies may only be made to the extent permitted by a licensing agreement from 7.13 +// Lattice Semiconductor Corporation. 7.14 +// 7.15 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 7.16 +// 5555 NE Moore Court 408-826-6000 (other locations) 7.17 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 7.18 +// U.S.A email: techsupport@latticesemi.com 7.19 +// =============================================================================/ 7.20 +// FILE DETAILS 7.21 +// Project : LatticeMico32 7.22 +// File : lm32_cpu.v 7.23 +// Title : Top-level of CPU. 7.24 +// Dependencies : lm32_include.v 7.25 +// 7.26 +// Version 3.4 7.27 +// 1. Bug Fix: In a tight infinite loop (add, sw, bi) incoming interrupts were 7.28 +// never serviced. 7.29 +// 7.30 +// Version 3.3 7.31 +// 1. Feature: Support for memory that is tightly coupled to processor core, and 7.32 +// has a single-cycle access latency (same as caches). Instruction port has 7.33 +// access to a dedicated physically-mapped memory. Data port has access to 7.34 +// a dedicated physically-mapped memory. In order to be able to manipulate 7.35 +// values in both these memories via the debugger, these memories also 7.36 +// interface with the data port of LM32. 7.37 +// 2. Feature: Extended Configuration Register 7.38 +// 3. Bug Fix: Removed port names that conflict with keywords reserved in System- 7.39 +// Verilog. 7.40 +// 7.41 +// Version 3.2 7.42 +// 1. Bug Fix: Single-stepping a load/store to invalid address causes debugger to 7.43 +// hang. At the same time CPU fails to register data bus error exception. Bug 7.44 +// is caused because (a) data bus error exception occurs after load/store has 7.45 +// passed X stage and next sequential instruction (e.g., brk) is already in X 7.46 +// stage, and (b) data bus error exception had lower priority than, say, brk 7.47 +// exception. 7.48 +// 2. Bug Fix: If a brk (or scall/eret/bret) sequentially follows a load/store to 7.49 +// invalid location, CPU will fail to register data bus error exception. The 7.50 +// solution is to stall scall/eret/bret/brk instructions in D pipeline stage 7.51 +// until load/store has completed. 7.52 +// 3. Feature: Enable precise identification of load/store that causes seg fault. 7.53 +// 4. SYNC resets used for register file when implemented in EBRs. 7.54 +// 7.55 +// Version 3.1 7.56 +// 1. Feature: LM32 Register File can now be mapped in to on-chip block RAM (EBR) 7.57 +// instead of distributed memory by enabling the option in LM32 GUI. 7.58 +// 2. Feature: LM32 also adds a static branch predictor to improve branch 7.59 +// performance. All immediate-based forward-pointing branches are predicted 7.60 +// not-taken. All immediate-based backward-pointing branches are predicted taken. 7.61 +// 7.62 +// Version 7.0SP2, 3.0 7.63 +// No Change 7.64 +// 7.65 +// Version 6.1.17 7.66 +// Initial Release 7.67 +// ============================================================================= 7.68 + 7.69 +`include "lm32_include.v" 7.70 + 7.71 +///////////////////////////////////////////////////// 7.72 +// Module interface 7.73 +///////////////////////////////////////////////////// 7.74 + 7.75 +module lm32_cpu ( 7.76 + // ----- Inputs ------- 7.77 + clk_i, 7.78 +`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE 7.79 + clk_n_i, 7.80 +`endif 7.81 + rst_i, 7.82 + // From external devices 7.83 +`ifdef CFG_INTERRUPTS_ENABLED 7.84 + interrupt_n, 7.85 +`endif 7.86 + // From user logic 7.87 +`ifdef CFG_USER_ENABLED 7.88 + user_result, 7.89 + user_complete, 7.90 +`endif 7.91 +`ifdef CFG_JTAG_ENABLED 7.92 + // From JTAG 7.93 + jtag_clk, 7.94 + jtag_update, 7.95 + jtag_reg_q, 7.96 + jtag_reg_addr_q, 7.97 +`endif 7.98 +`ifdef CFG_IWB_ENABLED 7.99 + // Instruction Wishbone master 7.100 + I_DAT_I, 7.101 + I_ACK_I, 7.102 + I_ERR_I, 7.103 + I_RTY_I, 7.104 +`endif 7.105 + // Data Wishbone master 7.106 + D_DAT_I, 7.107 + D_ACK_I, 7.108 + D_ERR_I, 7.109 + D_RTY_I, 7.110 + // ----- Outputs ------- 7.111 +`ifdef CFG_TRACE_ENABLED 7.112 + trace_pc, 7.113 + trace_pc_valid, 7.114 + trace_exception, 7.115 + trace_eid, 7.116 + trace_eret, 7.117 +`ifdef CFG_DEBUG_ENABLED 7.118 + trace_bret, 7.119 +`endif 7.120 +`endif 7.121 +`ifdef CFG_JTAG_ENABLED 7.122 + jtag_reg_d, 7.123 + jtag_reg_addr_d, 7.124 +`endif 7.125 +`ifdef CFG_USER_ENABLED 7.126 + user_valid, 7.127 + user_opcode, 7.128 + user_operand_0, 7.129 + user_operand_1, 7.130 +`endif 7.131 +`ifdef CFG_IWB_ENABLED 7.132 + // Instruction Wishbone master 7.133 + I_DAT_O, 7.134 + I_ADR_O, 7.135 + I_CYC_O, 7.136 + I_SEL_O, 7.137 + I_STB_O, 7.138 + I_WE_O, 7.139 + I_CTI_O, 7.140 + I_LOCK_O, 7.141 + I_BTE_O, 7.142 +`endif 7.143 + // Data Wishbone master 7.144 + D_DAT_O, 7.145 + D_ADR_O, 7.146 + D_CYC_O, 7.147 + D_SEL_O, 7.148 + D_STB_O, 7.149 + D_WE_O, 7.150 + D_CTI_O, 7.151 + D_LOCK_O, 7.152 + D_BTE_O 7.153 + ); 7.154 + 7.155 +///////////////////////////////////////////////////// 7.156 +// Parameters 7.157 +///////////////////////////////////////////////////// 7.158 + 7.159 +parameter eba_reset = `CFG_EBA_RESET; // Reset value for EBA CSR 7.160 +`ifdef CFG_DEBUG_ENABLED 7.161 +parameter deba_reset = `CFG_DEBA_RESET; // Reset value for DEBA CSR 7.162 +`endif 7.163 + 7.164 +`ifdef CFG_ICACHE_ENABLED 7.165 +parameter icache_associativity = `CFG_ICACHE_ASSOCIATIVITY; // Associativity of the cache (Number of ways) 7.166 +parameter icache_sets = `CFG_ICACHE_SETS; // Number of sets 7.167 +parameter icache_bytes_per_line = `CFG_ICACHE_BYTES_PER_LINE; // Number of bytes per cache line 7.168 +parameter icache_base_address = `CFG_ICACHE_BASE_ADDRESS; // Base address of cachable memory 7.169 +parameter icache_limit = `CFG_ICACHE_LIMIT; // Limit (highest address) of cachable memory 7.170 +`else 7.171 +parameter icache_associativity = 1; 7.172 +parameter icache_sets = 512; 7.173 +parameter icache_bytes_per_line = 16; 7.174 +parameter icache_base_address = 0; 7.175 +parameter icache_limit = 0; 7.176 +`endif 7.177 + 7.178 +`ifdef CFG_DCACHE_ENABLED 7.179 +parameter dcache_associativity = `CFG_DCACHE_ASSOCIATIVITY; // Associativity of the cache (Number of ways) 7.180 +parameter dcache_sets = `CFG_DCACHE_SETS; // Number of sets 7.181 +parameter dcache_bytes_per_line = `CFG_DCACHE_BYTES_PER_LINE; // Number of bytes per cache line 7.182 +parameter dcache_base_address = `CFG_DCACHE_BASE_ADDRESS; // Base address of cachable memory 7.183 +parameter dcache_limit = `CFG_DCACHE_LIMIT; // Limit (highest address) of cachable memory 7.184 +`else 7.185 +parameter dcache_associativity = 1; 7.186 +parameter dcache_sets = 512; 7.187 +parameter dcache_bytes_per_line = 16; 7.188 +parameter dcache_base_address = 0; 7.189 +parameter dcache_limit = 0; 7.190 +`endif 7.191 + 7.192 +`ifdef CFG_DEBUG_ENABLED 7.193 +parameter watchpoints = `CFG_WATCHPOINTS; // Number of h/w watchpoint CSRs 7.194 +`else 7.195 +parameter watchpoints = 0; 7.196 +`endif 7.197 +`ifdef CFG_ROM_DEBUG_ENABLED 7.198 +parameter breakpoints = `CFG_BREAKPOINTS; // Number of h/w breakpoint CSRs 7.199 +`else 7.200 +parameter breakpoints = 0; 7.201 +`endif 7.202 + 7.203 +`ifdef CFG_INTERRUPTS_ENABLED 7.204 +parameter interrupts = `CFG_INTERRUPTS; // Number of interrupts 7.205 +`else 7.206 +parameter interrupts = 0; 7.207 +`endif 7.208 + 7.209 +///////////////////////////////////////////////////// 7.210 +// Inputs 7.211 +///////////////////////////////////////////////////// 7.212 + 7.213 +input clk_i; // Clock 7.214 +`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE 7.215 +input clk_n_i; // Inverted clock 7.216 +`endif 7.217 +input rst_i; // Reset 7.218 + 7.219 +`ifdef CFG_INTERRUPTS_ENABLED 7.220 +input [`LM32_INTERRUPT_RNG] interrupt_n; // Interrupt pins, active-low 7.221 +`endif 7.222 + 7.223 +`ifdef CFG_USER_ENABLED 7.224 +input [`LM32_WORD_RNG] user_result; // User-defined instruction result 7.225 +input user_complete; // User-defined instruction execution is complete 7.226 +`endif 7.227 + 7.228 +`ifdef CFG_JTAG_ENABLED 7.229 +input jtag_clk; // JTAG clock 7.230 +input jtag_update; // JTAG state machine is in data register update state 7.231 +input [`LM32_BYTE_RNG] jtag_reg_q; 7.232 +input [2:0] jtag_reg_addr_q; 7.233 +`endif 7.234 + 7.235 +`ifdef CFG_IWB_ENABLED 7.236 +input [`LM32_WORD_RNG] I_DAT_I; // Instruction Wishbone interface read data 7.237 +input I_ACK_I; // Instruction Wishbone interface acknowledgement 7.238 +input I_ERR_I; // Instruction Wishbone interface error 7.239 +input I_RTY_I; // Instruction Wishbone interface retry 7.240 +`endif 7.241 + 7.242 +input [`LM32_WORD_RNG] D_DAT_I; // Data Wishbone interface read data 7.243 +input D_ACK_I; // Data Wishbone interface acknowledgement 7.244 +input D_ERR_I; // Data Wishbone interface error 7.245 +input D_RTY_I; // Data Wishbone interface retry 7.246 + 7.247 +///////////////////////////////////////////////////// 7.248 +// Outputs 7.249 +///////////////////////////////////////////////////// 7.250 + 7.251 +`ifdef CFG_TRACE_ENABLED 7.252 +output [`LM32_PC_RNG] trace_pc; // PC to trace 7.253 +reg [`LM32_PC_RNG] trace_pc; 7.254 +output trace_pc_valid; // Indicates that a new trace PC is valid 7.255 +reg trace_pc_valid; 7.256 +output trace_exception; // Indicates an exception has occured 7.257 +reg trace_exception; 7.258 +output [`LM32_EID_RNG] trace_eid; // Indicates what type of exception has occured 7.259 +reg [`LM32_EID_RNG] trace_eid; 7.260 +output trace_eret; // Indicates an eret instruction has been executed 7.261 +reg trace_eret; 7.262 +`ifdef CFG_DEBUG_ENABLED 7.263 +output trace_bret; // Indicates a bret instruction has been executed 7.264 +reg trace_bret; 7.265 +`endif 7.266 +`endif 7.267 + 7.268 +`ifdef CFG_JTAG_ENABLED 7.269 +output [`LM32_BYTE_RNG] jtag_reg_d; 7.270 +wire [`LM32_BYTE_RNG] jtag_reg_d; 7.271 +output [2:0] jtag_reg_addr_d; 7.272 +wire [2:0] jtag_reg_addr_d; 7.273 +`endif 7.274 + 7.275 +`ifdef CFG_USER_ENABLED 7.276 +output user_valid; // Indicates if user_opcode is valid 7.277 +wire user_valid; 7.278 +output [`LM32_USER_OPCODE_RNG] user_opcode; // User-defined instruction opcode 7.279 +reg [`LM32_USER_OPCODE_RNG] user_opcode; 7.280 +output [`LM32_WORD_RNG] user_operand_0; // First operand for user-defined instruction 7.281 +wire [`LM32_WORD_RNG] user_operand_0; 7.282 +output [`LM32_WORD_RNG] user_operand_1; // Second operand for user-defined instruction 7.283 +wire [`LM32_WORD_RNG] user_operand_1; 7.284 +`endif 7.285 + 7.286 +`ifdef CFG_IWB_ENABLED 7.287 +output [`LM32_WORD_RNG] I_DAT_O; // Instruction Wishbone interface write data 7.288 +wire [`LM32_WORD_RNG] I_DAT_O; 7.289 +output [`LM32_WORD_RNG] I_ADR_O; // Instruction Wishbone interface address 7.290 +wire [`LM32_WORD_RNG] I_ADR_O; 7.291 +output I_CYC_O; // Instruction Wishbone interface cycle 7.292 +wire I_CYC_O; 7.293 +output [`LM32_BYTE_SELECT_RNG] I_SEL_O; // Instruction Wishbone interface byte select 7.294 +wire [`LM32_BYTE_SELECT_RNG] I_SEL_O; 7.295 +output I_STB_O; // Instruction Wishbone interface strobe 7.296 +wire I_STB_O; 7.297 +output I_WE_O; // Instruction Wishbone interface write enable 7.298 +wire I_WE_O; 7.299 +output [`LM32_CTYPE_RNG] I_CTI_O; // Instruction Wishbone interface cycle type 7.300 +wire [`LM32_CTYPE_RNG] I_CTI_O; 7.301 +output I_LOCK_O; // Instruction Wishbone interface lock bus 7.302 +wire I_LOCK_O; 7.303 +output [`LM32_BTYPE_RNG] I_BTE_O; // Instruction Wishbone interface burst type 7.304 +wire [`LM32_BTYPE_RNG] I_BTE_O; 7.305 +`endif 7.306 + 7.307 +output [`LM32_WORD_RNG] D_DAT_O; // Data Wishbone interface write data 7.308 +wire [`LM32_WORD_RNG] D_DAT_O; 7.309 +output [`LM32_WORD_RNG] D_ADR_O; // Data Wishbone interface address 7.310 +wire [`LM32_WORD_RNG] D_ADR_O; 7.311 +output D_CYC_O; // Data Wishbone interface cycle 7.312 +wire D_CYC_O; 7.313 +output [`LM32_BYTE_SELECT_RNG] D_SEL_O; // Data Wishbone interface byte select 7.314 +wire [`LM32_BYTE_SELECT_RNG] D_SEL_O; 7.315 +output D_STB_O; // Data Wishbone interface strobe 7.316 +wire D_STB_O; 7.317 +output D_WE_O; // Data Wishbone interface write enable 7.318 +wire D_WE_O; 7.319 +output [`LM32_CTYPE_RNG] D_CTI_O; // Data Wishbone interface cycle type 7.320 +wire [`LM32_CTYPE_RNG] D_CTI_O; 7.321 +output D_LOCK_O; // Date Wishbone interface lock bus 7.322 +wire D_LOCK_O; 7.323 +output [`LM32_BTYPE_RNG] D_BTE_O; // Data Wishbone interface burst type 7.324 +wire [`LM32_BTYPE_RNG] D_BTE_O; 7.325 + 7.326 +///////////////////////////////////////////////////// 7.327 +// Internal nets and registers 7.328 +///////////////////////////////////////////////////// 7.329 + 7.330 +// Pipeline registers 7.331 + 7.332 +`ifdef LM32_CACHE_ENABLED 7.333 +reg valid_a; // Instruction in A stage is valid 7.334 +`endif 7.335 +reg valid_f; // Instruction in F stage is valid 7.336 +reg valid_d; // Instruction in D stage is valid 7.337 +reg valid_x; // Instruction in X stage is valid 7.338 +reg valid_m; // Instruction in M stage is valid 7.339 +reg valid_w; // Instruction in W stage is valid 7.340 + 7.341 +wire q_x; 7.342 +wire [`LM32_WORD_RNG] immediate_d; // Immediate operand 7.343 +wire load_d; // Indicates a load instruction 7.344 +reg load_x; 7.345 +reg load_m; 7.346 +wire load_q_x; 7.347 +wire store_q_x; 7.348 +wire store_d; // Indicates a store instruction 7.349 +reg store_x; 7.350 +reg store_m; 7.351 +wire [`LM32_SIZE_RNG] size_d; // Size of load/store (byte, hword, word) 7.352 +reg [`LM32_SIZE_RNG] size_x; 7.353 +wire branch_d; // Indicates a branch instruction 7.354 +wire branch_predict_d; // Indicates a branch is predicted 7.355 +wire branch_predict_taken_d; // Indicates a branch is predicted taken 7.356 +wire [`LM32_PC_RNG] branch_predict_address_d; // Address to which predicted branch jumps 7.357 +wire [`LM32_PC_RNG] branch_target_d; 7.358 +wire bi_unconditional; 7.359 +wire bi_conditional; 7.360 +reg branch_x; 7.361 +reg branch_predict_x; 7.362 +reg branch_predict_taken_x; 7.363 +reg branch_m; 7.364 +reg branch_predict_m; 7.365 +reg branch_predict_taken_m; 7.366 +wire branch_mispredict_taken_m; // Indicates a branch was mispredicted as taken 7.367 +wire branch_flushX_m; // Indicates that instruction in X stage must be squashed 7.368 +wire branch_reg_d; // Branch to register or immediate 7.369 +wire [`LM32_PC_RNG] branch_offset_d; // Branch offset for immediate branches 7.370 +reg [`LM32_PC_RNG] branch_target_x; // Address to branch to 7.371 +reg [`LM32_PC_RNG] branch_target_m; 7.372 +wire [`LM32_D_RESULT_SEL_0_RNG] d_result_sel_0_d; // Which result should be selected in D stage for operand 0 7.373 +wire [`LM32_D_RESULT_SEL_1_RNG] d_result_sel_1_d; // Which result should be selected in D stage for operand 1 7.374 + 7.375 +wire x_result_sel_csr_d; // Select X stage result from CSRs 7.376 +reg x_result_sel_csr_x; 7.377 +`ifdef LM32_MC_ARITHMETIC_ENABLED 7.378 +wire x_result_sel_mc_arith_d; // Select X stage result from multi-cycle arithmetic unit 7.379 +reg x_result_sel_mc_arith_x; 7.380 +`endif 7.381 +`ifdef LM32_NO_BARREL_SHIFT 7.382 +wire x_result_sel_shift_d; // Select X stage result from shifter 7.383 +reg x_result_sel_shift_x; 7.384 +`endif 7.385 +`ifdef CFG_SIGN_EXTEND_ENABLED 7.386 +wire x_result_sel_sext_d; // Select X stage result from sign-extend logic 7.387 +reg x_result_sel_sext_x; 7.388 +`endif 7.389 +wire x_result_sel_logic_d; // Select X stage result from logic op unit 7.390 +reg x_result_sel_logic_x; 7.391 +`ifdef CFG_USER_ENABLED 7.392 +wire x_result_sel_user_d; // Select X stage result from user-defined logic 7.393 +reg x_result_sel_user_x; 7.394 +`endif 7.395 +wire x_result_sel_add_d; // Select X stage result from adder 7.396 +reg x_result_sel_add_x; 7.397 +wire m_result_sel_compare_d; // Select M stage result from comparison logic 7.398 +reg m_result_sel_compare_x; 7.399 +reg m_result_sel_compare_m; 7.400 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 7.401 +wire m_result_sel_shift_d; // Select M stage result from shifter 7.402 +reg m_result_sel_shift_x; 7.403 +reg m_result_sel_shift_m; 7.404 +`endif 7.405 +wire w_result_sel_load_d; // Select W stage result from load/store unit 7.406 +reg w_result_sel_load_x; 7.407 +reg w_result_sel_load_m; 7.408 +reg w_result_sel_load_w; 7.409 +`ifdef CFG_PL_MULTIPLY_ENABLED 7.410 +wire w_result_sel_mul_d; // Select W stage result from multiplier 7.411 +reg w_result_sel_mul_x; 7.412 +reg w_result_sel_mul_m; 7.413 +reg w_result_sel_mul_w; 7.414 +`endif 7.415 +wire x_bypass_enable_d; // Whether result is bypassable in X stage 7.416 +reg x_bypass_enable_x; 7.417 +wire m_bypass_enable_d; // Whether result is bypassable in M stage 7.418 +reg m_bypass_enable_x; 7.419 +reg m_bypass_enable_m; 7.420 +wire sign_extend_d; // Whether to sign-extend or zero-extend 7.421 +reg sign_extend_x; 7.422 +wire write_enable_d; // Register file write enable 7.423 +reg write_enable_x; 7.424 +wire write_enable_q_x; 7.425 +reg write_enable_m; 7.426 +wire write_enable_q_m; 7.427 +reg write_enable_w; 7.428 +wire write_enable_q_w; 7.429 +wire read_enable_0_d; // Register file read enable 0 7.430 +wire [`LM32_REG_IDX_RNG] read_idx_0_d; // Register file read index 0 7.431 +wire read_enable_1_d; // Register file read enable 1 7.432 +wire [`LM32_REG_IDX_RNG] read_idx_1_d; // Register file read index 1 7.433 +wire [`LM32_REG_IDX_RNG] write_idx_d; // Register file write index 7.434 +reg [`LM32_REG_IDX_RNG] write_idx_x; 7.435 +reg [`LM32_REG_IDX_RNG] write_idx_m; 7.436 +reg [`LM32_REG_IDX_RNG] write_idx_w; 7.437 +wire [`LM32_CSR_RNG] csr_d; // CSR read/write index 7.438 +reg [`LM32_CSR_RNG] csr_x; 7.439 +wire [`LM32_CONDITION_RNG] condition_d; // Branch condition 7.440 +reg [`LM32_CONDITION_RNG] condition_x; 7.441 +`ifdef CFG_DEBUG_ENABLED 7.442 +wire break_d; // Indicates a break instruction 7.443 +reg break_x; 7.444 +`endif 7.445 +wire scall_d; // Indicates a scall instruction 7.446 +reg scall_x; 7.447 +wire eret_d; // Indicates an eret instruction 7.448 +reg eret_x; 7.449 +wire eret_q_x; 7.450 +reg eret_m; 7.451 +`ifdef CFG_TRACE_ENABLED 7.452 +reg eret_w; 7.453 +`endif 7.454 +`ifdef CFG_DEBUG_ENABLED 7.455 +wire bret_d; // Indicates a bret instruction 7.456 +reg bret_x; 7.457 +wire bret_q_x; 7.458 +reg bret_m; 7.459 +`ifdef CFG_TRACE_ENABLED 7.460 +reg bret_w; 7.461 +`endif 7.462 +`endif 7.463 +wire csr_write_enable_d; // CSR write enable 7.464 +reg csr_write_enable_x; 7.465 +wire csr_write_enable_q_x; 7.466 +`ifdef CFG_USER_ENABLED 7.467 +wire [`LM32_USER_OPCODE_RNG] user_opcode_d; // User-defined instruction opcode 7.468 +`endif 7.469 + 7.470 +`ifdef CFG_BUS_ERRORS_ENABLED 7.471 +wire bus_error_d; // Indicates an bus error occured while fetching the instruction in this pipeline stage 7.472 +reg bus_error_x; 7.473 +reg data_bus_error_exception_m; 7.474 +reg [`LM32_PC_RNG] memop_pc_w; 7.475 +`endif 7.476 + 7.477 +reg [`LM32_WORD_RNG] d_result_0; // Result of instruction in D stage (operand 0) 7.478 +reg [`LM32_WORD_RNG] d_result_1; // Result of instruction in D stage (operand 1) 7.479 +reg [`LM32_WORD_RNG] x_result; // Result of instruction in X stage 7.480 +reg [`LM32_WORD_RNG] m_result; // Result of instruction in M stage 7.481 +reg [`LM32_WORD_RNG] w_result; // Result of instruction in W stage 7.482 + 7.483 +reg [`LM32_WORD_RNG] operand_0_x; // Operand 0 for X stage instruction 7.484 +reg [`LM32_WORD_RNG] operand_1_x; // Operand 1 for X stage instruction 7.485 +reg [`LM32_WORD_RNG] store_operand_x; // Data read from register to store 7.486 +reg [`LM32_WORD_RNG] operand_m; // Operand for M stage instruction 7.487 +reg [`LM32_WORD_RNG] operand_w; // Operand for W stage instruction 7.488 + 7.489 +// To/from register file 7.490 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE 7.491 +reg [`LM32_WORD_RNG] reg_data_live_0; 7.492 +reg [`LM32_WORD_RNG] reg_data_live_1; 7.493 +reg use_buf; // Whether to use reg_data_live or reg_data_buf 7.494 +reg [`LM32_WORD_RNG] reg_data_buf_0; 7.495 +reg [`LM32_WORD_RNG] reg_data_buf_1; 7.496 +`endif 7.497 +`ifdef LM32_EBR_REGISTER_FILE 7.498 +`else 7.499 +reg [`LM32_WORD_RNG] registers[0:(1<<`LM32_REG_IDX_WIDTH)-1]; // Register file 7.500 +`endif 7.501 +wire [`LM32_WORD_RNG] reg_data_0; // Register file read port 0 data 7.502 +wire [`LM32_WORD_RNG] reg_data_1; // Register file read port 1 data 7.503 +reg [`LM32_WORD_RNG] bypass_data_0; // Register value 0 after bypassing 7.504 +reg [`LM32_WORD_RNG] bypass_data_1; // Register value 1 after bypassing 7.505 +wire reg_write_enable_q_w; 7.506 + 7.507 +reg interlock; // Indicates pipeline should be stalled because of a read-after-write hazzard 7.508 + 7.509 +wire stall_a; // Stall instruction in A pipeline stage 7.510 +wire stall_f; // Stall instruction in F pipeline stage 7.511 +wire stall_d; // Stall instruction in D pipeline stage 7.512 +wire stall_x; // Stall instruction in X pipeline stage 7.513 +wire stall_m; // Stall instruction in M pipeline stage 7.514 + 7.515 +// To/from adder 7.516 +wire adder_op_d; // Whether to add or subtract 7.517 +reg adder_op_x; 7.518 +reg adder_op_x_n; // Inverted version of adder_op_x 7.519 +wire [`LM32_WORD_RNG] adder_result_x; // Result from adder 7.520 +wire adder_overflow_x; // Whether a signed overflow occured 7.521 +wire adder_carry_n_x; // Whether a carry was generated 7.522 + 7.523 +// To/from logical operations unit 7.524 +wire [`LM32_LOGIC_OP_RNG] logic_op_d; // Which operation to perform 7.525 +reg [`LM32_LOGIC_OP_RNG] logic_op_x; 7.526 +wire [`LM32_WORD_RNG] logic_result_x; // Result of logical operation 7.527 + 7.528 +`ifdef CFG_SIGN_EXTEND_ENABLED 7.529 +// From sign-extension unit 7.530 +wire [`LM32_WORD_RNG] sextb_result_x; // Result of byte sign-extension 7.531 +wire [`LM32_WORD_RNG] sexth_result_x; // Result of half-word sign-extenstion 7.532 +wire [`LM32_WORD_RNG] sext_result_x; // Result of sign-extension specified by instruction 7.533 +`endif 7.534 + 7.535 +// To/from shifter 7.536 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 7.537 +`ifdef CFG_ROTATE_ENABLED 7.538 +wire rotate_d; // Whether we should rotate or shift 7.539 +reg rotate_x; 7.540 +`endif 7.541 +wire direction_d; // Which direction to shift in 7.542 +reg direction_x; 7.543 +reg direction_m; 7.544 +wire [`LM32_WORD_RNG] shifter_result_m; // Result of shifter 7.545 +`endif 7.546 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED 7.547 +wire shift_left_d; // Indicates whether to perform a left shift or not 7.548 +wire shift_left_q_d; 7.549 +wire shift_right_d; // Indicates whether to perform a right shift or not 7.550 +wire shift_right_q_d; 7.551 +`endif 7.552 +`ifdef LM32_NO_BARREL_SHIFT 7.553 +wire [`LM32_WORD_RNG] shifter_result_x; // Result of single-bit right shifter 7.554 +`endif 7.555 + 7.556 +// To/from multiplier 7.557 +`ifdef LM32_MULTIPLY_ENABLED 7.558 +wire [`LM32_WORD_RNG] multiplier_result_w; // Result from multiplier 7.559 +`endif 7.560 +`ifdef CFG_MC_MULTIPLY_ENABLED 7.561 +wire multiply_d; // Indicates whether to perform a multiply or not 7.562 +wire multiply_q_d; 7.563 +`endif 7.564 + 7.565 +// To/from divider 7.566 +`ifdef CFG_MC_DIVIDE_ENABLED 7.567 +wire divide_d; // Indicates whether to perform a divider or not 7.568 +wire divide_q_d; 7.569 +wire modulus_d; 7.570 +wire modulus_q_d; 7.571 +wire divide_by_zero_x; // Indicates an attempt was made to divide by zero 7.572 +`endif 7.573 + 7.574 +// To from multi-cycle arithmetic unit 7.575 +`ifdef LM32_MC_ARITHMETIC_ENABLED 7.576 +wire mc_stall_request_x; // Multi-cycle arithmetic unit stall request 7.577 +wire [`LM32_WORD_RNG] mc_result_x; 7.578 +`endif 7.579 + 7.580 +// From CSRs 7.581 +`ifdef CFG_INTERRUPTS_ENABLED 7.582 +wire [`LM32_WORD_RNG] interrupt_csr_read_data_x;// Data read from interrupt CSRs 7.583 +`endif 7.584 +wire [`LM32_WORD_RNG] cfg; // Configuration CSR 7.585 +wire [`LM32_WORD_RNG] cfg2; // Extended Configuration CSR 7.586 +`ifdef CFG_CYCLE_COUNTER_ENABLED 7.587 +reg [`LM32_WORD_RNG] cc; // Cycle counter CSR 7.588 +`endif 7.589 +reg [`LM32_WORD_RNG] csr_read_data_x; // Data read from CSRs 7.590 + 7.591 +// To/from instruction unit 7.592 +wire [`LM32_PC_RNG] pc_f; // PC of instruction in F stage 7.593 +wire [`LM32_PC_RNG] pc_d; // PC of instruction in D stage 7.594 +wire [`LM32_PC_RNG] pc_x; // PC of instruction in X stage 7.595 +wire [`LM32_PC_RNG] pc_m; // PC of instruction in M stage 7.596 +wire [`LM32_PC_RNG] pc_w; // PC of instruction in W stage 7.597 +`ifdef CFG_TRACE_ENABLED 7.598 +reg [`LM32_PC_RNG] pc_c; // PC of last commited instruction 7.599 +`endif 7.600 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE 7.601 +wire [`LM32_INSTRUCTION_RNG] instruction_f; // Instruction in F stage 7.602 +`endif 7.603 +//pragma attribute instruction_d preserve_signal true 7.604 +//pragma attribute instruction_d preserve_driver true 7.605 +wire [`LM32_INSTRUCTION_RNG] instruction_d; // Instruction in D stage 7.606 +`ifdef CFG_ICACHE_ENABLED 7.607 +wire iflush; // Flush instruction cache 7.608 +wire icache_stall_request; // Stall pipeline because instruction cache is busy 7.609 +wire icache_restart_request; // Restart instruction that caused an instruction cache miss 7.610 +wire icache_refill_request; // Request to refill instruction cache 7.611 +wire icache_refilling; // Indicates the instruction cache is being refilled 7.612 +`endif 7.613 +`ifdef CFG_IROM_ENABLED 7.614 +wire [`LM32_WORD_RNG] irom_store_data_m; // Store data to instruction ROM 7.615 +wire [`LM32_WORD_RNG] irom_address_xm; // Address to instruction ROM from load-store unit 7.616 +wire [`LM32_WORD_RNG] irom_data_m; // Load data from instruction ROM 7.617 +wire irom_we_xm; // Indicates data needs to be written to instruction ROM 7.618 +wire irom_stall_request_x; // Indicates D stage needs to be stalled on a store to instruction ROM 7.619 +`endif 7.620 + 7.621 +// To/from load/store unit 7.622 +`ifdef CFG_DCACHE_ENABLED 7.623 +wire dflush_x; // Flush data cache 7.624 +reg dflush_m; 7.625 +wire dcache_stall_request; // Stall pipeline because data cache is busy 7.626 +wire dcache_restart_request; // Restart instruction that caused a data cache miss 7.627 +wire dcache_refill_request; // Request to refill data cache 7.628 +wire dcache_refilling; // Indicates the data cache is being refilled 7.629 +`endif 7.630 +wire [`LM32_WORD_RNG] load_data_w; // Result of a load instruction 7.631 +wire stall_wb_load; // Stall pipeline because of a load via the data Wishbone interface 7.632 + 7.633 +// To/from JTAG interface 7.634 +`ifdef CFG_JTAG_ENABLED 7.635 +`ifdef CFG_JTAG_UART_ENABLED 7.636 +wire [`LM32_WORD_RNG] jtx_csr_read_data; // Read data for JTX CSR 7.637 +wire [`LM32_WORD_RNG] jrx_csr_read_data; // Read data for JRX CSR 7.638 +`endif 7.639 +`ifdef CFG_HW_DEBUG_ENABLED 7.640 +wire jtag_csr_write_enable; // Debugger CSR write enable 7.641 +wire [`LM32_WORD_RNG] jtag_csr_write_data; // Data to write to specified CSR 7.642 +wire [`LM32_CSR_RNG] jtag_csr; // Which CSR to write 7.643 +wire jtag_read_enable; 7.644 +wire [`LM32_BYTE_RNG] jtag_read_data; 7.645 +wire jtag_write_enable; 7.646 +wire [`LM32_BYTE_RNG] jtag_write_data; 7.647 +wire [`LM32_WORD_RNG] jtag_address; 7.648 +wire jtag_access_complete; 7.649 +`endif 7.650 +`ifdef CFG_DEBUG_ENABLED 7.651 +wire jtag_break; // Request from debugger to raise a breakpoint 7.652 +`endif 7.653 +`endif 7.654 + 7.655 +// Hazzard detection 7.656 +wire raw_x_0; // RAW hazzard between instruction in X stage and read port 0 7.657 +wire raw_x_1; // RAW hazzard between instruction in X stage and read port 1 7.658 +wire raw_m_0; // RAW hazzard between instruction in M stage and read port 0 7.659 +wire raw_m_1; // RAW hazzard between instruction in M stage and read port 1 7.660 +wire raw_w_0; // RAW hazzard between instruction in W stage and read port 0 7.661 +wire raw_w_1; // RAW hazzard between instruction in W stage and read port 1 7.662 + 7.663 +// Control flow 7.664 +wire cmp_zero; // Result of comparison is zero 7.665 +wire cmp_negative; // Result of comparison is negative 7.666 +wire cmp_overflow; // Comparison produced an overflow 7.667 +wire cmp_carry_n; // Comparison produced a carry, inverted 7.668 +reg condition_met_x; // Condition of branch instruction is met 7.669 +reg condition_met_m; 7.670 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH 7.671 +wire branch_taken_x; // Branch is taken in X stage 7.672 +`endif 7.673 +wire branch_taken_m; // Branch is taken in M stage 7.674 + 7.675 +wire kill_f; // Kill instruction in F stage 7.676 +wire kill_d; // Kill instruction in D stage 7.677 +wire kill_x; // Kill instruction in X stage 7.678 +wire kill_m; // Kill instruction in M stage 7.679 +wire kill_w; // Kill instruction in W stage 7.680 + 7.681 +reg [`LM32_PC_WIDTH+2-1:8] eba; // Exception Base Address (EBA) CSR 7.682 +`ifdef CFG_DEBUG_ENABLED 7.683 +reg [`LM32_PC_WIDTH+2-1:8] deba; // Debug Exception Base Address (DEBA) CSR 7.684 +`endif 7.685 +reg [`LM32_EID_RNG] eid_x; // Exception ID in X stage 7.686 +`ifdef CFG_TRACE_ENABLED 7.687 +reg [`LM32_EID_RNG] eid_m; // Exception ID in M stage 7.688 +reg [`LM32_EID_RNG] eid_w; // Exception ID in W stage 7.689 +`endif 7.690 + 7.691 +`ifdef CFG_DEBUG_ENABLED 7.692 +`ifdef LM32_SINGLE_STEP_ENABLED 7.693 +wire dc_ss; // Is single-step enabled 7.694 +`endif 7.695 +wire dc_re; // Remap all exceptions 7.696 +wire exception_x; // An exception occured in the X stage 7.697 +reg exception_m; // An instruction that caused an exception is in the M stage 7.698 +wire debug_exception_x; // Indicates if a debug exception has occured 7.699 +reg debug_exception_m; 7.700 +reg debug_exception_w; 7.701 +wire debug_exception_q_w; 7.702 +wire non_debug_exception_x; // Indicates if a non debug exception has occured 7.703 +reg non_debug_exception_m; 7.704 +reg non_debug_exception_w; 7.705 +wire non_debug_exception_q_w; 7.706 +`else 7.707 +wire exception_x; // Indicates if a debug exception has occured 7.708 +reg exception_m; 7.709 +reg exception_w; 7.710 +wire exception_q_w; 7.711 +`endif 7.712 + 7.713 +`ifdef CFG_DEBUG_ENABLED 7.714 +`ifdef CFG_JTAG_ENABLED 7.715 +wire reset_exception; // Indicates if a reset exception has occured 7.716 +`endif 7.717 +`endif 7.718 +`ifdef CFG_INTERRUPTS_ENABLED 7.719 +wire interrupt_exception; // Indicates if an interrupt exception has occured 7.720 +`endif 7.721 +`ifdef CFG_DEBUG_ENABLED 7.722 +wire breakpoint_exception; // Indicates if a breakpoint exception has occured 7.723 +wire watchpoint_exception; // Indicates if a watchpoint exception has occured 7.724 +`endif 7.725 +`ifdef CFG_BUS_ERRORS_ENABLED 7.726 +wire instruction_bus_error_exception; // Indicates if an instruction bus error exception has occured 7.727 +wire data_bus_error_exception; // Indicates if a data bus error exception has occured 7.728 +`endif 7.729 +`ifdef CFG_MC_DIVIDE_ENABLED 7.730 +wire divide_by_zero_exception; // Indicates if a divide by zero exception has occured 7.731 +`endif 7.732 +wire system_call_exception; // Indicates if a system call exception has occured 7.733 + 7.734 +`ifdef CFG_BUS_ERRORS_ENABLED 7.735 +reg data_bus_error_seen; // Indicates if a data bus error was seen 7.736 +`endif 7.737 + 7.738 +///////////////////////////////////////////////////// 7.739 +// Functions 7.740 +///////////////////////////////////////////////////// 7.741 + 7.742 +`include "lm32_functions.v" 7.743 + 7.744 +///////////////////////////////////////////////////// 7.745 +// Instantiations 7.746 +///////////////////////////////////////////////////// 7.747 + 7.748 +// Instruction unit 7.749 +lm32_instruction_unit #( 7.750 + .associativity (icache_associativity), 7.751 + .sets (icache_sets), 7.752 + .bytes_per_line (icache_bytes_per_line), 7.753 + .base_address (icache_base_address), 7.754 + .limit (icache_limit) 7.755 + ) instruction_unit ( 7.756 + // ----- Inputs ------- 7.757 + .clk_i (clk_i), 7.758 + .rst_i (rst_i), 7.759 + // From pipeline 7.760 + .stall_a (stall_a), 7.761 + .stall_f (stall_f), 7.762 + .stall_d (stall_d), 7.763 + .stall_x (stall_x), 7.764 + .stall_m (stall_m), 7.765 + .valid_f (valid_f), 7.766 + .valid_d (valid_d), 7.767 + .kill_f (kill_f), 7.768 + .branch_predict_taken_d (branch_predict_taken_d), 7.769 + .branch_predict_address_d (branch_predict_address_d), 7.770 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH 7.771 + .branch_taken_x (branch_taken_x), 7.772 + .branch_target_x (branch_target_x), 7.773 +`endif 7.774 + .exception_m (exception_m), 7.775 + .branch_taken_m (branch_taken_m), 7.776 + .branch_mispredict_taken_m (branch_mispredict_taken_m), 7.777 + .branch_target_m (branch_target_m), 7.778 +`ifdef CFG_ICACHE_ENABLED 7.779 + .iflush (iflush), 7.780 +`endif 7.781 +`ifdef CFG_IROM_ENABLED 7.782 + .irom_store_data_m (irom_store_data_m), 7.783 + .irom_address_xm (irom_address_xm), 7.784 + .irom_we_xm (irom_we_xm), 7.785 +`endif 7.786 +`ifdef CFG_DCACHE_ENABLED 7.787 + .dcache_restart_request (dcache_restart_request), 7.788 + .dcache_refill_request (dcache_refill_request), 7.789 + .dcache_refilling (dcache_refilling), 7.790 +`endif 7.791 +`ifdef CFG_IWB_ENABLED 7.792 + // From Wishbone 7.793 + .i_dat_i (I_DAT_I), 7.794 + .i_ack_i (I_ACK_I), 7.795 + .i_err_i (I_ERR_I), 7.796 + .i_rty_i (I_RTY_I), 7.797 +`endif 7.798 +`ifdef CFG_HW_DEBUG_ENABLED 7.799 + .jtag_read_enable (jtag_read_enable), 7.800 + .jtag_write_enable (jtag_write_enable), 7.801 + .jtag_write_data (jtag_write_data), 7.802 + .jtag_address (jtag_address), 7.803 +`endif 7.804 + // ----- Outputs ------- 7.805 + // To pipeline 7.806 + .pc_f (pc_f), 7.807 + .pc_d (pc_d), 7.808 + .pc_x (pc_x), 7.809 + .pc_m (pc_m), 7.810 + .pc_w (pc_w), 7.811 +`ifdef CFG_ICACHE_ENABLED 7.812 + .icache_stall_request (icache_stall_request), 7.813 + .icache_restart_request (icache_restart_request), 7.814 + .icache_refill_request (icache_refill_request), 7.815 + .icache_refilling (icache_refilling), 7.816 +`endif 7.817 +`ifdef CFG_IROM_ENABLED 7.818 + .irom_data_m (irom_data_m), 7.819 +`endif 7.820 +`ifdef CFG_IWB_ENABLED 7.821 + // To Wishbone 7.822 + .i_dat_o (I_DAT_O), 7.823 + .i_adr_o (I_ADR_O), 7.824 + .i_cyc_o (I_CYC_O), 7.825 + .i_sel_o (I_SEL_O), 7.826 + .i_stb_o (I_STB_O), 7.827 + .i_we_o (I_WE_O), 7.828 + .i_cti_o (I_CTI_O), 7.829 + .i_lock_o (I_LOCK_O), 7.830 + .i_bte_o (I_BTE_O), 7.831 +`endif 7.832 +`ifdef CFG_HW_DEBUG_ENABLED 7.833 + .jtag_read_data (jtag_read_data), 7.834 + .jtag_access_complete (jtag_access_complete), 7.835 +`endif 7.836 +`ifdef CFG_BUS_ERRORS_ENABLED 7.837 + .bus_error_d (bus_error_d), 7.838 +`endif 7.839 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE 7.840 + .instruction_f (instruction_f), 7.841 +`endif 7.842 + .instruction_d (instruction_d) 7.843 + ); 7.844 + 7.845 +// Instruction decoder 7.846 +lm32_decoder decoder ( 7.847 + // ----- Inputs ------- 7.848 + .instruction (instruction_d), 7.849 + // ----- Outputs ------- 7.850 + .d_result_sel_0 (d_result_sel_0_d), 7.851 + .d_result_sel_1 (d_result_sel_1_d), 7.852 + .x_result_sel_csr (x_result_sel_csr_d), 7.853 +`ifdef LM32_MC_ARITHMETIC_ENABLED 7.854 + .x_result_sel_mc_arith (x_result_sel_mc_arith_d), 7.855 +`endif 7.856 +`ifdef LM32_NO_BARREL_SHIFT 7.857 + .x_result_sel_shift (x_result_sel_shift_d), 7.858 +`endif 7.859 +`ifdef CFG_SIGN_EXTEND_ENABLED 7.860 + .x_result_sel_sext (x_result_sel_sext_d), 7.861 +`endif 7.862 + .x_result_sel_logic (x_result_sel_logic_d), 7.863 +`ifdef CFG_USER_ENABLED 7.864 + .x_result_sel_user (x_result_sel_user_d), 7.865 +`endif 7.866 + .x_result_sel_add (x_result_sel_add_d), 7.867 + .m_result_sel_compare (m_result_sel_compare_d), 7.868 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 7.869 + .m_result_sel_shift (m_result_sel_shift_d), 7.870 +`endif 7.871 + .w_result_sel_load (w_result_sel_load_d), 7.872 +`ifdef CFG_PL_MULTIPLY_ENABLED 7.873 + .w_result_sel_mul (w_result_sel_mul_d), 7.874 +`endif 7.875 + .x_bypass_enable (x_bypass_enable_d), 7.876 + .m_bypass_enable (m_bypass_enable_d), 7.877 + .read_enable_0 (read_enable_0_d), 7.878 + .read_idx_0 (read_idx_0_d), 7.879 + .read_enable_1 (read_enable_1_d), 7.880 + .read_idx_1 (read_idx_1_d), 7.881 + .write_enable (write_enable_d), 7.882 + .write_idx (write_idx_d), 7.883 + .immediate (immediate_d), 7.884 + .branch_offset (branch_offset_d), 7.885 + .load (load_d), 7.886 + .store (store_d), 7.887 + .size (size_d), 7.888 + .sign_extend (sign_extend_d), 7.889 + .adder_op (adder_op_d), 7.890 + .logic_op (logic_op_d), 7.891 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 7.892 + .direction (direction_d), 7.893 +`endif 7.894 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED 7.895 + .shift_left (shift_left_d), 7.896 + .shift_right (shift_right_d), 7.897 +`endif 7.898 +`ifdef CFG_MC_MULTIPLY_ENABLED 7.899 + .multiply (multiply_d), 7.900 +`endif 7.901 +`ifdef CFG_MC_DIVIDE_ENABLED 7.902 + .divide (divide_d), 7.903 + .modulus (modulus_d), 7.904 +`endif 7.905 + .branch (branch_d), 7.906 + .bi_unconditional (bi_unconditional), 7.907 + .bi_conditional (bi_conditional), 7.908 + .branch_reg (branch_reg_d), 7.909 + .condition (condition_d), 7.910 +`ifdef CFG_DEBUG_ENABLED 7.911 + .break_opcode (break_d), 7.912 +`endif 7.913 + .scall (scall_d), 7.914 + .eret (eret_d), 7.915 +`ifdef CFG_DEBUG_ENABLED 7.916 + .bret (bret_d), 7.917 +`endif 7.918 +`ifdef CFG_USER_ENABLED 7.919 + .user_opcode (user_opcode_d), 7.920 +`endif 7.921 + .csr_write_enable (csr_write_enable_d) 7.922 + ); 7.923 + 7.924 +// Load/store unit 7.925 +lm32_load_store_unit #( 7.926 + .associativity (dcache_associativity), 7.927 + .sets (dcache_sets), 7.928 + .bytes_per_line (dcache_bytes_per_line), 7.929 + .base_address (dcache_base_address), 7.930 + .limit (dcache_limit) 7.931 + ) load_store_unit ( 7.932 + // ----- Inputs ------- 7.933 + .clk_i (clk_i), 7.934 + .rst_i (rst_i), 7.935 + // From pipeline 7.936 + .stall_a (stall_a), 7.937 + .stall_x (stall_x), 7.938 + .stall_m (stall_m), 7.939 + .kill_x (kill_x), 7.940 + .kill_m (kill_m), 7.941 + .exception_m (exception_m), 7.942 + .store_operand_x (store_operand_x), 7.943 + .load_store_address_x (adder_result_x), 7.944 + .load_store_address_m (operand_m), 7.945 + .load_store_address_w (operand_w[1:0]), 7.946 + .load_x (load_x), 7.947 + .store_x (store_x), 7.948 + .load_q_x (load_q_x), 7.949 + .store_q_x (store_q_x), 7.950 + .load_q_m (load_q_m), 7.951 + .store_q_m (store_q_m), 7.952 + .sign_extend_x (sign_extend_x), 7.953 + .size_x (size_x), 7.954 +`ifdef CFG_DCACHE_ENABLED 7.955 + .dflush (dflush_m), 7.956 +`endif 7.957 +`ifdef CFG_IROM_ENABLED 7.958 + .irom_data_m (irom_data_m), 7.959 +`endif 7.960 + // From Wishbone 7.961 + .d_dat_i (D_DAT_I), 7.962 + .d_ack_i (D_ACK_I), 7.963 + .d_err_i (D_ERR_I), 7.964 + .d_rty_i (D_RTY_I), 7.965 + // ----- Outputs ------- 7.966 + // To pipeline 7.967 +`ifdef CFG_DCACHE_ENABLED 7.968 + .dcache_refill_request (dcache_refill_request), 7.969 + .dcache_restart_request (dcache_restart_request), 7.970 + .dcache_stall_request (dcache_stall_request), 7.971 + .dcache_refilling (dcache_refilling), 7.972 +`endif 7.973 +`ifdef CFG_IROM_ENABLED 7.974 + .irom_store_data_m (irom_store_data_m), 7.975 + .irom_address_xm (irom_address_xm), 7.976 + .irom_we_xm (irom_we_xm), 7.977 + .irom_stall_request_x (irom_stall_request_x), 7.978 +`endif 7.979 + .load_data_w (load_data_w), 7.980 + .stall_wb_load (stall_wb_load), 7.981 + // To Wishbone 7.982 + .d_dat_o (D_DAT_O), 7.983 + .d_adr_o (D_ADR_O), 7.984 + .d_cyc_o (D_CYC_O), 7.985 + .d_sel_o (D_SEL_O), 7.986 + .d_stb_o (D_STB_O), 7.987 + .d_we_o (D_WE_O), 7.988 + .d_cti_o (D_CTI_O), 7.989 + .d_lock_o (D_LOCK_O), 7.990 + .d_bte_o (D_BTE_O) 7.991 + ); 7.992 + 7.993 +// Adder 7.994 +lm32_adder adder ( 7.995 + // ----- Inputs ------- 7.996 + .adder_op_x (adder_op_x), 7.997 + .adder_op_x_n (adder_op_x_n), 7.998 + .operand_0_x (operand_0_x), 7.999 + .operand_1_x (operand_1_x), 7.1000 + // ----- Outputs ------- 7.1001 + .adder_result_x (adder_result_x), 7.1002 + .adder_carry_n_x (adder_carry_n_x), 7.1003 + .adder_overflow_x (adder_overflow_x) 7.1004 + ); 7.1005 + 7.1006 +// Logic operations 7.1007 +lm32_logic_op logic_op ( 7.1008 + // ----- Inputs ------- 7.1009 + .logic_op_x (logic_op_x), 7.1010 + .operand_0_x (operand_0_x), 7.1011 + 7.1012 + .operand_1_x (operand_1_x), 7.1013 + // ----- Outputs ------- 7.1014 + .logic_result_x (logic_result_x) 7.1015 + ); 7.1016 + 7.1017 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 7.1018 +// Pipelined barrel-shifter 7.1019 +lm32_shifter shifter ( 7.1020 + // ----- Inputs ------- 7.1021 + .clk_i (clk_i), 7.1022 + .rst_i (rst_i), 7.1023 + .stall_x (stall_x), 7.1024 + .direction_x (direction_x), 7.1025 + .sign_extend_x (sign_extend_x), 7.1026 + .operand_0_x (operand_0_x), 7.1027 + .operand_1_x (operand_1_x), 7.1028 + // ----- Outputs ------- 7.1029 + .shifter_result_m (shifter_result_m) 7.1030 + ); 7.1031 +`endif 7.1032 + 7.1033 +`ifdef CFG_PL_MULTIPLY_ENABLED 7.1034 +// Pipeline fixed-point multiplier 7.1035 +lm32_multiplier multiplier ( 7.1036 + // ----- Inputs ------- 7.1037 + .clk_i (clk_i), 7.1038 + .rst_i (rst_i), 7.1039 + .stall_x (stall_x), 7.1040 + .stall_m (stall_m), 7.1041 + .operand_0 (d_result_0), 7.1042 + .operand_1 (d_result_1), 7.1043 + // ----- Outputs ------- 7.1044 + .result (multiplier_result_w) 7.1045 + ); 7.1046 +`endif 7.1047 + 7.1048 +`ifdef LM32_MC_ARITHMETIC_ENABLED 7.1049 +// Multi-cycle arithmetic 7.1050 +lm32_mc_arithmetic mc_arithmetic ( 7.1051 + // ----- Inputs ------- 7.1052 + .clk_i (clk_i), 7.1053 + .rst_i (rst_i), 7.1054 + .stall_d (stall_d), 7.1055 + .kill_x (kill_x), 7.1056 +`ifdef CFG_MC_DIVIDE_ENABLED 7.1057 + .divide_d (divide_q_d), 7.1058 + .modulus_d (modulus_q_d), 7.1059 +`endif 7.1060 +`ifdef CFG_MC_MULTIPLY_ENABLED 7.1061 + .multiply_d (multiply_q_d), 7.1062 +`endif 7.1063 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED 7.1064 + .shift_left_d (shift_left_q_d), 7.1065 + .shift_right_d (shift_right_q_d), 7.1066 + .sign_extend_d (sign_extend_d), 7.1067 +`endif 7.1068 + .operand_0_d (d_result_0), 7.1069 + .operand_1_d (d_result_1), 7.1070 + // ----- Outputs ------- 7.1071 + .result_x (mc_result_x), 7.1072 +`ifdef CFG_MC_DIVIDE_ENABLED 7.1073 + .divide_by_zero_x (divide_by_zero_x), 7.1074 +`endif 7.1075 + .stall_request_x (mc_stall_request_x) 7.1076 + ); 7.1077 +`endif 7.1078 + 7.1079 +`ifdef CFG_INTERRUPTS_ENABLED 7.1080 +// Interrupt unit 7.1081 +lm32_interrupt interrupt ( 7.1082 + // ----- Inputs ------- 7.1083 + .clk_i (clk_i), 7.1084 + .rst_i (rst_i), 7.1085 + // From external devices 7.1086 + .interrupt_n (interrupt_n), 7.1087 + // From pipeline 7.1088 + .stall_x (stall_x), 7.1089 +`ifdef CFG_DEBUG_ENABLED 7.1090 + .non_debug_exception (non_debug_exception_q_w), 7.1091 + .debug_exception (debug_exception_q_w), 7.1092 +`else 7.1093 + .exception (exception_q_w), 7.1094 +`endif 7.1095 + .eret_q_x (eret_q_x), 7.1096 +`ifdef CFG_DEBUG_ENABLED 7.1097 + .bret_q_x (bret_q_x), 7.1098 +`endif 7.1099 + .csr (csr_x), 7.1100 + .csr_write_data (operand_1_x), 7.1101 + .csr_write_enable (csr_write_enable_q_x), 7.1102 + // ----- Outputs ------- 7.1103 + .interrupt_exception (interrupt_exception), 7.1104 + // To pipeline 7.1105 + .csr_read_data (interrupt_csr_read_data_x) 7.1106 + ); 7.1107 +`endif 7.1108 + 7.1109 +`ifdef CFG_JTAG_ENABLED 7.1110 +// JTAG interface 7.1111 +lm32_jtag jtag ( 7.1112 + // ----- Inputs ------- 7.1113 + .clk_i (clk_i), 7.1114 + .rst_i (rst_i), 7.1115 + // From JTAG 7.1116 + .jtag_clk (jtag_clk), 7.1117 + .jtag_update (jtag_update), 7.1118 + .jtag_reg_q (jtag_reg_q), 7.1119 + .jtag_reg_addr_q (jtag_reg_addr_q), 7.1120 + // From pipeline 7.1121 +`ifdef CFG_JTAG_UART_ENABLED 7.1122 + .csr (csr_x), 7.1123 + .csr_write_data (operand_1_x), 7.1124 + .csr_write_enable (csr_write_enable_q_x), 7.1125 + .stall_x (stall_x), 7.1126 +`endif 7.1127 +`ifdef CFG_HW_DEBUG_ENABLED 7.1128 + .jtag_read_data (jtag_read_data), 7.1129 + .jtag_access_complete (jtag_access_complete), 7.1130 +`endif 7.1131 +`ifdef CFG_DEBUG_ENABLED 7.1132 + .exception_q_w (debug_exception_q_w || non_debug_exception_q_w), 7.1133 +`endif 7.1134 + // ----- Outputs ------- 7.1135 + // To pipeline 7.1136 +`ifdef CFG_JTAG_UART_ENABLED 7.1137 + .jtx_csr_read_data (jtx_csr_read_data), 7.1138 + .jrx_csr_read_data (jrx_csr_read_data), 7.1139 +`endif 7.1140 +`ifdef CFG_HW_DEBUG_ENABLED 7.1141 + .jtag_csr_write_enable (jtag_csr_write_enable), 7.1142 + .jtag_csr_write_data (jtag_csr_write_data), 7.1143 + .jtag_csr (jtag_csr), 7.1144 + .jtag_read_enable (jtag_read_enable), 7.1145 + .jtag_write_enable (jtag_write_enable), 7.1146 + .jtag_write_data (jtag_write_data), 7.1147 + .jtag_address (jtag_address), 7.1148 +`endif 7.1149 +`ifdef CFG_DEBUG_ENABLED 7.1150 + .jtag_break (jtag_break), 7.1151 + .jtag_reset (reset_exception), 7.1152 +`endif 7.1153 + // To JTAG 7.1154 + .jtag_reg_d (jtag_reg_d), 7.1155 + .jtag_reg_addr_d (jtag_reg_addr_d) 7.1156 + ); 7.1157 +`endif 7.1158 + 7.1159 +`ifdef CFG_DEBUG_ENABLED 7.1160 +// Debug unit 7.1161 +lm32_debug #( 7.1162 + .breakpoints (breakpoints), 7.1163 + .watchpoints (watchpoints) 7.1164 + ) hw_debug ( 7.1165 + // ----- Inputs ------- 7.1166 + .clk_i (clk_i), 7.1167 + .rst_i (rst_i), 7.1168 + .pc_x (pc_x), 7.1169 + .load_x (load_x), 7.1170 + .store_x (store_x), 7.1171 + .load_store_address_x (adder_result_x), 7.1172 + .csr_write_enable_x (csr_write_enable_q_x), 7.1173 + .csr_write_data (operand_1_x), 7.1174 + .csr_x (csr_x), 7.1175 +`ifdef CFG_HW_DEBUG_ENABLED 7.1176 + .jtag_csr_write_enable (jtag_csr_write_enable), 7.1177 + .jtag_csr_write_data (jtag_csr_write_data), 7.1178 + .jtag_csr (jtag_csr), 7.1179 +`endif 7.1180 +`ifdef LM32_SINGLE_STEP_ENABLED 7.1181 + .eret_q_x (eret_q_x), 7.1182 + .bret_q_x (bret_q_x), 7.1183 + .stall_x (stall_x), 7.1184 + .exception_x (exception_x), 7.1185 + .q_x (q_x), 7.1186 +`ifdef CFG_DCACHE_ENABLED 7.1187 + .dcache_refill_request (dcache_refill_request), 7.1188 +`endif 7.1189 +`endif 7.1190 + // ----- Outputs ------- 7.1191 +`ifdef LM32_SINGLE_STEP_ENABLED 7.1192 + .dc_ss (dc_ss), 7.1193 +`endif 7.1194 + .dc_re (dc_re), 7.1195 + .bp_match (bp_match), 7.1196 + .wp_match (wp_match) 7.1197 + ); 7.1198 +`endif 7.1199 + 7.1200 +// Register file 7.1201 + 7.1202 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE 7.1203 + /*---------------------------------------------------------------------- 7.1204 + Register File is implemented using EBRs. There can be three accesses to 7.1205 + the register file in each cycle: two reads and one write. On-chip block 7.1206 + RAM has two read/write ports. To accomodate three accesses, two on-chip 7.1207 + block RAMs are used (each register file "write" is made to both block 7.1208 + RAMs). 7.1209 + 7.1210 + One limitation of the on-chip block RAMs is that one cannot perform a 7.1211 + read and write to same location in a cycle (if this is done, then the 7.1212 + data read out is indeterminate). 7.1213 + ----------------------------------------------------------------------*/ 7.1214 + wire [31:0] regfile_data_0, regfile_data_1; 7.1215 + reg [31:0] w_result_d; 7.1216 + reg regfile_raw_0, regfile_raw_0_nxt; 7.1217 + reg regfile_raw_1, regfile_raw_1_nxt; 7.1218 + 7.1219 + /*---------------------------------------------------------------------- 7.1220 + Check if read and write is being performed to same register in current 7.1221 + cycle? This is done by comparing the read and write IDXs. 7.1222 + ----------------------------------------------------------------------*/ 7.1223 + always @(reg_write_enable_q_w or write_idx_w or instruction_f) 7.1224 + begin 7.1225 + if (reg_write_enable_q_w 7.1226 + && (write_idx_w == instruction_f[25:21])) 7.1227 + regfile_raw_0_nxt = 1'b1; 7.1228 + else 7.1229 + regfile_raw_0_nxt = 1'b0; 7.1230 + 7.1231 + if (reg_write_enable_q_w 7.1232 + && (write_idx_w == instruction_f[20:16])) 7.1233 + regfile_raw_1_nxt = 1'b1; 7.1234 + else 7.1235 + regfile_raw_1_nxt = 1'b0; 7.1236 + end 7.1237 + 7.1238 + /*---------------------------------------------------------------------- 7.1239 + Select latched (delayed) write value or data from register file. If 7.1240 + read in previous cycle was performed to register written to in same 7.1241 + cycle, then latched (delayed) write value is selected. 7.1242 + ----------------------------------------------------------------------*/ 7.1243 + always @(regfile_raw_0 or w_result_d or regfile_data_0) 7.1244 + if (regfile_raw_0) 7.1245 + reg_data_live_0 = w_result_d; 7.1246 + else 7.1247 + reg_data_live_0 = regfile_data_0; 7.1248 + 7.1249 + /*---------------------------------------------------------------------- 7.1250 + Select latched (delayed) write value or data from register file. If 7.1251 + read in previous cycle was performed to register written to in same 7.1252 + cycle, then latched (delayed) write value is selected. 7.1253 + ----------------------------------------------------------------------*/ 7.1254 + always @(regfile_raw_1 or w_result_d or regfile_data_1) 7.1255 + if (regfile_raw_1) 7.1256 + reg_data_live_1 = w_result_d; 7.1257 + else 7.1258 + reg_data_live_1 = regfile_data_1; 7.1259 + 7.1260 + /*---------------------------------------------------------------------- 7.1261 + Latch value written to register file 7.1262 + ----------------------------------------------------------------------*/ 7.1263 + always @(posedge clk_i `CFG_RESET_SENSITIVITY) 7.1264 + if (rst_i == `TRUE) 7.1265 + begin 7.1266 + regfile_raw_0 <= 1'b0; 7.1267 + regfile_raw_1 <= 1'b0; 7.1268 + w_result_d <= 32'b0; 7.1269 + end 7.1270 + else 7.1271 + begin 7.1272 + regfile_raw_0 <= regfile_raw_0_nxt; 7.1273 + regfile_raw_1 <= regfile_raw_1_nxt; 7.1274 + w_result_d <= w_result; 7.1275 + end 7.1276 + 7.1277 + /*---------------------------------------------------------------------- 7.1278 + Register file instantiation as Pseudo-Dual Port EBRs. 7.1279 + ----------------------------------------------------------------------*/ 7.1280 + pmi_ram_dp 7.1281 + #( 7.1282 + // ----- Parameters ----- 7.1283 + .pmi_wr_addr_depth(1<<5), 7.1284 + .pmi_wr_addr_width(5), 7.1285 + .pmi_wr_data_width(32), 7.1286 + .pmi_rd_addr_depth(1<<5), 7.1287 + .pmi_rd_addr_width(5), 7.1288 + .pmi_rd_data_width(32), 7.1289 + .pmi_regmode("noreg"), 7.1290 + .pmi_gsr("enable"), 7.1291 + .pmi_resetmode("sync"), 7.1292 + .pmi_init_file("none"), 7.1293 + .pmi_init_file_format("binary"), 7.1294 + .pmi_family(`LATTICE_FAMILY), 7.1295 + .module_type("pmi_ram_dp") 7.1296 + ) 7.1297 + reg_0 7.1298 + ( 7.1299 + // ----- Inputs ----- 7.1300 + .Data(w_result), 7.1301 + .WrAddress(write_idx_w), 7.1302 + .RdAddress(instruction_f[25:21]), 7.1303 + .WrClock(clk_i), 7.1304 + .RdClock(clk_i), 7.1305 + .WrClockEn(`TRUE), 7.1306 + .RdClockEn(`TRUE), 7.1307 + .WE(reg_write_enable_q_w), 7.1308 + .Reset(rst_i), 7.1309 + // ----- Outputs ----- 7.1310 + .Q(regfile_data_0) 7.1311 + ); 7.1312 + 7.1313 + pmi_ram_dp 7.1314 + #( 7.1315 + // ----- Parameters ----- 7.1316 + .pmi_wr_addr_depth(1<<5), 7.1317 + .pmi_wr_addr_width(5), 7.1318 + .pmi_wr_data_width(32), 7.1319 + .pmi_rd_addr_depth(1<<5), 7.1320 + .pmi_rd_addr_width(5), 7.1321 + .pmi_rd_data_width(32), 7.1322 + .pmi_regmode("noreg"), 7.1323 + .pmi_gsr("enable"), 7.1324 + .pmi_resetmode("sync"), 7.1325 + .pmi_init_file("none"), 7.1326 + .pmi_init_file_format("binary"), 7.1327 + .pmi_family(`LATTICE_FAMILY), 7.1328 + .module_type("pmi_ram_dp") 7.1329 + ) 7.1330 + reg_1 7.1331 + ( 7.1332 + // ----- Inputs ----- 7.1333 + .Data(w_result), 7.1334 + .WrAddress(write_idx_w), 7.1335 + .RdAddress(instruction_f[20:16]), 7.1336 + .WrClock(clk_i), 7.1337 + .RdClock(clk_i), 7.1338 + .WrClockEn(`TRUE), 7.1339 + .RdClockEn(`TRUE), 7.1340 + .WE(reg_write_enable_q_w), 7.1341 + .Reset(rst_i), 7.1342 + // ----- Outputs ----- 7.1343 + .Q(regfile_data_1) 7.1344 + ); 7.1345 +`endif 7.1346 + 7.1347 +`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE 7.1348 + pmi_ram_dp 7.1349 + #( 7.1350 + // ----- Parameters ----- 7.1351 + .pmi_wr_addr_depth(1<<5), 7.1352 + .pmi_wr_addr_width(5), 7.1353 + .pmi_wr_data_width(32), 7.1354 + .pmi_rd_addr_depth(1<<5), 7.1355 + .pmi_rd_addr_width(5), 7.1356 + .pmi_rd_data_width(32), 7.1357 + .pmi_regmode("noreg"), 7.1358 + .pmi_gsr("enable"), 7.1359 + .pmi_resetmode("sync"), 7.1360 + .pmi_init_file("none"), 7.1361 + .pmi_init_file_format("binary"), 7.1362 + .pmi_family(`LATTICE_FAMILY), 7.1363 + .module_type("pmi_ram_dp") 7.1364 + ) 7.1365 + reg_0 7.1366 + ( 7.1367 + // ----- Inputs ----- 7.1368 + .Data(w_result), 7.1369 + .WrAddress(write_idx_w), 7.1370 + .RdAddress(read_idx_0_d), 7.1371 + .WrClock(clk_i), 7.1372 + .RdClock(clk_n_i), 7.1373 + .WrClockEn(`TRUE), 7.1374 + .RdClockEn(stall_f == `FALSE), 7.1375 + .WE(reg_write_enable_q_w), 7.1376 + .Reset(rst_i), 7.1377 + // ----- Outputs ----- 7.1378 + .Q(reg_data_0) 7.1379 + ); 7.1380 + 7.1381 + pmi_ram_dp 7.1382 + #( 7.1383 + // ----- Parameters ----- 7.1384 + .pmi_wr_addr_depth(1<<5), 7.1385 + .pmi_wr_addr_width(5), 7.1386 + .pmi_wr_data_width(32), 7.1387 + .pmi_rd_addr_depth(1<<5), 7.1388 + .pmi_rd_addr_width(5), 7.1389 + .pmi_rd_data_width(32), 7.1390 + .pmi_regmode("noreg"), 7.1391 + .pmi_gsr("enable"), 7.1392 + .pmi_resetmode("sync"), 7.1393 + .pmi_init_file("none"), 7.1394 + .pmi_init_file_format("binary"), 7.1395 + .pmi_family(`LATTICE_FAMILY), 7.1396 + .module_type("pmi_ram_dp") 7.1397 + ) 7.1398 + reg_1 7.1399 + ( 7.1400 + // ----- Inputs ----- 7.1401 + .Data(w_result), 7.1402 + .WrAddress(write_idx_w), 7.1403 + .RdAddress(read_idx_1_d), 7.1404 + .WrClock(clk_i), 7.1405 + .RdClock(clk_n_i), 7.1406 + .WrClockEn(`TRUE), 7.1407 + .RdClockEn(stall_f == `FALSE), 7.1408 + .WE(reg_write_enable_q_w), 7.1409 + .Reset(rst_i), 7.1410 + // ----- Outputs ----- 7.1411 + .Q(reg_data_1) 7.1412 + ); 7.1413 +`endif 7.1414 + 7.1415 + 7.1416 +///////////////////////////////////////////////////// 7.1417 +// Combinational Logic 7.1418 +///////////////////////////////////////////////////// 7.1419 + 7.1420 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE 7.1421 +// Select between buffered and live data from register file 7.1422 +assign reg_data_0 = use_buf ? reg_data_buf_0 : reg_data_live_0; 7.1423 +assign reg_data_1 = use_buf ? reg_data_buf_1 : reg_data_live_1; 7.1424 +`endif 7.1425 +`ifdef LM32_EBR_REGISTER_FILE 7.1426 +`else 7.1427 +// Register file read ports 7.1428 +assign reg_data_0 = registers[read_idx_0_d]; 7.1429 +assign reg_data_1 = registers[read_idx_1_d]; 7.1430 +`endif 7.1431 + 7.1432 +// Detect read-after-write hazzards 7.1433 +assign raw_x_0 = (write_idx_x == read_idx_0_d) && (write_enable_q_x == `TRUE); 7.1434 +assign raw_m_0 = (write_idx_m == read_idx_0_d) && (write_enable_q_m == `TRUE); 7.1435 +assign raw_w_0 = (write_idx_w == read_idx_0_d) && (write_enable_q_w == `TRUE); 7.1436 +assign raw_x_1 = (write_idx_x == read_idx_1_d) && (write_enable_q_x == `TRUE); 7.1437 +assign raw_m_1 = (write_idx_m == read_idx_1_d) && (write_enable_q_m == `TRUE); 7.1438 +assign raw_w_1 = (write_idx_w == read_idx_1_d) && (write_enable_q_w == `TRUE); 7.1439 + 7.1440 +// Interlock detection - Raise an interlock for RAW hazzards 7.1441 +always @(*) 7.1442 +begin 7.1443 + if ( ( (x_bypass_enable_x == `FALSE) 7.1444 + && ( ((read_enable_0_d == `TRUE) && (raw_x_0 == `TRUE)) 7.1445 + || ((read_enable_1_d == `TRUE) && (raw_x_1 == `TRUE)) 7.1446 + ) 7.1447 + ) 7.1448 + || ( (m_bypass_enable_m == `FALSE) 7.1449 + && ( ((read_enable_0_d == `TRUE) && (raw_m_0 == `TRUE)) 7.1450 + || ((read_enable_1_d == `TRUE) && (raw_m_1 == `TRUE)) 7.1451 + ) 7.1452 + ) 7.1453 + ) 7.1454 + interlock = `TRUE; 7.1455 + else 7.1456 + interlock = `FALSE; 7.1457 +end 7.1458 + 7.1459 +// Bypass for reg port 0 7.1460 +always @(*) 7.1461 +begin 7.1462 + if (raw_x_0 == `TRUE) 7.1463 + bypass_data_0 = x_result; 7.1464 + else if (raw_m_0 == `TRUE) 7.1465 + bypass_data_0 = m_result; 7.1466 + else if (raw_w_0 == `TRUE) 7.1467 + bypass_data_0 = w_result; 7.1468 + else 7.1469 + bypass_data_0 = reg_data_0; 7.1470 +end 7.1471 + 7.1472 +// Bypass for reg port 1 7.1473 +always @(*) 7.1474 +begin 7.1475 + if (raw_x_1 == `TRUE) 7.1476 + bypass_data_1 = x_result; 7.1477 + else if (raw_m_1 == `TRUE) 7.1478 + bypass_data_1 = m_result; 7.1479 + else if (raw_w_1 == `TRUE) 7.1480 + bypass_data_1 = w_result; 7.1481 + else 7.1482 + bypass_data_1 = reg_data_1; 7.1483 +end 7.1484 + 7.1485 + /*---------------------------------------------------------------------- 7.1486 + Branch prediction is performed in D stage of pipeline. Only PC-relative 7.1487 + branches are predicted: forward-pointing conditional branches are not- 7.1488 + taken, while backward-pointing conditional branches are taken. 7.1489 + Unconditional branches are always predicted taken! 7.1490 + ----------------------------------------------------------------------*/ 7.1491 + assign branch_predict_d = bi_unconditional | bi_conditional; 7.1492 + assign branch_predict_taken_d = bi_unconditional ? 1'b1 : (bi_conditional ? instruction_d[15] : 1'b0); 7.1493 + 7.1494 + // Compute branch target address: Branch PC PLUS Offset 7.1495 + assign branch_target_d = pc_d + branch_offset_d; 7.1496 + 7.1497 + // Compute fetch address. Address of instruction sequentially after the 7.1498 + // branch if branch is not taken. Target address of branch is branch is 7.1499 + // taken 7.1500 + assign branch_predict_address_d = branch_predict_taken_d ? branch_target_d : pc_f; 7.1501 + 7.1502 +// D stage result selection 7.1503 +always @(*) 7.1504 +begin 7.1505 + d_result_0 = d_result_sel_0_d[0] ? {pc_f, 2'b00} : bypass_data_0; 7.1506 + case (d_result_sel_1_d) 7.1507 + `LM32_D_RESULT_SEL_1_ZERO: d_result_1 = {`LM32_WORD_WIDTH{1'b0}}; 7.1508 + `LM32_D_RESULT_SEL_1_REG_1: d_result_1 = bypass_data_1; 7.1509 + `LM32_D_RESULT_SEL_1_IMMEDIATE: d_result_1 = immediate_d; 7.1510 + default: d_result_1 = {`LM32_WORD_WIDTH{1'bx}}; 7.1511 + endcase 7.1512 +end 7.1513 + 7.1514 +`ifdef CFG_USER_ENABLED 7.1515 +// Operands for user-defined instructions 7.1516 +assign user_operand_0 = operand_0_x; 7.1517 +assign user_operand_1 = operand_1_x; 7.1518 +`endif 7.1519 + 7.1520 +`ifdef CFG_SIGN_EXTEND_ENABLED 7.1521 +// Sign-extension 7.1522 +assign sextb_result_x = {{24{operand_0_x[7]}}, operand_0_x[7:0]}; 7.1523 +assign sexth_result_x = {{16{operand_0_x[15]}}, operand_0_x[15:0]}; 7.1524 +assign sext_result_x = size_x == `LM32_SIZE_BYTE ? sextb_result_x : sexth_result_x; 7.1525 +`endif 7.1526 + 7.1527 +`ifdef LM32_NO_BARREL_SHIFT 7.1528 +// Only single bit shift operations are supported when barrel-shifter isn't implemented 7.1529 +assign shifter_result_x = {operand_0_x[`LM32_WORD_WIDTH-1] & sign_extend_x, operand_0_x[`LM32_WORD_WIDTH-1:1]}; 7.1530 +`endif 7.1531 + 7.1532 +// Condition evaluation 7.1533 +assign cmp_zero = operand_0_x == operand_1_x; 7.1534 +assign cmp_negative = adder_result_x[`LM32_WORD_WIDTH-1]; 7.1535 +assign cmp_overflow = adder_overflow_x; 7.1536 +assign cmp_carry_n = adder_carry_n_x; 7.1537 +always @(*) 7.1538 +begin 7.1539 + case (condition_x) 7.1540 + `LM32_CONDITION_U1: condition_met_x = `TRUE; 7.1541 + `LM32_CONDITION_U2: condition_met_x = `TRUE; 7.1542 + `LM32_CONDITION_E: condition_met_x = cmp_zero; 7.1543 + `LM32_CONDITION_NE: condition_met_x = !cmp_zero; 7.1544 + `LM32_CONDITION_G: condition_met_x = !cmp_zero && (cmp_negative == cmp_overflow); 7.1545 + `LM32_CONDITION_GU: condition_met_x = cmp_carry_n && !cmp_zero; 7.1546 + `LM32_CONDITION_GE: condition_met_x = cmp_negative == cmp_overflow; 7.1547 + `LM32_CONDITION_GEU: condition_met_x = cmp_carry_n; 7.1548 + default: condition_met_x = 1'bx; 7.1549 + endcase 7.1550 +end 7.1551 + 7.1552 +// X stage result selection 7.1553 +always @(*) 7.1554 +begin 7.1555 + x_result = x_result_sel_add_x ? adder_result_x 7.1556 + : x_result_sel_csr_x ? csr_read_data_x 7.1557 +`ifdef CFG_SIGN_EXTEND_ENABLED 7.1558 + : x_result_sel_sext_x ? sext_result_x 7.1559 +`endif 7.1560 +`ifdef CFG_USER_ENABLED 7.1561 + : x_result_sel_user_x ? user_result 7.1562 +`endif 7.1563 +`ifdef LM32_NO_BARREL_SHIFT 7.1564 + : x_result_sel_shift_x ? shifter_result_x 7.1565 +`endif 7.1566 +`ifdef LM32_MC_ARITHMETIC_ENABLED 7.1567 + : x_result_sel_mc_arith_x ? mc_result_x 7.1568 +`endif 7.1569 + : logic_result_x; 7.1570 +end 7.1571 + 7.1572 +// M stage result selection 7.1573 +always @(*) 7.1574 +begin 7.1575 + m_result = m_result_sel_compare_m ? {{`LM32_WORD_WIDTH-1{1'b0}}, condition_met_m} 7.1576 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 7.1577 + : m_result_sel_shift_m ? shifter_result_m 7.1578 +`endif 7.1579 + : operand_m; 7.1580 +end 7.1581 + 7.1582 +// W stage result selection 7.1583 +always @(*) 7.1584 +begin 7.1585 + w_result = w_result_sel_load_w ? load_data_w 7.1586 +`ifdef CFG_PL_MULTIPLY_ENABLED 7.1587 + : w_result_sel_mul_w ? multiplier_result_w 7.1588 +`endif 7.1589 + : operand_w; 7.1590 +end 7.1591 + 7.1592 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH 7.1593 +// Indicate when a branch should be taken in X stage 7.1594 +assign branch_taken_x = (stall_x == `FALSE) 7.1595 + && ( (branch_x == `TRUE) 7.1596 + && ((condition_x == `LM32_CONDITION_U1) || (condition_x == `LM32_CONDITION_U2)) 7.1597 + && (valid_x == `TRUE) 7.1598 + && (branch_predict_x == `FALSE) 7.1599 + ); 7.1600 +`endif 7.1601 + 7.1602 +// Indicate when a branch should be taken in M stage (exceptions are a type of branch) 7.1603 +assign branch_taken_m = (stall_m == `FALSE) 7.1604 + && ( ( (branch_m == `TRUE) 7.1605 + && (valid_m == `TRUE) 7.1606 + && ( ( (condition_met_m == `TRUE) 7.1607 + && (branch_predict_taken_m == `FALSE) 7.1608 + ) 7.1609 + || ( (condition_met_m == `FALSE) 7.1610 + && (branch_predict_m == `TRUE) 7.1611 + && (branch_predict_taken_m == `TRUE) 7.1612 + ) 7.1613 + ) 7.1614 + ) 7.1615 + || (exception_m == `TRUE) 7.1616 + ); 7.1617 + 7.1618 +// Indicate when a branch in M stage is mispredicted as being taken 7.1619 +assign branch_mispredict_taken_m = (condition_met_m == `FALSE) 7.1620 + && (branch_predict_m == `TRUE) 7.1621 + && (branch_predict_taken_m == `TRUE); 7.1622 + 7.1623 +// Indicate when a branch in M stage will cause flush in X stage 7.1624 +assign branch_flushX_m = (stall_m == `FALSE) 7.1625 + && ( ( (branch_m == `TRUE) 7.1626 + && (valid_m == `TRUE) 7.1627 + && ( (condition_met_m == `TRUE) 7.1628 + || ( (condition_met_m == `FALSE) 7.1629 + && (branch_predict_m == `TRUE) 7.1630 + && (branch_predict_taken_m == `TRUE) 7.1631 + ) 7.1632 + ) 7.1633 + ) 7.1634 + || (exception_m == `TRUE) 7.1635 + ); 7.1636 + 7.1637 +// Generate signal that will kill instructions in each pipeline stage when necessary 7.1638 +assign kill_f = ( (valid_d == `TRUE) 7.1639 + && (branch_predict_taken_d == `TRUE) 7.1640 + ) 7.1641 + || (branch_taken_m == `TRUE) 7.1642 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH 7.1643 + || (branch_taken_x == `TRUE) 7.1644 +`endif 7.1645 +`ifdef CFG_ICACHE_ENABLED 7.1646 + || (icache_refill_request == `TRUE) 7.1647 +`endif 7.1648 +`ifdef CFG_DCACHE_ENABLED 7.1649 + || (dcache_refill_request == `TRUE) 7.1650 +`endif 7.1651 + ; 7.1652 +assign kill_d = (branch_taken_m == `TRUE) 7.1653 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH 7.1654 + || (branch_taken_x == `TRUE) 7.1655 +`endif 7.1656 +`ifdef CFG_ICACHE_ENABLED 7.1657 + || (icache_refill_request == `TRUE) 7.1658 +`endif 7.1659 +`ifdef CFG_DCACHE_ENABLED 7.1660 + || (dcache_refill_request == `TRUE) 7.1661 +`endif 7.1662 + ; 7.1663 +assign kill_x = (branch_flushX_m == `TRUE) 7.1664 +`ifdef CFG_DCACHE_ENABLED 7.1665 + || (dcache_refill_request == `TRUE) 7.1666 +`endif 7.1667 + ; 7.1668 +assign kill_m = `FALSE 7.1669 +`ifdef CFG_DCACHE_ENABLED 7.1670 + || (dcache_refill_request == `TRUE) 7.1671 +`endif 7.1672 + ; 7.1673 +assign kill_w = `FALSE 7.1674 +`ifdef CFG_DCACHE_ENABLED 7.1675 + || (dcache_refill_request == `TRUE) 7.1676 +`endif 7.1677 + ; 7.1678 + 7.1679 +// Exceptions 7.1680 + 7.1681 +`ifdef CFG_DEBUG_ENABLED 7.1682 +assign breakpoint_exception = ( ( (break_x == `TRUE) 7.1683 + || (bp_match == `TRUE) 7.1684 + ) 7.1685 + && (valid_x == `TRUE) 7.1686 + ) 7.1687 +`ifdef CFG_JTAG_ENABLED 7.1688 + || (jtag_break == `TRUE) 7.1689 +`endif 7.1690 + ; 7.1691 +`endif 7.1692 + 7.1693 +`ifdef CFG_DEBUG_ENABLED 7.1694 +assign watchpoint_exception = wp_match == `TRUE; 7.1695 +`endif 7.1696 + 7.1697 +`ifdef CFG_BUS_ERRORS_ENABLED 7.1698 +assign instruction_bus_error_exception = ( (bus_error_x == `TRUE) 7.1699 + && (valid_x == `TRUE) 7.1700 + ); 7.1701 +assign data_bus_error_exception = data_bus_error_seen == `TRUE; 7.1702 +`endif 7.1703 + 7.1704 +`ifdef CFG_MC_DIVIDE_ENABLED 7.1705 +assign divide_by_zero_exception = divide_by_zero_x == `TRUE; 7.1706 +`endif 7.1707 + 7.1708 +assign system_call_exception = ( (scall_x == `TRUE) 7.1709 +`ifdef CFG_BUS_ERRORS_ENABLED 7.1710 + && (valid_x == `TRUE) 7.1711 +`endif 7.1712 + ); 7.1713 + 7.1714 +`ifdef CFG_DEBUG_ENABLED 7.1715 +assign debug_exception_x = (breakpoint_exception == `TRUE) 7.1716 + || (watchpoint_exception == `TRUE) 7.1717 + ; 7.1718 + 7.1719 +assign non_debug_exception_x = (system_call_exception == `TRUE) 7.1720 +`ifdef CFG_JTAG_ENABLED 7.1721 + || (reset_exception == `TRUE) 7.1722 +`endif 7.1723 +`ifdef CFG_BUS_ERRORS_ENABLED 7.1724 + || (instruction_bus_error_exception == `TRUE) 7.1725 + || (data_bus_error_exception == `TRUE) 7.1726 +`endif 7.1727 +`ifdef CFG_MC_DIVIDE_ENABLED 7.1728 + || (divide_by_zero_exception == `TRUE) 7.1729 +`endif 7.1730 +`ifdef CFG_INTERRUPTS_ENABLED 7.1731 + || ( (interrupt_exception == `TRUE) 7.1732 +`ifdef LM32_SINGLE_STEP_ENABLED 7.1733 + && (dc_ss == `FALSE) 7.1734 +`endif 7.1735 +`ifdef CFG_BUS_ERRORS_ENABLED 7.1736 + && (store_q_m == `FALSE) 7.1737 + && (D_CYC_O == `FALSE) 7.1738 +`endif 7.1739 + ) 7.1740 +`endif 7.1741 + ; 7.1742 + 7.1743 +assign exception_x = (debug_exception_x == `TRUE) || (non_debug_exception_x == `TRUE); 7.1744 +`else 7.1745 +assign exception_x = (system_call_exception == `TRUE) 7.1746 +`ifdef CFG_BUS_ERRORS_ENABLED 7.1747 + || (instruction_bus_error_exception == `TRUE) 7.1748 + || (data_bus_error_exception == `TRUE) 7.1749 +`endif 7.1750 +`ifdef CFG_MC_DIVIDE_ENABLED 7.1751 + || (divide_by_zero_exception == `TRUE) 7.1752 +`endif 7.1753 +`ifdef CFG_INTERRUPTS_ENABLED 7.1754 + || ( (interrupt_exception == `TRUE) 7.1755 +`ifdef LM32_SINGLE_STEP_ENABLED 7.1756 + && (dc_ss == `FALSE) 7.1757 +`endif 7.1758 +`ifdef CFG_BUS_ERRORS_ENABLED 7.1759 + && (store_q_m == `FALSE) 7.1760 + && (D_CYC_O == `FALSE) 7.1761 +`endif 7.1762 + ) 7.1763 +`endif 7.1764 + ; 7.1765 +`endif 7.1766 + 7.1767 +// Exception ID 7.1768 +always @(*) 7.1769 +begin 7.1770 +`ifdef CFG_DEBUG_ENABLED 7.1771 +`ifdef CFG_JTAG_ENABLED 7.1772 + if (reset_exception == `TRUE) 7.1773 + eid_x = `LM32_EID_RESET; 7.1774 + else 7.1775 +`endif 7.1776 +`ifdef CFG_BUS_ERRORS_ENABLED 7.1777 + if (data_bus_error_exception == `TRUE) 7.1778 + eid_x = `LM32_EID_DATA_BUS_ERROR; 7.1779 + else 7.1780 +`endif 7.1781 + if (breakpoint_exception == `TRUE) 7.1782 + eid_x = `LM32_EID_BREAKPOINT; 7.1783 + else 7.1784 +`endif 7.1785 +`ifdef CFG_BUS_ERRORS_ENABLED 7.1786 + if (data_bus_error_exception == `TRUE) 7.1787 + eid_x = `LM32_EID_DATA_BUS_ERROR; 7.1788 + else 7.1789 + if (instruction_bus_error_exception == `TRUE) 7.1790 + eid_x = `LM32_EID_INST_BUS_ERROR; 7.1791 + else 7.1792 +`endif 7.1793 +`ifdef CFG_DEBUG_ENABLED 7.1794 + if (watchpoint_exception == `TRUE) 7.1795 + eid_x = `LM32_EID_WATCHPOINT; 7.1796 + else 7.1797 +`endif 7.1798 +`ifdef CFG_MC_DIVIDE_ENABLED 7.1799 + if (divide_by_zero_exception == `TRUE) 7.1800 + eid_x = `LM32_EID_DIVIDE_BY_ZERO; 7.1801 + else 7.1802 +`endif 7.1803 +`ifdef CFG_INTERRUPTS_ENABLED 7.1804 + if ( (interrupt_exception == `TRUE) 7.1805 +`ifdef LM32_SINGLE_STEP_ENABLED 7.1806 + && (dc_ss == `FALSE) 7.1807 +`endif 7.1808 + ) 7.1809 + eid_x = `LM32_EID_INTERRUPT; 7.1810 + else 7.1811 +`endif 7.1812 + eid_x = `LM32_EID_SCALL; 7.1813 +end 7.1814 + 7.1815 +// Stall generation 7.1816 + 7.1817 +assign stall_a = (stall_f == `TRUE); 7.1818 + 7.1819 +assign stall_f = (stall_d == `TRUE); 7.1820 + 7.1821 +assign stall_d = (stall_x == `TRUE) 7.1822 + || ( (interlock == `TRUE) 7.1823 + && (kill_d == `FALSE) 7.1824 + ) 7.1825 + || ( ( (eret_d == `TRUE) 7.1826 + || (scall_d == `TRUE) 7.1827 + || (bus_error_d == `TRUE) 7.1828 + ) 7.1829 + && ( (load_q_x == `TRUE) 7.1830 + || (load_q_m == `TRUE) 7.1831 + || (store_q_x == `TRUE) 7.1832 + || (store_q_m == `TRUE) 7.1833 + || (D_CYC_O == `TRUE) 7.1834 + ) 7.1835 + && (kill_d == `FALSE) 7.1836 + ) 7.1837 +`ifdef CFG_DEBUG_ENABLED 7.1838 + || ( ( (break_d == `TRUE) 7.1839 + || (bret_d == `TRUE) 7.1840 + ) 7.1841 + && ( (load_q_x == `TRUE) 7.1842 + || (store_q_x == `TRUE) 7.1843 + || (load_q_m == `TRUE) 7.1844 + || (store_q_m == `TRUE) 7.1845 + || (D_CYC_O == `TRUE) 7.1846 + ) 7.1847 + && (kill_d == `FALSE) 7.1848 + ) 7.1849 +`endif 7.1850 + || ( (csr_write_enable_d == `TRUE) 7.1851 + && (load_q_x == `TRUE) 7.1852 + ) 7.1853 + ; 7.1854 + 7.1855 +assign stall_x = (stall_m == `TRUE) 7.1856 +`ifdef LM32_MC_ARITHMETIC_ENABLED 7.1857 + || ( (mc_stall_request_x == `TRUE) 7.1858 + && (kill_x == `FALSE) 7.1859 + ) 7.1860 +`endif 7.1861 +`ifdef CFG_IROM_ENABLED 7.1862 + // Stall load/store instruction in D stage if there is an ongoing store 7.1863 + // operation to instruction ROM in M stage 7.1864 + || ( (irom_stall_request_x == `TRUE) 7.1865 + && ( (load_d == `TRUE) 7.1866 + || (store_d == `TRUE) 7.1867 + ) 7.1868 + ) 7.1869 +`endif 7.1870 + ; 7.1871 + 7.1872 +assign stall_m = (stall_wb_load == `TRUE) 7.1873 +`ifdef CFG_SIZE_OVER_SPEED 7.1874 + || (D_CYC_O == `TRUE) 7.1875 +`else 7.1876 + || ( (D_CYC_O == `TRUE) 7.1877 + && ( (store_m == `TRUE) 7.1878 + /* 7.1879 + Bug: Following loop does not allow interrupts to be services since 7.1880 + either D_CYC_O or store_m is always high during entire duration of 7.1881 + loop. 7.1882 + L1: addi r1, r1, 1 7.1883 + sw (r2,0), r1 7.1884 + bi L1 7.1885 + 7.1886 + Introduce a single-cycle stall when a wishbone cycle is in progress 7.1887 + and a new store instruction is in Execute stage and a interrupt 7.1888 + exception has occured. This stall will ensure that D_CYC_O and 7.1889 + store_m will both be low for one cycle. 7.1890 + */ 7.1891 + || ((store_x == `TRUE) && (interrupt_exception == `TRUE)) 7.1892 + || (load_m == `TRUE) 7.1893 + || (load_x == `TRUE) 7.1894 + ) 7.1895 + ) 7.1896 +`endif 7.1897 +`ifdef CFG_DCACHE_ENABLED 7.1898 + || (dcache_stall_request == `TRUE) // Need to stall in case a taken branch is in M stage and data cache is only being flush, so wont be restarted 7.1899 +`endif 7.1900 +`ifdef CFG_ICACHE_ENABLED 7.1901 + || (icache_stall_request == `TRUE) // Pipeline needs to be stalled otherwise branches may be lost 7.1902 + || ((I_CYC_O == `TRUE) && ((branch_m == `TRUE) || (exception_m == `TRUE))) 7.1903 +`else 7.1904 +`ifdef CFG_IWB_ENABLED 7.1905 + || (I_CYC_O == `TRUE) 7.1906 +`endif 7.1907 +`endif 7.1908 +`ifdef CFG_USER_ENABLED 7.1909 + || ( (user_valid == `TRUE) // Stall whole pipeline, rather than just X stage, where the instruction is, so we don't have to worry about exceptions (maybe) 7.1910 + && (user_complete == `FALSE) 7.1911 + ) 7.1912 +`endif 7.1913 + ; 7.1914 + 7.1915 +// Qualify state changing control signals 7.1916 +`ifdef LM32_MC_ARITHMETIC_ENABLED 7.1917 +assign q_d = (valid_d == `TRUE) && (kill_d == `FALSE); 7.1918 +`endif 7.1919 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED 7.1920 +assign shift_left_q_d = (shift_left_d == `TRUE) && (q_d == `TRUE); 7.1921 +assign shift_right_q_d = (shift_right_d == `TRUE) && (q_d == `TRUE); 7.1922 +`endif 7.1923 +`ifdef CFG_MC_MULTIPLY_ENABLED 7.1924 +assign multiply_q_d = (multiply_d == `TRUE) && (q_d == `TRUE); 7.1925 +`endif 7.1926 +`ifdef CFG_MC_DIVIDE_ENABLED 7.1927 +assign divide_q_d = (divide_d == `TRUE) && (q_d == `TRUE); 7.1928 +assign modulus_q_d = (modulus_d == `TRUE) && (q_d == `TRUE); 7.1929 +`endif 7.1930 +assign q_x = (valid_x == `TRUE) && (kill_x == `FALSE); 7.1931 +assign csr_write_enable_q_x = (csr_write_enable_x == `TRUE) && (q_x == `TRUE); 7.1932 +assign eret_q_x = (eret_x == `TRUE) && (q_x == `TRUE); 7.1933 +`ifdef CFG_DEBUG_ENABLED 7.1934 +assign bret_q_x = (bret_x == `TRUE) && (q_x == `TRUE); 7.1935 +`endif 7.1936 +assign load_q_x = (load_x == `TRUE) 7.1937 + && (q_x == `TRUE) 7.1938 +`ifdef CFG_DEBUG_ENABLED 7.1939 + && (bp_match == `FALSE) 7.1940 +`endif 7.1941 + ; 7.1942 +assign store_q_x = (store_x == `TRUE) 7.1943 + && (q_x == `TRUE) 7.1944 +`ifdef CFG_DEBUG_ENABLED 7.1945 + && (bp_match == `FALSE) 7.1946 +`endif 7.1947 + ; 7.1948 +`ifdef CFG_USER_ENABLED 7.1949 +assign user_valid = (x_result_sel_user_x == `TRUE) && (q_x == `TRUE); 7.1950 +`endif 7.1951 +assign q_m = (valid_m == `TRUE) && (kill_m == `FALSE) && (exception_m == `FALSE); 7.1952 +assign load_q_m = (load_m == `TRUE) && (q_m == `TRUE); 7.1953 +assign store_q_m = (store_m == `TRUE) && (q_m == `TRUE); 7.1954 +`ifdef CFG_DEBUG_ENABLED 7.1955 +assign debug_exception_q_w = ((debug_exception_w == `TRUE) && (valid_w == `TRUE)); 7.1956 +assign non_debug_exception_q_w = ((non_debug_exception_w == `TRUE) && (valid_w == `TRUE)); 7.1957 +`else 7.1958 +assign exception_q_w = ((exception_w == `TRUE) && (valid_w == `TRUE)); 7.1959 +`endif 7.1960 +// Don't qualify register write enables with kill, as the signal is needed early, and it doesn't matter if the instruction is killed (except for the actual write - but that is handled separately) 7.1961 +assign write_enable_q_x = (write_enable_x == `TRUE) && (valid_x == `TRUE) && (branch_flushX_m == `FALSE); 7.1962 +assign write_enable_q_m = (write_enable_m == `TRUE) && (valid_m == `TRUE); 7.1963 +assign write_enable_q_w = (write_enable_w == `TRUE) && (valid_w == `TRUE); 7.1964 +// The enable that actually does write the registers needs to be qualified with kill 7.1965 +assign reg_write_enable_q_w = (write_enable_w == `TRUE) && (kill_w == `FALSE) && (valid_w == `TRUE); 7.1966 + 7.1967 +// Configuration (CFG) CSR 7.1968 +assign cfg = { 7.1969 + `LM32_REVISION, 7.1970 + watchpoints[3:0], 7.1971 + breakpoints[3:0], 7.1972 + interrupts[5:0], 7.1973 +`ifdef CFG_JTAG_UART_ENABLED 7.1974 + `TRUE, 7.1975 +`else 7.1976 + `FALSE, 7.1977 +`endif 7.1978 +`ifdef CFG_ROM_DEBUG_ENABLED 7.1979 + `TRUE, 7.1980 +`else 7.1981 + `FALSE, 7.1982 +`endif 7.1983 +`ifdef CFG_HW_DEBUG_ENABLED 7.1984 + `TRUE, 7.1985 +`else 7.1986 + `FALSE, 7.1987 +`endif 7.1988 +`ifdef CFG_DEBUG_ENABLED 7.1989 + `TRUE, 7.1990 +`else 7.1991 + `FALSE, 7.1992 +`endif 7.1993 +`ifdef CFG_ICACHE_ENABLED 7.1994 + `TRUE, 7.1995 +`else 7.1996 + `FALSE, 7.1997 +`endif 7.1998 +`ifdef CFG_DCACHE_ENABLED 7.1999 + `TRUE, 7.2000 +`else 7.2001 + `FALSE, 7.2002 +`endif 7.2003 +`ifdef CFG_CYCLE_COUNTER_ENABLED 7.2004 + `TRUE, 7.2005 +`else 7.2006 + `FALSE, 7.2007 +`endif 7.2008 +`ifdef CFG_USER_ENABLED 7.2009 + `TRUE, 7.2010 +`else 7.2011 + `FALSE, 7.2012 +`endif 7.2013 +`ifdef CFG_SIGN_EXTEND_ENABLED 7.2014 + `TRUE, 7.2015 +`else 7.2016 + `FALSE, 7.2017 +`endif 7.2018 +`ifdef LM32_BARREL_SHIFT_ENABLED 7.2019 + `TRUE, 7.2020 +`else 7.2021 + `FALSE, 7.2022 +`endif 7.2023 +`ifdef CFG_MC_DIVIDE_ENABLED 7.2024 + `TRUE, 7.2025 +`else 7.2026 + `FALSE, 7.2027 +`endif 7.2028 +`ifdef LM32_MULTIPLY_ENABLED 7.2029 + `TRUE 7.2030 +`else 7.2031 + `FALSE 7.2032 +`endif 7.2033 + }; 7.2034 + 7.2035 +assign cfg2 = { 7.2036 + 30'b0, 7.2037 +`ifdef CFG_IROM_ENABLED 7.2038 + `TRUE, 7.2039 +`else 7.2040 + `FALSE, 7.2041 +`endif 7.2042 +`ifdef CFG_DRAM_ENABLED 7.2043 + `TRUE 7.2044 +`else 7.2045 + `FALSE 7.2046 +`endif 7.2047 + }; 7.2048 + 7.2049 +// Cache flush 7.2050 +`ifdef CFG_ICACHE_ENABLED 7.2051 +assign iflush = (csr_write_enable_d == `TRUE) 7.2052 + && (csr_d == `LM32_CSR_ICC) 7.2053 + && (stall_d == `FALSE) 7.2054 + && (kill_d == `FALSE) 7.2055 + && (valid_d == `TRUE); 7.2056 +`endif 7.2057 +`ifdef CFG_DCACHE_ENABLED 7.2058 +assign dflush_x = (csr_write_enable_q_x == `TRUE) 7.2059 + && (csr_x == `LM32_CSR_DCC); 7.2060 +`endif 7.2061 + 7.2062 +// Extract CSR index 7.2063 +assign csr_d = read_idx_0_d[`LM32_CSR_RNG]; 7.2064 + 7.2065 +// CSR reads 7.2066 +always @(*) 7.2067 +begin 7.2068 + case (csr_x) 7.2069 +`ifdef CFG_INTERRUPTS_ENABLED 7.2070 + `LM32_CSR_IE, 7.2071 + `LM32_CSR_IM, 7.2072 + `LM32_CSR_IP: csr_read_data_x = interrupt_csr_read_data_x; 7.2073 +`endif 7.2074 +`ifdef CFG_CYCLE_COUNTER_ENABLED 7.2075 + `LM32_CSR_CC: csr_read_data_x = cc; 7.2076 +`endif 7.2077 + `LM32_CSR_CFG: csr_read_data_x = cfg; 7.2078 + `LM32_CSR_EBA: csr_read_data_x = {eba, 8'h00}; 7.2079 +`ifdef CFG_DEBUG_ENABLED 7.2080 + `LM32_CSR_DEBA: csr_read_data_x = {deba, 8'h00}; 7.2081 +`endif 7.2082 +`ifdef CFG_JTAG_UART_ENABLED 7.2083 + `LM32_CSR_JTX: csr_read_data_x = jtx_csr_read_data; 7.2084 + `LM32_CSR_JRX: csr_read_data_x = jrx_csr_read_data; 7.2085 +`endif 7.2086 + `LM32_CSR_CFG2: csr_read_data_x = cfg2; 7.2087 + 7.2088 + default: csr_read_data_x = {`LM32_WORD_WIDTH{1'bx}}; 7.2089 + endcase 7.2090 +end 7.2091 + 7.2092 +///////////////////////////////////////////////////// 7.2093 +// Sequential Logic 7.2094 +///////////////////////////////////////////////////// 7.2095 + 7.2096 +// Exception Base Address (EBA) CSR 7.2097 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 7.2098 +begin 7.2099 + if (rst_i == `TRUE) 7.2100 + eba <= eba_reset[`LM32_PC_WIDTH+2-1:8]; 7.2101 + else 7.2102 + begin 7.2103 + if ((csr_write_enable_q_x == `TRUE) && (csr_x == `LM32_CSR_EBA) && (stall_x == `FALSE)) 7.2104 + eba <= operand_1_x[`LM32_PC_WIDTH+2-1:8]; 7.2105 +`ifdef CFG_HW_DEBUG_ENABLED 7.2106 + if ((jtag_csr_write_enable == `TRUE) && (jtag_csr == `LM32_CSR_EBA)) 7.2107 + eba <= jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8]; 7.2108 +`endif 7.2109 + end 7.2110 +end 7.2111 + 7.2112 +`ifdef CFG_DEBUG_ENABLED 7.2113 +// Debug Exception Base Address (DEBA) CSR 7.2114 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 7.2115 +begin 7.2116 + if (rst_i == `TRUE) 7.2117 + deba <= deba_reset[`LM32_PC_WIDTH+2-1:8]; 7.2118 + else 7.2119 + begin 7.2120 + if ((csr_write_enable_q_x == `TRUE) && (csr_x == `LM32_CSR_DEBA) && (stall_x == `FALSE)) 7.2121 + deba <= operand_1_x[`LM32_PC_WIDTH+2-1:8]; 7.2122 +`ifdef CFG_HW_DEBUG_ENABLED 7.2123 + if ((jtag_csr_write_enable == `TRUE) && (jtag_csr == `LM32_CSR_DEBA)) 7.2124 + deba <= jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8]; 7.2125 +`endif 7.2126 + end 7.2127 +end 7.2128 +`endif 7.2129 + 7.2130 +// Cycle Counter (CC) CSR 7.2131 +`ifdef CFG_CYCLE_COUNTER_ENABLED 7.2132 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 7.2133 +begin 7.2134 + if (rst_i == `TRUE) 7.2135 + cc <= {`LM32_WORD_WIDTH{1'b0}}; 7.2136 + else 7.2137 + cc <= cc + 1'b1; 7.2138 +end 7.2139 +`endif 7.2140 + 7.2141 +`ifdef CFG_BUS_ERRORS_ENABLED 7.2142 +// Watch for data bus errors 7.2143 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 7.2144 +begin 7.2145 + if (rst_i == `TRUE) 7.2146 + data_bus_error_seen <= `FALSE; 7.2147 + else 7.2148 + begin 7.2149 + // Set flag when bus error is detected 7.2150 + if ((D_ERR_I == `TRUE) && (D_CYC_O == `TRUE)) 7.2151 + data_bus_error_seen <= `TRUE; 7.2152 + // Clear flag when exception is taken 7.2153 + if ((exception_m == `TRUE) && (kill_m == `FALSE)) 7.2154 + data_bus_error_seen <= `FALSE; 7.2155 + end 7.2156 +end 7.2157 +`endif 7.2158 + 7.2159 +// Valid bits to indicate whether an instruction in a partcular pipeline stage is valid or not 7.2160 + 7.2161 +`ifdef CFG_ICACHE_ENABLED 7.2162 +`ifdef CFG_DCACHE_ENABLED 7.2163 +always @(*) 7.2164 +begin 7.2165 + if ( (icache_refill_request == `TRUE) 7.2166 + || (dcache_refill_request == `TRUE) 7.2167 + ) 7.2168 + valid_a = `FALSE; 7.2169 + else if ( (icache_restart_request == `TRUE) 7.2170 + || (dcache_restart_request == `TRUE) 7.2171 + ) 7.2172 + valid_a = `TRUE; 7.2173 + else 7.2174 + valid_a = !icache_refilling && !dcache_refilling; 7.2175 +end 7.2176 +`else 7.2177 +always @(*) 7.2178 +begin 7.2179 + if (icache_refill_request == `TRUE) 7.2180 + valid_a = `FALSE; 7.2181 + else if (icache_restart_request == `TRUE) 7.2182 + valid_a = `TRUE; 7.2183 + else 7.2184 + valid_a = !icache_refilling; 7.2185 +end 7.2186 +`endif 7.2187 +`else 7.2188 +`ifdef CFG_DCACHE_ENABLED 7.2189 +always @(*) 7.2190 +begin 7.2191 + if (dcache_refill_request == `TRUE) 7.2192 + valid_a = `FALSE; 7.2193 + else if (dcache_restart_request == `TRUE) 7.2194 + valid_a = `TRUE; 7.2195 + else 7.2196 + valid_a = !dcache_refilling; 7.2197 +end 7.2198 +`endif 7.2199 +`endif 7.2200 + 7.2201 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 7.2202 +begin 7.2203 + if (rst_i == `TRUE) 7.2204 + begin 7.2205 + valid_f <= `FALSE; 7.2206 + valid_d <= `FALSE; 7.2207 + valid_x <= `FALSE; 7.2208 + valid_m <= `FALSE; 7.2209 + valid_w <= `FALSE; 7.2210 + end 7.2211 + else 7.2212 + begin 7.2213 + if ((kill_f == `TRUE) || (stall_a == `FALSE)) 7.2214 +`ifdef LM32_CACHE_ENABLED 7.2215 + valid_f <= valid_a; 7.2216 +`else 7.2217 + valid_f <= `TRUE; 7.2218 +`endif 7.2219 + else if (stall_f == `FALSE) 7.2220 + valid_f <= `FALSE; 7.2221 + 7.2222 + if (kill_d == `TRUE) 7.2223 + valid_d <= `FALSE; 7.2224 + else if (stall_f == `FALSE) 7.2225 + valid_d <= valid_f & !kill_f; 7.2226 + else if (stall_d == `FALSE) 7.2227 + valid_d <= `FALSE; 7.2228 + 7.2229 + if (stall_d == `FALSE) 7.2230 + valid_x <= valid_d & !kill_d; 7.2231 + else if (kill_x == `TRUE) 7.2232 + valid_x <= `FALSE; 7.2233 + else if (stall_x == `FALSE) 7.2234 + valid_x <= `FALSE; 7.2235 + 7.2236 + if (kill_m == `TRUE) 7.2237 + valid_m <= `FALSE; 7.2238 + else if (stall_x == `FALSE) 7.2239 + valid_m <= valid_x & !kill_x; 7.2240 + else if (stall_m == `FALSE) 7.2241 + valid_m <= `FALSE; 7.2242 + 7.2243 + if (stall_m == `FALSE) 7.2244 + valid_w <= valid_m & !kill_m; 7.2245 + else 7.2246 + valid_w <= `FALSE; 7.2247 + end 7.2248 +end 7.2249 + 7.2250 +// Microcode pipeline registers 7.2251 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 7.2252 +begin 7.2253 + if (rst_i == `TRUE) 7.2254 + begin 7.2255 +`ifdef CFG_USER_ENABLED 7.2256 + user_opcode <= {`LM32_USER_OPCODE_WIDTH{1'b0}}; 7.2257 +`endif 7.2258 + operand_0_x <= {`LM32_WORD_WIDTH{1'b0}}; 7.2259 + operand_1_x <= {`LM32_WORD_WIDTH{1'b0}}; 7.2260 + store_operand_x <= {`LM32_WORD_WIDTH{1'b0}}; 7.2261 + branch_target_x <= {`LM32_WORD_WIDTH{1'b0}}; 7.2262 + x_result_sel_csr_x <= `FALSE; 7.2263 +`ifdef LM32_MC_ARITHMETIC_ENABLED 7.2264 + x_result_sel_mc_arith_x <= `FALSE; 7.2265 +`endif 7.2266 +`ifdef LM32_NO_BARREL_SHIFT 7.2267 + x_result_sel_shift_x <= `FALSE; 7.2268 +`endif 7.2269 +`ifdef CFG_SIGN_EXTEND_ENABLED 7.2270 + x_result_sel_sext_x <= `FALSE; 7.2271 +`endif 7.2272 + x_result_sel_logic_x <= `FALSE; 7.2273 +`ifdef CFG_USER_ENABLED 7.2274 + x_result_sel_user_x <= `FALSE; 7.2275 +`endif 7.2276 + x_result_sel_add_x <= `FALSE; 7.2277 + m_result_sel_compare_x <= `FALSE; 7.2278 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 7.2279 + m_result_sel_shift_x <= `FALSE; 7.2280 +`endif 7.2281 + w_result_sel_load_x <= `FALSE; 7.2282 +`ifdef CFG_PL_MULTIPLY_ENABLED 7.2283 + w_result_sel_mul_x <= `FALSE; 7.2284 +`endif 7.2285 + x_bypass_enable_x <= `FALSE; 7.2286 + m_bypass_enable_x <= `FALSE; 7.2287 + write_enable_x <= `FALSE; 7.2288 + write_idx_x <= {`LM32_REG_IDX_WIDTH{1'b0}}; 7.2289 + csr_x <= {`LM32_CSR_WIDTH{1'b0}}; 7.2290 + load_x <= `FALSE; 7.2291 + store_x <= `FALSE; 7.2292 + size_x <= {`LM32_SIZE_WIDTH{1'b0}}; 7.2293 + sign_extend_x <= `FALSE; 7.2294 + adder_op_x <= `FALSE; 7.2295 + adder_op_x_n <= `FALSE; 7.2296 + logic_op_x <= 4'h0; 7.2297 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 7.2298 + direction_x <= `FALSE; 7.2299 +`endif 7.2300 +`ifdef CFG_ROTATE_ENABLED 7.2301 + rotate_x <= `FALSE; 7.2302 + 7.2303 +`endif 7.2304 + branch_x <= `FALSE; 7.2305 + branch_predict_x <= `FALSE; 7.2306 + branch_predict_taken_x <= `FALSE; 7.2307 + condition_x <= `LM32_CONDITION_U1; 7.2308 +`ifdef CFG_DEBUG_ENABLED 7.2309 + break_x <= `FALSE; 7.2310 +`endif 7.2311 + scall_x <= `FALSE; 7.2312 + eret_x <= `FALSE; 7.2313 +`ifdef CFG_DEBUG_ENABLED 7.2314 + bret_x <= `FALSE; 7.2315 +`endif 7.2316 +`ifdef CFG_BUS_ERRORS_ENABLED 7.2317 + bus_error_x <= `FALSE; 7.2318 + data_bus_error_exception_m <= `FALSE; 7.2319 +`endif 7.2320 + csr_write_enable_x <= `FALSE; 7.2321 + operand_m <= {`LM32_WORD_WIDTH{1'b0}}; 7.2322 + branch_target_m <= {`LM32_WORD_WIDTH{1'b0}}; 7.2323 + m_result_sel_compare_m <= `FALSE; 7.2324 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 7.2325 + m_result_sel_shift_m <= `FALSE; 7.2326 +`endif 7.2327 + w_result_sel_load_m <= `FALSE; 7.2328 +`ifdef CFG_PL_MULTIPLY_ENABLED 7.2329 + w_result_sel_mul_m <= `FALSE; 7.2330 +`endif 7.2331 + m_bypass_enable_m <= `FALSE; 7.2332 + branch_m <= `FALSE; 7.2333 + branch_predict_m <= `FALSE; 7.2334 + branch_predict_taken_m <= `FALSE; 7.2335 + exception_m <= `FALSE; 7.2336 + load_m <= `FALSE; 7.2337 + store_m <= `FALSE; 7.2338 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 7.2339 + direction_m <= `FALSE; 7.2340 +`endif 7.2341 + write_enable_m <= `FALSE; 7.2342 + write_idx_m <= {`LM32_REG_IDX_WIDTH{1'b0}}; 7.2343 + condition_met_m <= `FALSE; 7.2344 +`ifdef CFG_DCACHE_ENABLED 7.2345 + dflush_m <= `FALSE; 7.2346 +`endif 7.2347 +`ifdef CFG_DEBUG_ENABLED 7.2348 + debug_exception_m <= `FALSE; 7.2349 + non_debug_exception_m <= `FALSE; 7.2350 +`endif 7.2351 + operand_w <= {`LM32_WORD_WIDTH{1'b0}}; 7.2352 + w_result_sel_load_w <= `FALSE; 7.2353 +`ifdef CFG_PL_MULTIPLY_ENABLED 7.2354 + w_result_sel_mul_w <= `FALSE; 7.2355 +`endif 7.2356 + write_idx_w <= {`LM32_REG_IDX_WIDTH{1'b0}}; 7.2357 + write_enable_w <= `FALSE; 7.2358 +`ifdef CFG_DEBUG_ENABLED 7.2359 + debug_exception_w <= `FALSE; 7.2360 + non_debug_exception_w <= `FALSE; 7.2361 +`else 7.2362 + exception_w <= `FALSE; 7.2363 +`endif 7.2364 +`ifdef CFG_BUS_ERRORS_ENABLED 7.2365 + memop_pc_w <= {`LM32_PC_WIDTH{1'b0}}; 7.2366 +`endif 7.2367 + end 7.2368 + else 7.2369 + begin 7.2370 + // D/X stage registers 7.2371 + 7.2372 + if (stall_x == `FALSE) 7.2373 + begin 7.2374 +`ifdef CFG_USER_ENABLED 7.2375 + user_opcode <= user_opcode_d; 7.2376 +`endif 7.2377 + operand_0_x <= d_result_0; 7.2378 + operand_1_x <= d_result_1; 7.2379 + store_operand_x <= bypass_data_1; 7.2380 + branch_target_x <= branch_reg_d == `TRUE ? bypass_data_0[`LM32_PC_RNG] : branch_target_d; 7.2381 + x_result_sel_csr_x <= x_result_sel_csr_d; 7.2382 +`ifdef LM32_MC_ARITHMETIC_ENABLED 7.2383 + x_result_sel_mc_arith_x <= x_result_sel_mc_arith_d; 7.2384 +`endif 7.2385 +`ifdef LM32_NO_BARREL_SHIFT 7.2386 + x_result_sel_shift_x <= x_result_sel_shift_d; 7.2387 +`endif 7.2388 +`ifdef CFG_SIGN_EXTEND_ENABLED 7.2389 + x_result_sel_sext_x <= x_result_sel_sext_d; 7.2390 +`endif 7.2391 + x_result_sel_logic_x <= x_result_sel_logic_d; 7.2392 +`ifdef CFG_USER_ENABLED 7.2393 + x_result_sel_user_x <= x_result_sel_user_d; 7.2394 +`endif 7.2395 + x_result_sel_add_x <= x_result_sel_add_d; 7.2396 + m_result_sel_compare_x <= m_result_sel_compare_d; 7.2397 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 7.2398 + m_result_sel_shift_x <= m_result_sel_shift_d; 7.2399 +`endif 7.2400 + w_result_sel_load_x <= w_result_sel_load_d; 7.2401 +`ifdef CFG_PL_MULTIPLY_ENABLED 7.2402 + w_result_sel_mul_x <= w_result_sel_mul_d; 7.2403 +`endif 7.2404 + x_bypass_enable_x <= x_bypass_enable_d; 7.2405 + m_bypass_enable_x <= m_bypass_enable_d; 7.2406 + load_x <= load_d; 7.2407 + store_x <= store_d; 7.2408 + branch_x <= branch_d; 7.2409 + branch_predict_x <= branch_predict_d; 7.2410 + branch_predict_taken_x <= branch_predict_taken_d; 7.2411 + write_idx_x <= write_idx_d; 7.2412 + csr_x <= csr_d; 7.2413 + size_x <= size_d; 7.2414 + sign_extend_x <= sign_extend_d; 7.2415 + adder_op_x <= adder_op_d; 7.2416 + adder_op_x_n <= ~adder_op_d; 7.2417 + logic_op_x <= logic_op_d; 7.2418 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 7.2419 + direction_x <= direction_d; 7.2420 +`endif 7.2421 +`ifdef CFG_ROTATE_ENABLED 7.2422 + rotate_x <= rotate_d; 7.2423 +`endif 7.2424 + condition_x <= condition_d; 7.2425 + csr_write_enable_x <= csr_write_enable_d; 7.2426 +`ifdef CFG_DEBUG_ENABLED 7.2427 + break_x <= break_d; 7.2428 +`endif 7.2429 + scall_x <= scall_d; 7.2430 +`ifdef CFG_BUS_ERRORS_ENABLED 7.2431 + bus_error_x <= bus_error_d; 7.2432 +`endif 7.2433 + eret_x <= eret_d; 7.2434 +`ifdef CFG_DEBUG_ENABLED 7.2435 + bret_x <= bret_d; 7.2436 +`endif 7.2437 + write_enable_x <= write_enable_d; 7.2438 + end 7.2439 + 7.2440 + // X/M stage registers 7.2441 + 7.2442 + if (stall_m == `FALSE) 7.2443 + begin 7.2444 + operand_m <= x_result; 7.2445 + m_result_sel_compare_m <= m_result_sel_compare_x; 7.2446 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 7.2447 + m_result_sel_shift_m <= m_result_sel_shift_x; 7.2448 +`endif 7.2449 + if (exception_x == `TRUE) 7.2450 + begin 7.2451 + w_result_sel_load_m <= `FALSE; 7.2452 +`ifdef CFG_PL_MULTIPLY_ENABLED 7.2453 + w_result_sel_mul_m <= `FALSE; 7.2454 +`endif 7.2455 + end 7.2456 + else 7.2457 + begin 7.2458 + w_result_sel_load_m <= w_result_sel_load_x; 7.2459 +`ifdef CFG_PL_MULTIPLY_ENABLED 7.2460 + w_result_sel_mul_m <= w_result_sel_mul_x; 7.2461 +`endif 7.2462 + end 7.2463 + m_bypass_enable_m <= m_bypass_enable_x; 7.2464 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 7.2465 + direction_m <= direction_x; 7.2466 +`endif 7.2467 + load_m <= load_x; 7.2468 + store_m <= store_x; 7.2469 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH 7.2470 + branch_m <= branch_x && !branch_taken_x; 7.2471 +`else 7.2472 + branch_m <= branch_x; 7.2473 + branch_predict_m <= branch_predict_x; 7.2474 + branch_predict_taken_m <= branch_predict_taken_x; 7.2475 +`endif 7.2476 +`ifdef CFG_DEBUG_ENABLED 7.2477 + // Data bus errors are generated by the wishbone and are 7.2478 + // made known to the processor only in next cycle (as a 7.2479 + // non-debug exception). A break instruction can be seen 7.2480 + // in same cycle (causing a debug exception). Handle non 7.2481 + // -debug exception first! 7.2482 + if (non_debug_exception_x == `TRUE) 7.2483 + write_idx_m <= `LM32_EA_REG; 7.2484 + else if (debug_exception_x == `TRUE) 7.2485 + write_idx_m <= `LM32_BA_REG; 7.2486 + else 7.2487 + write_idx_m <= write_idx_x; 7.2488 +`else 7.2489 + if (exception_x == `TRUE) 7.2490 + write_idx_m <= `LM32_EA_REG; 7.2491 + else 7.2492 + write_idx_m <= write_idx_x; 7.2493 +`endif 7.2494 + condition_met_m <= condition_met_x; 7.2495 +`ifdef CFG_DEBUG_ENABLED 7.2496 + if (exception_x == `TRUE) 7.2497 + if ((dc_re == `TRUE) 7.2498 + || ((debug_exception_x == `TRUE) 7.2499 + && (non_debug_exception_x == `FALSE))) 7.2500 + branch_target_m <= {deba, eid_x, {3{1'b0}}}; 7.2501 + else 7.2502 + branch_target_m <= {eba, eid_x, {3{1'b0}}}; 7.2503 + else 7.2504 + branch_target_m <= branch_target_x; 7.2505 +`else 7.2506 + branch_target_m <= exception_x == `TRUE ? {eba, eid_x, {3{1'b0}}} : branch_target_x; 7.2507 +`endif 7.2508 +`ifdef CFG_TRACE_ENABLED 7.2509 + eid_m <= eid_x; 7.2510 +`endif 7.2511 +`ifdef CFG_DCACHE_ENABLED 7.2512 + dflush_m <= dflush_x; 7.2513 +`endif 7.2514 + eret_m <= eret_q_x; 7.2515 +`ifdef CFG_DEBUG_ENABLED 7.2516 + bret_m <= bret_q_x; 7.2517 +`endif 7.2518 + write_enable_m <= exception_x == `TRUE ? `TRUE : write_enable_x; 7.2519 +`ifdef CFG_DEBUG_ENABLED 7.2520 + debug_exception_m <= debug_exception_x; 7.2521 + non_debug_exception_m <= non_debug_exception_x; 7.2522 +`endif 7.2523 + end 7.2524 + 7.2525 + // State changing regs 7.2526 + if (stall_m == `FALSE) 7.2527 + begin 7.2528 + if ((exception_x == `TRUE) && (q_x == `TRUE) && (stall_x == `FALSE)) 7.2529 + exception_m <= `TRUE; 7.2530 + else 7.2531 + exception_m <= `FALSE; 7.2532 +`ifdef CFG_BUS_ERRORS_ENABLED 7.2533 + data_bus_error_exception_m <= (data_bus_error_exception == `TRUE) 7.2534 +`ifdef CFG_DEBUG_ENABLED 7.2535 + && (reset_exception == `FALSE) 7.2536 +`endif 7.2537 + ; 7.2538 +`endif 7.2539 + end 7.2540 + 7.2541 + // M/W stage registers 7.2542 +`ifdef CFG_BUS_ERRORS_ENABLED 7.2543 + operand_w <= exception_m == `TRUE ? (data_bus_error_exception_m ? {memop_pc_w, 2'b00} : {pc_m, 2'b00}) : m_result; 7.2544 +`else 7.2545 + operand_w <= exception_m == `TRUE ? {pc_m, 2'b00} : m_result; 7.2546 +`endif 7.2547 + w_result_sel_load_w <= w_result_sel_load_m; 7.2548 +`ifdef CFG_PL_MULTIPLY_ENABLED 7.2549 + w_result_sel_mul_w <= w_result_sel_mul_m; 7.2550 +`endif 7.2551 + write_idx_w <= write_idx_m; 7.2552 +`ifdef CFG_TRACE_ENABLED 7.2553 + eid_w <= eid_m; 7.2554 + eret_w <= eret_m; 7.2555 +`ifdef CFG_DEBUG_ENABLED 7.2556 + bret_w <= bret_m; 7.2557 +`endif 7.2558 +`endif 7.2559 + write_enable_w <= write_enable_m; 7.2560 +`ifdef CFG_DEBUG_ENABLED 7.2561 + debug_exception_w <= debug_exception_m; 7.2562 + non_debug_exception_w <= non_debug_exception_m; 7.2563 +`else 7.2564 + exception_w <= exception_m; 7.2565 +`endif 7.2566 +`ifdef CFG_BUS_ERRORS_ENABLED 7.2567 + if ( (stall_m == `FALSE) 7.2568 + && ( (load_q_m == `TRUE) 7.2569 + || (store_q_m == `TRUE) 7.2570 + ) 7.2571 + ) 7.2572 + memop_pc_w <= pc_m; 7.2573 +`endif 7.2574 + end 7.2575 +end 7.2576 + 7.2577 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE 7.2578 +// Buffer data read from register file, in case a stall occurs, and watch for 7.2579 +// any writes to the modified registers 7.2580 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 7.2581 +begin 7.2582 + if (rst_i == `TRUE) 7.2583 + begin 7.2584 + use_buf <= `FALSE; 7.2585 + reg_data_buf_0 <= {`LM32_WORD_WIDTH{1'b0}}; 7.2586 + reg_data_buf_1 <= {`LM32_WORD_WIDTH{1'b0}}; 7.2587 + end 7.2588 + else 7.2589 + begin 7.2590 + if (stall_d == `FALSE) 7.2591 + use_buf <= `FALSE; 7.2592 + else if (use_buf == `FALSE) 7.2593 + begin 7.2594 + reg_data_buf_0 <= reg_data_live_0; 7.2595 + reg_data_buf_1 <= reg_data_live_1; 7.2596 + use_buf <= `TRUE; 7.2597 + end 7.2598 + if (reg_write_enable_q_w == `TRUE) 7.2599 + begin 7.2600 + if (write_idx_w == read_idx_0_d) 7.2601 + reg_data_buf_0 <= w_result; 7.2602 + if (write_idx_w == read_idx_1_d) 7.2603 + reg_data_buf_1 <= w_result; 7.2604 + end 7.2605 + end 7.2606 +end 7.2607 +`endif 7.2608 + 7.2609 +`ifdef LM32_EBR_REGISTER_FILE 7.2610 +`else 7.2611 +// Register file write port 7.2612 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 7.2613 +begin 7.2614 + if (rst_i == `TRUE) begin 7.2615 + registers[0] <= {`LM32_WORD_WIDTH{1'b0}}; 7.2616 + registers[1] <= {`LM32_WORD_WIDTH{1'b0}}; 7.2617 + registers[2] <= {`LM32_WORD_WIDTH{1'b0}}; 7.2618 + registers[3] <= {`LM32_WORD_WIDTH{1'b0}}; 7.2619 + registers[4] <= {`LM32_WORD_WIDTH{1'b0}}; 7.2620 + registers[5] <= {`LM32_WORD_WIDTH{1'b0}}; 7.2621 + registers[6] <= {`LM32_WORD_WIDTH{1'b0}}; 7.2622 + registers[7] <= {`LM32_WORD_WIDTH{1'b0}}; 7.2623 + registers[8] <= {`LM32_WORD_WIDTH{1'b0}}; 7.2624 + registers[9] <= {`LM32_WORD_WIDTH{1'b0}}; 7.2625 + registers[10] <= {`LM32_WORD_WIDTH{1'b0}}; 7.2626 + registers[11] <= {`LM32_WORD_WIDTH{1'b0}}; 7.2627 + registers[12] <= {`LM32_WORD_WIDTH{1'b0}}; 7.2628 + registers[13] <= {`LM32_WORD_WIDTH{1'b0}}; 7.2629 + registers[14] <= {`LM32_WORD_WIDTH{1'b0}}; 7.2630 + registers[15] <= {`LM32_WORD_WIDTH{1'b0}}; 7.2631 + registers[16] <= {`LM32_WORD_WIDTH{1'b0}}; 7.2632 + registers[17] <= {`LM32_WORD_WIDTH{1'b0}}; 7.2633 + registers[18] <= {`LM32_WORD_WIDTH{1'b0}}; 7.2634 + registers[19] <= {`LM32_WORD_WIDTH{1'b0}}; 7.2635 + registers[20] <= {`LM32_WORD_WIDTH{1'b0}}; 7.2636 + registers[21] <= {`LM32_WORD_WIDTH{1'b0}}; 7.2637 + registers[22] <= {`LM32_WORD_WIDTH{1'b0}}; 7.2638 + registers[23] <= {`LM32_WORD_WIDTH{1'b0}}; 7.2639 + registers[24] <= {`LM32_WORD_WIDTH{1'b0}}; 7.2640 + registers[25] <= {`LM32_WORD_WIDTH{1'b0}}; 7.2641 + registers[26] <= {`LM32_WORD_WIDTH{1'b0}}; 7.2642 + registers[27] <= {`LM32_WORD_WIDTH{1'b0}}; 7.2643 + registers[28] <= {`LM32_WORD_WIDTH{1'b0}}; 7.2644 + registers[29] <= {`LM32_WORD_WIDTH{1'b0}}; 7.2645 + registers[30] <= {`LM32_WORD_WIDTH{1'b0}}; 7.2646 + registers[31] <= {`LM32_WORD_WIDTH{1'b0}}; 7.2647 + end 7.2648 + else begin 7.2649 + if (reg_write_enable_q_w == `TRUE) 7.2650 + registers[write_idx_w] <= w_result; 7.2651 + end 7.2652 +end 7.2653 +`endif 7.2654 + 7.2655 +`ifdef CFG_TRACE_ENABLED 7.2656 +// PC tracing logic 7.2657 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 7.2658 +begin 7.2659 + if (rst_i == `TRUE) 7.2660 + begin 7.2661 + trace_pc_valid <= `FALSE; 7.2662 + trace_pc <= {`LM32_PC_WIDTH{1'b0}}; 7.2663 + trace_exception <= `FALSE; 7.2664 + trace_eid <= `LM32_EID_RESET; 7.2665 + trace_eret <= `FALSE; 7.2666 +`ifdef CFG_DEBUG_ENABLED 7.2667 + trace_bret <= `FALSE; 7.2668 +`endif 7.2669 + pc_c <= `CFG_EBA_RESET/4; 7.2670 + end 7.2671 + else 7.2672 + begin 7.2673 + trace_pc_valid <= `FALSE; 7.2674 + // Has an exception occured 7.2675 +`ifdef CFG_DEBUG_ENABLED 7.2676 + if ((debug_exception_q_w == `TRUE) || (non_debug_exception_q_w == `TRUE)) 7.2677 +`else 7.2678 + if (exception_q_w == `TRUE) 7.2679 +`endif 7.2680 + begin 7.2681 + trace_exception <= `TRUE; 7.2682 + trace_pc_valid <= `TRUE; 7.2683 + trace_pc <= pc_w; 7.2684 + trace_eid <= eid_w; 7.2685 + end 7.2686 + else 7.2687 + trace_exception <= `FALSE; 7.2688 + 7.2689 + if ((valid_w == `TRUE) && (!kill_w)) 7.2690 + begin 7.2691 + // An instruction is commiting. Determine if it is non-sequential 7.2692 + if (pc_c + 1'b1 != pc_w) 7.2693 + begin 7.2694 + // Non-sequential instruction 7.2695 + trace_pc_valid <= `TRUE; 7.2696 + trace_pc <= pc_w; 7.2697 + end 7.2698 + // Record PC so we can determine if next instruction is sequential or not 7.2699 + pc_c <= pc_w; 7.2700 + // Indicate if it was an eret/bret instruction 7.2701 + trace_eret <= eret_w; 7.2702 +`ifdef CFG_DEBUG_ENABLED 7.2703 + trace_bret <= bret_w; 7.2704 +`endif 7.2705 + end 7.2706 + else 7.2707 + begin 7.2708 + trace_eret <= `FALSE; 7.2709 +`ifdef CFG_DEBUG_ENABLED 7.2710 + trace_bret <= `FALSE; 7.2711 +`endif 7.2712 + end 7.2713 + end 7.2714 +end 7.2715 +`endif 7.2716 + 7.2717 +///////////////////////////////////////////////////// 7.2718 +// Behavioural Logic 7.2719 +///////////////////////////////////////////////////// 7.2720 + 7.2721 +// synthesis translate_off 7.2722 + 7.2723 +// Reset register 0. Only needed for simulation. 7.2724 +initial 7.2725 +begin 7.2726 +`ifdef LM32_EBR_REGISTER_FILE 7.2727 + reg_0.mem[0] = {`LM32_WORD_WIDTH{1'b0}}; 7.2728 + reg_1.mem[0] = {`LM32_WORD_WIDTH{1'b0}}; 7.2729 +`else 7.2730 + registers[0] = {`LM32_WORD_WIDTH{1'b0}}; 7.2731 +`endif 7.2732 +end 7.2733 + 7.2734 +// synthesis translate_on 7.2735 + 7.2736 +endmodule
8.1 diff -r 000000000000 -r cd0b58aa6f83 lm32_dcache.v 8.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 8.3 +++ b/lm32_dcache.v Sun Apr 04 20:40:03 2010 +0100 8.4 @@ -0,0 +1,533 @@ 8.5 +// ============================================================================= 8.6 +// COPYRIGHT NOTICE 8.7 +// Copyright 2006 (c) Lattice Semiconductor Corporation 8.8 +// ALL RIGHTS RESERVED 8.9 +// This confidential and proprietary software may be used only as authorised by 8.10 +// a licensing agreement from Lattice Semiconductor Corporation. 8.11 +// The entire notice above must be reproduced on all authorized copies and 8.12 +// copies may only be made to the extent permitted by a licensing agreement from 8.13 +// Lattice Semiconductor Corporation. 8.14 +// 8.15 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 8.16 +// 5555 NE Moore Court 408-826-6000 (other locations) 8.17 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 8.18 +// U.S.A email: techsupport@latticesemi.com 8.19 +// =============================================================================/ 8.20 +// FILE DETAILS 8.21 +// Project : LatticeMico32 8.22 +// File : lm32_dcache.v 8.23 +// Title : Data cache 8.24 +// Dependencies : lm32_include.v 8.25 +// Version : 6.1.17 8.26 +// : Initial Release 8.27 +// Version : 7.0SP2, 3.0 8.28 +// : No Change 8.29 +// Version : 3.1 8.30 +// : Support for user-selected resource usage when implementing 8.31 +// : cache memory. Additional parameters must be defined when 8.32 +// : invoking lm32_ram.v 8.33 +// ============================================================================= 8.34 + 8.35 +`include "lm32_include.v" 8.36 + 8.37 +`ifdef CFG_DCACHE_ENABLED 8.38 + 8.39 +`define LM32_DC_ADDR_OFFSET_RNG addr_offset_msb:addr_offset_lsb 8.40 +`define LM32_DC_ADDR_SET_RNG addr_set_msb:addr_set_lsb 8.41 +`define LM32_DC_ADDR_TAG_RNG addr_tag_msb:addr_tag_lsb 8.42 +`define LM32_DC_ADDR_IDX_RNG addr_set_msb:addr_offset_lsb 8.43 + 8.44 +`define LM32_DC_TMEM_ADDR_WIDTH addr_set_width 8.45 +`define LM32_DC_TMEM_ADDR_RNG (`LM32_DC_TMEM_ADDR_WIDTH-1):0 8.46 +`define LM32_DC_DMEM_ADDR_WIDTH (addr_offset_width+addr_set_width) 8.47 +`define LM32_DC_DMEM_ADDR_RNG (`LM32_DC_DMEM_ADDR_WIDTH-1):0 8.48 + 8.49 +`define LM32_DC_TAGS_WIDTH (addr_tag_width+1) 8.50 +`define LM32_DC_TAGS_RNG (`LM32_DC_TAGS_WIDTH-1):0 8.51 +`define LM32_DC_TAGS_TAG_RNG (`LM32_DC_TAGS_WIDTH-1):1 8.52 +`define LM32_DC_TAGS_VALID_RNG 0 8.53 + 8.54 +`define LM32_DC_STATE_RNG 2:0 8.55 +`define LM32_DC_STATE_FLUSH 3'b001 8.56 +`define LM32_DC_STATE_CHECK 3'b010 8.57 +`define LM32_DC_STATE_REFILL 3'b100 8.58 + 8.59 +///////////////////////////////////////////////////// 8.60 +// Module interface 8.61 +///////////////////////////////////////////////////// 8.62 + 8.63 +module lm32_dcache ( 8.64 + // ----- Inputs ----- 8.65 + clk_i, 8.66 + rst_i, 8.67 + stall_a, 8.68 + stall_x, 8.69 + stall_m, 8.70 + address_x, 8.71 + address_m, 8.72 + load_q_m, 8.73 + store_q_m, 8.74 + store_data, 8.75 + store_byte_select, 8.76 + refill_ready, 8.77 + refill_data, 8.78 + dflush, 8.79 + // ----- Outputs ----- 8.80 + stall_request, 8.81 + restart_request, 8.82 + refill_request, 8.83 + refill_address, 8.84 + refilling, 8.85 + load_data 8.86 + ); 8.87 + 8.88 +///////////////////////////////////////////////////// 8.89 +// Parameters 8.90 +///////////////////////////////////////////////////// 8.91 + 8.92 +parameter associativity = 1; // Associativity of the cache (Number of ways) 8.93 +parameter sets = 512; // Number of sets 8.94 +parameter bytes_per_line = 16; // Number of bytes per cache line 8.95 +parameter base_address = 0; // Base address of cachable memory 8.96 +parameter limit = 0; // Limit (highest address) of cachable memory 8.97 + 8.98 +localparam addr_offset_width = clogb2(bytes_per_line)-1-2; 8.99 +localparam addr_set_width = clogb2(sets)-1; 8.100 +localparam addr_offset_lsb = 2; 8.101 +localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1); 8.102 +localparam addr_set_lsb = (addr_offset_msb+1); 8.103 +localparam addr_set_msb = (addr_set_lsb+addr_set_width-1); 8.104 +localparam addr_tag_lsb = (addr_set_msb+1); 8.105 +localparam addr_tag_msb = clogb2(`CFG_DCACHE_LIMIT-`CFG_DCACHE_BASE_ADDRESS)-1; 8.106 +localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1); 8.107 + 8.108 +///////////////////////////////////////////////////// 8.109 +// Inputs 8.110 +///////////////////////////////////////////////////// 8.111 + 8.112 +input clk_i; // Clock 8.113 +input rst_i; // Reset 8.114 + 8.115 +input stall_a; // Stall A stage 8.116 +input stall_x; // Stall X stage 8.117 +input stall_m; // Stall M stage 8.118 + 8.119 +input [`LM32_WORD_RNG] address_x; // X stage load/store address 8.120 +input [`LM32_WORD_RNG] address_m; // M stage load/store address 8.121 +input load_q_m; // Load instruction in M stage 8.122 +input store_q_m; // Store instruction in M stage 8.123 +input [`LM32_WORD_RNG] store_data; // Data to store 8.124 +input [`LM32_BYTE_SELECT_RNG] store_byte_select; // Which bytes in store data should be modified 8.125 + 8.126 +input refill_ready; // Indicates next word of refill data is ready 8.127 +input [`LM32_WORD_RNG] refill_data; // Refill data 8.128 + 8.129 +input dflush; // Indicates cache should be flushed 8.130 + 8.131 +///////////////////////////////////////////////////// 8.132 +// Outputs 8.133 +///////////////////////////////////////////////////// 8.134 + 8.135 +output stall_request; // Request pipeline be stalled because cache is busy 8.136 +wire stall_request; 8.137 +output restart_request; // Request to restart instruction that caused the cache miss 8.138 +reg restart_request; 8.139 +output refill_request; // Request a refill 8.140 +reg refill_request; 8.141 +output [`LM32_WORD_RNG] refill_address; // Address to refill from 8.142 +reg [`LM32_WORD_RNG] refill_address; 8.143 +output refilling; // Indicates if the cache is currently refilling 8.144 +reg refilling; 8.145 +output [`LM32_WORD_RNG] load_data; // Data read from cache 8.146 +wire [`LM32_WORD_RNG] load_data; 8.147 + 8.148 +///////////////////////////////////////////////////// 8.149 +// Internal nets and registers 8.150 +///////////////////////////////////////////////////// 8.151 + 8.152 +wire read_port_enable; // Cache memory read port clock enable 8.153 +wire write_port_enable; // Cache memory write port clock enable 8.154 +wire [0:associativity-1] way_tmem_we; // Tag memory write enable 8.155 +wire [0:associativity-1] way_dmem_we; // Data memory write enable 8.156 +wire [`LM32_WORD_RNG] way_data[0:associativity-1]; // Data read from data memory 8.157 +wire [`LM32_DC_TAGS_TAG_RNG] way_tag[0:associativity-1];// Tag read from tag memory 8.158 +wire [0:associativity-1] way_valid; // Indicates which ways are valid 8.159 +wire [0:associativity-1] way_match; // Indicates which ways matched 8.160 +wire miss; // Indicates no ways matched 8.161 + 8.162 +wire [`LM32_DC_TMEM_ADDR_RNG] tmem_read_address; // Tag memory read address 8.163 +wire [`LM32_DC_TMEM_ADDR_RNG] tmem_write_address; // Tag memory write address 8.164 +wire [`LM32_DC_DMEM_ADDR_RNG] dmem_read_address; // Data memory read address 8.165 +wire [`LM32_DC_DMEM_ADDR_RNG] dmem_write_address; // Data memory write address 8.166 +wire [`LM32_DC_TAGS_RNG] tmem_write_data; // Tag memory write data 8.167 +reg [`LM32_WORD_RNG] dmem_write_data; // Data memory write data 8.168 + 8.169 +reg [`LM32_DC_STATE_RNG] state; // Current state of FSM 8.170 +wire flushing; // Indicates if cache is currently flushing 8.171 +wire check; // Indicates if cache is currently checking for hits/misses 8.172 +wire refill; // Indicates if cache is currently refilling 8.173 + 8.174 +wire valid_store; // Indicates if there is a valid store instruction 8.175 +reg [associativity-1:0] refill_way_select; // Which way should be refilled 8.176 +reg [`LM32_DC_ADDR_OFFSET_RNG] refill_offset; // Which word in cache line should be refilled 8.177 +wire last_refill; // Indicates when on last cycle of cache refill 8.178 +reg [`LM32_DC_TMEM_ADDR_RNG] flush_set; // Which set is currently being flushed 8.179 + 8.180 +genvar i, j; 8.181 + 8.182 +///////////////////////////////////////////////////// 8.183 +// Functions 8.184 +///////////////////////////////////////////////////// 8.185 + 8.186 +`include "lm32_functions.v" 8.187 + 8.188 +///////////////////////////////////////////////////// 8.189 +// Instantiations 8.190 +///////////////////////////////////////////////////// 8.191 + 8.192 + generate 8.193 + for (i = 0; i < associativity; i = i + 1) 8.194 + begin : memories 8.195 + // Way data 8.196 + if (`LM32_DC_DMEM_ADDR_WIDTH < 11) 8.197 + begin : data_memories 8.198 + lm32_ram 8.199 + #( 8.200 + // ----- Parameters ------- 8.201 + .data_width (32), 8.202 + .address_width (`LM32_DC_DMEM_ADDR_WIDTH), 8.203 +`ifdef CFG_DCACHE_DAT_USE_DP_TRUE 8.204 + .RAM_IMPLEMENTATION ("EBR"), 8.205 + .RAM_TYPE ("RAM_DP_TRUE") 8.206 +`else 8.207 + `ifdef CFG_DCACHE_DAT_USE_SLICE 8.208 + .RAM_IMPLEMENTATION ("SLICE") 8.209 + `else 8.210 + .RAM_IMPLEMENTATION ("AUTO") 8.211 + `endif 8.212 +`endif 8.213 + ) way_0_data_ram 8.214 + ( 8.215 + // ----- Inputs ------- 8.216 + .read_clk (clk_i), 8.217 + .write_clk (clk_i), 8.218 + .reset (rst_i), 8.219 + .read_address (dmem_read_address), 8.220 + .enable_read (read_port_enable), 8.221 + .write_address (dmem_write_address), 8.222 + .enable_write (write_port_enable), 8.223 + .write_enable (way_dmem_we[i]), 8.224 + .write_data (dmem_write_data), 8.225 + // ----- Outputs ------- 8.226 + .read_data (way_data[i]) 8.227 + ); 8.228 + end 8.229 + else 8.230 + begin 8.231 + for (j = 0; j < 4; j = j + 1) 8.232 + begin : byte_memories 8.233 + lm32_ram 8.234 + #( 8.235 + // ----- Parameters ------- 8.236 + .data_width (8), 8.237 + .address_width (`LM32_DC_DMEM_ADDR_WIDTH), 8.238 +`ifdef CFG_DCACHE_DAT_USE_DP_TRUE 8.239 + .RAM_IMPLEMENTATION ("EBR"), 8.240 + .RAM_TYPE ("RAM_DP_TRUE") 8.241 +`else 8.242 + `ifdef CFG_DCACHE_DAT_USE_SLICE 8.243 + .RAM_IMPLEMENTATION ("SLICE") 8.244 + `else 8.245 + .RAM_IMPLEMENTATION ("AUTO") 8.246 + `endif 8.247 +`endif 8.248 + ) way_0_data_ram 8.249 + ( 8.250 + // ----- Inputs ------- 8.251 + .read_clk (clk_i), 8.252 + .write_clk (clk_i), 8.253 + .reset (rst_i), 8.254 + .read_address (dmem_read_address), 8.255 + .enable_read (read_port_enable), 8.256 + .write_address (dmem_write_address), 8.257 + .enable_write (write_port_enable), 8.258 + .write_enable (way_dmem_we[i] & (store_byte_select[j] | refill)), 8.259 + .write_data (dmem_write_data[(j+1)*8-1:j*8]), 8.260 + // ----- Outputs ------- 8.261 + .read_data (way_data[i][(j+1)*8-1:j*8]) 8.262 + ); 8.263 + end 8.264 + end 8.265 + 8.266 + // Way tags 8.267 + lm32_ram 8.268 + #( 8.269 + // ----- Parameters ------- 8.270 + .data_width (`LM32_DC_TAGS_WIDTH), 8.271 + .address_width (`LM32_DC_TMEM_ADDR_WIDTH), 8.272 +`ifdef CFG_DCACHE_DAT_USE_DP_TRUE 8.273 + .RAM_IMPLEMENTATION ("EBR"), 8.274 + .RAM_TYPE ("RAM_DP_TRUE") 8.275 +`else 8.276 + `ifdef CFG_DCACHE_DAT_USE_SLICE 8.277 + .RAM_IMPLEMENTATION ("SLICE") 8.278 + `else 8.279 + .RAM_IMPLEMENTATION ("AUTO") 8.280 + `endif 8.281 +`endif 8.282 + ) way_0_tag_ram 8.283 + ( 8.284 + // ----- Inputs ------- 8.285 + .read_clk (clk_i), 8.286 + .write_clk (clk_i), 8.287 + .reset (rst_i), 8.288 + .read_address (tmem_read_address), 8.289 + .enable_read (read_port_enable), 8.290 + .write_address (tmem_write_address), 8.291 + .enable_write (`TRUE), 8.292 + .write_enable (way_tmem_we[i]), 8.293 + .write_data (tmem_write_data), 8.294 + // ----- Outputs ------- 8.295 + .read_data ({way_tag[i], way_valid[i]}) 8.296 + ); 8.297 + end 8.298 + 8.299 + endgenerate 8.300 + 8.301 +///////////////////////////////////////////////////// 8.302 +// Combinational logic 8.303 +///////////////////////////////////////////////////// 8.304 + 8.305 +// Compute which ways in the cache match the address being read 8.306 +generate 8.307 + for (i = 0; i < associativity; i = i + 1) 8.308 + begin : match 8.309 +assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_m[`LM32_DC_ADDR_TAG_RNG], `TRUE}); 8.310 + end 8.311 +endgenerate 8.312 + 8.313 +// Select data from way that matched the address being read 8.314 +generate 8.315 + if (associativity == 1) 8.316 + begin : data_1 8.317 +assign load_data = way_data[0]; 8.318 + end 8.319 + else if (associativity == 2) 8.320 + begin : data_2 8.321 +assign load_data = way_match[0] ? way_data[0] : way_data[1]; 8.322 + end 8.323 +endgenerate 8.324 + 8.325 +generate 8.326 + if (`LM32_DC_DMEM_ADDR_WIDTH < 11) 8.327 + begin 8.328 +// Select data to write to data memories 8.329 +always @(*) 8.330 +begin 8.331 + if (refill == `TRUE) 8.332 + dmem_write_data = refill_data; 8.333 + else 8.334 + begin 8.335 + dmem_write_data[`LM32_BYTE_0_RNG] = store_byte_select[0] ? store_data[`LM32_BYTE_0_RNG] : load_data[`LM32_BYTE_0_RNG]; 8.336 + dmem_write_data[`LM32_BYTE_1_RNG] = store_byte_select[1] ? store_data[`LM32_BYTE_1_RNG] : load_data[`LM32_BYTE_1_RNG]; 8.337 + dmem_write_data[`LM32_BYTE_2_RNG] = store_byte_select[2] ? store_data[`LM32_BYTE_2_RNG] : load_data[`LM32_BYTE_2_RNG]; 8.338 + dmem_write_data[`LM32_BYTE_3_RNG] = store_byte_select[3] ? store_data[`LM32_BYTE_3_RNG] : load_data[`LM32_BYTE_3_RNG]; 8.339 + end 8.340 +end 8.341 + end 8.342 + else 8.343 + begin 8.344 +// Select data to write to data memories - FIXME: Should use different write ports on dual port RAMs, but they don't work 8.345 +always @(*) 8.346 +begin 8.347 + if (refill == `TRUE) 8.348 + dmem_write_data = refill_data; 8.349 + else 8.350 + dmem_write_data = store_data; 8.351 +end 8.352 + end 8.353 +endgenerate 8.354 + 8.355 +// Compute address to use to index into the data memories 8.356 +generate 8.357 + if (bytes_per_line > 4) 8.358 +assign dmem_write_address = (refill == `TRUE) 8.359 + ? {refill_address[`LM32_DC_ADDR_SET_RNG], refill_offset} 8.360 + : address_m[`LM32_DC_ADDR_IDX_RNG]; 8.361 + else 8.362 +assign dmem_write_address = (refill == `TRUE) 8.363 + ? refill_address[`LM32_DC_ADDR_SET_RNG] 8.364 + : address_m[`LM32_DC_ADDR_IDX_RNG]; 8.365 +endgenerate 8.366 +assign dmem_read_address = address_x[`LM32_DC_ADDR_IDX_RNG]; 8.367 +// Compute address to use to index into the tag memories 8.368 +assign tmem_write_address = (flushing == `TRUE) 8.369 + ? flush_set 8.370 + : refill_address[`LM32_DC_ADDR_SET_RNG]; 8.371 +assign tmem_read_address = address_x[`LM32_DC_ADDR_SET_RNG]; 8.372 + 8.373 +// Compute signal to indicate when we are on the last refill accesses 8.374 +generate 8.375 + if (bytes_per_line > 4) 8.376 +assign last_refill = refill_offset == {addr_offset_width{1'b1}}; 8.377 + else 8.378 +assign last_refill = `TRUE; 8.379 +endgenerate 8.380 + 8.381 +// Compute data and tag memory access enable 8.382 +assign read_port_enable = (stall_x == `FALSE); 8.383 +assign write_port_enable = (refill_ready == `TRUE) || !stall_m; 8.384 + 8.385 +// Determine when we have a valid store 8.386 +assign valid_store = (store_q_m == `TRUE) && (check == `TRUE); 8.387 + 8.388 +// Compute data and tag memory write enables 8.389 +generate 8.390 + if (associativity == 1) 8.391 + begin : we_1 8.392 +assign way_dmem_we[0] = (refill_ready == `TRUE) || ((valid_store == `TRUE) && (way_match[0] == `TRUE)); 8.393 +assign way_tmem_we[0] = (refill_ready == `TRUE) || (flushing == `TRUE); 8.394 + end 8.395 + else 8.396 + begin : we_2 8.397 +assign way_dmem_we[0] = ((refill_ready == `TRUE) && (refill_way_select[0] == `TRUE)) || ((valid_store == `TRUE) && (way_match[0] == `TRUE)); 8.398 +assign way_dmem_we[1] = ((refill_ready == `TRUE) && (refill_way_select[1] == `TRUE)) || ((valid_store == `TRUE) && (way_match[1] == `TRUE)); 8.399 +assign way_tmem_we[0] = ((refill_ready == `TRUE) && (refill_way_select[0] == `TRUE)) || (flushing == `TRUE); 8.400 +assign way_tmem_we[1] = ((refill_ready == `TRUE) && (refill_way_select[1] == `TRUE)) || (flushing == `TRUE); 8.401 + end 8.402 +endgenerate 8.403 + 8.404 +// On the last refill cycle set the valid bit, for all other writes it should be cleared 8.405 +assign tmem_write_data[`LM32_DC_TAGS_VALID_RNG] = ((last_refill == `TRUE) || (valid_store == `TRUE)) && (flushing == `FALSE); 8.406 +assign tmem_write_data[`LM32_DC_TAGS_TAG_RNG] = refill_address[`LM32_DC_ADDR_TAG_RNG]; 8.407 + 8.408 +// Signals that indicate which state we are in 8.409 +assign flushing = state[0]; 8.410 +assign check = state[1]; 8.411 +assign refill = state[2]; 8.412 + 8.413 +assign miss = (~(|way_match)) && (load_q_m == `TRUE) && (stall_m == `FALSE); 8.414 +assign stall_request = (check == `FALSE); 8.415 + 8.416 +///////////////////////////////////////////////////// 8.417 +// Sequential logic 8.418 +///////////////////////////////////////////////////// 8.419 + 8.420 +// Record way selected for replacement on a cache miss 8.421 +generate 8.422 + if (associativity >= 2) 8.423 + begin : way_select 8.424 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 8.425 +begin 8.426 + if (rst_i == `TRUE) 8.427 + refill_way_select <= {{associativity-1{1'b0}}, 1'b1}; 8.428 + else 8.429 + begin 8.430 + if (refill_request == `TRUE) 8.431 + refill_way_select <= {refill_way_select[0], refill_way_select[1]}; 8.432 + end 8.433 +end 8.434 + end 8.435 +endgenerate 8.436 + 8.437 +// Record whether we are currently refilling 8.438 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 8.439 +begin 8.440 + if (rst_i == `TRUE) 8.441 + refilling <= `FALSE; 8.442 + else 8.443 + refilling <= refill; 8.444 +end 8.445 + 8.446 +// Instruction cache control FSM 8.447 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 8.448 +begin 8.449 + if (rst_i == `TRUE) 8.450 + begin 8.451 + state <= `LM32_DC_STATE_FLUSH; 8.452 + flush_set <= {`LM32_DC_TMEM_ADDR_WIDTH{1'b1}}; 8.453 + refill_request <= `FALSE; 8.454 + refill_address <= {`LM32_WORD_WIDTH{1'bx}}; 8.455 + restart_request <= `FALSE; 8.456 + end 8.457 + else 8.458 + begin 8.459 + case (state) 8.460 + 8.461 + // Flush the cache 8.462 + `LM32_DC_STATE_FLUSH: 8.463 + begin 8.464 + if (flush_set == {`LM32_DC_TMEM_ADDR_WIDTH{1'b0}}) 8.465 + state <= `LM32_DC_STATE_CHECK; 8.466 + flush_set <= flush_set - 1'b1; 8.467 + end 8.468 + 8.469 + // Check for cache misses 8.470 + `LM32_DC_STATE_CHECK: 8.471 + begin 8.472 + if (stall_a == `FALSE) 8.473 + restart_request <= `FALSE; 8.474 + if (miss == `TRUE) 8.475 + begin 8.476 + refill_request <= `TRUE; 8.477 + refill_address <= address_m; 8.478 + state <= `LM32_DC_STATE_REFILL; 8.479 + end 8.480 + else if (dflush == `TRUE) 8.481 + state <= `LM32_DC_STATE_FLUSH; 8.482 + end 8.483 + 8.484 + // Refill a cache line 8.485 + `LM32_DC_STATE_REFILL: 8.486 + begin 8.487 + refill_request <= `FALSE; 8.488 + if (refill_ready == `TRUE) 8.489 + begin 8.490 + if (last_refill == `TRUE) 8.491 + begin 8.492 + restart_request <= `TRUE; 8.493 + state <= `LM32_DC_STATE_CHECK; 8.494 + end 8.495 + end 8.496 + end 8.497 + 8.498 + endcase 8.499 + end 8.500 +end 8.501 + 8.502 +generate 8.503 + if (bytes_per_line > 4) 8.504 + begin 8.505 +// Refill offset 8.506 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 8.507 +begin 8.508 + if (rst_i == `TRUE) 8.509 + refill_offset <= {addr_offset_width{1'b0}}; 8.510 + else 8.511 + begin 8.512 + case (state) 8.513 + 8.514 + // Check for cache misses 8.515 + `LM32_DC_STATE_CHECK: 8.516 + begin 8.517 + if (miss == `TRUE) 8.518 + refill_offset <= {addr_offset_width{1'b0}}; 8.519 + end 8.520 + 8.521 + // Refill a cache line 8.522 + `LM32_DC_STATE_REFILL: 8.523 + begin 8.524 + if (refill_ready == `TRUE) 8.525 + refill_offset <= refill_offset + 1'b1; 8.526 + end 8.527 + 8.528 + endcase 8.529 + end 8.530 +end 8.531 + end 8.532 +endgenerate 8.533 + 8.534 +endmodule 8.535 + 8.536 +`endif 8.537 +
9.1 diff -r 000000000000 -r cd0b58aa6f83 lm32_debug.v 9.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 9.3 +++ b/lm32_debug.v Sun Apr 04 20:40:03 2010 +0100 9.4 @@ -0,0 +1,348 @@ 9.5 +// ============================================================================= 9.6 +// COPYRIGHT NOTICE 9.7 +// Copyright 2006 (c) Lattice Semiconductor Corporation 9.8 +// ALL RIGHTS RESERVED 9.9 +// This confidential and proprietary software may be used only as authorised by 9.10 +// a licensing agreement from Lattice Semiconductor Corporation. 9.11 +// The entire notice above must be reproduced on all authorized copies and 9.12 +// copies may only be made to the extent permitted by a licensing agreement from 9.13 +// Lattice Semiconductor Corporation. 9.14 +// 9.15 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 9.16 +// 5555 NE Moore Court 408-826-6000 (other locations) 9.17 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 9.18 +// U.S.A email: techsupport@latticesemi.com 9.19 +// =============================================================================/ 9.20 +// FILE DETAILS 9.21 +// Project : LatticeMico32 9.22 +// File : lm32_debug.v 9.23 +// Title : Hardware debug registers and associated logic. 9.24 +// Dependencies : lm32_include.v 9.25 +// Version : 6.1.17 9.26 +// : Initial Release 9.27 +// Version : 7.0SP2, 3.0 9.28 +// : No Change 9.29 +// Version : 3.1 9.30 +// : No Change 9.31 +// Version : 3.2 9.32 +// : Fixed simulation bug which flares up when number of 9.33 +// : watchpoints is zero. 9.34 +// ============================================================================= 9.35 + 9.36 +`include "lm32_include.v" 9.37 + 9.38 +`ifdef CFG_DEBUG_ENABLED 9.39 + 9.40 +// States for single-step FSM 9.41 +`define LM32_DEBUG_SS_STATE_RNG 2:0 9.42 +`define LM32_DEBUG_SS_STATE_IDLE 3'b000 9.43 +`define LM32_DEBUG_SS_STATE_WAIT_FOR_RET 3'b001 9.44 +`define LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN 3'b010 9.45 +`define LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT 3'b011 9.46 +`define LM32_DEBUG_SS_STATE_RESTART 3'b100 9.47 + 9.48 +///////////////////////////////////////////////////// 9.49 +// Module interface 9.50 +///////////////////////////////////////////////////// 9.51 + 9.52 +module lm32_debug ( 9.53 + // ----- Inputs ------- 9.54 + clk_i, 9.55 + rst_i, 9.56 + pc_x, 9.57 + load_x, 9.58 + store_x, 9.59 + load_store_address_x, 9.60 + csr_write_enable_x, 9.61 + csr_write_data, 9.62 + csr_x, 9.63 +`ifdef CFG_HW_DEBUG_ENABLED 9.64 + jtag_csr_write_enable, 9.65 + jtag_csr_write_data, 9.66 + jtag_csr, 9.67 +`endif 9.68 +`ifdef LM32_SINGLE_STEP_ENABLED 9.69 + eret_q_x, 9.70 + bret_q_x, 9.71 + stall_x, 9.72 + exception_x, 9.73 + q_x, 9.74 +`ifdef CFG_DCACHE_ENABLED 9.75 + dcache_refill_request, 9.76 +`endif 9.77 +`endif 9.78 + // ----- Outputs ------- 9.79 +`ifdef LM32_SINGLE_STEP_ENABLED 9.80 + dc_ss, 9.81 +`endif 9.82 + dc_re, 9.83 + bp_match, 9.84 + wp_match 9.85 + ); 9.86 + 9.87 +///////////////////////////////////////////////////// 9.88 +// Parameters 9.89 +///////////////////////////////////////////////////// 9.90 + 9.91 +parameter breakpoints = 0; // Number of breakpoint CSRs 9.92 +parameter watchpoints = 0; // Number of watchpoint CSRs 9.93 + 9.94 +///////////////////////////////////////////////////// 9.95 +// Inputs 9.96 +///////////////////////////////////////////////////// 9.97 + 9.98 +input clk_i; // Clock 9.99 +input rst_i; // Reset 9.100 + 9.101 +input [`LM32_PC_RNG] pc_x; // X stage PC 9.102 +input load_x; // Load instruction in X stage 9.103 +input store_x; // Store instruction in X stage 9.104 +input [`LM32_WORD_RNG] load_store_address_x; // Load or store effective address 9.105 +input csr_write_enable_x; // wcsr instruction in X stage 9.106 +input [`LM32_WORD_RNG] csr_write_data; // Data to write to CSR 9.107 +input [`LM32_CSR_RNG] csr_x; // Which CSR to write 9.108 +`ifdef CFG_HW_DEBUG_ENABLED 9.109 +input jtag_csr_write_enable; // JTAG interface CSR write enable 9.110 +input [`LM32_WORD_RNG] jtag_csr_write_data; // Data to write to CSR 9.111 +input [`LM32_CSR_RNG] jtag_csr; // Which CSR to write 9.112 +`endif 9.113 +`ifdef LM32_SINGLE_STEP_ENABLED 9.114 +input eret_q_x; // eret instruction in X stage 9.115 +input bret_q_x; // bret instruction in X stage 9.116 +input stall_x; // Instruction in X stage is stalled 9.117 +input exception_x; // An exception has occured in X stage 9.118 +input q_x; // Indicates the instruction in the X stage is qualified 9.119 +`ifdef CFG_DCACHE_ENABLED 9.120 +input dcache_refill_request; // Indicates data cache wants to be refilled 9.121 +`endif 9.122 +`endif 9.123 + 9.124 +///////////////////////////////////////////////////// 9.125 +// Outputs 9.126 +///////////////////////////////////////////////////// 9.127 + 9.128 +`ifdef LM32_SINGLE_STEP_ENABLED 9.129 +output dc_ss; // Single-step enable 9.130 +reg dc_ss; 9.131 +`endif 9.132 +output dc_re; // Remap exceptions 9.133 +reg dc_re; 9.134 +output bp_match; // Indicates a breakpoint has matched 9.135 +wire bp_match; 9.136 +output wp_match; // Indicates a watchpoint has matched 9.137 +wire wp_match; 9.138 + 9.139 +///////////////////////////////////////////////////// 9.140 +// Internal nets and registers 9.141 +///////////////////////////////////////////////////// 9.142 + 9.143 +genvar i; // Loop index for generate statements 9.144 + 9.145 +// Debug CSRs 9.146 + 9.147 +reg [`LM32_PC_RNG] bp_a[0:breakpoints-1]; // Instruction breakpoint address 9.148 +reg bp_e[0:breakpoints-1]; // Instruction breakpoint enable 9.149 +wire [0:breakpoints-1]bp_match_n; // Indicates if a h/w instruction breakpoint matched 9.150 + 9.151 +reg [`LM32_WPC_C_RNG] wpc_c[0:watchpoints-1]; // Watchpoint enable 9.152 +reg [`LM32_WORD_RNG] wp[0:watchpoints-1]; // Watchpoint address 9.153 +wire [0:watchpoints]wp_match_n; // Indicates if a h/w data watchpoint matched 9.154 + 9.155 +wire debug_csr_write_enable; // Debug CSR write enable (from either a wcsr instruction of external debugger) 9.156 +wire [`LM32_WORD_RNG] debug_csr_write_data; // Data to write to debug CSR 9.157 +wire [`LM32_CSR_RNG] debug_csr; // Debug CSR to write to 9.158 + 9.159 +`ifdef LM32_SINGLE_STEP_ENABLED 9.160 +// FIXME: Declaring this as a reg causes ModelSim 6.1.15b to crash, so use integer for now 9.161 +//reg [`LM32_DEBUG_SS_STATE_RNG] state; // State of single-step FSM 9.162 +integer state; // State of single-step FSM 9.163 +`endif 9.164 + 9.165 +///////////////////////////////////////////////////// 9.166 +// Functions 9.167 +///////////////////////////////////////////////////// 9.168 + 9.169 +`include "lm32_functions.v" 9.170 + 9.171 +///////////////////////////////////////////////////// 9.172 +// Combinational Logic 9.173 +///////////////////////////////////////////////////// 9.174 + 9.175 +// Check for breakpoints 9.176 +generate 9.177 + for (i = 0; i < breakpoints; i = i + 1) 9.178 + begin : bp_comb 9.179 +assign bp_match_n[i] = ((bp_a[i] == pc_x) && (bp_e[i] == `TRUE)); 9.180 + end 9.181 +endgenerate 9.182 +generate 9.183 +`ifdef LM32_SINGLE_STEP_ENABLED 9.184 + if (breakpoints > 0) 9.185 +assign bp_match = (|bp_match_n) || (state == `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT); 9.186 + else 9.187 +assign bp_match = state == `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT; 9.188 +`else 9.189 + if (breakpoints > 0) 9.190 +assign bp_match = |bp_match_n; 9.191 + else 9.192 +assign bp_match = `FALSE; 9.193 +`endif 9.194 +endgenerate 9.195 + 9.196 +// Check for watchpoints 9.197 +generate 9.198 + for (i = 0; i < watchpoints; i = i + 1) 9.199 + begin : wp_comb 9.200 +assign wp_match_n[i] = (wp[i] == load_store_address_x) && ((load_x & wpc_c[i][0]) | (store_x & wpc_c[i][1])); 9.201 + end 9.202 +endgenerate 9.203 +generate 9.204 + if (watchpoints > 0) 9.205 +assign wp_match = |wp_match_n; 9.206 + else 9.207 +assign wp_match = `FALSE; 9.208 +endgenerate 9.209 + 9.210 +`ifdef CFG_HW_DEBUG_ENABLED 9.211 +// Multiplex between wcsr instruction writes and debugger writes to the debug CSRs 9.212 +assign debug_csr_write_enable = (csr_write_enable_x == `TRUE) || (jtag_csr_write_enable == `TRUE); 9.213 +assign debug_csr_write_data = jtag_csr_write_enable == `TRUE ? jtag_csr_write_data : csr_write_data; 9.214 +assign debug_csr = jtag_csr_write_enable == `TRUE ? jtag_csr : csr_x; 9.215 +`else 9.216 +assign debug_csr_write_enable = csr_write_enable_x; 9.217 +assign debug_csr_write_data = csr_write_data; 9.218 +assign debug_csr = csr_x; 9.219 +`endif 9.220 + 9.221 +///////////////////////////////////////////////////// 9.222 +// Sequential Logic 9.223 +///////////////////////////////////////////////////// 9.224 + 9.225 +// Breakpoint address and enable CSRs 9.226 +generate 9.227 + for (i = 0; i < breakpoints; i = i + 1) 9.228 + begin : bp_seq 9.229 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 9.230 +begin 9.231 + if (rst_i == `TRUE) 9.232 + begin 9.233 + bp_a[i] <= {`LM32_PC_WIDTH{1'bx}}; 9.234 + bp_e[i] <= `FALSE; 9.235 + end 9.236 + else 9.237 + begin 9.238 + if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_BP0 + i)) 9.239 + begin 9.240 + bp_a[i] <= debug_csr_write_data[`LM32_PC_RNG]; 9.241 + bp_e[i] <= debug_csr_write_data[0]; 9.242 + end 9.243 + end 9.244 +end 9.245 + end 9.246 +endgenerate 9.247 + 9.248 +// Watchpoint address and control flags CSRs 9.249 +generate 9.250 + for (i = 0; i < watchpoints; i = i + 1) 9.251 + begin : wp_seq 9.252 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 9.253 +begin 9.254 + if (rst_i == `TRUE) 9.255 + begin 9.256 + wp[i] <= {`LM32_WORD_WIDTH{1'bx}}; 9.257 + wpc_c[i] <= `LM32_WPC_C_DISABLED; 9.258 + end 9.259 + else 9.260 + begin 9.261 + if (debug_csr_write_enable == `TRUE) 9.262 + begin 9.263 + if (debug_csr == `LM32_CSR_DC) 9.264 + wpc_c[i] <= debug_csr_write_data[3+i*2:2+i*2]; 9.265 + if (debug_csr == `LM32_CSR_WP0 + i) 9.266 + wp[i] <= debug_csr_write_data; 9.267 + end 9.268 + end 9.269 +end 9.270 + end 9.271 +endgenerate 9.272 + 9.273 +// Remap exceptions control bit 9.274 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 9.275 +begin 9.276 + if (rst_i == `TRUE) 9.277 + dc_re <= `FALSE; 9.278 + else 9.279 + begin 9.280 + if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_DC)) 9.281 + dc_re <= debug_csr_write_data[1]; 9.282 + end 9.283 +end 9.284 + 9.285 +`ifdef LM32_SINGLE_STEP_ENABLED 9.286 +// Single-step control flag 9.287 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 9.288 +begin 9.289 + if (rst_i == `TRUE) 9.290 + begin 9.291 + state <= `LM32_DEBUG_SS_STATE_IDLE; 9.292 + dc_ss <= `FALSE; 9.293 + end 9.294 + else 9.295 + begin 9.296 + if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_DC)) 9.297 + begin 9.298 + dc_ss <= debug_csr_write_data[0]; 9.299 + if (debug_csr_write_data[0] == `FALSE) 9.300 + state <= `LM32_DEBUG_SS_STATE_IDLE; 9.301 + else 9.302 + state <= `LM32_DEBUG_SS_STATE_WAIT_FOR_RET; 9.303 + end 9.304 + case (state) 9.305 + `LM32_DEBUG_SS_STATE_WAIT_FOR_RET: 9.306 + begin 9.307 + // Wait for eret or bret instruction to be executed 9.308 + if ( ( (eret_q_x == `TRUE) 9.309 + || (bret_q_x == `TRUE) 9.310 + ) 9.311 + && (stall_x == `FALSE) 9.312 + ) 9.313 + state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 9.314 + end 9.315 + `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN: 9.316 + begin 9.317 + // Wait for an instruction to be executed 9.318 + if ((q_x == `TRUE) && (stall_x == `FALSE)) 9.319 + state <= `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT; 9.320 + end 9.321 + `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT: 9.322 + begin 9.323 + // Wait for exception to be raised 9.324 +`ifdef CFG_DCACHE_ENABLED 9.325 + if (dcache_refill_request == `TRUE) 9.326 + state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 9.327 + else 9.328 +`endif 9.329 + if ((exception_x == `TRUE) && (q_x == `TRUE) && (stall_x == `FALSE)) 9.330 + begin 9.331 + dc_ss <= `FALSE; 9.332 + state <= `LM32_DEBUG_SS_STATE_RESTART; 9.333 + end 9.334 + end 9.335 + `LM32_DEBUG_SS_STATE_RESTART: 9.336 + begin 9.337 + // Watch to see if stepped instruction is restarted due to a cache miss 9.338 +`ifdef CFG_DCACHE_ENABLED 9.339 + if (dcache_refill_request == `TRUE) 9.340 + state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 9.341 + else 9.342 +`endif 9.343 + state <= `LM32_DEBUG_SS_STATE_IDLE; 9.344 + end 9.345 + endcase 9.346 + end 9.347 +end 9.348 +`endif 9.349 + 9.350 +endmodule 9.351 + 9.352 +`endif
10.1 diff -r 000000000000 -r cd0b58aa6f83 lm32_decoder.v 10.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 10.3 +++ b/lm32_decoder.v Sun Apr 04 20:40:03 2010 +0100 10.4 @@ -0,0 +1,583 @@ 10.5 +// ============================================================================= 10.6 +// COPYRIGHT NOTICE 10.7 +// Copyright 2006 (c) Lattice Semiconductor Corporation 10.8 +// ALL RIGHTS RESERVED 10.9 +// This confidential and proprietary software may be used only as authorised by 10.10 +// a licensing agreement from Lattice Semiconductor Corporation. 10.11 +// The entire notice above must be reproduced on all authorized copies and 10.12 +// copies may only be made to the extent permitted by a licensing agreement from 10.13 +// Lattice Semiconductor Corporation. 10.14 +// 10.15 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 10.16 +// 5555 NE Moore Court 408-826-6000 (other locations) 10.17 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 10.18 +// U.S.A email: techsupport@latticesemi.com 10.19 +// =============================================================================/ 10.20 +// FILE DETAILS 10.21 +// Project : LatticeMico32 10.22 +// File : lm32_decoder.v 10.23 +// Title : Instruction decoder 10.24 +// Dependencies : lm32_include.v 10.25 +// Version : 6.1.17 10.26 +// : Initial Release 10.27 +// Version : 7.0SP2, 3.0 10.28 +// : No Change 10.29 +// Version : 3.1 10.30 +// : Support for static branch prediction. Information about 10.31 +// : branch type is generated and passed on to the predictor. 10.32 +// Version : 3.2 10.33 +// : No change 10.34 +// Version : 3.3 10.35 +// : Renamed port names that conflict with keywords reserved 10.36 +// : in System-Verilog. 10.37 +// ============================================================================= 10.38 + 10.39 +`include "lm32_include.v" 10.40 + 10.41 +// Index of opcode field in an instruction 10.42 +`define LM32_OPCODE_RNG 31:26 10.43 +`define LM32_OP_RNG 30:26 10.44 + 10.45 +// Opcodes - Some are only listed as 5 bits as their MSB is a don't care 10.46 +`define LM32_OPCODE_ADD 5'b01101 10.47 +`define LM32_OPCODE_AND 5'b01000 10.48 +`define LM32_OPCODE_ANDHI 6'b011000 10.49 +`define LM32_OPCODE_B 6'b110000 10.50 +`define LM32_OPCODE_BI 6'b111000 10.51 +`define LM32_OPCODE_BE 6'b010001 10.52 +`define LM32_OPCODE_BG 6'b010010 10.53 +`define LM32_OPCODE_BGE 6'b010011 10.54 +`define LM32_OPCODE_BGEU 6'b010100 10.55 +`define LM32_OPCODE_BGU 6'b010101 10.56 +`define LM32_OPCODE_BNE 6'b010111 10.57 +`define LM32_OPCODE_CALL 6'b110110 10.58 +`define LM32_OPCODE_CALLI 6'b111110 10.59 +`define LM32_OPCODE_CMPE 5'b11001 10.60 +`define LM32_OPCODE_CMPG 5'b11010 10.61 +`define LM32_OPCODE_CMPGE 5'b11011 10.62 +`define LM32_OPCODE_CMPGEU 5'b11100 10.63 +`define LM32_OPCODE_CMPGU 5'b11101 10.64 +`define LM32_OPCODE_CMPNE 5'b11111 10.65 +`define LM32_OPCODE_DIVU 6'b100011 10.66 +`define LM32_OPCODE_LB 6'b000100 10.67 +`define LM32_OPCODE_LBU 6'b010000 10.68 +`define LM32_OPCODE_LH 6'b000111 10.69 +`define LM32_OPCODE_LHU 6'b001011 10.70 +`define LM32_OPCODE_LW 6'b001010 10.71 +`define LM32_OPCODE_MODU 6'b110001 10.72 +`define LM32_OPCODE_MUL 5'b00010 10.73 +`define LM32_OPCODE_NOR 5'b00001 10.74 +`define LM32_OPCODE_OR 5'b01110 10.75 +`define LM32_OPCODE_ORHI 6'b011110 10.76 +`define LM32_OPCODE_RAISE 6'b101011 10.77 +`define LM32_OPCODE_RCSR 6'b100100 10.78 +`define LM32_OPCODE_SB 6'b001100 10.79 +`define LM32_OPCODE_SEXTB 6'b101100 10.80 +`define LM32_OPCODE_SEXTH 6'b110111 10.81 +`define LM32_OPCODE_SH 6'b000011 10.82 +`define LM32_OPCODE_SL 5'b01111 10.83 +`define LM32_OPCODE_SR 5'b00101 10.84 +`define LM32_OPCODE_SRU 5'b00000 10.85 +`define LM32_OPCODE_SUB 6'b110010 10.86 +`define LM32_OPCODE_SW 6'b010110 10.87 +`define LM32_OPCODE_USER 6'b110011 10.88 +`define LM32_OPCODE_WCSR 6'b110100 10.89 +`define LM32_OPCODE_XNOR 5'b01001 10.90 +`define LM32_OPCODE_XOR 5'b00110 10.91 + 10.92 +///////////////////////////////////////////////////// 10.93 +// Module interface 10.94 +///////////////////////////////////////////////////// 10.95 + 10.96 +module lm32_decoder ( 10.97 + // ----- Inputs ------- 10.98 + instruction, 10.99 + // ----- Outputs ------- 10.100 + d_result_sel_0, 10.101 + d_result_sel_1, 10.102 + x_result_sel_csr, 10.103 +`ifdef LM32_MC_ARITHMETIC_ENABLED 10.104 + x_result_sel_mc_arith, 10.105 +`endif 10.106 +`ifdef LM32_NO_BARREL_SHIFT 10.107 + x_result_sel_shift, 10.108 +`endif 10.109 +`ifdef CFG_SIGN_EXTEND_ENABLED 10.110 + x_result_sel_sext, 10.111 +`endif 10.112 + x_result_sel_logic, 10.113 +`ifdef CFG_USER_ENABLED 10.114 + x_result_sel_user, 10.115 +`endif 10.116 + x_result_sel_add, 10.117 + m_result_sel_compare, 10.118 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 10.119 + m_result_sel_shift, 10.120 +`endif 10.121 + w_result_sel_load, 10.122 +`ifdef CFG_PL_MULTIPLY_ENABLED 10.123 + w_result_sel_mul, 10.124 +`endif 10.125 + x_bypass_enable, 10.126 + m_bypass_enable, 10.127 + read_enable_0, 10.128 + read_idx_0, 10.129 + read_enable_1, 10.130 + read_idx_1, 10.131 + write_enable, 10.132 + write_idx, 10.133 + immediate, 10.134 + branch_offset, 10.135 + load, 10.136 + store, 10.137 + size, 10.138 + sign_extend, 10.139 + adder_op, 10.140 + logic_op, 10.141 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 10.142 + direction, 10.143 +`endif 10.144 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED 10.145 + shift_left, 10.146 + shift_right, 10.147 +`endif 10.148 +`ifdef CFG_MC_MULTIPLY_ENABLED 10.149 + multiply, 10.150 +`endif 10.151 +`ifdef CFG_MC_DIVIDE_ENABLED 10.152 + divide, 10.153 + modulus, 10.154 +`endif 10.155 + branch, 10.156 + branch_reg, 10.157 + condition, 10.158 + bi_conditional, 10.159 + bi_unconditional, 10.160 +`ifdef CFG_DEBUG_ENABLED 10.161 + break_opcode, 10.162 +`endif 10.163 + scall, 10.164 + eret, 10.165 +`ifdef CFG_DEBUG_ENABLED 10.166 + bret, 10.167 +`endif 10.168 +`ifdef CFG_USER_ENABLED 10.169 + user_opcode, 10.170 +`endif 10.171 + csr_write_enable 10.172 + ); 10.173 + 10.174 +///////////////////////////////////////////////////// 10.175 +// Inputs 10.176 +///////////////////////////////////////////////////// 10.177 + 10.178 +input [`LM32_INSTRUCTION_RNG] instruction; // Instruction to decode 10.179 + 10.180 +///////////////////////////////////////////////////// 10.181 +// Outputs 10.182 +///////////////////////////////////////////////////// 10.183 + 10.184 +output [`LM32_D_RESULT_SEL_0_RNG] d_result_sel_0; 10.185 +reg [`LM32_D_RESULT_SEL_0_RNG] d_result_sel_0; 10.186 +output [`LM32_D_RESULT_SEL_1_RNG] d_result_sel_1; 10.187 +reg [`LM32_D_RESULT_SEL_1_RNG] d_result_sel_1; 10.188 +output x_result_sel_csr; 10.189 +reg x_result_sel_csr; 10.190 +`ifdef LM32_MC_ARITHMETIC_ENABLED 10.191 +output x_result_sel_mc_arith; 10.192 +reg x_result_sel_mc_arith; 10.193 +`endif 10.194 +`ifdef LM32_NO_BARREL_SHIFT 10.195 +output x_result_sel_shift; 10.196 +reg x_result_sel_shift; 10.197 +`endif 10.198 +`ifdef CFG_SIGN_EXTEND_ENABLED 10.199 +output x_result_sel_sext; 10.200 +reg x_result_sel_sext; 10.201 +`endif 10.202 +output x_result_sel_logic; 10.203 +reg x_result_sel_logic; 10.204 +`ifdef CFG_USER_ENABLED 10.205 +output x_result_sel_user; 10.206 +reg x_result_sel_user; 10.207 +`endif 10.208 +output x_result_sel_add; 10.209 +reg x_result_sel_add; 10.210 +output m_result_sel_compare; 10.211 +reg m_result_sel_compare; 10.212 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 10.213 +output m_result_sel_shift; 10.214 +reg m_result_sel_shift; 10.215 +`endif 10.216 +output w_result_sel_load; 10.217 +reg w_result_sel_load; 10.218 +`ifdef CFG_PL_MULTIPLY_ENABLED 10.219 +output w_result_sel_mul; 10.220 +reg w_result_sel_mul; 10.221 +`endif 10.222 +output x_bypass_enable; 10.223 +wire x_bypass_enable; 10.224 +output m_bypass_enable; 10.225 +wire m_bypass_enable; 10.226 +output read_enable_0; 10.227 +wire read_enable_0; 10.228 +output [`LM32_REG_IDX_RNG] read_idx_0; 10.229 +wire [`LM32_REG_IDX_RNG] read_idx_0; 10.230 +output read_enable_1; 10.231 +wire read_enable_1; 10.232 +output [`LM32_REG_IDX_RNG] read_idx_1; 10.233 +wire [`LM32_REG_IDX_RNG] read_idx_1; 10.234 +output write_enable; 10.235 +wire write_enable; 10.236 +output [`LM32_REG_IDX_RNG] write_idx; 10.237 +wire [`LM32_REG_IDX_RNG] write_idx; 10.238 +output [`LM32_WORD_RNG] immediate; 10.239 +wire [`LM32_WORD_RNG] immediate; 10.240 +output [`LM32_PC_RNG] branch_offset; 10.241 +wire [`LM32_PC_RNG] branch_offset; 10.242 +output load; 10.243 +wire load; 10.244 +output store; 10.245 +wire store; 10.246 +output [`LM32_SIZE_RNG] size; 10.247 +wire [`LM32_SIZE_RNG] size; 10.248 +output sign_extend; 10.249 +wire sign_extend; 10.250 +output adder_op; 10.251 +wire adder_op; 10.252 +output [`LM32_LOGIC_OP_RNG] logic_op; 10.253 +wire [`LM32_LOGIC_OP_RNG] logic_op; 10.254 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 10.255 +output direction; 10.256 +wire direction; 10.257 +`endif 10.258 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED 10.259 +output shift_left; 10.260 +wire shift_left; 10.261 +output shift_right; 10.262 +wire shift_right; 10.263 +`endif 10.264 +`ifdef CFG_MC_MULTIPLY_ENABLED 10.265 +output multiply; 10.266 +wire multiply; 10.267 +`endif 10.268 +`ifdef CFG_MC_DIVIDE_ENABLED 10.269 +output divide; 10.270 +wire divide; 10.271 +output modulus; 10.272 +wire modulus; 10.273 +`endif 10.274 +output branch; 10.275 +wire branch; 10.276 +output branch_reg; 10.277 +wire branch_reg; 10.278 +output [`LM32_CONDITION_RNG] condition; 10.279 +wire [`LM32_CONDITION_RNG] condition; 10.280 +output bi_conditional; 10.281 +wire bi_conditional; 10.282 +output bi_unconditional; 10.283 +wire bi_unconditional; 10.284 +`ifdef CFG_DEBUG_ENABLED 10.285 +output break_opcode; 10.286 +wire break_opcode; 10.287 +`endif 10.288 +output scall; 10.289 +wire scall; 10.290 +output eret; 10.291 +wire eret; 10.292 +`ifdef CFG_DEBUG_ENABLED 10.293 +output bret; 10.294 +wire bret; 10.295 +`endif 10.296 +`ifdef CFG_USER_ENABLED 10.297 +output [`LM32_USER_OPCODE_RNG] user_opcode; 10.298 +wire [`LM32_USER_OPCODE_RNG] user_opcode; 10.299 +`endif 10.300 +output csr_write_enable; 10.301 +wire csr_write_enable; 10.302 + 10.303 +///////////////////////////////////////////////////// 10.304 +// Internal nets and registers 10.305 +///////////////////////////////////////////////////// 10.306 + 10.307 +wire [`LM32_WORD_RNG] extended_immediate; // Zero or sign extended immediate 10.308 +wire [`LM32_WORD_RNG] high_immediate; // Immediate as high 16 bits 10.309 +wire [`LM32_WORD_RNG] call_immediate; // Call immediate 10.310 +wire [`LM32_WORD_RNG] branch_immediate; // Conditional branch immediate 10.311 +wire sign_extend_immediate; // Whether the immediate should be sign extended (`TRUE) or zero extended (`FALSE) 10.312 +wire select_high_immediate; // Whether to select the high immediate 10.313 +wire select_call_immediate; // Whether to select the call immediate 10.314 + 10.315 +///////////////////////////////////////////////////// 10.316 +// Functions 10.317 +///////////////////////////////////////////////////// 10.318 + 10.319 +`include "lm32_functions.v" 10.320 + 10.321 +///////////////////////////////////////////////////// 10.322 +// Combinational logic 10.323 +///////////////////////////////////////////////////// 10.324 + 10.325 +// Determine opcode 10.326 +assign op_add = instruction[`LM32_OP_RNG] == `LM32_OPCODE_ADD; 10.327 +assign op_and = instruction[`LM32_OP_RNG] == `LM32_OPCODE_AND; 10.328 +assign op_andhi = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_ANDHI; 10.329 +assign op_b = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_B; 10.330 +assign op_bi = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BI; 10.331 +assign op_be = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BE; 10.332 +assign op_bg = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BG; 10.333 +assign op_bge = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BGE; 10.334 +assign op_bgeu = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BGEU; 10.335 +assign op_bgu = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BGU; 10.336 +assign op_bne = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BNE; 10.337 +assign op_call = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_CALL; 10.338 +assign op_calli = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_CALLI; 10.339 +assign op_cmpe = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPE; 10.340 +assign op_cmpg = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPG; 10.341 +assign op_cmpge = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPGE; 10.342 +assign op_cmpgeu = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPGEU; 10.343 +assign op_cmpgu = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPGU; 10.344 +assign op_cmpne = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPNE; 10.345 +`ifdef CFG_MC_DIVIDE_ENABLED 10.346 +assign op_divu = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_DIVU; 10.347 +`endif 10.348 +assign op_lb = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LB; 10.349 +assign op_lbu = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LBU; 10.350 +assign op_lh = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LH; 10.351 +assign op_lhu = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LHU; 10.352 +assign op_lw = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LW; 10.353 +`ifdef CFG_MC_DIVIDE_ENABLED 10.354 +assign op_modu = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_MODU; 10.355 +`endif 10.356 +`ifdef LM32_MULTIPLY_ENABLED 10.357 +assign op_mul = instruction[`LM32_OP_RNG] == `LM32_OPCODE_MUL; 10.358 +`endif 10.359 +assign op_nor = instruction[`LM32_OP_RNG] == `LM32_OPCODE_NOR; 10.360 +assign op_or = instruction[`LM32_OP_RNG] == `LM32_OPCODE_OR; 10.361 +assign op_orhi = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_ORHI; 10.362 +assign op_raise = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_RAISE; 10.363 +assign op_rcsr = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_RCSR; 10.364 +assign op_sb = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SB; 10.365 +`ifdef CFG_SIGN_EXTEND_ENABLED 10.366 +assign op_sextb = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SEXTB; 10.367 +assign op_sexth = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SEXTH; 10.368 +`endif 10.369 +assign op_sh = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SH; 10.370 +`ifdef LM32_BARREL_SHIFT_ENABLED 10.371 +assign op_sl = instruction[`LM32_OP_RNG] == `LM32_OPCODE_SL; 10.372 +`endif 10.373 +assign op_sr = instruction[`LM32_OP_RNG] == `LM32_OPCODE_SR; 10.374 +assign op_sru = instruction[`LM32_OP_RNG] == `LM32_OPCODE_SRU; 10.375 +assign op_sub = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SUB; 10.376 +assign op_sw = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SW; 10.377 +assign op_user = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_USER; 10.378 +assign op_wcsr = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_WCSR; 10.379 +assign op_xnor = instruction[`LM32_OP_RNG] == `LM32_OPCODE_XNOR; 10.380 +assign op_xor = instruction[`LM32_OP_RNG] == `LM32_OPCODE_XOR; 10.381 + 10.382 +// Group opcodes by function 10.383 +assign arith = op_add | op_sub; 10.384 +assign logical = op_and | op_andhi | op_nor | op_or | op_orhi | op_xor | op_xnor; 10.385 +assign cmp = op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne; 10.386 +assign bi_conditional = op_be | op_bg | op_bge | op_bgeu | op_bgu | op_bne; 10.387 +assign bi_unconditional = op_bi; 10.388 +assign bra = op_b | bi_unconditional | bi_conditional; 10.389 +assign call = op_call | op_calli; 10.390 +`ifdef LM32_BARREL_SHIFT_ENABLED 10.391 +assign shift = op_sl | op_sr | op_sru; 10.392 +`endif 10.393 +`ifdef LM32_NO_BARREL_SHIFT 10.394 +assign shift = op_sr | op_sru; 10.395 +`endif 10.396 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED 10.397 +assign shift_left = op_sl; 10.398 +assign shift_right = op_sr | op_sru; 10.399 +`endif 10.400 +`ifdef CFG_SIGN_EXTEND_ENABLED 10.401 +assign sext = op_sextb | op_sexth; 10.402 +`endif 10.403 +`ifdef LM32_MULTIPLY_ENABLED 10.404 +assign multiply = op_mul; 10.405 +`endif 10.406 +`ifdef CFG_MC_DIVIDE_ENABLED 10.407 +assign divide = op_divu; 10.408 +assign modulus = op_modu; 10.409 +`endif 10.410 +assign load = op_lb | op_lbu | op_lh | op_lhu | op_lw; 10.411 +assign store = op_sb | op_sh | op_sw; 10.412 + 10.413 +// Select pipeline multiplexor controls 10.414 +always @(*) 10.415 +begin 10.416 + // D stage 10.417 + if (call) 10.418 + d_result_sel_0 = `LM32_D_RESULT_SEL_0_NEXT_PC; 10.419 + else 10.420 + d_result_sel_0 = `LM32_D_RESULT_SEL_0_REG_0; 10.421 + if (call) 10.422 + d_result_sel_1 = `LM32_D_RESULT_SEL_1_ZERO; 10.423 + else if ((instruction[31] == 1'b0) && !bra) 10.424 + d_result_sel_1 = `LM32_D_RESULT_SEL_1_IMMEDIATE; 10.425 + else 10.426 + d_result_sel_1 = `LM32_D_RESULT_SEL_1_REG_1; 10.427 + // X stage 10.428 + x_result_sel_csr = `FALSE; 10.429 +`ifdef LM32_MC_ARITHMETIC_ENABLED 10.430 + x_result_sel_mc_arith = `FALSE; 10.431 +`endif 10.432 +`ifdef LM32_NO_BARREL_SHIFT 10.433 + x_result_sel_shift = `FALSE; 10.434 +`endif 10.435 +`ifdef CFG_SIGN_EXTEND_ENABLED 10.436 + x_result_sel_sext = `FALSE; 10.437 +`endif 10.438 + x_result_sel_logic = `FALSE; 10.439 +`ifdef CFG_USER_ENABLED 10.440 + x_result_sel_user = `FALSE; 10.441 +`endif 10.442 + x_result_sel_add = `FALSE; 10.443 + if (op_rcsr) 10.444 + x_result_sel_csr = `TRUE; 10.445 +`ifdef LM32_MC_ARITHMETIC_ENABLED 10.446 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED 10.447 + else if (shift_left | shift_right) 10.448 + x_result_sel_mc_arith = `TRUE; 10.449 +`endif 10.450 +`ifdef CFG_MC_DIVIDE_ENABLED 10.451 + else if (divide | modulus) 10.452 + x_result_sel_mc_arith = `TRUE; 10.453 +`endif 10.454 +`ifdef CFG_MC_MULTIPLY_ENABLED 10.455 + else if (multiply) 10.456 + x_result_sel_mc_arith = `TRUE; 10.457 +`endif 10.458 +`endif 10.459 +`ifdef LM32_NO_BARREL_SHIFT 10.460 + else if (shift) 10.461 + x_result_sel_shift = `TRUE; 10.462 +`endif 10.463 +`ifdef CFG_SIGN_EXTEND_ENABLED 10.464 + else if (sext) 10.465 + x_result_sel_sext = `TRUE; 10.466 +`endif 10.467 + else if (logical) 10.468 + x_result_sel_logic = `TRUE; 10.469 +`ifdef CFG_USER_ENABLED 10.470 + else if (op_user) 10.471 + x_result_sel_user = `TRUE; 10.472 +`endif 10.473 + else 10.474 + x_result_sel_add = `TRUE; 10.475 + 10.476 + // M stage 10.477 + 10.478 + m_result_sel_compare = cmp; 10.479 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 10.480 + m_result_sel_shift = shift; 10.481 +`endif 10.482 + 10.483 + // W stage 10.484 + w_result_sel_load = load; 10.485 +`ifdef CFG_PL_MULTIPLY_ENABLED 10.486 + w_result_sel_mul = op_mul; 10.487 +`endif 10.488 +end 10.489 + 10.490 +// Set if result is valid at end of X stage 10.491 +assign x_bypass_enable = arith 10.492 + | logical 10.493 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED 10.494 + | shift_left 10.495 + | shift_right 10.496 +`endif 10.497 +`ifdef CFG_MC_MULTIPLY_ENABLED 10.498 + | multiply 10.499 +`endif 10.500 +`ifdef CFG_MC_DIVIDE_ENABLED 10.501 + | divide 10.502 + | modulus 10.503 +`endif 10.504 +`ifdef LM32_NO_BARREL_SHIFT 10.505 + | shift 10.506 +`endif 10.507 +`ifdef CFG_SIGN_EXTEND_ENABLED 10.508 + | sext 10.509 +`endif 10.510 +`ifdef CFG_USER_ENABLED 10.511 + | op_user 10.512 +`endif 10.513 + | op_rcsr 10.514 + ; 10.515 +// Set if result is valid at end of M stage 10.516 +assign m_bypass_enable = x_bypass_enable 10.517 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 10.518 + | shift 10.519 +`endif 10.520 + | cmp 10.521 + ; 10.522 +// Register file read port 0 10.523 +assign read_enable_0 = ~(op_bi | op_calli); 10.524 +assign read_idx_0 = instruction[25:21]; 10.525 +// Register file read port 1 10.526 +assign read_enable_1 = ~(op_bi | op_calli | load); 10.527 +assign read_idx_1 = instruction[20:16]; 10.528 +// Register file write port 10.529 +assign write_enable = ~(bra | op_raise | store | op_wcsr); 10.530 +assign write_idx = call 10.531 + ? 5'd29 10.532 + : instruction[31] == 1'b0 10.533 + ? instruction[20:16] 10.534 + : instruction[15:11]; 10.535 + 10.536 +// Size of load/stores 10.537 +assign size = instruction[27:26]; 10.538 +// Whether to sign or zero extend 10.539 +assign sign_extend = instruction[28]; 10.540 +// Set adder_op to 1 to perform a subtraction 10.541 +assign adder_op = op_sub | op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne | bra; 10.542 +// Logic operation (and, or, etc) 10.543 +assign logic_op = instruction[29:26]; 10.544 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 10.545 +// Shift direction 10.546 +assign direction = instruction[29]; 10.547 +`endif 10.548 +// Control flow microcodes 10.549 +assign branch = bra | call; 10.550 +assign branch_reg = op_call | op_b; 10.551 +assign condition = instruction[28:26]; 10.552 +`ifdef CFG_DEBUG_ENABLED 10.553 +assign break_opcode = op_raise & ~instruction[2]; 10.554 +`endif 10.555 +assign scall = op_raise & instruction[2]; 10.556 +assign eret = op_b & (instruction[25:21] == 5'd30); 10.557 +`ifdef CFG_DEBUG_ENABLED 10.558 +assign bret = op_b & (instruction[25:21] == 5'd31); 10.559 +`endif 10.560 +`ifdef CFG_USER_ENABLED 10.561 +// Extract user opcode 10.562 +assign user_opcode = instruction[10:0]; 10.563 +`endif 10.564 +// CSR read/write 10.565 +assign csr_write_enable = op_wcsr; 10.566 + 10.567 +// Extract immediate from instruction 10.568 + 10.569 +assign sign_extend_immediate = ~(op_and | op_cmpgeu | op_cmpgu | op_nor | op_or | op_xnor | op_xor); 10.570 +assign select_high_immediate = op_andhi | op_orhi; 10.571 +assign select_call_immediate = instruction[31]; 10.572 + 10.573 +assign high_immediate = {instruction[15:0], 16'h0000}; 10.574 +assign extended_immediate = {{16{sign_extend_immediate & instruction[15]}}, instruction[15:0]}; 10.575 +assign call_immediate = {{6{instruction[25]}}, instruction[25:0]}; 10.576 +assign branch_immediate = {{16{instruction[15]}}, instruction[15:0]}; 10.577 + 10.578 +assign immediate = select_high_immediate == `TRUE 10.579 + ? high_immediate 10.580 + : extended_immediate; 10.581 + 10.582 +assign branch_offset = select_call_immediate == `TRUE 10.583 + ? call_immediate 10.584 + : branch_immediate; 10.585 + 10.586 +endmodule 10.587 +
11.1 diff -r 000000000000 -r cd0b58aa6f83 lm32_functions.v 11.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 11.3 +++ b/lm32_functions.v Sun Apr 04 20:40:03 2010 +0100 11.4 @@ -0,0 +1,49 @@ 11.5 +// ============================================================================= 11.6 +// COPYRIGHT NOTICE 11.7 +// Copyright 2006 (c) Lattice Semiconductor Corporation 11.8 +// ALL RIGHTS RESERVED 11.9 +// This confidential and proprietary software may be used only as authorised by 11.10 +// a licensing agreement from Lattice Semiconductor Corporation. 11.11 +// The entire notice above must be reproduced on all authorized copies and 11.12 +// copies may only be made to the extent permitted by a licensing agreement from 11.13 +// Lattice Semiconductor Corporation. 11.14 +// 11.15 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 11.16 +// 5555 NE Moore Court 408-826-6000 (other locations) 11.17 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 11.18 +// U.S.A email: techsupport@latticesemi.com 11.19 +// =============================================================================/ 11.20 +// FILE DETAILS 11.21 +// Project : LatticeMico32 11.22 +// File : lm32_functions.v 11.23 +// Title : Common functions 11.24 +// Version : 6.1.17 11.25 +// : Initial Release 11.26 +// Version : 7.0SP2, 3.0 11.27 +// : No Change 11.28 +// Version : 3.5 11.29 +// : Added function to generate log-of-two that rounds-up to 11.30 +// : power-of-two 11.31 +// ============================================================================= 11.32 + 11.33 +function integer clogb2; 11.34 +input [31:0] value; 11.35 +begin 11.36 + for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) 11.37 + value = value >> 1; 11.38 +end 11.39 +endfunction 11.40 + 11.41 +function integer clogb2_v1; 11.42 +input [31:0] value; 11.43 +reg [31:0] i; 11.44 +reg [31:0] temp; 11.45 +begin 11.46 + temp = 0; 11.47 + i = 0; 11.48 + for (i = 0; temp < value; i = i + 1) 11.49 + temp = 1<<i; 11.50 + clogb2_v1 = i-1; 11.51 +end 11.52 +endfunction 11.53 +
12.1 diff -r 000000000000 -r cd0b58aa6f83 lm32_icache.v 12.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 12.3 +++ b/lm32_icache.v Sun Apr 04 20:40:03 2010 +0100 12.4 @@ -0,0 +1,488 @@ 12.5 +// ============================================================================= 12.6 +// COPYRIGHT NOTICE 12.7 +// Copyright 2006 (c) Lattice Semiconductor Corporation 12.8 +// ALL RIGHTS RESERVED 12.9 +// This confidential and proprietary software may be used only as authorised by 12.10 +// a licensing agreement from Lattice Semiconductor Corporation. 12.11 +// The entire notice above must be reproduced on all authorized copies and 12.12 +// copies may only be made to the extent permitted by a licensing agreement from 12.13 +// Lattice Semiconductor Corporation. 12.14 +// 12.15 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 12.16 +// 5555 NE Moore Court 408-826-6000 (other locations) 12.17 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 12.18 +// U.S.A email: techsupport@latticesemi.com 12.19 +// =============================================================================/ 12.20 +// FILE DETAILS 12.21 +// Project : LatticeMico32 12.22 +// File : lm32_icache.v 12.23 +// Title : Instruction cache 12.24 +// Dependencies : lm32_include.v 12.25 +// 12.26 +// Version 3.5 12.27 +// 1. Bug Fix: Instruction cache flushes issued from Instruction Inline Memory 12.28 +// cause segmentation fault due to incorrect fetches. 12.29 +// 12.30 +// Version 3.1 12.31 +// 1. Feature: Support for user-selected resource usage when implementing 12.32 +// cache memory. Additional parameters must be defined when invoking module 12.33 +// lm32_ram. Instruction cache miss mechanism is dependent on branch 12.34 +// prediction being performed in D stage of pipeline. 12.35 +// 12.36 +// Version 7.0SP2, 3.0 12.37 +// No change 12.38 +// ============================================================================= 12.39 + 12.40 +`include "lm32_include.v" 12.41 + 12.42 +`ifdef CFG_ICACHE_ENABLED 12.43 + 12.44 +`define LM32_IC_ADDR_OFFSET_RNG addr_offset_msb:addr_offset_lsb 12.45 +`define LM32_IC_ADDR_SET_RNG addr_set_msb:addr_set_lsb 12.46 +`define LM32_IC_ADDR_TAG_RNG addr_tag_msb:addr_tag_lsb 12.47 +`define LM32_IC_ADDR_IDX_RNG addr_set_msb:addr_offset_lsb 12.48 + 12.49 +`define LM32_IC_TMEM_ADDR_WIDTH addr_set_width 12.50 +`define LM32_IC_TMEM_ADDR_RNG (`LM32_IC_TMEM_ADDR_WIDTH-1):0 12.51 +`define LM32_IC_DMEM_ADDR_WIDTH (addr_offset_width+addr_set_width) 12.52 +`define LM32_IC_DMEM_ADDR_RNG (`LM32_IC_DMEM_ADDR_WIDTH-1):0 12.53 + 12.54 +`define LM32_IC_TAGS_WIDTH (addr_tag_width+1) 12.55 +`define LM32_IC_TAGS_RNG (`LM32_IC_TAGS_WIDTH-1):0 12.56 +`define LM32_IC_TAGS_TAG_RNG (`LM32_IC_TAGS_WIDTH-1):1 12.57 +`define LM32_IC_TAGS_VALID_RNG 0 12.58 + 12.59 +`define LM32_IC_STATE_RNG 3:0 12.60 +`define LM32_IC_STATE_FLUSH_INIT 4'b0001 12.61 +`define LM32_IC_STATE_FLUSH 4'b0010 12.62 +`define LM32_IC_STATE_CHECK 4'b0100 12.63 +`define LM32_IC_STATE_REFILL 4'b1000 12.64 + 12.65 +///////////////////////////////////////////////////// 12.66 +// Module interface 12.67 +///////////////////////////////////////////////////// 12.68 + 12.69 +module lm32_icache ( 12.70 + // ----- Inputs ----- 12.71 + clk_i, 12.72 + rst_i, 12.73 + stall_a, 12.74 + stall_f, 12.75 + address_a, 12.76 + address_f, 12.77 + read_enable_f, 12.78 + refill_ready, 12.79 + refill_data, 12.80 + iflush, 12.81 +`ifdef CFG_IROM_ENABLED 12.82 + select_f, 12.83 +`endif 12.84 + valid_d, 12.85 + branch_predict_taken_d, 12.86 + // ----- Outputs ----- 12.87 + stall_request, 12.88 + restart_request, 12.89 + refill_request, 12.90 + refill_address, 12.91 + refilling, 12.92 + inst 12.93 + ); 12.94 + 12.95 +///////////////////////////////////////////////////// 12.96 +// Parameters 12.97 +///////////////////////////////////////////////////// 12.98 + 12.99 +parameter associativity = 1; // Associativity of the cache (Number of ways) 12.100 +parameter sets = 512; // Number of sets 12.101 +parameter bytes_per_line = 16; // Number of bytes per cache line 12.102 +parameter base_address = 0; // Base address of cachable memory 12.103 +parameter limit = 0; // Limit (highest address) of cachable memory 12.104 + 12.105 +localparam addr_offset_width = clogb2(bytes_per_line)-1-2; 12.106 +localparam addr_set_width = clogb2(sets)-1; 12.107 +localparam addr_offset_lsb = 2; 12.108 +localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1); 12.109 +localparam addr_set_lsb = (addr_offset_msb+1); 12.110 +localparam addr_set_msb = (addr_set_lsb+addr_set_width-1); 12.111 +localparam addr_tag_lsb = (addr_set_msb+1); 12.112 +localparam addr_tag_msb = clogb2(`CFG_ICACHE_LIMIT-`CFG_ICACHE_BASE_ADDRESS)-1; 12.113 +localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1); 12.114 + 12.115 +///////////////////////////////////////////////////// 12.116 +// Inputs 12.117 +///////////////////////////////////////////////////// 12.118 + 12.119 +input clk_i; // Clock 12.120 +input rst_i; // Reset 12.121 + 12.122 +input stall_a; // Stall instruction in A stage 12.123 +input stall_f; // Stall instruction in F stage 12.124 + 12.125 +input valid_d; // Valid instruction in D stage 12.126 +input branch_predict_taken_d; // Instruction in D stage is a branch and is predicted taken 12.127 + 12.128 +input [`LM32_PC_RNG] address_a; // Address of instruction in A stage 12.129 +input [`LM32_PC_RNG] address_f; // Address of instruction in F stage 12.130 +input read_enable_f; // Indicates if cache access is valid 12.131 + 12.132 +input refill_ready; // Next word of refill data is ready 12.133 +input [`LM32_INSTRUCTION_RNG] refill_data; // Data to refill the cache with 12.134 + 12.135 +input iflush; // Flush the cache 12.136 +`ifdef CFG_IROM_ENABLED 12.137 +input select_f; // Instruction in F stage is mapped through instruction cache 12.138 +`endif 12.139 + 12.140 +///////////////////////////////////////////////////// 12.141 +// Outputs 12.142 +///////////////////////////////////////////////////// 12.143 + 12.144 +output stall_request; // Request to stall the pipeline 12.145 +wire stall_request; 12.146 +output restart_request; // Request to restart instruction that caused the cache miss 12.147 +reg restart_request; 12.148 +output refill_request; // Request to refill a cache line 12.149 +wire refill_request; 12.150 +output [`LM32_PC_RNG] refill_address; // Base address of cache refill 12.151 +reg [`LM32_PC_RNG] refill_address; 12.152 +output refilling; // Indicates the instruction cache is currently refilling 12.153 +reg refilling; 12.154 +output [`LM32_INSTRUCTION_RNG] inst; // Instruction read from cache 12.155 +wire [`LM32_INSTRUCTION_RNG] inst; 12.156 + 12.157 +///////////////////////////////////////////////////// 12.158 +// Internal nets and registers 12.159 +///////////////////////////////////////////////////// 12.160 + 12.161 +wire enable; 12.162 +wire [0:associativity-1] way_mem_we; 12.163 +wire [`LM32_INSTRUCTION_RNG] way_data[0:associativity-1]; 12.164 +wire [`LM32_IC_TAGS_TAG_RNG] way_tag[0:associativity-1]; 12.165 +wire [0:associativity-1] way_valid; 12.166 +wire [0:associativity-1] way_match; 12.167 +wire miss; 12.168 + 12.169 +wire [`LM32_IC_TMEM_ADDR_RNG] tmem_read_address; 12.170 +wire [`LM32_IC_TMEM_ADDR_RNG] tmem_write_address; 12.171 +wire [`LM32_IC_DMEM_ADDR_RNG] dmem_read_address; 12.172 +wire [`LM32_IC_DMEM_ADDR_RNG] dmem_write_address; 12.173 +wire [`LM32_IC_TAGS_RNG] tmem_write_data; 12.174 + 12.175 +reg [`LM32_IC_STATE_RNG] state; 12.176 +wire flushing; 12.177 +wire check; 12.178 +wire refill; 12.179 + 12.180 +reg [associativity-1:0] refill_way_select; 12.181 +reg [`LM32_IC_ADDR_OFFSET_RNG] refill_offset; 12.182 +wire last_refill; 12.183 +reg [`LM32_IC_TMEM_ADDR_RNG] flush_set; 12.184 + 12.185 +genvar i; 12.186 + 12.187 +///////////////////////////////////////////////////// 12.188 +// Functions 12.189 +///////////////////////////////////////////////////// 12.190 + 12.191 +`include "lm32_functions.v" 12.192 + 12.193 +///////////////////////////////////////////////////// 12.194 +// Instantiations 12.195 +///////////////////////////////////////////////////// 12.196 + 12.197 + generate 12.198 + for (i = 0; i < associativity; i = i + 1) 12.199 + begin : memories 12.200 + 12.201 + lm32_ram 12.202 + #( 12.203 + // ----- Parameters ------- 12.204 + .data_width (32), 12.205 + .address_width (`LM32_IC_DMEM_ADDR_WIDTH), 12.206 +`ifdef CFG_ICACHE_DAT_USE_DP_TRUE 12.207 + .RAM_IMPLEMENTATION ("EBR"), 12.208 + .RAM_TYPE ("RAM_DP_TRUE") 12.209 +`else 12.210 + `ifdef CFG_ICACHE_DAT_USE_DP 12.211 + .RAM_IMPLEMENTATION ("EBR"), 12.212 + .RAM_TYPE ("RAM_DP") 12.213 + `else 12.214 + `ifdef CFG_ICACHE_DAT_USE_SLICE 12.215 + .RAM_IMPLEMENTATION ("SLICE") 12.216 + `else 12.217 + .RAM_IMPLEMENTATION ("AUTO") 12.218 + `endif 12.219 + `endif 12.220 +`endif 12.221 + ) 12.222 + way_0_data_ram 12.223 + ( 12.224 + // ----- Inputs ------- 12.225 + .read_clk (clk_i), 12.226 + .write_clk (clk_i), 12.227 + .reset (rst_i), 12.228 + .read_address (dmem_read_address), 12.229 + .enable_read (enable), 12.230 + .write_address (dmem_write_address), 12.231 + .enable_write (`TRUE), 12.232 + .write_enable (way_mem_we[i]), 12.233 + .write_data (refill_data), 12.234 + // ----- Outputs ------- 12.235 + .read_data (way_data[i]) 12.236 + ); 12.237 + 12.238 + lm32_ram 12.239 + #( 12.240 + // ----- Parameters ------- 12.241 + .data_width (`LM32_IC_TAGS_WIDTH), 12.242 + .address_width (`LM32_IC_TMEM_ADDR_WIDTH), 12.243 +`ifdef CFG_ICACHE_DAT_USE_DP_TRUE 12.244 + .RAM_IMPLEMENTATION ("EBR"), 12.245 + .RAM_TYPE ("RAM_DP_TRUE") 12.246 +`else 12.247 + `ifdef CFG_ICACHE_DAT_USE_DP 12.248 + .RAM_IMPLEMENTATION ("EBR"), 12.249 + .RAM_TYPE ("RAM_DP") 12.250 + `else 12.251 + `ifdef CFG_ICACHE_DAT_USE_SLICE 12.252 + .RAM_IMPLEMENTATION ("SLICE") 12.253 + `else 12.254 + .RAM_IMPLEMENTATION ("AUTO") 12.255 + `endif 12.256 + `endif 12.257 +`endif 12.258 + ) 12.259 + way_0_tag_ram 12.260 + ( 12.261 + // ----- Inputs ------- 12.262 + .read_clk (clk_i), 12.263 + .write_clk (clk_i), 12.264 + .reset (rst_i), 12.265 + .read_address (tmem_read_address), 12.266 + .enable_read (enable), 12.267 + .write_address (tmem_write_address), 12.268 + .enable_write (`TRUE), 12.269 + .write_enable (way_mem_we[i] | flushing), 12.270 + .write_data (tmem_write_data), 12.271 + // ----- Outputs ------- 12.272 + .read_data ({way_tag[i], way_valid[i]}) 12.273 + ); 12.274 + 12.275 + end 12.276 +endgenerate 12.277 + 12.278 +///////////////////////////////////////////////////// 12.279 +// Combinational logic 12.280 +///////////////////////////////////////////////////// 12.281 + 12.282 +// Compute which ways in the cache match the address address being read 12.283 +generate 12.284 + for (i = 0; i < associativity; i = i + 1) 12.285 + begin : match 12.286 +assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_f[`LM32_IC_ADDR_TAG_RNG], `TRUE}); 12.287 + end 12.288 +endgenerate 12.289 + 12.290 +// Select data from way that matched the address being read 12.291 +generate 12.292 + if (associativity == 1) 12.293 + begin : inst_1 12.294 +assign inst = way_match[0] ? way_data[0] : 32'b0; 12.295 + end 12.296 + else if (associativity == 2) 12.297 + begin : inst_2 12.298 +assign inst = way_match[0] ? way_data[0] : (way_match[1] ? way_data[1] : 32'b0); 12.299 + end 12.300 +endgenerate 12.301 + 12.302 +// Compute address to use to index into the data memories 12.303 +generate 12.304 + if (bytes_per_line > 4) 12.305 +assign dmem_write_address = {refill_address[`LM32_IC_ADDR_SET_RNG], refill_offset}; 12.306 + else 12.307 +assign dmem_write_address = refill_address[`LM32_IC_ADDR_SET_RNG]; 12.308 +endgenerate 12.309 + 12.310 +assign dmem_read_address = address_a[`LM32_IC_ADDR_IDX_RNG]; 12.311 + 12.312 +// Compute address to use to index into the tag memories 12.313 +assign tmem_read_address = address_a[`LM32_IC_ADDR_SET_RNG]; 12.314 +assign tmem_write_address = flushing 12.315 + ? flush_set 12.316 + : refill_address[`LM32_IC_ADDR_SET_RNG]; 12.317 + 12.318 +// Compute signal to indicate when we are on the last refill accesses 12.319 +generate 12.320 + if (bytes_per_line > 4) 12.321 +assign last_refill = refill_offset == {addr_offset_width{1'b1}}; 12.322 + else 12.323 +assign last_refill = `TRUE; 12.324 +endgenerate 12.325 + 12.326 +// Compute data and tag memory access enable 12.327 +assign enable = (stall_a == `FALSE); 12.328 + 12.329 +// Compute data and tag memory write enables 12.330 +generate 12.331 + if (associativity == 1) 12.332 + begin : we_1 12.333 +assign way_mem_we[0] = (refill_ready == `TRUE); 12.334 + end 12.335 + else 12.336 + begin : we_2 12.337 +assign way_mem_we[0] = (refill_ready == `TRUE) && (refill_way_select[0] == `TRUE); 12.338 +assign way_mem_we[1] = (refill_ready == `TRUE) && (refill_way_select[1] == `TRUE); 12.339 + end 12.340 +endgenerate 12.341 + 12.342 +// On the last refill cycle set the valid bit, for all other writes it should be cleared 12.343 +assign tmem_write_data[`LM32_IC_TAGS_VALID_RNG] = last_refill & !flushing; 12.344 +assign tmem_write_data[`LM32_IC_TAGS_TAG_RNG] = refill_address[`LM32_IC_ADDR_TAG_RNG]; 12.345 + 12.346 +// Signals that indicate which state we are in 12.347 +assign flushing = |state[1:0]; 12.348 +assign check = state[2]; 12.349 +assign refill = state[3]; 12.350 + 12.351 +assign miss = (~(|way_match)) && (read_enable_f == `TRUE) && (stall_f == `FALSE) && !(valid_d && branch_predict_taken_d); 12.352 +assign stall_request = (check == `FALSE); 12.353 +assign refill_request = (refill == `TRUE); 12.354 + 12.355 +///////////////////////////////////////////////////// 12.356 +// Sequential logic 12.357 +///////////////////////////////////////////////////// 12.358 + 12.359 +// Record way selected for replacement on a cache miss 12.360 +generate 12.361 + if (associativity >= 2) 12.362 + begin : way_select 12.363 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 12.364 +begin 12.365 + if (rst_i == `TRUE) 12.366 + refill_way_select <= {{associativity-1{1'b0}}, 1'b1}; 12.367 + else 12.368 + begin 12.369 + if (miss == `TRUE) 12.370 + refill_way_select <= {refill_way_select[0], refill_way_select[1]}; 12.371 + end 12.372 +end 12.373 + end 12.374 +endgenerate 12.375 + 12.376 +// Record whether we are refilling 12.377 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 12.378 +begin 12.379 + if (rst_i == `TRUE) 12.380 + refilling <= `FALSE; 12.381 + else 12.382 + refilling <= refill; 12.383 +end 12.384 + 12.385 +// Instruction cache control FSM 12.386 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 12.387 +begin 12.388 + if (rst_i == `TRUE) 12.389 + begin 12.390 + state <= `LM32_IC_STATE_FLUSH_INIT; 12.391 + flush_set <= {`LM32_IC_TMEM_ADDR_WIDTH{1'b1}}; 12.392 + refill_address <= {`LM32_PC_WIDTH{1'bx}}; 12.393 + restart_request <= `FALSE; 12.394 + end 12.395 + else 12.396 + begin 12.397 + case (state) 12.398 + 12.399 + // Flush the cache for the first time after reset 12.400 + `LM32_IC_STATE_FLUSH_INIT: 12.401 + begin 12.402 + if (flush_set == {`LM32_IC_TMEM_ADDR_WIDTH{1'b0}}) 12.403 + state <= `LM32_IC_STATE_CHECK; 12.404 + flush_set <= flush_set - 1'b1; 12.405 + end 12.406 + 12.407 + // Flush the cache in response to an write to the ICC CSR 12.408 + `LM32_IC_STATE_FLUSH: 12.409 + begin 12.410 + if (flush_set == {`LM32_IC_TMEM_ADDR_WIDTH{1'b0}}) 12.411 +`ifdef CFG_IROM_ENABLED 12.412 + if (select_f) 12.413 + state <= `LM32_IC_STATE_REFILL; 12.414 + else 12.415 +`endif 12.416 + state <= `LM32_IC_STATE_CHECK; 12.417 + 12.418 + flush_set <= flush_set - 1'b1; 12.419 + end 12.420 + 12.421 + // Check for cache misses 12.422 + `LM32_IC_STATE_CHECK: 12.423 + begin 12.424 + if (stall_a == `FALSE) 12.425 + restart_request <= `FALSE; 12.426 + if (iflush == `TRUE) 12.427 + begin 12.428 + refill_address <= address_f; 12.429 + state <= `LM32_IC_STATE_FLUSH; 12.430 + end 12.431 + else if (miss == `TRUE) 12.432 + begin 12.433 + refill_address <= address_f; 12.434 + state <= `LM32_IC_STATE_REFILL; 12.435 + end 12.436 + end 12.437 + 12.438 + // Refill a cache line 12.439 + `LM32_IC_STATE_REFILL: 12.440 + begin 12.441 + if (refill_ready == `TRUE) 12.442 + begin 12.443 + if (last_refill == `TRUE) 12.444 + begin 12.445 + restart_request <= `TRUE; 12.446 + state <= `LM32_IC_STATE_CHECK; 12.447 + end 12.448 + end 12.449 + end 12.450 + 12.451 + endcase 12.452 + end 12.453 +end 12.454 + 12.455 +generate 12.456 + if (bytes_per_line > 4) 12.457 + begin 12.458 +// Refill offset 12.459 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 12.460 +begin 12.461 + if (rst_i == `TRUE) 12.462 + refill_offset <= {addr_offset_width{1'b0}}; 12.463 + else 12.464 + begin 12.465 + case (state) 12.466 + 12.467 + // Check for cache misses 12.468 + `LM32_IC_STATE_CHECK: 12.469 + begin 12.470 + if (iflush == `TRUE) 12.471 + refill_offset <= {addr_offset_width{1'b0}}; 12.472 + else if (miss == `TRUE) 12.473 + refill_offset <= {addr_offset_width{1'b0}}; 12.474 + end 12.475 + 12.476 + // Refill a cache line 12.477 + `LM32_IC_STATE_REFILL: 12.478 + begin 12.479 + if (refill_ready == `TRUE) 12.480 + refill_offset <= refill_offset + 1'b1; 12.481 + end 12.482 + 12.483 + endcase 12.484 + end 12.485 +end 12.486 + end 12.487 +endgenerate 12.488 + 12.489 +endmodule 12.490 + 12.491 +`endif 12.492 +
13.1 diff -r 000000000000 -r cd0b58aa6f83 lm32_include.v 13.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 13.3 +++ b/lm32_include.v Sun Apr 04 20:40:03 2010 +0100 13.4 @@ -0,0 +1,329 @@ 13.5 +// ============================================================================= 13.6 +// COPYRIGHT NOTICE 13.7 +// Copyright 2006 (c) Lattice Semiconductor Corporation 13.8 +// ALL RIGHTS RESERVED 13.9 +// This confidential and proprietary software may be used only as authorised by 13.10 +// a licensing agreement from Lattice Semiconductor Corporation. 13.11 +// The entire notice above must be reproduced on all authorized copies and 13.12 +// copies may only be made to the extent permitted by a licensing agreement from 13.13 +// Lattice Semiconductor Corporation. 13.14 +// 13.15 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 13.16 +// 5555 NE Moore Court 408-826-6000 (other locations) 13.17 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 13.18 +// U.S.A email: techsupport@latticesemi.com 13.19 +// =============================================================================/ 13.20 +// FILE DETAILS 13.21 +// Project : LatticeMico32 13.22 +// File : lm32_include.v 13.23 +// Title : CPU global macros 13.24 +// Version : 6.1.17 13.25 +// : Initial Release 13.26 +// Version : 7.0SP2, 3.0 13.27 +// : No Change 13.28 +// Version : 3.1 13.29 +// : No Change 13.30 +// Version : 3.2 13.31 +// : No Change 13.32 +// Version : 3.3 13.33 +// : Support for extended configuration register 13.34 +// ============================================================================= 13.35 + 13.36 +`ifdef LM32_INCLUDE_V 13.37 +`else 13.38 +`define LM32_INCLUDE_V 13.39 + 13.40 +// Configuration options 13.41 +`include "system_conf.v" 13.42 + 13.43 +`ifdef TRUE 13.44 +`else 13.45 +`define TRUE 1'b1 13.46 +`define FALSE 1'b0 13.47 +`define TRUE_N 1'b0 13.48 +`define FALSE_N 1'b1 13.49 +`endif 13.50 + 13.51 +// Wishbone configuration 13.52 +`define CFG_IWB_ENABLED 13.53 +`define CFG_DWB_ENABLED 13.54 + 13.55 +// Data-path width 13.56 +`define LM32_WORD_WIDTH 32 13.57 +`define LM32_WORD_RNG (`LM32_WORD_WIDTH-1):0 13.58 +`define LM32_SHIFT_WIDTH 5 13.59 +`define LM32_SHIFT_RNG (`LM32_SHIFT_WIDTH-1):0 13.60 +`define LM32_BYTE_SELECT_WIDTH 4 13.61 +`define LM32_BYTE_SELECT_RNG (`LM32_BYTE_SELECT_WIDTH-1):0 13.62 + 13.63 +// Register file size 13.64 +`define LM32_REGISTERS 32 13.65 +`define LM32_REG_IDX_WIDTH 5 13.66 +`define LM32_REG_IDX_RNG (`LM32_REG_IDX_WIDTH-1):0 13.67 + 13.68 +// Standard register numbers 13.69 +`define LM32_RA_REG `LM32_REG_IDX_WIDTH'd29 13.70 +`define LM32_EA_REG `LM32_REG_IDX_WIDTH'd30 13.71 +`define LM32_BA_REG `LM32_REG_IDX_WIDTH'd31 13.72 + 13.73 +// Range of Program Counter. Two LSBs are always 0. 13.74 +// `ifdef CFG_ICACHE_ENABLED 13.75 +// `define LM32_PC_WIDTH (clogb2(`CFG_ICACHE_LIMIT-`CFG_ICACHE_BASE_ADDRESS)-2) 13.76 +// `else 13.77 +// `ifdef CFG_IWB_ENABLED 13.78 +`define LM32_PC_WIDTH (`LM32_WORD_WIDTH-2) 13.79 +// `else 13.80 +// `define LM32_PC_WIDTH `LM32_IROM_ADDRESS_WIDTH 13.81 +// `endif 13.82 +// `endif 13.83 +`define LM32_PC_RNG (`LM32_PC_WIDTH+2-1):2 13.84 + 13.85 +// Range of an instruction 13.86 +`define LM32_INSTRUCTION_WIDTH 32 13.87 +`define LM32_INSTRUCTION_RNG (`LM32_INSTRUCTION_WIDTH-1):0 13.88 + 13.89 +// Adder operation 13.90 +`define LM32_ADDER_OP_ADD 1'b0 13.91 +`define LM32_ADDER_OP_SUBTRACT 1'b1 13.92 + 13.93 +// Shift direction 13.94 +`define LM32_SHIFT_OP_RIGHT 1'b0 13.95 +`define LM32_SHIFT_OP_LEFT 1'b1 13.96 + 13.97 +// Currently always enabled 13.98 +`define CFG_BUS_ERRORS_ENABLED 13.99 + 13.100 +// Derive macro that indicates whether we have single-stepping or not 13.101 +`ifdef CFG_ROM_DEBUG_ENABLED 13.102 +`define LM32_SINGLE_STEP_ENABLED 13.103 +`else 13.104 +`ifdef CFG_HW_DEBUG_ENABLED 13.105 +`define LM32_SINGLE_STEP_ENABLED 13.106 +`endif 13.107 +`endif 13.108 + 13.109 +// Derive macro that indicates whether JTAG interface is required 13.110 +`ifdef CFG_JTAG_UART_ENABLED 13.111 +`define LM32_JTAG_ENABLED 13.112 +`else 13.113 +`ifdef CFG_DEBUG_ENABLED 13.114 +`define LM32_JTAG_ENABLED 13.115 +`else 13.116 +`endif 13.117 +`endif 13.118 + 13.119 +// Derive macro that indicates whether we have a barrel-shifter or not 13.120 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED 13.121 +`define LM32_BARREL_SHIFT_ENABLED 13.122 +`else // CFG_PL_BARREL_SHIFT_ENABLED 13.123 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED 13.124 +`define LM32_BARREL_SHIFT_ENABLED 13.125 +`else 13.126 +`define LM32_NO_BARREL_SHIFT 13.127 +`endif 13.128 +`endif // CFG_PL_BARREL_SHIFT_ENABLED 13.129 + 13.130 +// Derive macro that indicates whether we have a multiplier or not 13.131 +`ifdef CFG_PL_MULTIPLY_ENABLED 13.132 +`define LM32_MULTIPLY_ENABLED 13.133 +`else 13.134 +`ifdef CFG_MC_MULTIPLY_ENABLED 13.135 +`define LM32_MULTIPLY_ENABLED 13.136 +`endif 13.137 +`endif 13.138 + 13.139 +// Derive a macro that indicates whether or not the multi-cycle arithmetic unit is required 13.140 +`ifdef CFG_MC_DIVIDE_ENABLED 13.141 +`define LM32_MC_ARITHMETIC_ENABLED 13.142 +`endif 13.143 +`ifdef CFG_MC_MULTIPLY_ENABLED 13.144 +`define LM32_MC_ARITHMETIC_ENABLED 13.145 +`endif 13.146 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED 13.147 +`define LM32_MC_ARITHMETIC_ENABLED 13.148 +`endif 13.149 + 13.150 +// Derive macro that indicates if we are using an EBR register file 13.151 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE 13.152 +`define LM32_EBR_REGISTER_FILE 13.153 +`endif 13.154 +`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE 13.155 +`define LM32_EBR_REGISTER_FILE 13.156 +`endif 13.157 + 13.158 +// Revision number 13.159 +`define LM32_REVISION 6'h02 13.160 + 13.161 +// Logical operations - Function encoded directly in instruction 13.162 +`define LM32_LOGIC_OP_RNG 3:0 13.163 + 13.164 +// Conditions for conditional branches 13.165 +`define LM32_CONDITION_WIDTH 3 13.166 +`define LM32_CONDITION_RNG (`LM32_CONDITION_WIDTH-1):0 13.167 +`define LM32_CONDITION_E 3'b001 13.168 +`define LM32_CONDITION_G 3'b010 13.169 +`define LM32_CONDITION_GE 3'b011 13.170 +`define LM32_CONDITION_GEU 3'b100 13.171 +`define LM32_CONDITION_GU 3'b101 13.172 +`define LM32_CONDITION_NE 3'b111 13.173 +`define LM32_CONDITION_U1 3'b000 13.174 +`define LM32_CONDITION_U2 3'b110 13.175 + 13.176 +// Size of load or store instruction - Encoding corresponds to opcode 13.177 +`define LM32_SIZE_WIDTH 2 13.178 +`define LM32_SIZE_RNG 1:0 13.179 +`define LM32_SIZE_BYTE 2'b00 13.180 +`define LM32_SIZE_HWORD 2'b11 13.181 +`define LM32_SIZE_WORD 2'b10 13.182 +`define LM32_ADDRESS_LSBS_WIDTH 2 13.183 + 13.184 +// Width and range of a CSR index 13.185 +`ifdef CFG_DEBUG_ENABLED 13.186 +`define LM32_CSR_WIDTH 5 13.187 +`define LM32_CSR_RNG (`LM32_CSR_WIDTH-1):0 13.188 +`else 13.189 +`ifdef CFG_JTAG_ENABLED 13.190 +`define LM32_CSR_WIDTH 4 13.191 +`define LM32_CSR_RNG (`LM32_CSR_WIDTH-1):0 13.192 +`else 13.193 +`define LM32_CSR_WIDTH 3 13.194 +`define LM32_CSR_RNG (`LM32_CSR_WIDTH-1):0 13.195 +`endif 13.196 +`endif 13.197 + 13.198 +// CSR indices 13.199 +`define LM32_CSR_IE `LM32_CSR_WIDTH'h0 13.200 +`define LM32_CSR_IM `LM32_CSR_WIDTH'h1 13.201 +`define LM32_CSR_IP `LM32_CSR_WIDTH'h2 13.202 +`define LM32_CSR_ICC `LM32_CSR_WIDTH'h3 13.203 +`define LM32_CSR_DCC `LM32_CSR_WIDTH'h4 13.204 +`define LM32_CSR_CC `LM32_CSR_WIDTH'h5 13.205 +`define LM32_CSR_CFG `LM32_CSR_WIDTH'h6 13.206 +`define LM32_CSR_EBA `LM32_CSR_WIDTH'h7 13.207 +`ifdef CFG_DEBUG_ENABLED 13.208 +`define LM32_CSR_DC `LM32_CSR_WIDTH'h8 13.209 +`define LM32_CSR_DEBA `LM32_CSR_WIDTH'h9 13.210 +`endif 13.211 +`define LM32_CSR_CFG2 `LM32_CSR_WIDTH'ha 13.212 +`ifdef CFG_JTAG_ENABLED 13.213 +`define LM32_CSR_JTX `LM32_CSR_WIDTH'he 13.214 +`define LM32_CSR_JRX `LM32_CSR_WIDTH'hf 13.215 +`endif 13.216 +`ifdef CFG_DEBUG_ENABLED 13.217 +`define LM32_CSR_BP0 `LM32_CSR_WIDTH'h10 13.218 +`define LM32_CSR_BP1 `LM32_CSR_WIDTH'h11 13.219 +`define LM32_CSR_BP2 `LM32_CSR_WIDTH'h12 13.220 +`define LM32_CSR_BP3 `LM32_CSR_WIDTH'h13 13.221 +`define LM32_CSR_WP0 `LM32_CSR_WIDTH'h18 13.222 +`define LM32_CSR_WP1 `LM32_CSR_WIDTH'h19 13.223 +`define LM32_CSR_WP2 `LM32_CSR_WIDTH'h1a 13.224 +`define LM32_CSR_WP3 `LM32_CSR_WIDTH'h1b 13.225 +`endif 13.226 + 13.227 +// Values for WPC CSR 13.228 +`define LM32_WPC_C_RNG 1:0 13.229 +`define LM32_WPC_C_DISABLED 2'b00 13.230 +`define LM32_WPC_C_READ 2'b01 13.231 +`define LM32_WPC_C_WRITE 2'b10 13.232 +`define LM32_WPC_C_READ_WRITE 2'b11 13.233 + 13.234 +// Exception IDs 13.235 +`define LM32_EID_WIDTH 3 13.236 +`define LM32_EID_RNG (`LM32_EID_WIDTH-1):0 13.237 +`define LM32_EID_RESET 3'h0 13.238 +`define LM32_EID_BREAKPOINT 3'd1 13.239 +`define LM32_EID_INST_BUS_ERROR 3'h2 13.240 +`define LM32_EID_WATCHPOINT 3'd3 13.241 +`define LM32_EID_DATA_BUS_ERROR 3'h4 13.242 +`define LM32_EID_DIVIDE_BY_ZERO 3'h5 13.243 +`define LM32_EID_INTERRUPT 3'h6 13.244 +`define LM32_EID_SCALL 3'h7 13.245 + 13.246 +// Pipeline result selection mux controls 13.247 + 13.248 +`define LM32_D_RESULT_SEL_0_RNG 0:0 13.249 +`define LM32_D_RESULT_SEL_0_REG_0 1'b0 13.250 +`define LM32_D_RESULT_SEL_0_NEXT_PC 1'b1 13.251 + 13.252 +`define LM32_D_RESULT_SEL_1_RNG 1:0 13.253 +`define LM32_D_RESULT_SEL_1_ZERO 2'b00 13.254 +`define LM32_D_RESULT_SEL_1_REG_1 2'b01 13.255 +`define LM32_D_RESULT_SEL_1_IMMEDIATE 2'b10 13.256 + 13.257 +`define LM32_USER_OPCODE_WIDTH 11 13.258 +`define LM32_USER_OPCODE_RNG (`LM32_USER_OPCODE_WIDTH-1):0 13.259 + 13.260 +// Derive a macro to indicate if either of the caches are implemented 13.261 +`ifdef CFG_ICACHE_ENABLED 13.262 +`define LM32_CACHE_ENABLED 13.263 +`else 13.264 +`ifdef CFG_DCACHE_ENABLED 13.265 +`define LM32_CACHE_ENABLED 13.266 +`endif 13.267 +`endif 13.268 + 13.269 +///////////////////////////////////////////////////// 13.270 +// Interrupts 13.271 +///////////////////////////////////////////////////// 13.272 + 13.273 +// Always enable interrupts 13.274 +`define CFG_INTERRUPTS_ENABLED 13.275 + 13.276 +// Currently this is fixed to 32 and should not be changed 13.277 +`define CFG_INTERRUPTS 32 13.278 +`define LM32_INTERRUPT_WIDTH `CFG_INTERRUPTS 13.279 +`define LM32_INTERRUPT_RNG (`LM32_INTERRUPT_WIDTH-1):0 13.280 + 13.281 +///////////////////////////////////////////////////// 13.282 +// General 13.283 +///////////////////////////////////////////////////// 13.284 + 13.285 +// Sub-word range types 13.286 +`define LM32_BYTE_WIDTH 8 13.287 +`define LM32_BYTE_RNG 7:0 13.288 +`define LM32_HWORD_WIDTH 16 13.289 +`define LM32_HWORD_RNG 15:0 13.290 + 13.291 +// Word sub-byte indicies 13.292 +`define LM32_BYTE_0_RNG 7:0 13.293 +`define LM32_BYTE_1_RNG 15:8 13.294 +`define LM32_BYTE_2_RNG 23:16 13.295 +`define LM32_BYTE_3_RNG 31:24 13.296 + 13.297 +// Word sub-halfword indices 13.298 +`define LM32_HWORD_0_RNG 15:0 13.299 +`define LM32_HWORD_1_RNG 31:16 13.300 + 13.301 +// Use an asynchronous reset 13.302 +// To use a synchronous reset, define this macro as nothing 13.303 +`define CFG_RESET_SENSITIVITY 13.304 + 13.305 +// V.T. Srce 13.306 +`define SRCE 13.307 + 13.308 +// Whether to include context registers for debug exceptions 13.309 +// in addition to standard exception handling registers 13.310 +// Bizarre - Removing this increases LUT count! 13.311 +`define CFG_DEBUG_EXCEPTIONS_ENABLED 13.312 + 13.313 +// Wishbone defines 13.314 +// Refer to Wishbone System-on-Chip Interconnection Architecture 13.315 +// These should probably be moved to a Wishbone common file 13.316 + 13.317 +// Wishbone cycle types 13.318 +`define LM32_CTYPE_WIDTH 3 13.319 +`define LM32_CTYPE_RNG (`LM32_CTYPE_WIDTH-1):0 13.320 +`define LM32_CTYPE_CLASSIC 3'b000 13.321 +`define LM32_CTYPE_CONSTANT 3'b001 13.322 +`define LM32_CTYPE_INCREMENTING 3'b010 13.323 +`define LM32_CTYPE_END 3'b111 13.324 + 13.325 +// Wishbone burst types 13.326 +`define LM32_BTYPE_WIDTH 2 13.327 +`define LM32_BTYPE_RNG (`LM32_BTYPE_WIDTH-1):0 13.328 +`define LM32_BTYPE_LINEAR 2'b00 13.329 +`define LM32_BTYPE_4_BEAT 2'b01 13.330 +`define LM32_BTYPE_8_BEAT 2'b10 13.331 +`define LM32_BTYPE_16_BEAT 2'b11 13.332 + 13.333 +`endif
14.1 diff -r 000000000000 -r cd0b58aa6f83 lm32_instruction_unit.v 14.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 14.3 +++ b/lm32_instruction_unit.v Sun Apr 04 20:40:03 2010 +0100 14.4 @@ -0,0 +1,841 @@ 14.5 +// ============================================================================= 14.6 +// COPYRIGHT NOTICE 14.7 +// Copyright 2006 (c) Lattice Semiconductor Corporation 14.8 +// ALL RIGHTS RESERVED 14.9 +// This confidential and proprietary software may be used only as authorised by 14.10 +// a licensing agreement from Lattice Semiconductor Corporation. 14.11 +// The entire notice above must be reproduced on all authorized copies and 14.12 +// copies may only be made to the extent permitted by a licensing agreement from 14.13 +// Lattice Semiconductor Corporation. 14.14 +// 14.15 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 14.16 +// 5555 NE Moore Court 408-826-6000 (other locations) 14.17 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 14.18 +// U.S.A email: techsupport@latticesemi.com 14.19 +// =============================================================================/ 14.20 +// FILE DETAILS 14.21 +// Project : LatticeMico32 14.22 +// File : lm32_instruction_unit.v 14.23 +// Title : Instruction unit 14.24 +// Dependencies : lm32_include.v 14.25 +// Version : 6.1.17 14.26 +// : Initial Release 14.27 +// Version : 7.0SP2, 3.0 14.28 +// : No Change 14.29 +// Version : 3.1 14.30 +// : Support for static branch prediction is added. Fetching of 14.31 +// : instructions can also be altered by branches predicted in D 14.32 +// : stage of pipeline, and mispredicted branches in the X and M 14.33 +// : stages of the pipeline. 14.34 +// Version : 3.2 14.35 +// : EBRs use SYNC resets instead of ASYNC resets. 14.36 +// Version : 3.3 14.37 +// : Support for a non-cacheable Instruction Memory that has a 14.38 +// : single-cycle access latency. This memory can be accessed by 14.39 +// : data port of LM32 (so that debugger has access to it). 14.40 +// Version : 3.4 14.41 +// : No change 14.42 +// Version : 3.5 14.43 +// : Bug fix: Inline memory is correctly generated if it is not a 14.44 +// : power-of-two. 14.45 +// : Bug fix: Fixed a bug that caused LM32 (configured without 14.46 +// : instruction cache) to lock up in to an infinite loop due to a 14.47 +// : instruction bus error when EBA was set to instruction inline 14.48 +// : memory. 14.49 +// ============================================================================= 14.50 + 14.51 +`include "lm32_include.v" 14.52 + 14.53 +///////////////////////////////////////////////////// 14.54 +// Module interface 14.55 +///////////////////////////////////////////////////// 14.56 + 14.57 +module lm32_instruction_unit ( 14.58 + // ----- Inputs ------- 14.59 + clk_i, 14.60 + rst_i, 14.61 + // From pipeline 14.62 + stall_a, 14.63 + stall_f, 14.64 + stall_d, 14.65 + stall_x, 14.66 + stall_m, 14.67 + valid_f, 14.68 + valid_d, 14.69 + kill_f, 14.70 + branch_predict_taken_d, 14.71 + branch_predict_address_d, 14.72 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH 14.73 + branch_taken_x, 14.74 + branch_target_x, 14.75 +`endif 14.76 + exception_m, 14.77 + branch_taken_m, 14.78 + branch_mispredict_taken_m, 14.79 + branch_target_m, 14.80 +`ifdef CFG_ICACHE_ENABLED 14.81 + iflush, 14.82 +`endif 14.83 +`ifdef CFG_DCACHE_ENABLED 14.84 + dcache_restart_request, 14.85 + dcache_refill_request, 14.86 + dcache_refilling, 14.87 +`endif 14.88 +`ifdef CFG_IROM_ENABLED 14.89 + irom_store_data_m, 14.90 + irom_address_xm, 14.91 + irom_we_xm, 14.92 +`endif 14.93 +`ifdef CFG_IWB_ENABLED 14.94 + // From Wishbone 14.95 + i_dat_i, 14.96 + i_ack_i, 14.97 + i_err_i, 14.98 + i_rty_i, 14.99 +`endif 14.100 +`ifdef CFG_HW_DEBUG_ENABLED 14.101 + jtag_read_enable, 14.102 + jtag_write_enable, 14.103 + jtag_write_data, 14.104 + jtag_address, 14.105 +`endif 14.106 + // ----- Outputs ------- 14.107 + // To pipeline 14.108 + pc_f, 14.109 + pc_d, 14.110 + pc_x, 14.111 + pc_m, 14.112 + pc_w, 14.113 +`ifdef CFG_ICACHE_ENABLED 14.114 + icache_stall_request, 14.115 + icache_restart_request, 14.116 + icache_refill_request, 14.117 + icache_refilling, 14.118 +`endif 14.119 +`ifdef CFG_IROM_ENABLED 14.120 + irom_data_m, 14.121 +`endif 14.122 +`ifdef CFG_IWB_ENABLED 14.123 + // To Wishbone 14.124 + i_dat_o, 14.125 + i_adr_o, 14.126 + i_cyc_o, 14.127 + i_sel_o, 14.128 + i_stb_o, 14.129 + i_we_o, 14.130 + i_cti_o, 14.131 + i_lock_o, 14.132 + i_bte_o, 14.133 +`endif 14.134 +`ifdef CFG_HW_DEBUG_ENABLED 14.135 + jtag_read_data, 14.136 + jtag_access_complete, 14.137 +`endif 14.138 +`ifdef CFG_BUS_ERRORS_ENABLED 14.139 + bus_error_d, 14.140 +`endif 14.141 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE 14.142 + instruction_f, 14.143 +`endif 14.144 + instruction_d 14.145 + ); 14.146 + 14.147 +///////////////////////////////////////////////////// 14.148 +// Parameters 14.149 +///////////////////////////////////////////////////// 14.150 + 14.151 +parameter associativity = 1; // Associativity of the cache (Number of ways) 14.152 +parameter sets = 512; // Number of sets 14.153 +parameter bytes_per_line = 16; // Number of bytes per cache line 14.154 +parameter base_address = 0; // Base address of cachable memory 14.155 +parameter limit = 0; // Limit (highest address) of cachable memory 14.156 + 14.157 +// For bytes_per_line == 4, we set 1 so part-select range isn't reversed, even though not really used 14.158 +localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2; 14.159 +localparam addr_offset_lsb = 2; 14.160 +localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1); 14.161 + 14.162 +///////////////////////////////////////////////////// 14.163 +// Inputs 14.164 +///////////////////////////////////////////////////// 14.165 + 14.166 +input clk_i; // Clock 14.167 +input rst_i; // Reset 14.168 + 14.169 +input stall_a; // Stall A stage instruction 14.170 +input stall_f; // Stall F stage instruction 14.171 +input stall_d; // Stall D stage instruction 14.172 +input stall_x; // Stall X stage instruction 14.173 +input stall_m; // Stall M stage instruction 14.174 +input valid_f; // Instruction in F stage is valid 14.175 +input valid_d; // Instruction in D stage is valid 14.176 +input kill_f; // Kill instruction in F stage 14.177 + 14.178 +input branch_predict_taken_d; // Branch is predicted taken in D stage 14.179 +input [`LM32_PC_RNG] branch_predict_address_d; // Branch target address 14.180 + 14.181 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH 14.182 +input branch_taken_x; // Branch instruction in X stage is taken 14.183 +input [`LM32_PC_RNG] branch_target_x; // Target PC of X stage branch instruction 14.184 +`endif 14.185 +input exception_m; 14.186 +input branch_taken_m; // Branch instruction in M stage is taken 14.187 +input branch_mispredict_taken_m; // Branch instruction in M stage is mispredicted as taken 14.188 +input [`LM32_PC_RNG] branch_target_m; // Target PC of M stage branch instruction 14.189 + 14.190 +`ifdef CFG_ICACHE_ENABLED 14.191 +input iflush; // Flush instruction cache 14.192 +`endif 14.193 +`ifdef CFG_DCACHE_ENABLED 14.194 +input dcache_restart_request; // Restart instruction that caused a data cache miss 14.195 +input dcache_refill_request; // Request to refill data cache 14.196 +input dcache_refilling; 14.197 +`endif 14.198 + 14.199 +`ifdef CFG_IROM_ENABLED 14.200 +input [`LM32_WORD_RNG] irom_store_data_m; // Data from load-store unit 14.201 +input [`LM32_WORD_RNG] irom_address_xm; // Address from load-store unit 14.202 +input irom_we_xm; // Indicates if memory operation is load or store 14.203 +`endif 14.204 + 14.205 +`ifdef CFG_IWB_ENABLED 14.206 +input [`LM32_WORD_RNG] i_dat_i; // Instruction Wishbone interface read data 14.207 +input i_ack_i; // Instruction Wishbone interface acknowledgement 14.208 +input i_err_i; // Instruction Wishbone interface error 14.209 +input i_rty_i; // Instruction Wishbone interface retry 14.210 +`endif 14.211 + 14.212 +`ifdef CFG_HW_DEBUG_ENABLED 14.213 +input jtag_read_enable; // JTAG read memory request 14.214 +input jtag_write_enable; // JTAG write memory request 14.215 +input [`LM32_BYTE_RNG] jtag_write_data; // JTAG wrirte data 14.216 +input [`LM32_WORD_RNG] jtag_address; // JTAG read/write address 14.217 +`endif 14.218 + 14.219 +///////////////////////////////////////////////////// 14.220 +// Outputs 14.221 +///////////////////////////////////////////////////// 14.222 + 14.223 +output [`LM32_PC_RNG] pc_f; // F stage PC 14.224 +reg [`LM32_PC_RNG] pc_f; 14.225 +output [`LM32_PC_RNG] pc_d; // D stage PC 14.226 +reg [`LM32_PC_RNG] pc_d; 14.227 +output [`LM32_PC_RNG] pc_x; // X stage PC 14.228 +reg [`LM32_PC_RNG] pc_x; 14.229 +output [`LM32_PC_RNG] pc_m; // M stage PC 14.230 +reg [`LM32_PC_RNG] pc_m; 14.231 +output [`LM32_PC_RNG] pc_w; // W stage PC 14.232 +reg [`LM32_PC_RNG] pc_w; 14.233 + 14.234 +`ifdef CFG_ICACHE_ENABLED 14.235 +output icache_stall_request; // Instruction cache stall request 14.236 +wire icache_stall_request; 14.237 +output icache_restart_request; // Request to restart instruction that cached instruction cache miss 14.238 +wire icache_restart_request; 14.239 +output icache_refill_request; // Instruction cache refill request 14.240 +wire icache_refill_request; 14.241 +output icache_refilling; // Indicates the icache is refilling 14.242 +wire icache_refilling; 14.243 +`endif 14.244 + 14.245 +`ifdef CFG_IROM_ENABLED 14.246 +output [`LM32_WORD_RNG] irom_data_m; // Data to load-store unit on load 14.247 +wire [`LM32_WORD_RNG] irom_data_m; 14.248 +`endif 14.249 + 14.250 +`ifdef CFG_IWB_ENABLED 14.251 +output [`LM32_WORD_RNG] i_dat_o; // Instruction Wishbone interface write data 14.252 +`ifdef CFG_HW_DEBUG_ENABLED 14.253 +reg [`LM32_WORD_RNG] i_dat_o; 14.254 +`else 14.255 +wire [`LM32_WORD_RNG] i_dat_o; 14.256 +`endif 14.257 +output [`LM32_WORD_RNG] i_adr_o; // Instruction Wishbone interface address 14.258 +reg [`LM32_WORD_RNG] i_adr_o; 14.259 +output i_cyc_o; // Instruction Wishbone interface cycle 14.260 +reg i_cyc_o; 14.261 +output [`LM32_BYTE_SELECT_RNG] i_sel_o; // Instruction Wishbone interface byte select 14.262 +`ifdef CFG_HW_DEBUG_ENABLED 14.263 +reg [`LM32_BYTE_SELECT_RNG] i_sel_o; 14.264 +`else 14.265 +wire [`LM32_BYTE_SELECT_RNG] i_sel_o; 14.266 +`endif 14.267 +output i_stb_o; // Instruction Wishbone interface strobe 14.268 +reg i_stb_o; 14.269 +output i_we_o; // Instruction Wishbone interface write enable 14.270 +`ifdef CFG_HW_DEBUG_ENABLED 14.271 +reg i_we_o; 14.272 +`else 14.273 +wire i_we_o; 14.274 +`endif 14.275 +output [`LM32_CTYPE_RNG] i_cti_o; // Instruction Wishbone interface cycle type 14.276 +reg [`LM32_CTYPE_RNG] i_cti_o; 14.277 +output i_lock_o; // Instruction Wishbone interface lock bus 14.278 +reg i_lock_o; 14.279 +output [`LM32_BTYPE_RNG] i_bte_o; // Instruction Wishbone interface burst type 14.280 +wire [`LM32_BTYPE_RNG] i_bte_o; 14.281 +`endif 14.282 + 14.283 +`ifdef CFG_HW_DEBUG_ENABLED 14.284 +output [`LM32_BYTE_RNG] jtag_read_data; // Data read for JTAG interface 14.285 +reg [`LM32_BYTE_RNG] jtag_read_data; 14.286 +output jtag_access_complete; // Requested memory access by JTAG interface is complete 14.287 +wire jtag_access_complete; 14.288 +`endif 14.289 + 14.290 +`ifdef CFG_BUS_ERRORS_ENABLED 14.291 +output bus_error_d; // Indicates a bus error occured while fetching the instruction 14.292 +reg bus_error_d; 14.293 +`endif 14.294 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE 14.295 +output [`LM32_INSTRUCTION_RNG] instruction_f; // F stage instruction (only to have register indices extracted from) 14.296 +wire [`LM32_INSTRUCTION_RNG] instruction_f; 14.297 +`endif 14.298 +output [`LM32_INSTRUCTION_RNG] instruction_d; // D stage instruction to be decoded 14.299 +reg [`LM32_INSTRUCTION_RNG] instruction_d; 14.300 + 14.301 +///////////////////////////////////////////////////// 14.302 +// Internal nets and registers 14.303 +///////////////////////////////////////////////////// 14.304 + 14.305 +reg [`LM32_PC_RNG] pc_a; // A stage PC 14.306 + 14.307 +`ifdef LM32_CACHE_ENABLED 14.308 +reg [`LM32_PC_RNG] restart_address; // Address to restart from after a cache miss 14.309 +`endif 14.310 + 14.311 +`ifdef CFG_ICACHE_ENABLED 14.312 +wire icache_read_enable_f; // Indicates if instruction cache miss is valid 14.313 +wire [`LM32_PC_RNG] icache_refill_address; // Address that caused cache miss 14.314 +reg icache_refill_ready; // Indicates when next word of refill data is ready to be written to cache 14.315 +reg [`LM32_INSTRUCTION_RNG] icache_refill_data; // Next word of refill data, fetched from Wishbone 14.316 +wire [`LM32_INSTRUCTION_RNG] icache_data_f; // Instruction fetched from instruction cache 14.317 +wire [`LM32_CTYPE_RNG] first_cycle_type; // First Wishbone cycle type 14.318 +wire [`LM32_CTYPE_RNG] next_cycle_type; // Next Wishbone cycle type 14.319 +wire last_word; // Indicates if this is the last word in the cache line 14.320 +wire [`LM32_PC_RNG] first_address; // First cache refill address 14.321 +`else 14.322 +`ifdef CFG_IWB_ENABLED 14.323 +reg [`LM32_INSTRUCTION_RNG] wb_data_f; // Instruction fetched from Wishbone 14.324 +`endif 14.325 +`endif 14.326 +`ifdef CFG_IROM_ENABLED 14.327 +wire irom_select_a; // Indicates if A stage PC maps to a ROM address 14.328 +reg irom_select_f; // Indicates if F stage PC maps to a ROM address 14.329 +wire [`LM32_INSTRUCTION_RNG] irom_data_f; // Instruction fetched from ROM 14.330 +`endif 14.331 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE 14.332 +`else 14.333 +wire [`LM32_INSTRUCTION_RNG] instruction_f; // F stage instruction 14.334 +`endif 14.335 +`ifdef CFG_BUS_ERRORS_ENABLED 14.336 +reg bus_error_f; // Indicates if a bus error occured while fetching the instruction in the F stage 14.337 +`endif 14.338 + 14.339 +`ifdef CFG_HW_DEBUG_ENABLED 14.340 +reg jtag_access; // Indicates if a JTAG WB access is in progress 14.341 +`endif 14.342 + 14.343 +///////////////////////////////////////////////////// 14.344 +// Functions 14.345 +///////////////////////////////////////////////////// 14.346 + 14.347 +`include "lm32_functions.v" 14.348 + 14.349 +///////////////////////////////////////////////////// 14.350 +// Instantiations 14.351 +///////////////////////////////////////////////////// 14.352 + 14.353 +// Instruction ROM 14.354 +`ifdef CFG_IROM_ENABLED 14.355 + pmi_ram_dp_true 14.356 + #( 14.357 + // ----- Parameters ------- 14.358 + .pmi_family (`LATTICE_FAMILY), 14.359 + 14.360 + //.pmi_addr_depth_a (1 << (clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)), 14.361 + //.pmi_addr_width_a ((clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)), 14.362 + //.pmi_data_width_a (`LM32_WORD_WIDTH), 14.363 + //.pmi_addr_depth_b (1 << (clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)), 14.364 + //.pmi_addr_width_b ((clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)), 14.365 + //.pmi_data_width_b (`LM32_WORD_WIDTH), 14.366 + 14.367 + .pmi_addr_depth_a (`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1), 14.368 + .pmi_addr_width_a (clogb2_v1(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)), 14.369 + .pmi_data_width_a (`LM32_WORD_WIDTH), 14.370 + .pmi_addr_depth_b (`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1), 14.371 + .pmi_addr_width_b (clogb2_v1(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)), 14.372 + .pmi_data_width_b (`LM32_WORD_WIDTH), 14.373 + 14.374 + .pmi_regmode_a ("noreg"), 14.375 + .pmi_regmode_b ("noreg"), 14.376 + .pmi_gsr ("enable"), 14.377 + .pmi_resetmode ("sync"), 14.378 + .pmi_init_file (`CFG_IROM_INIT_FILE), 14.379 + .pmi_init_file_format (`CFG_IROM_INIT_FILE_FORMAT), 14.380 + .module_type ("pmi_ram_dp_true") 14.381 + ) 14.382 + ram ( 14.383 + // ----- Inputs ------- 14.384 + .ClockA (clk_i), 14.385 + .ClockB (clk_i), 14.386 + .ResetA (rst_i), 14.387 + .ResetB (rst_i), 14.388 + .DataInA ({32{1'b0}}), 14.389 + .DataInB (irom_store_data_m), 14.390 + .AddressA (pc_a[(clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)+2-1:2]), 14.391 + .AddressB (irom_address_xm[(clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)+2-1:2]), 14.392 + .ClockEnA (!stall_a), 14.393 + .ClockEnB (!stall_x || !stall_m), 14.394 + .WrA (`FALSE), 14.395 + .WrB (irom_we_xm), 14.396 + // ----- Outputs ------- 14.397 + .QA (irom_data_f), 14.398 + .QB (irom_data_m) 14.399 + ); 14.400 +`endif 14.401 + 14.402 +`ifdef CFG_ICACHE_ENABLED 14.403 +// Instruction cache 14.404 +lm32_icache #( 14.405 + .associativity (associativity), 14.406 + .sets (sets), 14.407 + .bytes_per_line (bytes_per_line), 14.408 + .base_address (base_address), 14.409 + .limit (limit) 14.410 + ) icache ( 14.411 + // ----- Inputs ----- 14.412 + .clk_i (clk_i), 14.413 + .rst_i (rst_i), 14.414 + .stall_a (stall_a), 14.415 + .stall_f (stall_f), 14.416 + .branch_predict_taken_d (branch_predict_taken_d), 14.417 + .valid_d (valid_d), 14.418 + .address_a (pc_a), 14.419 + .address_f (pc_f), 14.420 + .read_enable_f (icache_read_enable_f), 14.421 + .refill_ready (icache_refill_ready), 14.422 + .refill_data (icache_refill_data), 14.423 + .iflush (iflush), 14.424 + // ----- Outputs ----- 14.425 + .stall_request (icache_stall_request), 14.426 + .restart_request (icache_restart_request), 14.427 + .refill_request (icache_refill_request), 14.428 + .refill_address (icache_refill_address), 14.429 + .refilling (icache_refilling), 14.430 + .inst (icache_data_f) 14.431 + ); 14.432 +`endif 14.433 + 14.434 +///////////////////////////////////////////////////// 14.435 +// Combinational Logic 14.436 +///////////////////////////////////////////////////// 14.437 + 14.438 +`ifdef CFG_ICACHE_ENABLED 14.439 +// Generate signal that indicates when instruction cache misses are valid 14.440 +assign icache_read_enable_f = (valid_f == `TRUE) 14.441 + && (kill_f == `FALSE) 14.442 +`ifdef CFG_DCACHE_ENABLED 14.443 + && (dcache_restart_request == `FALSE) 14.444 +`endif 14.445 +`ifdef CFG_IROM_ENABLED 14.446 + && (irom_select_f == `FALSE) 14.447 +`endif 14.448 + ; 14.449 +`endif 14.450 + 14.451 +// Compute address of next instruction to fetch 14.452 +always @(*) 14.453 +begin 14.454 + // The request from the latest pipeline stage must take priority 14.455 +`ifdef CFG_DCACHE_ENABLED 14.456 + if (dcache_restart_request == `TRUE) 14.457 + pc_a = restart_address; 14.458 + else 14.459 +`endif 14.460 + if (branch_taken_m == `TRUE) 14.461 + if ((branch_mispredict_taken_m == `TRUE) && (exception_m == `FALSE)) 14.462 + pc_a = pc_x; 14.463 + else 14.464 + pc_a = branch_target_m; 14.465 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH 14.466 + else if (branch_taken_x == `TRUE) 14.467 + pc_a = branch_target_x; 14.468 +`endif 14.469 + else 14.470 + if ( (valid_d == `TRUE) && (branch_predict_taken_d == `TRUE) ) 14.471 + pc_a = branch_predict_address_d; 14.472 + else 14.473 +`ifdef CFG_ICACHE_ENABLED 14.474 + if (icache_restart_request == `TRUE) 14.475 + pc_a = restart_address; 14.476 + else 14.477 +`endif 14.478 + pc_a = pc_f + 1'b1; 14.479 +end 14.480 + 14.481 +// Select where instruction should be fetched from 14.482 +`ifdef CFG_IROM_ENABLED 14.483 +assign irom_select_a = ({pc_a, 2'b00} >= `CFG_IROM_BASE_ADDRESS) && ({pc_a, 2'b00} <= `CFG_IROM_LIMIT); 14.484 +`endif 14.485 + 14.486 +// Select instruction from selected source 14.487 +`ifdef CFG_ICACHE_ENABLED 14.488 +`ifdef CFG_IROM_ENABLED 14.489 +assign instruction_f = irom_select_f == `TRUE ? irom_data_f : icache_data_f; 14.490 +`else 14.491 +assign instruction_f = icache_data_f; 14.492 +`endif 14.493 +`else 14.494 +`ifdef CFG_IROM_ENABLED 14.495 +`ifdef CFG_IWB_ENABLED 14.496 +assign instruction_f = irom_select_f == `TRUE ? irom_data_f : wb_data_f; 14.497 +`else 14.498 +assign instruction_f = irom_data_f; 14.499 +`endif 14.500 +`else 14.501 +assign instruction_f = wb_data_f; 14.502 +`endif 14.503 +`endif 14.504 + 14.505 +// Unused/constant Wishbone signals 14.506 +`ifdef CFG_IWB_ENABLED 14.507 +`ifdef CFG_HW_DEBUG_ENABLED 14.508 +`else 14.509 +assign i_dat_o = 32'd0; 14.510 +assign i_we_o = `FALSE; 14.511 +assign i_sel_o = 4'b1111; 14.512 +`endif 14.513 +assign i_bte_o = `LM32_BTYPE_LINEAR; 14.514 +`endif 14.515 + 14.516 +`ifdef CFG_ICACHE_ENABLED 14.517 +// Determine parameters for next cache refill Wishbone access 14.518 +generate 14.519 + case (bytes_per_line) 14.520 + 4: 14.521 + begin 14.522 +assign first_cycle_type = `LM32_CTYPE_END; 14.523 +assign next_cycle_type = `LM32_CTYPE_END; 14.524 +assign last_word = `TRUE; 14.525 +assign first_address = icache_refill_address; 14.526 + end 14.527 + 8: 14.528 + begin 14.529 +assign first_cycle_type = `LM32_CTYPE_INCREMENTING; 14.530 +assign next_cycle_type = `LM32_CTYPE_END; 14.531 +assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 1'b1; 14.532 +assign first_address = {icache_refill_address[`LM32_PC_WIDTH+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}}; 14.533 + end 14.534 + 16: 14.535 + begin 14.536 +assign first_cycle_type = `LM32_CTYPE_INCREMENTING; 14.537 +assign next_cycle_type = i_adr_o[addr_offset_msb] == 1'b1 ? `LM32_CTYPE_END : `LM32_CTYPE_INCREMENTING; 14.538 +assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 2'b11; 14.539 +assign first_address = {icache_refill_address[`LM32_PC_WIDTH+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}}; 14.540 + end 14.541 + endcase 14.542 +endgenerate 14.543 +`endif 14.544 + 14.545 +///////////////////////////////////////////////////// 14.546 +// Sequential Logic 14.547 +///////////////////////////////////////////////////// 14.548 + 14.549 +// PC 14.550 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 14.551 +begin 14.552 + if (rst_i == `TRUE) 14.553 + begin 14.554 + pc_f <= (`CFG_EBA_RESET-4)/4; 14.555 + pc_d <= {`LM32_PC_WIDTH{1'b0}}; 14.556 + pc_x <= {`LM32_PC_WIDTH{1'b0}}; 14.557 + pc_m <= {`LM32_PC_WIDTH{1'b0}}; 14.558 + pc_w <= {`LM32_PC_WIDTH{1'b0}}; 14.559 + end 14.560 + else 14.561 + begin 14.562 + if (stall_f == `FALSE) 14.563 + pc_f <= pc_a; 14.564 + if (stall_d == `FALSE) 14.565 + pc_d <= pc_f; 14.566 + if (stall_x == `FALSE) 14.567 + pc_x <= pc_d; 14.568 + if (stall_m == `FALSE) 14.569 + pc_m <= pc_x; 14.570 + pc_w <= pc_m; 14.571 + end 14.572 +end 14.573 + 14.574 +`ifdef LM32_CACHE_ENABLED 14.575 +// Address to restart from after a cache miss has been handled 14.576 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 14.577 +begin 14.578 + if (rst_i == `TRUE) 14.579 + restart_address <= {`LM32_PC_WIDTH{1'b0}}; 14.580 + else 14.581 + begin 14.582 +`ifdef CFG_DCACHE_ENABLED 14.583 +`ifdef CFG_ICACHE_ENABLED 14.584 + // D-cache restart address must take priority, otherwise instructions will be lost 14.585 + if (dcache_refill_request == `TRUE) 14.586 + restart_address <= pc_w; 14.587 + else if ((icache_refill_request == `TRUE) && (!dcache_refilling) && (!dcache_restart_request)) 14.588 + restart_address <= icache_refill_address; 14.589 +`else 14.590 + if (dcache_refill_request == `TRUE) 14.591 + restart_address <= pc_w; 14.592 +`endif 14.593 +`else 14.594 +`ifdef CFG_ICACHE_ENABLED 14.595 + if (icache_refill_request == `TRUE) 14.596 + restart_address <= icache_refill_address; 14.597 +`endif 14.598 +`endif 14.599 + end 14.600 +end 14.601 +`endif 14.602 + 14.603 +// Record where instruction was fetched from 14.604 +`ifdef CFG_IROM_ENABLED 14.605 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 14.606 +begin 14.607 + if (rst_i == `TRUE) 14.608 + irom_select_f <= `FALSE; 14.609 + else 14.610 + begin 14.611 + if (stall_f == `FALSE) 14.612 + irom_select_f <= irom_select_a; 14.613 + end 14.614 +end 14.615 +`endif 14.616 + 14.617 +`ifdef CFG_HW_DEBUG_ENABLED 14.618 +assign jtag_access_complete = (i_cyc_o == `TRUE) && ((i_ack_i == `TRUE) || (i_err_i == `TRUE)) && (jtag_access == `TRUE); 14.619 +always @(*) 14.620 +begin 14.621 + case (jtag_address[1:0]) 14.622 + 2'b00: jtag_read_data = i_dat_i[`LM32_BYTE_3_RNG]; 14.623 + 2'b01: jtag_read_data = i_dat_i[`LM32_BYTE_2_RNG]; 14.624 + 2'b10: jtag_read_data = i_dat_i[`LM32_BYTE_1_RNG]; 14.625 + 2'b11: jtag_read_data = i_dat_i[`LM32_BYTE_0_RNG]; 14.626 + endcase 14.627 +end 14.628 +`endif 14.629 + 14.630 +`ifdef CFG_IWB_ENABLED 14.631 +// Instruction Wishbone interface 14.632 +`ifdef CFG_ICACHE_ENABLED 14.633 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 14.634 +begin 14.635 + if (rst_i == `TRUE) 14.636 + begin 14.637 + i_cyc_o <= `FALSE; 14.638 + i_stb_o <= `FALSE; 14.639 + i_adr_o <= {`LM32_WORD_WIDTH{1'b0}}; 14.640 + i_cti_o <= `LM32_CTYPE_END; 14.641 + i_lock_o <= `FALSE; 14.642 + icache_refill_data <= {`LM32_INSTRUCTION_WIDTH{1'b0}}; 14.643 + icache_refill_ready <= `FALSE; 14.644 +`ifdef CFG_BUS_ERRORS_ENABLED 14.645 + bus_error_f <= `FALSE; 14.646 +`endif 14.647 +`ifdef CFG_HW_DEBUG_ENABLED 14.648 + i_we_o <= `FALSE; 14.649 + i_sel_o <= 4'b1111; 14.650 + jtag_access <= `FALSE; 14.651 +`endif 14.652 + end 14.653 + else 14.654 + begin 14.655 + icache_refill_ready <= `FALSE; 14.656 + // Is a cycle in progress? 14.657 + if (i_cyc_o == `TRUE) 14.658 + begin 14.659 + // Has cycle completed? 14.660 + if ((i_ack_i == `TRUE) || (i_err_i == `TRUE)) 14.661 + begin 14.662 +`ifdef CFG_HW_DEBUG_ENABLED 14.663 + if (jtag_access == `TRUE) 14.664 + begin 14.665 + i_cyc_o <= `FALSE; 14.666 + i_stb_o <= `FALSE; 14.667 + i_we_o <= `FALSE; 14.668 + jtag_access <= `FALSE; 14.669 + end 14.670 + else 14.671 +`endif 14.672 + begin 14.673 + if (last_word == `TRUE) 14.674 + begin 14.675 + // Cache line fill complete 14.676 + i_cyc_o <= `FALSE; 14.677 + i_stb_o <= `FALSE; 14.678 + i_lock_o <= `FALSE; 14.679 + end 14.680 + // Fetch next word in cache line 14.681 + i_adr_o[addr_offset_msb:addr_offset_lsb] <= i_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1; 14.682 + i_cti_o <= next_cycle_type; 14.683 + // Write fetched data into instruction cache 14.684 + icache_refill_ready <= `TRUE; 14.685 + icache_refill_data <= i_dat_i; 14.686 + end 14.687 + end 14.688 +`ifdef CFG_BUS_ERRORS_ENABLED 14.689 + if (i_err_i == `TRUE) 14.690 + begin 14.691 + bus_error_f <= `TRUE; 14.692 + $display ("Instruction bus error. Address: %x", i_adr_o); 14.693 + end 14.694 +`endif 14.695 + end 14.696 + else 14.697 + begin 14.698 + if ((icache_refill_request == `TRUE) && (icache_refill_ready == `FALSE)) 14.699 + begin 14.700 + // Read first word of cache line 14.701 +`ifdef CFG_HW_DEBUG_ENABLED 14.702 + i_sel_o <= 4'b1111; 14.703 +`endif 14.704 + i_adr_o <= {first_address, 2'b00}; 14.705 + i_cyc_o <= `TRUE; 14.706 + i_stb_o <= `TRUE; 14.707 + i_cti_o <= first_cycle_type; 14.708 + //i_lock_o <= `TRUE; 14.709 +`ifdef CFG_BUS_ERRORS_ENABLED 14.710 + bus_error_f <= `FALSE; 14.711 +`endif 14.712 + end 14.713 +`ifdef CFG_HW_DEBUG_ENABLED 14.714 + else 14.715 + begin 14.716 + if ((jtag_read_enable == `TRUE) || (jtag_write_enable == `TRUE)) 14.717 + begin 14.718 + case (jtag_address[1:0]) 14.719 + 2'b00: i_sel_o <= 4'b1000; 14.720 + 2'b01: i_sel_o <= 4'b0100; 14.721 + 2'b10: i_sel_o <= 4'b0010; 14.722 + 2'b11: i_sel_o <= 4'b0001; 14.723 + endcase 14.724 + i_adr_o <= jtag_address; 14.725 + i_dat_o <= {4{jtag_write_data}}; 14.726 + i_cyc_o <= `TRUE; 14.727 + i_stb_o <= `TRUE; 14.728 + i_we_o <= jtag_write_enable; 14.729 + i_cti_o <= `LM32_CTYPE_END; 14.730 + jtag_access <= `TRUE; 14.731 + end 14.732 + end 14.733 +`endif 14.734 +`ifdef CFG_BUS_ERRORS_ENABLED 14.735 + // Clear bus error when exception taken, otherwise they would be 14.736 + // continually generated if exception handler is cached 14.737 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH 14.738 + if (branch_taken_x == `TRUE) 14.739 + bus_error_f <= `FALSE; 14.740 +`endif 14.741 + if (branch_taken_m == `TRUE) 14.742 + bus_error_f <= `FALSE; 14.743 +`endif 14.744 + end 14.745 + end 14.746 +end 14.747 +`else 14.748 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 14.749 +begin 14.750 + if (rst_i == `TRUE) 14.751 + begin 14.752 + i_cyc_o <= `FALSE; 14.753 + i_stb_o <= `FALSE; 14.754 + i_adr_o <= {`LM32_WORD_WIDTH{1'b0}}; 14.755 + i_cti_o <= `LM32_CTYPE_END; 14.756 + i_lock_o <= `FALSE; 14.757 + wb_data_f <= {`LM32_INSTRUCTION_WIDTH{1'b0}}; 14.758 +`ifdef CFG_BUS_ERRORS_ENABLED 14.759 + bus_error_f <= `FALSE; 14.760 +`endif 14.761 + end 14.762 + else 14.763 + begin 14.764 + // Is a cycle in progress? 14.765 + if (i_cyc_o == `TRUE) 14.766 + begin 14.767 + // Has cycle completed? 14.768 + if((i_ack_i == `TRUE) || (i_err_i == `TRUE)) 14.769 + begin 14.770 + // Cycle complete 14.771 + i_cyc_o <= `FALSE; 14.772 + i_stb_o <= `FALSE; 14.773 + // Register fetched instruction 14.774 + wb_data_f <= i_dat_i; 14.775 + end 14.776 +`ifdef CFG_BUS_ERRORS_ENABLED 14.777 + if (i_err_i == `TRUE) 14.778 + begin 14.779 + bus_error_f <= `TRUE; 14.780 + $display ("Instruction bus error. Address: %x", i_adr_o); 14.781 + end 14.782 +`endif 14.783 + end 14.784 + else 14.785 + begin 14.786 + // Wait for an instruction fetch from an external address 14.787 + if ( (stall_a == `FALSE) 14.788 +`ifdef CFG_IROM_ENABLED 14.789 + && (irom_select_a == `FALSE) 14.790 +`endif 14.791 + ) 14.792 + begin 14.793 + // Fetch instruction 14.794 +`ifdef CFG_HW_DEBUG_ENABLED 14.795 + i_sel_o <= 4'b1111; 14.796 +`endif 14.797 + i_adr_o <= {pc_a, 2'b00}; 14.798 + i_cyc_o <= `TRUE; 14.799 + i_stb_o <= `TRUE; 14.800 +`ifdef CFG_BUS_ERRORS_ENABLED 14.801 + bus_error_f <= `FALSE; 14.802 +`endif 14.803 + end 14.804 + else 14.805 + begin 14.806 + if ( (stall_a == `FALSE) 14.807 +`ifdef CFG_IROM_ENABLED 14.808 + && (irom_select_a == `TRUE) 14.809 +`endif 14.810 + ) 14.811 + begin 14.812 +`ifdef CFG_BUS_ERRORS_ENABLED 14.813 + bus_error_f <= `FALSE; 14.814 +`endif 14.815 + end 14.816 + end 14.817 + end 14.818 + end 14.819 +end 14.820 +`endif 14.821 +`endif 14.822 + 14.823 +// Instruction register 14.824 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 14.825 +begin 14.826 + if (rst_i == `TRUE) 14.827 + begin 14.828 + instruction_d <= {`LM32_INSTRUCTION_WIDTH{1'b0}}; 14.829 +`ifdef CFG_BUS_ERRORS_ENABLED 14.830 + bus_error_d <= `FALSE; 14.831 +`endif 14.832 + end 14.833 + else 14.834 + begin 14.835 + if (stall_d == `FALSE) 14.836 + begin 14.837 + instruction_d <= instruction_f; 14.838 +`ifdef CFG_BUS_ERRORS_ENABLED 14.839 + bus_error_d <= bus_error_f; 14.840 +`endif 14.841 + end 14.842 + end 14.843 +end 14.844 + 14.845 +endmodule
15.1 diff -r 000000000000 -r cd0b58aa6f83 lm32_interrupt.v 15.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 15.3 +++ b/lm32_interrupt.v Sun Apr 04 20:40:03 2010 +0100 15.4 @@ -0,0 +1,335 @@ 15.5 +// ============================================================================= 15.6 +// COPYRIGHT NOTICE 15.7 +// Copyright 2006 (c) Lattice Semiconductor Corporation 15.8 +// ALL RIGHTS RESERVED 15.9 +// This confidential and proprietary software may be used only as authorised by 15.10 +// a licensing agreement from Lattice Semiconductor Corporation. 15.11 +// The entire notice above must be reproduced on all authorized copies and 15.12 +// copies may only be made to the extent permitted by a licensing agreement from 15.13 +// Lattice Semiconductor Corporation. 15.14 +// 15.15 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 15.16 +// 5555 NE Moore Court 408-826-6000 (other locations) 15.17 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 15.18 +// U.S.A email: techsupport@latticesemi.com 15.19 +// =============================================================================/ 15.20 +// FILE DETAILS 15.21 +// Project : LatticeMico32 15.22 +// File : lm32_interrupt.v 15.23 +// Title : Interrupt logic 15.24 +// Dependencies : lm32_include.v 15.25 +// Version : 6.1.17 15.26 +// : Initial Release 15.27 +// Version : 7.0SP2, 3.0 15.28 +// : No Change 15.29 +// Version : 3.1 15.30 +// : No Change 15.31 +// ============================================================================= 15.32 + 15.33 +`include "lm32_include.v" 15.34 + 15.35 +///////////////////////////////////////////////////// 15.36 +// Module interface 15.37 +///////////////////////////////////////////////////// 15.38 + 15.39 +module lm32_interrupt ( 15.40 + // ----- Inputs ------- 15.41 + clk_i, 15.42 + rst_i, 15.43 + // From external devices 15.44 + interrupt_n, 15.45 + // From pipeline 15.46 + stall_x, 15.47 +`ifdef CFG_DEBUG_ENABLED 15.48 + non_debug_exception, 15.49 + debug_exception, 15.50 +`else 15.51 + exception, 15.52 +`endif 15.53 + eret_q_x, 15.54 +`ifdef CFG_DEBUG_ENABLED 15.55 + bret_q_x, 15.56 +`endif 15.57 + csr, 15.58 + csr_write_data, 15.59 + csr_write_enable, 15.60 + // ----- Outputs ------- 15.61 + interrupt_exception, 15.62 + // To pipeline 15.63 + csr_read_data 15.64 + ); 15.65 + 15.66 +///////////////////////////////////////////////////// 15.67 +// Parameters 15.68 +///////////////////////////////////////////////////// 15.69 + 15.70 +parameter interrupts = `CFG_INTERRUPTS; // Number of interrupts 15.71 + 15.72 +///////////////////////////////////////////////////// 15.73 +// Inputs 15.74 +///////////////////////////////////////////////////// 15.75 + 15.76 +input clk_i; // Clock 15.77 +input rst_i; // Reset 15.78 + 15.79 +input [interrupts-1:0] interrupt_n; // Interrupt pins, active-low 15.80 + 15.81 +input stall_x; // Stall X pipeline stage 15.82 + 15.83 +`ifdef CFG_DEBUG_ENABLED 15.84 +input non_debug_exception; // Non-debug related exception has been raised 15.85 +input debug_exception; // Debug-related exception has been raised 15.86 +`else 15.87 +input exception; // Exception has been raised 15.88 +`endif 15.89 +input eret_q_x; // Return from exception 15.90 +`ifdef CFG_DEBUG_ENABLED 15.91 +input bret_q_x; // Return from breakpoint 15.92 +`endif 15.93 + 15.94 +input [`LM32_CSR_RNG] csr; // CSR read/write index 15.95 +input [`LM32_WORD_RNG] csr_write_data; // Data to write to specified CSR 15.96 +input csr_write_enable; // CSR write enable 15.97 + 15.98 +///////////////////////////////////////////////////// 15.99 +// Outputs 15.100 +///////////////////////////////////////////////////// 15.101 + 15.102 +output interrupt_exception; // Request to raide an interrupt exception 15.103 +wire interrupt_exception; 15.104 + 15.105 +output [`LM32_WORD_RNG] csr_read_data; // Data read from CSR 15.106 +reg [`LM32_WORD_RNG] csr_read_data; 15.107 + 15.108 +///////////////////////////////////////////////////// 15.109 +// Internal nets and registers 15.110 +///////////////////////////////////////////////////// 15.111 + 15.112 +wire [interrupts-1:0] asserted; // Which interrupts are currently being asserted 15.113 +//pragma attribute asserted preserve_signal true 15.114 +wire [interrupts-1:0] interrupt_n_exception; 15.115 + 15.116 +// Interrupt CSRs 15.117 + 15.118 +reg ie; // Interrupt enable 15.119 +reg eie; // Exception interrupt enable 15.120 +`ifdef CFG_DEBUG_ENABLED 15.121 +reg bie; // Breakpoint interrupt enable 15.122 +`endif 15.123 +reg [interrupts-1:0] ip; // Interrupt pending 15.124 +reg [interrupts-1:0] im; // Interrupt mask 15.125 + 15.126 +///////////////////////////////////////////////////// 15.127 +// Combinational Logic 15.128 +///////////////////////////////////////////////////// 15.129 + 15.130 +// Determine which interrupts have occured and are unmasked 15.131 +assign interrupt_n_exception = ip & im; 15.132 + 15.133 +// Determine if any unmasked interrupts have occured 15.134 +assign interrupt_exception = (|interrupt_n_exception) & ie; 15.135 + 15.136 +// Determine which interrupts are currently being asserted (active-low) or are already pending 15.137 +assign asserted = ip | ~interrupt_n; 15.138 + 15.139 +assign ie_csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}}, 15.140 +`ifdef CFG_DEBUG_ENABLED 15.141 + bie, 15.142 +`else 15.143 + 1'b0, 15.144 +`endif 15.145 + eie, 15.146 + ie 15.147 + }; 15.148 +assign ip_csr_read_data = ip; 15.149 +assign im_csr_read_data = im; 15.150 +generate 15.151 + if (interrupts > 1) 15.152 + begin 15.153 +// CSR read 15.154 +always @(*) 15.155 +begin 15.156 + case (csr) 15.157 + `LM32_CSR_IE: csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}}, 15.158 +`ifdef CFG_DEBUG_ENABLED 15.159 + bie, 15.160 +`else 15.161 + 1'b0, 15.162 +`endif 15.163 + eie, 15.164 + ie 15.165 + }; 15.166 + `LM32_CSR_IP: csr_read_data = ip; 15.167 + `LM32_CSR_IM: csr_read_data = im; 15.168 + default: csr_read_data = {`LM32_WORD_WIDTH{1'bx}}; 15.169 + endcase 15.170 +end 15.171 + end 15.172 + else 15.173 + begin 15.174 +// CSR read 15.175 +always @(*) 15.176 +begin 15.177 + case (csr) 15.178 + `LM32_CSR_IE: csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}}, 15.179 +`ifdef CFG_DEBUG_ENABLED 15.180 + bie, 15.181 +`else 15.182 + 1'b0, 15.183 +`endif 15.184 + eie, 15.185 + ie 15.186 + }; 15.187 + `LM32_CSR_IP: csr_read_data = ip; 15.188 + default: csr_read_data = {`LM32_WORD_WIDTH{1'bx}}; 15.189 + endcase 15.190 +end 15.191 + end 15.192 +endgenerate 15.193 + 15.194 +///////////////////////////////////////////////////// 15.195 +// Sequential Logic 15.196 +///////////////////////////////////////////////////// 15.197 + 15.198 +generate 15.199 + if (interrupts > 1) 15.200 + begin 15.201 +// IE, IM, IP - Interrupt Enable, Interrupt Mask and Interrupt Pending CSRs 15.202 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 15.203 +begin 15.204 + if (rst_i == `TRUE) 15.205 + begin 15.206 + ie <= `FALSE; 15.207 + eie <= `FALSE; 15.208 +`ifdef CFG_DEBUG_ENABLED 15.209 + bie <= `FALSE; 15.210 +`endif 15.211 + im <= {interrupts{1'b0}}; 15.212 + ip <= {interrupts{1'b0}}; 15.213 + end 15.214 + else 15.215 + begin 15.216 + // Set IP bit when interrupt line is asserted 15.217 + ip <= asserted; 15.218 +`ifdef CFG_DEBUG_ENABLED 15.219 + if (non_debug_exception == `TRUE) 15.220 + begin 15.221 + // Save and then clear interrupt enable 15.222 + eie <= ie; 15.223 + ie <= `FALSE; 15.224 + end 15.225 + else if (debug_exception == `TRUE) 15.226 + begin 15.227 + // Save and then clear interrupt enable 15.228 + bie <= ie; 15.229 + ie <= `FALSE; 15.230 + end 15.231 +`else 15.232 + if (exception == `TRUE) 15.233 + begin 15.234 + // Save and then clear interrupt enable 15.235 + eie <= ie; 15.236 + ie <= `FALSE; 15.237 + end 15.238 +`endif 15.239 + else if (stall_x == `FALSE) 15.240 + begin 15.241 + if (eret_q_x == `TRUE) 15.242 + // Restore interrupt enable 15.243 + ie <= eie; 15.244 +`ifdef CFG_DEBUG_ENABLED 15.245 + else if (bret_q_x == `TRUE) 15.246 + // Restore interrupt enable 15.247 + ie <= bie; 15.248 +`endif 15.249 + else if (csr_write_enable == `TRUE) 15.250 + begin 15.251 + // Handle wcsr write 15.252 + if (csr == `LM32_CSR_IE) 15.253 + begin 15.254 + ie <= csr_write_data[0]; 15.255 + eie <= csr_write_data[1]; 15.256 +`ifdef CFG_DEBUG_ENABLED 15.257 + bie <= csr_write_data[2]; 15.258 +`endif 15.259 + end 15.260 + if (csr == `LM32_CSR_IM) 15.261 + im <= csr_write_data[interrupts-1:0]; 15.262 + if (csr == `LM32_CSR_IP) 15.263 + ip <= asserted & ~csr_write_data[interrupts-1:0]; 15.264 + end 15.265 + end 15.266 + end 15.267 +end 15.268 + end 15.269 +else 15.270 + begin 15.271 +// IE, IM, IP - Interrupt Enable, Interrupt Mask and Interrupt Pending CSRs 15.272 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 15.273 +begin 15.274 + if (rst_i == `TRUE) 15.275 + begin 15.276 + ie <= `FALSE; 15.277 + eie <= `FALSE; 15.278 +`ifdef CFG_DEBUG_ENABLED 15.279 + bie <= `FALSE; 15.280 +`endif 15.281 + ip <= {interrupts{1'b0}}; 15.282 + end 15.283 + else 15.284 + begin 15.285 + // Set IP bit when interrupt line is asserted 15.286 + ip <= asserted; 15.287 +`ifdef CFG_DEBUG_ENABLED 15.288 + if (non_debug_exception == `TRUE) 15.289 + begin 15.290 + // Save and then clear interrupt enable 15.291 + eie <= ie; 15.292 + ie <= `FALSE; 15.293 + end 15.294 + else if (debug_exception == `TRUE) 15.295 + begin 15.296 + // Save and then clear interrupt enable 15.297 + bie <= ie; 15.298 + ie <= `FALSE; 15.299 + end 15.300 +`else 15.301 + if (exception == `TRUE) 15.302 + begin 15.303 + // Save and then clear interrupt enable 15.304 + eie <= ie; 15.305 + ie <= `FALSE; 15.306 + end 15.307 +`endif 15.308 + else if (stall_x == `FALSE) 15.309 + begin 15.310 + if (eret_q_x == `TRUE) 15.311 + // Restore interrupt enable 15.312 + ie <= eie; 15.313 +`ifdef CFG_DEBUG_ENABLED 15.314 + else if (bret_q_x == `TRUE) 15.315 + // Restore interrupt enable 15.316 + ie <= bie; 15.317 +`endif 15.318 + else if (csr_write_enable == `TRUE) 15.319 + begin 15.320 + // Handle wcsr write 15.321 + if (csr == `LM32_CSR_IE) 15.322 + begin 15.323 + ie <= csr_write_data[0]; 15.324 + eie <= csr_write_data[1]; 15.325 +`ifdef CFG_DEBUG_ENABLED 15.326 + bie <= csr_write_data[2]; 15.327 +`endif 15.328 + end 15.329 + if (csr == `LM32_CSR_IP) 15.330 + ip <= asserted & ~csr_write_data[interrupts-1:0]; 15.331 + end 15.332 + end 15.333 + end 15.334 +end 15.335 + end 15.336 +endgenerate 15.337 + 15.338 +endmodule 15.339 +
16.1 diff -r 000000000000 -r cd0b58aa6f83 lm32_jtag.v 16.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 16.3 +++ b/lm32_jtag.v Sun Apr 04 20:40:03 2010 +0100 16.4 @@ -0,0 +1,479 @@ 16.5 +// ============================================================================= 16.6 +// COPYRIGHT NOTICE 16.7 +// Copyright 2006 (c) Lattice Semiconductor Corporation 16.8 +// ALL RIGHTS RESERVED 16.9 +// This confidential and proprietary software may be used only as authorised by 16.10 +// a licensing agreement from Lattice Semiconductor Corporation. 16.11 +// The entire notice above must be reproduced on all authorized copies and 16.12 +// copies may only be made to the extent permitted by a licensing agreement from 16.13 +// Lattice Semiconductor Corporation. 16.14 +// 16.15 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 16.16 +// 5555 NE Moore Court 408-826-6000 (other locations) 16.17 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 16.18 +// U.S.A email: techsupport@latticesemi.com 16.19 +// =============================================================================/ 16.20 +// FILE DETAILS 16.21 +// Project : LatticeMico32 16.22 +// File : lm32_jtag.v 16.23 +// Title : JTAG interface 16.24 +// Dependencies : lm32_include.v 16.25 +// Version : 6.1.17 16.26 +// : Initial Release 16.27 +// Version : 7.0SP2, 3.0 16.28 +// : No Change 16.29 +// Version : 3.1 16.30 +// : No Change 16.31 +// ============================================================================= 16.32 + 16.33 +`include "lm32_include.v" 16.34 + 16.35 +`ifdef CFG_JTAG_ENABLED 16.36 + 16.37 +`define LM32_DP 3'b000 16.38 +`define LM32_TX 3'b001 16.39 +`define LM32_RX 3'b010 16.40 + 16.41 +// LM32 Debug Protocol commands IDs 16.42 +`define LM32_DP_RNG 3:0 16.43 +`define LM32_DP_READ_MEMORY 4'b0001 16.44 +`define LM32_DP_WRITE_MEMORY 4'b0010 16.45 +`define LM32_DP_READ_SEQUENTIAL 4'b0011 16.46 +`define LM32_DP_WRITE_SEQUENTIAL 4'b0100 16.47 +`define LM32_DP_WRITE_CSR 4'b0101 16.48 +`define LM32_DP_BREAK 4'b0110 16.49 +`define LM32_DP_RESET 4'b0111 16.50 + 16.51 +// States for FSM 16.52 +`define LM32_JTAG_STATE_RNG 3:0 16.53 +`define LM32_JTAG_STATE_READ_COMMAND 4'h0 16.54 +`define LM32_JTAG_STATE_READ_BYTE_0 4'h1 16.55 +`define LM32_JTAG_STATE_READ_BYTE_1 4'h2 16.56 +`define LM32_JTAG_STATE_READ_BYTE_2 4'h3 16.57 +`define LM32_JTAG_STATE_READ_BYTE_3 4'h4 16.58 +`define LM32_JTAG_STATE_READ_BYTE_4 4'h5 16.59 +`define LM32_JTAG_STATE_PROCESS_COMMAND 4'h6 16.60 +`define LM32_JTAG_STATE_WAIT_FOR_MEMORY 4'h7 16.61 +`define LM32_JTAG_STATE_WAIT_FOR_CSR 4'h8 16.62 + 16.63 +///////////////////////////////////////////////////// 16.64 +// Module interface 16.65 +///////////////////////////////////////////////////// 16.66 + 16.67 +module lm32_jtag ( 16.68 + // ----- Inputs ------- 16.69 + clk_i, 16.70 + rst_i, 16.71 + jtag_clk, 16.72 + jtag_update, 16.73 + jtag_reg_q, 16.74 + jtag_reg_addr_q, 16.75 +`ifdef CFG_JTAG_UART_ENABLED 16.76 + csr, 16.77 + csr_write_enable, 16.78 + csr_write_data, 16.79 + stall_x, 16.80 +`endif 16.81 +`ifdef CFG_HW_DEBUG_ENABLED 16.82 + jtag_read_data, 16.83 + jtag_access_complete, 16.84 +`endif 16.85 +`ifdef CFG_DEBUG_ENABLED 16.86 + exception_q_w, 16.87 +`endif 16.88 + // ----- Outputs ------- 16.89 +`ifdef CFG_JTAG_UART_ENABLED 16.90 + jtx_csr_read_data, 16.91 + jrx_csr_read_data, 16.92 +`endif 16.93 +`ifdef CFG_HW_DEBUG_ENABLED 16.94 + jtag_csr_write_enable, 16.95 + jtag_csr_write_data, 16.96 + jtag_csr, 16.97 + jtag_read_enable, 16.98 + jtag_write_enable, 16.99 + jtag_write_data, 16.100 + jtag_address, 16.101 +`endif 16.102 +`ifdef CFG_DEBUG_ENABLED 16.103 + jtag_break, 16.104 + jtag_reset, 16.105 +`endif 16.106 + jtag_reg_d, 16.107 + jtag_reg_addr_d 16.108 + ); 16.109 + 16.110 + parameter lat_family = `LATTICE_FAMILY; 16.111 + 16.112 +///////////////////////////////////////////////////// 16.113 +// Inputs 16.114 +///////////////////////////////////////////////////// 16.115 + 16.116 +input clk_i; // Clock 16.117 +input rst_i; // Reset 16.118 + 16.119 +input jtag_clk; // JTAG clock 16.120 +input jtag_update; // JTAG data register has been updated 16.121 +input [`LM32_BYTE_RNG] jtag_reg_q; // JTAG data register 16.122 +input [2:0] jtag_reg_addr_q; // JTAG data register 16.123 + 16.124 +`ifdef CFG_JTAG_UART_ENABLED 16.125 +input [`LM32_CSR_RNG] csr; // CSR to write 16.126 +input csr_write_enable; // CSR write enable 16.127 +input [`LM32_WORD_RNG] csr_write_data; // Data to write to specified CSR 16.128 +input stall_x; // Stall instruction in X stage 16.129 +`endif 16.130 +`ifdef CFG_HW_DEBUG_ENABLED 16.131 +input [`LM32_BYTE_RNG] jtag_read_data; // Data read from requested address 16.132 +input jtag_access_complete; // Memory access if complete 16.133 +`endif 16.134 +`ifdef CFG_DEBUG_ENABLED 16.135 +input exception_q_w; // Indicates an exception has occured in W stage 16.136 +`endif 16.137 + 16.138 +///////////////////////////////////////////////////// 16.139 +// Outputs 16.140 +///////////////////////////////////////////////////// 16.141 + 16.142 +`ifdef CFG_JTAG_UART_ENABLED 16.143 +output [`LM32_WORD_RNG] jtx_csr_read_data; // Value of JTX CSR for rcsr instructions 16.144 +wire [`LM32_WORD_RNG] jtx_csr_read_data; 16.145 +output [`LM32_WORD_RNG] jrx_csr_read_data; // Value of JRX CSR for rcsr instructions 16.146 +wire [`LM32_WORD_RNG] jrx_csr_read_data; 16.147 +`endif 16.148 +`ifdef CFG_HW_DEBUG_ENABLED 16.149 +output jtag_csr_write_enable; // CSR write enable 16.150 +reg jtag_csr_write_enable; 16.151 +output [`LM32_WORD_RNG] jtag_csr_write_data; // Data to write to specified CSR 16.152 +wire [`LM32_WORD_RNG] jtag_csr_write_data; 16.153 +output [`LM32_CSR_RNG] jtag_csr; // CSR to write 16.154 +wire [`LM32_CSR_RNG] jtag_csr; 16.155 +output jtag_read_enable; // Memory read enable 16.156 +reg jtag_read_enable; 16.157 +output jtag_write_enable; // Memory write enable 16.158 +reg jtag_write_enable; 16.159 +output [`LM32_BYTE_RNG] jtag_write_data; // Data to write to specified address 16.160 +wire [`LM32_BYTE_RNG] jtag_write_data; 16.161 +output [`LM32_WORD_RNG] jtag_address; // Memory read/write address 16.162 +wire [`LM32_WORD_RNG] jtag_address; 16.163 +`endif 16.164 +`ifdef CFG_DEBUG_ENABLED 16.165 +output jtag_break; // Request to raise a breakpoint exception 16.166 +reg jtag_break; 16.167 +output jtag_reset; // Request to raise a reset exception 16.168 +reg jtag_reset; 16.169 +`endif 16.170 +output [`LM32_BYTE_RNG] jtag_reg_d; 16.171 +reg [`LM32_BYTE_RNG] jtag_reg_d; 16.172 +output [2:0] jtag_reg_addr_d; 16.173 +wire [2:0] jtag_reg_addr_d; 16.174 + 16.175 +///////////////////////////////////////////////////// 16.176 +// Internal nets and registers 16.177 +///////////////////////////////////////////////////// 16.178 + 16.179 +reg rx_toggle; // Clock-domain crossing registers 16.180 +reg rx_toggle_r; // Registered version of rx_toggle 16.181 +reg rx_toggle_r_r; // Registered version of rx_toggle_r 16.182 +reg rx_toggle_r_r_r; // Registered version of rx_toggle_r_r 16.183 + 16.184 +reg [`LM32_BYTE_RNG] rx_byte; 16.185 +reg [2:0] rx_addr; 16.186 + 16.187 +`ifdef CFG_JTAG_UART_ENABLED 16.188 +reg [`LM32_BYTE_RNG] uart_tx_byte; // UART TX data 16.189 +reg uart_tx_valid; // TX data is valid 16.190 +reg [`LM32_BYTE_RNG] uart_rx_byte; // UART RX data 16.191 +reg uart_rx_valid; // RX data is valid 16.192 +`endif 16.193 + 16.194 +reg [`LM32_DP_RNG] command; // The last received command 16.195 +`ifdef CFG_HW_DEBUG_ENABLED 16.196 +reg [`LM32_BYTE_RNG] jtag_byte_0; // Registers to hold command paramaters 16.197 +reg [`LM32_BYTE_RNG] jtag_byte_1; 16.198 +reg [`LM32_BYTE_RNG] jtag_byte_2; 16.199 +reg [`LM32_BYTE_RNG] jtag_byte_3; 16.200 +reg [`LM32_BYTE_RNG] jtag_byte_4; 16.201 +reg processing; // Indicates if we're still processing a memory read/write 16.202 +`endif 16.203 + 16.204 +reg [`LM32_JTAG_STATE_RNG] state; // Current state of FSM 16.205 + 16.206 +///////////////////////////////////////////////////// 16.207 +// Combinational Logic 16.208 +///////////////////////////////////////////////////// 16.209 + 16.210 +`ifdef CFG_HW_DEBUG_ENABLED 16.211 +assign jtag_csr_write_data = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3}; 16.212 +assign jtag_csr = jtag_byte_4[`LM32_CSR_RNG]; 16.213 +assign jtag_address = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3}; 16.214 +assign jtag_write_data = jtag_byte_4; 16.215 +`endif 16.216 + 16.217 +// Generate status flags for reading via the JTAG interface 16.218 +`ifdef CFG_JTAG_UART_ENABLED 16.219 +assign jtag_reg_addr_d[1:0] = {uart_rx_valid, uart_tx_valid}; 16.220 +`else 16.221 +assign jtag_reg_addr_d[1:0] = 2'b00; 16.222 +`endif 16.223 +`ifdef CFG_HW_DEBUG_ENABLED 16.224 +assign jtag_reg_addr_d[2] = processing; 16.225 +`else 16.226 +assign jtag_reg_addr_d[2] = 1'b0; 16.227 +`endif 16.228 + 16.229 +`ifdef CFG_JTAG_UART_ENABLED 16.230 +assign jtx_csr_read_data = {{`LM32_WORD_WIDTH-9{1'b0}}, uart_tx_valid, 8'h00}; 16.231 +assign jrx_csr_read_data = {{`LM32_WORD_WIDTH-9{1'b0}}, uart_rx_valid, uart_rx_byte}; 16.232 +`endif 16.233 + 16.234 +///////////////////////////////////////////////////// 16.235 +// Sequential Logic 16.236 +///////////////////////////////////////////////////// 16.237 + 16.238 +// Toggle a flag when a JTAG write occurs 16.239 + 16.240 +always @(negedge jtag_update `CFG_RESET_SENSITIVITY) 16.241 +begin 16.242 +if (rst_i == `TRUE) 16.243 + rx_toggle <= 1'b0; 16.244 +else 16.245 + rx_toggle <= ~rx_toggle; 16.246 +end 16.247 + 16.248 +always @(*) 16.249 +begin 16.250 + rx_byte = jtag_reg_q; 16.251 + rx_addr = jtag_reg_addr_q; 16.252 +end 16.253 + 16.254 +// Clock domain crossing from JTAG clock domain to CPU clock domain 16.255 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 16.256 +begin 16.257 + if (rst_i == `TRUE) 16.258 + begin 16.259 + rx_toggle_r <= 1'b0; 16.260 + rx_toggle_r_r <= 1'b0; 16.261 + rx_toggle_r_r_r <= 1'b0; 16.262 + end 16.263 + else 16.264 + begin 16.265 + rx_toggle_r <= rx_toggle; 16.266 + rx_toggle_r_r <= rx_toggle_r; 16.267 + rx_toggle_r_r_r <= rx_toggle_r_r; 16.268 + end 16.269 +end 16.270 + 16.271 +// LM32 debug protocol state machine 16.272 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 16.273 +begin 16.274 + if (rst_i == `TRUE) 16.275 + begin 16.276 + state <= `LM32_JTAG_STATE_READ_COMMAND; 16.277 + command <= 4'b0000; 16.278 + jtag_reg_d <= 8'h00; 16.279 +`ifdef CFG_HW_DEBUG_ENABLED 16.280 + processing <= `FALSE; 16.281 + jtag_csr_write_enable <= `FALSE; 16.282 + jtag_read_enable <= `FALSE; 16.283 + jtag_write_enable <= `FALSE; 16.284 +`endif 16.285 +`ifdef CFG_DEBUG_ENABLED 16.286 + jtag_break <= `FALSE; 16.287 + jtag_reset <= `FALSE; 16.288 +`endif 16.289 +`ifdef CFG_JTAG_UART_ENABLED 16.290 + uart_tx_byte <= 8'h00; 16.291 + uart_tx_valid <= `FALSE; 16.292 + uart_rx_byte <= 8'h00; 16.293 + uart_rx_valid <= `FALSE; 16.294 +`endif 16.295 + end 16.296 + else 16.297 + begin 16.298 +`ifdef CFG_JTAG_UART_ENABLED 16.299 + if ((csr_write_enable == `TRUE) && (stall_x == `FALSE)) 16.300 + begin 16.301 + case (csr) 16.302 + `LM32_CSR_JTX: 16.303 + begin 16.304 + // Set flag indicating data is available 16.305 + uart_tx_byte <= csr_write_data[`LM32_BYTE_0_RNG]; 16.306 + uart_tx_valid <= `TRUE; 16.307 + end 16.308 + `LM32_CSR_JRX: 16.309 + begin 16.310 + // Clear flag indidicating data has been received 16.311 + uart_rx_valid <= `FALSE; 16.312 + end 16.313 + endcase 16.314 + end 16.315 +`endif 16.316 +`ifdef CFG_DEBUG_ENABLED 16.317 + // When an exception has occured, clear the requests 16.318 + if (exception_q_w == `TRUE) 16.319 + begin 16.320 + jtag_break <= `FALSE; 16.321 + jtag_reset <= `FALSE; 16.322 + end 16.323 +`endif 16.324 + case (state) 16.325 + `LM32_JTAG_STATE_READ_COMMAND: 16.326 + begin 16.327 + // Wait for rx register to toggle which indicates new data is available 16.328 + if (rx_toggle_r_r != rx_toggle_r_r_r) 16.329 + begin 16.330 + command <= rx_byte[7:4]; 16.331 + case (rx_addr) 16.332 +`ifdef CFG_DEBUG_ENABLED 16.333 + `LM32_DP: 16.334 + begin 16.335 + case (rx_byte[7:4]) 16.336 +`ifdef CFG_HW_DEBUG_ENABLED 16.337 + `LM32_DP_READ_MEMORY: 16.338 + state <= `LM32_JTAG_STATE_READ_BYTE_0; 16.339 + `LM32_DP_READ_SEQUENTIAL: 16.340 + begin 16.341 + {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1; 16.342 + state <= `LM32_JTAG_STATE_PROCESS_COMMAND; 16.343 + end 16.344 + `LM32_DP_WRITE_MEMORY: 16.345 + state <= `LM32_JTAG_STATE_READ_BYTE_0; 16.346 + `LM32_DP_WRITE_SEQUENTIAL: 16.347 + begin 16.348 + {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1; 16.349 + state <= 5; 16.350 + end 16.351 + `LM32_DP_WRITE_CSR: 16.352 + state <= `LM32_JTAG_STATE_READ_BYTE_0; 16.353 +`endif 16.354 + `LM32_DP_BREAK: 16.355 + begin 16.356 +`ifdef CFG_JTAG_UART_ENABLED 16.357 + uart_rx_valid <= `FALSE; 16.358 + uart_tx_valid <= `FALSE; 16.359 +`endif 16.360 + jtag_break <= `TRUE; 16.361 + end 16.362 + `LM32_DP_RESET: 16.363 + begin 16.364 +`ifdef CFG_JTAG_UART_ENABLED 16.365 + uart_rx_valid <= `FALSE; 16.366 + uart_tx_valid <= `FALSE; 16.367 +`endif 16.368 + jtag_reset <= `TRUE; 16.369 + end 16.370 + endcase 16.371 + end 16.372 +`endif 16.373 +`ifdef CFG_JTAG_UART_ENABLED 16.374 + `LM32_TX: 16.375 + begin 16.376 + uart_rx_byte <= rx_byte; 16.377 + uart_rx_valid <= `TRUE; 16.378 + end 16.379 + `LM32_RX: 16.380 + begin 16.381 + jtag_reg_d <= uart_tx_byte; 16.382 + uart_tx_valid <= `FALSE; 16.383 + end 16.384 +`endif 16.385 + default: 16.386 + ; 16.387 + endcase 16.388 + end 16.389 + end 16.390 +`ifdef CFG_HW_DEBUG_ENABLED 16.391 + `LM32_JTAG_STATE_READ_BYTE_0: 16.392 + begin 16.393 + if (rx_toggle_r_r != rx_toggle_r_r_r) 16.394 + begin 16.395 + jtag_byte_0 <= rx_byte; 16.396 + state <= `LM32_JTAG_STATE_READ_BYTE_1; 16.397 + end 16.398 + end 16.399 + `LM32_JTAG_STATE_READ_BYTE_1: 16.400 + begin 16.401 + if (rx_toggle_r_r != rx_toggle_r_r_r) 16.402 + begin 16.403 + jtag_byte_1 <= rx_byte; 16.404 + state <= `LM32_JTAG_STATE_READ_BYTE_2; 16.405 + end 16.406 + end 16.407 + `LM32_JTAG_STATE_READ_BYTE_2: 16.408 + begin 16.409 + if (rx_toggle_r_r != rx_toggle_r_r_r) 16.410 + begin 16.411 + jtag_byte_2 <= rx_byte; 16.412 + state <= `LM32_JTAG_STATE_READ_BYTE_3; 16.413 + end 16.414 + end 16.415 + `LM32_JTAG_STATE_READ_BYTE_3: 16.416 + begin 16.417 + if (rx_toggle_r_r != rx_toggle_r_r_r) 16.418 + begin 16.419 + jtag_byte_3 <= rx_byte; 16.420 + if (command == `LM32_DP_READ_MEMORY) 16.421 + state <= `LM32_JTAG_STATE_PROCESS_COMMAND; 16.422 + else 16.423 + state <= `LM32_JTAG_STATE_READ_BYTE_4; 16.424 + end 16.425 + end 16.426 + `LM32_JTAG_STATE_READ_BYTE_4: 16.427 + begin 16.428 + if (rx_toggle_r_r != rx_toggle_r_r_r) 16.429 + begin 16.430 + jtag_byte_4 <= rx_byte; 16.431 + state <= `LM32_JTAG_STATE_PROCESS_COMMAND; 16.432 + end 16.433 + end 16.434 + `LM32_JTAG_STATE_PROCESS_COMMAND: 16.435 + begin 16.436 + case (command) 16.437 + `LM32_DP_READ_MEMORY, 16.438 + `LM32_DP_READ_SEQUENTIAL: 16.439 + begin 16.440 + jtag_read_enable <= `TRUE; 16.441 + processing <= `TRUE; 16.442 + state <= `LM32_JTAG_STATE_WAIT_FOR_MEMORY; 16.443 + end 16.444 + `LM32_DP_WRITE_MEMORY, 16.445 + `LM32_DP_WRITE_SEQUENTIAL: 16.446 + begin 16.447 + jtag_write_enable <= `TRUE; 16.448 + processing <= `TRUE; 16.449 + state <= `LM32_JTAG_STATE_WAIT_FOR_MEMORY; 16.450 + end 16.451 + `LM32_DP_WRITE_CSR: 16.452 + begin 16.453 + jtag_csr_write_enable <= `TRUE; 16.454 + processing <= `TRUE; 16.455 + state <= `LM32_JTAG_STATE_WAIT_FOR_CSR; 16.456 + end 16.457 + endcase 16.458 + end 16.459 + `LM32_JTAG_STATE_WAIT_FOR_MEMORY: 16.460 + begin 16.461 + if (jtag_access_complete == `TRUE) 16.462 + begin 16.463 + jtag_read_enable <= `FALSE; 16.464 + jtag_reg_d <= jtag_read_data; 16.465 + jtag_write_enable <= `FALSE; 16.466 + processing <= `FALSE; 16.467 + state <= `LM32_JTAG_STATE_READ_COMMAND; 16.468 + end 16.469 + end 16.470 + `LM32_JTAG_STATE_WAIT_FOR_CSR: 16.471 + begin 16.472 + jtag_csr_write_enable <= `FALSE; 16.473 + processing <= `FALSE; 16.474 + state <= `LM32_JTAG_STATE_READ_COMMAND; 16.475 + end 16.476 +`endif 16.477 + endcase 16.478 + end 16.479 +end 16.480 + 16.481 +endmodule 16.482 + 16.483 +`endif
17.1 diff -r 000000000000 -r cd0b58aa6f83 lm32_load_store_unit.v 17.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 17.3 +++ b/lm32_load_store_unit.v Sun Apr 04 20:40:03 2010 +0100 17.4 @@ -0,0 +1,808 @@ 17.5 +// ============================================================================= 17.6 +// COPYRIGHT NOTICE 17.7 +// Copyright 2006 (c) Lattice Semiconductor Corporation 17.8 +// ALL RIGHTS RESERVED 17.9 +// This confidential and proprietary software may be used only as authorised by 17.10 +// a licensing agreement from Lattice Semiconductor Corporation. 17.11 +// The entire notice above must be reproduced on all authorized copies and 17.12 +// copies may only be made to the extent permitted by a licensing agreement from 17.13 +// Lattice Semiconductor Corporation. 17.14 +// 17.15 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 17.16 +// 5555 NE Moore Court 408-826-6000 (other locations) 17.17 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 17.18 +// U.S.A email: techsupport@latticesemi.com 17.19 +// =============================================================================/ 17.20 +// FILE DETAILS 17.21 +// Project : LatticeMico32 17.22 +// File : lm32_load_store_unit.v 17.23 +// Title : Load and store unit 17.24 +// Dependencies : lm32_include.v 17.25 +// Version : 6.1.17 17.26 +// : Initial Release 17.27 +// Version : 7.0SP2, 3.0 17.28 +// : No Change 17.29 +// Version : 3.1 17.30 +// : Instead of disallowing an instruction cache miss on a data cache 17.31 +// : miss, both can now occur at the same time. If both occur at same 17.32 +// : time, then restart address is the address of instruction that 17.33 +// : caused data cache miss. 17.34 +// Version : 3.2 17.35 +// : EBRs use SYNC resets instead of ASYNC resets. 17.36 +// Version : 3.3 17.37 +// : Support for new non-cacheable Data Memory that is accessible by 17.38 +// : the data port and has a one cycle access latency. 17.39 +// Version : 3.4 17.40 +// : No change 17.41 +// Version : 3.5 17.42 +// : Bug fix: Inline memory is correctly generated if it is not a 17.43 +// : power-of-two 17.44 +// ============================================================================= 17.45 + 17.46 +`include "lm32_include.v" 17.47 + 17.48 +///////////////////////////////////////////////////// 17.49 +// Module interface 17.50 +///////////////////////////////////////////////////// 17.51 + 17.52 +module lm32_load_store_unit ( 17.53 + // ----- Inputs ------- 17.54 + clk_i, 17.55 + rst_i, 17.56 + // From pipeline 17.57 + stall_a, 17.58 + stall_x, 17.59 + stall_m, 17.60 + kill_x, 17.61 + kill_m, 17.62 + exception_m, 17.63 + store_operand_x, 17.64 + load_store_address_x, 17.65 + load_store_address_m, 17.66 + load_store_address_w, 17.67 + load_x, 17.68 + store_x, 17.69 + load_q_x, 17.70 + store_q_x, 17.71 + load_q_m, 17.72 + store_q_m, 17.73 + sign_extend_x, 17.74 + size_x, 17.75 +`ifdef CFG_DCACHE_ENABLED 17.76 + dflush, 17.77 +`endif 17.78 +`ifdef CFG_IROM_ENABLED 17.79 + irom_data_m, 17.80 +`endif 17.81 + // From Wishbone 17.82 + d_dat_i, 17.83 + d_ack_i, 17.84 + d_err_i, 17.85 + d_rty_i, 17.86 + // ----- Outputs ------- 17.87 + // To pipeline 17.88 +`ifdef CFG_DCACHE_ENABLED 17.89 + dcache_refill_request, 17.90 + dcache_restart_request, 17.91 + dcache_stall_request, 17.92 + dcache_refilling, 17.93 +`endif 17.94 +`ifdef CFG_IROM_ENABLED 17.95 + irom_store_data_m, 17.96 + irom_address_xm, 17.97 + irom_we_xm, 17.98 + irom_stall_request_x, 17.99 +`endif 17.100 + load_data_w, 17.101 + stall_wb_load, 17.102 + // To Wishbone 17.103 + d_dat_o, 17.104 + d_adr_o, 17.105 + d_cyc_o, 17.106 + d_sel_o, 17.107 + d_stb_o, 17.108 + d_we_o, 17.109 + d_cti_o, 17.110 + d_lock_o, 17.111 + d_bte_o 17.112 + ); 17.113 + 17.114 +///////////////////////////////////////////////////// 17.115 +// Parameters 17.116 +///////////////////////////////////////////////////// 17.117 + 17.118 +parameter associativity = 1; // Associativity of the cache (Number of ways) 17.119 +parameter sets = 512; // Number of sets 17.120 +parameter bytes_per_line = 16; // Number of bytes per cache line 17.121 +parameter base_address = 0; // Base address of cachable memory 17.122 +parameter limit = 0; // Limit (highest address) of cachable memory 17.123 + 17.124 +// For bytes_per_line == 4, we set 1 so part-select range isn't reversed, even though not really used 17.125 +localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2; 17.126 +localparam addr_offset_lsb = 2; 17.127 +localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1); 17.128 + 17.129 +///////////////////////////////////////////////////// 17.130 +// Inputs 17.131 +///////////////////////////////////////////////////// 17.132 + 17.133 +input clk_i; // Clock 17.134 +input rst_i; // Reset 17.135 + 17.136 +input stall_a; // A stage stall 17.137 +input stall_x; // X stage stall 17.138 +input stall_m; // M stage stall 17.139 +input kill_x; // Kill instruction in X stage 17.140 +input kill_m; // Kill instruction in M stage 17.141 +input exception_m; // An exception occured in the M stage 17.142 + 17.143 +input [`LM32_WORD_RNG] store_operand_x; // Data read from register to store 17.144 +input [`LM32_WORD_RNG] load_store_address_x; // X stage load/store address 17.145 +input [`LM32_WORD_RNG] load_store_address_m; // M stage load/store address 17.146 +input [1:0] load_store_address_w; // W stage load/store address (only least two significant bits are needed) 17.147 +input load_x; // Load instruction in X stage 17.148 +input store_x; // Store instruction in X stage 17.149 +input load_q_x; // Load instruction in X stage 17.150 +input store_q_x; // Store instruction in X stage 17.151 +input load_q_m; // Load instruction in M stage 17.152 +input store_q_m; // Store instruction in M stage 17.153 +input sign_extend_x; // Whether load instruction in X stage should sign extend or zero extend 17.154 +input [`LM32_SIZE_RNG] size_x; // Size of load or store (byte, hword, word) 17.155 + 17.156 +`ifdef CFG_DCACHE_ENABLED 17.157 +input dflush; // Flush the data cache 17.158 +`endif 17.159 + 17.160 +`ifdef CFG_IROM_ENABLED 17.161 +input [`LM32_WORD_RNG] irom_data_m; // Data from Instruction-ROM 17.162 +`endif 17.163 + 17.164 +input [`LM32_WORD_RNG] d_dat_i; // Data Wishbone interface read data 17.165 +input d_ack_i; // Data Wishbone interface acknowledgement 17.166 +input d_err_i; // Data Wishbone interface error 17.167 +input d_rty_i; // Data Wishbone interface retry 17.168 + 17.169 +///////////////////////////////////////////////////// 17.170 +// Outputs 17.171 +///////////////////////////////////////////////////// 17.172 + 17.173 +`ifdef CFG_DCACHE_ENABLED 17.174 +output dcache_refill_request; // Request to refill data cache 17.175 +wire dcache_refill_request; 17.176 +output dcache_restart_request; // Request to restart the instruction that caused a data cache miss 17.177 +wire dcache_restart_request; 17.178 +output dcache_stall_request; // Data cache stall request 17.179 +wire dcache_stall_request; 17.180 +output dcache_refilling; 17.181 +wire dcache_refilling; 17.182 +`endif 17.183 + 17.184 +`ifdef CFG_IROM_ENABLED 17.185 +output irom_store_data_m; // Store data to Instruction ROM 17.186 +wire [`LM32_WORD_RNG] irom_store_data_m; 17.187 +output [`LM32_WORD_RNG] irom_address_xm; // Load/store address to Instruction ROM 17.188 +wire [`LM32_WORD_RNG] irom_address_xm; 17.189 +output irom_we_xm; // Write-enable of 2nd port of Instruction ROM 17.190 +wire irom_we_xm; 17.191 +output irom_stall_request_x; // Stall instruction in D stage 17.192 +wire irom_stall_request_x; 17.193 +`endif 17.194 + 17.195 +output [`LM32_WORD_RNG] load_data_w; // Result of a load instruction 17.196 +reg [`LM32_WORD_RNG] load_data_w; 17.197 +output stall_wb_load; // Request to stall pipeline due to a load from the Wishbone interface 17.198 +reg stall_wb_load; 17.199 + 17.200 +output [`LM32_WORD_RNG] d_dat_o; // Data Wishbone interface write data 17.201 +reg [`LM32_WORD_RNG] d_dat_o; 17.202 +output [`LM32_WORD_RNG] d_adr_o; // Data Wishbone interface address 17.203 +reg [`LM32_WORD_RNG] d_adr_o; 17.204 +output d_cyc_o; // Data Wishbone interface cycle 17.205 +reg d_cyc_o; 17.206 +output [`LM32_BYTE_SELECT_RNG] d_sel_o; // Data Wishbone interface byte select 17.207 +reg [`LM32_BYTE_SELECT_RNG] d_sel_o; 17.208 +output d_stb_o; // Data Wishbone interface strobe 17.209 +reg d_stb_o; 17.210 +output d_we_o; // Data Wishbone interface write enable 17.211 +reg d_we_o; 17.212 +output [`LM32_CTYPE_RNG] d_cti_o; // Data Wishbone interface cycle type 17.213 +reg [`LM32_CTYPE_RNG] d_cti_o; 17.214 +output d_lock_o; // Date Wishbone interface lock bus 17.215 +reg d_lock_o; 17.216 +output [`LM32_BTYPE_RNG] d_bte_o; // Data Wishbone interface burst type 17.217 +wire [`LM32_BTYPE_RNG] d_bte_o; 17.218 + 17.219 +///////////////////////////////////////////////////// 17.220 +// Internal nets and registers 17.221 +///////////////////////////////////////////////////// 17.222 + 17.223 +// Microcode pipeline registers - See inputs for description 17.224 +reg [`LM32_SIZE_RNG] size_m; 17.225 +reg [`LM32_SIZE_RNG] size_w; 17.226 +reg sign_extend_m; 17.227 +reg sign_extend_w; 17.228 +reg [`LM32_WORD_RNG] store_data_x; 17.229 +reg [`LM32_WORD_RNG] store_data_m; 17.230 +reg [`LM32_BYTE_SELECT_RNG] byte_enable_x; 17.231 +reg [`LM32_BYTE_SELECT_RNG] byte_enable_m; 17.232 +wire [`LM32_WORD_RNG] data_m; 17.233 +reg [`LM32_WORD_RNG] data_w; 17.234 + 17.235 +`ifdef CFG_DCACHE_ENABLED 17.236 +wire dcache_select_x; // Select data cache to load from / store to 17.237 +reg dcache_select_m; 17.238 +wire [`LM32_WORD_RNG] dcache_data_m; // Data read from cache 17.239 +wire [`LM32_WORD_RNG] dcache_refill_address; // Address to refill data cache from 17.240 +reg dcache_refill_ready; // Indicates the next word of refill data is ready 17.241 +wire [`LM32_CTYPE_RNG] first_cycle_type; // First Wishbone cycle type 17.242 +wire [`LM32_CTYPE_RNG] next_cycle_type; // Next Wishbone cycle type 17.243 +wire last_word; // Indicates if this is the last word in the cache line 17.244 +wire [`LM32_WORD_RNG] first_address; // First cache refill address 17.245 +`endif 17.246 +`ifdef CFG_DRAM_ENABLED 17.247 +wire dram_select_x; // Select data RAM to load from / store to 17.248 +reg dram_select_m; 17.249 +reg dram_bypass_en; // RAW in data RAM; read latched (bypass) value rather than value from memory 17.250 +reg [`LM32_WORD_RNG] dram_bypass_data; // Latched value of store'd data to data RAM 17.251 +wire [`LM32_WORD_RNG] dram_data_out; // Data read from data RAM 17.252 +wire [`LM32_WORD_RNG] dram_data_m; // Data read from data RAM: bypass value or value from memory 17.253 +wire [`LM32_WORD_RNG] dram_store_data_m; // Data to write to RAM 17.254 +`endif 17.255 +wire wb_select_x; // Select Wishbone to load from / store to 17.256 +`ifdef CFG_IROM_ENABLED 17.257 +wire irom_select_x; // Select instruction ROM to load from / store to 17.258 +reg irom_select_m; 17.259 +`endif 17.260 +reg wb_select_m; 17.261 +reg [`LM32_WORD_RNG] wb_data_m; // Data read from Wishbone 17.262 +reg wb_load_complete; // Indicates when a Wishbone load is complete 17.263 + 17.264 +///////////////////////////////////////////////////// 17.265 +// Functions 17.266 +///////////////////////////////////////////////////// 17.267 + 17.268 +`include "lm32_functions.v" 17.269 + 17.270 +///////////////////////////////////////////////////// 17.271 +// Instantiations 17.272 +///////////////////////////////////////////////////// 17.273 + 17.274 +`ifdef CFG_DRAM_ENABLED 17.275 + // Data RAM 17.276 + pmi_ram_dp_true 17.277 + #( 17.278 + // ----- Parameters ------- 17.279 + .pmi_family (`LATTICE_FAMILY), 17.280 + 17.281 + //.pmi_addr_depth_a (1 << (clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)), 17.282 + //.pmi_addr_width_a ((clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)), 17.283 + //.pmi_data_width_a (`LM32_WORD_WIDTH), 17.284 + //.pmi_addr_depth_b (1 << (clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)), 17.285 + //.pmi_addr_width_b ((clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)), 17.286 + //.pmi_data_width_b (`LM32_WORD_WIDTH), 17.287 + 17.288 + .pmi_addr_depth_a (`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1), 17.289 + .pmi_addr_width_a (clogb2_v1(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)), 17.290 + .pmi_data_width_a (`LM32_WORD_WIDTH), 17.291 + .pmi_addr_depth_b (`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1), 17.292 + .pmi_addr_width_b (clogb2_v1(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)), 17.293 + .pmi_data_width_b (`LM32_WORD_WIDTH), 17.294 + 17.295 + .pmi_regmode_a ("noreg"), 17.296 + .pmi_regmode_b ("noreg"), 17.297 + .pmi_gsr ("enable"), 17.298 + .pmi_resetmode ("sync"), 17.299 + .pmi_init_file (`CFG_DRAM_INIT_FILE), 17.300 + .pmi_init_file_format (`CFG_DRAM_INIT_FILE_FORMAT), 17.301 + .module_type ("pmi_ram_dp_true") 17.302 + ) 17.303 + ram ( 17.304 + // ----- Inputs ------- 17.305 + .ClockA (clk_i), 17.306 + .ClockB (clk_i), 17.307 + .ResetA (rst_i), 17.308 + .ResetB (rst_i), 17.309 + .DataInA ({32{1'b0}}), 17.310 + .DataInB (dram_store_data_m), 17.311 + .AddressA (load_store_address_x[(clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)+2-1:2]), 17.312 + .AddressB (load_store_address_m[(clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)+2-1:2]), 17.313 + // .ClockEnA (!stall_x & (load_x | store_x)), 17.314 + .ClockEnA (!stall_x), 17.315 + .ClockEnB (!stall_m), 17.316 + .WrA (`FALSE), 17.317 + .WrB (store_q_m & dram_select_m), 17.318 + // ----- Outputs ------- 17.319 + .QA (dram_data_out), 17.320 + .QB () 17.321 + ); 17.322 + 17.323 + /*---------------------------------------------------------------------- 17.324 + EBRs cannot perform reads from location 'written to' on the same clock 17.325 + edge. Therefore bypass logic is required to latch the store'd value 17.326 + and use it for the load (instead of value from memory). 17.327 + ----------------------------------------------------------------------*/ 17.328 + always @(posedge clk_i `CFG_RESET_SENSITIVITY) 17.329 + if (rst_i == `TRUE) 17.330 + begin 17.331 + dram_bypass_en <= `FALSE; 17.332 + dram_bypass_data <= 0; 17.333 + end 17.334 + else 17.335 + begin 17.336 + if (stall_x == `FALSE) 17.337 + dram_bypass_data <= dram_store_data_m; 17.338 + 17.339 + if ( (stall_m == `FALSE) 17.340 + && (stall_x == `FALSE) 17.341 + && (store_q_m == `TRUE) 17.342 + && ( (load_x == `TRUE) 17.343 + || (store_x == `TRUE) 17.344 + ) 17.345 + && (load_store_address_x[(`LM32_WORD_WIDTH-1):2] == load_store_address_m[(`LM32_WORD_WIDTH-1):2]) 17.346 + ) 17.347 + dram_bypass_en <= `TRUE; 17.348 + else 17.349 + if ( (dram_bypass_en == `TRUE) 17.350 + && (stall_x == `FALSE) 17.351 + ) 17.352 + dram_bypass_en <= `FALSE; 17.353 + end 17.354 + 17.355 + assign dram_data_m = dram_bypass_en ? dram_bypass_data : dram_data_out; 17.356 +`endif 17.357 + 17.358 +`ifdef CFG_DCACHE_ENABLED 17.359 +// Data cache 17.360 +lm32_dcache #( 17.361 + .associativity (associativity), 17.362 + .sets (sets), 17.363 + .bytes_per_line (bytes_per_line), 17.364 + .base_address (base_address), 17.365 + .limit (limit) 17.366 + ) dcache ( 17.367 + // ----- Inputs ----- 17.368 + .clk_i (clk_i), 17.369 + .rst_i (rst_i), 17.370 + .stall_a (stall_a), 17.371 + .stall_x (stall_x), 17.372 + .stall_m (stall_m), 17.373 + .address_x (load_store_address_x), 17.374 + .address_m (load_store_address_m), 17.375 + .load_q_m (load_q_m & dcache_select_m), 17.376 + .store_q_m (store_q_m & dcache_select_m), 17.377 + .store_data (store_data_m), 17.378 + .store_byte_select (byte_enable_m & {4{dcache_select_m}}), 17.379 + .refill_ready (dcache_refill_ready), 17.380 + .refill_data (wb_data_m), 17.381 + .dflush (dflush), 17.382 + // ----- Outputs ----- 17.383 + .stall_request (dcache_stall_request), 17.384 + .restart_request (dcache_restart_request), 17.385 + .refill_request (dcache_refill_request), 17.386 + .refill_address (dcache_refill_address), 17.387 + .refilling (dcache_refilling), 17.388 + .load_data (dcache_data_m) 17.389 + ); 17.390 +`endif 17.391 + 17.392 +///////////////////////////////////////////////////// 17.393 +// Combinational Logic 17.394 +///////////////////////////////////////////////////// 17.395 + 17.396 +// Select where data should be loaded from / stored to 17.397 +`ifdef CFG_DRAM_ENABLED 17.398 + assign dram_select_x = (load_store_address_x >= `CFG_DRAM_BASE_ADDRESS) 17.399 + && (load_store_address_x <= `CFG_DRAM_LIMIT); 17.400 +`endif 17.401 + 17.402 +`ifdef CFG_IROM_ENABLED 17.403 + assign irom_select_x = (load_store_address_x >= `CFG_IROM_BASE_ADDRESS) 17.404 + && (load_store_address_x <= `CFG_IROM_LIMIT); 17.405 +`endif 17.406 + 17.407 +`ifdef CFG_DCACHE_ENABLED 17.408 + assign dcache_select_x = (load_store_address_x >= `CFG_DCACHE_BASE_ADDRESS) 17.409 + && (load_store_address_x <= `CFG_DCACHE_LIMIT) 17.410 +`ifdef CFG_DRAM_ENABLED 17.411 + && (dram_select_x == `FALSE) 17.412 +`endif 17.413 +`ifdef CFG_IROM_ENABLED 17.414 + && (irom_select_x == `FALSE) 17.415 +`endif 17.416 + ; 17.417 +`endif 17.418 + 17.419 + assign wb_select_x = `TRUE 17.420 +`ifdef CFG_DCACHE_ENABLED 17.421 + && !dcache_select_x 17.422 +`endif 17.423 +`ifdef CFG_DRAM_ENABLED 17.424 + && !dram_select_x 17.425 +`endif 17.426 +`ifdef CFG_IROM_ENABLED 17.427 + && !irom_select_x 17.428 +`endif 17.429 + ; 17.430 + 17.431 +// Make sure data to store is in correct byte lane 17.432 +always @(*) 17.433 +begin 17.434 + case (size_x) 17.435 + `LM32_SIZE_BYTE: store_data_x = {4{store_operand_x[7:0]}}; 17.436 + `LM32_SIZE_HWORD: store_data_x = {2{store_operand_x[15:0]}}; 17.437 + `LM32_SIZE_WORD: store_data_x = store_operand_x; 17.438 + default: store_data_x = {`LM32_WORD_WIDTH{1'bx}}; 17.439 + endcase 17.440 +end 17.441 + 17.442 +// Generate byte enable accoring to size of load or store and address being accessed 17.443 +always @(*) 17.444 +begin 17.445 + casez ({size_x, load_store_address_x[1:0]}) 17.446 + {`LM32_SIZE_BYTE, 2'b11}: byte_enable_x = 4'b0001; 17.447 + {`LM32_SIZE_BYTE, 2'b10}: byte_enable_x = 4'b0010; 17.448 + {`LM32_SIZE_BYTE, 2'b01}: byte_enable_x = 4'b0100; 17.449 + {`LM32_SIZE_BYTE, 2'b00}: byte_enable_x = 4'b1000; 17.450 + {`LM32_SIZE_HWORD, 2'b1?}: byte_enable_x = 4'b0011; 17.451 + {`LM32_SIZE_HWORD, 2'b0?}: byte_enable_x = 4'b1100; 17.452 + {`LM32_SIZE_WORD, 2'b??}: byte_enable_x = 4'b1111; 17.453 + default: byte_enable_x = 4'bxxxx; 17.454 + endcase 17.455 +end 17.456 + 17.457 +`ifdef CFG_DRAM_ENABLED 17.458 +// Only replace selected bytes 17.459 +assign dram_store_data_m[`LM32_BYTE_0_RNG] = byte_enable_m[0] ? store_data_m[`LM32_BYTE_0_RNG] : dram_data_m[`LM32_BYTE_0_RNG]; 17.460 +assign dram_store_data_m[`LM32_BYTE_1_RNG] = byte_enable_m[1] ? store_data_m[`LM32_BYTE_1_RNG] : dram_data_m[`LM32_BYTE_1_RNG]; 17.461 +assign dram_store_data_m[`LM32_BYTE_2_RNG] = byte_enable_m[2] ? store_data_m[`LM32_BYTE_2_RNG] : dram_data_m[`LM32_BYTE_2_RNG]; 17.462 +assign dram_store_data_m[`LM32_BYTE_3_RNG] = byte_enable_m[3] ? store_data_m[`LM32_BYTE_3_RNG] : dram_data_m[`LM32_BYTE_3_RNG]; 17.463 +`endif 17.464 + 17.465 +`ifdef CFG_IROM_ENABLED 17.466 +// Only replace selected bytes 17.467 +assign irom_store_data_m[`LM32_BYTE_0_RNG] = byte_enable_m[0] ? store_data_m[`LM32_BYTE_0_RNG] : irom_data_m[`LM32_BYTE_0_RNG]; 17.468 +assign irom_store_data_m[`LM32_BYTE_1_RNG] = byte_enable_m[1] ? store_data_m[`LM32_BYTE_1_RNG] : irom_data_m[`LM32_BYTE_1_RNG]; 17.469 +assign irom_store_data_m[`LM32_BYTE_2_RNG] = byte_enable_m[2] ? store_data_m[`LM32_BYTE_2_RNG] : irom_data_m[`LM32_BYTE_2_RNG]; 17.470 +assign irom_store_data_m[`LM32_BYTE_3_RNG] = byte_enable_m[3] ? store_data_m[`LM32_BYTE_3_RNG] : irom_data_m[`LM32_BYTE_3_RNG]; 17.471 +`endif 17.472 + 17.473 +`ifdef CFG_IROM_ENABLED 17.474 + // Instead of implementing a byte-addressable instruction ROM (for store byte instruction), 17.475 + // a load-and-store architecture is used wherein a 32-bit value is loaded, the requisite 17.476 + // byte is replaced, and the whole 32-bit value is written back 17.477 + 17.478 + assign irom_address_xm = ((irom_select_m == `TRUE) && (store_q_m == `TRUE)) 17.479 + ? load_store_address_m 17.480 + : load_store_address_x; 17.481 + 17.482 + // All store instructions perform a write operation in the M stage 17.483 + assign irom_we_xm = (irom_select_m == `TRUE) 17.484 + && (store_q_m == `TRUE); 17.485 + 17.486 + // A single port in instruction ROM is available to load-store unit for doing loads/stores. 17.487 + // Since every store requires a load (in X stage) and then a store (in M stage), we cannot 17.488 + // allow load (or store) instructions sequentially after the store instructions to proceed 17.489 + // until the store instruction has vacated M stage (i.e., completed the store operation) 17.490 + assign irom_stall_request_x = (irom_select_x == `TRUE) 17.491 + && (store_q_x == `TRUE); 17.492 +`endif 17.493 + 17.494 +`ifdef CFG_DCACHE_ENABLED 17.495 + `ifdef CFG_DRAM_ENABLED 17.496 + `ifdef CFG_IROM_ENABLED 17.497 + // WB + DC + DRAM + IROM 17.498 + assign data_m = wb_select_m == `TRUE 17.499 + ? wb_data_m 17.500 + : dram_select_m == `TRUE 17.501 + ? dram_data_m 17.502 + : irom_select_m == `TRUE 17.503 + ? irom_data_m 17.504 + : dcache_data_m; 17.505 + `else 17.506 + // WB + DC + DRAM 17.507 + assign data_m = wb_select_m == `TRUE 17.508 + ? wb_data_m 17.509 + : dram_select_m == `TRUE 17.510 + ? dram_data_m 17.511 + : dcache_data_m; 17.512 + `endif 17.513 + `else 17.514 + `ifdef CFG_IROM_ENABLED 17.515 + // WB + DC + IROM 17.516 + assign data_m = wb_select_m == `TRUE 17.517 + ? wb_data_m 17.518 + : irom_select_m == `TRUE 17.519 + ? irom_data_m 17.520 + : dcache_data_m; 17.521 + `else 17.522 + // WB + DC 17.523 + assign data_m = wb_select_m == `TRUE 17.524 + ? wb_data_m 17.525 + : dcache_data_m; 17.526 + `endif 17.527 + `endif 17.528 +`else 17.529 + `ifdef CFG_DRAM_ENABLED 17.530 + `ifdef CFG_IROM_ENABLED 17.531 + // WB + DRAM + IROM 17.532 + assign data_m = wb_select_m == `TRUE 17.533 + ? wb_data_m 17.534 + : dram_select_m == `TRUE 17.535 + ? dram_data_m 17.536 + : irom_data_m; 17.537 + `else 17.538 + // WB + DRAM 17.539 + assign data_m = wb_select_m == `TRUE 17.540 + ? wb_data_m 17.541 + : dram_data_m; 17.542 + `endif 17.543 + `else 17.544 + `ifdef CFG_IROM_ENABLED 17.545 + // WB + IROM 17.546 + assign data_m = wb_select_m == `TRUE 17.547 + ? wb_data_m 17.548 + : irom_data_m; 17.549 + `else 17.550 + // WB 17.551 + assign data_m = wb_data_m; 17.552 + `endif 17.553 + `endif 17.554 +`endif 17.555 + 17.556 +// Sub-word selection and sign/zero-extension for loads 17.557 +always @(*) 17.558 +begin 17.559 + casez ({size_w, load_store_address_w[1:0]}) 17.560 + {`LM32_SIZE_BYTE, 2'b11}: load_data_w = {{24{sign_extend_w & data_w[7]}}, data_w[7:0]}; 17.561 + {`LM32_SIZE_BYTE, 2'b10}: load_data_w = {{24{sign_extend_w & data_w[15]}}, data_w[15:8]}; 17.562 + {`LM32_SIZE_BYTE, 2'b01}: load_data_w = {{24{sign_extend_w & data_w[23]}}, data_w[23:16]}; 17.563 + {`LM32_SIZE_BYTE, 2'b00}: load_data_w = {{24{sign_extend_w & data_w[31]}}, data_w[31:24]}; 17.564 + {`LM32_SIZE_HWORD, 2'b1?}: load_data_w = {{16{sign_extend_w & data_w[15]}}, data_w[15:0]}; 17.565 + {`LM32_SIZE_HWORD, 2'b0?}: load_data_w = {{16{sign_extend_w & data_w[31]}}, data_w[31:16]}; 17.566 + {`LM32_SIZE_WORD, 2'b??}: load_data_w = data_w; 17.567 + default: load_data_w = {`LM32_WORD_WIDTH{1'bx}}; 17.568 + endcase 17.569 +end 17.570 + 17.571 +// Unused/constant Wishbone signals 17.572 +assign d_bte_o = `LM32_BTYPE_LINEAR; 17.573 + 17.574 +`ifdef CFG_DCACHE_ENABLED 17.575 +// Generate signal to indicate last word in cache line 17.576 +generate 17.577 + case (bytes_per_line) 17.578 + 4: 17.579 + begin 17.580 +assign first_cycle_type = `LM32_CTYPE_END; 17.581 +assign next_cycle_type = `LM32_CTYPE_END; 17.582 +assign last_word = `TRUE; 17.583 +assign first_address = {dcache_refill_address[`LM32_WORD_WIDTH-1:2], 2'b00}; 17.584 + end 17.585 + 8: 17.586 + begin 17.587 +assign first_cycle_type = `LM32_CTYPE_INCREMENTING; 17.588 +assign next_cycle_type = `LM32_CTYPE_END; 17.589 +assign last_word = (&d_adr_o[addr_offset_msb:addr_offset_lsb]) == 1'b1; 17.590 +assign first_address = {dcache_refill_address[`LM32_WORD_WIDTH-1:addr_offset_msb+1], {addr_offset_width{1'b0}}, 2'b00}; 17.591 + end 17.592 + 16: 17.593 + begin 17.594 +assign first_cycle_type = `LM32_CTYPE_INCREMENTING; 17.595 +assign next_cycle_type = d_adr_o[addr_offset_msb] == 1'b1 ? `LM32_CTYPE_END : `LM32_CTYPE_INCREMENTING; 17.596 +assign last_word = (&d_adr_o[addr_offset_msb:addr_offset_lsb]) == 1'b1; 17.597 +assign first_address = {dcache_refill_address[`LM32_WORD_WIDTH-1:addr_offset_msb+1], {addr_offset_width{1'b0}}, 2'b00}; 17.598 + end 17.599 + endcase 17.600 +endgenerate 17.601 +`endif 17.602 + 17.603 +///////////////////////////////////////////////////// 17.604 +// Sequential Logic 17.605 +///////////////////////////////////////////////////// 17.606 + 17.607 +// Data Wishbone interface 17.608 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 17.609 +begin 17.610 + if (rst_i == `TRUE) 17.611 + begin 17.612 + d_cyc_o <= `FALSE; 17.613 + d_stb_o <= `FALSE; 17.614 + d_dat_o <= {`LM32_WORD_WIDTH{1'b0}}; 17.615 + d_adr_o <= {`LM32_WORD_WIDTH{1'b0}}; 17.616 + d_sel_o <= {`LM32_BYTE_SELECT_WIDTH{`FALSE}}; 17.617 + d_we_o <= `FALSE; 17.618 + d_cti_o <= `LM32_CTYPE_END; 17.619 + d_lock_o <= `FALSE; 17.620 + wb_data_m <= {`LM32_WORD_WIDTH{1'b0}}; 17.621 + wb_load_complete <= `FALSE; 17.622 + stall_wb_load <= `FALSE; 17.623 +`ifdef CFG_DCACHE_ENABLED 17.624 + dcache_refill_ready <= `FALSE; 17.625 +`endif 17.626 + end 17.627 + else 17.628 + begin 17.629 +`ifdef CFG_DCACHE_ENABLED 17.630 + // Refill ready should only be asserted for a single cycle 17.631 + dcache_refill_ready <= `FALSE; 17.632 +`endif 17.633 + // Is a Wishbone cycle already in progress? 17.634 + if (d_cyc_o == `TRUE) 17.635 + begin 17.636 + // Is the cycle complete? 17.637 + if ((d_ack_i == `TRUE) || (d_err_i == `TRUE)) 17.638 + begin 17.639 +`ifdef CFG_DCACHE_ENABLED 17.640 + if ((dcache_refilling == `TRUE) && (!last_word)) 17.641 + begin 17.642 + // Fetch next word of cache line 17.643 + d_adr_o[addr_offset_msb:addr_offset_lsb] <= d_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1; 17.644 + end 17.645 + else 17.646 +`endif 17.647 + begin 17.648 + // Refill/access complete 17.649 + d_cyc_o <= `FALSE; 17.650 + d_stb_o <= `FALSE; 17.651 + d_lock_o <= `FALSE; 17.652 + end 17.653 +`ifdef CFG_DCACHE_ENABLED 17.654 + d_cti_o <= next_cycle_type; 17.655 + // If we are performing a refill, indicate to cache next word of data is ready 17.656 + dcache_refill_ready <= dcache_refilling; 17.657 +`endif 17.658 + // Register data read from Wishbone interface 17.659 + wb_data_m <= d_dat_i; 17.660 + // Don't set when stores complete - otherwise we'll deadlock if load in m stage 17.661 + wb_load_complete <= !d_we_o; 17.662 + end 17.663 + // synthesis translate_off 17.664 + if (d_err_i == `TRUE) 17.665 + $display ("Data bus error. Address: %x", d_adr_o); 17.666 + // synthesis translate_on 17.667 + end 17.668 + else 17.669 + begin 17.670 +`ifdef CFG_DCACHE_ENABLED 17.671 + if (dcache_refill_request == `TRUE) 17.672 + begin 17.673 + // Start cache refill 17.674 + d_adr_o <= first_address; 17.675 + d_cyc_o <= `TRUE; 17.676 + d_sel_o <= {`LM32_WORD_WIDTH/8{`TRUE}}; 17.677 + d_stb_o <= `TRUE; 17.678 + d_we_o <= `FALSE; 17.679 + d_cti_o <= first_cycle_type; 17.680 + //d_lock_o <= `TRUE; 17.681 + end 17.682 + else 17.683 +`endif 17.684 + if ( (store_q_m == `TRUE) 17.685 + && (stall_m == `FALSE) 17.686 +`ifdef CFG_DRAM_ENABLED 17.687 + && (dram_select_m == `FALSE) 17.688 +`endif 17.689 +`ifdef CFG_IROM_ENABLED 17.690 + && (irom_select_m == `FALSE) 17.691 +`endif 17.692 + ) 17.693 + begin 17.694 + // Data cache is write through, so all stores go to memory 17.695 + d_dat_o <= store_data_m; 17.696 + d_adr_o <= load_store_address_m; 17.697 + d_cyc_o <= `TRUE; 17.698 + d_sel_o <= byte_enable_m; 17.699 + d_stb_o <= `TRUE; 17.700 + d_we_o <= `TRUE; 17.701 + d_cti_o <= `LM32_CTYPE_END; 17.702 + end 17.703 + else if ( (load_q_m == `TRUE) 17.704 + && (wb_select_m == `TRUE) 17.705 + && (wb_load_complete == `FALSE) 17.706 + // stall_m will be TRUE, because stall_wb_load will be TRUE 17.707 + ) 17.708 + begin 17.709 + // Read requested address 17.710 + stall_wb_load <= `FALSE; 17.711 + d_adr_o <= load_store_address_m; 17.712 + d_cyc_o <= `TRUE; 17.713 + d_sel_o <= byte_enable_m; 17.714 + d_stb_o <= `TRUE; 17.715 + d_we_o <= `FALSE; 17.716 + d_cti_o <= `LM32_CTYPE_END; 17.717 + end 17.718 + end 17.719 + // Clear load/store complete flag when instruction leaves M stage 17.720 + if (stall_m == `FALSE) 17.721 + wb_load_complete <= `FALSE; 17.722 + // When a Wishbone load first enters the M stage, we need to stall it 17.723 + if ((load_q_x == `TRUE) && (wb_select_x == `TRUE) && (stall_x == `FALSE)) 17.724 + stall_wb_load <= `TRUE; 17.725 + // Clear stall request if load instruction is killed 17.726 + if ((kill_m == `TRUE) || (exception_m == `TRUE)) 17.727 + stall_wb_load <= `FALSE; 17.728 + end 17.729 +end 17.730 + 17.731 +// Pipeline registers 17.732 + 17.733 +// X/M stage pipeline registers 17.734 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 17.735 +begin 17.736 + if (rst_i == `TRUE) 17.737 + begin 17.738 + sign_extend_m <= `FALSE; 17.739 + size_m <= 2'b00; 17.740 + byte_enable_m <= `FALSE; 17.741 + store_data_m <= {`LM32_WORD_WIDTH{1'b0}}; 17.742 +`ifdef CFG_DCACHE_ENABLED 17.743 + dcache_select_m <= `FALSE; 17.744 +`endif 17.745 +`ifdef CFG_DRAM_ENABLED 17.746 + dram_select_m <= `FALSE; 17.747 +`endif 17.748 +`ifdef CFG_IROM_ENABLED 17.749 + irom_select_m <= `FALSE; 17.750 +`endif 17.751 + wb_select_m <= `FALSE; 17.752 + end 17.753 + else 17.754 + begin 17.755 + if (stall_m == `FALSE) 17.756 + begin 17.757 + sign_extend_m <= sign_extend_x; 17.758 + size_m <= size_x; 17.759 + byte_enable_m <= byte_enable_x; 17.760 + store_data_m <= store_data_x; 17.761 +`ifdef CFG_DCACHE_ENABLED 17.762 + dcache_select_m <= dcache_select_x; 17.763 +`endif 17.764 +`ifdef CFG_DRAM_ENABLED 17.765 + dram_select_m <= dram_select_x; 17.766 +`endif 17.767 +`ifdef CFG_IROM_ENABLED 17.768 + irom_select_m <= irom_select_x; 17.769 +`endif 17.770 + wb_select_m <= wb_select_x; 17.771 + end 17.772 + end 17.773 +end 17.774 + 17.775 +// M/W stage pipeline registers 17.776 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 17.777 +begin 17.778 + if (rst_i == `TRUE) 17.779 + begin 17.780 + size_w <= 2'b00; 17.781 + data_w <= {`LM32_WORD_WIDTH{1'b0}}; 17.782 + sign_extend_w <= `FALSE; 17.783 + end 17.784 + else 17.785 + begin 17.786 + size_w <= size_m; 17.787 + data_w <= data_m; 17.788 + sign_extend_w <= sign_extend_m; 17.789 + end 17.790 +end 17.791 + 17.792 +///////////////////////////////////////////////////// 17.793 +// Behavioural Logic 17.794 +///////////////////////////////////////////////////// 17.795 + 17.796 +// synthesis translate_off 17.797 + 17.798 +// Check for non-aligned loads or stores 17.799 +always @(posedge clk_i) 17.800 +begin 17.801 + if (((load_q_m == `TRUE) || (store_q_m == `TRUE)) && (stall_m == `FALSE)) 17.802 + begin 17.803 + if ((size_m === `LM32_SIZE_HWORD) && (load_store_address_m[0] !== 1'b0)) 17.804 + $display ("Warning: Non-aligned halfword access. Address: 0x%0x Time: %0t.", load_store_address_m, $time); 17.805 + if ((size_m === `LM32_SIZE_WORD) && (load_store_address_m[1:0] !== 2'b00)) 17.806 + $display ("Warning: Non-aligned word access. Address: 0x%0x Time: %0t.", load_store_address_m, $time); 17.807 + end 17.808 +end 17.809 + 17.810 +// synthesis translate_on 17.811 + 17.812 +endmodule
18.1 diff -r 000000000000 -r cd0b58aa6f83 lm32_logic_op.v 18.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 18.3 +++ b/lm32_logic_op.v Sun Apr 04 20:40:03 2010 +0100 18.4 @@ -0,0 +1,76 @@ 18.5 +// ============================================================================= 18.6 +// COPYRIGHT NOTICE 18.7 +// Copyright 2006 (c) Lattice Semiconductor Corporation 18.8 +// ALL RIGHTS RESERVED 18.9 +// This confidential and proprietary software may be used only as authorised by 18.10 +// a licensing agreement from Lattice Semiconductor Corporation. 18.11 +// The entire notice above must be reproduced on all authorized copies and 18.12 +// copies may only be made to the extent permitted by a licensing agreement from 18.13 +// Lattice Semiconductor Corporation. 18.14 +// 18.15 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 18.16 +// 5555 NE Moore Court 408-826-6000 (other locations) 18.17 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 18.18 +// U.S.A email: techsupport@latticesemi.com 18.19 +// =============================================================================/ 18.20 +// FILE DETAILS 18.21 +// Project : LatticeMico32 18.22 +// File : lm32_logic_op.v 18.23 +// Title : Logic operations (and / or / not etc) 18.24 +// Dependencies : lm32_include.v 18.25 +// Version : 6.1.17 18.26 +// : Initial Release 18.27 +// Version : 7.0SP2, 3.0 18.28 +// : No Change 18.29 +// Version : 3.1 18.30 +// : No Change 18.31 +// ============================================================================= 18.32 + 18.33 +`include "lm32_include.v" 18.34 + 18.35 +///////////////////////////////////////////////////// 18.36 +// Module interface 18.37 +///////////////////////////////////////////////////// 18.38 + 18.39 +module lm32_logic_op ( 18.40 + // ----- Inputs ------- 18.41 + logic_op_x, 18.42 + operand_0_x, 18.43 + operand_1_x, 18.44 + // ----- Outputs ------- 18.45 + logic_result_x 18.46 + ); 18.47 + 18.48 +///////////////////////////////////////////////////// 18.49 +// Inputs 18.50 +///////////////////////////////////////////////////// 18.51 + 18.52 +input [`LM32_LOGIC_OP_RNG] logic_op_x; 18.53 +input [`LM32_WORD_RNG] operand_0_x; 18.54 +input [`LM32_WORD_RNG] operand_1_x; 18.55 + 18.56 +///////////////////////////////////////////////////// 18.57 +// Outputs 18.58 +///////////////////////////////////////////////////// 18.59 + 18.60 +output [`LM32_WORD_RNG] logic_result_x; 18.61 +reg [`LM32_WORD_RNG] logic_result_x; 18.62 + 18.63 +///////////////////////////////////////////////////// 18.64 +// Internal nets and registers 18.65 +///////////////////////////////////////////////////// 18.66 + 18.67 +integer logic_idx; 18.68 + 18.69 +///////////////////////////////////////////////////// 18.70 +// Combinational Logic 18.71 +///////////////////////////////////////////////////// 18.72 + 18.73 +always @(*) 18.74 +begin 18.75 + for(logic_idx = 0; logic_idx < `LM32_WORD_WIDTH; logic_idx = logic_idx + 1) 18.76 + logic_result_x[logic_idx] = logic_op_x[{operand_1_x[logic_idx], operand_0_x[logic_idx]}]; 18.77 +end 18.78 + 18.79 +endmodule 18.80 +
19.1 diff -r 000000000000 -r cd0b58aa6f83 lm32_mc_arithmetic.v 19.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 19.3 +++ b/lm32_mc_arithmetic.v Sun Apr 04 20:40:03 2010 +0100 19.4 @@ -0,0 +1,288 @@ 19.5 +// ============================================================================= 19.6 +// COPYRIGHT NOTICE 19.7 +// Copyright 2006 (c) Lattice Semiconductor Corporation 19.8 +// ALL RIGHTS RESERVED 19.9 +// This confidential and proprietary software may be used only as authorised by 19.10 +// a licensing agreement from Lattice Semiconductor Corporation. 19.11 +// The entire notice above must be reproduced on all authorized copies and 19.12 +// copies may only be made to the extent permitted by a licensing agreement from 19.13 +// Lattice Semiconductor Corporation. 19.14 +// 19.15 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 19.16 +// 5555 NE Moore Court 408-826-6000 (other locations) 19.17 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 19.18 +// U.S.A email: techsupport@latticesemi.com 19.19 +// =============================================================================/ 19.20 +// FILE DETAILS 19.21 +// Project : LatticeMico32 19.22 +// File : lm_mc_arithmetic.v 19.23 +// Title : Multi-cycle arithmetic unit. 19.24 +// Dependencies : lm32_include.v 19.25 +// Version : 6.1.17 19.26 +// : Initial Release 19.27 +// Version : 7.0SP2, 3.0 19.28 +// : No Change 19.29 +// Version : 3.1 19.30 +// : No Change 19.31 +// ============================================================================= 19.32 + 19.33 +`include "lm32_include.v" 19.34 + 19.35 +`define LM32_MC_STATE_RNG 2:0 19.36 +`define LM32_MC_STATE_IDLE 3'b000 19.37 +`define LM32_MC_STATE_MULTIPLY 3'b001 19.38 +`define LM32_MC_STATE_MODULUS 3'b010 19.39 +`define LM32_MC_STATE_DIVIDE 3'b011 19.40 +`define LM32_MC_STATE_SHIFT_LEFT 3'b100 19.41 +`define LM32_MC_STATE_SHIFT_RIGHT 3'b101 19.42 + 19.43 +///////////////////////////////////////////////////// 19.44 +// Module interface 19.45 +///////////////////////////////////////////////////// 19.46 + 19.47 +module lm32_mc_arithmetic ( 19.48 + // ----- Inputs ----- 19.49 + clk_i, 19.50 + rst_i, 19.51 + stall_d, 19.52 + kill_x, 19.53 +`ifdef CFG_MC_DIVIDE_ENABLED 19.54 + divide_d, 19.55 + modulus_d, 19.56 +`endif 19.57 +`ifdef CFG_MC_MULTIPLY_ENABLED 19.58 + multiply_d, 19.59 +`endif 19.60 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED 19.61 + shift_left_d, 19.62 + shift_right_d, 19.63 + sign_extend_d, 19.64 +`endif 19.65 + operand_0_d, 19.66 + operand_1_d, 19.67 + // ----- Ouputs ----- 19.68 + result_x, 19.69 +`ifdef CFG_MC_DIVIDE_ENABLED 19.70 + divide_by_zero_x, 19.71 +`endif 19.72 + stall_request_x 19.73 + ); 19.74 + 19.75 +///////////////////////////////////////////////////// 19.76 +// Inputs 19.77 +///////////////////////////////////////////////////// 19.78 + 19.79 +input clk_i; // Clock 19.80 +input rst_i; // Reset 19.81 +input stall_d; // Stall instruction in D stage 19.82 +input kill_x; // Kill instruction in X stage 19.83 +`ifdef CFG_MC_DIVIDE_ENABLED 19.84 +input divide_d; // Perform divide 19.85 +input modulus_d; // Perform modulus 19.86 +`endif 19.87 +`ifdef CFG_MC_MULTIPLY_ENABLED 19.88 +input multiply_d; // Perform multiply 19.89 +`endif 19.90 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED 19.91 +input shift_left_d; // Perform left shift 19.92 +input shift_right_d; // Perform right shift 19.93 +input sign_extend_d; // Whether to sign-extend (arithmetic) or zero-extend (logical) 19.94 +`endif 19.95 +input [`LM32_WORD_RNG] operand_0_d; 19.96 +input [`LM32_WORD_RNG] operand_1_d; 19.97 + 19.98 +///////////////////////////////////////////////////// 19.99 +// Outputs 19.100 +///////////////////////////////////////////////////// 19.101 + 19.102 +output [`LM32_WORD_RNG] result_x; // Result of operation 19.103 +reg [`LM32_WORD_RNG] result_x; 19.104 +`ifdef CFG_MC_DIVIDE_ENABLED 19.105 +output divide_by_zero_x; // A divide by zero was attempted 19.106 +reg divide_by_zero_x; 19.107 +`endif 19.108 +output stall_request_x; // Request to stall pipeline from X stage back 19.109 +wire stall_request_x; 19.110 + 19.111 +///////////////////////////////////////////////////// 19.112 +// Internal nets and registers 19.113 +///////////////////////////////////////////////////// 19.114 + 19.115 +reg [`LM32_WORD_RNG] p; // Temporary registers 19.116 +reg [`LM32_WORD_RNG] a; 19.117 +reg [`LM32_WORD_RNG] b; 19.118 +`ifdef CFG_MC_DIVIDE_ENABLED 19.119 +wire [32:0] t; 19.120 +`endif 19.121 + 19.122 +reg [`LM32_MC_STATE_RNG] state; // Current state of FSM 19.123 +reg [5:0] cycles; // Number of cycles remaining in the operation 19.124 + 19.125 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED 19.126 +reg sign_extend_x; // Whether to sign extend of zero extend right shifts 19.127 +wire fill_value; // Value to fill with for right barrel-shifts 19.128 +`endif 19.129 + 19.130 +///////////////////////////////////////////////////// 19.131 +// Combinational logic 19.132 +///////////////////////////////////////////////////// 19.133 + 19.134 +// Stall pipeline while any operation is being performed 19.135 +assign stall_request_x = state != `LM32_MC_STATE_IDLE; 19.136 + 19.137 +`ifdef CFG_MC_DIVIDE_ENABLED 19.138 +// Subtraction 19.139 +assign t = {p[`LM32_WORD_WIDTH-2:0], a[`LM32_WORD_WIDTH-1]} - b; 19.140 +`endif 19.141 + 19.142 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED 19.143 +// Determine fill value for right shift - Sign bit for arithmetic shift, or zero for logical shift 19.144 +assign fill_value = (sign_extend_x == `TRUE) & b[`LM32_WORD_WIDTH-1]; 19.145 +`endif 19.146 + 19.147 +///////////////////////////////////////////////////// 19.148 +// Sequential logic 19.149 +///////////////////////////////////////////////////// 19.150 + 19.151 +// Perform right shift 19.152 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 19.153 +begin 19.154 + if (rst_i == `TRUE) 19.155 + begin 19.156 + cycles <= {6{1'b0}}; 19.157 + p <= {`LM32_WORD_WIDTH{1'b0}}; 19.158 + a <= {`LM32_WORD_WIDTH{1'b0}}; 19.159 + b <= {`LM32_WORD_WIDTH{1'b0}}; 19.160 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED 19.161 + sign_extend_x <= 1'b0; 19.162 +`endif 19.163 +`ifdef CFG_MC_DIVIDE_ENABLED 19.164 + divide_by_zero_x <= `FALSE; 19.165 +`endif 19.166 + result_x <= {`LM32_WORD_WIDTH{1'b0}}; 19.167 + state <= `LM32_MC_STATE_IDLE; 19.168 + end 19.169 + else 19.170 + begin 19.171 +`ifdef CFG_MC_DIVIDE_ENABLED 19.172 + divide_by_zero_x <= `FALSE; 19.173 +`endif 19.174 + case (state) 19.175 + `LM32_MC_STATE_IDLE: 19.176 + begin 19.177 + if (stall_d == `FALSE) 19.178 + begin 19.179 + cycles <= `LM32_WORD_WIDTH; 19.180 + p <= 32'b0; 19.181 + a <= operand_0_d; 19.182 + b <= operand_1_d; 19.183 +`ifdef CFG_MC_DIVIDE_ENABLED 19.184 + if (divide_d == `TRUE) 19.185 + state <= `LM32_MC_STATE_DIVIDE; 19.186 + if (modulus_d == `TRUE) 19.187 + state <= `LM32_MC_STATE_MODULUS; 19.188 +`endif 19.189 +`ifdef CFG_MC_MULTIPLY_ENABLED 19.190 + if (multiply_d == `TRUE) 19.191 + state <= `LM32_MC_STATE_MULTIPLY; 19.192 +`endif 19.193 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED 19.194 + if (shift_left_d == `TRUE) 19.195 + begin 19.196 + state <= `LM32_MC_STATE_SHIFT_LEFT; 19.197 + sign_extend_x <= sign_extend_d; 19.198 + cycles <= operand_1_d[4:0]; 19.199 + a <= operand_0_d; 19.200 + b <= operand_0_d; 19.201 + end 19.202 + if (shift_right_d == `TRUE) 19.203 + begin 19.204 + state <= `LM32_MC_STATE_SHIFT_RIGHT; 19.205 + sign_extend_x <= sign_extend_d; 19.206 + cycles <= operand_1_d[4:0]; 19.207 + a <= operand_0_d; 19.208 + b <= operand_0_d; 19.209 + end 19.210 +`endif 19.211 + end 19.212 + end 19.213 +`ifdef CFG_MC_DIVIDE_ENABLED 19.214 + `LM32_MC_STATE_DIVIDE: 19.215 + begin 19.216 + if (t[32] == 1'b0) 19.217 + begin 19.218 + p <= t[31:0]; 19.219 + a <= {a[`LM32_WORD_WIDTH-2:0], 1'b1}; 19.220 + end 19.221 + else 19.222 + begin 19.223 + p <= {p[`LM32_WORD_WIDTH-2:0], a[`LM32_WORD_WIDTH-1]}; 19.224 + a <= {a[`LM32_WORD_WIDTH-2:0], 1'b0}; 19.225 + end 19.226 + result_x <= a; 19.227 + if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE)) 19.228 + begin 19.229 + // Check for divide by zero 19.230 + divide_by_zero_x <= b == {`LM32_WORD_WIDTH{1'b0}}; 19.231 + state <= `LM32_MC_STATE_IDLE; 19.232 + end 19.233 + cycles <= cycles - 1'b1; 19.234 + end 19.235 + `LM32_MC_STATE_MODULUS: 19.236 + begin 19.237 + if (t[32] == 1'b0) 19.238 + begin 19.239 + p <= t[31:0]; 19.240 + a <= {a[`LM32_WORD_WIDTH-2:0], 1'b1}; 19.241 + end 19.242 + else 19.243 + begin 19.244 + p <= {p[`LM32_WORD_WIDTH-2:0], a[`LM32_WORD_WIDTH-1]}; 19.245 + a <= {a[`LM32_WORD_WIDTH-2:0], 1'b0}; 19.246 + end 19.247 + result_x <= p; 19.248 + if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE)) 19.249 + begin 19.250 + // Check for divide by zero 19.251 + divide_by_zero_x <= b == {`LM32_WORD_WIDTH{1'b0}}; 19.252 + state <= `LM32_MC_STATE_IDLE; 19.253 + end 19.254 + cycles <= cycles - 1'b1; 19.255 + end 19.256 +`endif 19.257 +`ifdef CFG_MC_MULTIPLY_ENABLED 19.258 + `LM32_MC_STATE_MULTIPLY: 19.259 + begin 19.260 + if (b[0] == 1'b1) 19.261 + p <= p + a; 19.262 + b <= {1'b0, b[`LM32_WORD_WIDTH-1:1]}; 19.263 + a <= {a[`LM32_WORD_WIDTH-2:0], 1'b0}; 19.264 + result_x <= p; 19.265 + if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE)) 19.266 + state <= `LM32_MC_STATE_IDLE; 19.267 + cycles <= cycles - 1'b1; 19.268 + end 19.269 +`endif 19.270 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED 19.271 + `LM32_MC_STATE_SHIFT_LEFT: 19.272 + begin 19.273 + a <= {a[`LM32_WORD_WIDTH-2:0], 1'b0}; 19.274 + result_x <= a; 19.275 + if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE)) 19.276 + state <= `LM32_MC_STATE_IDLE; 19.277 + cycles <= cycles - 1'b1; 19.278 + end 19.279 + `LM32_MC_STATE_SHIFT_RIGHT: 19.280 + begin 19.281 + b <= {fill_value, b[`LM32_WORD_WIDTH-1:1]}; 19.282 + result_x <= b; 19.283 + if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE)) 19.284 + state <= `LM32_MC_STATE_IDLE; 19.285 + cycles <= cycles - 1'b1; 19.286 + end 19.287 +`endif 19.288 + endcase 19.289 + end 19.290 +end 19.291 + 19.292 +endmodule
20.1 diff -r 000000000000 -r cd0b58aa6f83 lm32_monitor.v 20.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 20.3 +++ b/lm32_monitor.v Sun Apr 04 20:40:03 2010 +0100 20.4 @@ -0,0 +1,173 @@ 20.5 +// ============================================================================= 20.6 +// COPYRIGHT NOTICE 20.7 +// Copyright 2006 (c) Lattice Semiconductor Corporation 20.8 +// ALL RIGHTS RESERVED 20.9 +// This confidential and proprietary software may be used only as authorised by 20.10 +// a licensing agreement from Lattice Semiconductor Corporation. 20.11 +// The entire notice above must be reproduced on all authorized copies and 20.12 +// copies may only be made to the extent permitted by a licensing agreement from 20.13 +// Lattice Semiconductor Corporation. 20.14 +// 20.15 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 20.16 +// 5555 NE Moore Court 408-826-6000 (other locations) 20.17 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 20.18 +// U.S.A email: techsupport@latticesemi.com 20.19 +// =============================================================================/ 20.20 +// FILE DETAILS 20.21 +// Project : LatticeMico32 20.22 +// File : lm32_monitor.v 20.23 +// Title : Debug monitor memory Wishbone interface 20.24 +// Version : 6.1.17 20.25 +// : Initial Release 20.26 +// Version : 7.0SP2, 3.0 20.27 +// : No Change 20.28 +// Version : 3.3 20.29 +// : Removed port mismatch in instantiation of module 20.30 +// : lm32_monitor_ram. 20.31 +// ============================================================================= 20.32 + 20.33 +`include "system_conf.v" 20.34 +`include "lm32_include.v" 20.35 + 20.36 +///////////////////////////////////////////////////// 20.37 +// Module interface 20.38 +///////////////////////////////////////////////////// 20.39 + 20.40 +module lm32_monitor ( 20.41 + // ----- Inputs ------- 20.42 + clk_i, 20.43 + rst_i, 20.44 + MON_ADR_I, 20.45 + MON_CYC_I, 20.46 + MON_DAT_I, 20.47 + MON_SEL_I, 20.48 + MON_STB_I, 20.49 + MON_WE_I, 20.50 + MON_LOCK_I, 20.51 + MON_CTI_I, 20.52 + MON_BTE_I, 20.53 + // ----- Outputs ------- 20.54 + MON_ACK_O, 20.55 + MON_RTY_O, 20.56 + MON_DAT_O, 20.57 + MON_ERR_O 20.58 + ); 20.59 + 20.60 +///////////////////////////////////////////////////// 20.61 +// Inputs 20.62 +///////////////////////////////////////////////////// 20.63 + 20.64 +input clk_i; // Wishbone clock 20.65 +input rst_i; // Wishbone reset 20.66 +input [`LM32_WORD_RNG] MON_ADR_I; // Wishbone address 20.67 +input MON_STB_I; // Wishbone strobe 20.68 +input MON_CYC_I; // Wishbone cycle 20.69 +input [`LM32_WORD_RNG] MON_DAT_I; // Wishbone write data 20.70 +input [`LM32_BYTE_SELECT_RNG] MON_SEL_I; // Wishbone byte select 20.71 +input MON_WE_I; // Wishbone write enable 20.72 +input MON_LOCK_I; // Wishbone locked transfer 20.73 +input [`LM32_CTYPE_RNG] MON_CTI_I; // Wishbone cycle type 20.74 +input [`LM32_BTYPE_RNG] MON_BTE_I; // Wishbone burst type 20.75 + 20.76 +///////////////////////////////////////////////////// 20.77 +// Outputs 20.78 +///////////////////////////////////////////////////// 20.79 + 20.80 +output MON_ACK_O; // Wishbone acknowlege 20.81 +reg MON_ACK_O; 20.82 +output [`LM32_WORD_RNG] MON_DAT_O; // Wishbone data output 20.83 +reg [`LM32_WORD_RNG] MON_DAT_O; 20.84 +output MON_RTY_O; // Wishbone retry 20.85 +wire MON_RTY_O; 20.86 +output MON_ERR_O; // Wishbone error 20.87 +wire MON_ERR_O; 20.88 + 20.89 +///////////////////////////////////////////////////// 20.90 +// Internal nets and registers 20.91 +///////////////////////////////////////////////////// 20.92 + 20.93 +reg [1:0] state; // Current state of FSM 20.94 +wire [`LM32_WORD_RNG] data, dataB; // Data read from RAM 20.95 +reg write_enable; // RAM write enable 20.96 +reg [`LM32_WORD_RNG] write_data; // RAM write data 20.97 + 20.98 +///////////////////////////////////////////////////// 20.99 +// Instantiations 20.100 +///////////////////////////////////////////////////// 20.101 + 20.102 +lm32_monitor_ram ram ( 20.103 + // ----- Inputs ------- 20.104 + .ClockA (clk_i), 20.105 + .ClockB (clk_i), 20.106 + .ResetA (rst_i), 20.107 + .ResetB (rst_i), 20.108 + .ClockEnA (`TRUE), 20.109 + .ClockEnB (`FALSE), 20.110 + .AddressA (MON_ADR_I[10:2]), 20.111 + .AddressB (9'b0), 20.112 + .DataInA (write_data), 20.113 + .DataInB (32'b0), 20.114 + .WrA (write_enable), 20.115 + .WrB (`FALSE), 20.116 + // ----- Outputs ------- 20.117 + .QA (data), 20.118 + .QB (dataB) 20.119 + ); 20.120 + 20.121 +///////////////////////////////////////////////////// 20.122 +// Combinational Logic 20.123 +///////////////////////////////////////////////////// 20.124 + 20.125 +assign MON_RTY_O = `FALSE; 20.126 +assign MON_ERR_O = `FALSE; 20.127 + 20.128 +///////////////////////////////////////////////////// 20.129 +// Sequential Logic 20.130 +///////////////////////////////////////////////////// 20.131 + 20.132 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 20.133 +begin 20.134 + if (rst_i == `TRUE) 20.135 + begin 20.136 + write_enable <= `FALSE; 20.137 + MON_ACK_O <= `FALSE; 20.138 + MON_DAT_O <= {`LM32_WORD_WIDTH{1'bx}}; 20.139 + state <= 2'b00; 20.140 + end 20.141 + else 20.142 + begin 20.143 + case (state) 20.144 + 2'b00: 20.145 + begin 20.146 + // Wait for a Wishbone access 20.147 + if ((MON_STB_I == `TRUE) && (MON_CYC_I == `TRUE)) 20.148 + state <= 2'b01; 20.149 + end 20.150 + 2'b01: 20.151 + begin 20.152 + // Output read data to Wishbone 20.153 + MON_ACK_O <= `TRUE; 20.154 + MON_DAT_O <= data; 20.155 + // Sub-word writes are performed using read-modify-write 20.156 + // as the Lattice EBRs don't support byte enables 20.157 + if (MON_WE_I == `TRUE) 20.158 + write_enable <= `TRUE; 20.159 + write_data[7:0] <= MON_SEL_I[0] ? MON_DAT_I[7:0] : data[7:0]; 20.160 + write_data[15:8] <= MON_SEL_I[1] ? MON_DAT_I[15:8] : data[15:8]; 20.161 + write_data[23:16] <= MON_SEL_I[2] ? MON_DAT_I[23:16] : data[23:16]; 20.162 + write_data[31:24] <= MON_SEL_I[3] ? MON_DAT_I[31:24] : data[31:24]; 20.163 + state <= 2'b10; 20.164 + end 20.165 + 2'b10: 20.166 + begin 20.167 + // Wishbone access occurs in this cycle 20.168 + write_enable <= `FALSE; 20.169 + MON_ACK_O <= `FALSE; 20.170 + MON_DAT_O <= {`LM32_WORD_WIDTH{1'bx}}; 20.171 + state <= 2'b00; 20.172 + end 20.173 + endcase 20.174 + end 20.175 +end 20.176 + 20.177 +endmodule
21.1 diff -r 000000000000 -r cd0b58aa6f83 lm32_monitor_ram.v 21.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 21.3 +++ b/lm32_monitor_ram.v Sun Apr 04 20:40:03 2010 +0100 21.4 @@ -0,0 +1,1682 @@ 21.5 +// ============================================================================= 21.6 +// COPYRIGHT NOTICE 21.7 +// Copyright 2006 (c) Lattice Semiconductor Corporation 21.8 +// ALL RIGHTS RESERVED 21.9 +// This confidential and proprietary software may be used only as authorised by 21.10 +// a licensing agreement from Lattice Semiconductor Corporation. 21.11 +// The entire notice above must be reproduced on all authorized copies and 21.12 +// copies may only be made to the extent permitted by a licensing agreement from 21.13 +// Lattice Semiconductor Corporation. 21.14 +// 21.15 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 21.16 +// 5555 NE Moore Court 408-826-6000 (other locations) 21.17 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 21.18 +// U.S.A email: techsupport@latticesemi.com 21.19 +// =============================================================================/ 21.20 +// FILE DETAILS 21.21 +// Project : LatticeMico32 21.22 +// File : lm32_monitor_ram.v 21.23 +// Title : LM32 monitor RAM, hold the load/monitor code 21.24 +// Dependencies : system_conf.v 21.25 +// Version : 6.1.17 21.26 +// : Initial Release 21.27 +// Version : version 7.0 (7.0SP2) 21.28 +// : No Change 21.29 +// : version 7.1: updated to fix r0 not being zero 21.30 +// : when hitting a breakpoint (CR 38134) 21.31 +// : version 7.2: updated to also store ip/im registers 21.32 +// : and update im register when restoring stack 21.33 +// ============================================================================= 21.34 +`include "system_conf.v" 21.35 + 21.36 +`timescale 1 ns / 1 ps 21.37 +module lm32_monitor_ram (DataInA, DataInB, AddressA, AddressB, ClockA, 21.38 + ClockB, ClockEnA, ClockEnB, WrA, WrB, ResetA, ResetB, QA, QB); 21.39 + input [31:0] DataInA; 21.40 + input [31:0] DataInB; 21.41 + input [8:0] AddressA; 21.42 + input [8:0] AddressB; 21.43 + input ClockA; 21.44 + input ClockB; 21.45 + input ClockEnA; 21.46 + input ClockEnB; 21.47 + input WrA; 21.48 + input WrB; 21.49 + input ResetA; 21.50 + input ResetB; 21.51 + output [31:0] QA; 21.52 + output [31:0] QB; 21.53 + 21.54 + parameter lat_family = `LATTICE_FAMILY; 21.55 + 21.56 + generate 21.57 + if (lat_family == "ECP3") begin 21.58 + 21.59 +/* Verilog netlist generated by SCUBA ispLever_v8.0_ALPHA (69) */ 21.60 +/* Module Version: 7.0 */ 21.61 +/* c:\ispTOOLS8_0\ispFPGA\bin\nt\scuba.exe -w -lang verilog -synth synplify -bus_exp 7 -bb -arch ep5c00 -type bram -wp 11 -rp 1010 -addr_width 9 -data_width 32 -num_rows 512 -gsr DISABLED -writemode NORMAL -resetmode SYNC -memfile ../../lm32_monitor.mem -memformat hex -n lm32_monitor_ram -e */ 21.62 +/* Tue Jun 16 18:01:57 2009 */ 21.63 + 21.64 + defparam lm32_monitor_ram_0_0_1.INITVAL_3F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.65 + defparam lm32_monitor_ram_0_0_1.INITVAL_3E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.66 + defparam lm32_monitor_ram_0_0_1.INITVAL_3D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.67 + defparam lm32_monitor_ram_0_0_1.INITVAL_3C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.68 + defparam lm32_monitor_ram_0_0_1.INITVAL_3B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.69 + defparam lm32_monitor_ram_0_0_1.INITVAL_3A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.70 + defparam lm32_monitor_ram_0_0_1.INITVAL_39 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.71 + defparam lm32_monitor_ram_0_0_1.INITVAL_38 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.72 + defparam lm32_monitor_ram_0_0_1.INITVAL_37 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.73 + defparam lm32_monitor_ram_0_0_1.INITVAL_36 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.74 + defparam lm32_monitor_ram_0_0_1.INITVAL_35 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.75 + defparam lm32_monitor_ram_0_0_1.INITVAL_34 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.76 + defparam lm32_monitor_ram_0_0_1.INITVAL_33 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.77 + defparam lm32_monitor_ram_0_0_1.INITVAL_32 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.78 + defparam lm32_monitor_ram_0_0_1.INITVAL_31 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.79 + defparam lm32_monitor_ram_0_0_1.INITVAL_30 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.80 + defparam lm32_monitor_ram_0_0_1.INITVAL_2F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.81 + defparam lm32_monitor_ram_0_0_1.INITVAL_2E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.82 + defparam lm32_monitor_ram_0_0_1.INITVAL_2D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.83 + defparam lm32_monitor_ram_0_0_1.INITVAL_2C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.84 + defparam lm32_monitor_ram_0_0_1.INITVAL_2B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.85 + defparam lm32_monitor_ram_0_0_1.INITVAL_2A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.86 + defparam lm32_monitor_ram_0_0_1.INITVAL_29 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.87 + defparam lm32_monitor_ram_0_0_1.INITVAL_28 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.88 + defparam lm32_monitor_ram_0_0_1.INITVAL_27 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.89 + defparam lm32_monitor_ram_0_0_1.INITVAL_26 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.90 + defparam lm32_monitor_ram_0_0_1.INITVAL_25 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.91 + defparam lm32_monitor_ram_0_0_1.INITVAL_24 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.92 + defparam lm32_monitor_ram_0_0_1.INITVAL_23 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.93 + defparam lm32_monitor_ram_0_0_1.INITVAL_22 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.94 + defparam lm32_monitor_ram_0_0_1.INITVAL_21 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.95 + defparam lm32_monitor_ram_0_0_1.INITVAL_20 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.96 + defparam lm32_monitor_ram_0_0_1.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.97 + defparam lm32_monitor_ram_0_0_1.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.98 + defparam lm32_monitor_ram_0_0_1.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.99 + defparam lm32_monitor_ram_0_0_1.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.100 + defparam lm32_monitor_ram_0_0_1.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.101 + defparam lm32_monitor_ram_0_0_1.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.102 + defparam lm32_monitor_ram_0_0_1.INITVAL_19 = "0x0000000000000000000000000000000000000000000000000000000000000000000000000003FF81" ; 21.103 + defparam lm32_monitor_ram_0_0_1.INITVAL_18 = "0x300003FF83300003FF85300003FF873FF4A1004F3FF8A300003FF8C300003FF8E300003FF9030000" ; 21.104 + defparam lm32_monitor_ram_0_0_1.INITVAL_17 = "0x3FF92300003FF94300003FF96300003FFC100800070003FFFB0000130001100003FF5B1001700000" ; 21.105 + defparam lm32_monitor_ram_0_0_1.INITVAL_16 = "0x068003FF70058003FF723FFFB300013FF6A00001100001FFAB00000068003FF7B058003FF7D3FFB1" ; 21.106 + defparam lm32_monitor_ram_0_0_1.INITVAL_15 = "0x3FF8D008003FFB4300000FFB61001B000361001A0002F10019000381001800038100130003310012" ; 21.107 + defparam lm32_monitor_ram_0_0_1.INITVAL_14 = "0x00033100110003310010000331000900033100080003310007010003FF89058003FF9C3FFF900800" ; 21.108 + defparam lm32_monitor_ram_0_0_1.INITVAL_13 = "0x070000FFFB30800070003FFD63FFB200800000041000A0004110006010003FF9A000000002410004" ; 21.109 + defparam lm32_monitor_ram_0_0_1.INITVAL_12 = "0x200081000C0001030014200181001C00020300240000000000000001000000000000000000010000" ; 21.110 + defparam lm32_monitor_ram_0_0_1.INITVAL_11 = "0x100010FFF310063000501004D000471006D00046100720002C100570001F10077010003FFBC00000" ; 21.111 + defparam lm32_monitor_ram_0_0_1.INITVAL_10 = "0x30000044003FC0010000100540FFFF0080010000100540FFFF008000880010004200081000C00010" ; 21.112 + defparam lm32_monitor_ram_0_0_1.INITVAL_0F = "0x30014200181001C00020300240FFDC0000000008100043FFDD100083FFDF100093FFE11000A3FFE3" ; 21.113 + defparam lm32_monitor_ram_0_0_1.INITVAL_0E = "0x1000B10008100040FFF8000000000C1000410008100083FFE7100093FFE91000A3FFEB1000B3FFED" ; 21.114 + defparam lm32_monitor_ram_0_0_1.INITVAL_0D = "0x100040FFF400000200000FFFF01000000000000210054100000FFFF01000100FF00000100FF00000" ; 21.115 + defparam lm32_monitor_ram_0_0_1.INITVAL_0C = "0x0FFFE1010001000000000007430084200002009830000300943000030090300003008C2007C10078" ; 21.116 + defparam lm32_monitor_ram_0_0_1.INITVAL_0B = "0x300702006C1006800064300602005C1005800054300502004C1004800044300402003C1003800034" ; 21.117 + defparam lm32_monitor_ram_0_0_1.INITVAL_0A = "0x300302002C1002800024300202001C1001800014300102000C100080000000074200842000020098" ; 21.118 + defparam lm32_monitor_ram_0_0_1.INITVAL_09 = "0x20000200942000020090200002008C3008010078300702006C1006800064300602005C1005800054" ; 21.119 + defparam lm32_monitor_ram_0_0_1.INITVAL_08 = "0x300502004C1004800044300402003C1003800034300302002C1002800024300202001C1001800014" ; 21.120 + defparam lm32_monitor_ram_0_0_1.INITVAL_07 = "0x300102000C10008000001F9A00E000000041007810000100881000110001100011000110001100FF" ; 21.121 + defparam lm32_monitor_ram_0_0_1.INITVAL_06 = "0x1F9A0100940080010090008001008C008001009C008001009800800300802007C00074300702006C" ; 21.122 + defparam lm32_monitor_ram_0_0_1.INITVAL_05 = "0x1006800064300602005C1005800054300502004C1004800044300402003C1003800034300302002C" ; 21.123 + defparam lm32_monitor_ram_0_0_1.INITVAL_04 = "0x1002800024300202001C1001800014300102000C100080000000000106603FFC530000007F40E000" ; 21.124 + defparam lm32_monitor_ram_0_0_1.INITVAL_03 = "0x0003E000BC1000400800200840000A000000000000046000C4100040080020084000120000000000" ; 21.125 + defparam lm32_monitor_ram_0_0_1.INITVAL_02 = "0x0004E000CC1000400800200840001A000000000000056000D4100040080020084000220000000000" ; 21.126 + defparam lm32_monitor_ram_0_0_1.INITVAL_01 = "0x00086000DC1000400800300840002A000000000000066000E4100040080020084000320000000000" ; 21.127 + defparam lm32_monitor_ram_0_0_1.INITVAL_00 = "0x00096000EC1000400800300840003A000000000000000000000000000000000000003E0000000000" ; 21.128 + defparam lm32_monitor_ram_0_0_1.CSDECODE_B = "0b000" ; 21.129 + defparam lm32_monitor_ram_0_0_1.CSDECODE_A = "0b000" ; 21.130 + defparam lm32_monitor_ram_0_0_1.WRITEMODE_B = "NORMAL" ; 21.131 + defparam lm32_monitor_ram_0_0_1.WRITEMODE_A = "NORMAL" ; 21.132 + defparam lm32_monitor_ram_0_0_1.GSR = "DISABLED" ; 21.133 + defparam lm32_monitor_ram_0_0_1.REGMODE_B = "NOREG" ; 21.134 + defparam lm32_monitor_ram_0_0_1.REGMODE_A = "NOREG" ; 21.135 + defparam lm32_monitor_ram_0_0_1.DATA_WIDTH_B = 18 ; 21.136 + defparam lm32_monitor_ram_0_0_1.DATA_WIDTH_A = 18 ; 21.137 + DP16KC lm32_monitor_ram_0_0_1 (.DIA0(DataInA[0]), .DIA1(DataInA[1]), 21.138 + .DIA2(DataInA[2]), .DIA3(DataInA[3]), .DIA4(DataInA[4]), .DIA5(DataInA[5]), 21.139 + .DIA6(DataInA[6]), .DIA7(DataInA[7]), .DIA8(DataInA[8]), .DIA9(DataInA[9]), 21.140 + .DIA10(DataInA[10]), .DIA11(DataInA[11]), .DIA12(DataInA[12]), .DIA13(DataInA[13]), 21.141 + .DIA14(DataInA[14]), .DIA15(DataInA[15]), .DIA16(DataInA[16]), .DIA17(DataInA[17]), 21.142 + .ADA0(scuba_vhi), .ADA1(scuba_vhi), .ADA2(scuba_vlo), .ADA3(scuba_vlo), 21.143 + .ADA4(AddressA[0]), .ADA5(AddressA[1]), .ADA6(AddressA[2]), .ADA7(AddressA[3]), 21.144 + .ADA8(AddressA[4]), .ADA9(AddressA[5]), .ADA10(AddressA[6]), .ADA11(AddressA[7]), 21.145 + .ADA12(AddressA[8]), .ADA13(scuba_vlo), .CEA(ClockEnA), .CLKA(ClockA), 21.146 + .OCEA(ClockEnA), .WEA(WrA), .CSA0(scuba_vlo), .CSA1(scuba_vlo), 21.147 + .CSA2(scuba_vlo), .RSTA(ResetA), .DIB0(DataInB[0]), .DIB1(DataInB[1]), 21.148 + .DIB2(DataInB[2]), .DIB3(DataInB[3]), .DIB4(DataInB[4]), .DIB5(DataInB[5]), 21.149 + .DIB6(DataInB[6]), .DIB7(DataInB[7]), .DIB8(DataInB[8]), .DIB9(DataInB[9]), 21.150 + .DIB10(DataInB[10]), .DIB11(DataInB[11]), .DIB12(DataInB[12]), .DIB13(DataInB[13]), 21.151 + .DIB14(DataInB[14]), .DIB15(DataInB[15]), .DIB16(DataInB[16]), .DIB17(DataInB[17]), 21.152 + .ADB0(scuba_vhi), .ADB1(scuba_vhi), .ADB2(scuba_vlo), .ADB3(scuba_vlo), 21.153 + .ADB4(AddressB[0]), .ADB5(AddressB[1]), .ADB6(AddressB[2]), .ADB7(AddressB[3]), 21.154 + .ADB8(AddressB[4]), .ADB9(AddressB[5]), .ADB10(AddressB[6]), .ADB11(AddressB[7]), 21.155 + .ADB12(AddressB[8]), .ADB13(scuba_vlo), .CEB(ClockEnB), .CLKB(ClockB), 21.156 + .OCEB(ClockEnB), .WEB(WrB), .CSB0(scuba_vlo), .CSB1(scuba_vlo), 21.157 + .CSB2(scuba_vlo), .RSTB(ResetB), .DOA0(QA[0]), .DOA1(QA[1]), .DOA2(QA[2]), 21.158 + .DOA3(QA[3]), .DOA4(QA[4]), .DOA5(QA[5]), .DOA6(QA[6]), .DOA7(QA[7]), 21.159 + .DOA8(QA[8]), .DOA9(QA[9]), .DOA10(QA[10]), .DOA11(QA[11]), .DOA12(QA[12]), 21.160 + .DOA13(QA[13]), .DOA14(QA[14]), .DOA15(QA[15]), .DOA16(QA[16]), 21.161 + .DOA17(QA[17]), .DOB0(QB[0]), .DOB1(QB[1]), .DOB2(QB[2]), .DOB3(QB[3]), 21.162 + .DOB4(QB[4]), .DOB5(QB[5]), .DOB6(QB[6]), .DOB7(QB[7]), .DOB8(QB[8]), 21.163 + .DOB9(QB[9]), .DOB10(QB[10]), .DOB11(QB[11]), .DOB12(QB[12]), .DOB13(QB[13]), 21.164 + .DOB14(QB[14]), .DOB15(QB[15]), .DOB16(QB[16]), .DOB17(QB[17])) 21.165 + /* synthesis MEM_LPC_FILE="lm32_monitor_ram.lpc" */ 21.166 + /* synthesis MEM_INIT_FILE="lm32_monitor.mem" */ 21.167 + /* synthesis RESETMODE="SYNC" */; 21.168 + 21.169 + VHI scuba_vhi_inst (.Z(scuba_vhi)); 21.170 + 21.171 + VLO scuba_vlo_inst (.Z(scuba_vlo)); 21.172 + 21.173 + defparam lm32_monitor_ram_0_1_0.INITVAL_3F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.174 + defparam lm32_monitor_ram_0_1_0.INITVAL_3E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.175 + defparam lm32_monitor_ram_0_1_0.INITVAL_3D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.176 + defparam lm32_monitor_ram_0_1_0.INITVAL_3C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.177 + defparam lm32_monitor_ram_0_1_0.INITVAL_3B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.178 + defparam lm32_monitor_ram_0_1_0.INITVAL_3A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.179 + defparam lm32_monitor_ram_0_1_0.INITVAL_39 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.180 + defparam lm32_monitor_ram_0_1_0.INITVAL_38 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.181 + defparam lm32_monitor_ram_0_1_0.INITVAL_37 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.182 + defparam lm32_monitor_ram_0_1_0.INITVAL_36 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.183 + defparam lm32_monitor_ram_0_1_0.INITVAL_35 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.184 + defparam lm32_monitor_ram_0_1_0.INITVAL_34 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.185 + defparam lm32_monitor_ram_0_1_0.INITVAL_33 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.186 + defparam lm32_monitor_ram_0_1_0.INITVAL_32 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.187 + defparam lm32_monitor_ram_0_1_0.INITVAL_31 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.188 + defparam lm32_monitor_ram_0_1_0.INITVAL_30 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.189 + defparam lm32_monitor_ram_0_1_0.INITVAL_2F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.190 + defparam lm32_monitor_ram_0_1_0.INITVAL_2E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.191 + defparam lm32_monitor_ram_0_1_0.INITVAL_2D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.192 + defparam lm32_monitor_ram_0_1_0.INITVAL_2C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.193 + defparam lm32_monitor_ram_0_1_0.INITVAL_2B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.194 + defparam lm32_monitor_ram_0_1_0.INITVAL_2A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.195 + defparam lm32_monitor_ram_0_1_0.INITVAL_29 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.196 + defparam lm32_monitor_ram_0_1_0.INITVAL_28 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.197 + defparam lm32_monitor_ram_0_1_0.INITVAL_27 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.198 + defparam lm32_monitor_ram_0_1_0.INITVAL_26 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.199 + defparam lm32_monitor_ram_0_1_0.INITVAL_25 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.200 + defparam lm32_monitor_ram_0_1_0.INITVAL_24 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.201 + defparam lm32_monitor_ram_0_1_0.INITVAL_23 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.202 + defparam lm32_monitor_ram_0_1_0.INITVAL_22 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.203 + defparam lm32_monitor_ram_0_1_0.INITVAL_21 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.204 + defparam lm32_monitor_ram_0_1_0.INITVAL_20 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.205 + defparam lm32_monitor_ram_0_1_0.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.206 + defparam lm32_monitor_ram_0_1_0.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.207 + defparam lm32_monitor_ram_0_1_0.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.208 + defparam lm32_monitor_ram_0_1_0.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.209 + defparam lm32_monitor_ram_0_1_0.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.210 + defparam lm32_monitor_ram_0_1_0.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ; 21.211 + defparam lm32_monitor_ram_0_1_0.INITVAL_19 = "0x000000000000000000000000000000000000000000000000000000000000000000000000000038FF" ; 21.212 + defparam lm32_monitor_ram_0_1_0.INITVAL_18 = "0x034D2038FF034C2038FF0349A038FF03EFF00D00038FF034CA038FF03492038FF0348A038FF03482" ; 21.213 + defparam lm32_monitor_ram_0_1_0.INITVAL_17 = "0x038FF0344A038FF03442038FF0343A038FF02E7002430038FF00D6300D5A00C5803EFF0136300D03" ; 21.214 + defparam lm32_monitor_ram_0_1_0.INITVAL_16 = "0x02E0803EFF02E0803EFF038FF00D5A03EFF00D63010580136300D0302E0803EFF02E0803EFF038FF" ; 21.215 + defparam lm32_monitor_ram_0_1_0.INITVAL_15 = "0x03EFF02E88038FF034DA0170801F100110801F100110801F100110801F100110801F100110801F10" ; 21.216 + defparam lm32_monitor_ram_0_1_0.INITVAL_14 = "0x0110801F100110801F100110801F100110801F100110801F0802E0803EFF02E0803EFF038FF02E70" ; 21.217 + defparam lm32_monitor_ram_0_1_0.INITVAL_13 = "0x024500110C0287302430038FF03EFF02E700110801F100110801F0802E0803EFF030E800DE700AE7" ; 21.218 + defparam lm32_monitor_ram_0_1_0.INITVAL_12 = "0x00AE400AE400AE400AE300AE300AE300AE300AE200D0000D0000D000342000D0000D0000D0003418" ; 21.219 + defparam lm32_monitor_ram_0_1_0.INITVAL_11 = "0x00D000170801F100110801F100110801F100110801F100110801F100110801F0802E0803EFF00E84" ; 21.220 + defparam lm32_monitor_ram_0_1_0.INITVAL_10 = "0x00E7B01E0401E030347000D0001708024700347000D00017080247002E08016E7016E4016E4016E4" ; 21.221 + defparam lm32_monitor_ram_0_1_0.INITVAL_0F = "0x016E3016E3016E3016E3016E200DE7030E800DE700AE703EFF010E003EFF010E003EFF010E003EFF" ; 21.222 + defparam lm32_monitor_ram_0_1_0.INITVAL_0E = "0x010E0016E0016E700DE7030E800DE700AE700AE000CE003EFF00CE003EFF00CE003EFF00CE003EFF" ; 21.223 + defparam lm32_monitor_ram_0_1_0.INITVAL_0D = "0x016E700DE7030E8034700171002470030E80110801F0803470017100247000808030E80081003478" ; 21.224 + defparam lm32_monitor_ram_0_1_0.INITVAL_0C = "0x011080081002478030F800AE700AE70340F00AE70340700AE70344F00AE70343F00AE700AE700AE7" ; 21.225 + defparam lm32_monitor_ram_0_1_0.INITVAL_0B = "0x00AE600AE600AE600AE600AE500AE500AE500AE500AE400AE400AE400AE400AE300AE300AE300AE3" ; 21.226 + defparam lm32_monitor_ram_0_1_0.INITVAL_0A = "0x00AE200AE200AE200AE200AE100AE100AE100AE100AE000AE000AE0030F000AE700AE70340F00AE7" ; 21.227 + defparam lm32_monitor_ram_0_1_0.INITVAL_09 = "0x0340700AE70344F00AE70343F00AE700AE700AE700AE600AE600AE600AE600AE500AE500AE500AE5" ; 21.228 + defparam lm32_monitor_ram_0_1_0.INITVAL_08 = "0x00AE400AE400AE400AE400AE300AE300AE300AE300AE200AE200AE200AE200AE100AE100AE100AE1" ; 21.229 + defparam lm32_monitor_ram_0_1_0.INITVAL_07 = "0x00AE000AE000AE0030E800DEF02EE8016E8016E800AE8016E8000080000800008000080000800808" ; 21.230 + defparam lm32_monitor_ram_0_1_0.INITVAL_06 = "0x00DE8016E802400016E802448016E802438016E802410016E802408016EF016EF016EF016EE016EE" ; 21.231 + defparam lm32_monitor_ram_0_1_0.INITVAL_05 = "0x016EE016EE016ED016ED016ED016ED016EC016EC016EC016EC016EB016EB016EB016EB016EA016EA" ; 21.232 + defparam lm32_monitor_ram_0_1_0.INITVAL_04 = "0x016EA016EA016E9016E9016E9016E9016E8016E8016E802600016E800DEF038FF00D0700DE702EE8" ; 21.233 + defparam lm32_monitor_ram_0_1_0.INITVAL_03 = "0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600" ; 21.234 + defparam lm32_monitor_ram_0_1_0.INITVAL_02 = "0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600" ; 21.235 + defparam lm32_monitor_ram_0_1_0.INITVAL_01 = "0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600" ; 21.236 + defparam lm32_monitor_ram_0_1_0.INITVAL_00 = "0x0380003E0000D0802EE0016E703E0002EE80260000D0000D0000D0000D0000D0003E000340802600" ; 21.237 + defparam lm32_monitor_ram_0_1_0.CSDECODE_B = "0b000" ; 21.238 + defparam lm32_monitor_ram_0_1_0.CSDECODE_A = "0b000" ; 21.239 + defparam lm32_monitor_ram_0_1_0.WRITEMODE_B = "NORMAL" ; 21.240 + defparam lm32_monitor_ram_0_1_0.WRITEMODE_A = "NORMAL" ; 21.241 + defparam lm32_monitor_ram_0_1_0.GSR = "DISABLED" ; 21.242 + defparam lm32_monitor_ram_0_1_0.REGMODE_B = "NOREG" ; 21.243 + defparam lm32_monitor_ram_0_1_0.REGMODE_A = "NOREG" ; 21.244 + defparam lm32_monitor_ram_0_1_0.DATA_WIDTH_B = 18 ; 21.245 + defparam lm32_monitor_ram_0_1_0.DATA_WIDTH_A = 18 ; 21.246 + DP16KC lm32_monitor_ram_0_1_0 (.DIA0(DataInA[18]), .DIA1(DataInA[19]), 21.247 + .DIA2(DataInA[20]), .DIA3(DataInA[21]), .DIA4(DataInA[22]), .DIA5(DataInA[23]), 21.248 + .DIA6(DataInA[24]), .DIA7(DataInA[25]), .DIA8(DataInA[26]), .DIA9(DataInA[27]), 21.249 + .DIA10(DataInA[28]), .DIA11(DataInA[29]), .DIA12(DataInA[30]), .DIA13(DataInA[31]), 21.250 + .DIA14(scuba_vlo), .DIA15(scuba_vlo), .DIA16(scuba_vlo), .DIA17(scuba_vlo), 21.251 + .ADA0(scuba_vhi), .ADA1(scuba_vhi), .ADA2(scuba_vlo), .ADA3(scuba_vlo), 21.252 + .ADA4(AddressA[0]), .ADA5(AddressA[1]), .ADA6(AddressA[2]), .ADA7(AddressA[3]), 21.253 + .ADA8(AddressA[4]), .ADA9(AddressA[5]), .ADA10(AddressA[6]), .ADA11(AddressA[7]), 21.254 + .ADA12(AddressA[8]), .ADA13(scuba_vlo), .CEA(ClockEnA), .CLKA(ClockA), 21.255 + .OCEA(ClockEnA), .WEA(WrA), .CSA0(scuba_vlo), .CSA1(scuba_vlo), 21.256 + .CSA2(scuba_vlo), .RSTA(ResetA), .DIB0(DataInB[18]), .DIB1(DataInB[19]), 21.257 + .DIB2(DataInB[20]), .DIB3(DataInB[21]), .DIB4(DataInB[22]), .DIB5(DataInB[23]), 21.258 + .DIB6(DataInB[24]), .DIB7(DataInB[25]), .DIB8(DataInB[26]), .DIB9(DataInB[27]), 21.259 + .DIB10(DataInB[28]), .DIB11(DataInB[29]), .DIB12(DataInB[30]), .DIB13(DataInB[31]), 21.260 + .DIB14(scuba_vlo), .DIB15(scuba_vlo), .DIB16(scuba_vlo), .DIB17(scuba_vlo), 21.261 + .ADB0(scuba_vhi), .ADB1(scuba_vhi), .ADB2(scuba_vlo), .ADB3(scuba_vlo), 21.262 + .ADB4(AddressB[0]), .ADB5(AddressB[1]), .ADB6(AddressB[2]), .ADB7(AddressB[3]), 21.263 + .ADB8(AddressB[4]), .ADB9(AddressB[5]), .ADB10(AddressB[6]), .ADB11(AddressB[7]), 21.264 + .ADB12(AddressB[8]), .ADB13(scuba_vlo), .CEB(ClockEnB), .CLKB(ClockB), 21.265 + .OCEB(ClockEnB), .WEB(WrB), .CSB0(scuba_vlo), .CSB1(scuba_vlo), 21.266 + .CSB2(scuba_vlo), .RSTB(ResetB), .DOA0(QA[18]), .DOA1(QA[19]), .DOA2(QA[20]), 21.267 + .DOA3(QA[21]), .DOA4(QA[22]), .DOA5(QA[23]), .DOA6(QA[24]), .DOA7(QA[25]), 21.268 + .DOA8(QA[26]), .DOA9(QA[27]), .DOA10(QA[28]), .DOA11(QA[29]), .DOA12(QA[30]), 21.269 + .DOA13(QA[31]), .DOA14(), .DOA15(), .DOA16(), .DOA17(), .DOB0(QB[18]), 21.270 + .DOB1(QB[19]), .DOB2(QB[20]), .DOB3(QB[21]), .DOB4(QB[22]), .DOB5(QB[23]), 21.271 + .DOB6(QB[24]), .DOB7(QB[25]), .DOB8(QB[26]), .DOB9(QB[27]), .DOB10(QB[28]), 21.272 + .DOB11(QB[29]), .DOB12(QB[30]), .DOB13(QB[31]), .DOB14(), .DOB15(), 21.273 + .DOB16(), .DOB17()) 21.274 + /* synthesis MEM_LPC_FILE="lm32_monitor_ram.lpc" */ 21.275 + /* synthesis MEM_INIT_FILE="lm32_monitor.mem" */ 21.276 + /* synthesis RESETMODE="SYNC" */; 21.277 + 21.278 + 21.279 + 21.280 + // exemplar begin 21.281 + // exemplar attribute lm32_monitor_ram_0_0_1 MEM_LPC_FILE lm32_monitor_ram.lpc 21.282 + // exemplar attribute lm32_monitor_ram_0_0_1 MEM_INIT_FILE lm32_monitor.mem 21.283 + // exemplar attribute lm32_monitor_ram_0_0_1 RESETMODE SYNC 21.284 + // exemplar attribute lm32_monitor_ram_0_1_0 MEM_LPC_FILE lm32_monitor_ram.lpc 21.285 + // exemplar attribute lm32_monitor_ram_0_1_0 MEM_INIT_FILE lm32_monitor.mem 21.286 + // exemplar attribute lm32_monitor_ram_0_1_0 RESETMODE SYNC 21.287 + // exemplar end 21.288 + 21.289 + end else if (lat_family == "EC" || lat_family == "ECP" || lat_family == "XP") begin 21.290 + 21.291 +/* Verilog netlist generated by SCUBA ispLever_v8.0_ALPHA (69) */ 21.292 +/* Module Version: 7.0 */ 21.293 +/* c:\ispTOOLS8_0\ispFPGA\bin\nt\scuba.exe -w -lang verilog -synth synplify -bus_exp 7 -bb -arch ep5g00 -type bram -wp 11 -rp 1010 -addr_width 9 -data_width 32 -num_rows 512 -gsr DISABLED -writemode NORMAL -resetmode SYNC -memfile ../../lm32_monitor.mem -memformat hex -n lm32_monitor_ram -e */ 21.294 +/* Tue Jun 16 18:01:57 2009 */ 21.295 + 21.296 + // synopsys translate_off 21.297 + defparam lm32_monitor_ram_0_0_1.INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.298 + defparam lm32_monitor_ram_0_0_1.INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.299 + defparam lm32_monitor_ram_0_0_1.INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.300 + defparam lm32_monitor_ram_0_0_1.INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.301 + defparam lm32_monitor_ram_0_0_1.INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.302 + defparam lm32_monitor_ram_0_0_1.INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.303 + defparam lm32_monitor_ram_0_0_1.INITVAL_19 = 320'h0000000000000000000000000000000000000000000000000000000000000000000000000003FF81 ; 21.304 + defparam lm32_monitor_ram_0_0_1.INITVAL_18 = 320'h300003FF83300003FF85300003FF873FF4A1004F3FF8A300003FF8C300003FF8E300003FF9030000 ; 21.305 + defparam lm32_monitor_ram_0_0_1.INITVAL_17 = 320'h3FF92300003FF94300003FF96300003FFC100800070003FFFB0000130001100003FF5B1001700000 ; 21.306 + defparam lm32_monitor_ram_0_0_1.INITVAL_16 = 320'h068003FF70058003FF723FFFB300013FF6A00001100001FFAB00000068003FF7B058003FF7D3FFB1 ; 21.307 + defparam lm32_monitor_ram_0_0_1.INITVAL_15 = 320'h3FF8D008003FFB4300000FFB61001B000361001A0002F10019000381001800038100130003310012 ; 21.308 + defparam lm32_monitor_ram_0_0_1.INITVAL_14 = 320'h00033100110003310010000331000900033100080003310007010003FF89058003FF9C3FFF900800 ; 21.309 + defparam lm32_monitor_ram_0_0_1.INITVAL_13 = 320'h070000FFFB30800070003FFD63FFB200800000041000A0004110006010003FF9A000000002410004 ; 21.310 + defparam lm32_monitor_ram_0_0_1.INITVAL_12 = 320'h200081000C0001030014200181001C00020300240000000000000001000000000000000000010000 ; 21.311 + defparam lm32_monitor_ram_0_0_1.INITVAL_11 = 320'h100010FFF310063000501004D000471006D00046100720002C100570001F10077010003FFBC00000 ; 21.312 + defparam lm32_monitor_ram_0_0_1.INITVAL_10 = 320'h30000044003FC0010000100540FFFF0080010000100540FFFF008000880010004200081000C00010 ; 21.313 + defparam lm32_monitor_ram_0_0_1.INITVAL_0F = 320'h30014200181001C00020300240FFDC0000000008100043FFDD100083FFDF100093FFE11000A3FFE3 ; 21.314 + defparam lm32_monitor_ram_0_0_1.INITVAL_0E = 320'h1000B10008100040FFF8000000000C1000410008100083FFE7100093FFE91000A3FFEB1000B3FFED ; 21.315 + defparam lm32_monitor_ram_0_0_1.INITVAL_0D = 320'h100040FFF400000200000FFFF01000000000000210054100000FFFF01000100FF00000100FF00000 ; 21.316 + defparam lm32_monitor_ram_0_0_1.INITVAL_0C = 320'h0FFFE1010001000000000007430084200002009830000300943000030090300003008C2007C10078 ; 21.317 + defparam lm32_monitor_ram_0_0_1.INITVAL_0B = 320'h300702006C1006800064300602005C1005800054300502004C1004800044300402003C1003800034 ; 21.318 + defparam lm32_monitor_ram_0_0_1.INITVAL_0A = 320'h300302002C1002800024300202001C1001800014300102000C100080000000074200842000020098 ; 21.319 + defparam lm32_monitor_ram_0_0_1.INITVAL_09 = 320'h20000200942000020090200002008C3008010078300702006C1006800064300602005C1005800054 ; 21.320 + defparam lm32_monitor_ram_0_0_1.INITVAL_08 = 320'h300502004C1004800044300402003C1003800034300302002C1002800024300202001C1001800014 ; 21.321 + defparam lm32_monitor_ram_0_0_1.INITVAL_07 = 320'h300102000C10008000001F9A00E000000041007810000100881000110001100011000110001100FF ; 21.322 + defparam lm32_monitor_ram_0_0_1.INITVAL_06 = 320'h1F9A0100940080010090008001008C008001009C008001009800800300802007C00074300702006C ; 21.323 + defparam lm32_monitor_ram_0_0_1.INITVAL_05 = 320'h1006800064300602005C1005800054300502004C1004800044300402003C1003800034300302002C ; 21.324 + defparam lm32_monitor_ram_0_0_1.INITVAL_04 = 320'h1002800024300202001C1001800014300102000C100080000000000106603FFC530000007F40E000 ; 21.325 + defparam lm32_monitor_ram_0_0_1.INITVAL_03 = 320'h0003E000BC1000400800200840000A000000000000046000C4100040080020084000120000000000 ; 21.326 + defparam lm32_monitor_ram_0_0_1.INITVAL_02 = 320'h0004E000CC1000400800200840001A000000000000056000D4100040080020084000220000000000 ; 21.327 + defparam lm32_monitor_ram_0_0_1.INITVAL_01 = 320'h00086000DC1000400800300840002A000000000000066000E4100040080020084000320000000000 ; 21.328 + defparam lm32_monitor_ram_0_0_1.INITVAL_00 = 320'h00096000EC1000400800300840003A000000000000000000000000000000000000003E0000000000 ; 21.329 + defparam lm32_monitor_ram_0_0_1.CSDECODE_B = "000" ; 21.330 + defparam lm32_monitor_ram_0_0_1.CSDECODE_A = "000" ; 21.331 + defparam lm32_monitor_ram_0_0_1.WRITEMODE_B = "NORMAL" ; 21.332 + defparam lm32_monitor_ram_0_0_1.WRITEMODE_A = "NORMAL" ; 21.333 + defparam lm32_monitor_ram_0_0_1.GSR = "DISABLED" ; 21.334 + defparam lm32_monitor_ram_0_0_1.RESETMODE = "SYNC" ; 21.335 + defparam lm32_monitor_ram_0_0_1.REGMODE_B = "NOREG" ; 21.336 + defparam lm32_monitor_ram_0_0_1.REGMODE_A = "NOREG" ; 21.337 + defparam lm32_monitor_ram_0_0_1.DATA_WIDTH_B = 18 ; 21.338 + defparam lm32_monitor_ram_0_0_1.DATA_WIDTH_A = 18 ; 21.339 + // synopsys translate_on 21.340 + DP8KA lm32_monitor_ram_0_0_1 (.CEA(ClockEnA), .CLKA(ClockA), .WEA(WrA), 21.341 + .CSA0(scuba_vlo), .CSA1(scuba_vlo), .CSA2(scuba_vlo), .RSTA(ResetA), 21.342 + .CEB(ClockEnB), .CLKB(ClockB), .WEB(WrB), .CSB0(scuba_vlo), .CSB1(scuba_vlo), 21.343 + .CSB2(scuba_vlo), .RSTB(ResetB), .DIA0(DataInA[0]), .DIA1(DataInA[1]), 21.344 + .DIA2(DataInA[2]), .DIA3(DataInA[3]), .DIA4(DataInA[4]), .DIA5(DataInA[5]), 21.345 + .DIA6(DataInA[6]), .DIA7(DataInA[7]), .DIA8(DataInA[8]), .DIA9(DataInA[9]), 21.346 + .DIA10(DataInA[10]), .DIA11(DataInA[11]), .DIA12(DataInA[12]), .DIA13(DataInA[13]), 21.347 + .DIA14(DataInA[14]), .DIA15(DataInA[15]), .DIA16(DataInA[16]), .DIA17(DataInA[17]), 21.348 + .ADA0(scuba_vhi), .ADA1(scuba_vhi), .ADA2(scuba_vlo), .ADA3(scuba_vlo), 21.349 + .ADA4(AddressA[0]), .ADA5(AddressA[1]), .ADA6(AddressA[2]), .ADA7(AddressA[3]), 21.350 + .ADA8(AddressA[4]), .ADA9(AddressA[5]), .ADA10(AddressA[6]), .ADA11(AddressA[7]), 21.351 + .ADA12(AddressA[8]), .DIB0(DataInB[0]), .DIB1(DataInB[1]), .DIB2(DataInB[2]), 21.352 + .DIB3(DataInB[3]), .DIB4(DataInB[4]), .DIB5(DataInB[5]), .DIB6(DataInB[6]), 21.353 + .DIB7(DataInB[7]), .DIB8(DataInB[8]), .DIB9(DataInB[9]), .DIB10(DataInB[10]), 21.354 + .DIB11(DataInB[11]), .DIB12(DataInB[12]), .DIB13(DataInB[13]), .DIB14(DataInB[14]), 21.355 + .DIB15(DataInB[15]), .DIB16(DataInB[16]), .DIB17(DataInB[17]), .ADB0(scuba_vhi), 21.356 + .ADB1(scuba_vhi), .ADB2(scuba_vlo), .ADB3(scuba_vlo), .ADB4(AddressB[0]), 21.357 + .ADB5(AddressB[1]), .ADB6(AddressB[2]), .ADB7(AddressB[3]), .ADB8(AddressB[4]), 21.358 + .ADB9(AddressB[5]), .ADB10(AddressB[6]), .ADB11(AddressB[7]), .ADB12(AddressB[8]), 21.359 + .DOA0(QA[0]), .DOA1(QA[1]), .DOA2(QA[2]), .DOA3(QA[3]), .DOA4(QA[4]), 21.360 + .DOA5(QA[5]), .DOA6(QA[6]), .DOA7(QA[7]), .DOA8(QA[8]), .DOA9(QA[9]), 21.361 + .DOA10(QA[10]), .DOA11(QA[11]), .DOA12(QA[12]), .DOA13(QA[13]), 21.362 + .DOA14(QA[14]), .DOA15(QA[15]), .DOA16(QA[16]), .DOA17(QA[17]), 21.363 + .DOB0(QB[0]), .DOB1(QB[1]), .DOB2(QB[2]), .DOB3(QB[3]), .DOB4(QB[4]), 21.364 + .DOB5(QB[5]), .DOB6(QB[6]), .DOB7(QB[7]), .DOB8(QB[8]), .DOB9(QB[9]), 21.365 + .DOB10(QB[10]), .DOB11(QB[11]), .DOB12(QB[12]), .DOB13(QB[13]), 21.366 + .DOB14(QB[14]), .DOB15(QB[15]), .DOB16(QB[16]), .DOB17(QB[17])) 21.367 + /* synthesis MEM_LPC_FILE="lm32_monitor_ram.lpc" */ 21.368 + /* synthesis MEM_INIT_FILE="lm32_monitor.mem" */ 21.369 + /* synthesis INITVAL_1F="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.370 + /* synthesis INITVAL_1E="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.371 + /* synthesis INITVAL_1D="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.372 + /* synthesis INITVAL_1C="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.373 + /* synthesis INITVAL_1B="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.374 + /* synthesis INITVAL_1A="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.375 + /* synthesis INITVAL_19="0x0000000000000000000000000000000000000000000000000000000000000000000000000003FF81" */ 21.376 + /* synthesis INITVAL_18="0x300003FF83300003FF85300003FF873FF4A1004F3FF8A300003FF8C300003FF8E300003FF9030000" */ 21.377 + /* synthesis INITVAL_17="0x3FF92300003FF94300003FF96300003FFC100800070003FFFB0000130001100003FF5B1001700000" */ 21.378 + /* synthesis INITVAL_16="0x068003FF70058003FF723FFFB300013FF6A00001100001FFAB00000068003FF7B058003FF7D3FFB1" */ 21.379 + /* synthesis INITVAL_15="0x3FF8D008003FFB4300000FFB61001B000361001A0002F10019000381001800038100130003310012" */ 21.380 + /* synthesis INITVAL_14="0x00033100110003310010000331000900033100080003310007010003FF89058003FF9C3FFF900800" */ 21.381 + /* synthesis INITVAL_13="0x070000FFFB30800070003FFD63FFB200800000041000A0004110006010003FF9A000000002410004" */ 21.382 + /* synthesis INITVAL_12="0x200081000C0001030014200181001C00020300240000000000000001000000000000000000010000" */ 21.383 + /* synthesis INITVAL_11="0x100010FFF310063000501004D000471006D00046100720002C100570001F10077010003FFBC00000" */ 21.384 + /* synthesis INITVAL_10="0x30000044003FC0010000100540FFFF0080010000100540FFFF008000880010004200081000C00010" */ 21.385 + /* synthesis INITVAL_0F="0x30014200181001C00020300240FFDC0000000008100043FFDD100083FFDF100093FFE11000A3FFE3" */ 21.386 + /* synthesis INITVAL_0E="0x1000B10008100040FFF8000000000C1000410008100083FFE7100093FFE91000A3FFEB1000B3FFED" */ 21.387 + /* synthesis INITVAL_0D="0x100040FFF400000200000FFFF01000000000000210054100000FFFF01000100FF00000100FF00000" */ 21.388 + /* synthesis INITVAL_0C="0x0FFFE1010001000000000007430084200002009830000300943000030090300003008C2007C10078" */ 21.389 + /* synthesis INITVAL_0B="0x300702006C1006800064300602005C1005800054300502004C1004800044300402003C1003800034" */ 21.390 + /* synthesis INITVAL_0A="0x300302002C1002800024300202001C1001800014300102000C100080000000074200842000020098" */ 21.391 + /* synthesis INITVAL_09="0x20000200942000020090200002008C3008010078300702006C1006800064300602005C1005800054" */ 21.392 + /* synthesis INITVAL_08="0x300502004C1004800044300402003C1003800034300302002C1002800024300202001C1001800014" */ 21.393 + /* synthesis INITVAL_07="0x300102000C10008000001F9A00E000000041007810000100881000110001100011000110001100FF" */ 21.394 + /* synthesis INITVAL_06="0x1F9A0100940080010090008001008C008001009C008001009800800300802007C00074300702006C" */ 21.395 + /* synthesis INITVAL_05="0x1006800064300602005C1005800054300502004C1004800044300402003C1003800034300302002C" */ 21.396 + /* synthesis INITVAL_04="0x1002800024300202001C1001800014300102000C100080000000000106603FFC530000007F40E000" */ 21.397 + /* synthesis INITVAL_03="0x0003E000BC1000400800200840000A000000000000046000C4100040080020084000120000000000" */ 21.398 + /* synthesis INITVAL_02="0x0004E000CC1000400800200840001A000000000000056000D4100040080020084000220000000000" */ 21.399 + /* synthesis INITVAL_01="0x00086000DC1000400800300840002A000000000000066000E4100040080020084000320000000000" */ 21.400 + /* synthesis INITVAL_00="0x00096000EC1000400800300840003A000000000000000000000000000000000000003E0000000000" */ 21.401 + /* synthesis CSDECODE_B="000" */ 21.402 + /* synthesis CSDECODE_A="000" */ 21.403 + /* synthesis WRITEMODE_B="NORMAL" */ 21.404 + /* synthesis WRITEMODE_A="NORMAL" */ 21.405 + /* synthesis GSR="DISABLED" */ 21.406 + /* synthesis RESETMODE="SYNC" */ 21.407 + /* synthesis REGMODE_B="NOREG" */ 21.408 + /* synthesis REGMODE_A="NOREG" */ 21.409 + /* synthesis DATA_WIDTH_B="18" */ 21.410 + /* synthesis DATA_WIDTH_A="18" */; 21.411 + 21.412 + VHI scuba_vhi_inst (.Z(scuba_vhi)); 21.413 + 21.414 + VLO scuba_vlo_inst (.Z(scuba_vlo)); 21.415 + 21.416 + // synopsys translate_off 21.417 + defparam lm32_monitor_ram_0_1_0.INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.418 + defparam lm32_monitor_ram_0_1_0.INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.419 + defparam lm32_monitor_ram_0_1_0.INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.420 + defparam lm32_monitor_ram_0_1_0.INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.421 + defparam lm32_monitor_ram_0_1_0.INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.422 + defparam lm32_monitor_ram_0_1_0.INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.423 + defparam lm32_monitor_ram_0_1_0.INITVAL_19 = 320'h000000000000000000000000000000000000000000000000000000000000000000000000000038FF ; 21.424 + defparam lm32_monitor_ram_0_1_0.INITVAL_18 = 320'h034D2038FF034C2038FF0349A038FF03EFF00D00038FF034CA038FF03492038FF0348A038FF03482 ; 21.425 + defparam lm32_monitor_ram_0_1_0.INITVAL_17 = 320'h038FF0344A038FF03442038FF0343A038FF02E7002430038FF00D6300D5A00C5803EFF0136300D03 ; 21.426 + defparam lm32_monitor_ram_0_1_0.INITVAL_16 = 320'h02E0803EFF02E0803EFF038FF00D5A03EFF00D63010580136300D0302E0803EFF02E0803EFF038FF ; 21.427 + defparam lm32_monitor_ram_0_1_0.INITVAL_15 = 320'h03EFF02E88038FF034DA0170801F100110801F100110801F100110801F100110801F100110801F10 ; 21.428 + defparam lm32_monitor_ram_0_1_0.INITVAL_14 = 320'h0110801F100110801F100110801F100110801F100110801F0802E0803EFF02E0803EFF038FF02E70 ; 21.429 + defparam lm32_monitor_ram_0_1_0.INITVAL_13 = 320'h024500110C0287302430038FF03EFF02E700110801F100110801F0802E0803EFF030E800DE700AE7 ; 21.430 + defparam lm32_monitor_ram_0_1_0.INITVAL_12 = 320'h00AE400AE400AE400AE300AE300AE300AE300AE200D0000D0000D000342000D0000D0000D0003418 ; 21.431 + defparam lm32_monitor_ram_0_1_0.INITVAL_11 = 320'h00D000170801F100110801F100110801F100110801F100110801F100110801F0802E0803EFF00E84 ; 21.432 + defparam lm32_monitor_ram_0_1_0.INITVAL_10 = 320'h00E7B01E0401E030347000D0001708024700347000D00017080247002E08016E7016E4016E4016E4 ; 21.433 + defparam lm32_monitor_ram_0_1_0.INITVAL_0F = 320'h016E3016E3016E3016E3016E200DE7030E800DE700AE703EFF010E003EFF010E003EFF010E003EFF ; 21.434 + defparam lm32_monitor_ram_0_1_0.INITVAL_0E = 320'h010E0016E0016E700DE7030E800DE700AE700AE000CE003EFF00CE003EFF00CE003EFF00CE003EFF ; 21.435 + defparam lm32_monitor_ram_0_1_0.INITVAL_0D = 320'h016E700DE7030E8034700171002470030E80110801F0803470017100247000808030E80081003478 ; 21.436 + defparam lm32_monitor_ram_0_1_0.INITVAL_0C = 320'h011080081002478030F800AE700AE70340F00AE70340700AE70344F00AE70343F00AE700AE700AE7 ; 21.437 + defparam lm32_monitor_ram_0_1_0.INITVAL_0B = 320'h00AE600AE600AE600AE600AE500AE500AE500AE500AE400AE400AE400AE400AE300AE300AE300AE3 ; 21.438 + defparam lm32_monitor_ram_0_1_0.INITVAL_0A = 320'h00AE200AE200AE200AE200AE100AE100AE100AE100AE000AE000AE0030F000AE700AE70340F00AE7 ; 21.439 + defparam lm32_monitor_ram_0_1_0.INITVAL_09 = 320'h0340700AE70344F00AE70343F00AE700AE700AE700AE600AE600AE600AE600AE500AE500AE500AE5 ; 21.440 + defparam lm32_monitor_ram_0_1_0.INITVAL_08 = 320'h00AE400AE400AE400AE400AE300AE300AE300AE300AE200AE200AE200AE200AE100AE100AE100AE1 ; 21.441 + defparam lm32_monitor_ram_0_1_0.INITVAL_07 = 320'h00AE000AE000AE0030E800DEF02EE8016E8016E800AE8016E8000080000800008000080000800808 ; 21.442 + defparam lm32_monitor_ram_0_1_0.INITVAL_06 = 320'h00DE8016E802400016E802448016E802438016E802410016E802408016EF016EF016EF016EE016EE ; 21.443 + defparam lm32_monitor_ram_0_1_0.INITVAL_05 = 320'h016EE016EE016ED016ED016ED016ED016EC016EC016EC016EC016EB016EB016EB016EB016EA016EA ; 21.444 + defparam lm32_monitor_ram_0_1_0.INITVAL_04 = 320'h016EA016EA016E9016E9016E9016E9016E8016E8016E802600016E800DEF038FF00D0700DE702EE8 ; 21.445 + defparam lm32_monitor_ram_0_1_0.INITVAL_03 = 320'h0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600 ; 21.446 + defparam lm32_monitor_ram_0_1_0.INITVAL_02 = 320'h0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600 ; 21.447 + defparam lm32_monitor_ram_0_1_0.INITVAL_01 = 320'h0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600 ; 21.448 + defparam lm32_monitor_ram_0_1_0.INITVAL_00 = 320'h0380003E0000D0802EE0016E703E0002EE80260000D0000D0000D0000D0000D0003E000340802600 ; 21.449 + defparam lm32_monitor_ram_0_1_0.CSDECODE_B = "000" ; 21.450 + defparam lm32_monitor_ram_0_1_0.CSDECODE_A = "000" ; 21.451 + defparam lm32_monitor_ram_0_1_0.WRITEMODE_B = "NORMAL" ; 21.452 + defparam lm32_monitor_ram_0_1_0.WRITEMODE_A = "NORMAL" ; 21.453 + defparam lm32_monitor_ram_0_1_0.GSR = "DISABLED" ; 21.454 + defparam lm32_monitor_ram_0_1_0.RESETMODE = "SYNC" ; 21.455 + defparam lm32_monitor_ram_0_1_0.REGMODE_B = "NOREG" ; 21.456 + defparam lm32_monitor_ram_0_1_0.REGMODE_A = "NOREG" ; 21.457 + defparam lm32_monitor_ram_0_1_0.DATA_WIDTH_B = 18 ; 21.458 + defparam lm32_monitor_ram_0_1_0.DATA_WIDTH_A = 18 ; 21.459 + // synopsys translate_on 21.460 + DP8KA lm32_monitor_ram_0_1_0 (.CEA(ClockEnA), .CLKA(ClockA), .WEA(WrA), 21.461 + .CSA0(scuba_vlo), .CSA1(scuba_vlo), .CSA2(scuba_vlo), .RSTA(ResetA), 21.462 + .CEB(ClockEnB), .CLKB(ClockB), .WEB(WrB), .CSB0(scuba_vlo), .CSB1(scuba_vlo), 21.463 + .CSB2(scuba_vlo), .RSTB(ResetB), .DIA0(DataInA[18]), .DIA1(DataInA[19]), 21.464 + .DIA2(DataInA[20]), .DIA3(DataInA[21]), .DIA4(DataInA[22]), .DIA5(DataInA[23]), 21.465 + .DIA6(DataInA[24]), .DIA7(DataInA[25]), .DIA8(DataInA[26]), .DIA9(DataInA[27]), 21.466 + .DIA10(DataInA[28]), .DIA11(DataInA[29]), .DIA12(DataInA[30]), .DIA13(DataInA[31]), 21.467 + .DIA14(scuba_vlo), .DIA15(scuba_vlo), .DIA16(scuba_vlo), .DIA17(scuba_vlo), 21.468 + .ADA0(scuba_vhi), .ADA1(scuba_vhi), .ADA2(scuba_vlo), .ADA3(scuba_vlo), 21.469 + .ADA4(AddressA[0]), .ADA5(AddressA[1]), .ADA6(AddressA[2]), .ADA7(AddressA[3]), 21.470 + .ADA8(AddressA[4]), .ADA9(AddressA[5]), .ADA10(AddressA[6]), .ADA11(AddressA[7]), 21.471 + .ADA12(AddressA[8]), .DIB0(DataInB[18]), .DIB1(DataInB[19]), .DIB2(DataInB[20]), 21.472 + .DIB3(DataInB[21]), .DIB4(DataInB[22]), .DIB5(DataInB[23]), .DIB6(DataInB[24]), 21.473 + .DIB7(DataInB[25]), .DIB8(DataInB[26]), .DIB9(DataInB[27]), .DIB10(DataInB[28]), 21.474 + .DIB11(DataInB[29]), .DIB12(DataInB[30]), .DIB13(DataInB[31]), .DIB14(scuba_vlo), 21.475 + .DIB15(scuba_vlo), .DIB16(scuba_vlo), .DIB17(scuba_vlo), .ADB0(scuba_vhi), 21.476 + .ADB1(scuba_vhi), .ADB2(scuba_vlo), .ADB3(scuba_vlo), .ADB4(AddressB[0]), 21.477 + .ADB5(AddressB[1]), .ADB6(AddressB[2]), .ADB7(AddressB[3]), .ADB8(AddressB[4]), 21.478 + .ADB9(AddressB[5]), .ADB10(AddressB[6]), .ADB11(AddressB[7]), .ADB12(AddressB[8]), 21.479 + .DOA0(QA[18]), .DOA1(QA[19]), .DOA2(QA[20]), .DOA3(QA[21]), .DOA4(QA[22]), 21.480 + .DOA5(QA[23]), .DOA6(QA[24]), .DOA7(QA[25]), .DOA8(QA[26]), .DOA9(QA[27]), 21.481 + .DOA10(QA[28]), .DOA11(QA[29]), .DOA12(QA[30]), .DOA13(QA[31]), 21.482 + .DOA14(), .DOA15(), .DOA16(), .DOA17(), .DOB0(QB[18]), .DOB1(QB[19]), 21.483 + .DOB2(QB[20]), .DOB3(QB[21]), .DOB4(QB[22]), .DOB5(QB[23]), .DOB6(QB[24]), 21.484 + .DOB7(QB[25]), .DOB8(QB[26]), .DOB9(QB[27]), .DOB10(QB[28]), .DOB11(QB[29]), 21.485 + .DOB12(QB[30]), .DOB13(QB[31]), .DOB14(), .DOB15(), .DOB16(), .DOB17()) 21.486 + /* synthesis MEM_LPC_FILE="lm32_monitor_ram.lpc" */ 21.487 + /* synthesis MEM_INIT_FILE="lm32_monitor.mem" */ 21.488 + /* synthesis INITVAL_1F="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.489 + /* synthesis INITVAL_1E="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.490 + /* synthesis INITVAL_1D="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.491 + /* synthesis INITVAL_1C="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.492 + /* synthesis INITVAL_1B="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.493 + /* synthesis INITVAL_1A="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.494 + /* synthesis INITVAL_19="0x000000000000000000000000000000000000000000000000000000000000000000000000000038FF" */ 21.495 + /* synthesis INITVAL_18="0x034D2038FF034C2038FF0349A038FF03EFF00D00038FF034CA038FF03492038FF0348A038FF03482" */ 21.496 + /* synthesis INITVAL_17="0x038FF0344A038FF03442038FF0343A038FF02E7002430038FF00D6300D5A00C5803EFF0136300D03" */ 21.497 + /* synthesis INITVAL_16="0x02E0803EFF02E0803EFF038FF00D5A03EFF00D63010580136300D0302E0803EFF02E0803EFF038FF" */ 21.498 + /* synthesis INITVAL_15="0x03EFF02E88038FF034DA0170801F100110801F100110801F100110801F100110801F100110801F10" */ 21.499 + /* synthesis INITVAL_14="0x0110801F100110801F100110801F100110801F100110801F0802E0803EFF02E0803EFF038FF02E70" */ 21.500 + /* synthesis INITVAL_13="0x024500110C0287302430038FF03EFF02E700110801F100110801F0802E0803EFF030E800DE700AE7" */ 21.501 + /* synthesis INITVAL_12="0x00AE400AE400AE400AE300AE300AE300AE300AE200D0000D0000D000342000D0000D0000D0003418" */ 21.502 + /* synthesis INITVAL_11="0x00D000170801F100110801F100110801F100110801F100110801F100110801F0802E0803EFF00E84" */ 21.503 + /* synthesis INITVAL_10="0x00E7B01E0401E030347000D0001708024700347000D00017080247002E08016E7016E4016E4016E4" */ 21.504 + /* synthesis INITVAL_0F="0x016E3016E3016E3016E3016E200DE7030E800DE700AE703EFF010E003EFF010E003EFF010E003EFF" */ 21.505 + /* synthesis INITVAL_0E="0x010E0016E0016E700DE7030E800DE700AE700AE000CE003EFF00CE003EFF00CE003EFF00CE003EFF" */ 21.506 + /* synthesis INITVAL_0D="0x016E700DE7030E8034700171002470030E80110801F0803470017100247000808030E80081003478" */ 21.507 + /* synthesis INITVAL_0C="0x011080081002478030F800AE700AE70340F00AE70340700AE70344F00AE70343F00AE700AE700AE7" */ 21.508 + /* synthesis INITVAL_0B="0x00AE600AE600AE600AE600AE500AE500AE500AE500AE400AE400AE400AE400AE300AE300AE300AE3" */ 21.509 + /* synthesis INITVAL_0A="0x00AE200AE200AE200AE200AE100AE100AE100AE100AE000AE000AE0030F000AE700AE70340F00AE7" */ 21.510 + /* synthesis INITVAL_09="0x0340700AE70344F00AE70343F00AE700AE700AE700AE600AE600AE600AE600AE500AE500AE500AE5" */ 21.511 + /* synthesis INITVAL_08="0x00AE400AE400AE400AE400AE300AE300AE300AE300AE200AE200AE200AE200AE100AE100AE100AE1" */ 21.512 + /* synthesis INITVAL_07="0x00AE000AE000AE0030E800DEF02EE8016E8016E800AE8016E8000080000800008000080000800808" */ 21.513 + /* synthesis INITVAL_06="0x00DE8016E802400016E802448016E802438016E802410016E802408016EF016EF016EF016EE016EE" */ 21.514 + /* synthesis INITVAL_05="0x016EE016EE016ED016ED016ED016ED016EC016EC016EC016EC016EB016EB016EB016EB016EA016EA" */ 21.515 + /* synthesis INITVAL_04="0x016EA016EA016E9016E9016E9016E9016E8016E8016E802600016E800DEF038FF00D0700DE702EE8" */ 21.516 + /* synthesis INITVAL_03="0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600" */ 21.517 + /* synthesis INITVAL_02="0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600" */ 21.518 + /* synthesis INITVAL_01="0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600" */ 21.519 + /* synthesis INITVAL_00="0x0380003E0000D0802EE0016E703E0002EE80260000D0000D0000D0000D0000D0003E000340802600" */ 21.520 + /* synthesis CSDECODE_B="000" */ 21.521 + /* synthesis CSDECODE_A="000" */ 21.522 + /* synthesis WRITEMODE_B="NORMAL" */ 21.523 + /* synthesis WRITEMODE_A="NORMAL" */ 21.524 + /* synthesis GSR="DISABLED" */ 21.525 + /* synthesis RESETMODE="SYNC" */ 21.526 + /* synthesis REGMODE_B="NOREG" */ 21.527 + /* synthesis REGMODE_A="NOREG" */ 21.528 + /* synthesis DATA_WIDTH_B="18" */ 21.529 + /* synthesis DATA_WIDTH_A="18" */; 21.530 + 21.531 + 21.532 + 21.533 + // exemplar begin 21.534 + // exemplar attribute lm32_monitor_ram_0_0_1 MEM_LPC_FILE lm32_monitor_ram.lpc 21.535 + // exemplar attribute lm32_monitor_ram_0_0_1 MEM_INIT_FILE lm32_monitor.mem 21.536 + // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_1F 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.537 + // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_1E 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.538 + // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_1D 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.539 + // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_1C 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.540 + // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_1B 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.541 + // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_1A 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.542 + // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_19 0x0000000000000000000000000000000000000000000000000000000000000000000000000003FF81 21.543 + // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_18 0x300003FF83300003FF85300003FF873FF4A1004F3FF8A300003FF8C300003FF8E300003FF9030000 21.544 + // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_17 0x3FF92300003FF94300003FF96300003FFC100800070003FFFB0000130001100003FF5B1001700000 21.545 + // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_16 0x068003FF70058003FF723FFFB300013FF6A00001100001FFAB00000068003FF7B058003FF7D3FFB1 21.546 + // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_15 0x3FF8D008003FFB4300000FFB61001B000361001A0002F10019000381001800038100130003310012 21.547 + // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_14 0x00033100110003310010000331000900033100080003310007010003FF89058003FF9C3FFF900800 21.548 + // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_13 0x070000FFFB30800070003FFD63FFB200800000041000A0004110006010003FF9A000000002410004 21.549 + // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_12 0x200081000C0001030014200181001C00020300240000000000000001000000000000000000010000 21.550 + // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_11 0x100010FFF310063000501004D000471006D00046100720002C100570001F10077010003FFBC00000 21.551 + // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_10 0x30000044003FC0010000100540FFFF0080010000100540FFFF008000880010004200081000C00010 21.552 + // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_0F 0x30014200181001C00020300240FFDC0000000008100043FFDD100083FFDF100093FFE11000A3FFE3 21.553 + // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_0E 0x1000B10008100040FFF8000000000C1000410008100083FFE7100093FFE91000A3FFEB1000B3FFED 21.554 + // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_0D 0x100040FFF400000200000FFFF01000000000000210054100000FFFF01000100FF00000100FF00000 21.555 + // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_0C 0x0FFFE1010001000000000007430084200002009830000300943000030090300003008C2007C10078 21.556 + // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_0B 0x300702006C1006800064300602005C1005800054300502004C1004800044300402003C1003800034 21.557 + // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_0A 0x300302002C1002800024300202001C1001800014300102000C100080000000074200842000020098 21.558 + // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_09 0x20000200942000020090200002008C3008010078300702006C1006800064300602005C1005800054 21.559 + // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_08 0x300502004C1004800044300402003C1003800034300302002C1002800024300202001C1001800014 21.560 + // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_07 0x300102000C10008000001F9A00E000000041007810000100881000110001100011000110001100FF 21.561 + // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_06 0x1F9A0100940080010090008001008C008001009C008001009800800300802007C00074300702006C 21.562 + // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_05 0x1006800064300602005C1005800054300502004C1004800044300402003C1003800034300302002C 21.563 + // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_04 0x1002800024300202001C1001800014300102000C100080000000000106603FFC530000007F40E000 21.564 + // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_03 0x0003E000BC1000400800200840000A000000000000046000C4100040080020084000120000000000 21.565 + // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_02 0x0004E000CC1000400800200840001A000000000000056000D4100040080020084000220000000000 21.566 + // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_01 0x00086000DC1000400800300840002A000000000000066000E4100040080020084000320000000000 21.567 + // exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_00 0x00096000EC1000400800300840003A000000000000000000000000000000000000003E0000000000 21.568 + // exemplar attribute lm32_monitor_ram_0_0_1 CSDECODE_B 000 21.569 + // exemplar attribute lm32_monitor_ram_0_0_1 CSDECODE_A 000 21.570 + // exemplar attribute lm32_monitor_ram_0_0_1 WRITEMODE_B NORMAL 21.571 + // exemplar attribute lm32_monitor_ram_0_0_1 WRITEMODE_A NORMAL 21.572 + // exemplar attribute lm32_monitor_ram_0_0_1 GSR DISABLED 21.573 + // exemplar attribute lm32_monitor_ram_0_0_1 RESETMODE SYNC 21.574 + // exemplar attribute lm32_monitor_ram_0_0_1 REGMODE_B NOREG 21.575 + // exemplar attribute lm32_monitor_ram_0_0_1 REGMODE_A NOREG 21.576 + // exemplar attribute lm32_monitor_ram_0_0_1 DATA_WIDTH_B 18 21.577 + // exemplar attribute lm32_monitor_ram_0_0_1 DATA_WIDTH_A 18 21.578 + // exemplar attribute lm32_monitor_ram_0_1_0 MEM_LPC_FILE lm32_monitor_ram.lpc 21.579 + // exemplar attribute lm32_monitor_ram_0_1_0 MEM_INIT_FILE lm32_monitor.mem 21.580 + // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_1F 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.581 + // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_1E 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.582 + // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_1D 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.583 + // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_1C 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.584 + // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_1B 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.585 + // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_1A 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.586 + // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_19 0x000000000000000000000000000000000000000000000000000000000000000000000000000038FF 21.587 + // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_18 0x034D2038FF034C2038FF0349A038FF03EFF00D00038FF034CA038FF03492038FF0348A038FF03482 21.588 + // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_17 0x038FF0344A038FF03442038FF0343A038FF02E7002430038FF00D6300D5A00C5803EFF0136300D03 21.589 + // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_16 0x02E0803EFF02E0803EFF038FF00D5A03EFF00D63010580136300D0302E0803EFF02E0803EFF038FF 21.590 + // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_15 0x03EFF02E88038FF034DA0170801F100110801F100110801F100110801F100110801F100110801F10 21.591 + // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_14 0x0110801F100110801F100110801F100110801F100110801F0802E0803EFF02E0803EFF038FF02E70 21.592 + // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_13 0x024500110C0287302430038FF03EFF02E700110801F100110801F0802E0803EFF030E800DE700AE7 21.593 + // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_12 0x00AE400AE400AE400AE300AE300AE300AE300AE200D0000D0000D000342000D0000D0000D0003418 21.594 + // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_11 0x00D000170801F100110801F100110801F100110801F100110801F100110801F0802E0803EFF00E84 21.595 + // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_10 0x00E7B01E0401E030347000D0001708024700347000D00017080247002E08016E7016E4016E4016E4 21.596 + // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_0F 0x016E3016E3016E3016E3016E200DE7030E800DE700AE703EFF010E003EFF010E003EFF010E003EFF 21.597 + // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_0E 0x010E0016E0016E700DE7030E800DE700AE700AE000CE003EFF00CE003EFF00CE003EFF00CE003EFF 21.598 + // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_0D 0x016E700DE7030E8034700171002470030E80110801F0803470017100247000808030E80081003478 21.599 + // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_0C 0x011080081002478030F800AE700AE70340F00AE70340700AE70344F00AE70343F00AE700AE700AE7 21.600 + // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_0B 0x00AE600AE600AE600AE600AE500AE500AE500AE500AE400AE400AE400AE400AE300AE300AE300AE3 21.601 + // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_0A 0x00AE200AE200AE200AE200AE100AE100AE100AE100AE000AE000AE0030F000AE700AE70340F00AE7 21.602 + // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_09 0x0340700AE70344F00AE70343F00AE700AE700AE700AE600AE600AE600AE600AE500AE500AE500AE5 21.603 + // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_08 0x00AE400AE400AE400AE400AE300AE300AE300AE300AE200AE200AE200AE200AE100AE100AE100AE1 21.604 + // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_07 0x00AE000AE000AE0030E800DEF02EE8016E8016E800AE8016E8000080000800008000080000800808 21.605 + // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_06 0x00DE8016E802400016E802448016E802438016E802410016E802408016EF016EF016EF016EE016EE 21.606 + // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_05 0x016EE016EE016ED016ED016ED016ED016EC016EC016EC016EC016EB016EB016EB016EB016EA016EA 21.607 + // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_04 0x016EA016EA016E9016E9016E9016E9016E8016E8016E802600016E800DEF038FF00D0700DE702EE8 21.608 + // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_03 0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600 21.609 + // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_02 0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600 21.610 + // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_01 0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600 21.611 + // exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_00 0x0380003E0000D0802EE0016E703E0002EE80260000D0000D0000D0000D0000D0003E000340802600 21.612 + // exemplar attribute lm32_monitor_ram_0_1_0 CSDECODE_B 000 21.613 + // exemplar attribute lm32_monitor_ram_0_1_0 CSDECODE_A 000 21.614 + // exemplar attribute lm32_monitor_ram_0_1_0 WRITEMODE_B NORMAL 21.615 + // exemplar attribute lm32_monitor_ram_0_1_0 WRITEMODE_A NORMAL 21.616 + // exemplar attribute lm32_monitor_ram_0_1_0 GSR DISABLED 21.617 + // exemplar attribute lm32_monitor_ram_0_1_0 RESETMODE SYNC 21.618 + // exemplar attribute lm32_monitor_ram_0_1_0 REGMODE_B NOREG 21.619 + // exemplar attribute lm32_monitor_ram_0_1_0 REGMODE_A NOREG 21.620 + // exemplar attribute lm32_monitor_ram_0_1_0 DATA_WIDTH_B 18 21.621 + // exemplar attribute lm32_monitor_ram_0_1_0 DATA_WIDTH_A 18 21.622 + // exemplar end 21.623 + 21.624 + end else if (lat_family == "ECP2" || lat_family == "ECP2M" || lat_family == "XP2") begin 21.625 + 21.626 +/* Verilog netlist generated by SCUBA ispLever_v8.0_ALPHA (69) */ 21.627 +/* Module Version: 7.0 */ 21.628 +/* c:\ispTOOLS8_0\ispFPGA\bin\nt\scuba.exe -w -lang verilog -synth synplify -bus_exp 7 -bb -arch ep5a00 -type bram -wp 11 -rp 1010 -addr_width 9 -data_width 32 -num_rows 512 -gsr DISABLED -writemode NORMAL -resetmode SYNC -memfile ../../lm32_monitor.mem -memformat hex -e -n lm32_monitor_ram_ecp2 */ 21.629 +/* Tue Jun 16 18:01:57 2009 */ 21.630 + 21.631 + // synopsys translate_off 21.632 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.633 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.634 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.635 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.636 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.637 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.638 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.639 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.640 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.641 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.642 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.643 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.644 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.645 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.646 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.647 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.648 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.649 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.650 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.651 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.652 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.653 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.654 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.655 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.656 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.657 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.658 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.659 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.660 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.661 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.662 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.663 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.664 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.665 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.666 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.667 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.668 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.669 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.670 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_19 = 320'h0000000000000000000000000000000000000000000000000000000000000000000000000003FF81 ; 21.671 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_18 = 320'h300003FF83300003FF85300003FF873FF4A1004F3FF8A300003FF8C300003FF8E300003FF9030000 ; 21.672 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_17 = 320'h3FF92300003FF94300003FF96300003FFC100800070003FFFB0000130001100003FF5B1001700000 ; 21.673 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_16 = 320'h068003FF70058003FF723FFFB300013FF6A00001100001FFAB00000068003FF7B058003FF7D3FFB1 ; 21.674 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_15 = 320'h3FF8D008003FFB4300000FFB61001B000361001A0002F10019000381001800038100130003310012 ; 21.675 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_14 = 320'h00033100110003310010000331000900033100080003310007010003FF89058003FF9C3FFF900800 ; 21.676 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_13 = 320'h070000FFFB30800070003FFD63FFB200800000041000A0004110006010003FF9A000000002410004 ; 21.677 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_12 = 320'h200081000C0001030014200181001C00020300240000000000000001000000000000000000010000 ; 21.678 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_11 = 320'h100010FFF310063000501004D000471006D00046100720002C100570001F10077010003FFBC00000 ; 21.679 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_10 = 320'h30000044003FC0010000100540FFFF0080010000100540FFFF008000880010004200081000C00010 ; 21.680 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_0F = 320'h30014200181001C00020300240FFDC0000000008100043FFDD100083FFDF100093FFE11000A3FFE3 ; 21.681 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_0E = 320'h1000B10008100040FFF8000000000C1000410008100083FFE7100093FFE91000A3FFEB1000B3FFED ; 21.682 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_0D = 320'h100040FFF400000200000FFFF01000000000000210054100000FFFF01000100FF00000100FF00000 ; 21.683 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_0C = 320'h0FFFE1010001000000000007430084200002009830000300943000030090300003008C2007C10078 ; 21.684 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_0B = 320'h300702006C1006800064300602005C1005800054300502004C1004800044300402003C1003800034 ; 21.685 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_0A = 320'h300302002C1002800024300202001C1001800014300102000C100080000000074200842000020098 ; 21.686 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_09 = 320'h20000200942000020090200002008C3008010078300702006C1006800064300602005C1005800054 ; 21.687 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_08 = 320'h300502004C1004800044300402003C1003800034300302002C1002800024300202001C1001800014 ; 21.688 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_07 = 320'h300102000C10008000001F9A00E000000041007810000100881000110001100011000110001100FF ; 21.689 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_06 = 320'h1F9A0100940080010090008001008C008001009C008001009800800300802007C00074300702006C ; 21.690 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_05 = 320'h1006800064300602005C1005800054300502004C1004800044300402003C1003800034300302002C ; 21.691 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_04 = 320'h1002800024300202001C1001800014300102000C100080000000000106603FFC530000007F40E000 ; 21.692 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_03 = 320'h0003E000BC1000400800200840000A000000000000046000C4100040080020084000120000000000 ; 21.693 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_02 = 320'h0004E000CC1000400800200840001A000000000000056000D4100040080020084000220000000000 ; 21.694 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_01 = 320'h00086000DC1000400800300840002A000000000000066000E4100040080020084000320000000000 ; 21.695 + defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_00 = 320'h00096000EC1000400800300840003A000000000000000000000000000000000000003E0000000000 ; 21.696 + defparam lm32_monitor_ram_ecp2_0_0_1.CSDECODE_B = 3'b000 ; 21.697 + defparam lm32_monitor_ram_ecp2_0_0_1.CSDECODE_A = 3'b000 ; 21.698 + defparam lm32_monitor_ram_ecp2_0_0_1.WRITEMODE_B = "NORMAL" ; 21.699 + defparam lm32_monitor_ram_ecp2_0_0_1.WRITEMODE_A = "NORMAL" ; 21.700 + defparam lm32_monitor_ram_ecp2_0_0_1.GSR = "DISABLED" ; 21.701 + defparam lm32_monitor_ram_ecp2_0_0_1.RESETMODE = "SYNC" ; 21.702 + defparam lm32_monitor_ram_ecp2_0_0_1.REGMODE_B = "NOREG" ; 21.703 + defparam lm32_monitor_ram_ecp2_0_0_1.REGMODE_A = "NOREG" ; 21.704 + defparam lm32_monitor_ram_ecp2_0_0_1.DATA_WIDTH_B = 18 ; 21.705 + defparam lm32_monitor_ram_ecp2_0_0_1.DATA_WIDTH_A = 18 ; 21.706 + // synopsys translate_on 21.707 + DP16KB lm32_monitor_ram_ecp2_0_0_1 (.DIA0(DataInA[0]), .DIA1(DataInA[1]), 21.708 + .DIA2(DataInA[2]), .DIA3(DataInA[3]), .DIA4(DataInA[4]), .DIA5(DataInA[5]), 21.709 + .DIA6(DataInA[6]), .DIA7(DataInA[7]), .DIA8(DataInA[8]), .DIA9(DataInA[9]), 21.710 + .DIA10(DataInA[10]), .DIA11(DataInA[11]), .DIA12(DataInA[12]), .DIA13(DataInA[13]), 21.711 + .DIA14(DataInA[14]), .DIA15(DataInA[15]), .DIA16(DataInA[16]), .DIA17(DataInA[17]), 21.712 + .ADA0(scuba_vhi), .ADA1(scuba_vhi), .ADA2(scuba_vlo), .ADA3(scuba_vlo), 21.713 + .ADA4(AddressA[0]), .ADA5(AddressA[1]), .ADA6(AddressA[2]), .ADA7(AddressA[3]), 21.714 + .ADA8(AddressA[4]), .ADA9(AddressA[5]), .ADA10(AddressA[6]), .ADA11(AddressA[7]), 21.715 + .ADA12(AddressA[8]), .ADA13(scuba_vlo), .CEA(ClockEnA), .CLKA(ClockA), 21.716 + .WEA(WrA), .CSA0(scuba_vlo), .CSA1(scuba_vlo), .CSA2(scuba_vlo), 21.717 + .RSTA(ResetA), .DIB0(DataInB[0]), .DIB1(DataInB[1]), .DIB2(DataInB[2]), 21.718 + .DIB3(DataInB[3]), .DIB4(DataInB[4]), .DIB5(DataInB[5]), .DIB6(DataInB[6]), 21.719 + .DIB7(DataInB[7]), .DIB8(DataInB[8]), .DIB9(DataInB[9]), .DIB10(DataInB[10]), 21.720 + .DIB11(DataInB[11]), .DIB12(DataInB[12]), .DIB13(DataInB[13]), .DIB14(DataInB[14]), 21.721 + .DIB15(DataInB[15]), .DIB16(DataInB[16]), .DIB17(DataInB[17]), .ADB0(scuba_vhi), 21.722 + .ADB1(scuba_vhi), .ADB2(scuba_vlo), .ADB3(scuba_vlo), .ADB4(AddressB[0]), 21.723 + .ADB5(AddressB[1]), .ADB6(AddressB[2]), .ADB7(AddressB[3]), .ADB8(AddressB[4]), 21.724 + .ADB9(AddressB[5]), .ADB10(AddressB[6]), .ADB11(AddressB[7]), .ADB12(AddressB[8]), 21.725 + .ADB13(scuba_vlo), .CEB(ClockEnB), .CLKB(ClockB), .WEB(WrB), .CSB0(scuba_vlo), 21.726 + .CSB1(scuba_vlo), .CSB2(scuba_vlo), .RSTB(ResetB), .DOA0(QA[0]), 21.727 + .DOA1(QA[1]), .DOA2(QA[2]), .DOA3(QA[3]), .DOA4(QA[4]), .DOA5(QA[5]), 21.728 + .DOA6(QA[6]), .DOA7(QA[7]), .DOA8(QA[8]), .DOA9(QA[9]), .DOA10(QA[10]), 21.729 + .DOA11(QA[11]), .DOA12(QA[12]), .DOA13(QA[13]), .DOA14(QA[14]), 21.730 + .DOA15(QA[15]), .DOA16(QA[16]), .DOA17(QA[17]), .DOB0(QB[0]), .DOB1(QB[1]), 21.731 + .DOB2(QB[2]), .DOB3(QB[3]), .DOB4(QB[4]), .DOB5(QB[5]), .DOB6(QB[6]), 21.732 + .DOB7(QB[7]), .DOB8(QB[8]), .DOB9(QB[9]), .DOB10(QB[10]), .DOB11(QB[11]), 21.733 + .DOB12(QB[12]), .DOB13(QB[13]), .DOB14(QB[14]), .DOB15(QB[15]), 21.734 + .DOB16(QB[16]), .DOB17(QB[17])) 21.735 + /* synthesis MEM_LPC_FILE="lm32_monitor_ram_ecp2.lpc" */ 21.736 + /* synthesis MEM_INIT_FILE="lm32_monitor.mem" */ 21.737 + /* synthesis INITVAL_3F="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.738 + /* synthesis INITVAL_3E="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.739 + /* synthesis INITVAL_3D="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.740 + /* synthesis INITVAL_3C="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.741 + /* synthesis INITVAL_3B="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.742 + /* synthesis INITVAL_3A="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.743 + /* synthesis INITVAL_39="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.744 + /* synthesis INITVAL_38="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.745 + /* synthesis INITVAL_37="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.746 + /* synthesis INITVAL_36="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.747 + /* synthesis INITVAL_35="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.748 + /* synthesis INITVAL_34="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.749 + /* synthesis INITVAL_33="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.750 + /* synthesis INITVAL_32="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.751 + /* synthesis INITVAL_31="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.752 + /* synthesis INITVAL_30="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.753 + /* synthesis INITVAL_2F="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.754 + /* synthesis INITVAL_2E="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.755 + /* synthesis INITVAL_2D="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.756 + /* synthesis INITVAL_2C="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.757 + /* synthesis INITVAL_2B="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.758 + /* synthesis INITVAL_2A="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.759 + /* synthesis INITVAL_29="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.760 + /* synthesis INITVAL_28="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.761 + /* synthesis INITVAL_27="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.762 + /* synthesis INITVAL_26="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.763 + /* synthesis INITVAL_25="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.764 + /* synthesis INITVAL_24="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.765 + /* synthesis INITVAL_23="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.766 + /* synthesis INITVAL_22="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.767 + /* synthesis INITVAL_21="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.768 + /* synthesis INITVAL_20="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.769 + /* synthesis INITVAL_1F="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.770 + /* synthesis INITVAL_1E="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.771 + /* synthesis INITVAL_1D="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.772 + /* synthesis INITVAL_1C="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.773 + /* synthesis INITVAL_1B="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.774 + /* synthesis INITVAL_1A="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.775 + /* synthesis INITVAL_19="0x0000000000000000000000000000000000000000000000000000000000000000000000000003FF81" */ 21.776 + /* synthesis INITVAL_18="0x300003FF83300003FF85300003FF873FF4A1004F3FF8A300003FF8C300003FF8E300003FF9030000" */ 21.777 + /* synthesis INITVAL_17="0x3FF92300003FF94300003FF96300003FFC100800070003FFFB0000130001100003FF5B1001700000" */ 21.778 + /* synthesis INITVAL_16="0x068003FF70058003FF723FFFB300013FF6A00001100001FFAB00000068003FF7B058003FF7D3FFB1" */ 21.779 + /* synthesis INITVAL_15="0x3FF8D008003FFB4300000FFB61001B000361001A0002F10019000381001800038100130003310012" */ 21.780 + /* synthesis INITVAL_14="0x00033100110003310010000331000900033100080003310007010003FF89058003FF9C3FFF900800" */ 21.781 + /* synthesis INITVAL_13="0x070000FFFB30800070003FFD63FFB200800000041000A0004110006010003FF9A000000002410004" */ 21.782 + /* synthesis INITVAL_12="0x200081000C0001030014200181001C00020300240000000000000001000000000000000000010000" */ 21.783 + /* synthesis INITVAL_11="0x100010FFF310063000501004D000471006D00046100720002C100570001F10077010003FFBC00000" */ 21.784 + /* synthesis INITVAL_10="0x30000044003FC0010000100540FFFF0080010000100540FFFF008000880010004200081000C00010" */ 21.785 + /* synthesis INITVAL_0F="0x30014200181001C00020300240FFDC0000000008100043FFDD100083FFDF100093FFE11000A3FFE3" */ 21.786 + /* synthesis INITVAL_0E="0x1000B10008100040FFF8000000000C1000410008100083FFE7100093FFE91000A3FFEB1000B3FFED" */ 21.787 + /* synthesis INITVAL_0D="0x100040FFF400000200000FFFF01000000000000210054100000FFFF01000100FF00000100FF00000" */ 21.788 + /* synthesis INITVAL_0C="0x0FFFE1010001000000000007430084200002009830000300943000030090300003008C2007C10078" */ 21.789 + /* synthesis INITVAL_0B="0x300702006C1006800064300602005C1005800054300502004C1004800044300402003C1003800034" */ 21.790 + /* synthesis INITVAL_0A="0x300302002C1002800024300202001C1001800014300102000C100080000000074200842000020098" */ 21.791 + /* synthesis INITVAL_09="0x20000200942000020090200002008C3008010078300702006C1006800064300602005C1005800054" */ 21.792 + /* synthesis INITVAL_08="0x300502004C1004800044300402003C1003800034300302002C1002800024300202001C1001800014" */ 21.793 + /* synthesis INITVAL_07="0x300102000C10008000001F9A00E000000041007810000100881000110001100011000110001100FF" */ 21.794 + /* synthesis INITVAL_06="0x1F9A0100940080010090008001008C008001009C008001009800800300802007C00074300702006C" */ 21.795 + /* synthesis INITVAL_05="0x1006800064300602005C1005800054300502004C1004800044300402003C1003800034300302002C" */ 21.796 + /* synthesis INITVAL_04="0x1002800024300202001C1001800014300102000C100080000000000106603FFC530000007F40E000" */ 21.797 + /* synthesis INITVAL_03="0x0003E000BC1000400800200840000A000000000000046000C4100040080020084000120000000000" */ 21.798 + /* synthesis INITVAL_02="0x0004E000CC1000400800200840001A000000000000056000D4100040080020084000220000000000" */ 21.799 + /* synthesis INITVAL_01="0x00086000DC1000400800300840002A000000000000066000E4100040080020084000320000000000" */ 21.800 + /* synthesis INITVAL_00="0x00096000EC1000400800300840003A000000000000000000000000000000000000003E0000000000" */ 21.801 + /* synthesis CSDECODE_B="0b000" */ 21.802 + /* synthesis CSDECODE_A="0b000" */ 21.803 + /* synthesis WRITEMODE_B="NORMAL" */ 21.804 + /* synthesis WRITEMODE_A="NORMAL" */ 21.805 + /* synthesis GSR="DISABLED" */ 21.806 + /* synthesis RESETMODE="SYNC" */ 21.807 + /* synthesis REGMODE_B="NOREG" */ 21.808 + /* synthesis REGMODE_A="NOREG" */ 21.809 + /* synthesis DATA_WIDTH_B="18" */ 21.810 + /* synthesis DATA_WIDTH_A="18" */; 21.811 + 21.812 + VHI scuba_vhi_inst (.Z(scuba_vhi)); 21.813 + 21.814 + VLO scuba_vlo_inst (.Z(scuba_vlo)); 21.815 + 21.816 + // synopsys translate_off 21.817 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.818 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.819 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.820 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.821 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.822 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.823 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.824 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.825 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.826 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.827 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.828 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.829 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.830 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.831 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.832 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.833 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.834 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.835 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.836 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.837 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.838 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.839 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.840 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.841 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.842 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.843 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.844 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.845 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.846 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.847 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.848 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.849 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.850 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.851 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.852 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.853 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.854 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.855 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_19 = 320'h000000000000000000000000000000000000000000000000000000000000000000000000000038FF ; 21.856 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_18 = 320'h034D2038FF034C2038FF0349A038FF03EFF00D00038FF034CA038FF03492038FF0348A038FF03482 ; 21.857 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_17 = 320'h038FF0344A038FF03442038FF0343A038FF02E7002430038FF00D6300D5A00C5803EFF0136300D03 ; 21.858 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_16 = 320'h02E0803EFF02E0803EFF038FF00D5A03EFF00D63010580136300D0302E0803EFF02E0803EFF038FF ; 21.859 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_15 = 320'h03EFF02E88038FF034DA0170801F100110801F100110801F100110801F100110801F100110801F10 ; 21.860 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_14 = 320'h0110801F100110801F100110801F100110801F100110801F0802E0803EFF02E0803EFF038FF02E70 ; 21.861 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_13 = 320'h024500110C0287302430038FF03EFF02E700110801F100110801F0802E0803EFF030E800DE700AE7 ; 21.862 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_12 = 320'h00AE400AE400AE400AE300AE300AE300AE300AE200D0000D0000D000342000D0000D0000D0003418 ; 21.863 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_11 = 320'h00D000170801F100110801F100110801F100110801F100110801F100110801F0802E0803EFF00E84 ; 21.864 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_10 = 320'h00E7B01E0401E030347000D0001708024700347000D00017080247002E08016E7016E4016E4016E4 ; 21.865 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_0F = 320'h016E3016E3016E3016E3016E200DE7030E800DE700AE703EFF010E003EFF010E003EFF010E003EFF ; 21.866 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_0E = 320'h010E0016E0016E700DE7030E800DE700AE700AE000CE003EFF00CE003EFF00CE003EFF00CE003EFF ; 21.867 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_0D = 320'h016E700DE7030E8034700171002470030E80110801F0803470017100247000808030E80081003478 ; 21.868 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_0C = 320'h011080081002478030F800AE700AE70340F00AE70340700AE70344F00AE70343F00AE700AE700AE7 ; 21.869 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_0B = 320'h00AE600AE600AE600AE600AE500AE500AE500AE500AE400AE400AE400AE400AE300AE300AE300AE3 ; 21.870 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_0A = 320'h00AE200AE200AE200AE200AE100AE100AE100AE100AE000AE000AE0030F000AE700AE70340F00AE7 ; 21.871 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_09 = 320'h0340700AE70344F00AE70343F00AE700AE700AE700AE600AE600AE600AE600AE500AE500AE500AE5 ; 21.872 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_08 = 320'h00AE400AE400AE400AE400AE300AE300AE300AE300AE200AE200AE200AE200AE100AE100AE100AE1 ; 21.873 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_07 = 320'h00AE000AE000AE0030E800DEF02EE8016E8016E800AE8016E8000080000800008000080000800808 ; 21.874 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_06 = 320'h00DE8016E802400016E802448016E802438016E802410016E802408016EF016EF016EF016EE016EE ; 21.875 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_05 = 320'h016EE016EE016ED016ED016ED016ED016EC016EC016EC016EC016EB016EB016EB016EB016EA016EA ; 21.876 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_04 = 320'h016EA016EA016E9016E9016E9016E9016E8016E8016E802600016E800DEF038FF00D0700DE702EE8 ; 21.877 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_03 = 320'h0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600 ; 21.878 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_02 = 320'h0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600 ; 21.879 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_01 = 320'h0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600 ; 21.880 + defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_00 = 320'h0380003E0000D0802EE0016E703E0002EE80260000D0000D0000D0000D0000D0003E000340802600 ; 21.881 + defparam lm32_monitor_ram_ecp2_0_1_0.CSDECODE_B = 3'b000 ; 21.882 + defparam lm32_monitor_ram_ecp2_0_1_0.CSDECODE_A = 3'b000 ; 21.883 + defparam lm32_monitor_ram_ecp2_0_1_0.WRITEMODE_B = "NORMAL" ; 21.884 + defparam lm32_monitor_ram_ecp2_0_1_0.WRITEMODE_A = "NORMAL" ; 21.885 + defparam lm32_monitor_ram_ecp2_0_1_0.GSR = "DISABLED" ; 21.886 + defparam lm32_monitor_ram_ecp2_0_1_0.RESETMODE = "SYNC" ; 21.887 + defparam lm32_monitor_ram_ecp2_0_1_0.REGMODE_B = "NOREG" ; 21.888 + defparam lm32_monitor_ram_ecp2_0_1_0.REGMODE_A = "NOREG" ; 21.889 + defparam lm32_monitor_ram_ecp2_0_1_0.DATA_WIDTH_B = 18 ; 21.890 + defparam lm32_monitor_ram_ecp2_0_1_0.DATA_WIDTH_A = 18 ; 21.891 + // synopsys translate_on 21.892 + DP16KB lm32_monitor_ram_ecp2_0_1_0 (.DIA0(DataInA[18]), .DIA1(DataInA[19]), 21.893 + .DIA2(DataInA[20]), .DIA3(DataInA[21]), .DIA4(DataInA[22]), .DIA5(DataInA[23]), 21.894 + .DIA6(DataInA[24]), .DIA7(DataInA[25]), .DIA8(DataInA[26]), .DIA9(DataInA[27]), 21.895 + .DIA10(DataInA[28]), .DIA11(DataInA[29]), .DIA12(DataInA[30]), .DIA13(DataInA[31]), 21.896 + .DIA14(scuba_vlo), .DIA15(scuba_vlo), .DIA16(scuba_vlo), .DIA17(scuba_vlo), 21.897 + .ADA0(scuba_vhi), .ADA1(scuba_vhi), .ADA2(scuba_vlo), .ADA3(scuba_vlo), 21.898 + .ADA4(AddressA[0]), .ADA5(AddressA[1]), .ADA6(AddressA[2]), .ADA7(AddressA[3]), 21.899 + .ADA8(AddressA[4]), .ADA9(AddressA[5]), .ADA10(AddressA[6]), .ADA11(AddressA[7]), 21.900 + .ADA12(AddressA[8]), .ADA13(scuba_vlo), .CEA(ClockEnA), .CLKA(ClockA), 21.901 + .WEA(WrA), .CSA0(scuba_vlo), .CSA1(scuba_vlo), .CSA2(scuba_vlo), 21.902 + .RSTA(ResetA), .DIB0(DataInB[18]), .DIB1(DataInB[19]), .DIB2(DataInB[20]), 21.903 + .DIB3(DataInB[21]), .DIB4(DataInB[22]), .DIB5(DataInB[23]), .DIB6(DataInB[24]), 21.904 + .DIB7(DataInB[25]), .DIB8(DataInB[26]), .DIB9(DataInB[27]), .DIB10(DataInB[28]), 21.905 + .DIB11(DataInB[29]), .DIB12(DataInB[30]), .DIB13(DataInB[31]), .DIB14(scuba_vlo), 21.906 + .DIB15(scuba_vlo), .DIB16(scuba_vlo), .DIB17(scuba_vlo), .ADB0(scuba_vhi), 21.907 + .ADB1(scuba_vhi), .ADB2(scuba_vlo), .ADB3(scuba_vlo), .ADB4(AddressB[0]), 21.908 + .ADB5(AddressB[1]), .ADB6(AddressB[2]), .ADB7(AddressB[3]), .ADB8(AddressB[4]), 21.909 + .ADB9(AddressB[5]), .ADB10(AddressB[6]), .ADB11(AddressB[7]), .ADB12(AddressB[8]), 21.910 + .ADB13(scuba_vlo), .CEB(ClockEnB), .CLKB(ClockB), .WEB(WrB), .CSB0(scuba_vlo), 21.911 + .CSB1(scuba_vlo), .CSB2(scuba_vlo), .RSTB(ResetB), .DOA0(QA[18]), 21.912 + .DOA1(QA[19]), .DOA2(QA[20]), .DOA3(QA[21]), .DOA4(QA[22]), .DOA5(QA[23]), 21.913 + .DOA6(QA[24]), .DOA7(QA[25]), .DOA8(QA[26]), .DOA9(QA[27]), .DOA10(QA[28]), 21.914 + .DOA11(QA[29]), .DOA12(QA[30]), .DOA13(QA[31]), .DOA14(), .DOA15(), 21.915 + .DOA16(), .DOA17(), .DOB0(QB[18]), .DOB1(QB[19]), .DOB2(QB[20]), 21.916 + .DOB3(QB[21]), .DOB4(QB[22]), .DOB5(QB[23]), .DOB6(QB[24]), .DOB7(QB[25]), 21.917 + .DOB8(QB[26]), .DOB9(QB[27]), .DOB10(QB[28]), .DOB11(QB[29]), .DOB12(QB[30]), 21.918 + .DOB13(QB[31]), .DOB14(), .DOB15(), .DOB16(), .DOB17()) 21.919 + /* synthesis MEM_LPC_FILE="lm32_monitor_ram_ecp2.lpc" */ 21.920 + /* synthesis MEM_INIT_FILE="lm32_monitor.mem" */ 21.921 + /* synthesis INITVAL_3F="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.922 + /* synthesis INITVAL_3E="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.923 + /* synthesis INITVAL_3D="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.924 + /* synthesis INITVAL_3C="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.925 + /* synthesis INITVAL_3B="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.926 + /* synthesis INITVAL_3A="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.927 + /* synthesis INITVAL_39="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.928 + /* synthesis INITVAL_38="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.929 + /* synthesis INITVAL_37="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.930 + /* synthesis INITVAL_36="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.931 + /* synthesis INITVAL_35="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.932 + /* synthesis INITVAL_34="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.933 + /* synthesis INITVAL_33="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.934 + /* synthesis INITVAL_32="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.935 + /* synthesis INITVAL_31="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.936 + /* synthesis INITVAL_30="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.937 + /* synthesis INITVAL_2F="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.938 + /* synthesis INITVAL_2E="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.939 + /* synthesis INITVAL_2D="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.940 + /* synthesis INITVAL_2C="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.941 + /* synthesis INITVAL_2B="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.942 + /* synthesis INITVAL_2A="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.943 + /* synthesis INITVAL_29="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.944 + /* synthesis INITVAL_28="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.945 + /* synthesis INITVAL_27="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.946 + /* synthesis INITVAL_26="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.947 + /* synthesis INITVAL_25="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.948 + /* synthesis INITVAL_24="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.949 + /* synthesis INITVAL_23="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.950 + /* synthesis INITVAL_22="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.951 + /* synthesis INITVAL_21="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.952 + /* synthesis INITVAL_20="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.953 + /* synthesis INITVAL_1F="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.954 + /* synthesis INITVAL_1E="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.955 + /* synthesis INITVAL_1D="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.956 + /* synthesis INITVAL_1C="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.957 + /* synthesis INITVAL_1B="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.958 + /* synthesis INITVAL_1A="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.959 + /* synthesis INITVAL_19="0x000000000000000000000000000000000000000000000000000000000000000000000000000038FF" */ 21.960 + /* synthesis INITVAL_18="0x034D2038FF034C2038FF0349A038FF03EFF00D00038FF034CA038FF03492038FF0348A038FF03482" */ 21.961 + /* synthesis INITVAL_17="0x038FF0344A038FF03442038FF0343A038FF02E7002430038FF00D6300D5A00C5803EFF0136300D03" */ 21.962 + /* synthesis INITVAL_16="0x02E0803EFF02E0803EFF038FF00D5A03EFF00D63010580136300D0302E0803EFF02E0803EFF038FF" */ 21.963 + /* synthesis INITVAL_15="0x03EFF02E88038FF034DA0170801F100110801F100110801F100110801F100110801F100110801F10" */ 21.964 + /* synthesis INITVAL_14="0x0110801F100110801F100110801F100110801F100110801F0802E0803EFF02E0803EFF038FF02E70" */ 21.965 + /* synthesis INITVAL_13="0x024500110C0287302430038FF03EFF02E700110801F100110801F0802E0803EFF030E800DE700AE7" */ 21.966 + /* synthesis INITVAL_12="0x00AE400AE400AE400AE300AE300AE300AE300AE200D0000D0000D000342000D0000D0000D0003418" */ 21.967 + /* synthesis INITVAL_11="0x00D000170801F100110801F100110801F100110801F100110801F100110801F0802E0803EFF00E84" */ 21.968 + /* synthesis INITVAL_10="0x00E7B01E0401E030347000D0001708024700347000D00017080247002E08016E7016E4016E4016E4" */ 21.969 + /* synthesis INITVAL_0F="0x016E3016E3016E3016E3016E200DE7030E800DE700AE703EFF010E003EFF010E003EFF010E003EFF" */ 21.970 + /* synthesis INITVAL_0E="0x010E0016E0016E700DE7030E800DE700AE700AE000CE003EFF00CE003EFF00CE003EFF00CE003EFF" */ 21.971 + /* synthesis INITVAL_0D="0x016E700DE7030E8034700171002470030E80110801F0803470017100247000808030E80081003478" */ 21.972 + /* synthesis INITVAL_0C="0x011080081002478030F800AE700AE70340F00AE70340700AE70344F00AE70343F00AE700AE700AE7" */ 21.973 + /* synthesis INITVAL_0B="0x00AE600AE600AE600AE600AE500AE500AE500AE500AE400AE400AE400AE400AE300AE300AE300AE3" */ 21.974 + /* synthesis INITVAL_0A="0x00AE200AE200AE200AE200AE100AE100AE100AE100AE000AE000AE0030F000AE700AE70340F00AE7" */ 21.975 + /* synthesis INITVAL_09="0x0340700AE70344F00AE70343F00AE700AE700AE700AE600AE600AE600AE600AE500AE500AE500AE5" */ 21.976 + /* synthesis INITVAL_08="0x00AE400AE400AE400AE400AE300AE300AE300AE300AE200AE200AE200AE200AE100AE100AE100AE1" */ 21.977 + /* synthesis INITVAL_07="0x00AE000AE000AE0030E800DEF02EE8016E8016E800AE8016E8000080000800008000080000800808" */ 21.978 + /* synthesis INITVAL_06="0x00DE8016E802400016E802448016E802438016E802410016E802408016EF016EF016EF016EE016EE" */ 21.979 + /* synthesis INITVAL_05="0x016EE016EE016ED016ED016ED016ED016EC016EC016EC016EC016EB016EB016EB016EB016EA016EA" */ 21.980 + /* synthesis INITVAL_04="0x016EA016EA016E9016E9016E9016E9016E8016E8016E802600016E800DEF038FF00D0700DE702EE8" */ 21.981 + /* synthesis INITVAL_03="0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600" */ 21.982 + /* synthesis INITVAL_02="0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600" */ 21.983 + /* synthesis INITVAL_01="0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600" */ 21.984 + /* synthesis INITVAL_00="0x0380003E0000D0802EE0016E703E0002EE80260000D0000D0000D0000D0000D0003E000340802600" */ 21.985 + /* synthesis CSDECODE_B="0b000" */ 21.986 + /* synthesis CSDECODE_A="0b000" */ 21.987 + /* synthesis WRITEMODE_B="NORMAL" */ 21.988 + /* synthesis WRITEMODE_A="NORMAL" */ 21.989 + /* synthesis GSR="DISABLED" */ 21.990 + /* synthesis RESETMODE="SYNC" */ 21.991 + /* synthesis REGMODE_B="NOREG" */ 21.992 + /* synthesis REGMODE_A="NOREG" */ 21.993 + /* synthesis DATA_WIDTH_B="18" */ 21.994 + /* synthesis DATA_WIDTH_A="18" */; 21.995 + 21.996 + 21.997 + 21.998 + // exemplar begin 21.999 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 MEM_LPC_FILE lm32_monitor_ram_ecp2.lpc 21.1000 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 MEM_INIT_FILE lm32_monitor.mem 21.1001 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_3F 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1002 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_3E 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1003 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_3D 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1004 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_3C 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1005 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_3B 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1006 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_3A 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1007 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_39 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1008 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_38 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1009 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_37 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1010 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_36 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1011 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_35 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1012 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_34 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1013 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_33 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1014 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_32 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1015 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_31 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1016 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_30 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1017 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_2F 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1018 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_2E 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1019 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_2D 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1020 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_2C 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1021 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_2B 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1022 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_2A 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1023 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_29 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1024 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_28 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1025 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_27 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1026 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_26 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1027 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_25 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1028 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_24 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1029 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_23 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1030 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_22 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1031 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_21 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1032 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_20 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1033 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_1F 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1034 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_1E 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1035 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_1D 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1036 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_1C 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1037 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_1B 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1038 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_1A 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1039 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_19 0x0000000000000000000000000000000000000000000000000000000000000000000000000003FF81 21.1040 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_18 0x300003FF83300003FF85300003FF873FF4A1004F3FF8A300003FF8C300003FF8E300003FF9030000 21.1041 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_17 0x3FF92300003FF94300003FF96300003FFC100800070003FFFB0000130001100003FF5B1001700000 21.1042 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_16 0x068003FF70058003FF723FFFB300013FF6A00001100001FFAB00000068003FF7B058003FF7D3FFB1 21.1043 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_15 0x3FF8D008003FFB4300000FFB61001B000361001A0002F10019000381001800038100130003310012 21.1044 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_14 0x00033100110003310010000331000900033100080003310007010003FF89058003FF9C3FFF900800 21.1045 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_13 0x070000FFFB30800070003FFD63FFB200800000041000A0004110006010003FF9A000000002410004 21.1046 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_12 0x200081000C0001030014200181001C00020300240000000000000001000000000000000000010000 21.1047 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_11 0x100010FFF310063000501004D000471006D00046100720002C100570001F10077010003FFBC00000 21.1048 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_10 0x30000044003FC0010000100540FFFF0080010000100540FFFF008000880010004200081000C00010 21.1049 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_0F 0x30014200181001C00020300240FFDC0000000008100043FFDD100083FFDF100093FFE11000A3FFE3 21.1050 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_0E 0x1000B10008100040FFF8000000000C1000410008100083FFE7100093FFE91000A3FFEB1000B3FFED 21.1051 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_0D 0x100040FFF400000200000FFFF01000000000000210054100000FFFF01000100FF00000100FF00000 21.1052 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_0C 0x0FFFE1010001000000000007430084200002009830000300943000030090300003008C2007C10078 21.1053 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_0B 0x300702006C1006800064300602005C1005800054300502004C1004800044300402003C1003800034 21.1054 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_0A 0x300302002C1002800024300202001C1001800014300102000C100080000000074200842000020098 21.1055 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_09 0x20000200942000020090200002008C3008010078300702006C1006800064300602005C1005800054 21.1056 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_08 0x300502004C1004800044300402003C1003800034300302002C1002800024300202001C1001800014 21.1057 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_07 0x300102000C10008000001F9A00E000000041007810000100881000110001100011000110001100FF 21.1058 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_06 0x1F9A0100940080010090008001008C008001009C008001009800800300802007C00074300702006C 21.1059 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_05 0x1006800064300602005C1005800054300502004C1004800044300402003C1003800034300302002C 21.1060 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_04 0x1002800024300202001C1001800014300102000C100080000000000106603FFC530000007F40E000 21.1061 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_03 0x0003E000BC1000400800200840000A000000000000046000C4100040080020084000120000000000 21.1062 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_02 0x0004E000CC1000400800200840001A000000000000056000D4100040080020084000220000000000 21.1063 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_01 0x00086000DC1000400800300840002A000000000000066000E4100040080020084000320000000000 21.1064 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_00 0x00096000EC1000400800300840003A000000000000000000000000000000000000003E0000000000 21.1065 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 CSDECODE_B 0b000 21.1066 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 CSDECODE_A 0b000 21.1067 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 WRITEMODE_B NORMAL 21.1068 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 WRITEMODE_A NORMAL 21.1069 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 GSR DISABLED 21.1070 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 RESETMODE SYNC 21.1071 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 REGMODE_B NOREG 21.1072 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 REGMODE_A NOREG 21.1073 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 DATA_WIDTH_B 18 21.1074 + // exemplar attribute lm32_monitor_ram_ecp2_0_0_1 DATA_WIDTH_A 18 21.1075 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 MEM_LPC_FILE lm32_monitor_ram_ecp2.lpc 21.1076 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 MEM_INIT_FILE lm32_monitor.mem 21.1077 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_3F 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1078 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_3E 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1079 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_3D 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1080 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_3C 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1081 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_3B 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1082 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_3A 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1083 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_39 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1084 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_38 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1085 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_37 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1086 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_36 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1087 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_35 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1088 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_34 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1089 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_33 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1090 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_32 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1091 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_31 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1092 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_30 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1093 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_2F 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1094 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_2E 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1095 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_2D 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1096 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_2C 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1097 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_2B 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1098 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_2A 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1099 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_29 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1100 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_28 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1101 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_27 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1102 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_26 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1103 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_25 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1104 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_24 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1105 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_23 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1106 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_22 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1107 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_21 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1108 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_20 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1109 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_1F 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1110 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_1E 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1111 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_1D 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1112 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_1C 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1113 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_1B 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1114 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_1A 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1115 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_19 0x000000000000000000000000000000000000000000000000000000000000000000000000000038FF 21.1116 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_18 0x034D2038FF034C2038FF0349A038FF03EFF00D00038FF034CA038FF03492038FF0348A038FF03482 21.1117 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_17 0x038FF0344A038FF03442038FF0343A038FF02E7002430038FF00D6300D5A00C5803EFF0136300D03 21.1118 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_16 0x02E0803EFF02E0803EFF038FF00D5A03EFF00D63010580136300D0302E0803EFF02E0803EFF038FF 21.1119 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_15 0x03EFF02E88038FF034DA0170801F100110801F100110801F100110801F100110801F100110801F10 21.1120 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_14 0x0110801F100110801F100110801F100110801F100110801F0802E0803EFF02E0803EFF038FF02E70 21.1121 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_13 0x024500110C0287302430038FF03EFF02E700110801F100110801F0802E0803EFF030E800DE700AE7 21.1122 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_12 0x00AE400AE400AE400AE300AE300AE300AE300AE200D0000D0000D000342000D0000D0000D0003418 21.1123 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_11 0x00D000170801F100110801F100110801F100110801F100110801F100110801F0802E0803EFF00E84 21.1124 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_10 0x00E7B01E0401E030347000D0001708024700347000D00017080247002E08016E7016E4016E4016E4 21.1125 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_0F 0x016E3016E3016E3016E3016E200DE7030E800DE700AE703EFF010E003EFF010E003EFF010E003EFF 21.1126 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_0E 0x010E0016E0016E700DE7030E800DE700AE700AE000CE003EFF00CE003EFF00CE003EFF00CE003EFF 21.1127 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_0D 0x016E700DE7030E8034700171002470030E80110801F0803470017100247000808030E80081003478 21.1128 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_0C 0x011080081002478030F800AE700AE70340F00AE70340700AE70344F00AE70343F00AE700AE700AE7 21.1129 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_0B 0x00AE600AE600AE600AE600AE500AE500AE500AE500AE400AE400AE400AE400AE300AE300AE300AE3 21.1130 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_0A 0x00AE200AE200AE200AE200AE100AE100AE100AE100AE000AE000AE0030F000AE700AE70340F00AE7 21.1131 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_09 0x0340700AE70344F00AE70343F00AE700AE700AE700AE600AE600AE600AE600AE500AE500AE500AE5 21.1132 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_08 0x00AE400AE400AE400AE400AE300AE300AE300AE300AE200AE200AE200AE200AE100AE100AE100AE1 21.1133 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_07 0x00AE000AE000AE0030E800DEF02EE8016E8016E800AE8016E8000080000800008000080000800808 21.1134 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_06 0x00DE8016E802400016E802448016E802438016E802410016E802408016EF016EF016EF016EE016EE 21.1135 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_05 0x016EE016EE016ED016ED016ED016ED016EC016EC016EC016EC016EB016EB016EB016EB016EA016EA 21.1136 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_04 0x016EA016EA016E9016E9016E9016E9016E8016E8016E802600016E800DEF038FF00D0700DE702EE8 21.1137 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_03 0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600 21.1138 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_02 0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600 21.1139 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_01 0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600 21.1140 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_00 0x0380003E0000D0802EE0016E703E0002EE80260000D0000D0000D0000D0000D0003E000340802600 21.1141 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 CSDECODE_B 0b000 21.1142 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 CSDECODE_A 0b000 21.1143 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 WRITEMODE_B NORMAL 21.1144 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 WRITEMODE_A NORMAL 21.1145 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 GSR DISABLED 21.1146 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 RESETMODE SYNC 21.1147 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 REGMODE_B NOREG 21.1148 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 REGMODE_A NOREG 21.1149 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 DATA_WIDTH_B 18 21.1150 + // exemplar attribute lm32_monitor_ram_ecp2_0_1_0 DATA_WIDTH_A 18 21.1151 + // exemplar end 21.1152 + 21.1153 + end else if (lat_family == "SC" || lat_family == "SCM") begin 21.1154 + 21.1155 +/* Verilog netlist generated by SCUBA ispLever_v8.0_ALPHA (69) */ 21.1156 +/* Module Version: 7.0 */ 21.1157 +/* c:\ispTOOLS8_0\ispFPGA\bin\nt\scuba.exe -w -lang verilog -synth synplify -bus_exp 7 -bb -arch or5s00 -type bram -wp 11 -rp 1010 -addr_width 9 -data_width 32 -num_rows 512 -gsr DISABLED -sync_reset -memfile ../../lm32_monitor.mem -memformat hex -e -n sc_rom_monitor */ 21.1158 +/* Tue Jun 16 18:01:58 2009 */ 21.1159 + 21.1160 + // synopsys translate_off 21.1161 + defparam sc_rom_monitor_0_0_1.INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1162 + defparam sc_rom_monitor_0_0_1.INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1163 + defparam sc_rom_monitor_0_0_1.INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1164 + defparam sc_rom_monitor_0_0_1.INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1165 + defparam sc_rom_monitor_0_0_1.INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1166 + defparam sc_rom_monitor_0_0_1.INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1167 + defparam sc_rom_monitor_0_0_1.INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1168 + defparam sc_rom_monitor_0_0_1.INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1169 + defparam sc_rom_monitor_0_0_1.INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1170 + defparam sc_rom_monitor_0_0_1.INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1171 + defparam sc_rom_monitor_0_0_1.INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1172 + defparam sc_rom_monitor_0_0_1.INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1173 + defparam sc_rom_monitor_0_0_1.INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1174 + defparam sc_rom_monitor_0_0_1.INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1175 + defparam sc_rom_monitor_0_0_1.INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1176 + defparam sc_rom_monitor_0_0_1.INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1177 + defparam sc_rom_monitor_0_0_1.INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1178 + defparam sc_rom_monitor_0_0_1.INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1179 + defparam sc_rom_monitor_0_0_1.INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1180 + defparam sc_rom_monitor_0_0_1.INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1181 + defparam sc_rom_monitor_0_0_1.INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1182 + defparam sc_rom_monitor_0_0_1.INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1183 + defparam sc_rom_monitor_0_0_1.INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1184 + defparam sc_rom_monitor_0_0_1.INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1185 + defparam sc_rom_monitor_0_0_1.INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1186 + defparam sc_rom_monitor_0_0_1.INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1187 + defparam sc_rom_monitor_0_0_1.INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1188 + defparam sc_rom_monitor_0_0_1.INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1189 + defparam sc_rom_monitor_0_0_1.INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1190 + defparam sc_rom_monitor_0_0_1.INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1191 + defparam sc_rom_monitor_0_0_1.INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1192 + defparam sc_rom_monitor_0_0_1.INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1193 + defparam sc_rom_monitor_0_0_1.INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1194 + defparam sc_rom_monitor_0_0_1.INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1195 + defparam sc_rom_monitor_0_0_1.INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1196 + defparam sc_rom_monitor_0_0_1.INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1197 + defparam sc_rom_monitor_0_0_1.INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1198 + defparam sc_rom_monitor_0_0_1.INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1199 + defparam sc_rom_monitor_0_0_1.INITVAL_19 = 320'h0000000000000000000000000000000000000000000000000000000000000000000000000003FF81 ; 21.1200 + defparam sc_rom_monitor_0_0_1.INITVAL_18 = 320'h300003FF83300003FF85300003FF873FF4A1004F3FF8A300003FF8C300003FF8E300003FF9030000 ; 21.1201 + defparam sc_rom_monitor_0_0_1.INITVAL_17 = 320'h3FF92300003FF94300003FF96300003FFC100800070003FFFB0000130001100003FF5B1001700000 ; 21.1202 + defparam sc_rom_monitor_0_0_1.INITVAL_16 = 320'h068003FF70058003FF723FFFB300013FF6A00001100001FFAB00000068003FF7B058003FF7D3FFB1 ; 21.1203 + defparam sc_rom_monitor_0_0_1.INITVAL_15 = 320'h3FF8D008003FFB4300000FFB61001B000361001A0002F10019000381001800038100130003310012 ; 21.1204 + defparam sc_rom_monitor_0_0_1.INITVAL_14 = 320'h00033100110003310010000331000900033100080003310007010003FF89058003FF9C3FFF900800 ; 21.1205 + defparam sc_rom_monitor_0_0_1.INITVAL_13 = 320'h070000FFFB30800070003FFD63FFB200800000041000A0004110006010003FF9A000000002410004 ; 21.1206 + defparam sc_rom_monitor_0_0_1.INITVAL_12 = 320'h200081000C0001030014200181001C00020300240000000000000001000000000000000000010000 ; 21.1207 + defparam sc_rom_monitor_0_0_1.INITVAL_11 = 320'h100010FFF310063000501004D000471006D00046100720002C100570001F10077010003FFBC00000 ; 21.1208 + defparam sc_rom_monitor_0_0_1.INITVAL_10 = 320'h30000044003FC0010000100540FFFF0080010000100540FFFF008000880010004200081000C00010 ; 21.1209 + defparam sc_rom_monitor_0_0_1.INITVAL_0F = 320'h30014200181001C00020300240FFDC0000000008100043FFDD100083FFDF100093FFE11000A3FFE3 ; 21.1210 + defparam sc_rom_monitor_0_0_1.INITVAL_0E = 320'h1000B10008100040FFF8000000000C1000410008100083FFE7100093FFE91000A3FFEB1000B3FFED ; 21.1211 + defparam sc_rom_monitor_0_0_1.INITVAL_0D = 320'h100040FFF400000200000FFFF01000000000000210054100000FFFF01000100FF00000100FF00000 ; 21.1212 + defparam sc_rom_monitor_0_0_1.INITVAL_0C = 320'h0FFFE1010001000000000007430084200002009830000300943000030090300003008C2007C10078 ; 21.1213 + defparam sc_rom_monitor_0_0_1.INITVAL_0B = 320'h300702006C1006800064300602005C1005800054300502004C1004800044300402003C1003800034 ; 21.1214 + defparam sc_rom_monitor_0_0_1.INITVAL_0A = 320'h300302002C1002800024300202001C1001800014300102000C100080000000074200842000020098 ; 21.1215 + defparam sc_rom_monitor_0_0_1.INITVAL_09 = 320'h20000200942000020090200002008C3008010078300702006C1006800064300602005C1005800054 ; 21.1216 + defparam sc_rom_monitor_0_0_1.INITVAL_08 = 320'h300502004C1004800044300402003C1003800034300302002C1002800024300202001C1001800014 ; 21.1217 + defparam sc_rom_monitor_0_0_1.INITVAL_07 = 320'h300102000C10008000001F9A00E000000041007810000100881000110001100011000110001100FF ; 21.1218 + defparam sc_rom_monitor_0_0_1.INITVAL_06 = 320'h1F9A0100940080010090008001008C008001009C008001009800800300802007C00074300702006C ; 21.1219 + defparam sc_rom_monitor_0_0_1.INITVAL_05 = 320'h1006800064300602005C1005800054300502004C1004800044300402003C1003800034300302002C ; 21.1220 + defparam sc_rom_monitor_0_0_1.INITVAL_04 = 320'h1002800024300202001C1001800014300102000C100080000000000106603FFC530000007F40E000 ; 21.1221 + defparam sc_rom_monitor_0_0_1.INITVAL_03 = 320'h0003E000BC1000400800200840000A000000000000046000C4100040080020084000120000000000 ; 21.1222 + defparam sc_rom_monitor_0_0_1.INITVAL_02 = 320'h0004E000CC1000400800200840001A000000000000056000D4100040080020084000220000000000 ; 21.1223 + defparam sc_rom_monitor_0_0_1.INITVAL_01 = 320'h00086000DC1000400800300840002A000000000000066000E4100040080020084000320000000000 ; 21.1224 + defparam sc_rom_monitor_0_0_1.INITVAL_00 = 320'h00096000EC1000400800300840003A000000000000000000000000000000000000003E0000000000 ; 21.1225 + defparam sc_rom_monitor_0_0_1.CSDECODE_B = 3'b000 ; 21.1226 + defparam sc_rom_monitor_0_0_1.CSDECODE_A = 3'b000 ; 21.1227 + defparam sc_rom_monitor_0_0_1.WRITEMODE_B = "NORMAL" ; 21.1228 + defparam sc_rom_monitor_0_0_1.WRITEMODE_A = "NORMAL" ; 21.1229 + defparam sc_rom_monitor_0_0_1.GSR = "DISABLED" ; 21.1230 + defparam sc_rom_monitor_0_0_1.RESETMODE = "SYNC" ; 21.1231 + defparam sc_rom_monitor_0_0_1.REGMODE_B = "NOREG" ; 21.1232 + defparam sc_rom_monitor_0_0_1.REGMODE_A = "NOREG" ; 21.1233 + defparam sc_rom_monitor_0_0_1.DATA_WIDTH_B = 18 ; 21.1234 + defparam sc_rom_monitor_0_0_1.DATA_WIDTH_A = 18 ; 21.1235 + // synopsys translate_on 21.1236 + DP16KA sc_rom_monitor_0_0_1 (.DIA0(DataInA[0]), .DIA1(DataInA[1]), .DIA2(DataInA[2]), 21.1237 + .DIA3(DataInA[3]), .DIA4(DataInA[4]), .DIA5(DataInA[5]), .DIA6(DataInA[6]), 21.1238 + .DIA7(DataInA[7]), .DIA8(DataInA[8]), .DIA9(DataInA[9]), .DIA10(DataInA[10]), 21.1239 + .DIA11(DataInA[11]), .DIA12(DataInA[12]), .DIA13(DataInA[13]), .DIA14(DataInA[14]), 21.1240 + .DIA15(DataInA[15]), .DIA16(DataInA[16]), .DIA17(DataInA[17]), .ADA0(scuba_vhi), 21.1241 + .ADA1(scuba_vhi), .ADA2(scuba_vlo), .ADA3(scuba_vlo), .ADA4(AddressA[0]), 21.1242 + .ADA5(AddressA[1]), .ADA6(AddressA[2]), .ADA7(AddressA[3]), .ADA8(AddressA[4]), 21.1243 + .ADA9(AddressA[5]), .ADA10(AddressA[6]), .ADA11(AddressA[7]), .ADA12(AddressA[8]), 21.1244 + .ADA13(scuba_vlo), .CEA(ClockEnA), .CLKA(ClockA), .WEA(WrA), .CSA0(scuba_vlo), 21.1245 + .CSA1(scuba_vlo), .CSA2(scuba_vlo), .RSTA(ResetA), .DIB0(DataInB[0]), 21.1246 + .DIB1(DataInB[1]), .DIB2(DataInB[2]), .DIB3(DataInB[3]), .DIB4(DataInB[4]), 21.1247 + .DIB5(DataInB[5]), .DIB6(DataInB[6]), .DIB7(DataInB[7]), .DIB8(DataInB[8]), 21.1248 + .DIB9(DataInB[9]), .DIB10(DataInB[10]), .DIB11(DataInB[11]), .DIB12(DataInB[12]), 21.1249 + .DIB13(DataInB[13]), .DIB14(DataInB[14]), .DIB15(DataInB[15]), .DIB16(DataInB[16]), 21.1250 + .DIB17(DataInB[17]), .ADB0(scuba_vhi), .ADB1(scuba_vhi), .ADB2(scuba_vlo), 21.1251 + .ADB3(scuba_vlo), .ADB4(AddressB[0]), .ADB5(AddressB[1]), .ADB6(AddressB[2]), 21.1252 + .ADB7(AddressB[3]), .ADB8(AddressB[4]), .ADB9(AddressB[5]), .ADB10(AddressB[6]), 21.1253 + .ADB11(AddressB[7]), .ADB12(AddressB[8]), .ADB13(scuba_vlo), .CEB(ClockEnB), 21.1254 + .CLKB(ClockB), .WEB(WrB), .CSB0(scuba_vlo), .CSB1(scuba_vlo), .CSB2(scuba_vlo), 21.1255 + .RSTB(ResetB), .DOA0(QA[0]), .DOA1(QA[1]), .DOA2(QA[2]), .DOA3(QA[3]), 21.1256 + .DOA4(QA[4]), .DOA5(QA[5]), .DOA6(QA[6]), .DOA7(QA[7]), .DOA8(QA[8]), 21.1257 + .DOA9(QA[9]), .DOA10(QA[10]), .DOA11(QA[11]), .DOA12(QA[12]), .DOA13(QA[13]), 21.1258 + .DOA14(QA[14]), .DOA15(QA[15]), .DOA16(QA[16]), .DOA17(QA[17]), 21.1259 + .DOB0(QB[0]), .DOB1(QB[1]), .DOB2(QB[2]), .DOB3(QB[3]), .DOB4(QB[4]), 21.1260 + .DOB5(QB[5]), .DOB6(QB[6]), .DOB7(QB[7]), .DOB8(QB[8]), .DOB9(QB[9]), 21.1261 + .DOB10(QB[10]), .DOB11(QB[11]), .DOB12(QB[12]), .DOB13(QB[13]), 21.1262 + .DOB14(QB[14]), .DOB15(QB[15]), .DOB16(QB[16]), .DOB17(QB[17])) 21.1263 + /* synthesis MEM_LPC_FILE="sc_rom_monitor.lpc" */ 21.1264 + /* synthesis MEM_INIT_FILE="lm32_monitor.mem" */ 21.1265 + /* synthesis INITVAL_3F="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1266 + /* synthesis INITVAL_3E="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1267 + /* synthesis INITVAL_3D="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1268 + /* synthesis INITVAL_3C="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1269 + /* synthesis INITVAL_3B="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1270 + /* synthesis INITVAL_3A="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1271 + /* synthesis INITVAL_39="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1272 + /* synthesis INITVAL_38="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1273 + /* synthesis INITVAL_37="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1274 + /* synthesis INITVAL_36="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1275 + /* synthesis INITVAL_35="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1276 + /* synthesis INITVAL_34="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1277 + /* synthesis INITVAL_33="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1278 + /* synthesis INITVAL_32="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1279 + /* synthesis INITVAL_31="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1280 + /* synthesis INITVAL_30="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1281 + /* synthesis INITVAL_2F="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1282 + /* synthesis INITVAL_2E="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1283 + /* synthesis INITVAL_2D="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1284 + /* synthesis INITVAL_2C="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1285 + /* synthesis INITVAL_2B="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1286 + /* synthesis INITVAL_2A="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1287 + /* synthesis INITVAL_29="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1288 + /* synthesis INITVAL_28="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1289 + /* synthesis INITVAL_27="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1290 + /* synthesis INITVAL_26="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1291 + /* synthesis INITVAL_25="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1292 + /* synthesis INITVAL_24="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1293 + /* synthesis INITVAL_23="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1294 + /* synthesis INITVAL_22="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1295 + /* synthesis INITVAL_21="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1296 + /* synthesis INITVAL_20="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1297 + /* synthesis INITVAL_1F="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1298 + /* synthesis INITVAL_1E="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1299 + /* synthesis INITVAL_1D="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1300 + /* synthesis INITVAL_1C="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1301 + /* synthesis INITVAL_1B="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1302 + /* synthesis INITVAL_1A="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1303 + /* synthesis INITVAL_19="0x0000000000000000000000000000000000000000000000000000000000000000000000000003FF81" */ 21.1304 + /* synthesis INITVAL_18="0x300003FF83300003FF85300003FF873FF4A1004F3FF8A300003FF8C300003FF8E300003FF9030000" */ 21.1305 + /* synthesis INITVAL_17="0x3FF92300003FF94300003FF96300003FFC100800070003FFFB0000130001100003FF5B1001700000" */ 21.1306 + /* synthesis INITVAL_16="0x068003FF70058003FF723FFFB300013FF6A00001100001FFAB00000068003FF7B058003FF7D3FFB1" */ 21.1307 + /* synthesis INITVAL_15="0x3FF8D008003FFB4300000FFB61001B000361001A0002F10019000381001800038100130003310012" */ 21.1308 + /* synthesis INITVAL_14="0x00033100110003310010000331000900033100080003310007010003FF89058003FF9C3FFF900800" */ 21.1309 + /* synthesis INITVAL_13="0x070000FFFB30800070003FFD63FFB200800000041000A0004110006010003FF9A000000002410004" */ 21.1310 + /* synthesis INITVAL_12="0x200081000C0001030014200181001C00020300240000000000000001000000000000000000010000" */ 21.1311 + /* synthesis INITVAL_11="0x100010FFF310063000501004D000471006D00046100720002C100570001F10077010003FFBC00000" */ 21.1312 + /* synthesis INITVAL_10="0x30000044003FC0010000100540FFFF0080010000100540FFFF008000880010004200081000C00010" */ 21.1313 + /* synthesis INITVAL_0F="0x30014200181001C00020300240FFDC0000000008100043FFDD100083FFDF100093FFE11000A3FFE3" */ 21.1314 + /* synthesis INITVAL_0E="0x1000B10008100040FFF8000000000C1000410008100083FFE7100093FFE91000A3FFEB1000B3FFED" */ 21.1315 + /* synthesis INITVAL_0D="0x100040FFF400000200000FFFF01000000000000210054100000FFFF01000100FF00000100FF00000" */ 21.1316 + /* synthesis INITVAL_0C="0x0FFFE1010001000000000007430084200002009830000300943000030090300003008C2007C10078" */ 21.1317 + /* synthesis INITVAL_0B="0x300702006C1006800064300602005C1005800054300502004C1004800044300402003C1003800034" */ 21.1318 + /* synthesis INITVAL_0A="0x300302002C1002800024300202001C1001800014300102000C100080000000074200842000020098" */ 21.1319 + /* synthesis INITVAL_09="0x20000200942000020090200002008C3008010078300702006C1006800064300602005C1005800054" */ 21.1320 + /* synthesis INITVAL_08="0x300502004C1004800044300402003C1003800034300302002C1002800024300202001C1001800014" */ 21.1321 + /* synthesis INITVAL_07="0x300102000C10008000001F9A00E000000041007810000100881000110001100011000110001100FF" */ 21.1322 + /* synthesis INITVAL_06="0x1F9A0100940080010090008001008C008001009C008001009800800300802007C00074300702006C" */ 21.1323 + /* synthesis INITVAL_05="0x1006800064300602005C1005800054300502004C1004800044300402003C1003800034300302002C" */ 21.1324 + /* synthesis INITVAL_04="0x1002800024300202001C1001800014300102000C100080000000000106603FFC530000007F40E000" */ 21.1325 + /* synthesis INITVAL_03="0x0003E000BC1000400800200840000A000000000000046000C4100040080020084000120000000000" */ 21.1326 + /* synthesis INITVAL_02="0x0004E000CC1000400800200840001A000000000000056000D4100040080020084000220000000000" */ 21.1327 + /* synthesis INITVAL_01="0x00086000DC1000400800300840002A000000000000066000E4100040080020084000320000000000" */ 21.1328 + /* synthesis INITVAL_00="0x00096000EC1000400800300840003A000000000000000000000000000000000000003E0000000000" */ 21.1329 + /* synthesis CSDECODE_B="0b000" */ 21.1330 + /* synthesis CSDECODE_A="0b000" */ 21.1331 + /* synthesis WRITEMODE_B="NORMAL" */ 21.1332 + /* synthesis WRITEMODE_A="NORMAL" */ 21.1333 + /* synthesis GSR="DISABLED" */ 21.1334 + /* synthesis RESETMODE="SYNC" */ 21.1335 + /* synthesis REGMODE_B="NOREG" */ 21.1336 + /* synthesis REGMODE_A="NOREG" */ 21.1337 + /* synthesis DATA_WIDTH_B="18" */ 21.1338 + /* synthesis DATA_WIDTH_A="18" */; 21.1339 + 21.1340 + VHI scuba_vhi_inst (.Z(scuba_vhi)); 21.1341 + 21.1342 + VLO scuba_vlo_inst (.Z(scuba_vlo)); 21.1343 + 21.1344 + // synopsys translate_off 21.1345 + defparam sc_rom_monitor_0_1_0.INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1346 + defparam sc_rom_monitor_0_1_0.INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1347 + defparam sc_rom_monitor_0_1_0.INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1348 + defparam sc_rom_monitor_0_1_0.INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1349 + defparam sc_rom_monitor_0_1_0.INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1350 + defparam sc_rom_monitor_0_1_0.INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1351 + defparam sc_rom_monitor_0_1_0.INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1352 + defparam sc_rom_monitor_0_1_0.INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1353 + defparam sc_rom_monitor_0_1_0.INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1354 + defparam sc_rom_monitor_0_1_0.INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1355 + defparam sc_rom_monitor_0_1_0.INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1356 + defparam sc_rom_monitor_0_1_0.INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1357 + defparam sc_rom_monitor_0_1_0.INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1358 + defparam sc_rom_monitor_0_1_0.INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1359 + defparam sc_rom_monitor_0_1_0.INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1360 + defparam sc_rom_monitor_0_1_0.INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1361 + defparam sc_rom_monitor_0_1_0.INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1362 + defparam sc_rom_monitor_0_1_0.INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1363 + defparam sc_rom_monitor_0_1_0.INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1364 + defparam sc_rom_monitor_0_1_0.INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1365 + defparam sc_rom_monitor_0_1_0.INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1366 + defparam sc_rom_monitor_0_1_0.INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1367 + defparam sc_rom_monitor_0_1_0.INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1368 + defparam sc_rom_monitor_0_1_0.INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1369 + defparam sc_rom_monitor_0_1_0.INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1370 + defparam sc_rom_monitor_0_1_0.INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1371 + defparam sc_rom_monitor_0_1_0.INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1372 + defparam sc_rom_monitor_0_1_0.INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1373 + defparam sc_rom_monitor_0_1_0.INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1374 + defparam sc_rom_monitor_0_1_0.INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1375 + defparam sc_rom_monitor_0_1_0.INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1376 + defparam sc_rom_monitor_0_1_0.INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1377 + defparam sc_rom_monitor_0_1_0.INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1378 + defparam sc_rom_monitor_0_1_0.INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1379 + defparam sc_rom_monitor_0_1_0.INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1380 + defparam sc_rom_monitor_0_1_0.INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1381 + defparam sc_rom_monitor_0_1_0.INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1382 + defparam sc_rom_monitor_0_1_0.INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ; 21.1383 + defparam sc_rom_monitor_0_1_0.INITVAL_19 = 320'h000000000000000000000000000000000000000000000000000000000000000000000000000038FF ; 21.1384 + defparam sc_rom_monitor_0_1_0.INITVAL_18 = 320'h034D2038FF034C2038FF0349A038FF03EFF00D00038FF034CA038FF03492038FF0348A038FF03482 ; 21.1385 + defparam sc_rom_monitor_0_1_0.INITVAL_17 = 320'h038FF0344A038FF03442038FF0343A038FF02E7002430038FF00D6300D5A00C5803EFF0136300D03 ; 21.1386 + defparam sc_rom_monitor_0_1_0.INITVAL_16 = 320'h02E0803EFF02E0803EFF038FF00D5A03EFF00D63010580136300D0302E0803EFF02E0803EFF038FF ; 21.1387 + defparam sc_rom_monitor_0_1_0.INITVAL_15 = 320'h03EFF02E88038FF034DA0170801F100110801F100110801F100110801F100110801F100110801F10 ; 21.1388 + defparam sc_rom_monitor_0_1_0.INITVAL_14 = 320'h0110801F100110801F100110801F100110801F100110801F0802E0803EFF02E0803EFF038FF02E70 ; 21.1389 + defparam sc_rom_monitor_0_1_0.INITVAL_13 = 320'h024500110C0287302430038FF03EFF02E700110801F100110801F0802E0803EFF030E800DE700AE7 ; 21.1390 + defparam sc_rom_monitor_0_1_0.INITVAL_12 = 320'h00AE400AE400AE400AE300AE300AE300AE300AE200D0000D0000D000342000D0000D0000D0003418 ; 21.1391 + defparam sc_rom_monitor_0_1_0.INITVAL_11 = 320'h00D000170801F100110801F100110801F100110801F100110801F100110801F0802E0803EFF00E84 ; 21.1392 + defparam sc_rom_monitor_0_1_0.INITVAL_10 = 320'h00E7B01E0401E030347000D0001708024700347000D00017080247002E08016E7016E4016E4016E4 ; 21.1393 + defparam sc_rom_monitor_0_1_0.INITVAL_0F = 320'h016E3016E3016E3016E3016E200DE7030E800DE700AE703EFF010E003EFF010E003EFF010E003EFF ; 21.1394 + defparam sc_rom_monitor_0_1_0.INITVAL_0E = 320'h010E0016E0016E700DE7030E800DE700AE700AE000CE003EFF00CE003EFF00CE003EFF00CE003EFF ; 21.1395 + defparam sc_rom_monitor_0_1_0.INITVAL_0D = 320'h016E700DE7030E8034700171002470030E80110801F0803470017100247000808030E80081003478 ; 21.1396 + defparam sc_rom_monitor_0_1_0.INITVAL_0C = 320'h011080081002478030F800AE700AE70340F00AE70340700AE70344F00AE70343F00AE700AE700AE7 ; 21.1397 + defparam sc_rom_monitor_0_1_0.INITVAL_0B = 320'h00AE600AE600AE600AE600AE500AE500AE500AE500AE400AE400AE400AE400AE300AE300AE300AE3 ; 21.1398 + defparam sc_rom_monitor_0_1_0.INITVAL_0A = 320'h00AE200AE200AE200AE200AE100AE100AE100AE100AE000AE000AE0030F000AE700AE70340F00AE7 ; 21.1399 + defparam sc_rom_monitor_0_1_0.INITVAL_09 = 320'h0340700AE70344F00AE70343F00AE700AE700AE700AE600AE600AE600AE600AE500AE500AE500AE5 ; 21.1400 + defparam sc_rom_monitor_0_1_0.INITVAL_08 = 320'h00AE400AE400AE400AE400AE300AE300AE300AE300AE200AE200AE200AE200AE100AE100AE100AE1 ; 21.1401 + defparam sc_rom_monitor_0_1_0.INITVAL_07 = 320'h00AE000AE000AE0030E800DEF02EE8016E8016E800AE8016E8000080000800008000080000800808 ; 21.1402 + defparam sc_rom_monitor_0_1_0.INITVAL_06 = 320'h00DE8016E802400016E802448016E802438016E802410016E802408016EF016EF016EF016EE016EE ; 21.1403 + defparam sc_rom_monitor_0_1_0.INITVAL_05 = 320'h016EE016EE016ED016ED016ED016ED016EC016EC016EC016EC016EB016EB016EB016EB016EA016EA ; 21.1404 + defparam sc_rom_monitor_0_1_0.INITVAL_04 = 320'h016EA016EA016E9016E9016E9016E9016E8016E8016E802600016E800DEF038FF00D0700DE702EE8 ; 21.1405 + defparam sc_rom_monitor_0_1_0.INITVAL_03 = 320'h0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600 ; 21.1406 + defparam sc_rom_monitor_0_1_0.INITVAL_02 = 320'h0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600 ; 21.1407 + defparam sc_rom_monitor_0_1_0.INITVAL_01 = 320'h0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600 ; 21.1408 + defparam sc_rom_monitor_0_1_0.INITVAL_00 = 320'h0380003E0000D0802EE0016E703E0002EE80260000D0000D0000D0000D0000D0003E000340802600 ; 21.1409 + defparam sc_rom_monitor_0_1_0.CSDECODE_B = 3'b000 ; 21.1410 + defparam sc_rom_monitor_0_1_0.CSDECODE_A = 3'b000 ; 21.1411 + defparam sc_rom_monitor_0_1_0.WRITEMODE_B = "NORMAL" ; 21.1412 + defparam sc_rom_monitor_0_1_0.WRITEMODE_A = "NORMAL" ; 21.1413 + defparam sc_rom_monitor_0_1_0.GSR = "DISABLED" ; 21.1414 + defparam sc_rom_monitor_0_1_0.RESETMODE = "SYNC" ; 21.1415 + defparam sc_rom_monitor_0_1_0.REGMODE_B = "NOREG" ; 21.1416 + defparam sc_rom_monitor_0_1_0.REGMODE_A = "NOREG" ; 21.1417 + defparam sc_rom_monitor_0_1_0.DATA_WIDTH_B = 18 ; 21.1418 + defparam sc_rom_monitor_0_1_0.DATA_WIDTH_A = 18 ; 21.1419 + // synopsys translate_on 21.1420 + DP16KA sc_rom_monitor_0_1_0 (.DIA0(DataInA[18]), .DIA1(DataInA[19]), 21.1421 + .DIA2(DataInA[20]), .DIA3(DataInA[21]), .DIA4(DataInA[22]), .DIA5(DataInA[23]), 21.1422 + .DIA6(DataInA[24]), .DIA7(DataInA[25]), .DIA8(DataInA[26]), .DIA9(DataInA[27]), 21.1423 + .DIA10(DataInA[28]), .DIA11(DataInA[29]), .DIA12(DataInA[30]), .DIA13(DataInA[31]), 21.1424 + .DIA14(scuba_vlo), .DIA15(scuba_vlo), .DIA16(scuba_vlo), .DIA17(scuba_vlo), 21.1425 + .ADA0(scuba_vhi), .ADA1(scuba_vhi), .ADA2(scuba_vlo), .ADA3(scuba_vlo), 21.1426 + .ADA4(AddressA[0]), .ADA5(AddressA[1]), .ADA6(AddressA[2]), .ADA7(AddressA[3]), 21.1427 + .ADA8(AddressA[4]), .ADA9(AddressA[5]), .ADA10(AddressA[6]), .ADA11(AddressA[7]), 21.1428 + .ADA12(AddressA[8]), .ADA13(scuba_vlo), .CEA(ClockEnA), .CLKA(ClockA), 21.1429 + .WEA(WrA), .CSA0(scuba_vlo), .CSA1(scuba_vlo), .CSA2(scuba_vlo), 21.1430 + .RSTA(ResetA), .DIB0(DataInB[18]), .DIB1(DataInB[19]), .DIB2(DataInB[20]), 21.1431 + .DIB3(DataInB[21]), .DIB4(DataInB[22]), .DIB5(DataInB[23]), .DIB6(DataInB[24]), 21.1432 + .DIB7(DataInB[25]), .DIB8(DataInB[26]), .DIB9(DataInB[27]), .DIB10(DataInB[28]), 21.1433 + .DIB11(DataInB[29]), .DIB12(DataInB[30]), .DIB13(DataInB[31]), .DIB14(scuba_vlo), 21.1434 + .DIB15(scuba_vlo), .DIB16(scuba_vlo), .DIB17(scuba_vlo), .ADB0(scuba_vhi), 21.1435 + .ADB1(scuba_vhi), .ADB2(scuba_vlo), .ADB3(scuba_vlo), .ADB4(AddressB[0]), 21.1436 + .ADB5(AddressB[1]), .ADB6(AddressB[2]), .ADB7(AddressB[3]), .ADB8(AddressB[4]), 21.1437 + .ADB9(AddressB[5]), .ADB10(AddressB[6]), .ADB11(AddressB[7]), .ADB12(AddressB[8]), 21.1438 + .ADB13(scuba_vlo), .CEB(ClockEnB), .CLKB(ClockB), .WEB(WrB), .CSB0(scuba_vlo), 21.1439 + .CSB1(scuba_vlo), .CSB2(scuba_vlo), .RSTB(ResetB), .DOA0(QA[18]), 21.1440 + .DOA1(QA[19]), .DOA2(QA[20]), .DOA3(QA[21]), .DOA4(QA[22]), .DOA5(QA[23]), 21.1441 + .DOA6(QA[24]), .DOA7(QA[25]), .DOA8(QA[26]), .DOA9(QA[27]), .DOA10(QA[28]), 21.1442 + .DOA11(QA[29]), .DOA12(QA[30]), .DOA13(QA[31]), .DOA14(), .DOA15(), 21.1443 + .DOA16(), .DOA17(), .DOB0(QB[18]), .DOB1(QB[19]), .DOB2(QB[20]), 21.1444 + .DOB3(QB[21]), .DOB4(QB[22]), .DOB5(QB[23]), .DOB6(QB[24]), .DOB7(QB[25]), 21.1445 + .DOB8(QB[26]), .DOB9(QB[27]), .DOB10(QB[28]), .DOB11(QB[29]), .DOB12(QB[30]), 21.1446 + .DOB13(QB[31]), .DOB14(), .DOB15(), .DOB16(), .DOB17()) 21.1447 + /* synthesis MEM_LPC_FILE="sc_rom_monitor.lpc" */ 21.1448 + /* synthesis MEM_INIT_FILE="lm32_monitor.mem" */ 21.1449 + /* synthesis INITVAL_3F="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1450 + /* synthesis INITVAL_3E="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1451 + /* synthesis INITVAL_3D="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1452 + /* synthesis INITVAL_3C="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1453 + /* synthesis INITVAL_3B="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1454 + /* synthesis INITVAL_3A="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1455 + /* synthesis INITVAL_39="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1456 + /* synthesis INITVAL_38="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1457 + /* synthesis INITVAL_37="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1458 + /* synthesis INITVAL_36="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1459 + /* synthesis INITVAL_35="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1460 + /* synthesis INITVAL_34="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1461 + /* synthesis INITVAL_33="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1462 + /* synthesis INITVAL_32="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1463 + /* synthesis INITVAL_31="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1464 + /* synthesis INITVAL_30="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1465 + /* synthesis INITVAL_2F="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1466 + /* synthesis INITVAL_2E="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1467 + /* synthesis INITVAL_2D="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1468 + /* synthesis INITVAL_2C="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1469 + /* synthesis INITVAL_2B="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1470 + /* synthesis INITVAL_2A="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1471 + /* synthesis INITVAL_29="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1472 + /* synthesis INITVAL_28="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1473 + /* synthesis INITVAL_27="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1474 + /* synthesis INITVAL_26="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1475 + /* synthesis INITVAL_25="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1476 + /* synthesis INITVAL_24="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1477 + /* synthesis INITVAL_23="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1478 + /* synthesis INITVAL_22="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1479 + /* synthesis INITVAL_21="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1480 + /* synthesis INITVAL_20="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1481 + /* synthesis INITVAL_1F="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1482 + /* synthesis INITVAL_1E="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1483 + /* synthesis INITVAL_1D="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1484 + /* synthesis INITVAL_1C="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1485 + /* synthesis INITVAL_1B="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1486 + /* synthesis INITVAL_1A="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */ 21.1487 + /* synthesis INITVAL_19="0x000000000000000000000000000000000000000000000000000000000000000000000000000038FF" */ 21.1488 + /* synthesis INITVAL_18="0x034D2038FF034C2038FF0349A038FF03EFF00D00038FF034CA038FF03492038FF0348A038FF03482" */ 21.1489 + /* synthesis INITVAL_17="0x038FF0344A038FF03442038FF0343A038FF02E7002430038FF00D6300D5A00C5803EFF0136300D03" */ 21.1490 + /* synthesis INITVAL_16="0x02E0803EFF02E0803EFF038FF00D5A03EFF00D63010580136300D0302E0803EFF02E0803EFF038FF" */ 21.1491 + /* synthesis INITVAL_15="0x03EFF02E88038FF034DA0170801F100110801F100110801F100110801F100110801F100110801F10" */ 21.1492 + /* synthesis INITVAL_14="0x0110801F100110801F100110801F100110801F100110801F0802E0803EFF02E0803EFF038FF02E70" */ 21.1493 + /* synthesis INITVAL_13="0x024500110C0287302430038FF03EFF02E700110801F100110801F0802E0803EFF030E800DE700AE7" */ 21.1494 + /* synthesis INITVAL_12="0x00AE400AE400AE400AE300AE300AE300AE300AE200D0000D0000D000342000D0000D0000D0003418" */ 21.1495 + /* synthesis INITVAL_11="0x00D000170801F100110801F100110801F100110801F100110801F100110801F0802E0803EFF00E84" */ 21.1496 + /* synthesis INITVAL_10="0x00E7B01E0401E030347000D0001708024700347000D00017080247002E08016E7016E4016E4016E4" */ 21.1497 + /* synthesis INITVAL_0F="0x016E3016E3016E3016E3016E200DE7030E800DE700AE703EFF010E003EFF010E003EFF010E003EFF" */ 21.1498 + /* synthesis INITVAL_0E="0x010E0016E0016E700DE7030E800DE700AE700AE000CE003EFF00CE003EFF00CE003EFF00CE003EFF" */ 21.1499 + /* synthesis INITVAL_0D="0x016E700DE7030E8034700171002470030E80110801F0803470017100247000808030E80081003478" */ 21.1500 + /* synthesis INITVAL_0C="0x011080081002478030F800AE700AE70340F00AE70340700AE70344F00AE70343F00AE700AE700AE7" */ 21.1501 + /* synthesis INITVAL_0B="0x00AE600AE600AE600AE600AE500AE500AE500AE500AE400AE400AE400AE400AE300AE300AE300AE3" */ 21.1502 + /* synthesis INITVAL_0A="0x00AE200AE200AE200AE200AE100AE100AE100AE100AE000AE000AE0030F000AE700AE70340F00AE7" */ 21.1503 + /* synthesis INITVAL_09="0x0340700AE70344F00AE70343F00AE700AE700AE700AE600AE600AE600AE600AE500AE500AE500AE5" */ 21.1504 + /* synthesis INITVAL_08="0x00AE400AE400AE400AE400AE300AE300AE300AE300AE200AE200AE200AE200AE100AE100AE100AE1" */ 21.1505 + /* synthesis INITVAL_07="0x00AE000AE000AE0030E800DEF02EE8016E8016E800AE8016E8000080000800008000080000800808" */ 21.1506 + /* synthesis INITVAL_06="0x00DE8016E802400016E802448016E802438016E802410016E802408016EF016EF016EF016EE016EE" */ 21.1507 + /* synthesis INITVAL_05="0x016EE016EE016ED016ED016ED016ED016EC016EC016EC016EC016EB016EB016EB016EB016EA016EA" */ 21.1508 + /* synthesis INITVAL_04="0x016EA016EA016E9016E9016E9016E9016E8016E8016E802600016E800DEF038FF00D0700DE702EE8" */ 21.1509 + /* synthesis INITVAL_03="0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600" */ 21.1510 + /* synthesis INITVAL_02="0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600" */ 21.1511 + /* synthesis INITVAL_01="0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600" */ 21.1512 + /* synthesis INITVAL_00="0x0380003E0000D0802EE0016E703E0002EE80260000D0000D0000D0000D0000D0003E000340802600" */ 21.1513 + /* synthesis CSDECODE_B="0b000" */ 21.1514 + /* synthesis CSDECODE_A="0b000" */ 21.1515 + /* synthesis WRITEMODE_B="NORMAL" */ 21.1516 + /* synthesis WRITEMODE_A="NORMAL" */ 21.1517 + /* synthesis GSR="DISABLED" */ 21.1518 + /* synthesis RESETMODE="SYNC" */ 21.1519 + /* synthesis REGMODE_B="NOREG" */ 21.1520 + /* synthesis REGMODE_A="NOREG" */ 21.1521 + /* synthesis DATA_WIDTH_B="18" */ 21.1522 + /* synthesis DATA_WIDTH_A="18" */; 21.1523 + 21.1524 + 21.1525 + 21.1526 + // exemplar begin 21.1527 + // exemplar attribute sc_rom_monitor_0_0_1 MEM_LPC_FILE sc_rom_monitor.lpc 21.1528 + // exemplar attribute sc_rom_monitor_0_0_1 MEM_INIT_FILE lm32_monitor.mem 21.1529 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_3F 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1530 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_3E 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1531 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_3D 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1532 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_3C 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1533 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_3B 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1534 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_3A 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1535 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_39 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1536 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_38 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1537 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_37 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1538 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_36 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1539 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_35 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1540 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_34 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1541 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_33 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1542 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_32 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1543 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_31 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1544 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_30 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1545 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_2F 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1546 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_2E 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1547 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_2D 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1548 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_2C 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1549 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_2B 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1550 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_2A 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1551 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_29 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1552 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_28 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1553 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_27 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1554 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_26 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1555 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_25 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1556 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_24 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1557 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_23 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1558 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_22 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1559 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_21 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1560 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_20 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1561 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_1F 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1562 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_1E 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1563 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_1D 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1564 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_1C 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1565 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_1B 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1566 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_1A 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1567 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_19 0x0000000000000000000000000000000000000000000000000000000000000000000000000003FF81 21.1568 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_18 0x300003FF83300003FF85300003FF873FF4A1004F3FF8A300003FF8C300003FF8E300003FF9030000 21.1569 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_17 0x3FF92300003FF94300003FF96300003FFC100800070003FFFB0000130001100003FF5B1001700000 21.1570 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_16 0x068003FF70058003FF723FFFB300013FF6A00001100001FFAB00000068003FF7B058003FF7D3FFB1 21.1571 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_15 0x3FF8D008003FFB4300000FFB61001B000361001A0002F10019000381001800038100130003310012 21.1572 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_14 0x00033100110003310010000331000900033100080003310007010003FF89058003FF9C3FFF900800 21.1573 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_13 0x070000FFFB30800070003FFD63FFB200800000041000A0004110006010003FF9A000000002410004 21.1574 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_12 0x200081000C0001030014200181001C00020300240000000000000001000000000000000000010000 21.1575 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_11 0x100010FFF310063000501004D000471006D00046100720002C100570001F10077010003FFBC00000 21.1576 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_10 0x30000044003FC0010000100540FFFF0080010000100540FFFF008000880010004200081000C00010 21.1577 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_0F 0x30014200181001C00020300240FFDC0000000008100043FFDD100083FFDF100093FFE11000A3FFE3 21.1578 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_0E 0x1000B10008100040FFF8000000000C1000410008100083FFE7100093FFE91000A3FFEB1000B3FFED 21.1579 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_0D 0x100040FFF400000200000FFFF01000000000000210054100000FFFF01000100FF00000100FF00000 21.1580 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_0C 0x0FFFE1010001000000000007430084200002009830000300943000030090300003008C2007C10078 21.1581 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_0B 0x300702006C1006800064300602005C1005800054300502004C1004800044300402003C1003800034 21.1582 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_0A 0x300302002C1002800024300202001C1001800014300102000C100080000000074200842000020098 21.1583 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_09 0x20000200942000020090200002008C3008010078300702006C1006800064300602005C1005800054 21.1584 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_08 0x300502004C1004800044300402003C1003800034300302002C1002800024300202001C1001800014 21.1585 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_07 0x300102000C10008000001F9A00E000000041007810000100881000110001100011000110001100FF 21.1586 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_06 0x1F9A0100940080010090008001008C008001009C008001009800800300802007C00074300702006C 21.1587 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_05 0x1006800064300602005C1005800054300502004C1004800044300402003C1003800034300302002C 21.1588 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_04 0x1002800024300202001C1001800014300102000C100080000000000106603FFC530000007F40E000 21.1589 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_03 0x0003E000BC1000400800200840000A000000000000046000C4100040080020084000120000000000 21.1590 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_02 0x0004E000CC1000400800200840001A000000000000056000D4100040080020084000220000000000 21.1591 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_01 0x00086000DC1000400800300840002A000000000000066000E4100040080020084000320000000000 21.1592 + // exemplar attribute sc_rom_monitor_0_0_1 INITVAL_00 0x00096000EC1000400800300840003A000000000000000000000000000000000000003E0000000000 21.1593 + // exemplar attribute sc_rom_monitor_0_0_1 CSDECODE_B 0b000 21.1594 + // exemplar attribute sc_rom_monitor_0_0_1 CSDECODE_A 0b000 21.1595 + // exemplar attribute sc_rom_monitor_0_0_1 WRITEMODE_B NORMAL 21.1596 + // exemplar attribute sc_rom_monitor_0_0_1 WRITEMODE_A NORMAL 21.1597 + // exemplar attribute sc_rom_monitor_0_0_1 GSR DISABLED 21.1598 + // exemplar attribute sc_rom_monitor_0_0_1 RESETMODE SYNC 21.1599 + // exemplar attribute sc_rom_monitor_0_0_1 REGMODE_B NOREG 21.1600 + // exemplar attribute sc_rom_monitor_0_0_1 REGMODE_A NOREG 21.1601 + // exemplar attribute sc_rom_monitor_0_0_1 DATA_WIDTH_B 18 21.1602 + // exemplar attribute sc_rom_monitor_0_0_1 DATA_WIDTH_A 18 21.1603 + // exemplar attribute sc_rom_monitor_0_1_0 MEM_LPC_FILE sc_rom_monitor.lpc 21.1604 + // exemplar attribute sc_rom_monitor_0_1_0 MEM_INIT_FILE lm32_monitor.mem 21.1605 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_3F 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1606 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_3E 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1607 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_3D 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1608 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_3C 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1609 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_3B 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1610 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_3A 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1611 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_39 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1612 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_38 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1613 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_37 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1614 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_36 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1615 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_35 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1616 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_34 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1617 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_33 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1618 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_32 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1619 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_31 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1620 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_30 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1621 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_2F 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1622 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_2E 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1623 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_2D 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1624 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_2C 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1625 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_2B 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1626 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_2A 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1627 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_29 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1628 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_28 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1629 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_27 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1630 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_26 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1631 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_25 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1632 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_24 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1633 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_23 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1634 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_22 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1635 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_21 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1636 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_20 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1637 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_1F 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1638 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_1E 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1639 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_1D 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1640 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_1C 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1641 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_1B 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1642 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_1A 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000 21.1643 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_19 0x000000000000000000000000000000000000000000000000000000000000000000000000000038FF 21.1644 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_18 0x034D2038FF034C2038FF0349A038FF03EFF00D00038FF034CA038FF03492038FF0348A038FF03482 21.1645 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_17 0x038FF0344A038FF03442038FF0343A038FF02E7002430038FF00D6300D5A00C5803EFF0136300D03 21.1646 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_16 0x02E0803EFF02E0803EFF038FF00D5A03EFF00D63010580136300D0302E0803EFF02E0803EFF038FF 21.1647 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_15 0x03EFF02E88038FF034DA0170801F100110801F100110801F100110801F100110801F100110801F10 21.1648 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_14 0x0110801F100110801F100110801F100110801F100110801F0802E0803EFF02E0803EFF038FF02E70 21.1649 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_13 0x024500110C0287302430038FF03EFF02E700110801F100110801F0802E0803EFF030E800DE700AE7 21.1650 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_12 0x00AE400AE400AE400AE300AE300AE300AE300AE200D0000D0000D000342000D0000D0000D0003418 21.1651 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_11 0x00D000170801F100110801F100110801F100110801F100110801F100110801F0802E0803EFF00E84 21.1652 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_10 0x00E7B01E0401E030347000D0001708024700347000D00017080247002E08016E7016E4016E4016E4 21.1653 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_0F 0x016E3016E3016E3016E3016E200DE7030E800DE700AE703EFF010E003EFF010E003EFF010E003EFF 21.1654 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_0E 0x010E0016E0016E700DE7030E800DE700AE700AE000CE003EFF00CE003EFF00CE003EFF00CE003EFF 21.1655 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_0D 0x016E700DE7030E8034700171002470030E80110801F0803470017100247000808030E80081003478 21.1656 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_0C 0x011080081002478030F800AE700AE70340F00AE70340700AE70344F00AE70343F00AE700AE700AE7 21.1657 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_0B 0x00AE600AE600AE600AE600AE500AE500AE500AE500AE400AE400AE400AE400AE300AE300AE300AE3 21.1658 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_0A 0x00AE200AE200AE200AE200AE100AE100AE100AE100AE000AE000AE0030F000AE700AE70340F00AE7 21.1659 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_09 0x0340700AE70344F00AE70343F00AE700AE700AE700AE600AE600AE600AE600AE500AE500AE500AE5 21.1660 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_08 0x00AE400AE400AE400AE400AE300AE300AE300AE300AE200AE200AE200AE200AE100AE100AE100AE1 21.1661 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_07 0x00AE000AE000AE0030E800DEF02EE8016E8016E800AE8016E8000080000800008000080000800808 21.1662 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_06 0x00DE8016E802400016E802448016E802438016E802410016E802408016EF016EF016EF016EE016EE 21.1663 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_05 0x016EE016EE016ED016ED016ED016ED016EC016EC016EC016EC016EB016EB016EB016EB016EA016EA 21.1664 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_04 0x016EA016EA016E9016E9016E9016E9016E8016E8016E802600016E800DEF038FF00D0700DE702EE8 21.1665 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_03 0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600 21.1666 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_02 0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600 21.1667 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_01 0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600 21.1668 + // exemplar attribute sc_rom_monitor_0_1_0 INITVAL_00 0x0380003E0000D0802EE0016E703E0002EE80260000D0000D0000D0000D0000D0003E000340802600 21.1669 + // exemplar attribute sc_rom_monitor_0_1_0 CSDECODE_B 0b000 21.1670 + // exemplar attribute sc_rom_monitor_0_1_0 CSDECODE_A 0b000 21.1671 + // exemplar attribute sc_rom_monitor_0_1_0 WRITEMODE_B NORMAL 21.1672 + // exemplar attribute sc_rom_monitor_0_1_0 WRITEMODE_A NORMAL 21.1673 + // exemplar attribute sc_rom_monitor_0_1_0 GSR DISABLED 21.1674 + // exemplar attribute sc_rom_monitor_0_1_0 RESETMODE SYNC 21.1675 + // exemplar attribute sc_rom_monitor_0_1_0 REGMODE_B NOREG 21.1676 + // exemplar attribute sc_rom_monitor_0_1_0 REGMODE_A NOREG 21.1677 + // exemplar attribute sc_rom_monitor_0_1_0 DATA_WIDTH_B 18 21.1678 + // exemplar attribute sc_rom_monitor_0_1_0 DATA_WIDTH_A 18 21.1679 + // exemplar end 21.1680 + 21.1681 + 21.1682 + end 21.1683 + endgenerate 21.1684 + 21.1685 +endmodule 21.1686 +
22.1 diff -r 000000000000 -r cd0b58aa6f83 lm32_multiplier.v 22.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 22.3 +++ b/lm32_multiplier.v Sun Apr 04 20:40:03 2010 +0100 22.4 @@ -0,0 +1,99 @@ 22.5 +// ============================================================================= 22.6 +// COPYRIGHT NOTICE 22.7 +// Copyright 2006 (c) Lattice Semiconductor Corporation 22.8 +// ALL RIGHTS RESERVED 22.9 +// This confidential and proprietary software may be used only as authorised by 22.10 +// a licensing agreement from Lattice Semiconductor Corporation. 22.11 +// The entire notice above must be reproduced on all authorized copies and 22.12 +// copies may only be made to the extent permitted by a licensing agreement from 22.13 +// Lattice Semiconductor Corporation. 22.14 +// 22.15 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 22.16 +// 5555 NE Moore Court 408-826-6000 (other locations) 22.17 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 22.18 +// U.S.A email: techsupport@latticesemi.com 22.19 +// =============================================================================/ 22.20 +// FILE DETAILS 22.21 +// Project : LatticeMico32 22.22 +// File : lm32_multiplier.v 22.23 +// Title : Pipelined multiplier. 22.24 +// Dependencies : lm32_include.v 22.25 +// Version : 6.1.17 22.26 +// : Initial Release 22.27 +// Version : 7.0SP2, 3.0 22.28 +// : No Change 22.29 +// Version : 3.1 22.30 +// : No Change 22.31 +// ============================================================================= 22.32 + 22.33 +`include "lm32_include.v" 22.34 + 22.35 +///////////////////////////////////////////////////// 22.36 +// Module interface 22.37 +///////////////////////////////////////////////////// 22.38 + 22.39 +module lm32_multiplier ( 22.40 + // ----- Inputs ----- 22.41 + clk_i, 22.42 + rst_i, 22.43 + stall_x, 22.44 + stall_m, 22.45 + operand_0, 22.46 + operand_1, 22.47 + // ----- Ouputs ----- 22.48 + result 22.49 + ); 22.50 + 22.51 +///////////////////////////////////////////////////// 22.52 +// Inputs 22.53 +///////////////////////////////////////////////////// 22.54 + 22.55 +input clk_i; // Clock 22.56 +input rst_i; // Reset 22.57 +input stall_x; // Stall instruction in X stage 22.58 +input stall_m; // Stall instruction in M stage 22.59 +input [`LM32_WORD_RNG] operand_0; // Muliplicand 22.60 +input [`LM32_WORD_RNG] operand_1; // Multiplier 22.61 + 22.62 +///////////////////////////////////////////////////// 22.63 +// Outputs 22.64 +///////////////////////////////////////////////////// 22.65 + 22.66 +output [`LM32_WORD_RNG] result; // Product of multiplication 22.67 +reg [`LM32_WORD_RNG] result; 22.68 + 22.69 +///////////////////////////////////////////////////// 22.70 +// Internal nets and registers 22.71 +///////////////////////////////////////////////////// 22.72 + 22.73 +reg [`LM32_WORD_RNG] muliplicand; 22.74 +reg [`LM32_WORD_RNG] multiplier; 22.75 +reg [`LM32_WORD_RNG] product; 22.76 + 22.77 +///////////////////////////////////////////////////// 22.78 +// Sequential logic 22.79 +///////////////////////////////////////////////////// 22.80 + 22.81 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 22.82 +begin 22.83 + if (rst_i == `TRUE) 22.84 + begin 22.85 + muliplicand <= {`LM32_WORD_WIDTH{1'b0}}; 22.86 + multiplier <= {`LM32_WORD_WIDTH{1'b0}}; 22.87 + product <= {`LM32_WORD_WIDTH{1'b0}}; 22.88 + result <= {`LM32_WORD_WIDTH{1'b0}}; 22.89 + end 22.90 + else 22.91 + begin 22.92 + if (stall_x == `FALSE) 22.93 + begin 22.94 + muliplicand <= operand_0; 22.95 + multiplier <= operand_1; 22.96 + end 22.97 + if (stall_m == `FALSE) 22.98 + product <= muliplicand * multiplier; 22.99 + result <= product; 22.100 + end 22.101 +end 22.102 + 22.103 +endmodule
23.1 diff -r 000000000000 -r cd0b58aa6f83 lm32_ram.v 23.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 23.3 +++ b/lm32_ram.v Sun Apr 04 20:40:03 2010 +0100 23.4 @@ -0,0 +1,289 @@ 23.5 +// ============================================================================= 23.6 +// COPYRIGHT NOTICE 23.7 +// Copyright 2006 (c) Lattice Semiconductor Corporation 23.8 +// ALL RIGHTS RESERVED 23.9 +// This confidential and proprietary software may be used only as authorised by 23.10 +// a licensing agreement from Lattice Semiconductor Corporation. 23.11 +// The entire notice above must be reproduced on all authorized copies and 23.12 +// copies may only be made to the extent permitted by a licensing agreement from 23.13 +// Lattice Semiconductor Corporation. 23.14 +// 23.15 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 23.16 +// 5555 NE Moore Court 408-826-6000 (other locations) 23.17 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 23.18 +// U.S.A email: techsupport@latticesemi.com 23.19 +// =============================================================================/ 23.20 +// FILE DETAILS 23.21 +// Project : LatticeMico32 23.22 +// File : lm32_ram.v 23.23 +// Title : Pseudo dual-port RAM. 23.24 +// Version : 6.1.17 23.25 +// : Initial Release 23.26 +// Version : 7.0SP2, 3.0 23.27 +// : No Change 23.28 +// Version : 3.1 23.29 +// : Options added to select EBRs (True-DP, Psuedo-DP, DQ, or 23.30 +// : Distributed RAM). 23.31 +// Version : 3.2 23.32 +// : EBRs use SYNC resets instead of ASYNC resets. 23.33 +// Version : 3.5 23.34 +// : Added read-after-write hazard resolution when using true 23.35 +// : dual-port EBRs 23.36 +// ============================================================================= 23.37 + 23.38 +`include "lm32_include.v" 23.39 + 23.40 +///////////////////////////////////////////////////// 23.41 +// Module interface 23.42 +///////////////////////////////////////////////////// 23.43 + 23.44 +module lm32_ram 23.45 + ( 23.46 + // ----- Inputs ------- 23.47 + read_clk, 23.48 + write_clk, 23.49 + reset, 23.50 + enable_read, 23.51 + read_address, 23.52 + enable_write, 23.53 + write_address, 23.54 + write_data, 23.55 + write_enable, 23.56 + // ----- Outputs ------- 23.57 + read_data 23.58 + ); 23.59 + 23.60 + /*---------------------------------------------------------------------- 23.61 + Parameters 23.62 + ----------------------------------------------------------------------*/ 23.63 + parameter data_width = 1; // Width of the data ports 23.64 + parameter address_width = 1; // Width of the address ports 23.65 + parameter RAM_IMPLEMENTATION = "AUTO"; // Implement memory in EBRs, else 23.66 + // let synthesis tool select best 23.67 + // possible solution (EBR or LUT) 23.68 + parameter RAM_TYPE = "RAM_DP"; // Type of EBR to be used 23.69 + 23.70 + /*---------------------------------------------------------------------- 23.71 + Inputs 23.72 + ----------------------------------------------------------------------*/ 23.73 + input read_clk; // Read clock 23.74 + input write_clk; // Write clock 23.75 + input reset; // Reset 23.76 + 23.77 + input enable_read; // Access enable 23.78 + input [address_width-1:0] read_address; // Read/write address 23.79 + input enable_write; // Access enable 23.80 + input [address_width-1:0] write_address;// Read/write address 23.81 + input [data_width-1:0] write_data; // Data to write to specified address 23.82 + input write_enable; // Write enable 23.83 + 23.84 + /*---------------------------------------------------------------------- 23.85 + Outputs 23.86 + ----------------------------------------------------------------------*/ 23.87 + output [data_width-1:0] read_data; // Data read from specified addess 23.88 + wire [data_width-1:0] read_data; 23.89 + 23.90 + generate 23.91 + 23.92 + if ( RAM_IMPLEMENTATION == "EBR" ) 23.93 + begin 23.94 + if ( RAM_TYPE == "RAM_DP" ) 23.95 + begin 23.96 + pmi_ram_dp 23.97 + #( 23.98 + // ----- Parameters ----- 23.99 + .pmi_wr_addr_depth(1<<address_width), 23.100 + .pmi_wr_addr_width(address_width), 23.101 + .pmi_wr_data_width(data_width), 23.102 + .pmi_rd_addr_depth(1<<address_width), 23.103 + .pmi_rd_addr_width(address_width), 23.104 + .pmi_rd_data_width(data_width), 23.105 + .pmi_regmode("noreg"), 23.106 + .pmi_gsr("enable"), 23.107 + .pmi_resetmode("sync"), 23.108 + .pmi_init_file("none"), 23.109 + .pmi_init_file_format("binary"), 23.110 + .pmi_family(`LATTICE_FAMILY), 23.111 + .module_type("pmi_ram_dp") 23.112 + ) 23.113 + lm32_ram_inst 23.114 + ( 23.115 + // ----- Inputs ----- 23.116 + .Data(write_data), 23.117 + .WrAddress(write_address), 23.118 + .RdAddress(read_address), 23.119 + .WrClock(write_clk), 23.120 + .RdClock(read_clk), 23.121 + .WrClockEn(enable_write), 23.122 + .RdClockEn(enable_read), 23.123 + .WE(write_enable), 23.124 + .Reset(reset), 23.125 + // ----- Outputs ----- 23.126 + .Q(read_data) 23.127 + ); 23.128 + end 23.129 + else 23.130 + begin 23.131 + // True Dual-Port EBR 23.132 + wire [data_width-1:0] read_data_A, read_data_B; 23.133 + reg [data_width-1:0] raw_data, raw_data_nxt; 23.134 + reg raw, raw_nxt; 23.135 + 23.136 + /*---------------------------------------------------------------------- 23.137 + Is a read being performed in the same cycle as a write? Indicate this 23.138 + event with a RAW hazard signal that is released only when a new read 23.139 + or write occurs later. 23.140 + ----------------------------------------------------------------------*/ 23.141 + always @(/*AUTOSENSE*/enable_read or enable_write 23.142 + or raw or raw_data or read_address 23.143 + or write_address or write_data 23.144 + or write_enable) 23.145 + if (// Read 23.146 + enable_read 23.147 + // Write 23.148 + && enable_write && write_enable 23.149 + // Read and write address match 23.150 + && (read_address == write_address)) 23.151 + begin 23.152 + raw_data_nxt = write_data; 23.153 + raw_nxt = 1'b1; 23.154 + end 23.155 + else 23.156 + if (raw && (enable_read == 1'b0) && (enable_write == 1'b0)) 23.157 + begin 23.158 + raw_data_nxt = raw_data; 23.159 + raw_nxt = 1'b1; 23.160 + end 23.161 + else 23.162 + begin 23.163 + raw_data_nxt = raw_data; 23.164 + raw_nxt = 1'b0; 23.165 + end 23.166 + 23.167 + // Send back write data in case of a RAW hazard; else send back 23.168 + // data from memory 23.169 + assign read_data = raw ? raw_data : read_data_B; 23.170 + 23.171 + /*---------------------------------------------------------------------- 23.172 + Sequential Logic 23.173 + ----------------------------------------------------------------------*/ 23.174 + always @(posedge read_clk) 23.175 + if (reset) 23.176 + begin 23.177 + raw_data <= #1 0; 23.178 + raw <= #1 1'b0; 23.179 + end 23.180 + else 23.181 + begin 23.182 + raw_data <= #1 raw_data_nxt; 23.183 + raw <= #1 raw_nxt; 23.184 + end 23.185 + 23.186 + pmi_ram_dp_true 23.187 + #( 23.188 + // ----- Parameters ----- 23.189 + .pmi_addr_depth_a(1<<address_width), 23.190 + .pmi_addr_width_a(address_width), 23.191 + .pmi_data_width_a(data_width), 23.192 + .pmi_addr_depth_b(1<<address_width), 23.193 + .pmi_addr_width_b(address_width), 23.194 + .pmi_data_width_b(data_width), 23.195 + .pmi_regmode_a("noreg"), 23.196 + .pmi_regmode_b("noreg"), 23.197 + .pmi_gsr("enable"), 23.198 + .pmi_resetmode("sync"), 23.199 + .pmi_init_file("none"), 23.200 + .pmi_init_file_format("binary"), 23.201 + .pmi_family(`LATTICE_FAMILY), 23.202 + .module_type("pmi_ram_dp_true") 23.203 + ) 23.204 + lm32_ram_inst 23.205 + ( 23.206 + // ----- Inputs ----- 23.207 + .DataInA(write_data), 23.208 + .DataInB(write_data), 23.209 + .AddressA(write_address), 23.210 + .AddressB(read_address), 23.211 + .ClockA(write_clk), 23.212 + .ClockB(read_clk), 23.213 + .ClockEnA(enable_write), 23.214 + .ClockEnB(enable_read), 23.215 + .WrA(write_enable), 23.216 + .WrB(`FALSE), 23.217 + .ResetA(reset), 23.218 + .ResetB(reset), 23.219 + // ----- Outputs ----- 23.220 + .QA(read_data_A), 23.221 + .QB(read_data_B) 23.222 + ); 23.223 + end 23.224 + end 23.225 + else if ( RAM_IMPLEMENTATION == "SLICE" ) 23.226 + begin 23.227 + reg [address_width-1:0] ra; // Registered read address 23.228 + 23.229 + pmi_distributed_dpram 23.230 + #( 23.231 + // ----- Parameters ----- 23.232 + .pmi_addr_depth(1<<address_width), 23.233 + .pmi_addr_width(address_width), 23.234 + .pmi_data_width(data_width), 23.235 + .pmi_regmode("noreg"), 23.236 + .pmi_init_file("none"), 23.237 + .pmi_init_file_format("binary"), 23.238 + .pmi_family(`LATTICE_FAMILY), 23.239 + .module_type("pmi_distributed_dpram") 23.240 + ) 23.241 + pmi_distributed_dpram_inst 23.242 + ( 23.243 + // ----- Inputs ----- 23.244 + .WrAddress(write_address), 23.245 + .Data(write_data), 23.246 + .WrClock(write_clk), 23.247 + .WE(write_enable), 23.248 + .WrClockEn(enable_write), 23.249 + .RdAddress(ra), 23.250 + .RdClock(read_clk), 23.251 + .RdClockEn(enable_read), 23.252 + .Reset(reset), 23.253 + // ----- Outputs ----- 23.254 + .Q(read_data) 23.255 + ); 23.256 + 23.257 + always @(posedge read_clk) 23.258 + if (enable_read) 23.259 + ra <= read_address; 23.260 + end 23.261 + 23.262 + else 23.263 + begin 23.264 + /*---------------------------------------------------------------------- 23.265 + Internal nets and registers 23.266 + ----------------------------------------------------------------------*/ 23.267 + reg [data_width-1:0] mem[0:(1<<address_width)-1]; // The RAM 23.268 + reg [address_width-1:0] ra; // Registered read address 23.269 + 23.270 + /*---------------------------------------------------------------------- 23.271 + Combinational Logic 23.272 + ----------------------------------------------------------------------*/ 23.273 + // Read port 23.274 + assign read_data = mem[ra]; 23.275 + 23.276 + /*---------------------------------------------------------------------- 23.277 + Sequential Logic 23.278 + ----------------------------------------------------------------------*/ 23.279 + // Write port 23.280 + always @(posedge write_clk) 23.281 + if ((write_enable == `TRUE) && (enable_write == `TRUE)) 23.282 + mem[write_address] <= write_data; 23.283 + 23.284 + // Register read address for use on next cycle 23.285 + always @(posedge read_clk) 23.286 + if (enable_read) 23.287 + ra <= read_address; 23.288 + 23.289 + end 23.290 + 23.291 + endgenerate 23.292 + 23.293 +endmodule
24.1 diff -r 000000000000 -r cd0b58aa6f83 lm32_shifter.v 24.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 24.3 +++ b/lm32_shifter.v Sun Apr 04 20:40:03 2010 +0100 24.4 @@ -0,0 +1,134 @@ 24.5 +// ============================================================================= 24.6 +// COPYRIGHT NOTICE 24.7 +// Copyright 2006 (c) Lattice Semiconductor Corporation 24.8 +// ALL RIGHTS RESERVED 24.9 +// This confidential and proprietary software may be used only as authorised by 24.10 +// a licensing agreement from Lattice Semiconductor Corporation. 24.11 +// The entire notice above must be reproduced on all authorized copies and 24.12 +// copies may only be made to the extent permitted by a licensing agreement from 24.13 +// Lattice Semiconductor Corporation. 24.14 +// 24.15 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 24.16 +// 5555 NE Moore Court 408-826-6000 (other locations) 24.17 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 24.18 +// U.S.A email: techsupport@latticesemi.com 24.19 +// =============================================================================/ 24.20 +// FILE DETAILS 24.21 +// Project : LatticeMico32 24.22 +// File : lm32_shifter.v 24.23 +// Title : Barrel shifter 24.24 +// Dependencies : lm32_include.v 24.25 +// Version : 6.1.17 24.26 +// : Initial Release 24.27 +// Version : 7.0SP2, 3.0 24.28 +// : No Change 24.29 +// Version : 3.1 24.30 +// : No Change 24.31 +// ============================================================================= 24.32 + 24.33 +`include "lm32_include.v" 24.34 + 24.35 +///////////////////////////////////////////////////// 24.36 +// Module interface 24.37 +///////////////////////////////////////////////////// 24.38 + 24.39 +module lm32_shifter ( 24.40 + // ----- Inputs ------- 24.41 + clk_i, 24.42 + rst_i, 24.43 + stall_x, 24.44 + direction_x, 24.45 + sign_extend_x, 24.46 + operand_0_x, 24.47 + operand_1_x, 24.48 + // ----- Outputs ------- 24.49 + shifter_result_m 24.50 + ); 24.51 + 24.52 +///////////////////////////////////////////////////// 24.53 +// Inputs 24.54 +///////////////////////////////////////////////////// 24.55 + 24.56 +input clk_i; // Clock 24.57 +input rst_i; // Reset 24.58 +input stall_x; // Stall instruction in X stage 24.59 +input direction_x; // Direction to shift 24.60 +input sign_extend_x; // Whether shift is arithmetic (1'b1) or logical (1'b0) 24.61 +input [`LM32_WORD_RNG] operand_0_x; // Operand to shift 24.62 +input [`LM32_WORD_RNG] operand_1_x; // Operand that specifies how many bits to shift by 24.63 + 24.64 +///////////////////////////////////////////////////// 24.65 +// Outputs 24.66 +///////////////////////////////////////////////////// 24.67 + 24.68 +output [`LM32_WORD_RNG] shifter_result_m; // Result of shift 24.69 +wire [`LM32_WORD_RNG] shifter_result_m; 24.70 + 24.71 +///////////////////////////////////////////////////// 24.72 +// Internal nets and registers 24.73 +///////////////////////////////////////////////////// 24.74 + 24.75 +reg direction_m; 24.76 +reg [`LM32_WORD_RNG] left_shift_result; 24.77 +reg [`LM32_WORD_RNG] right_shift_result; 24.78 +reg [`LM32_WORD_RNG] left_shift_operand; 24.79 +wire [`LM32_WORD_RNG] right_shift_operand; 24.80 +wire fill_value; 24.81 +wire [`LM32_WORD_RNG] right_shift_in; 24.82 + 24.83 +integer shift_idx_0; 24.84 +integer shift_idx_1; 24.85 + 24.86 +///////////////////////////////////////////////////// 24.87 +// Combinational Logic 24.88 +///////////////////////////////////////////////////// 24.89 + 24.90 +// Select operands - To perform a left shift, we reverse the bits and perform a right shift 24.91 +always @(*) 24.92 +begin 24.93 + for (shift_idx_0 = 0; shift_idx_0 < `LM32_WORD_WIDTH; shift_idx_0 = shift_idx_0 + 1) 24.94 + left_shift_operand[`LM32_WORD_WIDTH-1-shift_idx_0] = operand_0_x[shift_idx_0]; 24.95 +end 24.96 +assign right_shift_operand = direction_x == `LM32_SHIFT_OP_LEFT ? left_shift_operand : operand_0_x; 24.97 + 24.98 +// Determine fill value for right shift - Sign bit for arithmetic shift, or zero for logical shift 24.99 +assign fill_value = (sign_extend_x == `TRUE) && (direction_x == `LM32_SHIFT_OP_RIGHT) 24.100 + ? operand_0_x[`LM32_WORD_WIDTH-1] 24.101 + : 1'b0; 24.102 + 24.103 +// Determine bits to shift in for right shift or rotate 24.104 +assign right_shift_in = {`LM32_WORD_WIDTH{fill_value}}; 24.105 + 24.106 +// Reverse bits to get left shift result 24.107 +always @(*) 24.108 +begin 24.109 + for (shift_idx_1 = 0; shift_idx_1 < `LM32_WORD_WIDTH; shift_idx_1 = shift_idx_1 + 1) 24.110 + left_shift_result[`LM32_WORD_WIDTH-1-shift_idx_1] = right_shift_result[shift_idx_1]; 24.111 +end 24.112 + 24.113 +// Select result 24.114 +assign shifter_result_m = direction_m == `LM32_SHIFT_OP_LEFT ? left_shift_result : right_shift_result; 24.115 + 24.116 +///////////////////////////////////////////////////// 24.117 +// Sequential Logic 24.118 +///////////////////////////////////////////////////// 24.119 + 24.120 +// Perform right shift 24.121 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 24.122 +begin 24.123 + if (rst_i == `TRUE) 24.124 + begin 24.125 + right_shift_result <= {`LM32_WORD_WIDTH{1'b0}}; 24.126 + direction_m <= `FALSE; 24.127 + end 24.128 + else 24.129 + begin 24.130 + if (stall_x == `FALSE) 24.131 + begin 24.132 + right_shift_result <= {right_shift_in, right_shift_operand} >> operand_1_x[`LM32_SHIFT_RNG]; 24.133 + direction_m <= direction_x; 24.134 + end 24.135 + end 24.136 +end 24.137 + 24.138 +endmodule
25.1 diff -r 000000000000 -r cd0b58aa6f83 lm32_top.v 25.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 25.3 +++ b/lm32_top.v Sun Apr 04 20:40:03 2010 +0100 25.4 @@ -0,0 +1,395 @@ 25.5 +// ============================================================================= 25.6 +// COPYRIGHT NOTICE 25.7 +// Copyright 2006 (c) Lattice Semiconductor Corporation 25.8 +// ALL RIGHTS RESERVED 25.9 +// This confidential and proprietary software may be used only as authorised by 25.10 +// a licensing agreement from Lattice Semiconductor Corporation. 25.11 +// The entire notice above must be reproduced on all authorized copies and 25.12 +// copies may only be made to the extent permitted by a licensing agreement from 25.13 +// Lattice Semiconductor Corporation. 25.14 +// 25.15 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 25.16 +// 5555 NE Moore Court 408-826-6000 (other locations) 25.17 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 25.18 +// U.S.A email: techsupport@latticesemi.com 25.19 +// =============================================================================/ 25.20 +// FILE DETAILS 25.21 +// Project : LatticeMico32 25.22 +// File : lm32_top.v 25.23 +// Title : Top-level of CPU. 25.24 +// Dependencies : lm32_include.v 25.25 +// Version : 6.1.17 25.26 +// : removed SPI - 04/12/07 25.27 +// Version : 7.0SP2, 3.0 25.28 +// : No Change 25.29 +// Version : 3.1 25.30 +// : No Change 25.31 +// ============================================================================= 25.32 + 25.33 +`include "lm32_include.v" 25.34 + 25.35 +///////////////////////////////////////////////////// 25.36 +// Module interface 25.37 +///////////////////////////////////////////////////// 25.38 + 25.39 +module lm32_top ( 25.40 + // ----- Inputs ------- 25.41 + clk_i, 25.42 + rst_i, 25.43 + // From external devices 25.44 +`ifdef CFG_INTERRUPTS_ENABLED 25.45 + interrupt_n, 25.46 +`endif 25.47 + // From user logic 25.48 +`ifdef CFG_USER_ENABLED 25.49 + user_result, 25.50 + user_complete, 25.51 +`endif 25.52 +`ifdef CFG_IWB_ENABLED 25.53 + // Instruction Wishbone master 25.54 + I_DAT_I, 25.55 + I_ACK_I, 25.56 + I_ERR_I, 25.57 + I_RTY_I, 25.58 +`endif 25.59 + // Data Wishbone master 25.60 + D_DAT_I, 25.61 + D_ACK_I, 25.62 + D_ERR_I, 25.63 + D_RTY_I, 25.64 + // Debug Slave port WishboneInterface 25.65 + DEBUG_ADR_I, 25.66 + DEBUG_DAT_I, 25.67 + DEBUG_SEL_I, 25.68 + DEBUG_WE_I, 25.69 + DEBUG_CTI_I, 25.70 + DEBUG_BTE_I, 25.71 + DEBUG_LOCK_I, 25.72 + DEBUG_CYC_I, 25.73 + DEBUG_STB_I, 25.74 + // ----- Outputs ------- 25.75 +`ifdef CFG_USER_ENABLED 25.76 + user_valid, 25.77 + user_opcode, 25.78 + user_operand_0, 25.79 + user_operand_1, 25.80 +`endif 25.81 +`ifdef CFG_IWB_ENABLED 25.82 + // Instruction Wishbone master 25.83 + I_DAT_O, 25.84 + I_ADR_O, 25.85 + I_CYC_O, 25.86 + I_SEL_O, 25.87 + I_STB_O, 25.88 + I_WE_O, 25.89 + I_CTI_O, 25.90 + I_LOCK_O, 25.91 + I_BTE_O, 25.92 +`endif 25.93 + // Data Wishbone master 25.94 + D_DAT_O, 25.95 + D_ADR_O, 25.96 + D_CYC_O, 25.97 + D_SEL_O, 25.98 + D_STB_O, 25.99 + D_WE_O, 25.100 + D_CTI_O, 25.101 + D_LOCK_O, 25.102 + D_BTE_O, 25.103 + // Debug Slave port WishboneInterface 25.104 + DEBUG_ACK_O, 25.105 + DEBUG_ERR_O, 25.106 + DEBUG_RTY_O, 25.107 + DEBUG_DAT_O 25.108 + ); 25.109 + 25.110 +///////////////////////////////////////////////////// 25.111 +// Inputs 25.112 +///////////////////////////////////////////////////// 25.113 + 25.114 +input clk_i; // Clock 25.115 +input rst_i; // Reset 25.116 + 25.117 +`ifdef CFG_INTERRUPTS_ENABLED 25.118 +input [`LM32_INTERRUPT_RNG] interrupt_n; // Interrupt pins, active-low 25.119 +`endif 25.120 + 25.121 +`ifdef CFG_USER_ENABLED 25.122 +input [`LM32_WORD_RNG] user_result; // User-defined instruction result 25.123 +input user_complete; // Indicates the user-defined instruction result is valid 25.124 +`endif 25.125 + 25.126 +`ifdef CFG_IWB_ENABLED 25.127 +input [`LM32_WORD_RNG] I_DAT_I; // Instruction Wishbone interface read data 25.128 +input I_ACK_I; // Instruction Wishbone interface acknowledgement 25.129 +input I_ERR_I; // Instruction Wishbone interface error 25.130 +input I_RTY_I; // Instruction Wishbone interface retry 25.131 +`endif 25.132 + 25.133 +input [`LM32_WORD_RNG] D_DAT_I; // Data Wishbone interface read data 25.134 +input D_ACK_I; // Data Wishbone interface acknowledgement 25.135 +input D_ERR_I; // Data Wishbone interface error 25.136 +input D_RTY_I; // Data Wishbone interface retry 25.137 + 25.138 +input [`LM32_WORD_RNG] DEBUG_ADR_I; // Debug monitor Wishbone interface address 25.139 +input [`LM32_WORD_RNG] DEBUG_DAT_I; // Debug monitor Wishbone interface write data 25.140 +input [`LM32_BYTE_SELECT_RNG] DEBUG_SEL_I; // Debug monitor Wishbone interface byte select 25.141 +input DEBUG_WE_I; // Debug monitor Wishbone interface write enable 25.142 +input [`LM32_CTYPE_RNG] DEBUG_CTI_I; // Debug monitor Wishbone interface cycle type 25.143 +input [`LM32_BTYPE_RNG] DEBUG_BTE_I; // Debug monitor Wishbone interface burst type 25.144 +input DEBUG_LOCK_I; // Debug monitor Wishbone interface locked transfer 25.145 +input DEBUG_CYC_I; // Debug monitor Wishbone interface cycle 25.146 +input DEBUG_STB_I; // Debug monitor Wishbone interface strobe 25.147 + 25.148 +///////////////////////////////////////////////////// 25.149 +// Outputs 25.150 +///////////////////////////////////////////////////// 25.151 + 25.152 +`ifdef CFG_USER_ENABLED 25.153 +output user_valid; // Indicates that user_opcode and user_operand_* are valid 25.154 +wire user_valid; 25.155 +output [`LM32_USER_OPCODE_RNG] user_opcode; // User-defined instruction opcode 25.156 +reg [`LM32_USER_OPCODE_RNG] user_opcode; 25.157 +output [`LM32_WORD_RNG] user_operand_0; // First operand for user-defined instruction 25.158 +wire [`LM32_WORD_RNG] user_operand_0; 25.159 +output [`LM32_WORD_RNG] user_operand_1; // Second operand for user-defined instruction 25.160 +wire [`LM32_WORD_RNG] user_operand_1; 25.161 +`endif 25.162 + 25.163 +`ifdef CFG_IWB_ENABLED 25.164 +output [`LM32_WORD_RNG] I_DAT_O; // Instruction Wishbone interface write data 25.165 +wire [`LM32_WORD_RNG] I_DAT_O; 25.166 +output [`LM32_WORD_RNG] I_ADR_O; // Instruction Wishbone interface address 25.167 +wire [`LM32_WORD_RNG] I_ADR_O; 25.168 +output I_CYC_O; // Instruction Wishbone interface cycle 25.169 +wire I_CYC_O; 25.170 +output [`LM32_BYTE_SELECT_RNG] I_SEL_O; // Instruction Wishbone interface byte select 25.171 +wire [`LM32_BYTE_SELECT_RNG] I_SEL_O; 25.172 +output I_STB_O; // Instruction Wishbone interface strobe 25.173 +wire I_STB_O; 25.174 +output I_WE_O; // Instruction Wishbone interface write enable 25.175 +wire I_WE_O; 25.176 +output [`LM32_CTYPE_RNG] I_CTI_O; // Instruction Wishbone interface cycle type 25.177 +wire [`LM32_CTYPE_RNG] I_CTI_O; 25.178 +output I_LOCK_O; // Instruction Wishbone interface lock bus 25.179 +wire I_LOCK_O; 25.180 +output [`LM32_BTYPE_RNG] I_BTE_O; // Instruction Wishbone interface burst type 25.181 +wire [`LM32_BTYPE_RNG] I_BTE_O; 25.182 +`endif 25.183 + 25.184 +output [`LM32_WORD_RNG] D_DAT_O; // Data Wishbone interface write data 25.185 +wire [`LM32_WORD_RNG] D_DAT_O; 25.186 +output [`LM32_WORD_RNG] D_ADR_O; // Data Wishbone interface address 25.187 +wire [`LM32_WORD_RNG] D_ADR_O; 25.188 +output D_CYC_O; // Data Wishbone interface cycle 25.189 +wire D_CYC_O; 25.190 +output [`LM32_BYTE_SELECT_RNG] D_SEL_O; // Data Wishbone interface byte select 25.191 +wire [`LM32_BYTE_SELECT_RNG] D_SEL_O; 25.192 +output D_STB_O; // Data Wishbone interface strobe 25.193 +wire D_STB_O; 25.194 +output D_WE_O; // Data Wishbone interface write enable 25.195 +wire D_WE_O; 25.196 +output [`LM32_CTYPE_RNG] D_CTI_O; // Data Wishbone interface cycle type 25.197 +wire [`LM32_CTYPE_RNG] D_CTI_O; 25.198 +output D_LOCK_O; // Date Wishbone interface lock bus 25.199 +wire D_LOCK_O; 25.200 +output [`LM32_BTYPE_RNG] D_BTE_O; // Data Wishbone interface burst type 25.201 +wire [`LM32_BTYPE_RNG] D_BTE_O; 25.202 + 25.203 +output DEBUG_ACK_O; // Debug monitor Wishbone ack 25.204 +wire DEBUG_ACK_O; 25.205 +output DEBUG_ERR_O; // Debug monitor Wishbone error 25.206 +wire DEBUG_ERR_O; 25.207 +output DEBUG_RTY_O; // Debug monitor Wishbone retry 25.208 +wire DEBUG_RTY_O; 25.209 +output [`LM32_WORD_RNG] DEBUG_DAT_O; // Debug monitor Wishbone read data 25.210 +wire [`LM32_WORD_RNG] DEBUG_DAT_O; 25.211 + 25.212 +///////////////////////////////////////////////////// 25.213 +// Internal nets and registers 25.214 +///////////////////////////////////////////////////// 25.215 + 25.216 +`ifdef CFG_JTAG_ENABLED 25.217 +// Signals between JTAG interface and CPU 25.218 +wire [`LM32_BYTE_RNG] jtag_reg_d; 25.219 +wire [`LM32_BYTE_RNG] jtag_reg_q; 25.220 +wire jtag_update; 25.221 +wire [2:0] jtag_reg_addr_d; 25.222 +wire [2:0] jtag_reg_addr_q; 25.223 +wire jtck; 25.224 +wire jrstn; 25.225 +`endif 25.226 + 25.227 +`ifdef CFG_TRACE_ENABLED 25.228 +// PC trace signals 25.229 +wire [`LM32_PC_RNG] trace_pc; // PC to trace (address of next non-sequential instruction) 25.230 +wire trace_pc_valid; // Indicates that a new trace PC is valid 25.231 +wire trace_exception; // Indicates an exception has occured 25.232 +wire [`LM32_EID_RNG] trace_eid; // Indicates what type of exception has occured 25.233 +wire trace_eret; // Indicates an eret instruction has been executed 25.234 +`ifdef CFG_DEBUG_ENABLED 25.235 +wire trace_bret; // Indicates a bret instruction has been executed 25.236 +`endif 25.237 +`endif 25.238 + 25.239 +///////////////////////////////////////////////////// 25.240 +// Functions 25.241 +///////////////////////////////////////////////////// 25.242 + 25.243 +`include "lm32_functions.v" 25.244 +///////////////////////////////////////////////////// 25.245 +// Instantiations 25.246 +///////////////////////////////////////////////////// 25.247 + 25.248 +// LM32 CPU 25.249 +lm32_cpu cpu ( 25.250 + // ----- Inputs ------- 25.251 + .clk_i (clk_i), 25.252 +`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE 25.253 + .clk_n_i (clk_n), 25.254 +`endif 25.255 + .rst_i (rst_i), 25.256 + // From external devices 25.257 +`ifdef CFG_INTERRUPTS_ENABLED 25.258 + .interrupt_n (interrupt_n), 25.259 +`endif 25.260 + // From user logic 25.261 +`ifdef CFG_USER_ENABLED 25.262 + .user_result (user_result), 25.263 + .user_complete (user_complete), 25.264 +`endif 25.265 +`ifdef CFG_JTAG_ENABLED 25.266 + // From JTAG 25.267 + .jtag_clk (jtck), 25.268 + .jtag_update (jtag_update), 25.269 + .jtag_reg_q (jtag_reg_q), 25.270 + .jtag_reg_addr_q (jtag_reg_addr_q), 25.271 +`endif 25.272 +`ifdef CFG_IWB_ENABLED 25.273 + // Instruction Wishbone master 25.274 + .I_DAT_I (I_DAT_I), 25.275 + .I_ACK_I (I_ACK_I), 25.276 + .I_ERR_I (I_ERR_I), 25.277 + .I_RTY_I (I_RTY_I), 25.278 +`endif 25.279 + // Data Wishbone master 25.280 + .D_DAT_I (D_DAT_I), 25.281 + .D_ACK_I (D_ACK_I), 25.282 + .D_ERR_I (D_ERR_I), 25.283 + .D_RTY_I (D_RTY_I), 25.284 + // ----- Outputs ------- 25.285 +`ifdef CFG_TRACE_ENABLED 25.286 + .trace_pc (trace_pc), 25.287 + .trace_pc_valid (trace_pc_valid), 25.288 + .trace_exception (trace_exception), 25.289 + .trace_eid (trace_eid), 25.290 + .trace_eret (trace_eret), 25.291 +`ifdef CFG_DEBUG_ENABLED 25.292 + .trace_bret (trace_bret), 25.293 +`endif 25.294 +`endif 25.295 +`ifdef CFG_JTAG_ENABLED 25.296 + .jtag_reg_d (jtag_reg_d), 25.297 + .jtag_reg_addr_d (jtag_reg_addr_d), 25.298 +`endif 25.299 +`ifdef CFG_USER_ENABLED 25.300 + .user_valid (user_valid), 25.301 + .user_opcode (user_opcode), 25.302 + .user_operand_0 (user_operand_0), 25.303 + .user_operand_1 (user_operand_1), 25.304 +`endif 25.305 +`ifdef CFG_IWB_ENABLED 25.306 + // Instruction Wishbone master 25.307 + .I_DAT_O (I_DAT_O), 25.308 + .I_ADR_O (I_ADR_O), 25.309 + .I_CYC_O (I_CYC_O), 25.310 + .I_SEL_O (I_SEL_O), 25.311 + .I_STB_O (I_STB_O), 25.312 + .I_WE_O (I_WE_O), 25.313 + .I_CTI_O (I_CTI_O), 25.314 + .I_LOCK_O (I_LOCK_O), 25.315 + .I_BTE_O (I_BTE_O), 25.316 + `endif 25.317 + // Data Wishbone master 25.318 + .D_DAT_O (D_DAT_O), 25.319 + .D_ADR_O (D_ADR_O), 25.320 + .D_CYC_O (D_CYC_O), 25.321 + .D_SEL_O (D_SEL_O), 25.322 + .D_STB_O (D_STB_O), 25.323 + .D_WE_O (D_WE_O), 25.324 + .D_CTI_O (D_CTI_O), 25.325 + .D_LOCK_O (D_LOCK_O), 25.326 + .D_BTE_O (D_BTE_O) 25.327 + ); 25.328 + 25.329 + wire TRACE_ACK_O; 25.330 + wire [`LM32_WORD_RNG] TRACE_DAT_O; 25.331 +`ifdef CFG_TRACE_ENABLED 25.332 + lm32_trace trace_module (.clk_i (clk_i), 25.333 + .rst_i (rst_i), 25.334 + .stb_i (DEBUG_STB_I & DEBUG_ADR_I[13]), 25.335 + .we_i (DEBUG_WE_I), 25.336 + .sel_i (DEBUG_SEL_I), 25.337 + .dat_i (DEBUG_DAT_I), 25.338 + .adr_i (DEBUG_ADR_I), 25.339 + .trace_pc (trace_pc), 25.340 + .trace_eid (trace_eid), 25.341 + .trace_eret (trace_eret), 25.342 + .trace_bret (trace_bret), 25.343 + .trace_pc_valid (trace_pc_valid), 25.344 + .trace_exception (trace_exception), 25.345 + .ack_o (TRACE_ACK_O), 25.346 + .dat_o (TRACE_DAT_O)); 25.347 +`else 25.348 + assign TRACE_ACK_O = 0; 25.349 + assign TRACE_DAT_O = 0; 25.350 +`endif 25.351 +`ifdef DEBUG_ROM 25.352 + wire ROM_ACK_O; 25.353 + wire [`LM32_WORD_RNG] ROM_DAT_O; 25.354 + 25.355 + assign DEBUG_ACK_O = DEBUG_ADR_I[13] ? TRACE_ACK_O : ROM_ACK_O; 25.356 + assign DEBUG_DAT_O = DEBUG_ADR_I[13] ? TRACE_DAT_O : ROM_DAT_O; 25.357 + 25.358 + // ROM monitor 25.359 + lm32_monitor debug_rom ( 25.360 + // ----- Inputs ------- 25.361 + .clk_i (clk_i), 25.362 + .rst_i (rst_i), 25.363 + .MON_ADR_I (DEBUG_ADR_I), 25.364 + .MON_STB_I (DEBUG_STB_I & ~DEBUG_ADR_I[13]), 25.365 + .MON_CYC_I (DEBUG_CYC_I & ~DEBUG_ADR_I[13]), 25.366 + .MON_WE_I (DEBUG_WE_I), 25.367 + .MON_SEL_I (DEBUG_SEL_I), 25.368 + .MON_DAT_I (DEBUG_DAT_I), 25.369 + .MON_CTI_I (DEBUG_CTI_I), 25.370 + .MON_BTE_I (DEBUG_BTE_I), 25.371 + .MON_LOCK_I (DEBUG_LOCK_I), 25.372 + // ----- Outputs ------ 25.373 + .MON_RTY_O (DEBUG_RTY_O), 25.374 + .MON_ERR_O (DEBUG_ERR_O), 25.375 + .MON_ACK_O (ROM_ACK_O), 25.376 + .MON_DAT_O (ROM_DAT_O) 25.377 + ); 25.378 +`endif 25.379 + 25.380 +`ifdef CFG_JTAG_ENABLED 25.381 +// JTAG cores 25.382 +jtag_cores jtag_cores ( 25.383 + // ----- Inputs ----- 25.384 +`ifdef INCLUDE_LM32 25.385 + .reg_d (jtag_reg_d), 25.386 + .reg_addr_d (jtag_reg_addr_d), 25.387 +`endif 25.388 + // ----- Outputs ----- 25.389 +`ifdef INCLUDE_LM32 25.390 + .reg_update (jtag_update), 25.391 + .reg_q (jtag_reg_q), 25.392 + .reg_addr_q (jtag_reg_addr_q), 25.393 +`endif 25.394 + .jtck (jtck), 25.395 + .jrstn (jrstn) 25.396 + ); 25.397 +`endif 25.398 + 25.399 +endmodule
26.1 diff -r 000000000000 -r cd0b58aa6f83 lm32_trace.v 26.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 26.3 +++ b/lm32_trace.v Sun Apr 04 20:40:03 2010 +0100 26.4 @@ -0,0 +1,298 @@ 26.5 +// ============================================================================= 26.6 +// COPYRIGHT NOTICE 26.7 +// Copyright 2006 (c) Lattice Semiconductor Corporation 26.8 +// ALL RIGHTS RESERVED 26.9 +// This confidential and proprietary software may be used only as authorised by 26.10 +// a licensing agreement from Lattice Semiconductor Corporation. 26.11 +// The entire notice above must be reproduced on all authorized copies and 26.12 +// copies may only be made to the extent permitted by a licensing agreement from 26.13 +// Lattice Semiconductor Corporation. 26.14 +// 26.15 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 26.16 +// 5555 NE Moore Court 408-826-6000 (other locations) 26.17 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 26.18 +// U.S.A email: techsupport@latticesemi.com 26.19 +// =============================================================================/ 26.20 +// FILE DETAILS 26.21 +// Project : LatticeMico32 26.22 +// File : lm32_trace.v 26.23 +// Title : PC Trace and associated logic. 26.24 +// Dependencies : lm32_include.v, lm32_functions.v 26.25 +// Version : 6.1.17 26.26 +// : Initial Release 26.27 +// Version : 7.0SP2, 3.0 26.28 +// : No Change 26.29 +// Version : 3.1 26.30 +// : No Change 26.31 +// ============================================================================= 26.32 + 26.33 +`include "lm32_include.v" 26.34 +`include "system_conf.v" 26.35 + 26.36 +`ifdef CFG_TRACE_ENABLED 26.37 +module lm32_trace( 26.38 + // ----- Inputs ------- 26.39 + clk_i, 26.40 + rst_i, 26.41 + stb_i, 26.42 + we_i, 26.43 + sel_i, 26.44 + dat_i, 26.45 + adr_i, 26.46 + 26.47 + trace_pc, 26.48 + trace_eid, 26.49 + trace_eret, 26.50 + trace_bret, 26.51 + trace_pc_valid, 26.52 + trace_exception, 26.53 + 26.54 + // -- outputs 26.55 + ack_o, 26.56 + dat_o); 26.57 + 26.58 + input clk_i; 26.59 + input rst_i; 26.60 + input stb_i; 26.61 + input we_i; 26.62 + input [3:0] sel_i; 26.63 + input [`LM32_WORD_RNG] dat_i; 26.64 + input [`LM32_WORD_RNG] adr_i; 26.65 + input [`LM32_PC_RNG] trace_pc; 26.66 + input [`LM32_EID_RNG] trace_eid; 26.67 + input trace_eret; 26.68 + input trace_bret; 26.69 + input trace_pc_valid; 26.70 + input trace_exception; 26.71 + // -- outputs 26.72 + output ack_o; 26.73 + output [`LM32_WORD_RNG] dat_o; 26.74 + reg ovrflw; 26.75 + 26.76 + function integer clogb2; 26.77 + input [31:0] value; 26.78 + begin 26.79 + for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) 26.80 + value = value >> 1; 26.81 + end 26.82 + endfunction 26.83 + 26.84 + // instantiate the trace memory 26.85 + parameter mem_data_width = `LM32_PC_WIDTH; 26.86 + parameter mem_addr_width = clogb2(`CFG_TRACE_DEPTH-1); 26.87 + 26.88 + wire [`LM32_PC_RNG] trace_dat_o; 26.89 + wire [mem_addr_width-1:0] trace_raddr; 26.90 + wire [mem_addr_width-1:0] trace_waddr; 26.91 + reg trace_we; 26.92 + wire trace_be, trace_last; 26.93 + wire rw_creg = adr_i[12]; 26.94 + 26.95 + lm32_ram #(.data_width (mem_data_width), 26.96 + .address_width (mem_addr_width)) 26.97 + trace_mem (.read_clk (clk_i), 26.98 + .write_clk (clk_i), 26.99 + .reset (rst_i), 26.100 + .read_address (adr_i[mem_addr_width+1:2]), 26.101 + .write_address (trace_waddr), 26.102 + .enable_read (`TRUE), 26.103 + .enable_write ((trace_we | trace_be) & trace_pc_valid & !trace_last), 26.104 + .write_enable (`TRUE), 26.105 + .write_data (trace_pc), 26.106 + .read_data (trace_dat_o)); 26.107 + 26.108 + // trigger type & stop type 26.109 + // trig_type [0] = start capture when bret 26.110 + // trig_type [1] = start capture when eret 26.111 + // trig_type [2] = start capture when PC within a range 26.112 + // trig_type [3] = start when an exception happens (other than breakpoint) 26.113 + // trig_type [4] = start when a breakpoint exception happens 26.114 + 26.115 + 26.116 + reg [4:0] trig_type; // at address 0 26.117 + reg [4:0] stop_type; // at address 16 26.118 + reg [`LM32_WORD_RNG] trace_len; // at address 4 26.119 + reg [`LM32_WORD_RNG] pc_low; // at address 8 26.120 + reg [`LM32_WORD_RNG] pc_high; // at address 12 26.121 + reg trace_start,trace_stop; 26.122 + reg ack_o; 26.123 + reg mem_valid; 26.124 + reg [`LM32_WORD_RNG] reg_dat_o; 26.125 + reg started; 26.126 + reg capturing; 26.127 + assign dat_o = (rw_creg ? reg_dat_o : trace_dat_o); 26.128 + 26.129 + initial begin 26.130 + trig_type <= 0; 26.131 + stop_type <= 0; 26.132 + trace_len <= 0; 26.133 + pc_low <= 0; 26.134 + pc_high <= 0; 26.135 + trace_start <= 0; 26.136 + trace_stop <= 0; 26.137 + ack_o <= 0; 26.138 + reg_dat_o <= 0; 26.139 + mem_valid <= 0; 26.140 + started <= 0; 26.141 + capturing <= 0; 26.142 + end 26.143 + 26.144 + // the host side control 26.145 + always @(posedge clk_i `CFG_RESET_SENSITIVITY) 26.146 + begin 26.147 + if (rst_i == `TRUE) begin 26.148 + trig_type <= 0; 26.149 + trace_stop <= 0; 26.150 + trace_start <= 0; 26.151 + pc_low <= 0; 26.152 + pc_high <= 0; 26.153 + ack_o <= 0; 26.154 + end else begin 26.155 + if (stb_i == `TRUE && ack_o == `FALSE) begin 26.156 + if (rw_creg) begin // control register access 26.157 + ack_o <= `TRUE; 26.158 + if (we_i == `TRUE) begin 26.159 + case ({adr_i[11:2],2'b0}) 26.160 + // write to trig type 26.161 + 12'd0: 26.162 + begin 26.163 + if (sel_i[0]) begin 26.164 + trig_type[4:0] <= dat_i[4:0]; 26.165 + end 26.166 + if (sel_i[3]) begin 26.167 + trace_start <= dat_i[31]; 26.168 + trace_stop <= dat_i[30]; 26.169 + end 26.170 + end 26.171 + 12'd8: 26.172 + begin 26.173 + if (sel_i[3]) pc_low[31:24] <= dat_i[31:24]; 26.174 + if (sel_i[2]) pc_low[23:16] <= dat_i[23:16]; 26.175 + if (sel_i[1]) pc_low[15:8] <= dat_i[15:8]; 26.176 + if (sel_i[0]) pc_low[7:0] <= dat_i[7:0]; 26.177 + end 26.178 + 12'd12: 26.179 + begin 26.180 + if (sel_i[3]) pc_high[31:24] <= dat_i[31:24]; 26.181 + if (sel_i[2]) pc_high[23:16] <= dat_i[23:16]; 26.182 + if (sel_i[1]) pc_high[15:8] <= dat_i[15:8]; 26.183 + if (sel_i[0]) pc_high[7:0] <= dat_i[7:0]; 26.184 + end 26.185 + 12'd16: 26.186 + begin 26.187 + if (sel_i[0])begin 26.188 + stop_type[4:0] <= dat_i[4:0]; 26.189 + end 26.190 + end 26.191 + endcase 26.192 + end else begin // read control registers 26.193 + case ({adr_i[11:2],2'b0}) 26.194 + // read the trig type 26.195 + 12'd0: 26.196 + reg_dat_o <= {22'b1,capturing,mem_valid,ovrflw,trace_we,started,trig_type}; 26.197 + 12'd4: 26.198 + reg_dat_o <= trace_len; 26.199 + 12'd8: 26.200 + reg_dat_o <= pc_low; 26.201 + 12'd12: 26.202 + reg_dat_o <= pc_high; 26.203 + default: 26.204 + reg_dat_o <= {27'b0,stop_type}; 26.205 + endcase 26.206 + end // else: !if(we_i == `TRUE) 26.207 + end else // read / write memory 26.208 + if (we_i == `FALSE) begin 26.209 + ack_o <= `TRUE; 26.210 + end else 26.211 + ack_o <= `FALSE; 26.212 + // not allowed to write to trace memory 26.213 + end else begin // if (stb_i == `TRUE) 26.214 + trace_start <= `FALSE; 26.215 + trace_stop <= `FALSE; 26.216 + ack_o <= `FALSE; 26.217 + end // else: !if(stb_i == `TRUE) 26.218 + end // else: !if(rst_i == `TRUE) 26.219 + end 26.220 + 26.221 + wire [`LM32_WORD_RNG] trace_pc_tmp = {trace_pc,2'b0}; 26.222 + 26.223 + // trace state machine 26.224 + reg [2:0] tstate; 26.225 + wire pc_in_range = {trace_pc,2'b0} >= pc_low && 26.226 + {trace_pc,2'b0} <= pc_high; 26.227 + 26.228 + assign trace_waddr = trace_len[mem_addr_width-1:0]; 26.229 + 26.230 + wire trace_begin = ((trig_type[0] & trace_bret) || 26.231 + (trig_type[1] & trace_eret) || 26.232 + (trig_type[2] & pc_in_range & trace_pc_valid) || 26.233 + (trig_type[3] & trace_exception & (trace_eid != `LM32_EID_BREAKPOINT)) || 26.234 + (trig_type[4] & trace_exception & (trace_eid == `LM32_EID_BREAKPOINT)) 26.235 + ); 26.236 + 26.237 + 26.238 + wire trace_end = (trace_stop || 26.239 + (stop_type[0] & trace_bret) || 26.240 + (stop_type[1] & trace_eret) || 26.241 + (stop_type[2] & !pc_in_range & trace_pc_valid) || 26.242 + (stop_type[3] & trace_exception & (trace_eid != `LM32_EID_BREAKPOINT)) || 26.243 + (stop_type[4] & trace_exception & (trace_eid == `LM32_EID_BREAKPOINT)) 26.244 + ); 26.245 + 26.246 + assign trace_be = (trace_begin & (tstate == 3'd1)); 26.247 + assign trace_last = (trace_stop & (tstate == 3'd2)); 26.248 + 26.249 + always @(posedge clk_i `CFG_RESET_SENSITIVITY) 26.250 + begin 26.251 + if (rst_i == `TRUE) begin 26.252 + tstate <= 0; 26.253 + trace_we <= 0; 26.254 + trace_len <= 0; 26.255 + ovrflw <= `FALSE; 26.256 + mem_valid <= 0; 26.257 + started <= 0; 26.258 + capturing <= 0; 26.259 + end else begin 26.260 + case (tstate) 26.261 + 3'd0: 26.262 + // start capture 26.263 + if (trace_start) begin 26.264 + tstate <= 3'd1; 26.265 + mem_valid <= 0; 26.266 + started <= 1; 26.267 + end 26.268 + 3'd1: 26.269 + begin 26.270 + // wait for trigger 26.271 + if (trace_begin) begin 26.272 + capturing <= 1; 26.273 + tstate <= 3'd2; 26.274 + trace_we <= `TRUE; 26.275 + trace_len <= 0; 26.276 + ovrflw <= `FALSE; 26.277 + end 26.278 + end // case: 3'd1 26.279 + 26.280 + 3'd2: 26.281 + begin 26.282 + if (trace_pc_valid) begin 26.283 + if (trace_len[mem_addr_width]) 26.284 + trace_len <= 0; 26.285 + else 26.286 + trace_len <= trace_len + 1; 26.287 + end 26.288 + if (!ovrflw) ovrflw <= trace_len[mem_addr_width]; 26.289 + // wait for stop condition 26.290 + if (trace_end) begin 26.291 + tstate <= 3'd0; 26.292 + trace_we <= 0; 26.293 + mem_valid <= 1; 26.294 + started <= 0; 26.295 + capturing <= 0; 26.296 + end 26.297 + end // case: 3'd2 26.298 + endcase 26.299 + end // else: !if(rst_i == `TRUE) 26.300 + end 26.301 +endmodule 26.302 +`endif
27.1 diff -r 000000000000 -r cd0b58aa6f83 spiprog.v 27.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 27.3 +++ b/spiprog.v Sun Apr 04 20:40:03 2010 +0100 27.4 @@ -0,0 +1,193 @@ 27.5 +// ============================================================================= 27.6 +// COPYRIGHT NOTICE 27.7 +// Copyright 2006 (c) Lattice Semiconductor Corporation 27.8 +// ALL RIGHTS RESERVED 27.9 +// This confidential and proprietary software may be used only as authorised by 27.10 +// a licensing agreement from Lattice Semiconductor Corporation. 27.11 +// The entire notice above must be reproduced on all authorized copies and 27.12 +// copies may only be made to the extent permitted by a licensing agreement from 27.13 +// Lattice Semiconductor Corporation. 27.14 +// 27.15 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 27.16 +// 5555 NE Moore Court 408-826-6000 (other locations) 27.17 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 27.18 +// U.S.A email: techsupport@latticesemi.com 27.19 +// =============================================================================/ 27.20 +// FILE DETAILS 27.21 +// Project : LatticeMico32 27.22 +// File : SPIPROG.v 27.23 +// This module contains the ER2 regsiters of SPI Serial FLASH programmer IP 27.24 +// core. There are only three ER2 registers, one control register and two 27.25 +// data registers, in this IP core. The control register is a 8-bit wide 27.26 +// register for selecting which data register will be accessed when the 27.27 +// Control/Data# bit in ER1 register is low. Data register 0 is a readonly 27.28 +// ID register. It is composed of three register fields -- an 8-bit 27.29 +// "implementer", a 16-bit "IP_functionality", and a 12-bit "revision". 27.30 +// Data register 1 is a variable length register for sending commands to or 27.31 +// receiving readback data from the SPI Serial FLASH device. 27.32 +// Dependencies : None 27.33 +// Version : 6.1.17 27.34 +// 1. Reduced the the ID register (DR0) length from 36 bits to 8 bits. 27.35 +// 2. Same as TYPEA and TYPEB modules, use falling edge clock 27.36 +// for all TCK Flip-Flops. 27.37 +// 3. Added 7 delay Flip-Flops so that the DR1 readback data from 27.38 +// SPI Serial FLASH is in the byte boundary. 27.39 +// Version : 7.0SP2, 3.0 27.40 +// : No Change 27.41 +// Version : 3.1 27.42 +// : No Change 27.43 +// ============================================================================= 27.44 +//--------------------------------------------------------------------------- 27.45 +// 27.46 +//Name : SPIPROG.v 27.47 +// 27.48 +//Description: 27.49 +// 27.50 +// This module contains the ER2 regsiters of SPI Serial FLASH programmer IP 27.51 +// core. There are only three ER2 registers, one control register and two 27.52 +// data registers, in this IP core. The control register is a 8-bit wide 27.53 +// register for selecting which data register will be accessed when the 27.54 +// Control/Data# bit in ER1 register is low. Data register 0 is a readonly 27.55 +// ID register. It is composed of three register fields -- an 8-bit 27.56 +// "implementer", a 16-bit "IP_functionality", and a 12-bit "revision". 27.57 +// Data register 1 is a variable length register for sending commands to or 27.58 +// receiving readback data from the SPI Serial FLASH device. 27.59 +// 27.60 +//$Log: spiprog.vhd,v $ 27.61 +//Revision 1.2 2004-09-09 11:43:26-07 jhsin 27.62 +//1. Reduced the the ID register (DR0) length from 36 bits to 8 bits. 27.63 +//2. Same as TYPEA and TYPEB modules, use falling edge clock 27.64 +// for all TCK Flip-Flops. 27.65 +// 27.66 +//Revision 1.1 2004-08-12 13:22:05-07 jhsin 27.67 +//Added 7 delay Flip-Flops so that the DR1 readback data from SPI Serial FLASH is in the byte boundary. 27.68 +// 27.69 +//Revision 1.0 2004-08-03 18:35:56-07 jhsin 27.70 +//Initial revision 27.71 +// 27.72 +// 27.73 + 27.74 +module SPIPROG (input JTCK , 27.75 + input JTDI , 27.76 + output JTDO2 , 27.77 + input JSHIFT , 27.78 + input JUPDATE , 27.79 + input JRSTN , 27.80 + input JCE2 , 27.81 + input SPIPROG_ENABLE , 27.82 + input CONTROL_DATAN , 27.83 + output SPI_C , 27.84 + output SPI_D , 27.85 + output SPI_SN , 27.86 + input SPI_Q); 27.87 + 27.88 + wire er2Cr_enable ; 27.89 + wire er2Dr0_enable; 27.90 + wire er2Dr1_enable; 27.91 + 27.92 + wire tdo_er2Cr ; 27.93 + wire tdo_er2Dr0; 27.94 + wire tdo_er2Dr1; 27.95 + 27.96 + wire [7:0] encodedDrSelBits ; 27.97 + wire [8:0] er2CrTdiBit ; 27.98 + wire [8:0] er2Dr0TdiBit ; 27.99 + 27.100 + wire captureDrER2; 27.101 + reg spi_s ; 27.102 + reg [6:0] spi_q_dly; 27.103 + 27.104 + wire [7:0] ip_functionality_id; 27.105 + 27.106 + genvar i; 27.107 + 27.108 + // ------ Control Register 0 ------ 27.109 + 27.110 + assign er2Cr_enable = JCE2 & SPIPROG_ENABLE & CONTROL_DATAN; 27.111 + 27.112 + assign tdo_er2Cr = er2CrTdiBit[0]; 27.113 + 27.114 + // CR_BIT0_BIT7 27.115 + generate 27.116 + for(i=0; i<=7; i=i+1) 27.117 + begin:CR_BIT0_BIT7 27.118 + TYPEA BIT_N (.CLK (JTCK), 27.119 + .RESET_N (JRSTN), 27.120 + .CLKEN (er2Cr_enable), 27.121 + .TDI (er2CrTdiBit[i + 1]), 27.122 + .TDO (er2CrTdiBit[i]), 27.123 + .DATA_OUT (encodedDrSelBits[i]), 27.124 + .DATA_IN (encodedDrSelBits[i]), 27.125 + .CAPTURE_DR (captureDrER2), 27.126 + .UPDATE_DR (JUPDATE)); 27.127 + end 27.128 + endgenerate // CR_BIT0_BIT7 27.129 + 27.130 + assign er2CrTdiBit[8] = JTDI; 27.131 + 27.132 +// ------ Data Register 0 ------ 27.133 + assign er2Dr0_enable = (JCE2 & SPIPROG_ENABLE & ~CONTROL_DATAN & (encodedDrSelBits == 8'b00000000)) ? 1'b1 : 1'b0; 27.134 + 27.135 + assign tdo_er2Dr0 = er2Dr0TdiBit[0]; 27.136 + 27.137 + assign ip_functionality_id = 8'b00000001; //-- SPI Serial FLASH Programmer (0x01) 27.138 + 27.139 +// DR0_BIT0_BIT7 27.140 + generate 27.141 + for(i=0; i<=7; i=i+1) 27.142 + begin:DR0_BIT0_BIT7 27.143 + TYPEB BIT_N (.CLK (JTCK), 27.144 + .RESET_N (JRSTN), 27.145 + .CLKEN (er2Dr0_enable), 27.146 + .TDI (er2Dr0TdiBit[i + 1]), 27.147 + .TDO (er2Dr0TdiBit[i]), 27.148 + .DATA_IN (ip_functionality_id[i]), 27.149 + .CAPTURE_DR (captureDrER2)); 27.150 + end 27.151 + endgenerate // DR0_BIT0_BIT7 27.152 + 27.153 + assign er2Dr0TdiBit[8] = JTDI; 27.154 + 27.155 +// ------ Data Register 1 ------ 27.156 + 27.157 + assign er2Dr1_enable = (JCE2 & JSHIFT & SPIPROG_ENABLE & ~CONTROL_DATAN & (encodedDrSelBits == 8'b00000001)) ? 1'b1 : 1'b0; 27.158 + 27.159 + assign SPI_C = ~ (JTCK & er2Dr1_enable & spi_s); 27.160 + 27.161 + assign SPI_D = JTDI & er2Dr1_enable; 27.162 + 27.163 + // SPI_S_Proc 27.164 + always @(negedge JTCK or negedge JRSTN) 27.165 + begin 27.166 + if (~JRSTN) 27.167 + spi_s <= 1'b0; 27.168 + else 27.169 + if (JUPDATE) 27.170 + spi_s <= 1'b0; 27.171 + else 27.172 + spi_s <= er2Dr1_enable; 27.173 + end 27.174 + 27.175 + assign SPI_SN = ~spi_s; 27.176 + 27.177 + // SPI_Q_Proc 27.178 + always @(negedge JTCK or negedge JRSTN) 27.179 + begin 27.180 + if (~JRSTN) 27.181 + spi_q_dly <= 'b0; 27.182 + else 27.183 + if (er2Dr1_enable) 27.184 + spi_q_dly <= {spi_q_dly[5:0],SPI_Q}; 27.185 + end 27.186 + 27.187 + assign tdo_er2Dr1 = spi_q_dly[6]; 27.188 + 27.189 + // ------ JTDO2 MUX ------ 27.190 + 27.191 + assign JTDO2 = CONTROL_DATAN ? tdo_er2Cr : 27.192 + (encodedDrSelBits == 8'b00000000) ? tdo_er2Dr0 : 27.193 + (encodedDrSelBits == 8'b00000001) ? tdo_er2Dr1 : 1'b0; 27.194 + 27.195 + assign captureDrER2 = ~JSHIFT & JCE2; 27.196 + 27.197 +endmodule
28.1 diff -r 000000000000 -r cd0b58aa6f83 typea.v 28.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 28.3 +++ b/typea.v Sun Apr 04 20:40:03 2010 +0100 28.4 @@ -0,0 +1,81 @@ 28.5 +// ============================================================================= 28.6 +// COPYRIGHT NOTICE 28.7 +// Copyright 2006 (c) Lattice Semiconductor Corporation 28.8 +// ALL RIGHTS RESERVED 28.9 +// This confidential and proprietary software may be used only as authorised by 28.10 +// a licensing agreement from Lattice Semiconductor Corporation. 28.11 +// The entire notice above must be reproduced on all authorized copies and 28.12 +// copies may only be made to the extent permitted by a licensing agreement from 28.13 +// Lattice Semiconductor Corporation. 28.14 +// 28.15 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 28.16 +// 5555 NE Moore Court 408-826-6000 (other locations) 28.17 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 28.18 +// U.S.A email: techsupport@latticesemi.com 28.19 +// =============================================================================/ 28.20 +// FILE DETAILS 28.21 +// Project : LatticeMico32 28.22 +// File : TYPEA.v 28.23 +// Description: 28.24 +// This is one of the two types of cells that are used to create ER1/ER2 28.25 +// register bits. 28.26 +// Dependencies : None 28.27 +// Version : 6.1.17 28.28 +// The SHIFT_DR_CAPTURE_DR and ENABLE_ER1/2 signals of the 28.29 +// dedicate logic JTAG_PORT didn't act as what their names implied. 28.30 +// The SHIFT_DR_CAPTURE_DR actually acts as SHIFT_DR. 28.31 +// The ENABLE_ER1/2 actually acts as SHIFT_DR_CAPTURE_DR. 28.32 +// These had caused a lot of headaches for a long time and now they are 28.33 +// fixed by: 28.34 +// (1) Use SHIFT_DR_CAPTURE_DR and ENABLE_ER1/2 to create 28.35 +// CAPTURE_DR for all typeA, typeB bits in the ER1, ER2 registers. 28.36 +// (2) Use ENABLE_ER1 or the enESR, enCSR, enBAR (these 3 signals 28.37 +// have the same waveform of ENABLE_ER2) directly to be the CLKEN 28.38 +// of all typeA, typeB bits in the ER1, ER2 registers. 28.39 +// (3) Modify typea.vhd to use only UPDATE_DR signal for the clock enable 28.40 +// of the holding flip-flop. 28.41 +// These changes caused ispTracy.vhd and cge.dat changes and the new 28.42 +// CGE.exe version will be 1.3.5. 28.43 +// Version : 7.0SP2, 3.0 28.44 +// : No Change 28.45 +// Version : 3.1 28.46 +// : No Change 28.47 +// ============================================================================= 28.48 +module TYPEA( 28.49 + input CLK, 28.50 + input RESET_N, 28.51 + input CLKEN, 28.52 + input TDI, 28.53 + output TDO, 28.54 + output reg DATA_OUT, 28.55 + input DATA_IN, 28.56 + input CAPTURE_DR, 28.57 + input UPDATE_DR 28.58 + ); 28.59 + 28.60 + reg tdoInt; 28.61 + 28.62 + 28.63 + always @ (negedge CLK or negedge RESET_N) 28.64 + begin 28.65 + if (RESET_N == 1'b0) 28.66 + tdoInt <= 1'b0; 28.67 + else if (CLK == 1'b0) 28.68 + if (CLKEN == 1'b1) 28.69 + if (CAPTURE_DR == 1'b0) 28.70 + tdoInt <= TDI; 28.71 + else 28.72 + tdoInt <= DATA_IN; 28.73 + end 28.74 + 28.75 + assign TDO = tdoInt; 28.76 + 28.77 + always @ (negedge CLK or negedge RESET_N) 28.78 + begin 28.79 + if (RESET_N == 1'b0) 28.80 + DATA_OUT <= 1'b0; 28.81 + else if (CLK == 1'b0) 28.82 + if (UPDATE_DR == 1'b1) 28.83 + DATA_OUT <= tdoInt; 28.84 + end 28.85 +endmodule
29.1 diff -r 000000000000 -r cd0b58aa6f83 typeb.v 29.2 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 29.3 +++ b/typeb.v Sun Apr 04 20:40:03 2010 +0100 29.4 @@ -0,0 +1,58 @@ 29.5 +// ============================================================================= 29.6 +// COPYRIGHT NOTICE 29.7 +// Copyright 2006 (c) Lattice Semiconductor Corporation 29.8 +// ALL RIGHTS RESERVED 29.9 +// This confidential and proprietary software may be used only as authorised by 29.10 +// a licensing agreement from Lattice Semiconductor Corporation. 29.11 +// The entire notice above must be reproduced on all authorized copies and 29.12 +// copies may only be made to the extent permitted by a licensing agreement from 29.13 +// Lattice Semiconductor Corporation. 29.14 +// 29.15 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 29.16 +// 5555 NE Moore Court 408-826-6000 (other locations) 29.17 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 29.18 +// U.S.A email: techsupport@latticesemi.com 29.19 +// =============================================================================/ 29.20 +// FILE DETAILS 29.21 +// Project : LatticeMico32 29.22 +// File : TYPEB.v 29.23 +// Description: 29.24 +// This is one of the two types of cells that are used to create ER1/ER2 29.25 +// register bits. 29.26 +// Dependencies : None 29.27 +// Version : 6.1.17 29.28 +// Modified typeb module to remove redundant DATA_OUT port. 29.29 +// Version : 7.0SP2, 3.0 29.30 +// : No Change 29.31 +// Version : 3.1 29.32 +// : No Change 29.33 +// ============================================================================= 29.34 +module TYPEB 29.35 + ( 29.36 + input CLK, 29.37 + input RESET_N, 29.38 + input CLKEN, 29.39 + input TDI, 29.40 + output TDO, 29.41 + input DATA_IN, 29.42 + input CAPTURE_DR 29.43 + ); 29.44 + 29.45 + reg tdoInt; 29.46 + 29.47 + always @ (negedge CLK or negedge RESET_N) 29.48 + begin 29.49 + if (RESET_N== 1'b0) 29.50 + tdoInt <= 1'b0; 29.51 + else if (CLK == 1'b0) 29.52 + if (CLKEN==1'b1) 29.53 + if (CAPTURE_DR==1'b0) 29.54 + tdoInt <= TDI; 29.55 + else 29.56 + tdoInt <= DATA_IN; 29.57 + end 29.58 + 29.59 + assign TDO = tdoInt; 29.60 + 29.61 +endmodule 29.62 +