1.1 --- a/lm32_trace.v Sat Aug 06 00:02:46 2011 +0100 1.2 +++ b/lm32_trace.v Sat Aug 06 01:26:56 2011 +0100 1.3 @@ -146,65 +146,65 @@ 1.4 assign dat_o = (rw_creg ? reg_dat_o : trace_dat_o); 1.5 1.6 initial begin 1.7 - trig_type <= #1 0; 1.8 - stop_type <= #1 0; 1.9 - trace_len <= #1 0; 1.10 - pc_low <= #1 0; 1.11 - pc_high <= #1 0; 1.12 - trace_start <= #1 0; 1.13 - trace_stop <= #1 0; 1.14 - ack_o <= #1 0; 1.15 - reg_dat_o <= #1 0; 1.16 - mem_valid <= #1 0; 1.17 - started <= #1 0; 1.18 - capturing <= #1 0; 1.19 + trig_type <= 0; 1.20 + stop_type <= 0; 1.21 + trace_len <= 0; 1.22 + pc_low <= 0; 1.23 + pc_high <= 0; 1.24 + trace_start <= 0; 1.25 + trace_stop <= 0; 1.26 + ack_o <= 0; 1.27 + reg_dat_o <= 0; 1.28 + mem_valid <= 0; 1.29 + started <= 0; 1.30 + capturing <= 0; 1.31 end 1.32 1.33 // the host side control 1.34 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.35 begin 1.36 if (rst_i == `TRUE) begin 1.37 - trig_type <= #1 0; 1.38 - trace_stop <= #1 0; 1.39 - trace_start <= #1 0; 1.40 - pc_low <= #1 0; 1.41 - pc_high <= #1 0; 1.42 - ack_o <= #1 0; 1.43 + trig_type <= 0; 1.44 + trace_stop <= 0; 1.45 + trace_start <= 0; 1.46 + pc_low <= 0; 1.47 + pc_high <= 0; 1.48 + ack_o <= 0; 1.49 end else begin 1.50 if (stb_i == `TRUE && ack_o == `FALSE) begin 1.51 if (rw_creg) begin // control register access 1.52 - ack_o <= #1 `TRUE; 1.53 + ack_o <= `TRUE; 1.54 if (we_i == `TRUE) begin 1.55 case ({adr_i[11:2],2'b0}) 1.56 // write to trig type 1.57 12'd0: 1.58 begin 1.59 if (sel_i[0]) begin 1.60 - trig_type[4:0] <= #1 dat_i[4:0]; 1.61 + trig_type[4:0] <= dat_i[4:0]; 1.62 end 1.63 if (sel_i[3]) begin 1.64 - trace_start <= #1 dat_i[31]; 1.65 - trace_stop <= #1 dat_i[30]; 1.66 + trace_start <= dat_i[31]; 1.67 + trace_stop <= dat_i[30]; 1.68 end 1.69 end 1.70 12'd8: 1.71 begin 1.72 - if (sel_i[3]) pc_low[31:24] <= #1 dat_i[31:24]; 1.73 - if (sel_i[2]) pc_low[23:16] <= #1 dat_i[23:16]; 1.74 - if (sel_i[1]) pc_low[15:8] <= #1 dat_i[15:8]; 1.75 - if (sel_i[0]) pc_low[7:0] <= #1 dat_i[7:0]; 1.76 + if (sel_i[3]) pc_low[31:24] <= dat_i[31:24]; 1.77 + if (sel_i[2]) pc_low[23:16] <= dat_i[23:16]; 1.78 + if (sel_i[1]) pc_low[15:8] <= dat_i[15:8]; 1.79 + if (sel_i[0]) pc_low[7:0] <= dat_i[7:0]; 1.80 end 1.81 12'd12: 1.82 begin 1.83 - if (sel_i[3]) pc_high[31:24] <= #1 dat_i[31:24]; 1.84 - if (sel_i[2]) pc_high[23:16] <= #1 dat_i[23:16]; 1.85 - if (sel_i[1]) pc_high[15:8] <= #1 dat_i[15:8]; 1.86 - if (sel_i[0]) pc_high[7:0] <= #1 dat_i[7:0]; 1.87 + if (sel_i[3]) pc_high[31:24] <= dat_i[31:24]; 1.88 + if (sel_i[2]) pc_high[23:16] <= dat_i[23:16]; 1.89 + if (sel_i[1]) pc_high[15:8] <= dat_i[15:8]; 1.90 + if (sel_i[0]) pc_high[7:0] <= dat_i[7:0]; 1.91 end 1.92 12'd16: 1.93 begin 1.94 if (sel_i[0])begin 1.95 - stop_type[4:0] <= #1 dat_i[4:0]; 1.96 + stop_type[4:0] <= dat_i[4:0]; 1.97 end 1.98 end 1.99 endcase 1.100 @@ -212,27 +212,27 @@ 1.101 case ({adr_i[11:2],2'b0}) 1.102 // read the trig type 1.103 12'd0: 1.104 - reg_dat_o <= #1 {22'b1,capturing,mem_valid,ovrflw,trace_we,started,trig_type}; 1.105 + reg_dat_o <= {22'b1,capturing,mem_valid,ovrflw,trace_we,started,trig_type}; 1.106 12'd4: 1.107 - reg_dat_o <= #1 trace_len; 1.108 + reg_dat_o <= trace_len; 1.109 12'd8: 1.110 - reg_dat_o <= #1 pc_low; 1.111 + reg_dat_o <= pc_low; 1.112 12'd12: 1.113 - reg_dat_o <= #1 pc_high; 1.114 + reg_dat_o <= pc_high; 1.115 default: 1.116 - reg_dat_o <= #1 {27'b0,stop_type}; 1.117 + reg_dat_o <= {27'b0,stop_type}; 1.118 endcase 1.119 end // else: !if(we_i == `TRUE) 1.120 end else // read / write memory 1.121 if (we_i == `FALSE) begin 1.122 - ack_o <= #1 `TRUE; 1.123 + ack_o <= `TRUE; 1.124 end else 1.125 - ack_o <= #1 `FALSE; 1.126 + ack_o <= `FALSE; 1.127 // not allowed to write to trace memory 1.128 end else begin // if (stb_i == `TRUE) 1.129 - trace_start <= #1 `FALSE; 1.130 - trace_stop <= #1 `FALSE; 1.131 - ack_o <= #1 `FALSE; 1.132 + trace_start <= `FALSE; 1.133 + trace_stop <= `FALSE; 1.134 + ack_o <= `FALSE; 1.135 end // else: !if(stb_i == `TRUE) 1.136 end // else: !if(rst_i == `TRUE) 1.137 end 1.138 @@ -268,31 +268,31 @@ 1.139 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.140 begin 1.141 if (rst_i == `TRUE) begin 1.142 - tstate <= #1 0; 1.143 - trace_we <= #1 0; 1.144 - trace_len <= #1 0; 1.145 - ovrflw <= #1 `FALSE; 1.146 - mem_valid <= #1 0; 1.147 - started <= #1 0; 1.148 - capturing <= #1 0; 1.149 + tstate <= 0; 1.150 + trace_we <= 0; 1.151 + trace_len <= 0; 1.152 + ovrflw <= `FALSE; 1.153 + mem_valid <= 0; 1.154 + started <= 0; 1.155 + capturing <= 0; 1.156 end else begin 1.157 case (tstate) 1.158 3'd0: 1.159 // start capture 1.160 if (trace_start) begin 1.161 - tstate <= #1 3'd1; 1.162 - mem_valid <= #1 0; 1.163 - started <= #1 1; 1.164 + tstate <= 3'd1; 1.165 + mem_valid <= 0; 1.166 + started <= 1; 1.167 end 1.168 3'd1: 1.169 begin 1.170 // wait for trigger 1.171 if (trace_begin) begin 1.172 - capturing <= #1 1; 1.173 - tstate <= #1 3'd2; 1.174 - trace_we <= #1 `TRUE; 1.175 - trace_len <= #1 0; 1.176 - ovrflw <= #1 `FALSE; 1.177 + capturing <= 1; 1.178 + tstate <= 3'd2; 1.179 + trace_we <= `TRUE; 1.180 + trace_len <= 0; 1.181 + ovrflw <= `FALSE; 1.182 end 1.183 end // case: 3'd1 1.184 1.185 @@ -300,18 +300,18 @@ 1.186 begin 1.187 if (trace_pc_valid) begin 1.188 if (trace_len[mem_addr_width]) 1.189 - trace_len <= #1 0; 1.190 + trace_len <= 0; 1.191 else 1.192 - trace_len <= #1 trace_len + 1; 1.193 + trace_len <= trace_len + 1; 1.194 end 1.195 - if (!ovrflw) ovrflw <= #1 trace_len[mem_addr_width]; 1.196 + if (!ovrflw) ovrflw <= trace_len[mem_addr_width]; 1.197 // wait for stop condition 1.198 if (trace_end) begin 1.199 - tstate <= #1 3'd0; 1.200 - trace_we <= #1 0; 1.201 - mem_valid <= #1 1; 1.202 - started <= #1 0; 1.203 - capturing <= #1 0; 1.204 + tstate <= 3'd0; 1.205 + trace_we <= 0; 1.206 + mem_valid <= 1; 1.207 + started <= 0; 1.208 + capturing <= 0; 1.209 end 1.210 end // case: 3'd2 1.211 endcase