1.1 diff -r 73de224304c1 -r d6c693415d59 lm32_trace.v 1.2 --- a/lm32_trace.v Sat Aug 06 00:02:46 2011 +0100 1.3 +++ b/lm32_trace.v Sat Aug 06 01:26:56 2011 +0100 1.4 @@ -146,65 +146,65 @@ 1.5 assign dat_o = (rw_creg ? reg_dat_o : trace_dat_o); 1.6 1.7 initial begin 1.8 - trig_type <= #1 0; 1.9 - stop_type <= #1 0; 1.10 - trace_len <= #1 0; 1.11 - pc_low <= #1 0; 1.12 - pc_high <= #1 0; 1.13 - trace_start <= #1 0; 1.14 - trace_stop <= #1 0; 1.15 - ack_o <= #1 0; 1.16 - reg_dat_o <= #1 0; 1.17 - mem_valid <= #1 0; 1.18 - started <= #1 0; 1.19 - capturing <= #1 0; 1.20 + trig_type <= 0; 1.21 + stop_type <= 0; 1.22 + trace_len <= 0; 1.23 + pc_low <= 0; 1.24 + pc_high <= 0; 1.25 + trace_start <= 0; 1.26 + trace_stop <= 0; 1.27 + ack_o <= 0; 1.28 + reg_dat_o <= 0; 1.29 + mem_valid <= 0; 1.30 + started <= 0; 1.31 + capturing <= 0; 1.32 end 1.33 1.34 // the host side control 1.35 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.36 begin 1.37 if (rst_i == `TRUE) begin 1.38 - trig_type <= #1 0; 1.39 - trace_stop <= #1 0; 1.40 - trace_start <= #1 0; 1.41 - pc_low <= #1 0; 1.42 - pc_high <= #1 0; 1.43 - ack_o <= #1 0; 1.44 + trig_type <= 0; 1.45 + trace_stop <= 0; 1.46 + trace_start <= 0; 1.47 + pc_low <= 0; 1.48 + pc_high <= 0; 1.49 + ack_o <= 0; 1.50 end else begin 1.51 if (stb_i == `TRUE && ack_o == `FALSE) begin 1.52 if (rw_creg) begin // control register access 1.53 - ack_o <= #1 `TRUE; 1.54 + ack_o <= `TRUE; 1.55 if (we_i == `TRUE) begin 1.56 case ({adr_i[11:2],2'b0}) 1.57 // write to trig type 1.58 12'd0: 1.59 begin 1.60 if (sel_i[0]) begin 1.61 - trig_type[4:0] <= #1 dat_i[4:0]; 1.62 + trig_type[4:0] <= dat_i[4:0]; 1.63 end 1.64 if (sel_i[3]) begin 1.65 - trace_start <= #1 dat_i[31]; 1.66 - trace_stop <= #1 dat_i[30]; 1.67 + trace_start <= dat_i[31]; 1.68 + trace_stop <= dat_i[30]; 1.69 end 1.70 end 1.71 12'd8: 1.72 begin 1.73 - if (sel_i[3]) pc_low[31:24] <= #1 dat_i[31:24]; 1.74 - if (sel_i[2]) pc_low[23:16] <= #1 dat_i[23:16]; 1.75 - if (sel_i[1]) pc_low[15:8] <= #1 dat_i[15:8]; 1.76 - if (sel_i[0]) pc_low[7:0] <= #1 dat_i[7:0]; 1.77 + if (sel_i[3]) pc_low[31:24] <= dat_i[31:24]; 1.78 + if (sel_i[2]) pc_low[23:16] <= dat_i[23:16]; 1.79 + if (sel_i[1]) pc_low[15:8] <= dat_i[15:8]; 1.80 + if (sel_i[0]) pc_low[7:0] <= dat_i[7:0]; 1.81 end 1.82 12'd12: 1.83 begin 1.84 - if (sel_i[3]) pc_high[31:24] <= #1 dat_i[31:24]; 1.85 - if (sel_i[2]) pc_high[23:16] <= #1 dat_i[23:16]; 1.86 - if (sel_i[1]) pc_high[15:8] <= #1 dat_i[15:8]; 1.87 - if (sel_i[0]) pc_high[7:0] <= #1 dat_i[7:0]; 1.88 + if (sel_i[3]) pc_high[31:24] <= dat_i[31:24]; 1.89 + if (sel_i[2]) pc_high[23:16] <= dat_i[23:16]; 1.90 + if (sel_i[1]) pc_high[15:8] <= dat_i[15:8]; 1.91 + if (sel_i[0]) pc_high[7:0] <= dat_i[7:0]; 1.92 end 1.93 12'd16: 1.94 begin 1.95 if (sel_i[0])begin 1.96 - stop_type[4:0] <= #1 dat_i[4:0]; 1.97 + stop_type[4:0] <= dat_i[4:0]; 1.98 end 1.99 end 1.100 endcase 1.101 @@ -212,27 +212,27 @@ 1.102 case ({adr_i[11:2],2'b0}) 1.103 // read the trig type 1.104 12'd0: 1.105 - reg_dat_o <= #1 {22'b1,capturing,mem_valid,ovrflw,trace_we,started,trig_type}; 1.106 + reg_dat_o <= {22'b1,capturing,mem_valid,ovrflw,trace_we,started,trig_type}; 1.107 12'd4: 1.108 - reg_dat_o <= #1 trace_len; 1.109 + reg_dat_o <= trace_len; 1.110 12'd8: 1.111 - reg_dat_o <= #1 pc_low; 1.112 + reg_dat_o <= pc_low; 1.113 12'd12: 1.114 - reg_dat_o <= #1 pc_high; 1.115 + reg_dat_o <= pc_high; 1.116 default: 1.117 - reg_dat_o <= #1 {27'b0,stop_type}; 1.118 + reg_dat_o <= {27'b0,stop_type}; 1.119 endcase 1.120 end // else: !if(we_i == `TRUE) 1.121 end else // read / write memory 1.122 if (we_i == `FALSE) begin 1.123 - ack_o <= #1 `TRUE; 1.124 + ack_o <= `TRUE; 1.125 end else 1.126 - ack_o <= #1 `FALSE; 1.127 + ack_o <= `FALSE; 1.128 // not allowed to write to trace memory 1.129 end else begin // if (stb_i == `TRUE) 1.130 - trace_start <= #1 `FALSE; 1.131 - trace_stop <= #1 `FALSE; 1.132 - ack_o <= #1 `FALSE; 1.133 + trace_start <= `FALSE; 1.134 + trace_stop <= `FALSE; 1.135 + ack_o <= `FALSE; 1.136 end // else: !if(stb_i == `TRUE) 1.137 end // else: !if(rst_i == `TRUE) 1.138 end 1.139 @@ -268,31 +268,31 @@ 1.140 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.141 begin 1.142 if (rst_i == `TRUE) begin 1.143 - tstate <= #1 0; 1.144 - trace_we <= #1 0; 1.145 - trace_len <= #1 0; 1.146 - ovrflw <= #1 `FALSE; 1.147 - mem_valid <= #1 0; 1.148 - started <= #1 0; 1.149 - capturing <= #1 0; 1.150 + tstate <= 0; 1.151 + trace_we <= 0; 1.152 + trace_len <= 0; 1.153 + ovrflw <= `FALSE; 1.154 + mem_valid <= 0; 1.155 + started <= 0; 1.156 + capturing <= 0; 1.157 end else begin 1.158 case (tstate) 1.159 3'd0: 1.160 // start capture 1.161 if (trace_start) begin 1.162 - tstate <= #1 3'd1; 1.163 - mem_valid <= #1 0; 1.164 - started <= #1 1; 1.165 + tstate <= 3'd1; 1.166 + mem_valid <= 0; 1.167 + started <= 1; 1.168 end 1.169 3'd1: 1.170 begin 1.171 // wait for trigger 1.172 if (trace_begin) begin 1.173 - capturing <= #1 1; 1.174 - tstate <= #1 3'd2; 1.175 - trace_we <= #1 `TRUE; 1.176 - trace_len <= #1 0; 1.177 - ovrflw <= #1 `FALSE; 1.178 + capturing <= 1; 1.179 + tstate <= 3'd2; 1.180 + trace_we <= `TRUE; 1.181 + trace_len <= 0; 1.182 + ovrflw <= `FALSE; 1.183 end 1.184 end // case: 3'd1 1.185 1.186 @@ -300,18 +300,18 @@ 1.187 begin 1.188 if (trace_pc_valid) begin 1.189 if (trace_len[mem_addr_width]) 1.190 - trace_len <= #1 0; 1.191 + trace_len <= 0; 1.192 else 1.193 - trace_len <= #1 trace_len + 1; 1.194 + trace_len <= trace_len + 1; 1.195 end 1.196 - if (!ovrflw) ovrflw <= #1 trace_len[mem_addr_width]; 1.197 + if (!ovrflw) ovrflw <= trace_len[mem_addr_width]; 1.198 // wait for stop condition 1.199 if (trace_end) begin 1.200 - tstate <= #1 3'd0; 1.201 - trace_we <= #1 0; 1.202 - mem_valid <= #1 1; 1.203 - started <= #1 0; 1.204 - capturing <= #1 0; 1.205 + tstate <= 3'd0; 1.206 + trace_we <= 0; 1.207 + mem_valid <= 1; 1.208 + started <= 0; 1.209 + capturing <= 0; 1.210 end 1.211 end // case: 3'd2 1.212 endcase