1.1 --- a/rtl/lm32_cpu.v Tue Mar 08 09:59:34 2011 +0000 1.2 +++ b/rtl/lm32_cpu.v Sat Aug 06 01:32:07 2011 +0100 1.3 @@ -1,24 +1,50 @@ 1.4 -// ============================================================================= 1.5 -// COPYRIGHT NOTICE 1.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation 1.7 -// ALL RIGHTS RESERVED 1.8 -// This confidential and proprietary software may be used only as authorised by 1.9 -// a licensing agreement from Lattice Semiconductor Corporation. 1.10 -// The entire notice above must be reproduced on all authorized copies and 1.11 -// copies may only be made to the extent permitted by a licensing agreement from 1.12 -// Lattice Semiconductor Corporation. 1.13 +// ================================================================== 1.14 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 1.15 +// ------------------------------------------------------------------ 1.16 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 1.17 +// ALL RIGHTS RESERVED 1.18 +// ------------------------------------------------------------------ 1.19 +// 1.20 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 1.21 +// 1.22 +// Permission: 1.23 +// 1.24 +// Lattice Semiconductor grants permission to use this code 1.25 +// pursuant to the terms of the Lattice Semiconductor Corporation 1.26 +// Open Source License Agreement. 1.27 +// 1.28 +// Disclaimer: 1.29 // 1.30 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 1.31 -// 5555 NE Moore Court 408-826-6000 (other locations) 1.32 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 1.33 -// U.S.A email: techsupport@latticesemi.com 1.34 -// =============================================================================/ 1.35 +// Lattice Semiconductor provides no warranty regarding the use or 1.36 +// functionality of this code. It is the user's responsibility to 1.37 +// verify the user’s design for consistency and functionality through 1.38 +// the use of formal verification methods. 1.39 +// 1.40 +// -------------------------------------------------------------------- 1.41 +// 1.42 +// Lattice Semiconductor Corporation 1.43 +// 5555 NE Moore Court 1.44 +// Hillsboro, OR 97214 1.45 +// U.S.A 1.46 +// 1.47 +// TEL: 1-800-Lattice (USA and Canada) 1.48 +// 503-286-8001 (other locations) 1.49 +// 1.50 +// web: http://www.latticesemi.com/ 1.51 +// email: techsupport@latticesemi.com 1.52 +// 1.53 +// -------------------------------------------------------------------- 1.54 // FILE DETAILS 1.55 // Project : LatticeMico32 1.56 // File : lm32_cpu.v 1.57 // Title : Top-level of CPU. 1.58 // Dependencies : lm32_include.v 1.59 // 1.60 +// Version 3.8 1.61 +// 1. Feature: Support for dynamically switching EBA to DEBA via a GPIO. 1.62 +// 2. Bug: EA now reports instruction that caused the data abort, rather than 1.63 +// next instruction. 1.64 +// 1.65 // Version 3.4 1.66 // 1. Bug Fix: In a tight infinite loop (add, sw, bi) incoming interrupts were 1.67 // never serviced. 1.68 @@ -75,6 +101,11 @@ 1.69 clk_n_i, 1.70 `endif 1.71 rst_i, 1.72 +`ifdef CFG_DEBUG_ENABLED 1.73 + `ifdef CFG_ALTERNATE_EBA 1.74 + at_debug, 1.75 + `endif 1.76 +`endif 1.77 // From external devices 1.78 `ifdef CFG_INTERRUPTS_ENABLED 1.79 interrupt, 1.80 @@ -212,6 +243,12 @@ 1.81 `endif 1.82 input rst_i; // Reset 1.83 1.84 +`ifdef CFG_DEBUG_ENABLED 1.85 + `ifdef CFG_ALTERNATE_EBA 1.86 + input at_debug; // GPIO input that maps EBA to DEBA 1.87 + `endif 1.88 +`endif 1.89 + 1.90 `ifdef CFG_INTERRUPTS_ENABLED 1.91 input [`LM32_INTERRUPT_RNG] interrupt; // Interrupt pins 1.92 `endif 1.93 @@ -751,6 +788,11 @@ 1.94 // ----- Inputs ------- 1.95 .clk_i (clk_i), 1.96 .rst_i (rst_i), 1.97 +`ifdef CFG_DEBUG_ENABLED 1.98 + `ifdef CFG_ALTERNATE_EBA 1.99 + .at_debug (at_debug), 1.100 + `endif 1.101 +`endif 1.102 // From pipeline 1.103 .stall_a (stall_a), 1.104 .stall_f (stall_f), 1.105 @@ -2476,6 +2518,9 @@ 1.106 `ifdef CFG_DEBUG_ENABLED 1.107 if (exception_x == `TRUE) 1.108 if ((dc_re == `TRUE) 1.109 + `ifdef CFG_ALTERNATE_EBA 1.110 + || (at_debug == `TRUE) 1.111 + `endif 1.112 || ((debug_exception_x == `TRUE) 1.113 && (non_debug_exception_x == `FALSE))) 1.114 branch_target_m <= {deba, eid_x, {3{1'b0}}}; 1.115 @@ -2546,6 +2591,7 @@ 1.116 `endif 1.117 `ifdef CFG_BUS_ERRORS_ENABLED 1.118 if ( (stall_m == `FALSE) 1.119 + && (data_bus_error_exception == `FALSE) 1.120 && ( (load_q_m == `TRUE) 1.121 || (store_q_m == `TRUE) 1.122 )