rtl/lm32_cpu.v

changeset 28
da23ab8ef7b4
parent 27
d6c693415d59
parent 24
c336e674a37e
     1.1 diff -r 7422134cbfea -r da23ab8ef7b4 rtl/lm32_cpu.v
     1.2 --- a/rtl/lm32_cpu.v	Tue Mar 08 09:59:34 2011 +0000
     1.3 +++ b/rtl/lm32_cpu.v	Sat Aug 06 01:32:07 2011 +0100
     1.4 @@ -1,24 +1,50 @@
     1.5 -// =============================================================================
     1.6 -//                           COPYRIGHT NOTICE
     1.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation
     1.8 -// ALL RIGHTS RESERVED
     1.9 -// This confidential and proprietary software may be used only as authorised by
    1.10 -// a licensing agreement from Lattice Semiconductor Corporation.
    1.11 -// The entire notice above must be reproduced on all authorized copies and
    1.12 -// copies may only be made to the extent permitted by a licensing agreement from
    1.13 -// Lattice Semiconductor Corporation.
    1.14 +//   ==================================================================
    1.15 +//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
    1.16 +//   ------------------------------------------------------------------
    1.17 +//   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
    1.18 +//   ALL RIGHTS RESERVED 
    1.19 +//   ------------------------------------------------------------------
    1.20 +//
    1.21 +//   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
    1.22 +//
    1.23 +//   Permission:
    1.24 +//
    1.25 +//      Lattice Semiconductor grants permission to use this code
    1.26 +//      pursuant to the terms of the Lattice Semiconductor Corporation
    1.27 +//      Open Source License Agreement.  
    1.28 +//
    1.29 +//   Disclaimer:
    1.30  //
    1.31 -// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
    1.32 -// 5555 NE Moore Court                            408-826-6000 (other locations)
    1.33 -// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
    1.34 -// U.S.A                                   email: techsupport@latticesemi.com
    1.35 -// =============================================================================/
    1.36 +//      Lattice Semiconductor provides no warranty regarding the use or
    1.37 +//      functionality of this code. It is the user's responsibility to
    1.38 +//      verify the user’s design for consistency and functionality through
    1.39 +//      the use of formal verification methods.
    1.40 +//
    1.41 +//   --------------------------------------------------------------------
    1.42 +//
    1.43 +//                  Lattice Semiconductor Corporation
    1.44 +//                  5555 NE Moore Court
    1.45 +//                  Hillsboro, OR 97214
    1.46 +//                  U.S.A
    1.47 +//
    1.48 +//                  TEL: 1-800-Lattice (USA and Canada)
    1.49 +//                         503-286-8001 (other locations)
    1.50 +//
    1.51 +//                  web: http://www.latticesemi.com/
    1.52 +//                  email: techsupport@latticesemi.com
    1.53 +//
    1.54 +//   --------------------------------------------------------------------
    1.55  //                         FILE DETAILS
    1.56  // Project          : LatticeMico32
    1.57  // File             : lm32_cpu.v
    1.58  // Title            : Top-level of CPU.
    1.59  // Dependencies     : lm32_include.v
    1.60  //
    1.61 +// Version 3.8
    1.62 +// 1. Feature: Support for dynamically switching EBA to DEBA via a GPIO.
    1.63 +// 2. Bug: EA now reports instruction that caused the data abort, rather than
    1.64 +//    next instruction.
    1.65 +//
    1.66  // Version 3.4
    1.67  // 1. Bug Fix: In a tight infinite loop (add, sw, bi) incoming interrupts were 
    1.68  //    never serviced.
    1.69 @@ -75,6 +101,11 @@
    1.70      clk_n_i,
    1.71  `endif    
    1.72      rst_i,
    1.73 +`ifdef CFG_DEBUG_ENABLED
    1.74 + `ifdef CFG_ALTERNATE_EBA
    1.75 +    at_debug,
    1.76 + `endif
    1.77 +`endif
    1.78      // From external devices
    1.79  `ifdef CFG_INTERRUPTS_ENABLED
    1.80      interrupt,
    1.81 @@ -212,6 +243,12 @@
    1.82  `endif    
    1.83  input rst_i;                                    // Reset
    1.84  
    1.85 +`ifdef CFG_DEBUG_ENABLED
    1.86 + `ifdef CFG_ALTERNATE_EBA
    1.87 +   input at_debug;                              // GPIO input that maps EBA to DEBA
    1.88 + `endif
    1.89 +`endif
    1.90 +
    1.91  `ifdef CFG_INTERRUPTS_ENABLED
    1.92  input [`LM32_INTERRUPT_RNG] interrupt;          // Interrupt pins
    1.93  `endif
    1.94 @@ -751,6 +788,11 @@
    1.95      // ----- Inputs -------
    1.96      .clk_i                  (clk_i),
    1.97      .rst_i                  (rst_i),
    1.98 +`ifdef CFG_DEBUG_ENABLED
    1.99 + `ifdef CFG_ALTERNATE_EBA
   1.100 +    .at_debug               (at_debug),
   1.101 + `endif
   1.102 +`endif
   1.103      // From pipeline
   1.104      .stall_a                (stall_a),
   1.105      .stall_f                (stall_f),
   1.106 @@ -2476,6 +2518,9 @@
   1.107  `ifdef CFG_DEBUG_ENABLED
   1.108  	   if (exception_x == `TRUE)
   1.109  	     if ((dc_re == `TRUE)
   1.110 + `ifdef CFG_ALTERNATE_EBA
   1.111 +		 || (at_debug == `TRUE)
   1.112 + `endif
   1.113  		 || ((debug_exception_x == `TRUE) 
   1.114  		     && (non_debug_exception_x == `FALSE)))
   1.115  	       branch_target_m <= {deba, eid_x, {3{1'b0}}};
   1.116 @@ -2546,6 +2591,7 @@
   1.117  `endif
   1.118  `ifdef CFG_BUS_ERRORS_ENABLED
   1.119          if (   (stall_m == `FALSE)
   1.120 +	    && (data_bus_error_exception == `FALSE)
   1.121              && (   (load_q_m == `TRUE) 
   1.122                  || (store_q_m == `TRUE)
   1.123                 )