1.1 --- a/rtl/lm32_instruction_unit.v Tue Mar 08 09:59:34 2011 +0000 1.2 +++ b/rtl/lm32_instruction_unit.v Sat Aug 06 01:32:07 2011 +0100 1.3 @@ -1,18 +1,39 @@ 1.4 -// ============================================================================= 1.5 -// COPYRIGHT NOTICE 1.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation 1.7 -// ALL RIGHTS RESERVED 1.8 -// This confidential and proprietary software may be used only as authorised by 1.9 -// a licensing agreement from Lattice Semiconductor Corporation. 1.10 -// The entire notice above must be reproduced on all authorized copies and 1.11 -// copies may only be made to the extent permitted by a licensing agreement from 1.12 -// Lattice Semiconductor Corporation. 1.13 +// ================================================================== 1.14 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 1.15 +// ------------------------------------------------------------------ 1.16 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 1.17 +// ALL RIGHTS RESERVED 1.18 +// ------------------------------------------------------------------ 1.19 +// 1.20 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 1.21 +// 1.22 +// Permission: 1.23 +// 1.24 +// Lattice Semiconductor grants permission to use this code 1.25 +// pursuant to the terms of the Lattice Semiconductor Corporation 1.26 +// Open Source License Agreement. 1.27 +// 1.28 +// Disclaimer: 1.29 // 1.30 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 1.31 -// 5555 NE Moore Court 408-826-6000 (other locations) 1.32 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 1.33 -// U.S.A email: techsupport@latticesemi.com 1.34 -// =============================================================================/ 1.35 +// Lattice Semiconductor provides no warranty regarding the use or 1.36 +// functionality of this code. It is the user's responsibility to 1.37 +// verify the user’s design for consistency and functionality through 1.38 +// the use of formal verification methods. 1.39 +// 1.40 +// -------------------------------------------------------------------- 1.41 +// 1.42 +// Lattice Semiconductor Corporation 1.43 +// 5555 NE Moore Court 1.44 +// Hillsboro, OR 97214 1.45 +// U.S.A 1.46 +// 1.47 +// TEL: 1-800-Lattice (USA and Canada) 1.48 +// 503-286-8001 (other locations) 1.49 +// 1.50 +// web: http://www.latticesemi.com/ 1.51 +// email: techsupport@latticesemi.com 1.52 +// 1.53 +// -------------------------------------------------------------------- 1.54 // FILE DETAILS 1.55 // Project : LatticeMico32 1.56 // File : lm32_instruction_unit.v 1.57 @@ -42,6 +63,9 @@ 1.58 // : instruction cache) to lock up in to an infinite loop due to a 1.59 // : instruction bus error when EBA was set to instruction inline 1.60 // : memory. 1.61 +// Version : 3.8 1.62 +// : Feature: Support for dynamically switching EBA to DEBA via a 1.63 +// : GPIO. 1.64 // ============================================================================= 1.65 1.66 `include "lm32_include.v" 1.67 @@ -54,6 +78,11 @@ 1.68 // ----- Inputs ------- 1.69 clk_i, 1.70 rst_i, 1.71 +`ifdef CFG_DEBUG_ENABLED 1.72 + `ifdef CFG_ALTERNATE_EBA 1.73 + at_debug, 1.74 + `endif 1.75 +`endif 1.76 // From pipeline 1.77 stall_a, 1.78 stall_f, 1.79 @@ -161,6 +190,12 @@ 1.80 input clk_i; // Clock 1.81 input rst_i; // Reset 1.82 1.83 +`ifdef CFG_DEBUG_ENABLED 1.84 + `ifdef CFG_ALTERNATE_EBA 1.85 + input at_debug; // GPIO input that maps EBA to DEBA 1.86 + `endif 1.87 +`endif 1.88 + 1.89 input stall_a; // Stall A stage instruction 1.90 input stall_f; // Stall F stage instruction 1.91 input stall_d; // Stall D stage instruction 1.92 @@ -334,6 +369,10 @@ 1.93 reg jtag_access; // Indicates if a JTAG WB access is in progress 1.94 `endif 1.95 1.96 +`ifdef CFG_ALTERNATE_EBA 1.97 + reg alternate_eba_taken; 1.98 +`endif 1.99 + 1.100 ///////////////////////////////////////////////////// 1.101 // Functions 1.102 ///////////////////////////////////////////////////// 1.103 @@ -381,8 +420,8 @@ 1.104 .ResetB (rst_i), 1.105 .DataInA ({32{1'b0}}), 1.106 .DataInB (irom_store_data_m), 1.107 - .AddressA (pc_a[(clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)+2-1:2]), 1.108 - .AddressB (irom_address_xm[(clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)+2-1:2]), 1.109 + .AddressA (pc_a[clogb2_v1(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)+2-1:2]), 1.110 + .AddressB (irom_address_xm[clogb2_v1(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)+2-1:2]), 1.111 .ClockEnA (!stall_a), 1.112 .ClockEnB (!stall_x || !stall_m), 1.113 .WrA (`FALSE), 1.114 @@ -469,7 +508,7 @@ 1.115 pc_a = restart_address; 1.116 else 1.117 `endif 1.118 - pc_a = pc_f + 1'b1; 1.119 + pc_a = pc_f + 1'b1; 1.120 end 1.121 1.122 // Select where instruction should be fetched from 1.123 @@ -542,28 +581,39 @@ 1.124 1.125 // PC 1.126 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.127 -begin 1.128 - if (rst_i == `TRUE) 1.129 - begin 1.130 - pc_f <= (`CFG_EBA_RESET-4)/4; 1.131 - pc_d <= {`LM32_PC_WIDTH{1'b0}}; 1.132 - pc_x <= {`LM32_PC_WIDTH{1'b0}}; 1.133 - pc_m <= {`LM32_PC_WIDTH{1'b0}}; 1.134 - pc_w <= {`LM32_PC_WIDTH{1'b0}}; 1.135 - end 1.136 - else 1.137 - begin 1.138 - if (stall_f == `FALSE) 1.139 + begin 1.140 + if (rst_i == `TRUE) 1.141 + begin 1.142 +`ifdef CFG_DEBUG_ENABLED 1.143 + `ifdef CFG_ALTERNATE_EBA 1.144 + if (at_debug == `TRUE) 1.145 + pc_f <= (`CFG_DEBA_RESET-4)/4; 1.146 + else 1.147 + pc_f <= (`CFG_EBA_RESET-4)/4; 1.148 + `else 1.149 + pc_f <= (`CFG_EBA_RESET-4)/4; 1.150 + `endif 1.151 +`else 1.152 + pc_f <= (`CFG_EBA_RESET-4)/4; 1.153 +`endif 1.154 + pc_d <= {`LM32_PC_WIDTH{1'b0}}; 1.155 + pc_x <= {`LM32_PC_WIDTH{1'b0}}; 1.156 + pc_m <= {`LM32_PC_WIDTH{1'b0}}; 1.157 + pc_w <= {`LM32_PC_WIDTH{1'b0}}; 1.158 + end 1.159 + else 1.160 + begin 1.161 + if (stall_f == `FALSE) 1.162 pc_f <= pc_a; 1.163 - if (stall_d == `FALSE) 1.164 + if (stall_d == `FALSE) 1.165 pc_d <= pc_f; 1.166 - if (stall_x == `FALSE) 1.167 + if (stall_x == `FALSE) 1.168 pc_x <= pc_d; 1.169 - if (stall_m == `FALSE) 1.170 + if (stall_m == `FALSE) 1.171 pc_m <= pc_x; 1.172 - pc_w <= pc_m; 1.173 - end 1.174 -end 1.175 + pc_w <= pc_m; 1.176 + end 1.177 + end 1.178 1.179 `ifdef LM32_CACHE_ENABLED 1.180 // Address to restart from after a cache miss has been handled